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i40e/i40evf: enable prefetch of Tx descriptors during cleanup
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_txrx.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
29 #include "i40e.h"
30 #include "i40e_prototype.h"
31
32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34 {
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40 }
41
42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
43 #define I40E_FD_CLEAN_DELAY 10
44 /**
45 * i40e_program_fdir_filter - Program a Flow Director filter
46 * @fdir_data: Packet data that will be filter parameters
47 * @raw_packet: the pre-allocated packet buffer for FDir
48 * @pf: The pf pointer
49 * @add: True for add/update, False for remove
50 **/
51 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
52 struct i40e_pf *pf, bool add)
53 {
54 struct i40e_filter_program_desc *fdir_desc;
55 struct i40e_tx_buffer *tx_buf, *first;
56 struct i40e_tx_desc *tx_desc;
57 struct i40e_ring *tx_ring;
58 unsigned int fpt, dcc;
59 struct i40e_vsi *vsi;
60 struct device *dev;
61 dma_addr_t dma;
62 u32 td_cmd = 0;
63 u16 delay = 0;
64 u16 i;
65
66 /* find existing FDIR VSI */
67 vsi = NULL;
68 for (i = 0; i < pf->num_alloc_vsi; i++)
69 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
70 vsi = pf->vsi[i];
71 if (!vsi)
72 return -ENOENT;
73
74 tx_ring = vsi->tx_rings[0];
75 dev = tx_ring->dev;
76
77 /* we need two descriptors to add/del a filter and we can wait */
78 do {
79 if (I40E_DESC_UNUSED(tx_ring) > 1)
80 break;
81 msleep_interruptible(1);
82 delay++;
83 } while (delay < I40E_FD_CLEAN_DELAY);
84
85 if (!(I40E_DESC_UNUSED(tx_ring) > 1))
86 return -EAGAIN;
87
88 dma = dma_map_single(dev, raw_packet,
89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
90 if (dma_mapping_error(dev, dma))
91 goto dma_fail;
92
93 /* grab the next descriptor */
94 i = tx_ring->next_to_use;
95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
96 first = &tx_ring->tx_bi[i];
97 memset(first, 0, sizeof(struct i40e_tx_buffer));
98
99 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
100
101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
102 I40E_TXD_FLTR_QW0_QINDEX_MASK;
103
104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
106
107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
108 I40E_TXD_FLTR_QW0_PCTYPE_MASK;
109
110 /* Use LAN VSI Id if not programmed by user */
111 if (fdir_data->dest_vsi == 0)
112 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
114 else
115 fpt |= ((u32)fdir_data->dest_vsi <<
116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
118
119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
120
121 if (add)
122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
123 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
124 else
125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
126 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
127
128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
129 I40E_TXD_FLTR_QW1_DEST_MASK;
130
131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
133
134 if (fdir_data->cnt_index != 0) {
135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
136 dcc |= ((u32)fdir_data->cnt_index <<
137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
139 }
140
141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
142 fdir_desc->rsvd = cpu_to_le32(0);
143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
145
146 /* Now program a dummy descriptor */
147 i = tx_ring->next_to_use;
148 tx_desc = I40E_TX_DESC(tx_ring, i);
149 tx_buf = &tx_ring->tx_bi[i];
150
151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
152
153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
154
155 /* record length, and DMA address */
156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
157 dma_unmap_addr_set(tx_buf, dma, dma);
158
159 tx_desc->buffer_addr = cpu_to_le64(dma);
160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
161
162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
163 tx_buf->raw_buf = (void *)raw_packet;
164
165 tx_desc->cmd_type_offset_bsz =
166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
167
168 /* set the timestamp */
169 tx_buf->time_stamp = jiffies;
170
171 /* Force memory writes to complete before letting h/w
172 * know there are new descriptors to fetch.
173 */
174 wmb();
175
176 /* Mark the data descriptor to be watched */
177 first->next_to_watch = tx_desc;
178
179 writel(tx_ring->next_to_use, tx_ring->tail);
180 return 0;
181
182 dma_fail:
183 return -1;
184 }
185
186 #define IP_HEADER_OFFSET 14
187 #define I40E_UDPIP_DUMMY_PACKET_LEN 42
188 /**
189 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
190 * @vsi: pointer to the targeted VSI
191 * @fd_data: the flow director data required for the FDir descriptor
192 * @add: true adds a filter, false removes it
193 *
194 * Returns 0 if the filters were successfully added or removed
195 **/
196 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
197 struct i40e_fdir_filter *fd_data,
198 bool add)
199 {
200 struct i40e_pf *pf = vsi->back;
201 struct udphdr *udp;
202 struct iphdr *ip;
203 bool err = false;
204 u8 *raw_packet;
205 int ret;
206 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
207 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
209
210 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
211 if (!raw_packet)
212 return -ENOMEM;
213 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
214
215 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
216 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
217 + sizeof(struct iphdr));
218
219 ip->daddr = fd_data->dst_ip[0];
220 udp->dest = fd_data->dst_port;
221 ip->saddr = fd_data->src_ip[0];
222 udp->source = fd_data->src_port;
223
224 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
225 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
226 if (ret) {
227 dev_info(&pf->pdev->dev,
228 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
229 fd_data->pctype, fd_data->fd_id, ret);
230 err = true;
231 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
232 if (add)
233 dev_info(&pf->pdev->dev,
234 "Filter OK for PCTYPE %d loc = %d\n",
235 fd_data->pctype, fd_data->fd_id);
236 else
237 dev_info(&pf->pdev->dev,
238 "Filter deleted for PCTYPE %d loc = %d\n",
239 fd_data->pctype, fd_data->fd_id);
240 }
241 return err ? -EOPNOTSUPP : 0;
242 }
243
244 #define I40E_TCPIP_DUMMY_PACKET_LEN 54
245 /**
246 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
247 * @vsi: pointer to the targeted VSI
248 * @fd_data: the flow director data required for the FDir descriptor
249 * @add: true adds a filter, false removes it
250 *
251 * Returns 0 if the filters were successfully added or removed
252 **/
253 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
254 struct i40e_fdir_filter *fd_data,
255 bool add)
256 {
257 struct i40e_pf *pf = vsi->back;
258 struct tcphdr *tcp;
259 struct iphdr *ip;
260 bool err = false;
261 u8 *raw_packet;
262 int ret;
263 /* Dummy packet */
264 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
265 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
267 0x0, 0x72, 0, 0, 0, 0};
268
269 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
270 if (!raw_packet)
271 return -ENOMEM;
272 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
273
274 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
275 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
276 + sizeof(struct iphdr));
277
278 ip->daddr = fd_data->dst_ip[0];
279 tcp->dest = fd_data->dst_port;
280 ip->saddr = fd_data->src_ip[0];
281 tcp->source = fd_data->src_port;
282
283 if (add) {
284 pf->fd_tcp_rule++;
285 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
286 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
287 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
288 }
289 } else {
290 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
291 (pf->fd_tcp_rule - 1) : 0;
292 if (pf->fd_tcp_rule == 0) {
293 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
294 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
295 }
296 }
297
298 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
299 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
300
301 if (ret) {
302 dev_info(&pf->pdev->dev,
303 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
304 fd_data->pctype, fd_data->fd_id, ret);
305 err = true;
306 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
307 if (add)
308 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
309 fd_data->pctype, fd_data->fd_id);
310 else
311 dev_info(&pf->pdev->dev,
312 "Filter deleted for PCTYPE %d loc = %d\n",
313 fd_data->pctype, fd_data->fd_id);
314 }
315
316 return err ? -EOPNOTSUPP : 0;
317 }
318
319 /**
320 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
321 * a specific flow spec
322 * @vsi: pointer to the targeted VSI
323 * @fd_data: the flow director data required for the FDir descriptor
324 * @add: true adds a filter, false removes it
325 *
326 * Always returns -EOPNOTSUPP
327 **/
328 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
329 struct i40e_fdir_filter *fd_data,
330 bool add)
331 {
332 return -EOPNOTSUPP;
333 }
334
335 #define I40E_IP_DUMMY_PACKET_LEN 34
336 /**
337 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
338 * a specific flow spec
339 * @vsi: pointer to the targeted VSI
340 * @fd_data: the flow director data required for the FDir descriptor
341 * @add: true adds a filter, false removes it
342 *
343 * Returns 0 if the filters were successfully added or removed
344 **/
345 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
346 struct i40e_fdir_filter *fd_data,
347 bool add)
348 {
349 struct i40e_pf *pf = vsi->back;
350 struct iphdr *ip;
351 bool err = false;
352 u8 *raw_packet;
353 int ret;
354 int i;
355 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
356 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
357 0, 0, 0, 0};
358
359 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
360 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
361 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
362 if (!raw_packet)
363 return -ENOMEM;
364 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
365 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
366
367 ip->saddr = fd_data->src_ip[0];
368 ip->daddr = fd_data->dst_ip[0];
369 ip->protocol = 0;
370
371 fd_data->pctype = i;
372 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
373
374 if (ret) {
375 dev_info(&pf->pdev->dev,
376 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
377 fd_data->pctype, fd_data->fd_id, ret);
378 err = true;
379 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
380 if (add)
381 dev_info(&pf->pdev->dev,
382 "Filter OK for PCTYPE %d loc = %d\n",
383 fd_data->pctype, fd_data->fd_id);
384 else
385 dev_info(&pf->pdev->dev,
386 "Filter deleted for PCTYPE %d loc = %d\n",
387 fd_data->pctype, fd_data->fd_id);
388 }
389 }
390
391 return err ? -EOPNOTSUPP : 0;
392 }
393
394 /**
395 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
396 * @vsi: pointer to the targeted VSI
397 * @cmd: command to get or set RX flow classification rules
398 * @add: true adds a filter, false removes it
399 *
400 **/
401 int i40e_add_del_fdir(struct i40e_vsi *vsi,
402 struct i40e_fdir_filter *input, bool add)
403 {
404 struct i40e_pf *pf = vsi->back;
405 int ret;
406
407 switch (input->flow_type & ~FLOW_EXT) {
408 case TCP_V4_FLOW:
409 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
410 break;
411 case UDP_V4_FLOW:
412 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
413 break;
414 case SCTP_V4_FLOW:
415 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
416 break;
417 case IPV4_FLOW:
418 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
419 break;
420 case IP_USER_FLOW:
421 switch (input->ip4_proto) {
422 case IPPROTO_TCP:
423 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
424 break;
425 case IPPROTO_UDP:
426 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
427 break;
428 case IPPROTO_SCTP:
429 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
430 break;
431 default:
432 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
433 break;
434 }
435 break;
436 default:
437 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
438 input->flow_type);
439 ret = -EINVAL;
440 }
441
442 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
443 return ret;
444 }
445
446 /**
447 * i40e_fd_handle_status - check the Programming Status for FD
448 * @rx_ring: the Rx ring for this descriptor
449 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
450 * @prog_id: the id originally used for programming
451 *
452 * This is used to verify if the FD programming or invalidation
453 * requested by SW to the HW is successful or not and take actions accordingly.
454 **/
455 static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
456 union i40e_rx_desc *rx_desc, u8 prog_id)
457 {
458 struct i40e_pf *pf = rx_ring->vsi->back;
459 struct pci_dev *pdev = pf->pdev;
460 u32 fcnt_prog, fcnt_avail;
461 u32 error;
462 u64 qw;
463
464 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
465 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
466 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
467
468 if (error == (0x1 << I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
469 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
470 (I40E_DEBUG_FD & pf->hw.debug_mask))
471 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
472 rx_desc->wb.qword0.hi_dword.fd_id);
473
474 /* Check if the programming error is for ATR.
475 * If so, auto disable ATR and set a state for
476 * flush in progress. Next time we come here if flush is in
477 * progress do nothing, once flush is complete the state will
478 * be cleared.
479 */
480 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
481 return;
482
483 pf->fd_add_err++;
484 /* store the current atr filter count */
485 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
486
487 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
488 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
489 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
490 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
491 }
492
493 /* filter programming failed most likely due to table full */
494 fcnt_prog = i40e_get_global_fd_count(pf);
495 fcnt_avail = pf->fdir_pf_filter_count;
496 /* If ATR is running fcnt_prog can quickly change,
497 * if we are very close to full, it makes sense to disable
498 * FD ATR/SB and then re-enable it when there is room.
499 */
500 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
501 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
502 !(pf->auto_disable_flags &
503 I40E_FLAG_FD_SB_ENABLED)) {
504 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
505 pf->auto_disable_flags |=
506 I40E_FLAG_FD_SB_ENABLED;
507 }
508 } else {
509 dev_info(&pdev->dev,
510 "FD filter programming failed due to incorrect filter parameters\n");
511 }
512 } else if (error ==
513 (0x1 << I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
514 if (I40E_DEBUG_FD & pf->hw.debug_mask)
515 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
516 rx_desc->wb.qword0.hi_dword.fd_id);
517 }
518 }
519
520 /**
521 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
522 * @ring: the ring that owns the buffer
523 * @tx_buffer: the buffer to free
524 **/
525 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
526 struct i40e_tx_buffer *tx_buffer)
527 {
528 if (tx_buffer->skb) {
529 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
530 kfree(tx_buffer->raw_buf);
531 else
532 dev_kfree_skb_any(tx_buffer->skb);
533
534 if (dma_unmap_len(tx_buffer, len))
535 dma_unmap_single(ring->dev,
536 dma_unmap_addr(tx_buffer, dma),
537 dma_unmap_len(tx_buffer, len),
538 DMA_TO_DEVICE);
539 } else if (dma_unmap_len(tx_buffer, len)) {
540 dma_unmap_page(ring->dev,
541 dma_unmap_addr(tx_buffer, dma),
542 dma_unmap_len(tx_buffer, len),
543 DMA_TO_DEVICE);
544 }
545 tx_buffer->next_to_watch = NULL;
546 tx_buffer->skb = NULL;
547 dma_unmap_len_set(tx_buffer, len, 0);
548 /* tx_buffer must be completely set up in the transmit path */
549 }
550
551 /**
552 * i40e_clean_tx_ring - Free any empty Tx buffers
553 * @tx_ring: ring to be cleaned
554 **/
555 void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
556 {
557 unsigned long bi_size;
558 u16 i;
559
560 /* ring already cleared, nothing to do */
561 if (!tx_ring->tx_bi)
562 return;
563
564 /* Free all the Tx ring sk_buffs */
565 for (i = 0; i < tx_ring->count; i++)
566 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
567
568 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
569 memset(tx_ring->tx_bi, 0, bi_size);
570
571 /* Zero out the descriptor ring */
572 memset(tx_ring->desc, 0, tx_ring->size);
573
574 tx_ring->next_to_use = 0;
575 tx_ring->next_to_clean = 0;
576
577 if (!tx_ring->netdev)
578 return;
579
580 /* cleanup Tx queue statistics */
581 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
582 tx_ring->queue_index));
583 }
584
585 /**
586 * i40e_free_tx_resources - Free Tx resources per queue
587 * @tx_ring: Tx descriptor ring for a specific queue
588 *
589 * Free all transmit software resources
590 **/
591 void i40e_free_tx_resources(struct i40e_ring *tx_ring)
592 {
593 i40e_clean_tx_ring(tx_ring);
594 kfree(tx_ring->tx_bi);
595 tx_ring->tx_bi = NULL;
596
597 if (tx_ring->desc) {
598 dma_free_coherent(tx_ring->dev, tx_ring->size,
599 tx_ring->desc, tx_ring->dma);
600 tx_ring->desc = NULL;
601 }
602 }
603
604 /**
605 * i40e_get_head - Retrieve head from head writeback
606 * @tx_ring: tx ring to fetch head of
607 *
608 * Returns value of Tx ring head based on value stored
609 * in head write-back location
610 **/
611 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
612 {
613 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
614
615 return le32_to_cpu(*(volatile __le32 *)head);
616 }
617
618 /**
619 * i40e_get_tx_pending - how many tx descriptors not processed
620 * @tx_ring: the ring of descriptors
621 *
622 * Since there is no access to the ring head register
623 * in XL710, we need to use our local copies
624 **/
625 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
626 {
627 u32 head, tail;
628
629 head = i40e_get_head(ring);
630 tail = readl(ring->tail);
631
632 if (head != tail)
633 return (head < tail) ?
634 tail - head : (tail + ring->count - head);
635
636 return 0;
637 }
638
639 /**
640 * i40e_check_tx_hang - Is there a hang in the Tx queue
641 * @tx_ring: the ring of descriptors
642 **/
643 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
644 {
645 u32 tx_done = tx_ring->stats.packets;
646 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
647 u32 tx_pending = i40e_get_tx_pending(tx_ring);
648 struct i40e_pf *pf = tx_ring->vsi->back;
649 bool ret = false;
650
651 clear_check_for_tx_hang(tx_ring);
652
653 /* Check for a hung queue, but be thorough. This verifies
654 * that a transmit has been completed since the previous
655 * check AND there is at least one packet pending. The
656 * ARMED bit is set to indicate a potential hang. The
657 * bit is cleared if a pause frame is received to remove
658 * false hang detection due to PFC or 802.3x frames. By
659 * requiring this to fail twice we avoid races with
660 * PFC clearing the ARMED bit and conditions where we
661 * run the check_tx_hang logic with a transmit completion
662 * pending but without time to complete it yet.
663 */
664 if ((tx_done_old == tx_done) && tx_pending) {
665 /* make sure it is true for two checks in a row */
666 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
667 &tx_ring->state);
668 } else if (tx_done_old == tx_done &&
669 (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) {
670 if (I40E_DEBUG_FLOW & pf->hw.debug_mask)
671 dev_info(tx_ring->dev, "HW needs some more descs to do a cacheline flush. tx_pending %d, queue %d",
672 tx_pending, tx_ring->queue_index);
673 pf->tx_sluggish_count++;
674 } else {
675 /* update completed stats and disarm the hang check */
676 tx_ring->tx_stats.tx_done_old = tx_done;
677 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
678 }
679
680 return ret;
681 }
682
683 #define WB_STRIDE 0x3
684
685 /**
686 * i40e_clean_tx_irq - Reclaim resources after transmit completes
687 * @tx_ring: tx ring to clean
688 * @budget: how many cleans we're allowed
689 *
690 * Returns true if there's any budget left (e.g. the clean is finished)
691 **/
692 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
693 {
694 u16 i = tx_ring->next_to_clean;
695 struct i40e_tx_buffer *tx_buf;
696 struct i40e_tx_desc *tx_head;
697 struct i40e_tx_desc *tx_desc;
698 unsigned int total_packets = 0;
699 unsigned int total_bytes = 0;
700
701 tx_buf = &tx_ring->tx_bi[i];
702 tx_desc = I40E_TX_DESC(tx_ring, i);
703 i -= tx_ring->count;
704
705 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
706
707 do {
708 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
709
710 /* if next_to_watch is not set then there is no work pending */
711 if (!eop_desc)
712 break;
713
714 /* prevent any other reads prior to eop_desc */
715 read_barrier_depends();
716
717 /* we have caught up to head, no work left to do */
718 if (tx_head == tx_desc)
719 break;
720
721 /* clear next_to_watch to prevent false hangs */
722 tx_buf->next_to_watch = NULL;
723
724 /* update the statistics for this packet */
725 total_bytes += tx_buf->bytecount;
726 total_packets += tx_buf->gso_segs;
727
728 /* free the skb */
729 dev_consume_skb_any(tx_buf->skb);
730
731 /* unmap skb header data */
732 dma_unmap_single(tx_ring->dev,
733 dma_unmap_addr(tx_buf, dma),
734 dma_unmap_len(tx_buf, len),
735 DMA_TO_DEVICE);
736
737 /* clear tx_buffer data */
738 tx_buf->skb = NULL;
739 dma_unmap_len_set(tx_buf, len, 0);
740
741 /* unmap remaining buffers */
742 while (tx_desc != eop_desc) {
743
744 tx_buf++;
745 tx_desc++;
746 i++;
747 if (unlikely(!i)) {
748 i -= tx_ring->count;
749 tx_buf = tx_ring->tx_bi;
750 tx_desc = I40E_TX_DESC(tx_ring, 0);
751 }
752
753 /* unmap any remaining paged data */
754 if (dma_unmap_len(tx_buf, len)) {
755 dma_unmap_page(tx_ring->dev,
756 dma_unmap_addr(tx_buf, dma),
757 dma_unmap_len(tx_buf, len),
758 DMA_TO_DEVICE);
759 dma_unmap_len_set(tx_buf, len, 0);
760 }
761 }
762
763 /* move us one more past the eop_desc for start of next pkt */
764 tx_buf++;
765 tx_desc++;
766 i++;
767 if (unlikely(!i)) {
768 i -= tx_ring->count;
769 tx_buf = tx_ring->tx_bi;
770 tx_desc = I40E_TX_DESC(tx_ring, 0);
771 }
772
773 prefetch(tx_desc);
774
775 /* update budget accounting */
776 budget--;
777 } while (likely(budget));
778
779 i += tx_ring->count;
780 tx_ring->next_to_clean = i;
781 u64_stats_update_begin(&tx_ring->syncp);
782 tx_ring->stats.bytes += total_bytes;
783 tx_ring->stats.packets += total_packets;
784 u64_stats_update_end(&tx_ring->syncp);
785 tx_ring->q_vector->tx.total_bytes += total_bytes;
786 tx_ring->q_vector->tx.total_packets += total_packets;
787
788 /* check to see if there are any non-cache aligned descriptors
789 * waiting to be written back, and kick the hardware to force
790 * them to be written back in case of napi polling
791 */
792 if (budget &&
793 !((i & WB_STRIDE) == WB_STRIDE) &&
794 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
795 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
796 tx_ring->arm_wb = true;
797 else
798 tx_ring->arm_wb = false;
799
800 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
801 /* schedule immediate reset if we believe we hung */
802 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
803 " VSI <%d>\n"
804 " Tx Queue <%d>\n"
805 " next_to_use <%x>\n"
806 " next_to_clean <%x>\n",
807 tx_ring->vsi->seid,
808 tx_ring->queue_index,
809 tx_ring->next_to_use, i);
810 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
811 " time_stamp <%lx>\n"
812 " jiffies <%lx>\n",
813 tx_ring->tx_bi[i].time_stamp, jiffies);
814
815 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
816
817 dev_info(tx_ring->dev,
818 "tx hang detected on queue %d, reset requested\n",
819 tx_ring->queue_index);
820
821 /* do not fire the reset immediately, wait for the stack to
822 * decide we are truly stuck, also prevents every queue from
823 * simultaneously requesting a reset
824 */
825
826 /* the adapter is about to reset, no point in enabling polling */
827 budget = 1;
828 }
829
830 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
831 tx_ring->queue_index),
832 total_packets, total_bytes);
833
834 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
835 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
836 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
837 /* Make sure that anybody stopping the queue after this
838 * sees the new next_to_clean.
839 */
840 smp_mb();
841 if (__netif_subqueue_stopped(tx_ring->netdev,
842 tx_ring->queue_index) &&
843 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
844 netif_wake_subqueue(tx_ring->netdev,
845 tx_ring->queue_index);
846 ++tx_ring->tx_stats.restart_queue;
847 }
848 }
849
850 return !!budget;
851 }
852
853 /**
854 * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors
855 * @vsi: the VSI we care about
856 * @q_vector: the vector on which to force writeback
857 *
858 **/
859 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
860 {
861 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
862 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
863 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
864 /* allow 00 to be written to the index */
865
866 wr32(&vsi->back->hw,
867 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1),
868 val);
869 }
870
871 /**
872 * i40e_set_new_dynamic_itr - Find new ITR level
873 * @rc: structure containing ring performance data
874 *
875 * Stores a new ITR value based on packets and byte counts during
876 * the last interrupt. The advantage of per interrupt computation
877 * is faster updates and more accurate ITR for the current traffic
878 * pattern. Constants in this function were computed based on
879 * theoretical maximum wire speed and thresholds were set based on
880 * testing data as well as attempting to minimize response time
881 * while increasing bulk throughput.
882 **/
883 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
884 {
885 enum i40e_latency_range new_latency_range = rc->latency_range;
886 u32 new_itr = rc->itr;
887 int bytes_per_int;
888
889 if (rc->total_packets == 0 || !rc->itr)
890 return;
891
892 /* simple throttlerate management
893 * 0-10MB/s lowest (100000 ints/s)
894 * 10-20MB/s low (20000 ints/s)
895 * 20-1249MB/s bulk (8000 ints/s)
896 */
897 bytes_per_int = rc->total_bytes / rc->itr;
898 switch (rc->itr) {
899 case I40E_LOWEST_LATENCY:
900 if (bytes_per_int > 10)
901 new_latency_range = I40E_LOW_LATENCY;
902 break;
903 case I40E_LOW_LATENCY:
904 if (bytes_per_int > 20)
905 new_latency_range = I40E_BULK_LATENCY;
906 else if (bytes_per_int <= 10)
907 new_latency_range = I40E_LOWEST_LATENCY;
908 break;
909 case I40E_BULK_LATENCY:
910 if (bytes_per_int <= 20)
911 rc->latency_range = I40E_LOW_LATENCY;
912 break;
913 }
914
915 switch (new_latency_range) {
916 case I40E_LOWEST_LATENCY:
917 new_itr = I40E_ITR_100K;
918 break;
919 case I40E_LOW_LATENCY:
920 new_itr = I40E_ITR_20K;
921 break;
922 case I40E_BULK_LATENCY:
923 new_itr = I40E_ITR_8K;
924 break;
925 default:
926 break;
927 }
928
929 if (new_itr != rc->itr) {
930 /* do an exponential smoothing */
931 new_itr = (10 * new_itr * rc->itr) /
932 ((9 * new_itr) + rc->itr);
933 rc->itr = new_itr & I40E_MAX_ITR;
934 }
935
936 rc->total_bytes = 0;
937 rc->total_packets = 0;
938 }
939
940 /**
941 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
942 * @q_vector: the vector to adjust
943 **/
944 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
945 {
946 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
947 struct i40e_hw *hw = &q_vector->vsi->back->hw;
948 u32 reg_addr;
949 u16 old_itr;
950
951 reg_addr = I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1);
952 old_itr = q_vector->rx.itr;
953 i40e_set_new_dynamic_itr(&q_vector->rx);
954 if (old_itr != q_vector->rx.itr)
955 wr32(hw, reg_addr, q_vector->rx.itr);
956
957 reg_addr = I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1);
958 old_itr = q_vector->tx.itr;
959 i40e_set_new_dynamic_itr(&q_vector->tx);
960 if (old_itr != q_vector->tx.itr)
961 wr32(hw, reg_addr, q_vector->tx.itr);
962 }
963
964 /**
965 * i40e_clean_programming_status - clean the programming status descriptor
966 * @rx_ring: the rx ring that has this descriptor
967 * @rx_desc: the rx descriptor written back by HW
968 *
969 * Flow director should handle FD_FILTER_STATUS to check its filter programming
970 * status being successful or not and take actions accordingly. FCoE should
971 * handle its context/filter programming/invalidation status and take actions.
972 *
973 **/
974 static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
975 union i40e_rx_desc *rx_desc)
976 {
977 u64 qw;
978 u8 id;
979
980 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
981 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
982 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
983
984 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
985 i40e_fd_handle_status(rx_ring, rx_desc, id);
986 #ifdef I40E_FCOE
987 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
988 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
989 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
990 #endif
991 }
992
993 /**
994 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
995 * @tx_ring: the tx ring to set up
996 *
997 * Return 0 on success, negative on error
998 **/
999 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1000 {
1001 struct device *dev = tx_ring->dev;
1002 int bi_size;
1003
1004 if (!dev)
1005 return -ENOMEM;
1006
1007 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1008 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1009 if (!tx_ring->tx_bi)
1010 goto err;
1011
1012 /* round up to nearest 4K */
1013 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1014 /* add u32 for head writeback, align after this takes care of
1015 * guaranteeing this is at least one cache line in size
1016 */
1017 tx_ring->size += sizeof(u32);
1018 tx_ring->size = ALIGN(tx_ring->size, 4096);
1019 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1020 &tx_ring->dma, GFP_KERNEL);
1021 if (!tx_ring->desc) {
1022 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1023 tx_ring->size);
1024 goto err;
1025 }
1026
1027 tx_ring->next_to_use = 0;
1028 tx_ring->next_to_clean = 0;
1029 return 0;
1030
1031 err:
1032 kfree(tx_ring->tx_bi);
1033 tx_ring->tx_bi = NULL;
1034 return -ENOMEM;
1035 }
1036
1037 /**
1038 * i40e_clean_rx_ring - Free Rx buffers
1039 * @rx_ring: ring to be cleaned
1040 **/
1041 void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1042 {
1043 struct device *dev = rx_ring->dev;
1044 struct i40e_rx_buffer *rx_bi;
1045 unsigned long bi_size;
1046 u16 i;
1047
1048 /* ring already cleared, nothing to do */
1049 if (!rx_ring->rx_bi)
1050 return;
1051
1052 if (ring_is_ps_enabled(rx_ring)) {
1053 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
1054
1055 rx_bi = &rx_ring->rx_bi[0];
1056 if (rx_bi->hdr_buf) {
1057 dma_free_coherent(dev,
1058 bufsz,
1059 rx_bi->hdr_buf,
1060 rx_bi->dma);
1061 for (i = 0; i < rx_ring->count; i++) {
1062 rx_bi = &rx_ring->rx_bi[i];
1063 rx_bi->dma = 0;
1064 rx_bi->hdr_buf = NULL;
1065 }
1066 }
1067 }
1068 /* Free all the Rx ring sk_buffs */
1069 for (i = 0; i < rx_ring->count; i++) {
1070 rx_bi = &rx_ring->rx_bi[i];
1071 if (rx_bi->dma) {
1072 dma_unmap_single(dev,
1073 rx_bi->dma,
1074 rx_ring->rx_buf_len,
1075 DMA_FROM_DEVICE);
1076 rx_bi->dma = 0;
1077 }
1078 if (rx_bi->skb) {
1079 dev_kfree_skb(rx_bi->skb);
1080 rx_bi->skb = NULL;
1081 }
1082 if (rx_bi->page) {
1083 if (rx_bi->page_dma) {
1084 dma_unmap_page(dev,
1085 rx_bi->page_dma,
1086 PAGE_SIZE / 2,
1087 DMA_FROM_DEVICE);
1088 rx_bi->page_dma = 0;
1089 }
1090 __free_page(rx_bi->page);
1091 rx_bi->page = NULL;
1092 rx_bi->page_offset = 0;
1093 }
1094 }
1095
1096 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1097 memset(rx_ring->rx_bi, 0, bi_size);
1098
1099 /* Zero out the descriptor ring */
1100 memset(rx_ring->desc, 0, rx_ring->size);
1101
1102 rx_ring->next_to_clean = 0;
1103 rx_ring->next_to_use = 0;
1104 }
1105
1106 /**
1107 * i40e_free_rx_resources - Free Rx resources
1108 * @rx_ring: ring to clean the resources from
1109 *
1110 * Free all receive software resources
1111 **/
1112 void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1113 {
1114 i40e_clean_rx_ring(rx_ring);
1115 kfree(rx_ring->rx_bi);
1116 rx_ring->rx_bi = NULL;
1117
1118 if (rx_ring->desc) {
1119 dma_free_coherent(rx_ring->dev, rx_ring->size,
1120 rx_ring->desc, rx_ring->dma);
1121 rx_ring->desc = NULL;
1122 }
1123 }
1124
1125 /**
1126 * i40e_alloc_rx_headers - allocate rx header buffers
1127 * @rx_ring: ring to alloc buffers
1128 *
1129 * Allocate rx header buffers for the entire ring. As these are static,
1130 * this is only called when setting up a new ring.
1131 **/
1132 void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1133 {
1134 struct device *dev = rx_ring->dev;
1135 struct i40e_rx_buffer *rx_bi;
1136 dma_addr_t dma;
1137 void *buffer;
1138 int buf_size;
1139 int i;
1140
1141 if (rx_ring->rx_bi[0].hdr_buf)
1142 return;
1143 /* Make sure the buffers don't cross cache line boundaries. */
1144 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1145 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1146 &dma, GFP_KERNEL);
1147 if (!buffer)
1148 return;
1149 for (i = 0; i < rx_ring->count; i++) {
1150 rx_bi = &rx_ring->rx_bi[i];
1151 rx_bi->dma = dma + (i * buf_size);
1152 rx_bi->hdr_buf = buffer + (i * buf_size);
1153 }
1154 }
1155
1156 /**
1157 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1158 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1159 *
1160 * Returns 0 on success, negative on failure
1161 **/
1162 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1163 {
1164 struct device *dev = rx_ring->dev;
1165 int bi_size;
1166
1167 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1168 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1169 if (!rx_ring->rx_bi)
1170 goto err;
1171
1172 u64_stats_init(&rx_ring->syncp);
1173
1174 /* Round up to nearest 4K */
1175 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1176 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1177 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1178 rx_ring->size = ALIGN(rx_ring->size, 4096);
1179 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1180 &rx_ring->dma, GFP_KERNEL);
1181
1182 if (!rx_ring->desc) {
1183 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1184 rx_ring->size);
1185 goto err;
1186 }
1187
1188 rx_ring->next_to_clean = 0;
1189 rx_ring->next_to_use = 0;
1190
1191 return 0;
1192 err:
1193 kfree(rx_ring->rx_bi);
1194 rx_ring->rx_bi = NULL;
1195 return -ENOMEM;
1196 }
1197
1198 /**
1199 * i40e_release_rx_desc - Store the new tail and head values
1200 * @rx_ring: ring to bump
1201 * @val: new head index
1202 **/
1203 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1204 {
1205 rx_ring->next_to_use = val;
1206 /* Force memory writes to complete before letting h/w
1207 * know there are new descriptors to fetch. (Only
1208 * applicable for weak-ordered memory model archs,
1209 * such as IA-64).
1210 */
1211 wmb();
1212 writel(val, rx_ring->tail);
1213 }
1214
1215 /**
1216 * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
1217 * @rx_ring: ring to place buffers on
1218 * @cleaned_count: number of buffers to replace
1219 **/
1220 void i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1221 {
1222 u16 i = rx_ring->next_to_use;
1223 union i40e_rx_desc *rx_desc;
1224 struct i40e_rx_buffer *bi;
1225
1226 /* do nothing if no valid netdev defined */
1227 if (!rx_ring->netdev || !cleaned_count)
1228 return;
1229
1230 while (cleaned_count--) {
1231 rx_desc = I40E_RX_DESC(rx_ring, i);
1232 bi = &rx_ring->rx_bi[i];
1233
1234 if (bi->skb) /* desc is in use */
1235 goto no_buffers;
1236 if (!bi->page) {
1237 bi->page = alloc_page(GFP_ATOMIC);
1238 if (!bi->page) {
1239 rx_ring->rx_stats.alloc_page_failed++;
1240 goto no_buffers;
1241 }
1242 }
1243
1244 if (!bi->page_dma) {
1245 /* use a half page if we're re-using */
1246 bi->page_offset ^= PAGE_SIZE / 2;
1247 bi->page_dma = dma_map_page(rx_ring->dev,
1248 bi->page,
1249 bi->page_offset,
1250 PAGE_SIZE / 2,
1251 DMA_FROM_DEVICE);
1252 if (dma_mapping_error(rx_ring->dev,
1253 bi->page_dma)) {
1254 rx_ring->rx_stats.alloc_page_failed++;
1255 bi->page_dma = 0;
1256 goto no_buffers;
1257 }
1258 }
1259
1260 dma_sync_single_range_for_device(rx_ring->dev,
1261 bi->dma,
1262 0,
1263 rx_ring->rx_hdr_len,
1264 DMA_FROM_DEVICE);
1265 /* Refresh the desc even if buffer_addrs didn't change
1266 * because each write-back erases this info.
1267 */
1268 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1269 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1270 i++;
1271 if (i == rx_ring->count)
1272 i = 0;
1273 }
1274
1275 no_buffers:
1276 if (rx_ring->next_to_use != i)
1277 i40e_release_rx_desc(rx_ring, i);
1278 }
1279
1280 /**
1281 * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1282 * @rx_ring: ring to place buffers on
1283 * @cleaned_count: number of buffers to replace
1284 **/
1285 void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
1286 {
1287 u16 i = rx_ring->next_to_use;
1288 union i40e_rx_desc *rx_desc;
1289 struct i40e_rx_buffer *bi;
1290 struct sk_buff *skb;
1291
1292 /* do nothing if no valid netdev defined */
1293 if (!rx_ring->netdev || !cleaned_count)
1294 return;
1295
1296 while (cleaned_count--) {
1297 rx_desc = I40E_RX_DESC(rx_ring, i);
1298 bi = &rx_ring->rx_bi[i];
1299 skb = bi->skb;
1300
1301 if (!skb) {
1302 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1303 rx_ring->rx_buf_len);
1304 if (!skb) {
1305 rx_ring->rx_stats.alloc_buff_failed++;
1306 goto no_buffers;
1307 }
1308 /* initialize queue mapping */
1309 skb_record_rx_queue(skb, rx_ring->queue_index);
1310 bi->skb = skb;
1311 }
1312
1313 if (!bi->dma) {
1314 bi->dma = dma_map_single(rx_ring->dev,
1315 skb->data,
1316 rx_ring->rx_buf_len,
1317 DMA_FROM_DEVICE);
1318 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1319 rx_ring->rx_stats.alloc_buff_failed++;
1320 bi->dma = 0;
1321 goto no_buffers;
1322 }
1323 }
1324
1325 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1326 rx_desc->read.hdr_addr = 0;
1327 i++;
1328 if (i == rx_ring->count)
1329 i = 0;
1330 }
1331
1332 no_buffers:
1333 if (rx_ring->next_to_use != i)
1334 i40e_release_rx_desc(rx_ring, i);
1335 }
1336
1337 /**
1338 * i40e_receive_skb - Send a completed packet up the stack
1339 * @rx_ring: rx ring in play
1340 * @skb: packet to send up
1341 * @vlan_tag: vlan tag for packet
1342 **/
1343 static void i40e_receive_skb(struct i40e_ring *rx_ring,
1344 struct sk_buff *skb, u16 vlan_tag)
1345 {
1346 struct i40e_q_vector *q_vector = rx_ring->q_vector;
1347 struct i40e_vsi *vsi = rx_ring->vsi;
1348 u64 flags = vsi->back->flags;
1349
1350 if (vlan_tag & VLAN_VID_MASK)
1351 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1352
1353 if (flags & I40E_FLAG_IN_NETPOLL)
1354 netif_rx(skb);
1355 else
1356 napi_gro_receive(&q_vector->napi, skb);
1357 }
1358
1359 /**
1360 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1361 * @vsi: the VSI we care about
1362 * @skb: skb currently being received and modified
1363 * @rx_status: status value of last descriptor in packet
1364 * @rx_error: error value of last descriptor in packet
1365 * @rx_ptype: ptype value of last descriptor in packet
1366 **/
1367 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1368 struct sk_buff *skb,
1369 u32 rx_status,
1370 u32 rx_error,
1371 u16 rx_ptype)
1372 {
1373 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1374 bool ipv4 = false, ipv6 = false;
1375 bool ipv4_tunnel, ipv6_tunnel;
1376 __wsum rx_udp_csum;
1377 struct iphdr *iph;
1378 __sum16 csum;
1379
1380 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1381 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1382 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1383 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
1384
1385 skb->ip_summed = CHECKSUM_NONE;
1386
1387 /* Rx csum enabled and ip headers found? */
1388 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1389 return;
1390
1391 /* did the hardware decode the packet and checksum? */
1392 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1393 return;
1394
1395 /* both known and outer_ip must be set for the below code to work */
1396 if (!(decoded.known && decoded.outer_ip))
1397 return;
1398
1399 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1400 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
1401 ipv4 = true;
1402 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1403 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
1404 ipv6 = true;
1405
1406 if (ipv4 &&
1407 (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
1408 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1409 goto checksum_fail;
1410
1411 /* likely incorrect csum if alternate IP extension headers found */
1412 if (ipv6 &&
1413 rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1414 /* don't increment checksum err here, non-fatal err */
1415 return;
1416
1417 /* there was some L4 error, count error and punt packet to the stack */
1418 if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
1419 goto checksum_fail;
1420
1421 /* handle packets that were not able to be checksummed due
1422 * to arrival speed, in this case the stack can compute
1423 * the csum.
1424 */
1425 if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
1426 return;
1427
1428 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
1429 * it in the driver, hardware does not do it for us.
1430 * Since L3L4P bit was set we assume a valid IHL value (>=5)
1431 * so the total length of IPv4 header is IHL*4 bytes
1432 * The UDP_0 bit *may* bet set if the *inner* header is UDP
1433 */
1434 if (ipv4_tunnel) {
1435 skb->transport_header = skb->mac_header +
1436 sizeof(struct ethhdr) +
1437 (ip_hdr(skb)->ihl * 4);
1438
1439 /* Add 4 bytes for VLAN tagged packets */
1440 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1441 skb->protocol == htons(ETH_P_8021AD))
1442 ? VLAN_HLEN : 0;
1443
1444 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
1445 (udp_hdr(skb)->check != 0)) {
1446 rx_udp_csum = udp_csum(skb);
1447 iph = ip_hdr(skb);
1448 csum = csum_tcpudp_magic(
1449 iph->saddr, iph->daddr,
1450 (skb->len - skb_transport_offset(skb)),
1451 IPPROTO_UDP, rx_udp_csum);
1452
1453 if (udp_hdr(skb)->check != csum)
1454 goto checksum_fail;
1455
1456 } /* else its GRE and so no outer UDP header */
1457 }
1458
1459 skb->ip_summed = CHECKSUM_UNNECESSARY;
1460 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
1461
1462 return;
1463
1464 checksum_fail:
1465 vsi->back->hw_csum_rx_error++;
1466 }
1467
1468 /**
1469 * i40e_rx_hash - returns the hash value from the Rx descriptor
1470 * @ring: descriptor ring
1471 * @rx_desc: specific descriptor
1472 **/
1473 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
1474 union i40e_rx_desc *rx_desc)
1475 {
1476 const __le64 rss_mask =
1477 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1478 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1479
1480 if ((ring->netdev->features & NETIF_F_RXHASH) &&
1481 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
1482 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1483 else
1484 return 0;
1485 }
1486
1487 /**
1488 * i40e_ptype_to_hash - get a hash type
1489 * @ptype: the ptype value from the descriptor
1490 *
1491 * Returns a hash type to be used by skb_set_hash
1492 **/
1493 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
1494 {
1495 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1496
1497 if (!decoded.known)
1498 return PKT_HASH_TYPE_NONE;
1499
1500 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1501 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1502 return PKT_HASH_TYPE_L4;
1503 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1504 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1505 return PKT_HASH_TYPE_L3;
1506 else
1507 return PKT_HASH_TYPE_L2;
1508 }
1509
1510 /**
1511 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
1512 * @rx_ring: rx ring to clean
1513 * @budget: how many cleans we're allowed
1514 *
1515 * Returns true if there's any budget left (e.g. the clean is finished)
1516 **/
1517 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
1518 {
1519 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1520 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1521 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1522 const int current_node = numa_node_id();
1523 struct i40e_vsi *vsi = rx_ring->vsi;
1524 u16 i = rx_ring->next_to_clean;
1525 union i40e_rx_desc *rx_desc;
1526 u32 rx_error, rx_status;
1527 u8 rx_ptype;
1528 u64 qword;
1529
1530 if (budget <= 0)
1531 return 0;
1532
1533 do {
1534 struct i40e_rx_buffer *rx_bi;
1535 struct sk_buff *skb;
1536 u16 vlan_tag;
1537 /* return some buffers to hardware, one at a time is too slow */
1538 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1539 i40e_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1540 cleaned_count = 0;
1541 }
1542
1543 i = rx_ring->next_to_clean;
1544 rx_desc = I40E_RX_DESC(rx_ring, i);
1545 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1546 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1547 I40E_RXD_QW1_STATUS_SHIFT;
1548
1549 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1550 break;
1551
1552 /* This memory barrier is needed to keep us from reading
1553 * any other fields out of the rx_desc until we know the
1554 * DD bit is set.
1555 */
1556 rmb();
1557 if (i40e_rx_is_programming_status(qword)) {
1558 i40e_clean_programming_status(rx_ring, rx_desc);
1559 I40E_RX_INCREMENT(rx_ring, i);
1560 continue;
1561 }
1562 rx_bi = &rx_ring->rx_bi[i];
1563 skb = rx_bi->skb;
1564 if (likely(!skb)) {
1565 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1566 rx_ring->rx_hdr_len);
1567 if (!skb)
1568 rx_ring->rx_stats.alloc_buff_failed++;
1569 /* initialize queue mapping */
1570 skb_record_rx_queue(skb, rx_ring->queue_index);
1571 /* we are reusing so sync this buffer for CPU use */
1572 dma_sync_single_range_for_cpu(rx_ring->dev,
1573 rx_bi->dma,
1574 0,
1575 rx_ring->rx_hdr_len,
1576 DMA_FROM_DEVICE);
1577 }
1578 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1579 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1580 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1581 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1582 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1583 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1584
1585 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1586 I40E_RXD_QW1_ERROR_SHIFT;
1587 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1588 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1589
1590 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1591 I40E_RXD_QW1_PTYPE_SHIFT;
1592 prefetch(rx_bi->page);
1593 rx_bi->skb = NULL;
1594 cleaned_count++;
1595 if (rx_hbo || rx_sph) {
1596 int len;
1597 if (rx_hbo)
1598 len = I40E_RX_HDR_SIZE;
1599 else
1600 len = rx_header_len;
1601 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1602 } else if (skb->len == 0) {
1603 int len;
1604
1605 len = (rx_packet_len > skb_headlen(skb) ?
1606 skb_headlen(skb) : rx_packet_len);
1607 memcpy(__skb_put(skb, len),
1608 rx_bi->page + rx_bi->page_offset,
1609 len);
1610 rx_bi->page_offset += len;
1611 rx_packet_len -= len;
1612 }
1613
1614 /* Get the rest of the data if this was a header split */
1615 if (rx_packet_len) {
1616 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1617 rx_bi->page,
1618 rx_bi->page_offset,
1619 rx_packet_len);
1620
1621 skb->len += rx_packet_len;
1622 skb->data_len += rx_packet_len;
1623 skb->truesize += rx_packet_len;
1624
1625 if ((page_count(rx_bi->page) == 1) &&
1626 (page_to_nid(rx_bi->page) == current_node))
1627 get_page(rx_bi->page);
1628 else
1629 rx_bi->page = NULL;
1630
1631 dma_unmap_page(rx_ring->dev,
1632 rx_bi->page_dma,
1633 PAGE_SIZE / 2,
1634 DMA_FROM_DEVICE);
1635 rx_bi->page_dma = 0;
1636 }
1637 I40E_RX_INCREMENT(rx_ring, i);
1638
1639 if (unlikely(
1640 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1641 struct i40e_rx_buffer *next_buffer;
1642
1643 next_buffer = &rx_ring->rx_bi[i];
1644 next_buffer->skb = skb;
1645 rx_ring->rx_stats.non_eop_descs++;
1646 continue;
1647 }
1648
1649 /* ERR_MASK will only have valid bits if EOP set */
1650 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1651 dev_kfree_skb_any(skb);
1652 /* TODO: shouldn't we increment a counter indicating the
1653 * drop?
1654 */
1655 continue;
1656 }
1657
1658 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1659 i40e_ptype_to_hash(rx_ptype));
1660 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1661 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1662 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1663 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1664 rx_ring->last_rx_timestamp = jiffies;
1665 }
1666
1667 /* probably a little skewed due to removing CRC */
1668 total_rx_bytes += skb->len;
1669 total_rx_packets++;
1670
1671 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1672
1673 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1674
1675 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1676 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1677 : 0;
1678 #ifdef I40E_FCOE
1679 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1680 dev_kfree_skb_any(skb);
1681 continue;
1682 }
1683 #endif
1684 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1685 i40e_receive_skb(rx_ring, skb, vlan_tag);
1686
1687 rx_ring->netdev->last_rx = jiffies;
1688 rx_desc->wb.qword1.status_error_len = 0;
1689
1690 } while (likely(total_rx_packets < budget));
1691
1692 u64_stats_update_begin(&rx_ring->syncp);
1693 rx_ring->stats.packets += total_rx_packets;
1694 rx_ring->stats.bytes += total_rx_bytes;
1695 u64_stats_update_end(&rx_ring->syncp);
1696 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1697 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1698
1699 return total_rx_packets;
1700 }
1701
1702 /**
1703 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1704 * @rx_ring: rx ring to clean
1705 * @budget: how many cleans we're allowed
1706 *
1707 * Returns number of packets cleaned
1708 **/
1709 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1710 {
1711 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1712 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1713 struct i40e_vsi *vsi = rx_ring->vsi;
1714 union i40e_rx_desc *rx_desc;
1715 u32 rx_error, rx_status;
1716 u16 rx_packet_len;
1717 u8 rx_ptype;
1718 u64 qword;
1719 u16 i;
1720
1721 do {
1722 struct i40e_rx_buffer *rx_bi;
1723 struct sk_buff *skb;
1724 u16 vlan_tag;
1725 /* return some buffers to hardware, one at a time is too slow */
1726 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1727 i40e_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1728 cleaned_count = 0;
1729 }
1730
1731 i = rx_ring->next_to_clean;
1732 rx_desc = I40E_RX_DESC(rx_ring, i);
1733 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1734 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1735 I40E_RXD_QW1_STATUS_SHIFT;
1736
1737 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1738 break;
1739
1740 /* This memory barrier is needed to keep us from reading
1741 * any other fields out of the rx_desc until we know the
1742 * DD bit is set.
1743 */
1744 rmb();
1745
1746 if (i40e_rx_is_programming_status(qword)) {
1747 i40e_clean_programming_status(rx_ring, rx_desc);
1748 I40E_RX_INCREMENT(rx_ring, i);
1749 continue;
1750 }
1751 rx_bi = &rx_ring->rx_bi[i];
1752 skb = rx_bi->skb;
1753 prefetch(skb->data);
1754
1755 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1756 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1757
1758 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1759 I40E_RXD_QW1_ERROR_SHIFT;
1760 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1761
1762 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1763 I40E_RXD_QW1_PTYPE_SHIFT;
1764 rx_bi->skb = NULL;
1765 cleaned_count++;
1766
1767 /* Get the header and possibly the whole packet
1768 * If this is an skb from previous receive dma will be 0
1769 */
1770 skb_put(skb, rx_packet_len);
1771 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1772 DMA_FROM_DEVICE);
1773 rx_bi->dma = 0;
1774
1775 I40E_RX_INCREMENT(rx_ring, i);
1776
1777 if (unlikely(
1778 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1779 rx_ring->rx_stats.non_eop_descs++;
1780 continue;
1781 }
1782
1783 /* ERR_MASK will only have valid bits if EOP set */
1784 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1785 dev_kfree_skb_any(skb);
1786 /* TODO: shouldn't we increment a counter indicating the
1787 * drop?
1788 */
1789 continue;
1790 }
1791
1792 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1793 i40e_ptype_to_hash(rx_ptype));
1794 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1795 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1796 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1797 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1798 rx_ring->last_rx_timestamp = jiffies;
1799 }
1800
1801 /* probably a little skewed due to removing CRC */
1802 total_rx_bytes += skb->len;
1803 total_rx_packets++;
1804
1805 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1806
1807 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1808
1809 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1810 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1811 : 0;
1812 #ifdef I40E_FCOE
1813 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1814 dev_kfree_skb_any(skb);
1815 continue;
1816 }
1817 #endif
1818 i40e_receive_skb(rx_ring, skb, vlan_tag);
1819
1820 rx_ring->netdev->last_rx = jiffies;
1821 rx_desc->wb.qword1.status_error_len = 0;
1822 } while (likely(total_rx_packets < budget));
1823
1824 u64_stats_update_begin(&rx_ring->syncp);
1825 rx_ring->stats.packets += total_rx_packets;
1826 rx_ring->stats.bytes += total_rx_bytes;
1827 u64_stats_update_end(&rx_ring->syncp);
1828 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1829 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1830
1831 return total_rx_packets;
1832 }
1833
1834 /**
1835 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1836 * @napi: napi struct with our devices info in it
1837 * @budget: amount of work driver is allowed to do this pass, in packets
1838 *
1839 * This function will clean all queues associated with a q_vector.
1840 *
1841 * Returns the amount of work done
1842 **/
1843 int i40e_napi_poll(struct napi_struct *napi, int budget)
1844 {
1845 struct i40e_q_vector *q_vector =
1846 container_of(napi, struct i40e_q_vector, napi);
1847 struct i40e_vsi *vsi = q_vector->vsi;
1848 struct i40e_ring *ring;
1849 bool clean_complete = true;
1850 bool arm_wb = false;
1851 int budget_per_ring;
1852 int cleaned;
1853
1854 if (test_bit(__I40E_DOWN, &vsi->state)) {
1855 napi_complete(napi);
1856 return 0;
1857 }
1858
1859 /* Since the actual Tx work is minimal, we can give the Tx a larger
1860 * budget and be more aggressive about cleaning up the Tx descriptors.
1861 */
1862 i40e_for_each_ring(ring, q_vector->tx) {
1863 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1864 arm_wb |= ring->arm_wb;
1865 }
1866
1867 /* We attempt to distribute budget to each Rx queue fairly, but don't
1868 * allow the budget to go below 1 because that would exit polling early.
1869 */
1870 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1871
1872 i40e_for_each_ring(ring, q_vector->rx) {
1873 if (ring_is_ps_enabled(ring))
1874 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1875 else
1876 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1877 /* if we didn't clean as many as budgeted, we must be done */
1878 clean_complete &= (budget_per_ring != cleaned);
1879 }
1880
1881 /* If work not completed, return budget and polling will return */
1882 if (!clean_complete) {
1883 if (arm_wb)
1884 i40e_force_wb(vsi, q_vector);
1885 return budget;
1886 }
1887
1888 /* Work is done so exit the polling mode and re-enable the interrupt */
1889 napi_complete(napi);
1890 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1891 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1892 i40e_update_dynamic_itr(q_vector);
1893
1894 if (!test_bit(__I40E_DOWN, &vsi->state)) {
1895 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1896 i40e_irq_dynamic_enable(vsi,
1897 q_vector->v_idx + vsi->base_vector);
1898 } else {
1899 struct i40e_hw *hw = &vsi->back->hw;
1900 /* We re-enable the queue 0 cause, but
1901 * don't worry about dynamic_enable
1902 * because we left it on for the other
1903 * possible interrupts during napi
1904 */
1905 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
1906 qval |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1907 wr32(hw, I40E_QINT_RQCTL(0), qval);
1908
1909 qval = rd32(hw, I40E_QINT_TQCTL(0));
1910 qval |= I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1911 wr32(hw, I40E_QINT_TQCTL(0), qval);
1912
1913 i40e_irq_dynamic_enable_icr0(vsi->back);
1914 }
1915 }
1916
1917 return 0;
1918 }
1919
1920 /**
1921 * i40e_atr - Add a Flow Director ATR filter
1922 * @tx_ring: ring to add programming descriptor to
1923 * @skb: send buffer
1924 * @flags: send flags
1925 * @protocol: wire protocol
1926 **/
1927 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
1928 u32 flags, __be16 protocol)
1929 {
1930 struct i40e_filter_program_desc *fdir_desc;
1931 struct i40e_pf *pf = tx_ring->vsi->back;
1932 union {
1933 unsigned char *network;
1934 struct iphdr *ipv4;
1935 struct ipv6hdr *ipv6;
1936 } hdr;
1937 struct tcphdr *th;
1938 unsigned int hlen;
1939 u32 flex_ptype, dtype_cmd;
1940 u16 i;
1941
1942 /* make sure ATR is enabled */
1943 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
1944 return;
1945
1946 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1947 return;
1948
1949 /* if sampling is disabled do nothing */
1950 if (!tx_ring->atr_sample_rate)
1951 return;
1952
1953 /* snag network header to get L4 type and address */
1954 hdr.network = skb_network_header(skb);
1955
1956 /* Currently only IPv4/IPv6 with TCP is supported */
1957 if (protocol == htons(ETH_P_IP)) {
1958 if (hdr.ipv4->protocol != IPPROTO_TCP)
1959 return;
1960
1961 /* access ihl as a u8 to avoid unaligned access on ia64 */
1962 hlen = (hdr.network[0] & 0x0F) << 2;
1963 } else if (protocol == htons(ETH_P_IPV6)) {
1964 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1965 return;
1966
1967 hlen = sizeof(struct ipv6hdr);
1968 } else {
1969 return;
1970 }
1971
1972 th = (struct tcphdr *)(hdr.network + hlen);
1973
1974 /* Due to lack of space, no more new filters can be programmed */
1975 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1976 return;
1977
1978 tx_ring->atr_count++;
1979
1980 /* sample on all syn/fin/rst packets or once every atr sample rate */
1981 if (!th->fin &&
1982 !th->syn &&
1983 !th->rst &&
1984 (tx_ring->atr_count < tx_ring->atr_sample_rate))
1985 return;
1986
1987 tx_ring->atr_count = 0;
1988
1989 /* grab the next descriptor */
1990 i = tx_ring->next_to_use;
1991 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
1992
1993 i++;
1994 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1995
1996 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1997 I40E_TXD_FLTR_QW0_QINDEX_MASK;
1998 flex_ptype |= (protocol == htons(ETH_P_IP)) ?
1999 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2000 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2001 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2002 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2003
2004 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2005
2006 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2007
2008 dtype_cmd |= (th->fin || th->rst) ?
2009 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2010 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2011 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2012 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2013
2014 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2015 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2016
2017 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2018 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2019
2020 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2021 dtype_cmd |=
2022 ((u32)pf->fd_atr_cnt_idx << I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2023 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2024
2025 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2026 fdir_desc->rsvd = cpu_to_le32(0);
2027 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2028 fdir_desc->fd_id = cpu_to_le32(0);
2029 }
2030
2031 /**
2032 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2033 * @skb: send buffer
2034 * @tx_ring: ring to send buffer on
2035 * @flags: the tx flags to be set
2036 *
2037 * Checks the skb and set up correspondingly several generic transmit flags
2038 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2039 *
2040 * Returns error code indicate the frame should be dropped upon error and the
2041 * otherwise returns 0 to indicate the flags has been set properly.
2042 **/
2043 #ifdef I40E_FCOE
2044 int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2045 struct i40e_ring *tx_ring,
2046 u32 *flags)
2047 #else
2048 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2049 struct i40e_ring *tx_ring,
2050 u32 *flags)
2051 #endif
2052 {
2053 __be16 protocol = skb->protocol;
2054 u32 tx_flags = 0;
2055
2056 /* if we have a HW VLAN tag being added, default to the HW one */
2057 if (skb_vlan_tag_present(skb)) {
2058 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2059 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2060 /* else if it is a SW VLAN, check the next protocol and store the tag */
2061 } else if (protocol == htons(ETH_P_8021Q)) {
2062 struct vlan_hdr *vhdr, _vhdr;
2063 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2064 if (!vhdr)
2065 return -EINVAL;
2066
2067 protocol = vhdr->h_vlan_encapsulated_proto;
2068 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2069 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2070 }
2071
2072 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2073 goto out;
2074
2075 /* Insert 802.1p priority into VLAN header */
2076 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2077 (skb->priority != TC_PRIO_CONTROL)) {
2078 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2079 tx_flags |= (skb->priority & 0x7) <<
2080 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2081 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2082 struct vlan_ethhdr *vhdr;
2083 int rc;
2084
2085 rc = skb_cow_head(skb, 0);
2086 if (rc < 0)
2087 return rc;
2088 vhdr = (struct vlan_ethhdr *)skb->data;
2089 vhdr->h_vlan_TCI = htons(tx_flags >>
2090 I40E_TX_FLAGS_VLAN_SHIFT);
2091 } else {
2092 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2093 }
2094 }
2095
2096 out:
2097 *flags = tx_flags;
2098 return 0;
2099 }
2100
2101 /**
2102 * i40e_tso - set up the tso context descriptor
2103 * @tx_ring: ptr to the ring to send
2104 * @skb: ptr to the skb we're sending
2105 * @tx_flags: the collected send information
2106 * @protocol: the send protocol
2107 * @hdr_len: ptr to the size of the packet header
2108 * @cd_tunneling: ptr to context descriptor bits
2109 *
2110 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2111 **/
2112 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
2113 u32 tx_flags, __be16 protocol, u8 *hdr_len,
2114 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
2115 {
2116 u32 cd_cmd, cd_tso_len, cd_mss;
2117 struct ipv6hdr *ipv6h;
2118 struct tcphdr *tcph;
2119 struct iphdr *iph;
2120 u32 l4len;
2121 int err;
2122
2123 if (!skb_is_gso(skb))
2124 return 0;
2125
2126 err = skb_cow_head(skb, 0);
2127 if (err < 0)
2128 return err;
2129
2130 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
2131 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
2132
2133 if (iph->version == 4) {
2134 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2135 iph->tot_len = 0;
2136 iph->check = 0;
2137 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
2138 0, IPPROTO_TCP, 0);
2139 } else if (ipv6h->version == 6) {
2140 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2141 ipv6h->payload_len = 0;
2142 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
2143 0, IPPROTO_TCP, 0);
2144 }
2145
2146 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
2147 *hdr_len = (skb->encapsulation
2148 ? (skb_inner_transport_header(skb) - skb->data)
2149 : skb_transport_offset(skb)) + l4len;
2150
2151 /* find the field values */
2152 cd_cmd = I40E_TX_CTX_DESC_TSO;
2153 cd_tso_len = skb->len - *hdr_len;
2154 cd_mss = skb_shinfo(skb)->gso_size;
2155 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2156 ((u64)cd_tso_len <<
2157 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2158 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2159 return 1;
2160 }
2161
2162 /**
2163 * i40e_tsyn - set up the tsyn context descriptor
2164 * @tx_ring: ptr to the ring to send
2165 * @skb: ptr to the skb we're sending
2166 * @tx_flags: the collected send information
2167 *
2168 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2169 **/
2170 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2171 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2172 {
2173 struct i40e_pf *pf;
2174
2175 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2176 return 0;
2177
2178 /* Tx timestamps cannot be sampled when doing TSO */
2179 if (tx_flags & I40E_TX_FLAGS_TSO)
2180 return 0;
2181
2182 /* only timestamp the outbound packet if the user has requested it and
2183 * we are not already transmitting a packet to be timestamped
2184 */
2185 pf = i40e_netdev_to_pf(tx_ring->netdev);
2186 if (!(pf->flags & I40E_FLAG_PTP))
2187 return 0;
2188
2189 if (pf->ptp_tx &&
2190 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
2191 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2192 pf->ptp_tx_skb = skb_get(skb);
2193 } else {
2194 return 0;
2195 }
2196
2197 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2198 I40E_TXD_CTX_QW1_CMD_SHIFT;
2199
2200 return 1;
2201 }
2202
2203 /**
2204 * i40e_tx_enable_csum - Enable Tx checksum offloads
2205 * @skb: send buffer
2206 * @tx_flags: Tx flags currently set
2207 * @td_cmd: Tx descriptor command bits to set
2208 * @td_offset: Tx descriptor header offsets to set
2209 * @cd_tunneling: ptr to context desc bits
2210 **/
2211 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
2212 u32 *td_cmd, u32 *td_offset,
2213 struct i40e_ring *tx_ring,
2214 u32 *cd_tunneling)
2215 {
2216 struct ipv6hdr *this_ipv6_hdr;
2217 unsigned int this_tcp_hdrlen;
2218 struct iphdr *this_ip_hdr;
2219 u32 network_hdr_len;
2220 u8 l4_hdr = 0;
2221 u32 l4_tunnel = 0;
2222
2223 if (skb->encapsulation) {
2224 switch (ip_hdr(skb)->protocol) {
2225 case IPPROTO_UDP:
2226 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
2227 break;
2228 default:
2229 return;
2230 }
2231 network_hdr_len = skb_inner_network_header_len(skb);
2232 this_ip_hdr = inner_ip_hdr(skb);
2233 this_ipv6_hdr = inner_ipv6_hdr(skb);
2234 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
2235
2236 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2237
2238 if (tx_flags & I40E_TX_FLAGS_TSO) {
2239 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
2240 ip_hdr(skb)->check = 0;
2241 } else {
2242 *cd_tunneling |=
2243 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2244 }
2245 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
2246 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
2247 if (tx_flags & I40E_TX_FLAGS_TSO)
2248 ip_hdr(skb)->check = 0;
2249 }
2250
2251 /* Now set the ctx descriptor fields */
2252 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
2253 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
2254 l4_tunnel |
2255 ((skb_inner_network_offset(skb) -
2256 skb_transport_offset(skb)) >> 1) <<
2257 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
2258 if (this_ip_hdr->version == 6) {
2259 tx_flags &= ~I40E_TX_FLAGS_IPV4;
2260 tx_flags |= I40E_TX_FLAGS_IPV6;
2261 }
2262 } else {
2263 network_hdr_len = skb_network_header_len(skb);
2264 this_ip_hdr = ip_hdr(skb);
2265 this_ipv6_hdr = ipv6_hdr(skb);
2266 this_tcp_hdrlen = tcp_hdrlen(skb);
2267 }
2268
2269 /* Enable IP checksum offloads */
2270 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2271 l4_hdr = this_ip_hdr->protocol;
2272 /* the stack computes the IP header already, the only time we
2273 * need the hardware to recompute it is in the case of TSO.
2274 */
2275 if (tx_flags & I40E_TX_FLAGS_TSO) {
2276 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
2277 this_ip_hdr->check = 0;
2278 } else {
2279 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
2280 }
2281 /* Now set the td_offset for IP header length */
2282 *td_offset = (network_hdr_len >> 2) <<
2283 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2284 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
2285 l4_hdr = this_ipv6_hdr->nexthdr;
2286 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2287 /* Now set the td_offset for IP header length */
2288 *td_offset = (network_hdr_len >> 2) <<
2289 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2290 }
2291 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
2292 *td_offset |= (skb_network_offset(skb) >> 1) <<
2293 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2294
2295 /* Enable L4 checksum offloads */
2296 switch (l4_hdr) {
2297 case IPPROTO_TCP:
2298 /* enable checksum offloads */
2299 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2300 *td_offset |= (this_tcp_hdrlen >> 2) <<
2301 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2302 break;
2303 case IPPROTO_SCTP:
2304 /* enable SCTP checksum offload */
2305 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2306 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
2307 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2308 break;
2309 case IPPROTO_UDP:
2310 /* enable UDP checksum offload */
2311 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2312 *td_offset |= (sizeof(struct udphdr) >> 2) <<
2313 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2314 break;
2315 default:
2316 break;
2317 }
2318 }
2319
2320 /**
2321 * i40e_create_tx_ctx Build the Tx context descriptor
2322 * @tx_ring: ring to create the descriptor on
2323 * @cd_type_cmd_tso_mss: Quad Word 1
2324 * @cd_tunneling: Quad Word 0 - bits 0-31
2325 * @cd_l2tag2: Quad Word 0 - bits 32-63
2326 **/
2327 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2328 const u64 cd_type_cmd_tso_mss,
2329 const u32 cd_tunneling, const u32 cd_l2tag2)
2330 {
2331 struct i40e_tx_context_desc *context_desc;
2332 int i = tx_ring->next_to_use;
2333
2334 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2335 !cd_tunneling && !cd_l2tag2)
2336 return;
2337
2338 /* grab the next descriptor */
2339 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2340
2341 i++;
2342 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2343
2344 /* cpu_to_le32 and assign to struct fields */
2345 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2346 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2347 context_desc->rsvd = cpu_to_le16(0);
2348 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2349 }
2350
2351 /**
2352 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2353 * @tx_ring: the ring to be checked
2354 * @size: the size buffer we want to assure is available
2355 *
2356 * Returns -EBUSY if a stop is needed, else 0
2357 **/
2358 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2359 {
2360 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2361 /* Memory barrier before checking head and tail */
2362 smp_mb();
2363
2364 /* Check again in a case another CPU has just made room available. */
2365 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2366 return -EBUSY;
2367
2368 /* A reprieve! - use start_queue because it doesn't call schedule */
2369 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2370 ++tx_ring->tx_stats.restart_queue;
2371 return 0;
2372 }
2373
2374 /**
2375 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2376 * @tx_ring: the ring to be checked
2377 * @size: the size buffer we want to assure is available
2378 *
2379 * Returns 0 if stop is not needed
2380 **/
2381 #ifdef I40E_FCOE
2382 int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2383 #else
2384 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2385 #endif
2386 {
2387 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2388 return 0;
2389 return __i40e_maybe_stop_tx(tx_ring, size);
2390 }
2391
2392 /**
2393 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
2394 * @skb: send buffer
2395 * @tx_flags: collected send information
2396 * @hdr_len: size of the packet header
2397 *
2398 * Note: Our HW can't scatter-gather more than 8 fragments to build
2399 * a packet on the wire and so we need to figure out the cases where we
2400 * need to linearize the skb.
2401 **/
2402 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags,
2403 const u8 hdr_len)
2404 {
2405 struct skb_frag_struct *frag;
2406 bool linearize = false;
2407 unsigned int size = 0;
2408 u16 num_frags;
2409 u16 gso_segs;
2410
2411 num_frags = skb_shinfo(skb)->nr_frags;
2412 gso_segs = skb_shinfo(skb)->gso_segs;
2413
2414 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
2415 u16 j = 1;
2416
2417 if (num_frags < (I40E_MAX_BUFFER_TXD))
2418 goto linearize_chk_done;
2419 /* try the simple math, if we have too many frags per segment */
2420 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
2421 I40E_MAX_BUFFER_TXD) {
2422 linearize = true;
2423 goto linearize_chk_done;
2424 }
2425 frag = &skb_shinfo(skb)->frags[0];
2426 size = hdr_len;
2427 /* we might still have more fragments per segment */
2428 do {
2429 size += skb_frag_size(frag);
2430 frag++; j++;
2431 if (j == I40E_MAX_BUFFER_TXD) {
2432 if (size < skb_shinfo(skb)->gso_size) {
2433 linearize = true;
2434 break;
2435 }
2436 j = 1;
2437 size -= skb_shinfo(skb)->gso_size;
2438 if (size)
2439 j++;
2440 size += hdr_len;
2441 }
2442 num_frags--;
2443 } while (num_frags);
2444 } else {
2445 if (num_frags >= I40E_MAX_BUFFER_TXD)
2446 linearize = true;
2447 }
2448
2449 linearize_chk_done:
2450 return linearize;
2451 }
2452
2453 /**
2454 * i40e_tx_map - Build the Tx descriptor
2455 * @tx_ring: ring to send buffer on
2456 * @skb: send buffer
2457 * @first: first buffer info buffer to use
2458 * @tx_flags: collected send information
2459 * @hdr_len: size of the packet header
2460 * @td_cmd: the command field in the descriptor
2461 * @td_offset: offset for checksum or crc
2462 **/
2463 #ifdef I40E_FCOE
2464 void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2465 struct i40e_tx_buffer *first, u32 tx_flags,
2466 const u8 hdr_len, u32 td_cmd, u32 td_offset)
2467 #else
2468 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2469 struct i40e_tx_buffer *first, u32 tx_flags,
2470 const u8 hdr_len, u32 td_cmd, u32 td_offset)
2471 #endif
2472 {
2473 unsigned int data_len = skb->data_len;
2474 unsigned int size = skb_headlen(skb);
2475 struct skb_frag_struct *frag;
2476 struct i40e_tx_buffer *tx_bi;
2477 struct i40e_tx_desc *tx_desc;
2478 u16 i = tx_ring->next_to_use;
2479 u32 td_tag = 0;
2480 dma_addr_t dma;
2481 u16 gso_segs;
2482
2483 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2484 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2485 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2486 I40E_TX_FLAGS_VLAN_SHIFT;
2487 }
2488
2489 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2490 gso_segs = skb_shinfo(skb)->gso_segs;
2491 else
2492 gso_segs = 1;
2493
2494 /* multiply data chunks by size of headers */
2495 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2496 first->gso_segs = gso_segs;
2497 first->skb = skb;
2498 first->tx_flags = tx_flags;
2499
2500 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2501
2502 tx_desc = I40E_TX_DESC(tx_ring, i);
2503 tx_bi = first;
2504
2505 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2506 if (dma_mapping_error(tx_ring->dev, dma))
2507 goto dma_error;
2508
2509 /* record length, and DMA address */
2510 dma_unmap_len_set(tx_bi, len, size);
2511 dma_unmap_addr_set(tx_bi, dma, dma);
2512
2513 tx_desc->buffer_addr = cpu_to_le64(dma);
2514
2515 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
2516 tx_desc->cmd_type_offset_bsz =
2517 build_ctob(td_cmd, td_offset,
2518 I40E_MAX_DATA_PER_TXD, td_tag);
2519
2520 tx_desc++;
2521 i++;
2522 if (i == tx_ring->count) {
2523 tx_desc = I40E_TX_DESC(tx_ring, 0);
2524 i = 0;
2525 }
2526
2527 dma += I40E_MAX_DATA_PER_TXD;
2528 size -= I40E_MAX_DATA_PER_TXD;
2529
2530 tx_desc->buffer_addr = cpu_to_le64(dma);
2531 }
2532
2533 if (likely(!data_len))
2534 break;
2535
2536 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2537 size, td_tag);
2538
2539 tx_desc++;
2540 i++;
2541 if (i == tx_ring->count) {
2542 tx_desc = I40E_TX_DESC(tx_ring, 0);
2543 i = 0;
2544 }
2545
2546 size = skb_frag_size(frag);
2547 data_len -= size;
2548
2549 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2550 DMA_TO_DEVICE);
2551
2552 tx_bi = &tx_ring->tx_bi[i];
2553 }
2554
2555 /* Place RS bit on last descriptor of any packet that spans across the
2556 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
2557 */
2558 if (((i & WB_STRIDE) != WB_STRIDE) &&
2559 (first <= &tx_ring->tx_bi[i]) &&
2560 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
2561 tx_desc->cmd_type_offset_bsz =
2562 build_ctob(td_cmd, td_offset, size, td_tag) |
2563 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
2564 I40E_TXD_QW1_CMD_SHIFT);
2565 } else {
2566 tx_desc->cmd_type_offset_bsz =
2567 build_ctob(td_cmd, td_offset, size, td_tag) |
2568 cpu_to_le64((u64)I40E_TXD_CMD <<
2569 I40E_TXD_QW1_CMD_SHIFT);
2570 }
2571
2572 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2573 tx_ring->queue_index),
2574 first->bytecount);
2575
2576 /* set the timestamp */
2577 first->time_stamp = jiffies;
2578
2579 /* Force memory writes to complete before letting h/w
2580 * know there are new descriptors to fetch. (Only
2581 * applicable for weak-ordered memory model archs,
2582 * such as IA-64).
2583 */
2584 wmb();
2585
2586 /* set next_to_watch value indicating a packet is present */
2587 first->next_to_watch = tx_desc;
2588
2589 i++;
2590 if (i == tx_ring->count)
2591 i = 0;
2592
2593 tx_ring->next_to_use = i;
2594
2595 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2596 /* notify HW of packet */
2597 if (!skb->xmit_more ||
2598 netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2599 tx_ring->queue_index)))
2600 writel(i, tx_ring->tail);
2601
2602 return;
2603
2604 dma_error:
2605 dev_info(tx_ring->dev, "TX DMA map failed\n");
2606
2607 /* clear dma mappings for failed tx_bi map */
2608 for (;;) {
2609 tx_bi = &tx_ring->tx_bi[i];
2610 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2611 if (tx_bi == first)
2612 break;
2613 if (i == 0)
2614 i = tx_ring->count;
2615 i--;
2616 }
2617
2618 tx_ring->next_to_use = i;
2619 }
2620
2621 /**
2622 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2623 * @skb: send buffer
2624 * @tx_ring: ring to send buffer on
2625 *
2626 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2627 * there is not enough descriptors available in this ring since we need at least
2628 * one descriptor.
2629 **/
2630 #ifdef I40E_FCOE
2631 int i40e_xmit_descriptor_count(struct sk_buff *skb,
2632 struct i40e_ring *tx_ring)
2633 #else
2634 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
2635 struct i40e_ring *tx_ring)
2636 #endif
2637 {
2638 unsigned int f;
2639 int count = 0;
2640
2641 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2642 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2643 * + 4 desc gap to avoid the cache line where head is,
2644 * + 1 desc for context descriptor,
2645 * otherwise try next time
2646 */
2647 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2648 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2649
2650 count += TXD_USE_COUNT(skb_headlen(skb));
2651 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2652 tx_ring->tx_stats.tx_busy++;
2653 return 0;
2654 }
2655 return count;
2656 }
2657
2658 /**
2659 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2660 * @skb: send buffer
2661 * @tx_ring: ring to send buffer on
2662 *
2663 * Returns NETDEV_TX_OK if sent, else an error code
2664 **/
2665 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2666 struct i40e_ring *tx_ring)
2667 {
2668 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2669 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2670 struct i40e_tx_buffer *first;
2671 u32 td_offset = 0;
2672 u32 tx_flags = 0;
2673 __be16 protocol;
2674 u32 td_cmd = 0;
2675 u8 hdr_len = 0;
2676 int tsyn;
2677 int tso;
2678 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2679 return NETDEV_TX_BUSY;
2680
2681 /* prepare the xmit flags */
2682 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2683 goto out_drop;
2684
2685 /* obtain protocol of skb */
2686 protocol = vlan_get_protocol(skb);
2687
2688 /* record the location of the first descriptor for this packet */
2689 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2690
2691 /* setup IPv4/IPv6 offloads */
2692 if (protocol == htons(ETH_P_IP))
2693 tx_flags |= I40E_TX_FLAGS_IPV4;
2694 else if (protocol == htons(ETH_P_IPV6))
2695 tx_flags |= I40E_TX_FLAGS_IPV6;
2696
2697 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
2698 &cd_type_cmd_tso_mss, &cd_tunneling);
2699
2700 if (tso < 0)
2701 goto out_drop;
2702 else if (tso)
2703 tx_flags |= I40E_TX_FLAGS_TSO;
2704
2705 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2706
2707 if (tsyn)
2708 tx_flags |= I40E_TX_FLAGS_TSYN;
2709
2710 if (i40e_chk_linearize(skb, tx_flags, hdr_len))
2711 if (skb_linearize(skb))
2712 goto out_drop;
2713
2714 skb_tx_timestamp(skb);
2715
2716 /* always enable CRC insertion offload */
2717 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2718
2719 /* Always offload the checksum, since it's in the data descriptor */
2720 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2721 tx_flags |= I40E_TX_FLAGS_CSUM;
2722
2723 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
2724 tx_ring, &cd_tunneling);
2725 }
2726
2727 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2728 cd_tunneling, cd_l2tag2);
2729
2730 /* Add Flow Director ATR if it's enabled.
2731 *
2732 * NOTE: this must always be directly before the data descriptor.
2733 */
2734 i40e_atr(tx_ring, skb, tx_flags, protocol);
2735
2736 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2737 td_cmd, td_offset);
2738
2739 return NETDEV_TX_OK;
2740
2741 out_drop:
2742 dev_kfree_skb_any(skb);
2743 return NETDEV_TX_OK;
2744 }
2745
2746 /**
2747 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2748 * @skb: send buffer
2749 * @netdev: network interface device structure
2750 *
2751 * Returns NETDEV_TX_OK if sent, else an error code
2752 **/
2753 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2754 {
2755 struct i40e_netdev_priv *np = netdev_priv(netdev);
2756 struct i40e_vsi *vsi = np->vsi;
2757 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
2758
2759 /* hardware can't handle really short frames, hardware padding works
2760 * beyond this point
2761 */
2762 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2763 return NETDEV_TX_OK;
2764
2765 return i40e_xmit_frame_ring(skb, tx_ring);
2766 }
Linux kernel - Deliverables
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