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i40e/i40evf: Add set_fc and init of FC settings
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_type.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36
37 /* Device IDs */
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_VF 0x154C
47 #define I40E_DEV_ID_VF_HV 0x1571
48
49 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
50 (d) == I40E_DEV_ID_QSFP_B || \
51 (d) == I40E_DEV_ID_QSFP_C)
52
53 /* I40E_MASK is a macro used on 32 bit registers */
54 #define I40E_MASK(mask, shift) (mask << shift)
55
56 #define I40E_MAX_VSI_QP 16
57 #define I40E_MAX_VF_VSI 3
58 #define I40E_MAX_CHAINED_RX_BUFFERS 5
59 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
60
61 /* Max default timeout in ms, */
62 #define I40E_MAX_NVM_TIMEOUT 18000
63
64 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
65 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
66
67 /* forward declaration */
68 struct i40e_hw;
69 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
70
71 /* Data type manipulation macros. */
72
73 #define I40E_DESC_UNUSED(R) \
74 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
75 (R)->next_to_clean - (R)->next_to_use - 1)
76
77 /* bitfields for Tx queue mapping in QTX_CTL */
78 #define I40E_QTX_CTL_VF_QUEUE 0x0
79 #define I40E_QTX_CTL_VM_QUEUE 0x1
80 #define I40E_QTX_CTL_PF_QUEUE 0x2
81
82 /* debug masks - set these bits in hw->debug_mask to control output */
83 enum i40e_debug_mask {
84 I40E_DEBUG_INIT = 0x00000001,
85 I40E_DEBUG_RELEASE = 0x00000002,
86
87 I40E_DEBUG_LINK = 0x00000010,
88 I40E_DEBUG_PHY = 0x00000020,
89 I40E_DEBUG_HMC = 0x00000040,
90 I40E_DEBUG_NVM = 0x00000080,
91 I40E_DEBUG_LAN = 0x00000100,
92 I40E_DEBUG_FLOW = 0x00000200,
93 I40E_DEBUG_DCB = 0x00000400,
94 I40E_DEBUG_DIAG = 0x00000800,
95 I40E_DEBUG_FD = 0x00001000,
96
97 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
98 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
99 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
100 I40E_DEBUG_AQ_COMMAND = 0x06000000,
101 I40E_DEBUG_AQ = 0x0F000000,
102
103 I40E_DEBUG_USER = 0xF0000000,
104
105 I40E_DEBUG_ALL = 0xFFFFFFFF
106 };
107
108 /* These are structs for managing the hardware information and the operations.
109 * The structures of function pointers are filled out at init time when we
110 * know for sure exactly which hardware we're working with. This gives us the
111 * flexibility of using the same main driver code but adapting to slightly
112 * different hardware needs as new parts are developed. For this architecture,
113 * the Firmware and AdminQ are intended to insulate the driver from most of the
114 * future changes, but these structures will also do part of the job.
115 */
116 enum i40e_mac_type {
117 I40E_MAC_UNKNOWN = 0,
118 I40E_MAC_X710,
119 I40E_MAC_XL710,
120 I40E_MAC_VF,
121 I40E_MAC_GENERIC,
122 };
123
124 enum i40e_media_type {
125 I40E_MEDIA_TYPE_UNKNOWN = 0,
126 I40E_MEDIA_TYPE_FIBER,
127 I40E_MEDIA_TYPE_BASET,
128 I40E_MEDIA_TYPE_BACKPLANE,
129 I40E_MEDIA_TYPE_CX4,
130 I40E_MEDIA_TYPE_DA,
131 I40E_MEDIA_TYPE_VIRTUAL
132 };
133
134 enum i40e_fc_mode {
135 I40E_FC_NONE = 0,
136 I40E_FC_RX_PAUSE,
137 I40E_FC_TX_PAUSE,
138 I40E_FC_FULL,
139 I40E_FC_PFC,
140 I40E_FC_DEFAULT
141 };
142
143 enum i40e_set_fc_aq_failures {
144 I40E_SET_FC_AQ_FAIL_NONE = 0,
145 I40E_SET_FC_AQ_FAIL_GET = 1,
146 I40E_SET_FC_AQ_FAIL_SET = 2,
147 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
148 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
149 };
150
151 enum i40e_vsi_type {
152 I40E_VSI_MAIN = 0,
153 I40E_VSI_VMDQ1,
154 I40E_VSI_VMDQ2,
155 I40E_VSI_CTRL,
156 I40E_VSI_FCOE,
157 I40E_VSI_MIRROR,
158 I40E_VSI_SRIOV,
159 I40E_VSI_FDIR,
160 I40E_VSI_TYPE_UNKNOWN
161 };
162
163 enum i40e_queue_type {
164 I40E_QUEUE_TYPE_RX = 0,
165 I40E_QUEUE_TYPE_TX,
166 I40E_QUEUE_TYPE_PE_CEQ,
167 I40E_QUEUE_TYPE_UNKNOWN
168 };
169
170 struct i40e_link_status {
171 enum i40e_aq_phy_type phy_type;
172 enum i40e_aq_link_speed link_speed;
173 u8 link_info;
174 u8 an_info;
175 u8 ext_info;
176 u8 loopback;
177 bool an_enabled;
178 /* is Link Status Event notification to SW enabled */
179 bool lse_enable;
180 u16 max_frame_size;
181 bool crc_enable;
182 u8 pacing;
183 };
184
185 struct i40e_phy_info {
186 struct i40e_link_status link_info;
187 struct i40e_link_status link_info_old;
188 u32 autoneg_advertised;
189 u32 phy_id;
190 u32 module_type;
191 bool get_link_info;
192 enum i40e_media_type media_type;
193 };
194
195 #define I40E_HW_CAP_MAX_GPIO 30
196 /* Capabilities of a PF or a VF or the whole device */
197 struct i40e_hw_capabilities {
198 u32 switch_mode;
199 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
200 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
201 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
202
203 u32 management_mode;
204 u32 npar_enable;
205 u32 os2bmc;
206 u32 valid_functions;
207 bool sr_iov_1_1;
208 bool vmdq;
209 bool evb_802_1_qbg; /* Edge Virtual Bridging */
210 bool evb_802_1_qbh; /* Bridge Port Extension */
211 bool dcb;
212 bool fcoe;
213 bool mfp_mode_1;
214 bool mgmt_cem;
215 bool ieee_1588;
216 bool iwarp;
217 bool fd;
218 u32 fd_filters_guaranteed;
219 u32 fd_filters_best_effort;
220 bool rss;
221 u32 rss_table_size;
222 u32 rss_table_entry_width;
223 bool led[I40E_HW_CAP_MAX_GPIO];
224 bool sdp[I40E_HW_CAP_MAX_GPIO];
225 u32 nvm_image_type;
226 u32 num_flow_director_filters;
227 u32 num_vfs;
228 u32 vf_base_id;
229 u32 num_vsis;
230 u32 num_rx_qp;
231 u32 num_tx_qp;
232 u32 base_queue;
233 u32 num_msix_vectors;
234 u32 num_msix_vectors_vf;
235 u32 led_pin_num;
236 u32 sdp_pin_num;
237 u32 mdio_port_num;
238 u32 mdio_port_mode;
239 u8 rx_buf_chain_len;
240 u32 enabled_tcmap;
241 u32 maxtc;
242 };
243
244 struct i40e_mac_info {
245 enum i40e_mac_type type;
246 u8 addr[ETH_ALEN];
247 u8 perm_addr[ETH_ALEN];
248 u8 san_addr[ETH_ALEN];
249 u16 max_fcoeq;
250 };
251
252 enum i40e_aq_resources_ids {
253 I40E_NVM_RESOURCE_ID = 1
254 };
255
256 enum i40e_aq_resource_access_type {
257 I40E_RESOURCE_READ = 1,
258 I40E_RESOURCE_WRITE
259 };
260
261 struct i40e_nvm_info {
262 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
263 u64 hw_semaphore_wait; /* - || - */
264 u32 timeout; /* [ms] */
265 u16 sr_size; /* Shadow RAM size in words */
266 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
267 u16 version; /* NVM package version */
268 u32 eetrack; /* NVM data version */
269 };
270
271 /* PCI bus types */
272 enum i40e_bus_type {
273 i40e_bus_type_unknown = 0,
274 i40e_bus_type_pci,
275 i40e_bus_type_pcix,
276 i40e_bus_type_pci_express,
277 i40e_bus_type_reserved
278 };
279
280 /* PCI bus speeds */
281 enum i40e_bus_speed {
282 i40e_bus_speed_unknown = 0,
283 i40e_bus_speed_33 = 33,
284 i40e_bus_speed_66 = 66,
285 i40e_bus_speed_100 = 100,
286 i40e_bus_speed_120 = 120,
287 i40e_bus_speed_133 = 133,
288 i40e_bus_speed_2500 = 2500,
289 i40e_bus_speed_5000 = 5000,
290 i40e_bus_speed_8000 = 8000,
291 i40e_bus_speed_reserved
292 };
293
294 /* PCI bus widths */
295 enum i40e_bus_width {
296 i40e_bus_width_unknown = 0,
297 i40e_bus_width_pcie_x1 = 1,
298 i40e_bus_width_pcie_x2 = 2,
299 i40e_bus_width_pcie_x4 = 4,
300 i40e_bus_width_pcie_x8 = 8,
301 i40e_bus_width_32 = 32,
302 i40e_bus_width_64 = 64,
303 i40e_bus_width_reserved
304 };
305
306 /* Bus parameters */
307 struct i40e_bus_info {
308 enum i40e_bus_speed speed;
309 enum i40e_bus_width width;
310 enum i40e_bus_type type;
311
312 u16 func;
313 u16 device;
314 u16 lan_id;
315 };
316
317 /* Flow control (FC) parameters */
318 struct i40e_fc_info {
319 enum i40e_fc_mode current_mode; /* FC mode in effect */
320 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
321 };
322
323 #define I40E_MAX_TRAFFIC_CLASS 8
324 #define I40E_MAX_USER_PRIORITY 8
325 #define I40E_DCBX_MAX_APPS 32
326 #define I40E_LLDPDU_SIZE 1500
327
328 /* IEEE 802.1Qaz ETS Configuration data */
329 struct i40e_ieee_ets_config {
330 u8 willing;
331 u8 cbs;
332 u8 maxtcs;
333 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
334 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
335 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
336 };
337
338 /* IEEE 802.1Qaz ETS Recommendation data */
339 struct i40e_ieee_ets_recommend {
340 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
341 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
342 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
343 };
344
345 /* IEEE 802.1Qaz PFC Configuration data */
346 struct i40e_ieee_pfc_config {
347 u8 willing;
348 u8 mbc;
349 u8 pfccap;
350 u8 pfcenable;
351 };
352
353 /* IEEE 802.1Qaz Application Priority data */
354 struct i40e_ieee_app_priority_table {
355 u8 priority;
356 u8 selector;
357 u16 protocolid;
358 };
359
360 struct i40e_dcbx_config {
361 u32 numapps;
362 struct i40e_ieee_ets_config etscfg;
363 struct i40e_ieee_ets_recommend etsrec;
364 struct i40e_ieee_pfc_config pfc;
365 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
366 };
367
368 /* Port hardware description */
369 struct i40e_hw {
370 u8 __iomem *hw_addr;
371 void *back;
372
373 /* function pointer structs */
374 struct i40e_phy_info phy;
375 struct i40e_mac_info mac;
376 struct i40e_bus_info bus;
377 struct i40e_nvm_info nvm;
378 struct i40e_fc_info fc;
379
380 /* pci info */
381 u16 device_id;
382 u16 vendor_id;
383 u16 subsystem_device_id;
384 u16 subsystem_vendor_id;
385 u8 revision_id;
386 u8 port;
387 bool adapter_stopped;
388
389 /* capabilities for entire device and PCI func */
390 struct i40e_hw_capabilities dev_caps;
391 struct i40e_hw_capabilities func_caps;
392
393 /* Flow Director shared filter space */
394 u16 fdir_shared_filter_count;
395
396 /* device profile info */
397 u8 pf_id;
398 u16 main_vsi_seid;
399
400 /* Closest numa node to the device */
401 u16 numa_node;
402
403 /* Admin Queue info */
404 struct i40e_adminq_info aq;
405
406 /* HMC info */
407 struct i40e_hmc_info hmc; /* HMC info struct */
408
409 /* LLDP/DCBX Status */
410 u16 dcbx_status;
411
412 /* DCBX info */
413 struct i40e_dcbx_config local_dcbx_config;
414 struct i40e_dcbx_config remote_dcbx_config;
415
416 /* debug mask */
417 u32 debug_mask;
418 };
419
420 struct i40e_driver_version {
421 u8 major_version;
422 u8 minor_version;
423 u8 build_version;
424 u8 subbuild_version;
425 u8 driver_string[32];
426 };
427
428 /* RX Descriptors */
429 union i40e_16byte_rx_desc {
430 struct {
431 __le64 pkt_addr; /* Packet buffer address */
432 __le64 hdr_addr; /* Header buffer address */
433 } read;
434 struct {
435 struct {
436 struct {
437 union {
438 __le16 mirroring_status;
439 __le16 fcoe_ctx_id;
440 } mirr_fcoe;
441 __le16 l2tag1;
442 } lo_dword;
443 union {
444 __le32 rss; /* RSS Hash */
445 __le32 fd_id; /* Flow director filter id */
446 __le32 fcoe_param; /* FCoE DDP Context id */
447 } hi_dword;
448 } qword0;
449 struct {
450 /* ext status/error/pktype/length */
451 __le64 status_error_len;
452 } qword1;
453 } wb; /* writeback */
454 };
455
456 union i40e_32byte_rx_desc {
457 struct {
458 __le64 pkt_addr; /* Packet buffer address */
459 __le64 hdr_addr; /* Header buffer address */
460 /* bit 0 of hdr_buffer_addr is DD bit */
461 __le64 rsvd1;
462 __le64 rsvd2;
463 } read;
464 struct {
465 struct {
466 struct {
467 union {
468 __le16 mirroring_status;
469 __le16 fcoe_ctx_id;
470 } mirr_fcoe;
471 __le16 l2tag1;
472 } lo_dword;
473 union {
474 __le32 rss; /* RSS Hash */
475 __le32 fcoe_param; /* FCoE DDP Context id */
476 /* Flow director filter id in case of
477 * Programming status desc WB
478 */
479 __le32 fd_id;
480 } hi_dword;
481 } qword0;
482 struct {
483 /* status/error/pktype/length */
484 __le64 status_error_len;
485 } qword1;
486 struct {
487 __le16 ext_status; /* extended status */
488 __le16 rsvd;
489 __le16 l2tag2_1;
490 __le16 l2tag2_2;
491 } qword2;
492 struct {
493 union {
494 __le32 flex_bytes_lo;
495 __le32 pe_status;
496 } lo_dword;
497 union {
498 __le32 flex_bytes_hi;
499 __le32 fd_id;
500 } hi_dword;
501 } qword3;
502 } wb; /* writeback */
503 };
504
505 enum i40e_rx_desc_status_bits {
506 /* Note: These are predefined bit offsets */
507 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
508 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
509 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
510 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
511 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
512 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
513 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
514 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
515 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
516 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
517 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
518 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
519 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
520 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
521 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
522 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
523 };
524
525 #define I40E_RXD_QW1_STATUS_SHIFT 0
526 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
527 << I40E_RXD_QW1_STATUS_SHIFT)
528
529 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
530 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
531 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
532
533 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
534 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
535 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
536
537 enum i40e_rx_desc_fltstat_values {
538 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
539 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
540 I40E_RX_DESC_FLTSTAT_RSV = 2,
541 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
542 };
543
544 #define I40E_RXD_QW1_ERROR_SHIFT 19
545 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
546
547 enum i40e_rx_desc_error_bits {
548 /* Note: These are predefined bit offsets */
549 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
550 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
551 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
552 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
553 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
554 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
555 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
556 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
557 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
558 };
559
560 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
561 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
562 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
563 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
564 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
565 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
566 };
567
568 #define I40E_RXD_QW1_PTYPE_SHIFT 30
569 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
570
571 /* Packet type non-ip values */
572 enum i40e_rx_l2_ptype {
573 I40E_RX_PTYPE_L2_RESERVED = 0,
574 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
575 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
576 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
577 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
578 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
579 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
580 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
581 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
582 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
583 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
584 I40E_RX_PTYPE_L2_ARP = 11,
585 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
586 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
587 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
588 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
589 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
590 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
591 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
592 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
593 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
594 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
595 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
596 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
597 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
598 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
599 };
600
601 struct i40e_rx_ptype_decoded {
602 u32 ptype:8;
603 u32 known:1;
604 u32 outer_ip:1;
605 u32 outer_ip_ver:1;
606 u32 outer_frag:1;
607 u32 tunnel_type:3;
608 u32 tunnel_end_prot:2;
609 u32 tunnel_end_frag:1;
610 u32 inner_prot:4;
611 u32 payload_layer:3;
612 };
613
614 enum i40e_rx_ptype_outer_ip {
615 I40E_RX_PTYPE_OUTER_L2 = 0,
616 I40E_RX_PTYPE_OUTER_IP = 1
617 };
618
619 enum i40e_rx_ptype_outer_ip_ver {
620 I40E_RX_PTYPE_OUTER_NONE = 0,
621 I40E_RX_PTYPE_OUTER_IPV4 = 0,
622 I40E_RX_PTYPE_OUTER_IPV6 = 1
623 };
624
625 enum i40e_rx_ptype_outer_fragmented {
626 I40E_RX_PTYPE_NOT_FRAG = 0,
627 I40E_RX_PTYPE_FRAG = 1
628 };
629
630 enum i40e_rx_ptype_tunnel_type {
631 I40E_RX_PTYPE_TUNNEL_NONE = 0,
632 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
633 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
634 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
635 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
636 };
637
638 enum i40e_rx_ptype_tunnel_end_prot {
639 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
640 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
641 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
642 };
643
644 enum i40e_rx_ptype_inner_prot {
645 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
646 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
647 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
648 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
649 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
650 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
651 };
652
653 enum i40e_rx_ptype_payload_layer {
654 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
655 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
656 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
657 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
658 };
659
660 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
661 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
662 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
663
664 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
665 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
666 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
667
668 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
669 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
670 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
671
672 enum i40e_rx_desc_ext_status_bits {
673 /* Note: These are predefined bit offsets */
674 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
675 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
676 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
677 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
678 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
679 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
680 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
681 };
682
683 enum i40e_rx_desc_pe_status_bits {
684 /* Note: These are predefined bit offsets */
685 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
686 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
687 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
688 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
689 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
690 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
691 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
692 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
693 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
694 };
695
696 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
697 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
698
699 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
700 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
701 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
702
703 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
704 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
705 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
706
707 enum i40e_rx_prog_status_desc_status_bits {
708 /* Note: These are predefined bit offsets */
709 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
710 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
711 };
712
713 enum i40e_rx_prog_status_desc_prog_id_masks {
714 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
715 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
716 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
717 };
718
719 enum i40e_rx_prog_status_desc_error_bits {
720 /* Note: These are predefined bit offsets */
721 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
722 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
723 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
724 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
725 };
726
727 /* TX Descriptor */
728 struct i40e_tx_desc {
729 __le64 buffer_addr; /* Address of descriptor's data buf */
730 __le64 cmd_type_offset_bsz;
731 };
732
733 #define I40E_TXD_QW1_DTYPE_SHIFT 0
734 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
735
736 enum i40e_tx_desc_dtype_value {
737 I40E_TX_DESC_DTYPE_DATA = 0x0,
738 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
739 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
740 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
741 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
742 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
743 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
744 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
745 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
746 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
747 };
748
749 #define I40E_TXD_QW1_CMD_SHIFT 4
750 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
751
752 enum i40e_tx_desc_cmd_bits {
753 I40E_TX_DESC_CMD_EOP = 0x0001,
754 I40E_TX_DESC_CMD_RS = 0x0002,
755 I40E_TX_DESC_CMD_ICRC = 0x0004,
756 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
757 I40E_TX_DESC_CMD_DUMMY = 0x0010,
758 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
759 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
760 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
761 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
762 I40E_TX_DESC_CMD_FCOET = 0x0080,
763 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
764 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
765 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
766 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
767 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
768 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
769 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
770 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
771 };
772
773 #define I40E_TXD_QW1_OFFSET_SHIFT 16
774 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
775 I40E_TXD_QW1_OFFSET_SHIFT)
776
777 enum i40e_tx_desc_length_fields {
778 /* Note: These are predefined bit offsets */
779 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
780 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
781 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
782 };
783
784 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
785 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
786 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
787
788 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
789 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
790
791 /* Context descriptors */
792 struct i40e_tx_context_desc {
793 __le32 tunneling_params;
794 __le16 l2tag2;
795 __le16 rsvd;
796 __le64 type_cmd_tso_mss;
797 };
798
799 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
800 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
801
802 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
803 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
804
805 enum i40e_tx_ctx_desc_cmd_bits {
806 I40E_TX_CTX_DESC_TSO = 0x01,
807 I40E_TX_CTX_DESC_TSYN = 0x02,
808 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
809 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
810 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
811 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
812 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
813 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
814 I40E_TX_CTX_DESC_SWPE = 0x40
815 };
816
817 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
818 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
819 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
820
821 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
822 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
823 I40E_TXD_CTX_QW1_MSS_SHIFT)
824
825 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
826 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
827
828 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
829 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
830 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
831
832 enum i40e_tx_ctx_desc_eipt_offload {
833 I40E_TX_CTX_EXT_IP_NONE = 0x0,
834 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
835 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
836 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
837 };
838
839 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
840 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
841 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
842
843 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
844 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
845
846 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
847 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
848
849 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
850 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
851 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
852
853 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
854
855 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
856 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
857 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
858
859 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
860 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
861 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
862
863 struct i40e_filter_program_desc {
864 __le32 qindex_flex_ptype_vsi;
865 __le32 rsvd;
866 __le32 dtype_cmd_cntindex;
867 __le32 fd_id;
868 };
869 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
870 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
871 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
872 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
873 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
874 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
875 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
876 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
877 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
878
879 /* Packet Classifier Types for filters */
880 enum i40e_filter_pctype {
881 /* Note: Values 0-30 are reserved for future use */
882 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
883 /* Note: Value 32 is reserved for future use */
884 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
885 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
886 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
887 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
888 /* Note: Values 37-40 are reserved for future use */
889 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
890 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
891 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
892 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
893 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
894 /* Note: Value 47 is reserved for future use */
895 I40E_FILTER_PCTYPE_FCOE_OX = 48,
896 I40E_FILTER_PCTYPE_FCOE_RX = 49,
897 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
898 /* Note: Values 51-62 are reserved for future use */
899 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
900 };
901
902 enum i40e_filter_program_desc_dest {
903 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
904 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
905 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
906 };
907
908 enum i40e_filter_program_desc_fd_status {
909 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
910 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
911 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
912 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
913 };
914
915 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
916 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
917 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
918
919 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
920 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
921 I40E_TXD_FLTR_QW1_CMD_SHIFT)
922
923 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
924 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
925
926 enum i40e_filter_program_desc_pcmd {
927 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
928 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
929 };
930
931 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
932 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
933
934 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
935 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
936 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
937
938 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
939 I40E_TXD_FLTR_QW1_CMD_SHIFT)
940 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
941 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
942
943 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
944 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
945 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
946
947 enum i40e_filter_type {
948 I40E_FLOW_DIRECTOR_FLTR = 0,
949 I40E_PE_QUAD_HASH_FLTR = 1,
950 I40E_ETHERTYPE_FLTR,
951 I40E_FCOE_CTX_FLTR,
952 I40E_MAC_VLAN_FLTR,
953 I40E_HASH_FLTR
954 };
955
956 struct i40e_vsi_context {
957 u16 seid;
958 u16 uplink_seid;
959 u16 vsi_number;
960 u16 vsis_allocated;
961 u16 vsis_unallocated;
962 u16 flags;
963 u8 pf_num;
964 u8 vf_num;
965 u8 connection_type;
966 struct i40e_aqc_vsi_properties_data info;
967 };
968
969 struct i40e_veb_context {
970 u16 seid;
971 u16 uplink_seid;
972 u16 veb_number;
973 u16 vebs_allocated;
974 u16 vebs_unallocated;
975 u16 flags;
976 struct i40e_aqc_get_veb_parameters_completion info;
977 };
978
979 /* Statistics collected by each port, VSI, VEB, and S-channel */
980 struct i40e_eth_stats {
981 u64 rx_bytes; /* gorc */
982 u64 rx_unicast; /* uprc */
983 u64 rx_multicast; /* mprc */
984 u64 rx_broadcast; /* bprc */
985 u64 rx_discards; /* rdpc */
986 u64 rx_unknown_protocol; /* rupp */
987 u64 tx_bytes; /* gotc */
988 u64 tx_unicast; /* uptc */
989 u64 tx_multicast; /* mptc */
990 u64 tx_broadcast; /* bptc */
991 u64 tx_discards; /* tdpc */
992 u64 tx_errors; /* tepc */
993 };
994
995 /* Statistics collected by the MAC */
996 struct i40e_hw_port_stats {
997 /* eth stats collected by the port */
998 struct i40e_eth_stats eth;
999
1000 /* additional port specific stats */
1001 u64 tx_dropped_link_down; /* tdold */
1002 u64 crc_errors; /* crcerrs */
1003 u64 illegal_bytes; /* illerrc */
1004 u64 error_bytes; /* errbc */
1005 u64 mac_local_faults; /* mlfc */
1006 u64 mac_remote_faults; /* mrfc */
1007 u64 rx_length_errors; /* rlec */
1008 u64 link_xon_rx; /* lxonrxc */
1009 u64 link_xoff_rx; /* lxoffrxc */
1010 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1011 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1012 u64 link_xon_tx; /* lxontxc */
1013 u64 link_xoff_tx; /* lxofftxc */
1014 u64 priority_xon_tx[8]; /* pxontxc[8] */
1015 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1016 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1017 u64 rx_size_64; /* prc64 */
1018 u64 rx_size_127; /* prc127 */
1019 u64 rx_size_255; /* prc255 */
1020 u64 rx_size_511; /* prc511 */
1021 u64 rx_size_1023; /* prc1023 */
1022 u64 rx_size_1522; /* prc1522 */
1023 u64 rx_size_big; /* prc9522 */
1024 u64 rx_undersize; /* ruc */
1025 u64 rx_fragments; /* rfc */
1026 u64 rx_oversize; /* roc */
1027 u64 rx_jabber; /* rjc */
1028 u64 tx_size_64; /* ptc64 */
1029 u64 tx_size_127; /* ptc127 */
1030 u64 tx_size_255; /* ptc255 */
1031 u64 tx_size_511; /* ptc511 */
1032 u64 tx_size_1023; /* ptc1023 */
1033 u64 tx_size_1522; /* ptc1522 */
1034 u64 tx_size_big; /* ptc9522 */
1035 u64 mac_short_packet_dropped; /* mspdc */
1036 u64 checksum_error; /* xec */
1037 /* flow director stats */
1038 u64 fd_atr_match;
1039 u64 fd_sb_match;
1040 /* EEE LPI */
1041 u32 tx_lpi_status;
1042 u32 rx_lpi_status;
1043 u64 tx_lpi_count; /* etlpic */
1044 u64 rx_lpi_count; /* erlpic */
1045 };
1046
1047 /* Checksum and Shadow RAM pointers */
1048 #define I40E_SR_NVM_CONTROL_WORD 0x00
1049 #define I40E_SR_EMP_MODULE_PTR 0x0F
1050 #define I40E_SR_NVM_IMAGE_VERSION 0x18
1051 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1052 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1053 #define I40E_SR_NVM_EETRACK_LO 0x2D
1054 #define I40E_SR_NVM_EETRACK_HI 0x2E
1055 #define I40E_SR_VPD_PTR 0x2F
1056 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1057 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1058
1059 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1060 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1061 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1062 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1063 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1064
1065 /* Shadow RAM related */
1066 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1067 #define I40E_SR_WORDS_IN_1KB 512
1068 /* Checksum should be calculated such that after adding all the words,
1069 * including the checksum word itself, the sum should be 0xBABA.
1070 */
1071 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1072
1073 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1074
1075 enum i40e_switch_element_types {
1076 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1077 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1078 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1079 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1080 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1081 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1082 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1083 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1084 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1085 };
1086
1087 /* Supported EtherType filters */
1088 enum i40e_ether_type_index {
1089 I40E_ETHER_TYPE_1588 = 0,
1090 I40E_ETHER_TYPE_FIP = 1,
1091 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1092 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1093 I40E_ETHER_TYPE_LLDP = 4,
1094 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1095 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1096 I40E_ETHER_TYPE_QCN_CNM = 7,
1097 I40E_ETHER_TYPE_8021X = 8,
1098 I40E_ETHER_TYPE_ARP = 9,
1099 I40E_ETHER_TYPE_RSV1 = 10,
1100 I40E_ETHER_TYPE_RSV2 = 11,
1101 };
1102
1103 /* Filter context base size is 1K */
1104 #define I40E_HASH_FILTER_BASE_SIZE 1024
1105 /* Supported Hash filter values */
1106 enum i40e_hash_filter_size {
1107 I40E_HASH_FILTER_SIZE_1K = 0,
1108 I40E_HASH_FILTER_SIZE_2K = 1,
1109 I40E_HASH_FILTER_SIZE_4K = 2,
1110 I40E_HASH_FILTER_SIZE_8K = 3,
1111 I40E_HASH_FILTER_SIZE_16K = 4,
1112 I40E_HASH_FILTER_SIZE_32K = 5,
1113 I40E_HASH_FILTER_SIZE_64K = 6,
1114 I40E_HASH_FILTER_SIZE_128K = 7,
1115 I40E_HASH_FILTER_SIZE_256K = 8,
1116 I40E_HASH_FILTER_SIZE_512K = 9,
1117 I40E_HASH_FILTER_SIZE_1M = 10,
1118 };
1119
1120 /* DMA context base size is 0.5K */
1121 #define I40E_DMA_CNTX_BASE_SIZE 512
1122 /* Supported DMA context values */
1123 enum i40e_dma_cntx_size {
1124 I40E_DMA_CNTX_SIZE_512 = 0,
1125 I40E_DMA_CNTX_SIZE_1K = 1,
1126 I40E_DMA_CNTX_SIZE_2K = 2,
1127 I40E_DMA_CNTX_SIZE_4K = 3,
1128 I40E_DMA_CNTX_SIZE_8K = 4,
1129 I40E_DMA_CNTX_SIZE_16K = 5,
1130 I40E_DMA_CNTX_SIZE_32K = 6,
1131 I40E_DMA_CNTX_SIZE_64K = 7,
1132 I40E_DMA_CNTX_SIZE_128K = 8,
1133 I40E_DMA_CNTX_SIZE_256K = 9,
1134 };
1135
1136 /* Supported Hash look up table (LUT) sizes */
1137 enum i40e_hash_lut_size {
1138 I40E_HASH_LUT_SIZE_128 = 0,
1139 I40E_HASH_LUT_SIZE_512 = 1,
1140 };
1141
1142 /* Structure to hold a per PF filter control settings */
1143 struct i40e_filter_control_settings {
1144 /* number of PE Quad Hash filter buckets */
1145 enum i40e_hash_filter_size pe_filt_num;
1146 /* number of PE Quad Hash contexts */
1147 enum i40e_dma_cntx_size pe_cntx_num;
1148 /* number of FCoE filter buckets */
1149 enum i40e_hash_filter_size fcoe_filt_num;
1150 /* number of FCoE DDP contexts */
1151 enum i40e_dma_cntx_size fcoe_cntx_num;
1152 /* size of the Hash LUT */
1153 enum i40e_hash_lut_size hash_lut_size;
1154 /* enable FDIR filters for PF and its VFs */
1155 bool enable_fdir;
1156 /* enable Ethertype filters for PF and its VFs */
1157 bool enable_ethtype;
1158 /* enable MAC/VLAN filters for PF and its VFs */
1159 bool enable_macvlan;
1160 };
1161
1162 /* Structure to hold device level control filter counts */
1163 struct i40e_control_filter_stats {
1164 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1165 u16 etype_used; /* Used perfect EtherType filters */
1166 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1167 u16 etype_free; /* Un-used perfect EtherType filters */
1168 };
1169
1170 enum i40e_reset_type {
1171 I40E_RESET_POR = 0,
1172 I40E_RESET_CORER = 1,
1173 I40E_RESET_GLOBR = 2,
1174 I40E_RESET_EMPR = 3,
1175 };
1176
1177 /* RSS Hash Table Size */
1178 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1179 #endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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