drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * The full GNU General Public License is included in this distribution in
  20  * the file called "COPYING".
  21  *
  22  * Contact Information:
  23  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25  *
  26  ******************************************************************************/
  27
  28 #ifndef _I40E_TYPE_H_
  29 #define _I40E_TYPE_H_
  30
  31 #include "i40e_status.h"
  32 #include "i40e_osdep.h"
  33 #include "i40e_register.h"
  34 #include "i40e_adminq.h"
  35 #include "i40e_hmc.h"
  36 #include "i40e_lan_hmc.h"
  37
  38 /* Device IDs */
  39 #define I40E_SFP_XL710_DEVICE_ID        0x1572
  40 #define I40E_SFP_X710_DEVICE_ID         0x1573
  41 #define I40E_QEMU_DEVICE_ID             0x1574
  42 #define I40E_KX_A_DEVICE_ID             0x157F
  43 #define I40E_KX_B_DEVICE_ID             0x1580
  44 #define I40E_KX_C_DEVICE_ID             0x1581
  45 #define I40E_KX_D_DEVICE_ID             0x1582
  46 #define I40E_QSFP_A_DEVICE_ID           0x1583
  47 #define I40E_QSFP_B_DEVICE_ID           0x1584
  48 #define I40E_QSFP_C_DEVICE_ID           0x1585
  49 #define I40E_VF_DEVICE_ID               0x154C
  50 #define I40E_VF_HV_DEVICE_ID            0x1571
  51
  52 #define I40E_FW_API_VERSION_MAJOR  0x0001
  53 #define I40E_FW_API_VERSION_MINOR  0x0000
  54
  55 #define I40E_MAX_VSI_QP                 16
  56 #define I40E_MAX_VF_VSI                 3
  57 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  58
  59 /* Max default timeout in ms, */
  60 #define I40E_MAX_NVM_TIMEOUT            18000
  61
  62 /* Check whether address is multicast.  This is little-endian specific check.*/
  63 #define I40E_IS_MULTICAST(address)      \
  64         (bool)(((u8 *)(address))[0] & ((u8)0x01))
  65
  66 /* Check whether an address is broadcast. */
  67 #define I40E_IS_BROADCAST(address)      \
  68         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  69         (((u8 *)(address))[1] == ((u8)0xff)))
  70
  71 /* Switch from mc to the 2usec global time (this is the GTIME resolution) */
  72 #define I40E_MS_TO_GTIME(time)          (((time) * 1000) / 2)
  73
  74 /* forward declaration */
  75 struct i40e_hw;
  76 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  77
  78 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  79
  80 /* Data type manipulation macros. */
  81
  82 #define I40E_DESC_UNUSED(R)     \
  83         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  84         (R)->next_to_clean - (R)->next_to_use - 1)
  85
  86 /* bitfields for Tx queue mapping in QTX_CTL */
  87 #define I40E_QTX_CTL_VF_QUEUE   0x0
  88 #define I40E_QTX_CTL_PF_QUEUE   0x2
  89
  90 /* debug masks */
  91 enum i40e_debug_mask {
  92         I40E_DEBUG_INIT                 = 0x00000001,
  93         I40E_DEBUG_RELEASE              = 0x00000002,
  94
  95         I40E_DEBUG_LINK                 = 0x00000010,
  96         I40E_DEBUG_PHY                  = 0x00000020,
  97         I40E_DEBUG_HMC                  = 0x00000040,
  98         I40E_DEBUG_NVM                  = 0x00000080,
  99         I40E_DEBUG_LAN                  = 0x00000100,
 100         I40E_DEBUG_FLOW                 = 0x00000200,
 101         I40E_DEBUG_DCB                  = 0x00000400,
 102         I40E_DEBUG_DIAG                 = 0x00000800,
 103
 104         I40E_DEBUG_AQ_MESSAGE           = 0x01000000, /* for i40e_debug() */
 105         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 106         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 107         I40E_DEBUG_AQ_COMMAND           = 0x06000000, /* for i40e_debug_aq() */
 108         I40E_DEBUG_AQ                   = 0x0F000000,
 109
 110         I40E_DEBUG_USER                 = 0xF0000000,
 111
 112         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 113 };
 114
 115 /* These are structs for managing the hardware information and the operations.
 116  * The structures of function pointers are filled out at init time when we
 117  * know for sure exactly which hardware we're working with.  This gives us the
 118  * flexibility of using the same main driver code but adapting to slightly
 119  * different hardware needs as new parts are developed.  For this architecture,
 120  * the Firmware and AdminQ are intended to insulate the driver from most of the
 121  * future changes, but these structures will also do part of the job.
 122  */
 123 enum i40e_mac_type {
 124         I40E_MAC_UNKNOWN = 0,
 125         I40E_MAC_X710,
 126         I40E_MAC_XL710,
 127         I40E_MAC_VF,
 128         I40E_MAC_GENERIC,
 129 };
 130
 131 enum i40e_media_type {
 132         I40E_MEDIA_TYPE_UNKNOWN = 0,
 133         I40E_MEDIA_TYPE_FIBER,
 134         I40E_MEDIA_TYPE_BASET,
 135         I40E_MEDIA_TYPE_BACKPLANE,
 136         I40E_MEDIA_TYPE_CX4,
 137         I40E_MEDIA_TYPE_VIRTUAL
 138 };
 139
 140 enum i40e_fc_mode {
 141         I40E_FC_NONE = 0,
 142         I40E_FC_RX_PAUSE,
 143         I40E_FC_TX_PAUSE,
 144         I40E_FC_FULL,
 145         I40E_FC_PFC,
 146         I40E_FC_DEFAULT
 147 };
 148
 149 enum i40e_vsi_type {
 150         I40E_VSI_MAIN = 0,
 151         I40E_VSI_VMDQ1,
 152         I40E_VSI_VMDQ2,
 153         I40E_VSI_CTRL,
 154         I40E_VSI_FCOE,
 155         I40E_VSI_MIRROR,
 156         I40E_VSI_SRIOV,
 157         I40E_VSI_FDIR,
 158         I40E_VSI_TYPE_UNKNOWN
 159 };
 160
 161 enum i40e_queue_type {
 162         I40E_QUEUE_TYPE_RX = 0,
 163         I40E_QUEUE_TYPE_TX,
 164         I40E_QUEUE_TYPE_PE_CEQ,
 165         I40E_QUEUE_TYPE_UNKNOWN
 166 };
 167
 168 struct i40e_link_status {
 169         enum i40e_aq_phy_type phy_type;
 170         enum i40e_aq_link_speed link_speed;
 171         u8 link_info;
 172         u8 an_info;
 173         u8 ext_info;
 174         /* is Link Status Event notification to SW enabled */
 175         bool lse_enable;
 176 };
 177
 178 struct i40e_phy_info {
 179         struct i40e_link_status link_info;
 180         struct i40e_link_status link_info_old;
 181         u32 autoneg_advertised;
 182         u32 phy_id;
 183         u32 module_type;
 184         bool get_link_info;
 185         enum i40e_media_type media_type;
 186 };
 187
 188 #define I40E_HW_CAP_MAX_GPIO                    30
 189 /* Capabilities of a PF or a VF or the whole device */
 190 struct i40e_hw_capabilities {
 191         u32  switch_mode;
 192 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 193 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 194 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 195
 196         u32  management_mode;
 197         u32  npar_enable;
 198         u32  os2bmc;
 199         u32  valid_functions;
 200         bool sr_iov_1_1;
 201         bool vmdq;
 202         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 203         bool evb_802_1_qbh; /* Bridge Port Extension */
 204         bool dcb;
 205         bool fcoe;
 206         bool mfp_mode_1;
 207         bool mgmt_cem;
 208         bool ieee_1588;
 209         bool iwarp;
 210         bool fd;
 211         u32 fd_filters_guaranteed;
 212         u32 fd_filters_best_effort;
 213         bool rss;
 214         u32 rss_table_size;
 215         u32 rss_table_entry_width;
 216         bool led[I40E_HW_CAP_MAX_GPIO];
 217         bool sdp[I40E_HW_CAP_MAX_GPIO];
 218         u32 nvm_image_type;
 219         u32 num_flow_director_filters;
 220         u32 num_vfs;
 221         u32 vf_base_id;
 222         u32 num_vsis;
 223         u32 num_rx_qp;
 224         u32 num_tx_qp;
 225         u32 base_queue;
 226         u32 num_msix_vectors;
 227         u32 num_msix_vectors_vf;
 228         u32 led_pin_num;
 229         u32 sdp_pin_num;
 230         u32 mdio_port_num;
 231         u32 mdio_port_mode;
 232         u8 rx_buf_chain_len;
 233         u32 enabled_tcmap;
 234         u32 maxtc;
 235 };
 236
 237 struct i40e_mac_info {
 238         enum i40e_mac_type type;
 239         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 240         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 241         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 242         u16 max_fcoeq;
 243 };
 244
 245 enum i40e_aq_resources_ids {
 246         I40E_NVM_RESOURCE_ID = 1
 247 };
 248
 249 enum i40e_aq_resource_access_type {
 250         I40E_RESOURCE_READ = 1,
 251         I40E_RESOURCE_WRITE
 252 };
 253
 254 struct i40e_nvm_info {
 255         u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
 256         u64 hw_semaphore_wait;    /* - || - */
 257         u32 timeout;              /* [ms] */
 258         u16 sr_size;              /* Shadow RAM size in words */
 259         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 260         u16 version;              /* NVM package version */
 261         u32 eetrack;              /* NVM data version */
 262 };
 263
 264 /* PCI bus types */
 265 enum i40e_bus_type {
 266         i40e_bus_type_unknown = 0,
 267         i40e_bus_type_pci,
 268         i40e_bus_type_pcix,
 269         i40e_bus_type_pci_express,
 270         i40e_bus_type_reserved
 271 };
 272
 273 /* PCI bus speeds */
 274 enum i40e_bus_speed {
 275         i40e_bus_speed_unknown  = 0,
 276         i40e_bus_speed_33       = 33,
 277         i40e_bus_speed_66       = 66,
 278         i40e_bus_speed_100      = 100,
 279         i40e_bus_speed_120      = 120,
 280         i40e_bus_speed_133      = 133,
 281         i40e_bus_speed_2500     = 2500,
 282         i40e_bus_speed_5000     = 5000,
 283         i40e_bus_speed_8000     = 8000,
 284         i40e_bus_speed_reserved
 285 };
 286
 287 /* PCI bus widths */
 288 enum i40e_bus_width {
 289         i40e_bus_width_unknown  = 0,
 290         i40e_bus_width_pcie_x1  = 1,
 291         i40e_bus_width_pcie_x2  = 2,
 292         i40e_bus_width_pcie_x4  = 4,
 293         i40e_bus_width_pcie_x8  = 8,
 294         i40e_bus_width_32       = 32,
 295         i40e_bus_width_64       = 64,
 296         i40e_bus_width_reserved
 297 };
 298
 299 /* Bus parameters */
 300 struct i40e_bus_info {
 301         enum i40e_bus_speed speed;
 302         enum i40e_bus_width width;
 303         enum i40e_bus_type type;
 304
 305         u16 func;
 306         u16 device;
 307         u16 lan_id;
 308 };
 309
 310 /* Flow control (FC) parameters */
 311 struct i40e_fc_info {
 312         enum i40e_fc_mode current_mode; /* FC mode in effect */
 313         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 314 };
 315
 316 #define I40E_MAX_TRAFFIC_CLASS          8
 317 #define I40E_MAX_USER_PRIORITY          8
 318 #define I40E_DCBX_MAX_APPS              32
 319 #define I40E_LLDPDU_SIZE                1500
 320
 321 /* IEEE 802.1Qaz ETS Configuration data */
 322 struct i40e_ieee_ets_config {
 323         u8 willing;
 324         u8 cbs;
 325         u8 maxtcs;
 326         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 327         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 328         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 329 };
 330
 331 /* IEEE 802.1Qaz ETS Recommendation data */
 332 struct i40e_ieee_ets_recommend {
 333         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 334         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 335         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 336 };
 337
 338 /* IEEE 802.1Qaz PFC Configuration data */
 339 struct i40e_ieee_pfc_config {
 340         u8 willing;
 341         u8 mbc;
 342         u8 pfccap;
 343         u8 pfcenable;
 344 };
 345
 346 /* IEEE 802.1Qaz Application Priority data */
 347 struct i40e_ieee_app_priority_table {
 348         u8  priority;
 349         u8  selector;
 350         u16 protocolid;
 351 };
 352
 353 struct i40e_dcbx_config {
 354         u32 numapps;
 355         struct i40e_ieee_ets_config etscfg;
 356         struct i40e_ieee_ets_recommend etsrec;
 357         struct i40e_ieee_pfc_config pfc;
 358         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 359 };
 360
 361 /* Port hardware description */
 362 struct i40e_hw {
 363         u8 __iomem *hw_addr;
 364         void *back;
 365
 366         /* function pointer structs */
 367         struct i40e_phy_info phy;
 368         struct i40e_mac_info mac;
 369         struct i40e_bus_info bus;
 370         struct i40e_nvm_info nvm;
 371         struct i40e_fc_info fc;
 372
 373         /* pci info */
 374         u16 device_id;
 375         u16 vendor_id;
 376         u16 subsystem_device_id;
 377         u16 subsystem_vendor_id;
 378         u8 revision_id;
 379         u8 port;
 380         bool adapter_stopped;
 381
 382         /* capabilities for entire device and PCI func */
 383         struct i40e_hw_capabilities dev_caps;
 384         struct i40e_hw_capabilities func_caps;
 385
 386         /* Flow Director shared filter space */
 387         u16 fdir_shared_filter_count;
 388
 389         /* device profile info */
 390         u8  pf_id;
 391         u16 main_vsi_seid;
 392
 393         /* Closest numa node to the device */
 394         u16 numa_node;
 395
 396         /* Admin Queue info */
 397         struct i40e_adminq_info aq;
 398
 399         /* HMC info */
 400         struct i40e_hmc_info hmc; /* HMC info struct */
 401
 402         /* LLDP/DCBX Status */
 403         u16 dcbx_status;
 404
 405         /* DCBX info */
 406         struct i40e_dcbx_config local_dcbx_config;
 407         struct i40e_dcbx_config remote_dcbx_config;
 408
 409         /* debug mask */
 410         u32 debug_mask;
 411 };
 412
 413 struct i40e_driver_version {
 414         u8 major_version;
 415         u8 minor_version;
 416         u8 build_version;
 417         u8 subbuild_version;
 418 };
 419
 420 /* RX Descriptors */
 421 union i40e_16byte_rx_desc {
 422         struct {
 423                 __le64 pkt_addr; /* Packet buffer address */
 424                 __le64 hdr_addr; /* Header buffer address */
 425         } read;
 426         struct {
 427                 struct {
 428                         struct {
 429                                 union {
 430                                         __le16 mirroring_status;
 431                                         __le16 fcoe_ctx_id;
 432                                 } mirr_fcoe;
 433                                 __le16 l2tag1;
 434                         } lo_dword;
 435                         union {
 436                                 __le32 rss; /* RSS Hash */
 437                                 __le32 fd_id; /* Flow director filter id */
 438                                 __le32 fcoe_param; /* FCoE DDP Context id */
 439                         } hi_dword;
 440                 } qword0;
 441                 struct {
 442                         /* ext status/error/pktype/length */
 443                         __le64 status_error_len;
 444                 } qword1;
 445         } wb;  /* writeback */
 446 };
 447
 448 union i40e_32byte_rx_desc {
 449         struct {
 450                 __le64  pkt_addr; /* Packet buffer address */
 451                 __le64  hdr_addr; /* Header buffer address */
 452                         /* bit 0 of hdr_buffer_addr is DD bit */
 453                 __le64  rsvd1;
 454                 __le64  rsvd2;
 455         } read;
 456         struct {
 457                 struct {
 458                         struct {
 459                                 union {
 460                                         __le16 mirroring_status;
 461                                         __le16 fcoe_ctx_id;
 462                                 } mirr_fcoe;
 463                                 __le16 l2tag1;
 464                         } lo_dword;
 465                         union {
 466                                 __le32 rss; /* RSS Hash */
 467                                 __le32 fcoe_param; /* FCoE DDP Context id */
 468                         } hi_dword;
 469                 } qword0;
 470                 struct {
 471                         /* status/error/pktype/length */
 472                         __le64 status_error_len;
 473                 } qword1;
 474                 struct {
 475                         __le16 ext_status; /* extended status */
 476                         __le16 rsvd;
 477                         __le16 l2tag2_1;
 478                         __le16 l2tag2_2;
 479                 } qword2;
 480                 struct {
 481                         union {
 482                                 __le32 flex_bytes_lo;
 483                                 __le32 pe_status;
 484                         } lo_dword;
 485                         union {
 486                                 __le32 flex_bytes_hi;
 487                                 __le32 fd_id;
 488                         } hi_dword;
 489                 } qword3;
 490         } wb;  /* writeback */
 491 };
 492
 493 #define I40E_RXD_QW1_STATUS_SHIFT       0
 494 #define I40E_RXD_QW1_STATUS_MASK        (0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)
 495
 496 enum i40e_rx_desc_status_bits {
 497         /* Note: These are predefined bit offsets */
 498         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 499         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 500         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 501         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 502         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 503         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 3 BITS */
 504         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 505         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 506         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 507         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 508         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14
 509 };
 510
 511 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 512 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x7UL << \
 513                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 514
 515 enum i40e_rx_desc_fltstat_values {
 516         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 517         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 518         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 519         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 520 };
 521
 522 #define I40E_RXD_QW1_ERROR_SHIFT        19
 523 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 524
 525 enum i40e_rx_desc_error_bits {
 526         /* Note: These are predefined bit offsets */
 527         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 528         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 529         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 530         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 531         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 532         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 533         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 534         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6
 535 };
 536
 537 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 538         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 539         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 540         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 541         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 542         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 543 };
 544
 545 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 546 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 547
 548 /* Packet type non-ip values */
 549 enum i40e_rx_l2_ptype {
 550         I40E_RX_PTYPE_L2_RESERVED               = 0,
 551         I40E_RX_PTYPE_L2_MAC_PAY2               = 1,
 552         I40E_RX_PTYPE_L2_TIMESYNC_PAY2          = 2,
 553         I40E_RX_PTYPE_L2_FIP_PAY2               = 3,
 554         I40E_RX_PTYPE_L2_OUI_PAY2               = 4,
 555         I40E_RX_PTYPE_L2_MACCNTRL_PAY2          = 5,
 556         I40E_RX_PTYPE_L2_LLDP_PAY2              = 6,
 557         I40E_RX_PTYPE_L2_ECP_PAY2               = 7,
 558         I40E_RX_PTYPE_L2_EVB_PAY2               = 8,
 559         I40E_RX_PTYPE_L2_QCN_PAY2               = 9,
 560         I40E_RX_PTYPE_L2_EAPOL_PAY2             = 10,
 561         I40E_RX_PTYPE_L2_ARP                    = 11,
 562         I40E_RX_PTYPE_L2_FCOE_PAY3              = 12,
 563         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3       = 13,
 564         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3        = 14,
 565         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3        = 15,
 566         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA        = 16,
 567         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3          = 17,
 568         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA        = 18,
 569         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY         = 19,
 570         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP         = 20,
 571         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER       = 21
 572 };
 573
 574 struct i40e_rx_ptype_decoded {
 575         u32 ptype:8;
 576         u32 known:1;
 577         u32 outer_ip:1;
 578         u32 outer_ip_ver:1;
 579         u32 outer_frag:1;
 580         u32 tunnel_type:3;
 581         u32 tunnel_end_prot:2;
 582         u32 tunnel_end_frag:1;
 583         u32 inner_prot:4;
 584         u32 payload_layer:3;
 585 };
 586
 587 enum i40e_rx_ptype_outer_ip {
 588         I40E_RX_PTYPE_OUTER_L2  = 0,
 589         I40E_RX_PTYPE_OUTER_IP  = 1
 590 };
 591
 592 enum i40e_rx_ptype_outer_ip_ver {
 593         I40E_RX_PTYPE_OUTER_NONE        = 0,
 594         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 595         I40E_RX_PTYPE_OUTER_IPV6        = 1
 596 };
 597
 598 enum i40e_rx_ptype_outer_fragmented {
 599         I40E_RX_PTYPE_NOT_FRAG  = 0,
 600         I40E_RX_PTYPE_FRAG      = 1
 601 };
 602
 603 enum i40e_rx_ptype_tunnel_type {
 604         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 605         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 606         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 607         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 608         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 609 };
 610
 611 enum i40e_rx_ptype_tunnel_end_prot {
 612         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 613         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 614         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 615 };
 616
 617 enum i40e_rx_ptype_inner_prot {
 618         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 619         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 620         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 621         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 622         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 623         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 624 };
 625
 626 enum i40e_rx_ptype_payload_layer {
 627         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 628         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 629         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 630         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 631 };
 632
 633 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 634 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 635                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 636
 637 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 638 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 639                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 640
 641 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 642 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 643                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 644
 645 enum i40e_rx_desc_ext_status_bits {
 646         /* Note: These are predefined bit offsets */
 647         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 648         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 649         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 650         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 651         I40E_RX_DESC_EXT_STATUS_FTYPE_SHIFT     = 6, /* 3 BITS */
 652         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 653         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 654         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 655 };
 656
 657 enum i40e_rx_desc_pe_status_bits {
 658         /* Note: These are predefined bit offsets */
 659         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 660         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 661         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 662         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 663         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 664         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 665         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 666         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 667         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 668 };
 669
 670 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 671 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 672
 673 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 674 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 675                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 676
 677 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 678 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 679                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 680
 681 enum i40e_rx_prog_status_desc_status_bits {
 682         /* Note: These are predefined bit offsets */
 683         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 684         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 685 };
 686
 687 enum i40e_rx_prog_status_desc_prog_id_masks {
 688         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 689         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 690         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 691 };
 692
 693 enum i40e_rx_prog_status_desc_error_bits {
 694         /* Note: These are predefined bit offsets */
 695         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 696         I40E_RX_PROG_STATUS_DESC_NO_FD_QUOTA_SHIFT      = 1,
 697         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 698         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 699 };
 700
 701 /* TX Descriptor */
 702 struct i40e_tx_desc {
 703         __le64 buffer_addr; /* Address of descriptor's data buf */
 704         __le64 cmd_type_offset_bsz;
 705 };
 706
 707 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 708 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 709
 710 enum i40e_tx_desc_dtype_value {
 711         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 712         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 713         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 714         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 715         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 716         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 717         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 718         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 719         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 720         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 721 };
 722
 723 #define I40E_TXD_QW1_CMD_SHIFT  4
 724 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 725
 726 enum i40e_tx_desc_cmd_bits {
 727         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 728         I40E_TX_DESC_CMD_RS                     = 0x0002,
 729         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 730         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 731         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 732         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 733         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 734         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 735         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 736         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 737         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 738         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 739         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 740         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 741         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 742         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 743         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 744         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 745 };
 746
 747 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 748 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 749                                          I40E_TXD_QW1_OFFSET_SHIFT)
 750
 751 enum i40e_tx_desc_length_fields {
 752         /* Note: These are predefined bit offsets */
 753         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 754         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 755         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 756 };
 757
 758 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 759 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 760                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 761
 762 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 763 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 764
 765 /* Context descriptors */
 766 struct i40e_tx_context_desc {
 767         __le32 tunneling_params;
 768         __le16 l2tag2;
 769         __le16 rsvd;
 770         __le64 type_cmd_tso_mss;
 771 };
 772
 773 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 774 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 775
 776 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 777 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 778
 779 enum i40e_tx_ctx_desc_cmd_bits {
 780         I40E_TX_CTX_DESC_TSO            = 0x01,
 781         I40E_TX_CTX_DESC_TSYN           = 0x02,
 782         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 783         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 784         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 785         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 786         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 787         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 788         I40E_TX_CTX_DESC_SWPE           = 0x40
 789 };
 790
 791 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 792 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 793                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 794
 795 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 796 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 797                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 798
 799 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 800 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 801
 802 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 803 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 804                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 805
 806 enum i40e_tx_ctx_desc_eipt_offload {
 807         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 808         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 809         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 810         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 811 };
 812
 813 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 814 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 815                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 816
 817 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 818 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 819
 820 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 821 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 822
 823 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 824 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
 825                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 826
 827 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 828
 829 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 830 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 831                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 832
 833 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 834 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 835                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 836
 837 struct i40e_filter_program_desc {
 838         __le32 qindex_flex_ptype_vsi;
 839         __le32 rsvd;
 840         __le32 dtype_cmd_cntindex;
 841         __le32 fd_id;
 842 };
 843 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 844 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 845                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 846 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 847 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 848                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 849 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 850 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 851                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 852
 853 /* Packet Classifier Types for filters */
 854 enum i40e_filter_pctype {
 855         /* Note: Value 0-25 are reserved for future use */
 856         I40E_FILTER_PCTYPE_IPV4_TEREDO_UDP              = 26,
 857         I40E_FILTER_PCTYPE_IPV6_TEREDO_UDP              = 27,
 858         I40E_FILTER_PCTYPE_NONF_IPV4_1588_UDP           = 28,
 859         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
 860         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
 861         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 862         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN            = 32,
 863         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 864         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 865         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 866         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 867         /* Note: Value 37 is reserved for future use */
 868         I40E_FILTER_PCTYPE_NONF_IPV6_1588_UDP           = 38,
 869         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
 870         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
 871         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 872         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN            = 42,
 873         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 874         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 875         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 876         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 877         /* Note: Value 47 is reserved for future use */
 878         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
 879         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
 880         /* Note: Value 50-62 are reserved for future use */
 881         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 882 };
 883
 884 enum i40e_filter_program_desc_dest {
 885         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
 886         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
 887         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
 888 };
 889
 890 enum i40e_filter_program_desc_fd_status {
 891         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
 892         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
 893         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
 894         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
 895 };
 896
 897 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
 898 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
 899                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
 900
 901 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
 902 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
 903                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
 904
 905 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 906 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
 907
 908 enum i40e_filter_program_desc_pcmd {
 909         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
 910         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
 911 };
 912
 913 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 914 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
 915
 916 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 917 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
 918                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
 919
 920 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
 921                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
 922 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
 923                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
 924
 925 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
 926 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
 927                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
 928
 929 enum i40e_filter_type {
 930         I40E_FLOW_DIRECTOR_FLTR = 0,
 931         I40E_PE_QUAD_HASH_FLTR = 1,
 932         I40E_ETHERTYPE_FLTR,
 933         I40E_FCOE_CTX_FLTR,
 934         I40E_MAC_VLAN_FLTR,
 935         I40E_HASH_FLTR
 936 };
 937
 938 struct i40e_vsi_context {
 939         u16 seid;
 940         u16 uplink_seid;
 941         u16 vsi_number;
 942         u16 vsis_allocated;
 943         u16 vsis_unallocated;
 944         u16 flags;
 945         u8 pf_num;
 946         u8 vf_num;
 947         u8 connection_type;
 948         struct i40e_aqc_vsi_properties_data info;
 949 };
 950
 951 /* Statistics collected by each port, VSI, VEB, and S-channel */
 952 struct i40e_eth_stats {
 953         u64 rx_bytes;                   /* gorc */
 954         u64 rx_unicast;                 /* uprc */
 955         u64 rx_multicast;               /* mprc */
 956         u64 rx_broadcast;               /* bprc */
 957         u64 rx_discards;                /* rdpc */
 958         u64 rx_errors;                  /* repc */
 959         u64 rx_missed;                  /* rmpc */
 960         u64 rx_unknown_protocol;        /* rupp */
 961         u64 tx_bytes;                   /* gotc */
 962         u64 tx_unicast;                 /* uptc */
 963         u64 tx_multicast;               /* mptc */
 964         u64 tx_broadcast;               /* bptc */
 965         u64 tx_discards;                /* tdpc */
 966         u64 tx_errors;                  /* tepc */
 967 };
 968
 969 /* Statistics collected by the MAC */
 970 struct i40e_hw_port_stats {
 971         /* eth stats collected by the port */
 972         struct i40e_eth_stats eth;
 973
 974         /* additional port specific stats */
 975         u64 tx_dropped_link_down;       /* tdold */
 976         u64 crc_errors;                 /* crcerrs */
 977         u64 illegal_bytes;              /* illerrc */
 978         u64 error_bytes;                /* errbc */
 979         u64 mac_local_faults;           /* mlfc */
 980         u64 mac_remote_faults;          /* mrfc */
 981         u64 rx_length_errors;           /* rlec */
 982         u64 link_xon_rx;                /* lxonrxc */
 983         u64 link_xoff_rx;               /* lxoffrxc */
 984         u64 priority_xon_rx[8];         /* pxonrxc[8] */
 985         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
 986         u64 link_xon_tx;                /* lxontxc */
 987         u64 link_xoff_tx;               /* lxofftxc */
 988         u64 priority_xon_tx[8];         /* pxontxc[8] */
 989         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
 990         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
 991         u64 rx_size_64;                 /* prc64 */
 992         u64 rx_size_127;                /* prc127 */
 993         u64 rx_size_255;                /* prc255 */
 994         u64 rx_size_511;                /* prc511 */
 995         u64 rx_size_1023;               /* prc1023 */
 996         u64 rx_size_1522;               /* prc1522 */
 997         u64 rx_size_big;                /* prc9522 */
 998         u64 rx_undersize;               /* ruc */
 999         u64 rx_fragments;               /* rfc */
1000         u64 rx_oversize;                /* roc */
1001         u64 rx_jabber;                  /* rjc */
1002         u64 tx_size_64;                 /* ptc64 */
1003         u64 tx_size_127;                /* ptc127 */
1004         u64 tx_size_255;                /* ptc255 */
1005         u64 tx_size_511;                /* ptc511 */
1006         u64 tx_size_1023;               /* ptc1023 */
1007         u64 tx_size_1522;               /* ptc1522 */
1008         u64 tx_size_big;                /* ptc9522 */
1009         u64 mac_short_packet_dropped;   /* mspdc */
1010         u64 checksum_error;             /* xec */
1011 };
1012
1013 /* Checksum and Shadow RAM pointers */
1014 #define I40E_SR_NVM_CONTROL_WORD                0x00
1015 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1016 #define I40E_SR_NVM_IMAGE_VERSION               0x18
1017 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1018 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1019 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1020 #define I40E_SR_VPD_PTR                         0x2F
1021 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1022 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1023
1024 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1025 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1026 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1027 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1028 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1029
1030 /* Shadow RAM related */
1031 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1032 #define I40E_SR_WORDS_IN_1KB            512
1033 /* Checksum should be calculated such that after adding all the words,
1034  * including the checksum word itself, the sum should be 0xBABA.
1035  */
1036 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1037
1038 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1039
1040 enum i40e_switch_element_types {
1041         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1042         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1043         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1044         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1045         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1046         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1047         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1048         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1049         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1050 };
1051
1052 /* Supported EtherType filters */
1053 enum i40e_ether_type_index {
1054         I40E_ETHER_TYPE_1588            = 0,
1055         I40E_ETHER_TYPE_FIP             = 1,
1056         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1057         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1058         I40E_ETHER_TYPE_LLDP            = 4,
1059         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1060         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1061         I40E_ETHER_TYPE_QCN_CNM         = 7,
1062         I40E_ETHER_TYPE_8021X           = 8,
1063         I40E_ETHER_TYPE_ARP             = 9,
1064         I40E_ETHER_TYPE_RSV1            = 10,
1065         I40E_ETHER_TYPE_RSV2            = 11,
1066 };
1067
1068 /* Filter context base size is 1K */
1069 #define I40E_HASH_FILTER_BASE_SIZE      1024
1070 /* Supported Hash filter values */
1071 enum i40e_hash_filter_size {
1072         I40E_HASH_FILTER_SIZE_1K        = 0,
1073         I40E_HASH_FILTER_SIZE_2K        = 1,
1074         I40E_HASH_FILTER_SIZE_4K        = 2,
1075         I40E_HASH_FILTER_SIZE_8K        = 3,
1076         I40E_HASH_FILTER_SIZE_16K       = 4,
1077         I40E_HASH_FILTER_SIZE_32K       = 5,
1078         I40E_HASH_FILTER_SIZE_64K       = 6,
1079         I40E_HASH_FILTER_SIZE_128K      = 7,
1080         I40E_HASH_FILTER_SIZE_256K      = 8,
1081         I40E_HASH_FILTER_SIZE_512K      = 9,
1082         I40E_HASH_FILTER_SIZE_1M        = 10,
1083 };
1084
1085 /* DMA context base size is 0.5K */
1086 #define I40E_DMA_CNTX_BASE_SIZE         512
1087 /* Supported DMA context values */
1088 enum i40e_dma_cntx_size {
1089         I40E_DMA_CNTX_SIZE_512          = 0,
1090         I40E_DMA_CNTX_SIZE_1K           = 1,
1091         I40E_DMA_CNTX_SIZE_2K           = 2,
1092         I40E_DMA_CNTX_SIZE_4K           = 3,
1093         I40E_DMA_CNTX_SIZE_8K           = 4,
1094         I40E_DMA_CNTX_SIZE_16K          = 5,
1095         I40E_DMA_CNTX_SIZE_32K          = 6,
1096         I40E_DMA_CNTX_SIZE_64K          = 7,
1097         I40E_DMA_CNTX_SIZE_128K         = 8,
1098         I40E_DMA_CNTX_SIZE_256K         = 9,
1099 };
1100
1101 /* Supported Hash look up table (LUT) sizes */
1102 enum i40e_hash_lut_size {
1103         I40E_HASH_LUT_SIZE_128          = 0,
1104         I40E_HASH_LUT_SIZE_512          = 1,
1105 };
1106
1107 /* Structure to hold a per PF filter control settings */
1108 struct i40e_filter_control_settings {
1109         /* number of PE Quad Hash filter buckets */
1110         enum i40e_hash_filter_size pe_filt_num;
1111         /* number of PE Quad Hash contexts */
1112         enum i40e_dma_cntx_size pe_cntx_num;
1113         /* number of FCoE filter buckets */
1114         enum i40e_hash_filter_size fcoe_filt_num;
1115         /* number of FCoE DDP contexts */
1116         enum i40e_dma_cntx_size fcoe_cntx_num;
1117         /* size of the Hash LUT */
1118         enum i40e_hash_lut_size hash_lut_size;
1119         /* enable FDIR filters for PF and its VFs */
1120         bool enable_fdir;
1121         /* enable Ethertype filters for PF and its VFs */
1122         bool enable_ethtype;
1123         /* enable MAC/VLAN filters for PF and its VFs */
1124         bool enable_macvlan;
1125 };
1126
1127 /* Structure to hold device level control filter counts */
1128 struct i40e_control_filter_stats {
1129         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1130         u16 etype_used;       /* Used perfect EtherType filters */
1131         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1132         u16 etype_free;       /* Un-used perfect EtherType filters */
1133 };
1134
1135 enum i40e_reset_type {
1136         I40E_RESET_POR          = 0,
1137         I40E_RESET_CORER        = 1,
1138         I40E_RESET_GLOBR        = 2,
1139         I40E_RESET_EMPR         = 3,
1140 };
1141
1142 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1143 #define I40E_NVM_LLDP_CFG_PTR           0xF
1144 struct i40e_lldp_variables {
1145         u16 length;
1146         u16 adminstatus;
1147         u16 msgfasttx;
1148         u16 msgtxinterval;
1149         u16 txparams;
1150         u16 timers;
1151         u16 crc8;
1152 };
1153
1154 #endif /* _I40E_TYPE_H_ */