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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next...
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_type.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36
37 /* Device IDs */
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_20G_KR2 0x1587
48 #define I40E_DEV_ID_20G_KR2_A 0x1588
49 #define I40E_DEV_ID_VF 0x154C
50 #define I40E_DEV_ID_VF_HV 0x1571
51 #define I40E_DEV_ID_SFP_X722 0x37D0
52 #define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
53 #define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
54 #define I40E_DEV_ID_X722_VF 0x37CD
55 #define I40E_DEV_ID_X722_VF_HV 0x37D9
56
57 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
58 (d) == I40E_DEV_ID_QSFP_B || \
59 (d) == I40E_DEV_ID_QSFP_C)
60
61 /* I40E_MASK is a macro used on 32 bit registers */
62 #define I40E_MASK(mask, shift) (mask << shift)
63
64 #define I40E_MAX_VSI_QP 16
65 #define I40E_MAX_VF_VSI 3
66 #define I40E_MAX_CHAINED_RX_BUFFERS 5
67 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
68
69 /* Max default timeout in ms, */
70 #define I40E_MAX_NVM_TIMEOUT 18000
71
72 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
73 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
74
75 /* forward declaration */
76 struct i40e_hw;
77 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
78
79 /* Data type manipulation macros. */
80
81 #define I40E_DESC_UNUSED(R) \
82 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
83 (R)->next_to_clean - (R)->next_to_use - 1)
84
85 /* bitfields for Tx queue mapping in QTX_CTL */
86 #define I40E_QTX_CTL_VF_QUEUE 0x0
87 #define I40E_QTX_CTL_VM_QUEUE 0x1
88 #define I40E_QTX_CTL_PF_QUEUE 0x2
89
90 /* debug masks - set these bits in hw->debug_mask to control output */
91 enum i40e_debug_mask {
92 I40E_DEBUG_INIT = 0x00000001,
93 I40E_DEBUG_RELEASE = 0x00000002,
94
95 I40E_DEBUG_LINK = 0x00000010,
96 I40E_DEBUG_PHY = 0x00000020,
97 I40E_DEBUG_HMC = 0x00000040,
98 I40E_DEBUG_NVM = 0x00000080,
99 I40E_DEBUG_LAN = 0x00000100,
100 I40E_DEBUG_FLOW = 0x00000200,
101 I40E_DEBUG_DCB = 0x00000400,
102 I40E_DEBUG_DIAG = 0x00000800,
103 I40E_DEBUG_FD = 0x00001000,
104
105 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
106 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
107 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
108 I40E_DEBUG_AQ_COMMAND = 0x06000000,
109 I40E_DEBUG_AQ = 0x0F000000,
110
111 I40E_DEBUG_USER = 0xF0000000,
112
113 I40E_DEBUG_ALL = 0xFFFFFFFF
114 };
115
116 /* These are structs for managing the hardware information and the operations.
117 * The structures of function pointers are filled out at init time when we
118 * know for sure exactly which hardware we're working with. This gives us the
119 * flexibility of using the same main driver code but adapting to slightly
120 * different hardware needs as new parts are developed. For this architecture,
121 * the Firmware and AdminQ are intended to insulate the driver from most of the
122 * future changes, but these structures will also do part of the job.
123 */
124 enum i40e_mac_type {
125 I40E_MAC_UNKNOWN = 0,
126 I40E_MAC_X710,
127 I40E_MAC_XL710,
128 I40E_MAC_VF,
129 I40E_MAC_X722,
130 I40E_MAC_X722_VF,
131 I40E_MAC_GENERIC,
132 };
133
134 enum i40e_media_type {
135 I40E_MEDIA_TYPE_UNKNOWN = 0,
136 I40E_MEDIA_TYPE_FIBER,
137 I40E_MEDIA_TYPE_BASET,
138 I40E_MEDIA_TYPE_BACKPLANE,
139 I40E_MEDIA_TYPE_CX4,
140 I40E_MEDIA_TYPE_DA,
141 I40E_MEDIA_TYPE_VIRTUAL
142 };
143
144 enum i40e_fc_mode {
145 I40E_FC_NONE = 0,
146 I40E_FC_RX_PAUSE,
147 I40E_FC_TX_PAUSE,
148 I40E_FC_FULL,
149 I40E_FC_PFC,
150 I40E_FC_DEFAULT
151 };
152
153 enum i40e_set_fc_aq_failures {
154 I40E_SET_FC_AQ_FAIL_NONE = 0,
155 I40E_SET_FC_AQ_FAIL_GET = 1,
156 I40E_SET_FC_AQ_FAIL_SET = 2,
157 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
158 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
159 };
160
161 enum i40e_vsi_type {
162 I40E_VSI_MAIN = 0,
163 I40E_VSI_VMDQ1,
164 I40E_VSI_VMDQ2,
165 I40E_VSI_CTRL,
166 I40E_VSI_FCOE,
167 I40E_VSI_MIRROR,
168 I40E_VSI_SRIOV,
169 I40E_VSI_FDIR,
170 I40E_VSI_TYPE_UNKNOWN
171 };
172
173 enum i40e_queue_type {
174 I40E_QUEUE_TYPE_RX = 0,
175 I40E_QUEUE_TYPE_TX,
176 I40E_QUEUE_TYPE_PE_CEQ,
177 I40E_QUEUE_TYPE_UNKNOWN
178 };
179
180 struct i40e_link_status {
181 enum i40e_aq_phy_type phy_type;
182 enum i40e_aq_link_speed link_speed;
183 u8 link_info;
184 u8 an_info;
185 u8 ext_info;
186 u8 loopback;
187 /* is Link Status Event notification to SW enabled */
188 bool lse_enable;
189 u16 max_frame_size;
190 bool crc_enable;
191 u8 pacing;
192 u8 requested_speeds;
193 };
194
195 struct i40e_phy_info {
196 struct i40e_link_status link_info;
197 struct i40e_link_status link_info_old;
198 u32 autoneg_advertised;
199 u32 phy_id;
200 u32 module_type;
201 bool get_link_info;
202 enum i40e_media_type media_type;
203 };
204
205 #define I40E_HW_CAP_MAX_GPIO 30
206 /* Capabilities of a PF or a VF or the whole device */
207 struct i40e_hw_capabilities {
208 u32 switch_mode;
209 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
210 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
211 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
212
213 u32 management_mode;
214 u32 npar_enable;
215 u32 os2bmc;
216 u32 valid_functions;
217 bool sr_iov_1_1;
218 bool vmdq;
219 bool evb_802_1_qbg; /* Edge Virtual Bridging */
220 bool evb_802_1_qbh; /* Bridge Port Extension */
221 bool dcb;
222 bool fcoe;
223 bool iscsi; /* Indicates iSCSI enabled */
224 bool flex10_enable;
225 bool flex10_capable;
226 u32 flex10_mode;
227 #define I40E_FLEX10_MODE_UNKNOWN 0x0
228 #define I40E_FLEX10_MODE_DCC 0x1
229 #define I40E_FLEX10_MODE_DCI 0x2
230
231 u32 flex10_status;
232 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
233 #define I40E_FLEX10_STATUS_VC_MODE 0x2
234
235 bool mgmt_cem;
236 bool ieee_1588;
237 bool iwarp;
238 bool fd;
239 u32 fd_filters_guaranteed;
240 u32 fd_filters_best_effort;
241 bool rss;
242 u32 rss_table_size;
243 u32 rss_table_entry_width;
244 bool led[I40E_HW_CAP_MAX_GPIO];
245 bool sdp[I40E_HW_CAP_MAX_GPIO];
246 u32 nvm_image_type;
247 u32 num_flow_director_filters;
248 u32 num_vfs;
249 u32 vf_base_id;
250 u32 num_vsis;
251 u32 num_rx_qp;
252 u32 num_tx_qp;
253 u32 base_queue;
254 u32 num_msix_vectors;
255 u32 num_msix_vectors_vf;
256 u32 led_pin_num;
257 u32 sdp_pin_num;
258 u32 mdio_port_num;
259 u32 mdio_port_mode;
260 u8 rx_buf_chain_len;
261 u32 enabled_tcmap;
262 u32 maxtc;
263 u64 wr_csr_prot;
264 };
265
266 struct i40e_mac_info {
267 enum i40e_mac_type type;
268 u8 addr[ETH_ALEN];
269 u8 perm_addr[ETH_ALEN];
270 u8 san_addr[ETH_ALEN];
271 u8 port_addr[ETH_ALEN];
272 u16 max_fcoeq;
273 };
274
275 enum i40e_aq_resources_ids {
276 I40E_NVM_RESOURCE_ID = 1
277 };
278
279 enum i40e_aq_resource_access_type {
280 I40E_RESOURCE_READ = 1,
281 I40E_RESOURCE_WRITE
282 };
283
284 struct i40e_nvm_info {
285 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
286 u32 timeout; /* [ms] */
287 u16 sr_size; /* Shadow RAM size in words */
288 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
289 u16 version; /* NVM package version */
290 u32 eetrack; /* NVM data version */
291 };
292
293 /* definitions used in NVM update support */
294
295 enum i40e_nvmupd_cmd {
296 I40E_NVMUPD_INVALID,
297 I40E_NVMUPD_READ_CON,
298 I40E_NVMUPD_READ_SNT,
299 I40E_NVMUPD_READ_LCB,
300 I40E_NVMUPD_READ_SA,
301 I40E_NVMUPD_WRITE_ERA,
302 I40E_NVMUPD_WRITE_CON,
303 I40E_NVMUPD_WRITE_SNT,
304 I40E_NVMUPD_WRITE_LCB,
305 I40E_NVMUPD_WRITE_SA,
306 I40E_NVMUPD_CSUM_CON,
307 I40E_NVMUPD_CSUM_SA,
308 I40E_NVMUPD_CSUM_LCB,
309 I40E_NVMUPD_STATUS,
310 I40E_NVMUPD_EXEC_AQ,
311 I40E_NVMUPD_GET_AQ_RESULT,
312 };
313
314 enum i40e_nvmupd_state {
315 I40E_NVMUPD_STATE_INIT,
316 I40E_NVMUPD_STATE_READING,
317 I40E_NVMUPD_STATE_WRITING,
318 I40E_NVMUPD_STATE_INIT_WAIT,
319 I40E_NVMUPD_STATE_WRITE_WAIT,
320 };
321
322 /* nvm_access definition and its masks/shifts need to be accessible to
323 * application, core driver, and shared code. Where is the right file?
324 */
325 #define I40E_NVM_READ 0xB
326 #define I40E_NVM_WRITE 0xC
327
328 #define I40E_NVM_MOD_PNT_MASK 0xFF
329
330 #define I40E_NVM_TRANS_SHIFT 8
331 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
332 #define I40E_NVM_CON 0x0
333 #define I40E_NVM_SNT 0x1
334 #define I40E_NVM_LCB 0x2
335 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
336 #define I40E_NVM_ERA 0x4
337 #define I40E_NVM_CSUM 0x8
338 #define I40E_NVM_EXEC 0xf
339
340 #define I40E_NVM_ADAPT_SHIFT 16
341 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
342
343 #define I40E_NVMUPD_MAX_DATA 4096
344 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
345
346 struct i40e_nvm_access {
347 u32 command;
348 u32 config;
349 u32 offset; /* in bytes */
350 u32 data_size; /* in bytes */
351 u8 data[1];
352 };
353
354 /* PCI bus types */
355 enum i40e_bus_type {
356 i40e_bus_type_unknown = 0,
357 i40e_bus_type_pci,
358 i40e_bus_type_pcix,
359 i40e_bus_type_pci_express,
360 i40e_bus_type_reserved
361 };
362
363 /* PCI bus speeds */
364 enum i40e_bus_speed {
365 i40e_bus_speed_unknown = 0,
366 i40e_bus_speed_33 = 33,
367 i40e_bus_speed_66 = 66,
368 i40e_bus_speed_100 = 100,
369 i40e_bus_speed_120 = 120,
370 i40e_bus_speed_133 = 133,
371 i40e_bus_speed_2500 = 2500,
372 i40e_bus_speed_5000 = 5000,
373 i40e_bus_speed_8000 = 8000,
374 i40e_bus_speed_reserved
375 };
376
377 /* PCI bus widths */
378 enum i40e_bus_width {
379 i40e_bus_width_unknown = 0,
380 i40e_bus_width_pcie_x1 = 1,
381 i40e_bus_width_pcie_x2 = 2,
382 i40e_bus_width_pcie_x4 = 4,
383 i40e_bus_width_pcie_x8 = 8,
384 i40e_bus_width_32 = 32,
385 i40e_bus_width_64 = 64,
386 i40e_bus_width_reserved
387 };
388
389 /* Bus parameters */
390 struct i40e_bus_info {
391 enum i40e_bus_speed speed;
392 enum i40e_bus_width width;
393 enum i40e_bus_type type;
394
395 u16 func;
396 u16 device;
397 u16 lan_id;
398 };
399
400 /* Flow control (FC) parameters */
401 struct i40e_fc_info {
402 enum i40e_fc_mode current_mode; /* FC mode in effect */
403 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
404 };
405
406 #define I40E_MAX_TRAFFIC_CLASS 8
407 #define I40E_MAX_USER_PRIORITY 8
408 #define I40E_DCBX_MAX_APPS 32
409 #define I40E_LLDPDU_SIZE 1500
410 #define I40E_TLV_STATUS_OPER 0x1
411 #define I40E_TLV_STATUS_SYNC 0x2
412 #define I40E_TLV_STATUS_ERR 0x4
413 #define I40E_CEE_OPER_MAX_APPS 3
414 #define I40E_APP_PROTOID_FCOE 0x8906
415 #define I40E_APP_PROTOID_ISCSI 0x0cbc
416 #define I40E_APP_PROTOID_FIP 0x8914
417 #define I40E_APP_SEL_ETHTYPE 0x1
418 #define I40E_APP_SEL_TCPIP 0x2
419
420 /* CEE or IEEE 802.1Qaz ETS Configuration data */
421 struct i40e_dcb_ets_config {
422 u8 willing;
423 u8 cbs;
424 u8 maxtcs;
425 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
426 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
427 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
428 };
429
430 /* CEE or IEEE 802.1Qaz PFC Configuration data */
431 struct i40e_dcb_pfc_config {
432 u8 willing;
433 u8 mbc;
434 u8 pfccap;
435 u8 pfcenable;
436 };
437
438 /* CEE or IEEE 802.1Qaz Application Priority data */
439 struct i40e_dcb_app_priority_table {
440 u8 priority;
441 u8 selector;
442 u16 protocolid;
443 };
444
445 struct i40e_dcbx_config {
446 u8 dcbx_mode;
447 #define I40E_DCBX_MODE_CEE 0x1
448 #define I40E_DCBX_MODE_IEEE 0x2
449 u32 numapps;
450 u32 tlv_status; /* CEE mode TLV status */
451 struct i40e_dcb_ets_config etscfg;
452 struct i40e_dcb_ets_config etsrec;
453 struct i40e_dcb_pfc_config pfc;
454 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
455 };
456
457 /* Port hardware description */
458 struct i40e_hw {
459 u8 __iomem *hw_addr;
460 void *back;
461
462 /* subsystem structs */
463 struct i40e_phy_info phy;
464 struct i40e_mac_info mac;
465 struct i40e_bus_info bus;
466 struct i40e_nvm_info nvm;
467 struct i40e_fc_info fc;
468
469 /* pci info */
470 u16 device_id;
471 u16 vendor_id;
472 u16 subsystem_device_id;
473 u16 subsystem_vendor_id;
474 u8 revision_id;
475 u8 port;
476 bool adapter_stopped;
477
478 /* capabilities for entire device and PCI func */
479 struct i40e_hw_capabilities dev_caps;
480 struct i40e_hw_capabilities func_caps;
481
482 /* Flow Director shared filter space */
483 u16 fdir_shared_filter_count;
484
485 /* device profile info */
486 u8 pf_id;
487 u16 main_vsi_seid;
488
489 /* for multi-function MACs */
490 u16 partition_id;
491 u16 num_partitions;
492 u16 num_ports;
493
494 /* Closest numa node to the device */
495 u16 numa_node;
496
497 /* Admin Queue info */
498 struct i40e_adminq_info aq;
499
500 /* state of nvm update process */
501 enum i40e_nvmupd_state nvmupd_state;
502 struct i40e_aq_desc nvm_wb_desc;
503 struct i40e_virt_mem nvm_buff;
504
505 /* HMC info */
506 struct i40e_hmc_info hmc; /* HMC info struct */
507
508 /* LLDP/DCBX Status */
509 u16 dcbx_status;
510
511 /* DCBX info */
512 struct i40e_dcbx_config local_dcbx_config;
513 struct i40e_dcbx_config remote_dcbx_config;
514
515 /* debug mask */
516 u32 debug_mask;
517 char err_str[16];
518 };
519
520 static inline bool i40e_is_vf(struct i40e_hw *hw)
521 {
522 return (hw->mac.type == I40E_MAC_VF ||
523 hw->mac.type == I40E_MAC_X722_VF);
524 }
525
526 struct i40e_driver_version {
527 u8 major_version;
528 u8 minor_version;
529 u8 build_version;
530 u8 subbuild_version;
531 u8 driver_string[32];
532 };
533
534 /* RX Descriptors */
535 union i40e_16byte_rx_desc {
536 struct {
537 __le64 pkt_addr; /* Packet buffer address */
538 __le64 hdr_addr; /* Header buffer address */
539 } read;
540 struct {
541 struct {
542 struct {
543 union {
544 __le16 mirroring_status;
545 __le16 fcoe_ctx_id;
546 } mirr_fcoe;
547 __le16 l2tag1;
548 } lo_dword;
549 union {
550 __le32 rss; /* RSS Hash */
551 __le32 fd_id; /* Flow director filter id */
552 __le32 fcoe_param; /* FCoE DDP Context id */
553 } hi_dword;
554 } qword0;
555 struct {
556 /* ext status/error/pktype/length */
557 __le64 status_error_len;
558 } qword1;
559 } wb; /* writeback */
560 };
561
562 union i40e_32byte_rx_desc {
563 struct {
564 __le64 pkt_addr; /* Packet buffer address */
565 __le64 hdr_addr; /* Header buffer address */
566 /* bit 0 of hdr_buffer_addr is DD bit */
567 __le64 rsvd1;
568 __le64 rsvd2;
569 } read;
570 struct {
571 struct {
572 struct {
573 union {
574 __le16 mirroring_status;
575 __le16 fcoe_ctx_id;
576 } mirr_fcoe;
577 __le16 l2tag1;
578 } lo_dword;
579 union {
580 __le32 rss; /* RSS Hash */
581 __le32 fcoe_param; /* FCoE DDP Context id */
582 /* Flow director filter id in case of
583 * Programming status desc WB
584 */
585 __le32 fd_id;
586 } hi_dword;
587 } qword0;
588 struct {
589 /* status/error/pktype/length */
590 __le64 status_error_len;
591 } qword1;
592 struct {
593 __le16 ext_status; /* extended status */
594 __le16 rsvd;
595 __le16 l2tag2_1;
596 __le16 l2tag2_2;
597 } qword2;
598 struct {
599 union {
600 __le32 flex_bytes_lo;
601 __le32 pe_status;
602 } lo_dword;
603 union {
604 __le32 flex_bytes_hi;
605 __le32 fd_id;
606 } hi_dword;
607 } qword3;
608 } wb; /* writeback */
609 };
610
611 enum i40e_rx_desc_status_bits {
612 /* Note: These are predefined bit offsets */
613 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
614 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
615 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
616 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
617 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
618 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
619 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
620 /* Note: Bit 8 is reserved in X710 and XL710 */
621 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
622 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
623 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
624 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
625 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
626 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
627 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
628 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
629 * UDP header
630 */
631 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
632 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
633 };
634
635 #define I40E_RXD_QW1_STATUS_SHIFT 0
636 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
637 << I40E_RXD_QW1_STATUS_SHIFT)
638
639 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
640 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
641 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
642
643 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
644 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
645 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
646
647 enum i40e_rx_desc_fltstat_values {
648 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
649 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
650 I40E_RX_DESC_FLTSTAT_RSV = 2,
651 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
652 };
653
654 #define I40E_RXD_QW1_ERROR_SHIFT 19
655 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
656
657 enum i40e_rx_desc_error_bits {
658 /* Note: These are predefined bit offsets */
659 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
660 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
661 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
662 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
663 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
664 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
665 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
666 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
667 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
668 };
669
670 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
671 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
672 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
673 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
674 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
675 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
676 };
677
678 #define I40E_RXD_QW1_PTYPE_SHIFT 30
679 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
680
681 /* Packet type non-ip values */
682 enum i40e_rx_l2_ptype {
683 I40E_RX_PTYPE_L2_RESERVED = 0,
684 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
685 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
686 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
687 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
688 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
689 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
690 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
691 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
692 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
693 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
694 I40E_RX_PTYPE_L2_ARP = 11,
695 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
696 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
697 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
698 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
699 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
700 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
701 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
702 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
703 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
704 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
705 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
706 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
707 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
708 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
709 };
710
711 struct i40e_rx_ptype_decoded {
712 u32 ptype:8;
713 u32 known:1;
714 u32 outer_ip:1;
715 u32 outer_ip_ver:1;
716 u32 outer_frag:1;
717 u32 tunnel_type:3;
718 u32 tunnel_end_prot:2;
719 u32 tunnel_end_frag:1;
720 u32 inner_prot:4;
721 u32 payload_layer:3;
722 };
723
724 enum i40e_rx_ptype_outer_ip {
725 I40E_RX_PTYPE_OUTER_L2 = 0,
726 I40E_RX_PTYPE_OUTER_IP = 1
727 };
728
729 enum i40e_rx_ptype_outer_ip_ver {
730 I40E_RX_PTYPE_OUTER_NONE = 0,
731 I40E_RX_PTYPE_OUTER_IPV4 = 0,
732 I40E_RX_PTYPE_OUTER_IPV6 = 1
733 };
734
735 enum i40e_rx_ptype_outer_fragmented {
736 I40E_RX_PTYPE_NOT_FRAG = 0,
737 I40E_RX_PTYPE_FRAG = 1
738 };
739
740 enum i40e_rx_ptype_tunnel_type {
741 I40E_RX_PTYPE_TUNNEL_NONE = 0,
742 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
743 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
744 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
745 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
746 };
747
748 enum i40e_rx_ptype_tunnel_end_prot {
749 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
750 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
751 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
752 };
753
754 enum i40e_rx_ptype_inner_prot {
755 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
756 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
757 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
758 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
759 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
760 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
761 };
762
763 enum i40e_rx_ptype_payload_layer {
764 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
765 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
766 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
767 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
768 };
769
770 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
771 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
772 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
773
774 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
775 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
776 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
777
778 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
779 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
780
781 enum i40e_rx_desc_ext_status_bits {
782 /* Note: These are predefined bit offsets */
783 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
784 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
785 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
786 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
787 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
788 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
789 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
790 };
791
792 enum i40e_rx_desc_pe_status_bits {
793 /* Note: These are predefined bit offsets */
794 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
795 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
796 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
797 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
798 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
799 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
800 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
801 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
802 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
803 };
804
805 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
806 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
807
808 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
809 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
810 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
811
812 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
813 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
814 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
815
816 enum i40e_rx_prog_status_desc_status_bits {
817 /* Note: These are predefined bit offsets */
818 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
819 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
820 };
821
822 enum i40e_rx_prog_status_desc_prog_id_masks {
823 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
824 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
825 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
826 };
827
828 enum i40e_rx_prog_status_desc_error_bits {
829 /* Note: These are predefined bit offsets */
830 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
831 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
832 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
833 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
834 };
835
836 /* TX Descriptor */
837 struct i40e_tx_desc {
838 __le64 buffer_addr; /* Address of descriptor's data buf */
839 __le64 cmd_type_offset_bsz;
840 };
841
842 #define I40E_TXD_QW1_DTYPE_SHIFT 0
843 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
844
845 enum i40e_tx_desc_dtype_value {
846 I40E_TX_DESC_DTYPE_DATA = 0x0,
847 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
848 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
849 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
850 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
851 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
852 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
853 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
854 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
855 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
856 };
857
858 #define I40E_TXD_QW1_CMD_SHIFT 4
859 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
860
861 enum i40e_tx_desc_cmd_bits {
862 I40E_TX_DESC_CMD_EOP = 0x0001,
863 I40E_TX_DESC_CMD_RS = 0x0002,
864 I40E_TX_DESC_CMD_ICRC = 0x0004,
865 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
866 I40E_TX_DESC_CMD_DUMMY = 0x0010,
867 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
868 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
869 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
870 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
871 I40E_TX_DESC_CMD_FCOET = 0x0080,
872 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
873 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
874 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
875 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
876 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
877 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
878 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
879 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
880 };
881
882 #define I40E_TXD_QW1_OFFSET_SHIFT 16
883 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
884 I40E_TXD_QW1_OFFSET_SHIFT)
885
886 enum i40e_tx_desc_length_fields {
887 /* Note: These are predefined bit offsets */
888 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
889 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
890 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
891 };
892
893 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
894 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
895 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
896
897 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
898 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
899
900 /* Context descriptors */
901 struct i40e_tx_context_desc {
902 __le32 tunneling_params;
903 __le16 l2tag2;
904 __le16 rsvd;
905 __le64 type_cmd_tso_mss;
906 };
907
908 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
909 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
910
911 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
912 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
913
914 enum i40e_tx_ctx_desc_cmd_bits {
915 I40E_TX_CTX_DESC_TSO = 0x01,
916 I40E_TX_CTX_DESC_TSYN = 0x02,
917 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
918 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
919 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
920 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
921 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
922 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
923 I40E_TX_CTX_DESC_SWPE = 0x40
924 };
925
926 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
927 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
928 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
929
930 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
931 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
932 I40E_TXD_CTX_QW1_MSS_SHIFT)
933
934 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
935 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
936
937 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
938 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
939 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
940
941 enum i40e_tx_ctx_desc_eipt_offload {
942 I40E_TX_CTX_EXT_IP_NONE = 0x0,
943 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
944 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
945 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
946 };
947
948 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
949 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
950 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
951
952 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
953 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
954
955 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
956 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
957
958 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
959 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
960 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
961
962 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
963
964 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
965 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
966 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
967
968 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
969 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
970 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
971
972 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
973 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
974 struct i40e_filter_program_desc {
975 __le32 qindex_flex_ptype_vsi;
976 __le32 rsvd;
977 __le32 dtype_cmd_cntindex;
978 __le32 fd_id;
979 };
980 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
981 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
982 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
983 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
984 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
985 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
986 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
987 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
988 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
989
990 /* Packet Classifier Types for filters */
991 enum i40e_filter_pctype {
992 /* Note: Values 0-28 are reserved for future use.
993 * Value 29, 30, 32 are not supported on XL710 and X710.
994 */
995 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
996 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
997 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
998 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
999 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1000 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1001 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1002 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1003 /* Note: Values 37-38 are reserved for future use.
1004 * Value 39, 40, 42 are not supported on XL710 and X710.
1005 */
1006 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1007 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1008 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1009 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1010 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1011 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1012 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1013 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1014 /* Note: Value 47 is reserved for future use */
1015 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1016 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1017 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1018 /* Note: Values 51-62 are reserved for future use */
1019 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1020 };
1021
1022 enum i40e_filter_program_desc_dest {
1023 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1024 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1025 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1026 };
1027
1028 enum i40e_filter_program_desc_fd_status {
1029 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1030 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1031 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1032 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1033 };
1034
1035 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1036 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1037 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1038
1039 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1040 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1041 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1042
1043 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1044 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1045
1046 enum i40e_filter_program_desc_pcmd {
1047 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1048 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1049 };
1050
1051 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1052 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1053
1054 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1055 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1056
1057 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1058 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1059 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1060 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1061
1062 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1063 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1064 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1065
1066 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1067 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1068 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1069
1070 enum i40e_filter_type {
1071 I40E_FLOW_DIRECTOR_FLTR = 0,
1072 I40E_PE_QUAD_HASH_FLTR = 1,
1073 I40E_ETHERTYPE_FLTR,
1074 I40E_FCOE_CTX_FLTR,
1075 I40E_MAC_VLAN_FLTR,
1076 I40E_HASH_FLTR
1077 };
1078
1079 struct i40e_vsi_context {
1080 u16 seid;
1081 u16 uplink_seid;
1082 u16 vsi_number;
1083 u16 vsis_allocated;
1084 u16 vsis_unallocated;
1085 u16 flags;
1086 u8 pf_num;
1087 u8 vf_num;
1088 u8 connection_type;
1089 struct i40e_aqc_vsi_properties_data info;
1090 };
1091
1092 struct i40e_veb_context {
1093 u16 seid;
1094 u16 uplink_seid;
1095 u16 veb_number;
1096 u16 vebs_allocated;
1097 u16 vebs_unallocated;
1098 u16 flags;
1099 struct i40e_aqc_get_veb_parameters_completion info;
1100 };
1101
1102 /* Statistics collected by each port, VSI, VEB, and S-channel */
1103 struct i40e_eth_stats {
1104 u64 rx_bytes; /* gorc */
1105 u64 rx_unicast; /* uprc */
1106 u64 rx_multicast; /* mprc */
1107 u64 rx_broadcast; /* bprc */
1108 u64 rx_discards; /* rdpc */
1109 u64 rx_unknown_protocol; /* rupp */
1110 u64 tx_bytes; /* gotc */
1111 u64 tx_unicast; /* uptc */
1112 u64 tx_multicast; /* mptc */
1113 u64 tx_broadcast; /* bptc */
1114 u64 tx_discards; /* tdpc */
1115 u64 tx_errors; /* tepc */
1116 };
1117
1118 /* Statistics collected per VEB per TC */
1119 struct i40e_veb_tc_stats {
1120 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1121 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1122 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1123 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1124 };
1125
1126 #ifdef I40E_FCOE
1127 /* Statistics collected per function for FCoE */
1128 struct i40e_fcoe_stats {
1129 u64 rx_fcoe_packets; /* fcoeprc */
1130 u64 rx_fcoe_dwords; /* focedwrc */
1131 u64 rx_fcoe_dropped; /* fcoerpdc */
1132 u64 tx_fcoe_packets; /* fcoeptc */
1133 u64 tx_fcoe_dwords; /* focedwtc */
1134 u64 fcoe_bad_fccrc; /* fcoecrc */
1135 u64 fcoe_last_error; /* fcoelast */
1136 u64 fcoe_ddp_count; /* fcoeddpc */
1137 };
1138
1139 /* offset to per function FCoE statistics block */
1140 #define I40E_FCOE_VF_STAT_OFFSET 0
1141 #define I40E_FCOE_PF_STAT_OFFSET 128
1142 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1143
1144 #endif
1145 /* Statistics collected by the MAC */
1146 struct i40e_hw_port_stats {
1147 /* eth stats collected by the port */
1148 struct i40e_eth_stats eth;
1149
1150 /* additional port specific stats */
1151 u64 tx_dropped_link_down; /* tdold */
1152 u64 crc_errors; /* crcerrs */
1153 u64 illegal_bytes; /* illerrc */
1154 u64 error_bytes; /* errbc */
1155 u64 mac_local_faults; /* mlfc */
1156 u64 mac_remote_faults; /* mrfc */
1157 u64 rx_length_errors; /* rlec */
1158 u64 link_xon_rx; /* lxonrxc */
1159 u64 link_xoff_rx; /* lxoffrxc */
1160 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1161 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1162 u64 link_xon_tx; /* lxontxc */
1163 u64 link_xoff_tx; /* lxofftxc */
1164 u64 priority_xon_tx[8]; /* pxontxc[8] */
1165 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1166 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1167 u64 rx_size_64; /* prc64 */
1168 u64 rx_size_127; /* prc127 */
1169 u64 rx_size_255; /* prc255 */
1170 u64 rx_size_511; /* prc511 */
1171 u64 rx_size_1023; /* prc1023 */
1172 u64 rx_size_1522; /* prc1522 */
1173 u64 rx_size_big; /* prc9522 */
1174 u64 rx_undersize; /* ruc */
1175 u64 rx_fragments; /* rfc */
1176 u64 rx_oversize; /* roc */
1177 u64 rx_jabber; /* rjc */
1178 u64 tx_size_64; /* ptc64 */
1179 u64 tx_size_127; /* ptc127 */
1180 u64 tx_size_255; /* ptc255 */
1181 u64 tx_size_511; /* ptc511 */
1182 u64 tx_size_1023; /* ptc1023 */
1183 u64 tx_size_1522; /* ptc1522 */
1184 u64 tx_size_big; /* ptc9522 */
1185 u64 mac_short_packet_dropped; /* mspdc */
1186 u64 checksum_error; /* xec */
1187 /* flow director stats */
1188 u64 fd_atr_match;
1189 u64 fd_sb_match;
1190 u64 fd_atr_tunnel_match;
1191 u32 fd_atr_status;
1192 u32 fd_sb_status;
1193 /* EEE LPI */
1194 u32 tx_lpi_status;
1195 u32 rx_lpi_status;
1196 u64 tx_lpi_count; /* etlpic */
1197 u64 rx_lpi_count; /* erlpic */
1198 };
1199
1200 /* Checksum and Shadow RAM pointers */
1201 #define I40E_SR_NVM_CONTROL_WORD 0x00
1202 #define I40E_SR_EMP_MODULE_PTR 0x0F
1203 #define I40E_SR_PBA_FLAGS 0x15
1204 #define I40E_SR_PBA_BLOCK_PTR 0x16
1205 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1206 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1207 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1208 #define I40E_SR_NVM_EETRACK_LO 0x2D
1209 #define I40E_SR_NVM_EETRACK_HI 0x2E
1210 #define I40E_SR_VPD_PTR 0x2F
1211 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1212 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1213
1214 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1215 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1216 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1217 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1218 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1219
1220 /* Shadow RAM related */
1221 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1222 #define I40E_SR_WORDS_IN_1KB 512
1223 /* Checksum should be calculated such that after adding all the words,
1224 * including the checksum word itself, the sum should be 0xBABA.
1225 */
1226 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1227
1228 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1229
1230 #ifdef I40E_FCOE
1231 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1232
1233 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1234 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1235 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1236 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1237 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1238 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1239 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1240 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1241 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1242 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1243 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1244 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1245 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1246 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1247 };
1248
1249 /* FCoE DDP Context descriptor */
1250 struct i40e_fcoe_ddp_context_desc {
1251 __le64 rsvd;
1252 __le64 type_cmd_foff_lsize;
1253 };
1254
1255 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1256 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1257 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1258
1259 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1260 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1261 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1262
1263 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1264 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1265 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1266 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1267 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1268 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1269 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1270 };
1271
1272 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1273 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1274 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1275
1276 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1277 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1278 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1279
1280 /* FCoE DDP/DWO Queue Context descriptor */
1281 struct i40e_fcoe_queue_context_desc {
1282 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1283 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1284 };
1285
1286 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1287 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1288 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1289
1290 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1291 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1292 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1293
1294 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1295 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1296 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1297
1298 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1299 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1300 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1301
1302 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1303 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1304 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1305 };
1306
1307 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1308 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1309 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1310
1311 /* FCoE DDP/DWO Filter Context descriptor */
1312 struct i40e_fcoe_filter_context_desc {
1313 __le32 param;
1314 __le16 seqn;
1315
1316 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1317 __le16 rsvd_dmaindx;
1318
1319 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1320 __le64 flags_rsvd_lanq;
1321 };
1322
1323 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1324 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1325 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1326
1327 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1328 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1329 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1330 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1331 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1332 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1333 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1334 };
1335
1336 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1337 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1338 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1339
1340 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1341 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1342 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1343
1344 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1345 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1346 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1347
1348 #endif /* I40E_FCOE */
1349 enum i40e_switch_element_types {
1350 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1351 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1352 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1353 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1354 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1355 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1356 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1357 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1358 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1359 };
1360
1361 /* Supported EtherType filters */
1362 enum i40e_ether_type_index {
1363 I40E_ETHER_TYPE_1588 = 0,
1364 I40E_ETHER_TYPE_FIP = 1,
1365 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1366 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1367 I40E_ETHER_TYPE_LLDP = 4,
1368 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1369 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1370 I40E_ETHER_TYPE_QCN_CNM = 7,
1371 I40E_ETHER_TYPE_8021X = 8,
1372 I40E_ETHER_TYPE_ARP = 9,
1373 I40E_ETHER_TYPE_RSV1 = 10,
1374 I40E_ETHER_TYPE_RSV2 = 11,
1375 };
1376
1377 /* Filter context base size is 1K */
1378 #define I40E_HASH_FILTER_BASE_SIZE 1024
1379 /* Supported Hash filter values */
1380 enum i40e_hash_filter_size {
1381 I40E_HASH_FILTER_SIZE_1K = 0,
1382 I40E_HASH_FILTER_SIZE_2K = 1,
1383 I40E_HASH_FILTER_SIZE_4K = 2,
1384 I40E_HASH_FILTER_SIZE_8K = 3,
1385 I40E_HASH_FILTER_SIZE_16K = 4,
1386 I40E_HASH_FILTER_SIZE_32K = 5,
1387 I40E_HASH_FILTER_SIZE_64K = 6,
1388 I40E_HASH_FILTER_SIZE_128K = 7,
1389 I40E_HASH_FILTER_SIZE_256K = 8,
1390 I40E_HASH_FILTER_SIZE_512K = 9,
1391 I40E_HASH_FILTER_SIZE_1M = 10,
1392 };
1393
1394 /* DMA context base size is 0.5K */
1395 #define I40E_DMA_CNTX_BASE_SIZE 512
1396 /* Supported DMA context values */
1397 enum i40e_dma_cntx_size {
1398 I40E_DMA_CNTX_SIZE_512 = 0,
1399 I40E_DMA_CNTX_SIZE_1K = 1,
1400 I40E_DMA_CNTX_SIZE_2K = 2,
1401 I40E_DMA_CNTX_SIZE_4K = 3,
1402 I40E_DMA_CNTX_SIZE_8K = 4,
1403 I40E_DMA_CNTX_SIZE_16K = 5,
1404 I40E_DMA_CNTX_SIZE_32K = 6,
1405 I40E_DMA_CNTX_SIZE_64K = 7,
1406 I40E_DMA_CNTX_SIZE_128K = 8,
1407 I40E_DMA_CNTX_SIZE_256K = 9,
1408 };
1409
1410 /* Supported Hash look up table (LUT) sizes */
1411 enum i40e_hash_lut_size {
1412 I40E_HASH_LUT_SIZE_128 = 0,
1413 I40E_HASH_LUT_SIZE_512 = 1,
1414 };
1415
1416 /* Structure to hold a per PF filter control settings */
1417 struct i40e_filter_control_settings {
1418 /* number of PE Quad Hash filter buckets */
1419 enum i40e_hash_filter_size pe_filt_num;
1420 /* number of PE Quad Hash contexts */
1421 enum i40e_dma_cntx_size pe_cntx_num;
1422 /* number of FCoE filter buckets */
1423 enum i40e_hash_filter_size fcoe_filt_num;
1424 /* number of FCoE DDP contexts */
1425 enum i40e_dma_cntx_size fcoe_cntx_num;
1426 /* size of the Hash LUT */
1427 enum i40e_hash_lut_size hash_lut_size;
1428 /* enable FDIR filters for PF and its VFs */
1429 bool enable_fdir;
1430 /* enable Ethertype filters for PF and its VFs */
1431 bool enable_ethtype;
1432 /* enable MAC/VLAN filters for PF and its VFs */
1433 bool enable_macvlan;
1434 };
1435
1436 /* Structure to hold device level control filter counts */
1437 struct i40e_control_filter_stats {
1438 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1439 u16 etype_used; /* Used perfect EtherType filters */
1440 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1441 u16 etype_free; /* Un-used perfect EtherType filters */
1442 };
1443
1444 enum i40e_reset_type {
1445 I40E_RESET_POR = 0,
1446 I40E_RESET_CORER = 1,
1447 I40E_RESET_GLOBR = 2,
1448 I40E_RESET_EMPR = 3,
1449 };
1450
1451 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1452 #define I40E_NVM_LLDP_CFG_PTR 0xD
1453 struct i40e_lldp_variables {
1454 u16 length;
1455 u16 adminstatus;
1456 u16 msgfasttx;
1457 u16 msgtxinterval;
1458 u16 txparams;
1459 u16 timers;
1460 u16 crc8;
1461 };
1462
1463 /* Offsets into Alternate Ram */
1464 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1465 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1466 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1467 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1468 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1469 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1470
1471 /* Alternate Ram Bandwidth Masks */
1472 #define I40E_ALT_BW_VALUE_MASK 0xFF
1473 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1474 #define I40E_ALT_BW_VALID_MASK 0x80000000
1475
1476 /* RSS Hash Table Size */
1477 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1478 #endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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