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Merge branch 'net/rds/4.3-v3' of git://git.kernel.org/pub/scm/linux/kernel/git/ssanto...
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_type.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36
37 /* Device IDs */
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_20G_KR2 0x1587
48 #define I40E_DEV_ID_20G_KR2_A 0x1588
49 #define I40E_DEV_ID_10G_BASE_T4 0x1589
50 #define I40E_DEV_ID_VF 0x154C
51 #define I40E_DEV_ID_VF_HV 0x1571
52 #define I40E_DEV_ID_SFP_X722 0x37D0
53 #define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
54 #define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
55 #define I40E_DEV_ID_X722_VF 0x37CD
56 #define I40E_DEV_ID_X722_VF_HV 0x37D9
57
58 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
59 (d) == I40E_DEV_ID_QSFP_B || \
60 (d) == I40E_DEV_ID_QSFP_C)
61
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
64
65 #define I40E_MAX_VSI_QP 16
66 #define I40E_MAX_VF_VSI 3
67 #define I40E_MAX_CHAINED_RX_BUFFERS 5
68 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
69
70 /* Max default timeout in ms, */
71 #define I40E_MAX_NVM_TIMEOUT 18000
72
73 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
74 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
75
76 /* forward declaration */
77 struct i40e_hw;
78 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
79
80 /* Data type manipulation macros. */
81
82 #define I40E_DESC_UNUSED(R) \
83 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
84 (R)->next_to_clean - (R)->next_to_use - 1)
85
86 /* bitfields for Tx queue mapping in QTX_CTL */
87 #define I40E_QTX_CTL_VF_QUEUE 0x0
88 #define I40E_QTX_CTL_VM_QUEUE 0x1
89 #define I40E_QTX_CTL_PF_QUEUE 0x2
90
91 /* debug masks - set these bits in hw->debug_mask to control output */
92 enum i40e_debug_mask {
93 I40E_DEBUG_INIT = 0x00000001,
94 I40E_DEBUG_RELEASE = 0x00000002,
95
96 I40E_DEBUG_LINK = 0x00000010,
97 I40E_DEBUG_PHY = 0x00000020,
98 I40E_DEBUG_HMC = 0x00000040,
99 I40E_DEBUG_NVM = 0x00000080,
100 I40E_DEBUG_LAN = 0x00000100,
101 I40E_DEBUG_FLOW = 0x00000200,
102 I40E_DEBUG_DCB = 0x00000400,
103 I40E_DEBUG_DIAG = 0x00000800,
104 I40E_DEBUG_FD = 0x00001000,
105
106 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
107 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
108 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
109 I40E_DEBUG_AQ_COMMAND = 0x06000000,
110 I40E_DEBUG_AQ = 0x0F000000,
111
112 I40E_DEBUG_USER = 0xF0000000,
113
114 I40E_DEBUG_ALL = 0xFFFFFFFF
115 };
116
117 /* These are structs for managing the hardware information and the operations.
118 * The structures of function pointers are filled out at init time when we
119 * know for sure exactly which hardware we're working with. This gives us the
120 * flexibility of using the same main driver code but adapting to slightly
121 * different hardware needs as new parts are developed. For this architecture,
122 * the Firmware and AdminQ are intended to insulate the driver from most of the
123 * future changes, but these structures will also do part of the job.
124 */
125 enum i40e_mac_type {
126 I40E_MAC_UNKNOWN = 0,
127 I40E_MAC_X710,
128 I40E_MAC_XL710,
129 I40E_MAC_VF,
130 I40E_MAC_X722,
131 I40E_MAC_X722_VF,
132 I40E_MAC_GENERIC,
133 };
134
135 enum i40e_media_type {
136 I40E_MEDIA_TYPE_UNKNOWN = 0,
137 I40E_MEDIA_TYPE_FIBER,
138 I40E_MEDIA_TYPE_BASET,
139 I40E_MEDIA_TYPE_BACKPLANE,
140 I40E_MEDIA_TYPE_CX4,
141 I40E_MEDIA_TYPE_DA,
142 I40E_MEDIA_TYPE_VIRTUAL
143 };
144
145 enum i40e_fc_mode {
146 I40E_FC_NONE = 0,
147 I40E_FC_RX_PAUSE,
148 I40E_FC_TX_PAUSE,
149 I40E_FC_FULL,
150 I40E_FC_PFC,
151 I40E_FC_DEFAULT
152 };
153
154 enum i40e_set_fc_aq_failures {
155 I40E_SET_FC_AQ_FAIL_NONE = 0,
156 I40E_SET_FC_AQ_FAIL_GET = 1,
157 I40E_SET_FC_AQ_FAIL_SET = 2,
158 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
159 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
160 };
161
162 enum i40e_vsi_type {
163 I40E_VSI_MAIN = 0,
164 I40E_VSI_VMDQ1,
165 I40E_VSI_VMDQ2,
166 I40E_VSI_CTRL,
167 I40E_VSI_FCOE,
168 I40E_VSI_MIRROR,
169 I40E_VSI_SRIOV,
170 I40E_VSI_FDIR,
171 I40E_VSI_TYPE_UNKNOWN
172 };
173
174 enum i40e_queue_type {
175 I40E_QUEUE_TYPE_RX = 0,
176 I40E_QUEUE_TYPE_TX,
177 I40E_QUEUE_TYPE_PE_CEQ,
178 I40E_QUEUE_TYPE_UNKNOWN
179 };
180
181 struct i40e_link_status {
182 enum i40e_aq_phy_type phy_type;
183 enum i40e_aq_link_speed link_speed;
184 u8 link_info;
185 u8 an_info;
186 u8 ext_info;
187 u8 loopback;
188 /* is Link Status Event notification to SW enabled */
189 bool lse_enable;
190 u16 max_frame_size;
191 bool crc_enable;
192 u8 pacing;
193 u8 requested_speeds;
194 };
195
196 struct i40e_phy_info {
197 struct i40e_link_status link_info;
198 struct i40e_link_status link_info_old;
199 u32 autoneg_advertised;
200 u32 phy_id;
201 u32 module_type;
202 bool get_link_info;
203 enum i40e_media_type media_type;
204 };
205
206 #define I40E_HW_CAP_MAX_GPIO 30
207 /* Capabilities of a PF or a VF or the whole device */
208 struct i40e_hw_capabilities {
209 u32 switch_mode;
210 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
211 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
212 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
213
214 u32 management_mode;
215 u32 npar_enable;
216 u32 os2bmc;
217 u32 valid_functions;
218 bool sr_iov_1_1;
219 bool vmdq;
220 bool evb_802_1_qbg; /* Edge Virtual Bridging */
221 bool evb_802_1_qbh; /* Bridge Port Extension */
222 bool dcb;
223 bool fcoe;
224 bool iscsi; /* Indicates iSCSI enabled */
225 bool flex10_enable;
226 bool flex10_capable;
227 u32 flex10_mode;
228 #define I40E_FLEX10_MODE_UNKNOWN 0x0
229 #define I40E_FLEX10_MODE_DCC 0x1
230 #define I40E_FLEX10_MODE_DCI 0x2
231
232 u32 flex10_status;
233 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
234 #define I40E_FLEX10_STATUS_VC_MODE 0x2
235
236 bool mgmt_cem;
237 bool ieee_1588;
238 bool iwarp;
239 bool fd;
240 u32 fd_filters_guaranteed;
241 u32 fd_filters_best_effort;
242 bool rss;
243 u32 rss_table_size;
244 u32 rss_table_entry_width;
245 bool led[I40E_HW_CAP_MAX_GPIO];
246 bool sdp[I40E_HW_CAP_MAX_GPIO];
247 u32 nvm_image_type;
248 u32 num_flow_director_filters;
249 u32 num_vfs;
250 u32 vf_base_id;
251 u32 num_vsis;
252 u32 num_rx_qp;
253 u32 num_tx_qp;
254 u32 base_queue;
255 u32 num_msix_vectors;
256 u32 num_msix_vectors_vf;
257 u32 led_pin_num;
258 u32 sdp_pin_num;
259 u32 mdio_port_num;
260 u32 mdio_port_mode;
261 u8 rx_buf_chain_len;
262 u32 enabled_tcmap;
263 u32 maxtc;
264 u64 wr_csr_prot;
265 };
266
267 struct i40e_mac_info {
268 enum i40e_mac_type type;
269 u8 addr[ETH_ALEN];
270 u8 perm_addr[ETH_ALEN];
271 u8 san_addr[ETH_ALEN];
272 u8 port_addr[ETH_ALEN];
273 u16 max_fcoeq;
274 };
275
276 enum i40e_aq_resources_ids {
277 I40E_NVM_RESOURCE_ID = 1
278 };
279
280 enum i40e_aq_resource_access_type {
281 I40E_RESOURCE_READ = 1,
282 I40E_RESOURCE_WRITE
283 };
284
285 struct i40e_nvm_info {
286 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
287 u32 timeout; /* [ms] */
288 u16 sr_size; /* Shadow RAM size in words */
289 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
290 u16 version; /* NVM package version */
291 u32 eetrack; /* NVM data version */
292 };
293
294 /* definitions used in NVM update support */
295
296 enum i40e_nvmupd_cmd {
297 I40E_NVMUPD_INVALID,
298 I40E_NVMUPD_READ_CON,
299 I40E_NVMUPD_READ_SNT,
300 I40E_NVMUPD_READ_LCB,
301 I40E_NVMUPD_READ_SA,
302 I40E_NVMUPD_WRITE_ERA,
303 I40E_NVMUPD_WRITE_CON,
304 I40E_NVMUPD_WRITE_SNT,
305 I40E_NVMUPD_WRITE_LCB,
306 I40E_NVMUPD_WRITE_SA,
307 I40E_NVMUPD_CSUM_CON,
308 I40E_NVMUPD_CSUM_SA,
309 I40E_NVMUPD_CSUM_LCB,
310 I40E_NVMUPD_STATUS,
311 I40E_NVMUPD_EXEC_AQ,
312 I40E_NVMUPD_GET_AQ_RESULT,
313 };
314
315 enum i40e_nvmupd_state {
316 I40E_NVMUPD_STATE_INIT,
317 I40E_NVMUPD_STATE_READING,
318 I40E_NVMUPD_STATE_WRITING,
319 I40E_NVMUPD_STATE_INIT_WAIT,
320 I40E_NVMUPD_STATE_WRITE_WAIT,
321 };
322
323 /* nvm_access definition and its masks/shifts need to be accessible to
324 * application, core driver, and shared code. Where is the right file?
325 */
326 #define I40E_NVM_READ 0xB
327 #define I40E_NVM_WRITE 0xC
328
329 #define I40E_NVM_MOD_PNT_MASK 0xFF
330
331 #define I40E_NVM_TRANS_SHIFT 8
332 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
333 #define I40E_NVM_CON 0x0
334 #define I40E_NVM_SNT 0x1
335 #define I40E_NVM_LCB 0x2
336 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
337 #define I40E_NVM_ERA 0x4
338 #define I40E_NVM_CSUM 0x8
339 #define I40E_NVM_EXEC 0xf
340
341 #define I40E_NVM_ADAPT_SHIFT 16
342 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
343
344 #define I40E_NVMUPD_MAX_DATA 4096
345 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
346
347 struct i40e_nvm_access {
348 u32 command;
349 u32 config;
350 u32 offset; /* in bytes */
351 u32 data_size; /* in bytes */
352 u8 data[1];
353 };
354
355 /* PCI bus types */
356 enum i40e_bus_type {
357 i40e_bus_type_unknown = 0,
358 i40e_bus_type_pci,
359 i40e_bus_type_pcix,
360 i40e_bus_type_pci_express,
361 i40e_bus_type_reserved
362 };
363
364 /* PCI bus speeds */
365 enum i40e_bus_speed {
366 i40e_bus_speed_unknown = 0,
367 i40e_bus_speed_33 = 33,
368 i40e_bus_speed_66 = 66,
369 i40e_bus_speed_100 = 100,
370 i40e_bus_speed_120 = 120,
371 i40e_bus_speed_133 = 133,
372 i40e_bus_speed_2500 = 2500,
373 i40e_bus_speed_5000 = 5000,
374 i40e_bus_speed_8000 = 8000,
375 i40e_bus_speed_reserved
376 };
377
378 /* PCI bus widths */
379 enum i40e_bus_width {
380 i40e_bus_width_unknown = 0,
381 i40e_bus_width_pcie_x1 = 1,
382 i40e_bus_width_pcie_x2 = 2,
383 i40e_bus_width_pcie_x4 = 4,
384 i40e_bus_width_pcie_x8 = 8,
385 i40e_bus_width_32 = 32,
386 i40e_bus_width_64 = 64,
387 i40e_bus_width_reserved
388 };
389
390 /* Bus parameters */
391 struct i40e_bus_info {
392 enum i40e_bus_speed speed;
393 enum i40e_bus_width width;
394 enum i40e_bus_type type;
395
396 u16 func;
397 u16 device;
398 u16 lan_id;
399 };
400
401 /* Flow control (FC) parameters */
402 struct i40e_fc_info {
403 enum i40e_fc_mode current_mode; /* FC mode in effect */
404 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
405 };
406
407 #define I40E_MAX_TRAFFIC_CLASS 8
408 #define I40E_MAX_USER_PRIORITY 8
409 #define I40E_DCBX_MAX_APPS 32
410 #define I40E_LLDPDU_SIZE 1500
411 #define I40E_TLV_STATUS_OPER 0x1
412 #define I40E_TLV_STATUS_SYNC 0x2
413 #define I40E_TLV_STATUS_ERR 0x4
414 #define I40E_CEE_OPER_MAX_APPS 3
415 #define I40E_APP_PROTOID_FCOE 0x8906
416 #define I40E_APP_PROTOID_ISCSI 0x0cbc
417 #define I40E_APP_PROTOID_FIP 0x8914
418 #define I40E_APP_SEL_ETHTYPE 0x1
419 #define I40E_APP_SEL_TCPIP 0x2
420
421 /* CEE or IEEE 802.1Qaz ETS Configuration data */
422 struct i40e_dcb_ets_config {
423 u8 willing;
424 u8 cbs;
425 u8 maxtcs;
426 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
427 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
428 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
429 };
430
431 /* CEE or IEEE 802.1Qaz PFC Configuration data */
432 struct i40e_dcb_pfc_config {
433 u8 willing;
434 u8 mbc;
435 u8 pfccap;
436 u8 pfcenable;
437 };
438
439 /* CEE or IEEE 802.1Qaz Application Priority data */
440 struct i40e_dcb_app_priority_table {
441 u8 priority;
442 u8 selector;
443 u16 protocolid;
444 };
445
446 struct i40e_dcbx_config {
447 u8 dcbx_mode;
448 #define I40E_DCBX_MODE_CEE 0x1
449 #define I40E_DCBX_MODE_IEEE 0x2
450 u32 numapps;
451 u32 tlv_status; /* CEE mode TLV status */
452 struct i40e_dcb_ets_config etscfg;
453 struct i40e_dcb_ets_config etsrec;
454 struct i40e_dcb_pfc_config pfc;
455 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
456 };
457
458 /* Port hardware description */
459 struct i40e_hw {
460 u8 __iomem *hw_addr;
461 void *back;
462
463 /* subsystem structs */
464 struct i40e_phy_info phy;
465 struct i40e_mac_info mac;
466 struct i40e_bus_info bus;
467 struct i40e_nvm_info nvm;
468 struct i40e_fc_info fc;
469
470 /* pci info */
471 u16 device_id;
472 u16 vendor_id;
473 u16 subsystem_device_id;
474 u16 subsystem_vendor_id;
475 u8 revision_id;
476 u8 port;
477 bool adapter_stopped;
478
479 /* capabilities for entire device and PCI func */
480 struct i40e_hw_capabilities dev_caps;
481 struct i40e_hw_capabilities func_caps;
482
483 /* Flow Director shared filter space */
484 u16 fdir_shared_filter_count;
485
486 /* device profile info */
487 u8 pf_id;
488 u16 main_vsi_seid;
489
490 /* for multi-function MACs */
491 u16 partition_id;
492 u16 num_partitions;
493 u16 num_ports;
494
495 /* Closest numa node to the device */
496 u16 numa_node;
497
498 /* Admin Queue info */
499 struct i40e_adminq_info aq;
500
501 /* state of nvm update process */
502 enum i40e_nvmupd_state nvmupd_state;
503 struct i40e_aq_desc nvm_wb_desc;
504 struct i40e_virt_mem nvm_buff;
505
506 /* HMC info */
507 struct i40e_hmc_info hmc; /* HMC info struct */
508
509 /* LLDP/DCBX Status */
510 u16 dcbx_status;
511
512 /* DCBX info */
513 struct i40e_dcbx_config local_dcbx_config;
514 struct i40e_dcbx_config remote_dcbx_config;
515
516 /* debug mask */
517 u32 debug_mask;
518 char err_str[16];
519 };
520
521 static inline bool i40e_is_vf(struct i40e_hw *hw)
522 {
523 return (hw->mac.type == I40E_MAC_VF ||
524 hw->mac.type == I40E_MAC_X722_VF);
525 }
526
527 struct i40e_driver_version {
528 u8 major_version;
529 u8 minor_version;
530 u8 build_version;
531 u8 subbuild_version;
532 u8 driver_string[32];
533 };
534
535 /* RX Descriptors */
536 union i40e_16byte_rx_desc {
537 struct {
538 __le64 pkt_addr; /* Packet buffer address */
539 __le64 hdr_addr; /* Header buffer address */
540 } read;
541 struct {
542 struct {
543 struct {
544 union {
545 __le16 mirroring_status;
546 __le16 fcoe_ctx_id;
547 } mirr_fcoe;
548 __le16 l2tag1;
549 } lo_dword;
550 union {
551 __le32 rss; /* RSS Hash */
552 __le32 fd_id; /* Flow director filter id */
553 __le32 fcoe_param; /* FCoE DDP Context id */
554 } hi_dword;
555 } qword0;
556 struct {
557 /* ext status/error/pktype/length */
558 __le64 status_error_len;
559 } qword1;
560 } wb; /* writeback */
561 };
562
563 union i40e_32byte_rx_desc {
564 struct {
565 __le64 pkt_addr; /* Packet buffer address */
566 __le64 hdr_addr; /* Header buffer address */
567 /* bit 0 of hdr_buffer_addr is DD bit */
568 __le64 rsvd1;
569 __le64 rsvd2;
570 } read;
571 struct {
572 struct {
573 struct {
574 union {
575 __le16 mirroring_status;
576 __le16 fcoe_ctx_id;
577 } mirr_fcoe;
578 __le16 l2tag1;
579 } lo_dword;
580 union {
581 __le32 rss; /* RSS Hash */
582 __le32 fcoe_param; /* FCoE DDP Context id */
583 /* Flow director filter id in case of
584 * Programming status desc WB
585 */
586 __le32 fd_id;
587 } hi_dword;
588 } qword0;
589 struct {
590 /* status/error/pktype/length */
591 __le64 status_error_len;
592 } qword1;
593 struct {
594 __le16 ext_status; /* extended status */
595 __le16 rsvd;
596 __le16 l2tag2_1;
597 __le16 l2tag2_2;
598 } qword2;
599 struct {
600 union {
601 __le32 flex_bytes_lo;
602 __le32 pe_status;
603 } lo_dword;
604 union {
605 __le32 flex_bytes_hi;
606 __le32 fd_id;
607 } hi_dword;
608 } qword3;
609 } wb; /* writeback */
610 };
611
612 enum i40e_rx_desc_status_bits {
613 /* Note: These are predefined bit offsets */
614 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
615 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
616 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
617 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
618 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
619 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
620 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
621 /* Note: Bit 8 is reserved in X710 and XL710 */
622 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
623 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
624 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
625 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
626 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
627 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
628 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
629 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
630 * UDP header
631 */
632 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
633 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
634 };
635
636 #define I40E_RXD_QW1_STATUS_SHIFT 0
637 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
638 << I40E_RXD_QW1_STATUS_SHIFT)
639
640 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
641 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
642 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
643
644 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
645 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
646 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
647
648 enum i40e_rx_desc_fltstat_values {
649 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
650 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
651 I40E_RX_DESC_FLTSTAT_RSV = 2,
652 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
653 };
654
655 #define I40E_RXD_QW1_ERROR_SHIFT 19
656 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
657
658 enum i40e_rx_desc_error_bits {
659 /* Note: These are predefined bit offsets */
660 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
661 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
662 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
663 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
664 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
665 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
666 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
667 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
668 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
669 };
670
671 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
672 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
673 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
674 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
675 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
676 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
677 };
678
679 #define I40E_RXD_QW1_PTYPE_SHIFT 30
680 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
681
682 /* Packet type non-ip values */
683 enum i40e_rx_l2_ptype {
684 I40E_RX_PTYPE_L2_RESERVED = 0,
685 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
686 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
687 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
688 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
689 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
690 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
691 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
692 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
693 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
694 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
695 I40E_RX_PTYPE_L2_ARP = 11,
696 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
697 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
698 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
699 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
700 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
701 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
702 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
703 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
704 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
705 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
706 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
707 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
708 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
709 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
710 };
711
712 struct i40e_rx_ptype_decoded {
713 u32 ptype:8;
714 u32 known:1;
715 u32 outer_ip:1;
716 u32 outer_ip_ver:1;
717 u32 outer_frag:1;
718 u32 tunnel_type:3;
719 u32 tunnel_end_prot:2;
720 u32 tunnel_end_frag:1;
721 u32 inner_prot:4;
722 u32 payload_layer:3;
723 };
724
725 enum i40e_rx_ptype_outer_ip {
726 I40E_RX_PTYPE_OUTER_L2 = 0,
727 I40E_RX_PTYPE_OUTER_IP = 1
728 };
729
730 enum i40e_rx_ptype_outer_ip_ver {
731 I40E_RX_PTYPE_OUTER_NONE = 0,
732 I40E_RX_PTYPE_OUTER_IPV4 = 0,
733 I40E_RX_PTYPE_OUTER_IPV6 = 1
734 };
735
736 enum i40e_rx_ptype_outer_fragmented {
737 I40E_RX_PTYPE_NOT_FRAG = 0,
738 I40E_RX_PTYPE_FRAG = 1
739 };
740
741 enum i40e_rx_ptype_tunnel_type {
742 I40E_RX_PTYPE_TUNNEL_NONE = 0,
743 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
744 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
745 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
746 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
747 };
748
749 enum i40e_rx_ptype_tunnel_end_prot {
750 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
751 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
752 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
753 };
754
755 enum i40e_rx_ptype_inner_prot {
756 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
757 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
758 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
759 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
760 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
761 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
762 };
763
764 enum i40e_rx_ptype_payload_layer {
765 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
766 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
767 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
768 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
769 };
770
771 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
772 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
773 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
774
775 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
776 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
777 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
778
779 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
780 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
781
782 enum i40e_rx_desc_ext_status_bits {
783 /* Note: These are predefined bit offsets */
784 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
785 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
786 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
787 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
788 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
789 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
790 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
791 };
792
793 enum i40e_rx_desc_pe_status_bits {
794 /* Note: These are predefined bit offsets */
795 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
796 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
797 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
798 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
799 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
800 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
801 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
802 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
803 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
804 };
805
806 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
807 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
808
809 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
810 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
811 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
812
813 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
814 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
815 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
816
817 enum i40e_rx_prog_status_desc_status_bits {
818 /* Note: These are predefined bit offsets */
819 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
820 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
821 };
822
823 enum i40e_rx_prog_status_desc_prog_id_masks {
824 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
825 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
826 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
827 };
828
829 enum i40e_rx_prog_status_desc_error_bits {
830 /* Note: These are predefined bit offsets */
831 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
832 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
833 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
834 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
835 };
836
837 /* TX Descriptor */
838 struct i40e_tx_desc {
839 __le64 buffer_addr; /* Address of descriptor's data buf */
840 __le64 cmd_type_offset_bsz;
841 };
842
843 #define I40E_TXD_QW1_DTYPE_SHIFT 0
844 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
845
846 enum i40e_tx_desc_dtype_value {
847 I40E_TX_DESC_DTYPE_DATA = 0x0,
848 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
849 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
850 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
851 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
852 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
853 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
854 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
855 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
856 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
857 };
858
859 #define I40E_TXD_QW1_CMD_SHIFT 4
860 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
861
862 enum i40e_tx_desc_cmd_bits {
863 I40E_TX_DESC_CMD_EOP = 0x0001,
864 I40E_TX_DESC_CMD_RS = 0x0002,
865 I40E_TX_DESC_CMD_ICRC = 0x0004,
866 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
867 I40E_TX_DESC_CMD_DUMMY = 0x0010,
868 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
869 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
870 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
871 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
872 I40E_TX_DESC_CMD_FCOET = 0x0080,
873 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
874 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
875 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
876 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
877 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
878 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
879 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
880 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
881 };
882
883 #define I40E_TXD_QW1_OFFSET_SHIFT 16
884 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
885 I40E_TXD_QW1_OFFSET_SHIFT)
886
887 enum i40e_tx_desc_length_fields {
888 /* Note: These are predefined bit offsets */
889 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
890 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
891 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
892 };
893
894 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
895 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
896 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
897
898 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
899 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
900
901 /* Context descriptors */
902 struct i40e_tx_context_desc {
903 __le32 tunneling_params;
904 __le16 l2tag2;
905 __le16 rsvd;
906 __le64 type_cmd_tso_mss;
907 };
908
909 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
910 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
911
912 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
913 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
914
915 enum i40e_tx_ctx_desc_cmd_bits {
916 I40E_TX_CTX_DESC_TSO = 0x01,
917 I40E_TX_CTX_DESC_TSYN = 0x02,
918 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
919 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
920 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
921 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
922 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
923 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
924 I40E_TX_CTX_DESC_SWPE = 0x40
925 };
926
927 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
928 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
929 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
930
931 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
932 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
933 I40E_TXD_CTX_QW1_MSS_SHIFT)
934
935 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
936 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
937
938 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
939 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
940 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
941
942 enum i40e_tx_ctx_desc_eipt_offload {
943 I40E_TX_CTX_EXT_IP_NONE = 0x0,
944 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
945 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
946 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
947 };
948
949 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
950 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
951 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
952
953 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
954 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
955
956 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
957 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
958
959 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
960 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
961 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
962
963 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
964
965 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
966 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
967 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
968
969 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
970 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
971 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
972
973 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
974 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
975 struct i40e_filter_program_desc {
976 __le32 qindex_flex_ptype_vsi;
977 __le32 rsvd;
978 __le32 dtype_cmd_cntindex;
979 __le32 fd_id;
980 };
981 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
982 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
983 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
984 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
985 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
986 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
987 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
988 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
989 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
990
991 /* Packet Classifier Types for filters */
992 enum i40e_filter_pctype {
993 /* Note: Values 0-28 are reserved for future use.
994 * Value 29, 30, 32 are not supported on XL710 and X710.
995 */
996 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
997 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
998 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
999 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1000 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1001 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1002 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1003 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1004 /* Note: Values 37-38 are reserved for future use.
1005 * Value 39, 40, 42 are not supported on XL710 and X710.
1006 */
1007 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1008 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1009 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1010 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1011 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1012 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1013 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1014 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1015 /* Note: Value 47 is reserved for future use */
1016 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1017 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1018 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1019 /* Note: Values 51-62 are reserved for future use */
1020 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1021 };
1022
1023 enum i40e_filter_program_desc_dest {
1024 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1025 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1026 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1027 };
1028
1029 enum i40e_filter_program_desc_fd_status {
1030 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1031 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1032 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1033 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1034 };
1035
1036 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1037 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1038 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1039
1040 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1041 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1042 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1043
1044 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1045 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1046
1047 enum i40e_filter_program_desc_pcmd {
1048 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1049 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1050 };
1051
1052 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1053 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1054
1055 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1056 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1057
1058 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1059 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1060 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1061 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1062
1063 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1064 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1065 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1066
1067 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1068 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1069 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1070
1071 enum i40e_filter_type {
1072 I40E_FLOW_DIRECTOR_FLTR = 0,
1073 I40E_PE_QUAD_HASH_FLTR = 1,
1074 I40E_ETHERTYPE_FLTR,
1075 I40E_FCOE_CTX_FLTR,
1076 I40E_MAC_VLAN_FLTR,
1077 I40E_HASH_FLTR
1078 };
1079
1080 struct i40e_vsi_context {
1081 u16 seid;
1082 u16 uplink_seid;
1083 u16 vsi_number;
1084 u16 vsis_allocated;
1085 u16 vsis_unallocated;
1086 u16 flags;
1087 u8 pf_num;
1088 u8 vf_num;
1089 u8 connection_type;
1090 struct i40e_aqc_vsi_properties_data info;
1091 };
1092
1093 struct i40e_veb_context {
1094 u16 seid;
1095 u16 uplink_seid;
1096 u16 veb_number;
1097 u16 vebs_allocated;
1098 u16 vebs_unallocated;
1099 u16 flags;
1100 struct i40e_aqc_get_veb_parameters_completion info;
1101 };
1102
1103 /* Statistics collected by each port, VSI, VEB, and S-channel */
1104 struct i40e_eth_stats {
1105 u64 rx_bytes; /* gorc */
1106 u64 rx_unicast; /* uprc */
1107 u64 rx_multicast; /* mprc */
1108 u64 rx_broadcast; /* bprc */
1109 u64 rx_discards; /* rdpc */
1110 u64 rx_unknown_protocol; /* rupp */
1111 u64 tx_bytes; /* gotc */
1112 u64 tx_unicast; /* uptc */
1113 u64 tx_multicast; /* mptc */
1114 u64 tx_broadcast; /* bptc */
1115 u64 tx_discards; /* tdpc */
1116 u64 tx_errors; /* tepc */
1117 };
1118
1119 /* Statistics collected per VEB per TC */
1120 struct i40e_veb_tc_stats {
1121 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1122 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1123 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1124 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1125 };
1126
1127 #ifdef I40E_FCOE
1128 /* Statistics collected per function for FCoE */
1129 struct i40e_fcoe_stats {
1130 u64 rx_fcoe_packets; /* fcoeprc */
1131 u64 rx_fcoe_dwords; /* focedwrc */
1132 u64 rx_fcoe_dropped; /* fcoerpdc */
1133 u64 tx_fcoe_packets; /* fcoeptc */
1134 u64 tx_fcoe_dwords; /* focedwtc */
1135 u64 fcoe_bad_fccrc; /* fcoecrc */
1136 u64 fcoe_last_error; /* fcoelast */
1137 u64 fcoe_ddp_count; /* fcoeddpc */
1138 };
1139
1140 /* offset to per function FCoE statistics block */
1141 #define I40E_FCOE_VF_STAT_OFFSET 0
1142 #define I40E_FCOE_PF_STAT_OFFSET 128
1143 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1144
1145 #endif
1146 /* Statistics collected by the MAC */
1147 struct i40e_hw_port_stats {
1148 /* eth stats collected by the port */
1149 struct i40e_eth_stats eth;
1150
1151 /* additional port specific stats */
1152 u64 tx_dropped_link_down; /* tdold */
1153 u64 crc_errors; /* crcerrs */
1154 u64 illegal_bytes; /* illerrc */
1155 u64 error_bytes; /* errbc */
1156 u64 mac_local_faults; /* mlfc */
1157 u64 mac_remote_faults; /* mrfc */
1158 u64 rx_length_errors; /* rlec */
1159 u64 link_xon_rx; /* lxonrxc */
1160 u64 link_xoff_rx; /* lxoffrxc */
1161 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1162 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1163 u64 link_xon_tx; /* lxontxc */
1164 u64 link_xoff_tx; /* lxofftxc */
1165 u64 priority_xon_tx[8]; /* pxontxc[8] */
1166 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1167 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1168 u64 rx_size_64; /* prc64 */
1169 u64 rx_size_127; /* prc127 */
1170 u64 rx_size_255; /* prc255 */
1171 u64 rx_size_511; /* prc511 */
1172 u64 rx_size_1023; /* prc1023 */
1173 u64 rx_size_1522; /* prc1522 */
1174 u64 rx_size_big; /* prc9522 */
1175 u64 rx_undersize; /* ruc */
1176 u64 rx_fragments; /* rfc */
1177 u64 rx_oversize; /* roc */
1178 u64 rx_jabber; /* rjc */
1179 u64 tx_size_64; /* ptc64 */
1180 u64 tx_size_127; /* ptc127 */
1181 u64 tx_size_255; /* ptc255 */
1182 u64 tx_size_511; /* ptc511 */
1183 u64 tx_size_1023; /* ptc1023 */
1184 u64 tx_size_1522; /* ptc1522 */
1185 u64 tx_size_big; /* ptc9522 */
1186 u64 mac_short_packet_dropped; /* mspdc */
1187 u64 checksum_error; /* xec */
1188 /* flow director stats */
1189 u64 fd_atr_match;
1190 u64 fd_sb_match;
1191 u64 fd_atr_tunnel_match;
1192 u32 fd_atr_status;
1193 u32 fd_sb_status;
1194 /* EEE LPI */
1195 u32 tx_lpi_status;
1196 u32 rx_lpi_status;
1197 u64 tx_lpi_count; /* etlpic */
1198 u64 rx_lpi_count; /* erlpic */
1199 };
1200
1201 /* Checksum and Shadow RAM pointers */
1202 #define I40E_SR_NVM_CONTROL_WORD 0x00
1203 #define I40E_SR_EMP_MODULE_PTR 0x0F
1204 #define I40E_SR_PBA_FLAGS 0x15
1205 #define I40E_SR_PBA_BLOCK_PTR 0x16
1206 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1207 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1208 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1209 #define I40E_SR_NVM_EETRACK_LO 0x2D
1210 #define I40E_SR_NVM_EETRACK_HI 0x2E
1211 #define I40E_SR_VPD_PTR 0x2F
1212 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1213 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1214
1215 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1216 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1217 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1218 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1219 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1220
1221 /* Shadow RAM related */
1222 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1223 #define I40E_SR_WORDS_IN_1KB 512
1224 /* Checksum should be calculated such that after adding all the words,
1225 * including the checksum word itself, the sum should be 0xBABA.
1226 */
1227 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1228
1229 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1230
1231 #ifdef I40E_FCOE
1232 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1233
1234 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1235 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1236 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1237 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1238 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1239 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1240 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1241 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1242 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1243 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1244 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1245 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1246 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1247 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1248 };
1249
1250 /* FCoE DDP Context descriptor */
1251 struct i40e_fcoe_ddp_context_desc {
1252 __le64 rsvd;
1253 __le64 type_cmd_foff_lsize;
1254 };
1255
1256 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1257 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1258 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1259
1260 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1261 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1262 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1263
1264 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1265 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1266 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1267 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1268 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1269 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1270 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1271 };
1272
1273 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1274 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1275 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1276
1277 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1278 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1279 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1280
1281 /* FCoE DDP/DWO Queue Context descriptor */
1282 struct i40e_fcoe_queue_context_desc {
1283 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1284 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1285 };
1286
1287 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1288 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1289 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1290
1291 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1292 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1293 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1294
1295 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1296 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1297 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1298
1299 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1300 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1301 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1302
1303 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1304 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1305 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1306 };
1307
1308 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1309 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1310 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1311
1312 /* FCoE DDP/DWO Filter Context descriptor */
1313 struct i40e_fcoe_filter_context_desc {
1314 __le32 param;
1315 __le16 seqn;
1316
1317 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1318 __le16 rsvd_dmaindx;
1319
1320 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1321 __le64 flags_rsvd_lanq;
1322 };
1323
1324 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1325 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1326 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1327
1328 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1329 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1330 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1331 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1332 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1333 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1334 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1335 };
1336
1337 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1338 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1339 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1340
1341 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1342 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1343 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1344
1345 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1346 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1347 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1348
1349 #endif /* I40E_FCOE */
1350 enum i40e_switch_element_types {
1351 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1352 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1353 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1354 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1355 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1356 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1357 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1358 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1359 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1360 };
1361
1362 /* Supported EtherType filters */
1363 enum i40e_ether_type_index {
1364 I40E_ETHER_TYPE_1588 = 0,
1365 I40E_ETHER_TYPE_FIP = 1,
1366 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1367 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1368 I40E_ETHER_TYPE_LLDP = 4,
1369 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1370 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1371 I40E_ETHER_TYPE_QCN_CNM = 7,
1372 I40E_ETHER_TYPE_8021X = 8,
1373 I40E_ETHER_TYPE_ARP = 9,
1374 I40E_ETHER_TYPE_RSV1 = 10,
1375 I40E_ETHER_TYPE_RSV2 = 11,
1376 };
1377
1378 /* Filter context base size is 1K */
1379 #define I40E_HASH_FILTER_BASE_SIZE 1024
1380 /* Supported Hash filter values */
1381 enum i40e_hash_filter_size {
1382 I40E_HASH_FILTER_SIZE_1K = 0,
1383 I40E_HASH_FILTER_SIZE_2K = 1,
1384 I40E_HASH_FILTER_SIZE_4K = 2,
1385 I40E_HASH_FILTER_SIZE_8K = 3,
1386 I40E_HASH_FILTER_SIZE_16K = 4,
1387 I40E_HASH_FILTER_SIZE_32K = 5,
1388 I40E_HASH_FILTER_SIZE_64K = 6,
1389 I40E_HASH_FILTER_SIZE_128K = 7,
1390 I40E_HASH_FILTER_SIZE_256K = 8,
1391 I40E_HASH_FILTER_SIZE_512K = 9,
1392 I40E_HASH_FILTER_SIZE_1M = 10,
1393 };
1394
1395 /* DMA context base size is 0.5K */
1396 #define I40E_DMA_CNTX_BASE_SIZE 512
1397 /* Supported DMA context values */
1398 enum i40e_dma_cntx_size {
1399 I40E_DMA_CNTX_SIZE_512 = 0,
1400 I40E_DMA_CNTX_SIZE_1K = 1,
1401 I40E_DMA_CNTX_SIZE_2K = 2,
1402 I40E_DMA_CNTX_SIZE_4K = 3,
1403 I40E_DMA_CNTX_SIZE_8K = 4,
1404 I40E_DMA_CNTX_SIZE_16K = 5,
1405 I40E_DMA_CNTX_SIZE_32K = 6,
1406 I40E_DMA_CNTX_SIZE_64K = 7,
1407 I40E_DMA_CNTX_SIZE_128K = 8,
1408 I40E_DMA_CNTX_SIZE_256K = 9,
1409 };
1410
1411 /* Supported Hash look up table (LUT) sizes */
1412 enum i40e_hash_lut_size {
1413 I40E_HASH_LUT_SIZE_128 = 0,
1414 I40E_HASH_LUT_SIZE_512 = 1,
1415 };
1416
1417 /* Structure to hold a per PF filter control settings */
1418 struct i40e_filter_control_settings {
1419 /* number of PE Quad Hash filter buckets */
1420 enum i40e_hash_filter_size pe_filt_num;
1421 /* number of PE Quad Hash contexts */
1422 enum i40e_dma_cntx_size pe_cntx_num;
1423 /* number of FCoE filter buckets */
1424 enum i40e_hash_filter_size fcoe_filt_num;
1425 /* number of FCoE DDP contexts */
1426 enum i40e_dma_cntx_size fcoe_cntx_num;
1427 /* size of the Hash LUT */
1428 enum i40e_hash_lut_size hash_lut_size;
1429 /* enable FDIR filters for PF and its VFs */
1430 bool enable_fdir;
1431 /* enable Ethertype filters for PF and its VFs */
1432 bool enable_ethtype;
1433 /* enable MAC/VLAN filters for PF and its VFs */
1434 bool enable_macvlan;
1435 };
1436
1437 /* Structure to hold device level control filter counts */
1438 struct i40e_control_filter_stats {
1439 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1440 u16 etype_used; /* Used perfect EtherType filters */
1441 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1442 u16 etype_free; /* Un-used perfect EtherType filters */
1443 };
1444
1445 enum i40e_reset_type {
1446 I40E_RESET_POR = 0,
1447 I40E_RESET_CORER = 1,
1448 I40E_RESET_GLOBR = 2,
1449 I40E_RESET_EMPR = 3,
1450 };
1451
1452 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1453 #define I40E_NVM_LLDP_CFG_PTR 0xD
1454 struct i40e_lldp_variables {
1455 u16 length;
1456 u16 adminstatus;
1457 u16 msgfasttx;
1458 u16 msgtxinterval;
1459 u16 txparams;
1460 u16 timers;
1461 u16 crc8;
1462 };
1463
1464 /* Offsets into Alternate Ram */
1465 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1466 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1467 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1468 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1469 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1470 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1471
1472 /* Alternate Ram Bandwidth Masks */
1473 #define I40E_ALT_BW_VALUE_MASK 0xFF
1474 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1475 #define I40E_ALT_BW_VALID_MASK 0x80000000
1476
1477 /* RSS Hash Table Size */
1478 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1479 #endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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