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i40e/i40evf: split device ids into a separate file
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_type.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36 #include "i40e_devids.h"
37
38 /* I40E_MASK is a macro used on 32 bit registers */
39 #define I40E_MASK(mask, shift) (mask << shift)
40
41 #define I40E_MAX_VSI_QP 16
42 #define I40E_MAX_VF_VSI 3
43 #define I40E_MAX_CHAINED_RX_BUFFERS 5
44 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
45
46 /* Max default timeout in ms, */
47 #define I40E_MAX_NVM_TIMEOUT 18000
48
49 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
50 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
51
52 /* forward declaration */
53 struct i40e_hw;
54 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
55
56 /* Data type manipulation macros. */
57
58 #define I40E_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
61
62 /* bitfields for Tx queue mapping in QTX_CTL */
63 #define I40E_QTX_CTL_VF_QUEUE 0x0
64 #define I40E_QTX_CTL_VM_QUEUE 0x1
65 #define I40E_QTX_CTL_PF_QUEUE 0x2
66
67 /* debug masks - set these bits in hw->debug_mask to control output */
68 enum i40e_debug_mask {
69 I40E_DEBUG_INIT = 0x00000001,
70 I40E_DEBUG_RELEASE = 0x00000002,
71
72 I40E_DEBUG_LINK = 0x00000010,
73 I40E_DEBUG_PHY = 0x00000020,
74 I40E_DEBUG_HMC = 0x00000040,
75 I40E_DEBUG_NVM = 0x00000080,
76 I40E_DEBUG_LAN = 0x00000100,
77 I40E_DEBUG_FLOW = 0x00000200,
78 I40E_DEBUG_DCB = 0x00000400,
79 I40E_DEBUG_DIAG = 0x00000800,
80 I40E_DEBUG_FD = 0x00001000,
81
82 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
83 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
84 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
85 I40E_DEBUG_AQ_COMMAND = 0x06000000,
86 I40E_DEBUG_AQ = 0x0F000000,
87
88 I40E_DEBUG_USER = 0xF0000000,
89
90 I40E_DEBUG_ALL = 0xFFFFFFFF
91 };
92
93 /* These are structs for managing the hardware information and the operations.
94 * The structures of function pointers are filled out at init time when we
95 * know for sure exactly which hardware we're working with. This gives us the
96 * flexibility of using the same main driver code but adapting to slightly
97 * different hardware needs as new parts are developed. For this architecture,
98 * the Firmware and AdminQ are intended to insulate the driver from most of the
99 * future changes, but these structures will also do part of the job.
100 */
101 enum i40e_mac_type {
102 I40E_MAC_UNKNOWN = 0,
103 I40E_MAC_X710,
104 I40E_MAC_XL710,
105 I40E_MAC_VF,
106 I40E_MAC_X722,
107 I40E_MAC_X722_VF,
108 I40E_MAC_GENERIC,
109 };
110
111 enum i40e_media_type {
112 I40E_MEDIA_TYPE_UNKNOWN = 0,
113 I40E_MEDIA_TYPE_FIBER,
114 I40E_MEDIA_TYPE_BASET,
115 I40E_MEDIA_TYPE_BACKPLANE,
116 I40E_MEDIA_TYPE_CX4,
117 I40E_MEDIA_TYPE_DA,
118 I40E_MEDIA_TYPE_VIRTUAL
119 };
120
121 enum i40e_fc_mode {
122 I40E_FC_NONE = 0,
123 I40E_FC_RX_PAUSE,
124 I40E_FC_TX_PAUSE,
125 I40E_FC_FULL,
126 I40E_FC_PFC,
127 I40E_FC_DEFAULT
128 };
129
130 enum i40e_set_fc_aq_failures {
131 I40E_SET_FC_AQ_FAIL_NONE = 0,
132 I40E_SET_FC_AQ_FAIL_GET = 1,
133 I40E_SET_FC_AQ_FAIL_SET = 2,
134 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
135 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
136 };
137
138 enum i40e_vsi_type {
139 I40E_VSI_MAIN = 0,
140 I40E_VSI_VMDQ1 = 1,
141 I40E_VSI_VMDQ2 = 2,
142 I40E_VSI_CTRL = 3,
143 I40E_VSI_FCOE = 4,
144 I40E_VSI_MIRROR = 5,
145 I40E_VSI_SRIOV = 6,
146 I40E_VSI_FDIR = 7,
147 I40E_VSI_TYPE_UNKNOWN
148 };
149
150 enum i40e_queue_type {
151 I40E_QUEUE_TYPE_RX = 0,
152 I40E_QUEUE_TYPE_TX,
153 I40E_QUEUE_TYPE_PE_CEQ,
154 I40E_QUEUE_TYPE_UNKNOWN
155 };
156
157 struct i40e_link_status {
158 enum i40e_aq_phy_type phy_type;
159 enum i40e_aq_link_speed link_speed;
160 u8 link_info;
161 u8 an_info;
162 u8 ext_info;
163 u8 loopback;
164 /* is Link Status Event notification to SW enabled */
165 bool lse_enable;
166 u16 max_frame_size;
167 bool crc_enable;
168 u8 pacing;
169 u8 requested_speeds;
170 };
171
172 struct i40e_phy_info {
173 struct i40e_link_status link_info;
174 struct i40e_link_status link_info_old;
175 u32 autoneg_advertised;
176 u32 phy_id;
177 u32 module_type;
178 bool get_link_info;
179 enum i40e_media_type media_type;
180 };
181
182 #define I40E_HW_CAP_MAX_GPIO 30
183 /* Capabilities of a PF or a VF or the whole device */
184 struct i40e_hw_capabilities {
185 u32 switch_mode;
186 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
187 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
188 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
189
190 u32 management_mode;
191 u32 npar_enable;
192 u32 os2bmc;
193 u32 valid_functions;
194 bool sr_iov_1_1;
195 bool vmdq;
196 bool evb_802_1_qbg; /* Edge Virtual Bridging */
197 bool evb_802_1_qbh; /* Bridge Port Extension */
198 bool dcb;
199 bool fcoe;
200 bool iscsi; /* Indicates iSCSI enabled */
201 bool flex10_enable;
202 bool flex10_capable;
203 u32 flex10_mode;
204 #define I40E_FLEX10_MODE_UNKNOWN 0x0
205 #define I40E_FLEX10_MODE_DCC 0x1
206 #define I40E_FLEX10_MODE_DCI 0x2
207
208 u32 flex10_status;
209 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
210 #define I40E_FLEX10_STATUS_VC_MODE 0x2
211
212 bool mgmt_cem;
213 bool ieee_1588;
214 bool iwarp;
215 bool fd;
216 u32 fd_filters_guaranteed;
217 u32 fd_filters_best_effort;
218 bool rss;
219 u32 rss_table_size;
220 u32 rss_table_entry_width;
221 bool led[I40E_HW_CAP_MAX_GPIO];
222 bool sdp[I40E_HW_CAP_MAX_GPIO];
223 u32 nvm_image_type;
224 u32 num_flow_director_filters;
225 u32 num_vfs;
226 u32 vf_base_id;
227 u32 num_vsis;
228 u32 num_rx_qp;
229 u32 num_tx_qp;
230 u32 base_queue;
231 u32 num_msix_vectors;
232 u32 num_msix_vectors_vf;
233 u32 led_pin_num;
234 u32 sdp_pin_num;
235 u32 mdio_port_num;
236 u32 mdio_port_mode;
237 u8 rx_buf_chain_len;
238 u32 enabled_tcmap;
239 u32 maxtc;
240 u64 wr_csr_prot;
241 };
242
243 struct i40e_mac_info {
244 enum i40e_mac_type type;
245 u8 addr[ETH_ALEN];
246 u8 perm_addr[ETH_ALEN];
247 u8 san_addr[ETH_ALEN];
248 u8 port_addr[ETH_ALEN];
249 u16 max_fcoeq;
250 };
251
252 enum i40e_aq_resources_ids {
253 I40E_NVM_RESOURCE_ID = 1
254 };
255
256 enum i40e_aq_resource_access_type {
257 I40E_RESOURCE_READ = 1,
258 I40E_RESOURCE_WRITE
259 };
260
261 struct i40e_nvm_info {
262 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
263 u32 timeout; /* [ms] */
264 u16 sr_size; /* Shadow RAM size in words */
265 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
266 u16 version; /* NVM package version */
267 u32 eetrack; /* NVM data version */
268 u32 oem_ver; /* OEM version info */
269 };
270
271 /* definitions used in NVM update support */
272
273 enum i40e_nvmupd_cmd {
274 I40E_NVMUPD_INVALID,
275 I40E_NVMUPD_READ_CON,
276 I40E_NVMUPD_READ_SNT,
277 I40E_NVMUPD_READ_LCB,
278 I40E_NVMUPD_READ_SA,
279 I40E_NVMUPD_WRITE_ERA,
280 I40E_NVMUPD_WRITE_CON,
281 I40E_NVMUPD_WRITE_SNT,
282 I40E_NVMUPD_WRITE_LCB,
283 I40E_NVMUPD_WRITE_SA,
284 I40E_NVMUPD_CSUM_CON,
285 I40E_NVMUPD_CSUM_SA,
286 I40E_NVMUPD_CSUM_LCB,
287 I40E_NVMUPD_STATUS,
288 I40E_NVMUPD_EXEC_AQ,
289 I40E_NVMUPD_GET_AQ_RESULT,
290 };
291
292 enum i40e_nvmupd_state {
293 I40E_NVMUPD_STATE_INIT,
294 I40E_NVMUPD_STATE_READING,
295 I40E_NVMUPD_STATE_WRITING,
296 I40E_NVMUPD_STATE_INIT_WAIT,
297 I40E_NVMUPD_STATE_WRITE_WAIT,
298 };
299
300 /* nvm_access definition and its masks/shifts need to be accessible to
301 * application, core driver, and shared code. Where is the right file?
302 */
303 #define I40E_NVM_READ 0xB
304 #define I40E_NVM_WRITE 0xC
305
306 #define I40E_NVM_MOD_PNT_MASK 0xFF
307
308 #define I40E_NVM_TRANS_SHIFT 8
309 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
310 #define I40E_NVM_CON 0x0
311 #define I40E_NVM_SNT 0x1
312 #define I40E_NVM_LCB 0x2
313 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
314 #define I40E_NVM_ERA 0x4
315 #define I40E_NVM_CSUM 0x8
316 #define I40E_NVM_EXEC 0xf
317
318 #define I40E_NVM_ADAPT_SHIFT 16
319 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
320
321 #define I40E_NVMUPD_MAX_DATA 4096
322 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
323
324 struct i40e_nvm_access {
325 u32 command;
326 u32 config;
327 u32 offset; /* in bytes */
328 u32 data_size; /* in bytes */
329 u8 data[1];
330 };
331
332 /* PCI bus types */
333 enum i40e_bus_type {
334 i40e_bus_type_unknown = 0,
335 i40e_bus_type_pci,
336 i40e_bus_type_pcix,
337 i40e_bus_type_pci_express,
338 i40e_bus_type_reserved
339 };
340
341 /* PCI bus speeds */
342 enum i40e_bus_speed {
343 i40e_bus_speed_unknown = 0,
344 i40e_bus_speed_33 = 33,
345 i40e_bus_speed_66 = 66,
346 i40e_bus_speed_100 = 100,
347 i40e_bus_speed_120 = 120,
348 i40e_bus_speed_133 = 133,
349 i40e_bus_speed_2500 = 2500,
350 i40e_bus_speed_5000 = 5000,
351 i40e_bus_speed_8000 = 8000,
352 i40e_bus_speed_reserved
353 };
354
355 /* PCI bus widths */
356 enum i40e_bus_width {
357 i40e_bus_width_unknown = 0,
358 i40e_bus_width_pcie_x1 = 1,
359 i40e_bus_width_pcie_x2 = 2,
360 i40e_bus_width_pcie_x4 = 4,
361 i40e_bus_width_pcie_x8 = 8,
362 i40e_bus_width_32 = 32,
363 i40e_bus_width_64 = 64,
364 i40e_bus_width_reserved
365 };
366
367 /* Bus parameters */
368 struct i40e_bus_info {
369 enum i40e_bus_speed speed;
370 enum i40e_bus_width width;
371 enum i40e_bus_type type;
372
373 u16 func;
374 u16 device;
375 u16 lan_id;
376 };
377
378 /* Flow control (FC) parameters */
379 struct i40e_fc_info {
380 enum i40e_fc_mode current_mode; /* FC mode in effect */
381 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
382 };
383
384 #define I40E_MAX_TRAFFIC_CLASS 8
385 #define I40E_MAX_USER_PRIORITY 8
386 #define I40E_DCBX_MAX_APPS 32
387 #define I40E_LLDPDU_SIZE 1500
388 #define I40E_TLV_STATUS_OPER 0x1
389 #define I40E_TLV_STATUS_SYNC 0x2
390 #define I40E_TLV_STATUS_ERR 0x4
391 #define I40E_CEE_OPER_MAX_APPS 3
392 #define I40E_APP_PROTOID_FCOE 0x8906
393 #define I40E_APP_PROTOID_ISCSI 0x0cbc
394 #define I40E_APP_PROTOID_FIP 0x8914
395 #define I40E_APP_SEL_ETHTYPE 0x1
396 #define I40E_APP_SEL_TCPIP 0x2
397 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
398 #define I40E_CEE_APP_SEL_TCPIP 0x1
399
400 /* CEE or IEEE 802.1Qaz ETS Configuration data */
401 struct i40e_dcb_ets_config {
402 u8 willing;
403 u8 cbs;
404 u8 maxtcs;
405 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
406 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
407 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
408 };
409
410 /* CEE or IEEE 802.1Qaz PFC Configuration data */
411 struct i40e_dcb_pfc_config {
412 u8 willing;
413 u8 mbc;
414 u8 pfccap;
415 u8 pfcenable;
416 };
417
418 /* CEE or IEEE 802.1Qaz Application Priority data */
419 struct i40e_dcb_app_priority_table {
420 u8 priority;
421 u8 selector;
422 u16 protocolid;
423 };
424
425 struct i40e_dcbx_config {
426 u8 dcbx_mode;
427 #define I40E_DCBX_MODE_CEE 0x1
428 #define I40E_DCBX_MODE_IEEE 0x2
429 u32 numapps;
430 u32 tlv_status; /* CEE mode TLV status */
431 struct i40e_dcb_ets_config etscfg;
432 struct i40e_dcb_ets_config etsrec;
433 struct i40e_dcb_pfc_config pfc;
434 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
435 };
436
437 /* Port hardware description */
438 struct i40e_hw {
439 u8 __iomem *hw_addr;
440 void *back;
441
442 /* subsystem structs */
443 struct i40e_phy_info phy;
444 struct i40e_mac_info mac;
445 struct i40e_bus_info bus;
446 struct i40e_nvm_info nvm;
447 struct i40e_fc_info fc;
448
449 /* pci info */
450 u16 device_id;
451 u16 vendor_id;
452 u16 subsystem_device_id;
453 u16 subsystem_vendor_id;
454 u8 revision_id;
455 u8 port;
456 bool adapter_stopped;
457
458 /* capabilities for entire device and PCI func */
459 struct i40e_hw_capabilities dev_caps;
460 struct i40e_hw_capabilities func_caps;
461
462 /* Flow Director shared filter space */
463 u16 fdir_shared_filter_count;
464
465 /* device profile info */
466 u8 pf_id;
467 u16 main_vsi_seid;
468
469 /* for multi-function MACs */
470 u16 partition_id;
471 u16 num_partitions;
472 u16 num_ports;
473
474 /* Closest numa node to the device */
475 u16 numa_node;
476
477 /* Admin Queue info */
478 struct i40e_adminq_info aq;
479
480 /* state of nvm update process */
481 enum i40e_nvmupd_state nvmupd_state;
482 struct i40e_aq_desc nvm_wb_desc;
483 struct i40e_virt_mem nvm_buff;
484
485 /* HMC info */
486 struct i40e_hmc_info hmc; /* HMC info struct */
487
488 /* LLDP/DCBX Status */
489 u16 dcbx_status;
490
491 /* DCBX info */
492 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
493 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
494 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
495
496 /* debug mask */
497 u32 debug_mask;
498 char err_str[16];
499 };
500
501 static inline bool i40e_is_vf(struct i40e_hw *hw)
502 {
503 return (hw->mac.type == I40E_MAC_VF ||
504 hw->mac.type == I40E_MAC_X722_VF);
505 }
506
507 struct i40e_driver_version {
508 u8 major_version;
509 u8 minor_version;
510 u8 build_version;
511 u8 subbuild_version;
512 u8 driver_string[32];
513 };
514
515 /* RX Descriptors */
516 union i40e_16byte_rx_desc {
517 struct {
518 __le64 pkt_addr; /* Packet buffer address */
519 __le64 hdr_addr; /* Header buffer address */
520 } read;
521 struct {
522 struct {
523 struct {
524 union {
525 __le16 mirroring_status;
526 __le16 fcoe_ctx_id;
527 } mirr_fcoe;
528 __le16 l2tag1;
529 } lo_dword;
530 union {
531 __le32 rss; /* RSS Hash */
532 __le32 fd_id; /* Flow director filter id */
533 __le32 fcoe_param; /* FCoE DDP Context id */
534 } hi_dword;
535 } qword0;
536 struct {
537 /* ext status/error/pktype/length */
538 __le64 status_error_len;
539 } qword1;
540 } wb; /* writeback */
541 };
542
543 union i40e_32byte_rx_desc {
544 struct {
545 __le64 pkt_addr; /* Packet buffer address */
546 __le64 hdr_addr; /* Header buffer address */
547 /* bit 0 of hdr_buffer_addr is DD bit */
548 __le64 rsvd1;
549 __le64 rsvd2;
550 } read;
551 struct {
552 struct {
553 struct {
554 union {
555 __le16 mirroring_status;
556 __le16 fcoe_ctx_id;
557 } mirr_fcoe;
558 __le16 l2tag1;
559 } lo_dword;
560 union {
561 __le32 rss; /* RSS Hash */
562 __le32 fcoe_param; /* FCoE DDP Context id */
563 /* Flow director filter id in case of
564 * Programming status desc WB
565 */
566 __le32 fd_id;
567 } hi_dword;
568 } qword0;
569 struct {
570 /* status/error/pktype/length */
571 __le64 status_error_len;
572 } qword1;
573 struct {
574 __le16 ext_status; /* extended status */
575 __le16 rsvd;
576 __le16 l2tag2_1;
577 __le16 l2tag2_2;
578 } qword2;
579 struct {
580 union {
581 __le32 flex_bytes_lo;
582 __le32 pe_status;
583 } lo_dword;
584 union {
585 __le32 flex_bytes_hi;
586 __le32 fd_id;
587 } hi_dword;
588 } qword3;
589 } wb; /* writeback */
590 };
591
592 enum i40e_rx_desc_status_bits {
593 /* Note: These are predefined bit offsets */
594 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
595 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
596 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
597 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
598 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
599 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
600 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
601 /* Note: Bit 8 is reserved in X710 and XL710 */
602 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
603 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
604 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
605 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
606 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
607 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
608 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
609 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
610 * UDP header
611 */
612 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
613 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
614 };
615
616 #define I40E_RXD_QW1_STATUS_SHIFT 0
617 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
618 << I40E_RXD_QW1_STATUS_SHIFT)
619
620 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
621 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
622 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
623
624 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
625 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
626 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
627
628 enum i40e_rx_desc_fltstat_values {
629 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
630 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
631 I40E_RX_DESC_FLTSTAT_RSV = 2,
632 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
633 };
634
635 #define I40E_RXD_QW1_ERROR_SHIFT 19
636 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
637
638 enum i40e_rx_desc_error_bits {
639 /* Note: These are predefined bit offsets */
640 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
641 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
642 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
643 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
644 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
645 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
646 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
647 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
648 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
649 };
650
651 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
652 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
653 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
654 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
655 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
656 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
657 };
658
659 #define I40E_RXD_QW1_PTYPE_SHIFT 30
660 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
661
662 /* Packet type non-ip values */
663 enum i40e_rx_l2_ptype {
664 I40E_RX_PTYPE_L2_RESERVED = 0,
665 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
666 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
667 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
668 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
669 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
670 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
671 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
672 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
673 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
674 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
675 I40E_RX_PTYPE_L2_ARP = 11,
676 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
677 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
678 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
679 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
680 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
681 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
682 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
683 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
684 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
685 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
686 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
687 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
688 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
689 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
690 };
691
692 struct i40e_rx_ptype_decoded {
693 u32 ptype:8;
694 u32 known:1;
695 u32 outer_ip:1;
696 u32 outer_ip_ver:1;
697 u32 outer_frag:1;
698 u32 tunnel_type:3;
699 u32 tunnel_end_prot:2;
700 u32 tunnel_end_frag:1;
701 u32 inner_prot:4;
702 u32 payload_layer:3;
703 };
704
705 enum i40e_rx_ptype_outer_ip {
706 I40E_RX_PTYPE_OUTER_L2 = 0,
707 I40E_RX_PTYPE_OUTER_IP = 1
708 };
709
710 enum i40e_rx_ptype_outer_ip_ver {
711 I40E_RX_PTYPE_OUTER_NONE = 0,
712 I40E_RX_PTYPE_OUTER_IPV4 = 0,
713 I40E_RX_PTYPE_OUTER_IPV6 = 1
714 };
715
716 enum i40e_rx_ptype_outer_fragmented {
717 I40E_RX_PTYPE_NOT_FRAG = 0,
718 I40E_RX_PTYPE_FRAG = 1
719 };
720
721 enum i40e_rx_ptype_tunnel_type {
722 I40E_RX_PTYPE_TUNNEL_NONE = 0,
723 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
724 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
725 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
726 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
727 };
728
729 enum i40e_rx_ptype_tunnel_end_prot {
730 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
731 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
732 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
733 };
734
735 enum i40e_rx_ptype_inner_prot {
736 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
737 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
738 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
739 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
740 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
741 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
742 };
743
744 enum i40e_rx_ptype_payload_layer {
745 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
746 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
747 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
748 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
749 };
750
751 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
752 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
753 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
754
755 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
756 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
757 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
758
759 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
760 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
761
762 enum i40e_rx_desc_ext_status_bits {
763 /* Note: These are predefined bit offsets */
764 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
765 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
766 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
767 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
768 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
769 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
770 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
771 };
772
773 enum i40e_rx_desc_pe_status_bits {
774 /* Note: These are predefined bit offsets */
775 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
776 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
777 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
778 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
779 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
780 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
781 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
782 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
783 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
784 };
785
786 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
787 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
788
789 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
790 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
791 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
792
793 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
794 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
795 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
796
797 enum i40e_rx_prog_status_desc_status_bits {
798 /* Note: These are predefined bit offsets */
799 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
800 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
801 };
802
803 enum i40e_rx_prog_status_desc_prog_id_masks {
804 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
805 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
806 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
807 };
808
809 enum i40e_rx_prog_status_desc_error_bits {
810 /* Note: These are predefined bit offsets */
811 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
812 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
813 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
814 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
815 };
816
817 /* TX Descriptor */
818 struct i40e_tx_desc {
819 __le64 buffer_addr; /* Address of descriptor's data buf */
820 __le64 cmd_type_offset_bsz;
821 };
822
823 #define I40E_TXD_QW1_DTYPE_SHIFT 0
824 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
825
826 enum i40e_tx_desc_dtype_value {
827 I40E_TX_DESC_DTYPE_DATA = 0x0,
828 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
829 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
830 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
831 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
832 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
833 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
834 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
835 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
836 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
837 };
838
839 #define I40E_TXD_QW1_CMD_SHIFT 4
840 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
841
842 enum i40e_tx_desc_cmd_bits {
843 I40E_TX_DESC_CMD_EOP = 0x0001,
844 I40E_TX_DESC_CMD_RS = 0x0002,
845 I40E_TX_DESC_CMD_ICRC = 0x0004,
846 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
847 I40E_TX_DESC_CMD_DUMMY = 0x0010,
848 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
849 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
850 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
851 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
852 I40E_TX_DESC_CMD_FCOET = 0x0080,
853 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
854 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
855 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
856 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
857 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
858 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
859 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
860 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
861 };
862
863 #define I40E_TXD_QW1_OFFSET_SHIFT 16
864 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
865 I40E_TXD_QW1_OFFSET_SHIFT)
866
867 enum i40e_tx_desc_length_fields {
868 /* Note: These are predefined bit offsets */
869 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
870 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
871 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
872 };
873
874 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
875 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
876 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
877
878 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
879 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
880
881 /* Context descriptors */
882 struct i40e_tx_context_desc {
883 __le32 tunneling_params;
884 __le16 l2tag2;
885 __le16 rsvd;
886 __le64 type_cmd_tso_mss;
887 };
888
889 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
890 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
891
892 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
893 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
894
895 enum i40e_tx_ctx_desc_cmd_bits {
896 I40E_TX_CTX_DESC_TSO = 0x01,
897 I40E_TX_CTX_DESC_TSYN = 0x02,
898 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
899 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
900 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
901 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
902 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
903 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
904 I40E_TX_CTX_DESC_SWPE = 0x40
905 };
906
907 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
908 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
909 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
910
911 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
912 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
913 I40E_TXD_CTX_QW1_MSS_SHIFT)
914
915 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
916 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
917
918 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
919 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
920 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
921
922 enum i40e_tx_ctx_desc_eipt_offload {
923 I40E_TX_CTX_EXT_IP_NONE = 0x0,
924 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
925 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
926 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
927 };
928
929 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
930 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
931 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
932
933 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
934 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
935
936 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
937 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
938
939 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
940 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
941 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
942
943 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
944
945 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
946 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
947 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
948
949 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
950 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
951 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
952
953 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
954 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
955 struct i40e_filter_program_desc {
956 __le32 qindex_flex_ptype_vsi;
957 __le32 rsvd;
958 __le32 dtype_cmd_cntindex;
959 __le32 fd_id;
960 };
961 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
962 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
963 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
964 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
965 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
966 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
967 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
968 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
969 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
970
971 /* Packet Classifier Types for filters */
972 enum i40e_filter_pctype {
973 /* Note: Values 0-28 are reserved for future use.
974 * Value 29, 30, 32 are not supported on XL710 and X710.
975 */
976 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
977 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
978 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
979 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
980 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
981 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
982 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
983 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
984 /* Note: Values 37-38 are reserved for future use.
985 * Value 39, 40, 42 are not supported on XL710 and X710.
986 */
987 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
988 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
989 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
990 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
991 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
992 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
993 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
994 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
995 /* Note: Value 47 is reserved for future use */
996 I40E_FILTER_PCTYPE_FCOE_OX = 48,
997 I40E_FILTER_PCTYPE_FCOE_RX = 49,
998 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
999 /* Note: Values 51-62 are reserved for future use */
1000 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1001 };
1002
1003 enum i40e_filter_program_desc_dest {
1004 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1005 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1006 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1007 };
1008
1009 enum i40e_filter_program_desc_fd_status {
1010 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1011 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1012 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1013 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1014 };
1015
1016 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1017 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1018 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1019
1020 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1021 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1022 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1023
1024 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1025 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1026
1027 enum i40e_filter_program_desc_pcmd {
1028 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1029 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1030 };
1031
1032 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1033 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1034
1035 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1036 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1037
1038 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1039 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1040 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1041 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1042
1043 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1044 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1045 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1046
1047 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1048 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1049 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1050
1051 enum i40e_filter_type {
1052 I40E_FLOW_DIRECTOR_FLTR = 0,
1053 I40E_PE_QUAD_HASH_FLTR = 1,
1054 I40E_ETHERTYPE_FLTR,
1055 I40E_FCOE_CTX_FLTR,
1056 I40E_MAC_VLAN_FLTR,
1057 I40E_HASH_FLTR
1058 };
1059
1060 struct i40e_vsi_context {
1061 u16 seid;
1062 u16 uplink_seid;
1063 u16 vsi_number;
1064 u16 vsis_allocated;
1065 u16 vsis_unallocated;
1066 u16 flags;
1067 u8 pf_num;
1068 u8 vf_num;
1069 u8 connection_type;
1070 struct i40e_aqc_vsi_properties_data info;
1071 };
1072
1073 struct i40e_veb_context {
1074 u16 seid;
1075 u16 uplink_seid;
1076 u16 veb_number;
1077 u16 vebs_allocated;
1078 u16 vebs_unallocated;
1079 u16 flags;
1080 struct i40e_aqc_get_veb_parameters_completion info;
1081 };
1082
1083 /* Statistics collected by each port, VSI, VEB, and S-channel */
1084 struct i40e_eth_stats {
1085 u64 rx_bytes; /* gorc */
1086 u64 rx_unicast; /* uprc */
1087 u64 rx_multicast; /* mprc */
1088 u64 rx_broadcast; /* bprc */
1089 u64 rx_discards; /* rdpc */
1090 u64 rx_unknown_protocol; /* rupp */
1091 u64 tx_bytes; /* gotc */
1092 u64 tx_unicast; /* uptc */
1093 u64 tx_multicast; /* mptc */
1094 u64 tx_broadcast; /* bptc */
1095 u64 tx_discards; /* tdpc */
1096 u64 tx_errors; /* tepc */
1097 };
1098
1099 /* Statistics collected per VEB per TC */
1100 struct i40e_veb_tc_stats {
1101 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1102 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1103 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1104 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1105 };
1106
1107 #ifdef I40E_FCOE
1108 /* Statistics collected per function for FCoE */
1109 struct i40e_fcoe_stats {
1110 u64 rx_fcoe_packets; /* fcoeprc */
1111 u64 rx_fcoe_dwords; /* focedwrc */
1112 u64 rx_fcoe_dropped; /* fcoerpdc */
1113 u64 tx_fcoe_packets; /* fcoeptc */
1114 u64 tx_fcoe_dwords; /* focedwtc */
1115 u64 fcoe_bad_fccrc; /* fcoecrc */
1116 u64 fcoe_last_error; /* fcoelast */
1117 u64 fcoe_ddp_count; /* fcoeddpc */
1118 };
1119
1120 /* offset to per function FCoE statistics block */
1121 #define I40E_FCOE_VF_STAT_OFFSET 0
1122 #define I40E_FCOE_PF_STAT_OFFSET 128
1123 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1124
1125 #endif
1126 /* Statistics collected by the MAC */
1127 struct i40e_hw_port_stats {
1128 /* eth stats collected by the port */
1129 struct i40e_eth_stats eth;
1130
1131 /* additional port specific stats */
1132 u64 tx_dropped_link_down; /* tdold */
1133 u64 crc_errors; /* crcerrs */
1134 u64 illegal_bytes; /* illerrc */
1135 u64 error_bytes; /* errbc */
1136 u64 mac_local_faults; /* mlfc */
1137 u64 mac_remote_faults; /* mrfc */
1138 u64 rx_length_errors; /* rlec */
1139 u64 link_xon_rx; /* lxonrxc */
1140 u64 link_xoff_rx; /* lxoffrxc */
1141 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1142 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1143 u64 link_xon_tx; /* lxontxc */
1144 u64 link_xoff_tx; /* lxofftxc */
1145 u64 priority_xon_tx[8]; /* pxontxc[8] */
1146 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1147 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1148 u64 rx_size_64; /* prc64 */
1149 u64 rx_size_127; /* prc127 */
1150 u64 rx_size_255; /* prc255 */
1151 u64 rx_size_511; /* prc511 */
1152 u64 rx_size_1023; /* prc1023 */
1153 u64 rx_size_1522; /* prc1522 */
1154 u64 rx_size_big; /* prc9522 */
1155 u64 rx_undersize; /* ruc */
1156 u64 rx_fragments; /* rfc */
1157 u64 rx_oversize; /* roc */
1158 u64 rx_jabber; /* rjc */
1159 u64 tx_size_64; /* ptc64 */
1160 u64 tx_size_127; /* ptc127 */
1161 u64 tx_size_255; /* ptc255 */
1162 u64 tx_size_511; /* ptc511 */
1163 u64 tx_size_1023; /* ptc1023 */
1164 u64 tx_size_1522; /* ptc1522 */
1165 u64 tx_size_big; /* ptc9522 */
1166 u64 mac_short_packet_dropped; /* mspdc */
1167 u64 checksum_error; /* xec */
1168 /* flow director stats */
1169 u64 fd_atr_match;
1170 u64 fd_sb_match;
1171 u64 fd_atr_tunnel_match;
1172 u32 fd_atr_status;
1173 u32 fd_sb_status;
1174 /* EEE LPI */
1175 u32 tx_lpi_status;
1176 u32 rx_lpi_status;
1177 u64 tx_lpi_count; /* etlpic */
1178 u64 rx_lpi_count; /* erlpic */
1179 };
1180
1181 /* Checksum and Shadow RAM pointers */
1182 #define I40E_SR_NVM_CONTROL_WORD 0x00
1183 #define I40E_SR_EMP_MODULE_PTR 0x0F
1184 #define I40E_SR_PBA_FLAGS 0x15
1185 #define I40E_SR_PBA_BLOCK_PTR 0x16
1186 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1187 #define I40E_NVM_OEM_VER_OFF 0x83
1188 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1189 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1190 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1191 #define I40E_SR_NVM_EETRACK_LO 0x2D
1192 #define I40E_SR_NVM_EETRACK_HI 0x2E
1193 #define I40E_SR_VPD_PTR 0x2F
1194 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1195 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1196
1197 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1198 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1199 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1200 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1201 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1202
1203 /* Shadow RAM related */
1204 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1205 #define I40E_SR_WORDS_IN_1KB 512
1206 /* Checksum should be calculated such that after adding all the words,
1207 * including the checksum word itself, the sum should be 0xBABA.
1208 */
1209 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1210
1211 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1212
1213 #ifdef I40E_FCOE
1214 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1215
1216 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1217 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1218 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1219 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1220 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1221 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1222 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1223 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1224 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1225 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1226 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1227 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1228 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1229 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1230 };
1231
1232 /* FCoE DDP Context descriptor */
1233 struct i40e_fcoe_ddp_context_desc {
1234 __le64 rsvd;
1235 __le64 type_cmd_foff_lsize;
1236 };
1237
1238 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1239 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1240 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1241
1242 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1243 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1244 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1245
1246 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1247 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1248 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1249 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1250 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1251 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1252 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1253 };
1254
1255 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1256 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1257 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1258
1259 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1260 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1261 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1262
1263 /* FCoE DDP/DWO Queue Context descriptor */
1264 struct i40e_fcoe_queue_context_desc {
1265 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1266 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1267 };
1268
1269 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1270 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1271 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1272
1273 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1274 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1275 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1276
1277 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1278 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1279 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1280
1281 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1282 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1283 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1284
1285 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1286 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1287 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1288 };
1289
1290 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1291 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1292 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1293
1294 /* FCoE DDP/DWO Filter Context descriptor */
1295 struct i40e_fcoe_filter_context_desc {
1296 __le32 param;
1297 __le16 seqn;
1298
1299 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1300 __le16 rsvd_dmaindx;
1301
1302 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1303 __le64 flags_rsvd_lanq;
1304 };
1305
1306 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1307 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1308 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1309
1310 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1311 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1312 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1313 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1314 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1315 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1316 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1317 };
1318
1319 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1320 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1321 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1322
1323 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1324 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1325 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1326
1327 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1328 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1329 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1330
1331 #endif /* I40E_FCOE */
1332 enum i40e_switch_element_types {
1333 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1334 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1335 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1336 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1337 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1338 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1339 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1340 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1341 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1342 };
1343
1344 /* Supported EtherType filters */
1345 enum i40e_ether_type_index {
1346 I40E_ETHER_TYPE_1588 = 0,
1347 I40E_ETHER_TYPE_FIP = 1,
1348 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1349 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1350 I40E_ETHER_TYPE_LLDP = 4,
1351 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1352 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1353 I40E_ETHER_TYPE_QCN_CNM = 7,
1354 I40E_ETHER_TYPE_8021X = 8,
1355 I40E_ETHER_TYPE_ARP = 9,
1356 I40E_ETHER_TYPE_RSV1 = 10,
1357 I40E_ETHER_TYPE_RSV2 = 11,
1358 };
1359
1360 /* Filter context base size is 1K */
1361 #define I40E_HASH_FILTER_BASE_SIZE 1024
1362 /* Supported Hash filter values */
1363 enum i40e_hash_filter_size {
1364 I40E_HASH_FILTER_SIZE_1K = 0,
1365 I40E_HASH_FILTER_SIZE_2K = 1,
1366 I40E_HASH_FILTER_SIZE_4K = 2,
1367 I40E_HASH_FILTER_SIZE_8K = 3,
1368 I40E_HASH_FILTER_SIZE_16K = 4,
1369 I40E_HASH_FILTER_SIZE_32K = 5,
1370 I40E_HASH_FILTER_SIZE_64K = 6,
1371 I40E_HASH_FILTER_SIZE_128K = 7,
1372 I40E_HASH_FILTER_SIZE_256K = 8,
1373 I40E_HASH_FILTER_SIZE_512K = 9,
1374 I40E_HASH_FILTER_SIZE_1M = 10,
1375 };
1376
1377 /* DMA context base size is 0.5K */
1378 #define I40E_DMA_CNTX_BASE_SIZE 512
1379 /* Supported DMA context values */
1380 enum i40e_dma_cntx_size {
1381 I40E_DMA_CNTX_SIZE_512 = 0,
1382 I40E_DMA_CNTX_SIZE_1K = 1,
1383 I40E_DMA_CNTX_SIZE_2K = 2,
1384 I40E_DMA_CNTX_SIZE_4K = 3,
1385 I40E_DMA_CNTX_SIZE_8K = 4,
1386 I40E_DMA_CNTX_SIZE_16K = 5,
1387 I40E_DMA_CNTX_SIZE_32K = 6,
1388 I40E_DMA_CNTX_SIZE_64K = 7,
1389 I40E_DMA_CNTX_SIZE_128K = 8,
1390 I40E_DMA_CNTX_SIZE_256K = 9,
1391 };
1392
1393 /* Supported Hash look up table (LUT) sizes */
1394 enum i40e_hash_lut_size {
1395 I40E_HASH_LUT_SIZE_128 = 0,
1396 I40E_HASH_LUT_SIZE_512 = 1,
1397 };
1398
1399 /* Structure to hold a per PF filter control settings */
1400 struct i40e_filter_control_settings {
1401 /* number of PE Quad Hash filter buckets */
1402 enum i40e_hash_filter_size pe_filt_num;
1403 /* number of PE Quad Hash contexts */
1404 enum i40e_dma_cntx_size pe_cntx_num;
1405 /* number of FCoE filter buckets */
1406 enum i40e_hash_filter_size fcoe_filt_num;
1407 /* number of FCoE DDP contexts */
1408 enum i40e_dma_cntx_size fcoe_cntx_num;
1409 /* size of the Hash LUT */
1410 enum i40e_hash_lut_size hash_lut_size;
1411 /* enable FDIR filters for PF and its VFs */
1412 bool enable_fdir;
1413 /* enable Ethertype filters for PF and its VFs */
1414 bool enable_ethtype;
1415 /* enable MAC/VLAN filters for PF and its VFs */
1416 bool enable_macvlan;
1417 };
1418
1419 /* Structure to hold device level control filter counts */
1420 struct i40e_control_filter_stats {
1421 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1422 u16 etype_used; /* Used perfect EtherType filters */
1423 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1424 u16 etype_free; /* Un-used perfect EtherType filters */
1425 };
1426
1427 enum i40e_reset_type {
1428 I40E_RESET_POR = 0,
1429 I40E_RESET_CORER = 1,
1430 I40E_RESET_GLOBR = 2,
1431 I40E_RESET_EMPR = 3,
1432 };
1433
1434 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1435 #define I40E_NVM_LLDP_CFG_PTR 0xD
1436 struct i40e_lldp_variables {
1437 u16 length;
1438 u16 adminstatus;
1439 u16 msgfasttx;
1440 u16 msgtxinterval;
1441 u16 txparams;
1442 u16 timers;
1443 u16 crc8;
1444 };
1445
1446 /* Offsets into Alternate Ram */
1447 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1448 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1449 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1450 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1451 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1452 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1453
1454 /* Alternate Ram Bandwidth Masks */
1455 #define I40E_ALT_BW_VALUE_MASK 0xFF
1456 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1457 #define I40E_ALT_BW_VALID_MASK 0x80000000
1458
1459 /* RSS Hash Table Size */
1460 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1461 #endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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