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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_type.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36
37 /* Device IDs */
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_20G_KR2 0x1587
48 #define I40E_DEV_ID_VF 0x154C
49 #define I40E_DEV_ID_VF_HV 0x1571
50 #define I40E_DEV_ID_SFP_X722 0x37D0
51 #define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
52 #define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
53 #define I40E_DEV_ID_X722_VF 0x37CD
54 #define I40E_DEV_ID_X722_VF_HV 0x37D9
55
56 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
57 (d) == I40E_DEV_ID_QSFP_B || \
58 (d) == I40E_DEV_ID_QSFP_C)
59
60 /* I40E_MASK is a macro used on 32 bit registers */
61 #define I40E_MASK(mask, shift) (mask << shift)
62
63 #define I40E_MAX_VSI_QP 16
64 #define I40E_MAX_VF_VSI 3
65 #define I40E_MAX_CHAINED_RX_BUFFERS 5
66 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
67
68 /* Max default timeout in ms, */
69 #define I40E_MAX_NVM_TIMEOUT 18000
70
71 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
72 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
73
74 /* forward declaration */
75 struct i40e_hw;
76 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
77
78 /* Data type manipulation macros. */
79
80 #define I40E_DESC_UNUSED(R) \
81 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
82 (R)->next_to_clean - (R)->next_to_use - 1)
83
84 /* bitfields for Tx queue mapping in QTX_CTL */
85 #define I40E_QTX_CTL_VF_QUEUE 0x0
86 #define I40E_QTX_CTL_VM_QUEUE 0x1
87 #define I40E_QTX_CTL_PF_QUEUE 0x2
88
89 /* debug masks - set these bits in hw->debug_mask to control output */
90 enum i40e_debug_mask {
91 I40E_DEBUG_INIT = 0x00000001,
92 I40E_DEBUG_RELEASE = 0x00000002,
93
94 I40E_DEBUG_LINK = 0x00000010,
95 I40E_DEBUG_PHY = 0x00000020,
96 I40E_DEBUG_HMC = 0x00000040,
97 I40E_DEBUG_NVM = 0x00000080,
98 I40E_DEBUG_LAN = 0x00000100,
99 I40E_DEBUG_FLOW = 0x00000200,
100 I40E_DEBUG_DCB = 0x00000400,
101 I40E_DEBUG_DIAG = 0x00000800,
102 I40E_DEBUG_FD = 0x00001000,
103
104 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
105 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
106 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
107 I40E_DEBUG_AQ_COMMAND = 0x06000000,
108 I40E_DEBUG_AQ = 0x0F000000,
109
110 I40E_DEBUG_USER = 0xF0000000,
111
112 I40E_DEBUG_ALL = 0xFFFFFFFF
113 };
114
115 /* These are structs for managing the hardware information and the operations.
116 * The structures of function pointers are filled out at init time when we
117 * know for sure exactly which hardware we're working with. This gives us the
118 * flexibility of using the same main driver code but adapting to slightly
119 * different hardware needs as new parts are developed. For this architecture,
120 * the Firmware and AdminQ are intended to insulate the driver from most of the
121 * future changes, but these structures will also do part of the job.
122 */
123 enum i40e_mac_type {
124 I40E_MAC_UNKNOWN = 0,
125 I40E_MAC_X710,
126 I40E_MAC_XL710,
127 I40E_MAC_VF,
128 I40E_MAC_X722,
129 I40E_MAC_X722_VF,
130 I40E_MAC_GENERIC,
131 };
132
133 enum i40e_media_type {
134 I40E_MEDIA_TYPE_UNKNOWN = 0,
135 I40E_MEDIA_TYPE_FIBER,
136 I40E_MEDIA_TYPE_BASET,
137 I40E_MEDIA_TYPE_BACKPLANE,
138 I40E_MEDIA_TYPE_CX4,
139 I40E_MEDIA_TYPE_DA,
140 I40E_MEDIA_TYPE_VIRTUAL
141 };
142
143 enum i40e_fc_mode {
144 I40E_FC_NONE = 0,
145 I40E_FC_RX_PAUSE,
146 I40E_FC_TX_PAUSE,
147 I40E_FC_FULL,
148 I40E_FC_PFC,
149 I40E_FC_DEFAULT
150 };
151
152 enum i40e_set_fc_aq_failures {
153 I40E_SET_FC_AQ_FAIL_NONE = 0,
154 I40E_SET_FC_AQ_FAIL_GET = 1,
155 I40E_SET_FC_AQ_FAIL_SET = 2,
156 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
157 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
158 };
159
160 enum i40e_vsi_type {
161 I40E_VSI_MAIN = 0,
162 I40E_VSI_VMDQ1,
163 I40E_VSI_VMDQ2,
164 I40E_VSI_CTRL,
165 I40E_VSI_FCOE,
166 I40E_VSI_MIRROR,
167 I40E_VSI_SRIOV,
168 I40E_VSI_FDIR,
169 I40E_VSI_TYPE_UNKNOWN
170 };
171
172 enum i40e_queue_type {
173 I40E_QUEUE_TYPE_RX = 0,
174 I40E_QUEUE_TYPE_TX,
175 I40E_QUEUE_TYPE_PE_CEQ,
176 I40E_QUEUE_TYPE_UNKNOWN
177 };
178
179 struct i40e_link_status {
180 enum i40e_aq_phy_type phy_type;
181 enum i40e_aq_link_speed link_speed;
182 u8 link_info;
183 u8 an_info;
184 u8 ext_info;
185 u8 loopback;
186 /* is Link Status Event notification to SW enabled */
187 bool lse_enable;
188 u16 max_frame_size;
189 bool crc_enable;
190 u8 pacing;
191 u8 requested_speeds;
192 };
193
194 struct i40e_phy_info {
195 struct i40e_link_status link_info;
196 struct i40e_link_status link_info_old;
197 u32 autoneg_advertised;
198 u32 phy_id;
199 u32 module_type;
200 bool get_link_info;
201 enum i40e_media_type media_type;
202 };
203
204 #define I40E_HW_CAP_MAX_GPIO 30
205 /* Capabilities of a PF or a VF or the whole device */
206 struct i40e_hw_capabilities {
207 u32 switch_mode;
208 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
209 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
210 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
211
212 u32 management_mode;
213 u32 npar_enable;
214 u32 os2bmc;
215 u32 valid_functions;
216 bool sr_iov_1_1;
217 bool vmdq;
218 bool evb_802_1_qbg; /* Edge Virtual Bridging */
219 bool evb_802_1_qbh; /* Bridge Port Extension */
220 bool dcb;
221 bool fcoe;
222 bool iscsi; /* Indicates iSCSI enabled */
223 bool flex10_enable;
224 bool flex10_capable;
225 u32 flex10_mode;
226 #define I40E_FLEX10_MODE_UNKNOWN 0x0
227 #define I40E_FLEX10_MODE_DCC 0x1
228 #define I40E_FLEX10_MODE_DCI 0x2
229
230 u32 flex10_status;
231 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
232 #define I40E_FLEX10_STATUS_VC_MODE 0x2
233
234 bool mgmt_cem;
235 bool ieee_1588;
236 bool iwarp;
237 bool fd;
238 u32 fd_filters_guaranteed;
239 u32 fd_filters_best_effort;
240 bool rss;
241 u32 rss_table_size;
242 u32 rss_table_entry_width;
243 bool led[I40E_HW_CAP_MAX_GPIO];
244 bool sdp[I40E_HW_CAP_MAX_GPIO];
245 u32 nvm_image_type;
246 u32 num_flow_director_filters;
247 u32 num_vfs;
248 u32 vf_base_id;
249 u32 num_vsis;
250 u32 num_rx_qp;
251 u32 num_tx_qp;
252 u32 base_queue;
253 u32 num_msix_vectors;
254 u32 num_msix_vectors_vf;
255 u32 led_pin_num;
256 u32 sdp_pin_num;
257 u32 mdio_port_num;
258 u32 mdio_port_mode;
259 u8 rx_buf_chain_len;
260 u32 enabled_tcmap;
261 u32 maxtc;
262 u64 wr_csr_prot;
263 };
264
265 struct i40e_mac_info {
266 enum i40e_mac_type type;
267 u8 addr[ETH_ALEN];
268 u8 perm_addr[ETH_ALEN];
269 u8 san_addr[ETH_ALEN];
270 u8 port_addr[ETH_ALEN];
271 u16 max_fcoeq;
272 };
273
274 enum i40e_aq_resources_ids {
275 I40E_NVM_RESOURCE_ID = 1
276 };
277
278 enum i40e_aq_resource_access_type {
279 I40E_RESOURCE_READ = 1,
280 I40E_RESOURCE_WRITE
281 };
282
283 struct i40e_nvm_info {
284 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
285 u32 timeout; /* [ms] */
286 u16 sr_size; /* Shadow RAM size in words */
287 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
288 u16 version; /* NVM package version */
289 u32 eetrack; /* NVM data version */
290 };
291
292 /* definitions used in NVM update support */
293
294 enum i40e_nvmupd_cmd {
295 I40E_NVMUPD_INVALID,
296 I40E_NVMUPD_READ_CON,
297 I40E_NVMUPD_READ_SNT,
298 I40E_NVMUPD_READ_LCB,
299 I40E_NVMUPD_READ_SA,
300 I40E_NVMUPD_WRITE_ERA,
301 I40E_NVMUPD_WRITE_CON,
302 I40E_NVMUPD_WRITE_SNT,
303 I40E_NVMUPD_WRITE_LCB,
304 I40E_NVMUPD_WRITE_SA,
305 I40E_NVMUPD_CSUM_CON,
306 I40E_NVMUPD_CSUM_SA,
307 I40E_NVMUPD_CSUM_LCB,
308 I40E_NVMUPD_STATUS,
309 I40E_NVMUPD_EXEC_AQ,
310 I40E_NVMUPD_GET_AQ_RESULT,
311 };
312
313 enum i40e_nvmupd_state {
314 I40E_NVMUPD_STATE_INIT,
315 I40E_NVMUPD_STATE_READING,
316 I40E_NVMUPD_STATE_WRITING,
317 I40E_NVMUPD_STATE_INIT_WAIT,
318 I40E_NVMUPD_STATE_WRITE_WAIT,
319 };
320
321 /* nvm_access definition and its masks/shifts need to be accessible to
322 * application, core driver, and shared code. Where is the right file?
323 */
324 #define I40E_NVM_READ 0xB
325 #define I40E_NVM_WRITE 0xC
326
327 #define I40E_NVM_MOD_PNT_MASK 0xFF
328
329 #define I40E_NVM_TRANS_SHIFT 8
330 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
331 #define I40E_NVM_CON 0x0
332 #define I40E_NVM_SNT 0x1
333 #define I40E_NVM_LCB 0x2
334 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
335 #define I40E_NVM_ERA 0x4
336 #define I40E_NVM_CSUM 0x8
337 #define I40E_NVM_EXEC 0xf
338
339 #define I40E_NVM_ADAPT_SHIFT 16
340 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
341
342 #define I40E_NVMUPD_MAX_DATA 4096
343 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
344
345 struct i40e_nvm_access {
346 u32 command;
347 u32 config;
348 u32 offset; /* in bytes */
349 u32 data_size; /* in bytes */
350 u8 data[1];
351 };
352
353 /* PCI bus types */
354 enum i40e_bus_type {
355 i40e_bus_type_unknown = 0,
356 i40e_bus_type_pci,
357 i40e_bus_type_pcix,
358 i40e_bus_type_pci_express,
359 i40e_bus_type_reserved
360 };
361
362 /* PCI bus speeds */
363 enum i40e_bus_speed {
364 i40e_bus_speed_unknown = 0,
365 i40e_bus_speed_33 = 33,
366 i40e_bus_speed_66 = 66,
367 i40e_bus_speed_100 = 100,
368 i40e_bus_speed_120 = 120,
369 i40e_bus_speed_133 = 133,
370 i40e_bus_speed_2500 = 2500,
371 i40e_bus_speed_5000 = 5000,
372 i40e_bus_speed_8000 = 8000,
373 i40e_bus_speed_reserved
374 };
375
376 /* PCI bus widths */
377 enum i40e_bus_width {
378 i40e_bus_width_unknown = 0,
379 i40e_bus_width_pcie_x1 = 1,
380 i40e_bus_width_pcie_x2 = 2,
381 i40e_bus_width_pcie_x4 = 4,
382 i40e_bus_width_pcie_x8 = 8,
383 i40e_bus_width_32 = 32,
384 i40e_bus_width_64 = 64,
385 i40e_bus_width_reserved
386 };
387
388 /* Bus parameters */
389 struct i40e_bus_info {
390 enum i40e_bus_speed speed;
391 enum i40e_bus_width width;
392 enum i40e_bus_type type;
393
394 u16 func;
395 u16 device;
396 u16 lan_id;
397 };
398
399 /* Flow control (FC) parameters */
400 struct i40e_fc_info {
401 enum i40e_fc_mode current_mode; /* FC mode in effect */
402 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
403 };
404
405 #define I40E_MAX_TRAFFIC_CLASS 8
406 #define I40E_MAX_USER_PRIORITY 8
407 #define I40E_DCBX_MAX_APPS 32
408 #define I40E_LLDPDU_SIZE 1500
409 #define I40E_TLV_STATUS_OPER 0x1
410 #define I40E_TLV_STATUS_SYNC 0x2
411 #define I40E_TLV_STATUS_ERR 0x4
412 #define I40E_CEE_OPER_MAX_APPS 3
413 #define I40E_APP_PROTOID_FCOE 0x8906
414 #define I40E_APP_PROTOID_ISCSI 0x0cbc
415 #define I40E_APP_PROTOID_FIP 0x8914
416 #define I40E_APP_SEL_ETHTYPE 0x1
417 #define I40E_APP_SEL_TCPIP 0x2
418
419 /* CEE or IEEE 802.1Qaz ETS Configuration data */
420 struct i40e_dcb_ets_config {
421 u8 willing;
422 u8 cbs;
423 u8 maxtcs;
424 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
425 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
426 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
427 };
428
429 /* CEE or IEEE 802.1Qaz PFC Configuration data */
430 struct i40e_dcb_pfc_config {
431 u8 willing;
432 u8 mbc;
433 u8 pfccap;
434 u8 pfcenable;
435 };
436
437 /* CEE or IEEE 802.1Qaz Application Priority data */
438 struct i40e_dcb_app_priority_table {
439 u8 priority;
440 u8 selector;
441 u16 protocolid;
442 };
443
444 struct i40e_dcbx_config {
445 u8 dcbx_mode;
446 #define I40E_DCBX_MODE_CEE 0x1
447 #define I40E_DCBX_MODE_IEEE 0x2
448 u32 numapps;
449 u32 tlv_status; /* CEE mode TLV status */
450 struct i40e_dcb_ets_config etscfg;
451 struct i40e_dcb_ets_config etsrec;
452 struct i40e_dcb_pfc_config pfc;
453 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
454 };
455
456 /* Port hardware description */
457 struct i40e_hw {
458 u8 __iomem *hw_addr;
459 void *back;
460
461 /* subsystem structs */
462 struct i40e_phy_info phy;
463 struct i40e_mac_info mac;
464 struct i40e_bus_info bus;
465 struct i40e_nvm_info nvm;
466 struct i40e_fc_info fc;
467
468 /* pci info */
469 u16 device_id;
470 u16 vendor_id;
471 u16 subsystem_device_id;
472 u16 subsystem_vendor_id;
473 u8 revision_id;
474 u8 port;
475 bool adapter_stopped;
476
477 /* capabilities for entire device and PCI func */
478 struct i40e_hw_capabilities dev_caps;
479 struct i40e_hw_capabilities func_caps;
480
481 /* Flow Director shared filter space */
482 u16 fdir_shared_filter_count;
483
484 /* device profile info */
485 u8 pf_id;
486 u16 main_vsi_seid;
487
488 /* for multi-function MACs */
489 u16 partition_id;
490 u16 num_partitions;
491 u16 num_ports;
492
493 /* Closest numa node to the device */
494 u16 numa_node;
495
496 /* Admin Queue info */
497 struct i40e_adminq_info aq;
498
499 /* state of nvm update process */
500 enum i40e_nvmupd_state nvmupd_state;
501 struct i40e_aq_desc nvm_wb_desc;
502 struct i40e_virt_mem nvm_buff;
503
504 /* HMC info */
505 struct i40e_hmc_info hmc; /* HMC info struct */
506
507 /* LLDP/DCBX Status */
508 u16 dcbx_status;
509
510 /* DCBX info */
511 struct i40e_dcbx_config local_dcbx_config;
512 struct i40e_dcbx_config remote_dcbx_config;
513
514 /* debug mask */
515 u32 debug_mask;
516 char err_str[16];
517 };
518
519 static inline bool i40e_is_vf(struct i40e_hw *hw)
520 {
521 return (hw->mac.type == I40E_MAC_VF ||
522 hw->mac.type == I40E_MAC_X722_VF);
523 }
524
525 struct i40e_driver_version {
526 u8 major_version;
527 u8 minor_version;
528 u8 build_version;
529 u8 subbuild_version;
530 u8 driver_string[32];
531 };
532
533 /* RX Descriptors */
534 union i40e_16byte_rx_desc {
535 struct {
536 __le64 pkt_addr; /* Packet buffer address */
537 __le64 hdr_addr; /* Header buffer address */
538 } read;
539 struct {
540 struct {
541 struct {
542 union {
543 __le16 mirroring_status;
544 __le16 fcoe_ctx_id;
545 } mirr_fcoe;
546 __le16 l2tag1;
547 } lo_dword;
548 union {
549 __le32 rss; /* RSS Hash */
550 __le32 fd_id; /* Flow director filter id */
551 __le32 fcoe_param; /* FCoE DDP Context id */
552 } hi_dword;
553 } qword0;
554 struct {
555 /* ext status/error/pktype/length */
556 __le64 status_error_len;
557 } qword1;
558 } wb; /* writeback */
559 };
560
561 union i40e_32byte_rx_desc {
562 struct {
563 __le64 pkt_addr; /* Packet buffer address */
564 __le64 hdr_addr; /* Header buffer address */
565 /* bit 0 of hdr_buffer_addr is DD bit */
566 __le64 rsvd1;
567 __le64 rsvd2;
568 } read;
569 struct {
570 struct {
571 struct {
572 union {
573 __le16 mirroring_status;
574 __le16 fcoe_ctx_id;
575 } mirr_fcoe;
576 __le16 l2tag1;
577 } lo_dword;
578 union {
579 __le32 rss; /* RSS Hash */
580 __le32 fcoe_param; /* FCoE DDP Context id */
581 /* Flow director filter id in case of
582 * Programming status desc WB
583 */
584 __le32 fd_id;
585 } hi_dword;
586 } qword0;
587 struct {
588 /* status/error/pktype/length */
589 __le64 status_error_len;
590 } qword1;
591 struct {
592 __le16 ext_status; /* extended status */
593 __le16 rsvd;
594 __le16 l2tag2_1;
595 __le16 l2tag2_2;
596 } qword2;
597 struct {
598 union {
599 __le32 flex_bytes_lo;
600 __le32 pe_status;
601 } lo_dword;
602 union {
603 __le32 flex_bytes_hi;
604 __le32 fd_id;
605 } hi_dword;
606 } qword3;
607 } wb; /* writeback */
608 };
609
610 enum i40e_rx_desc_status_bits {
611 /* Note: These are predefined bit offsets */
612 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
613 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
614 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
615 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
616 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
617 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
618 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
619 /* Note: Bit 8 is reserved in X710 and XL710 */
620 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
621 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
622 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
623 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
624 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
625 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
626 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
627 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
628 * UDP header
629 */
630 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
631 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
632 };
633
634 #define I40E_RXD_QW1_STATUS_SHIFT 0
635 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
636 << I40E_RXD_QW1_STATUS_SHIFT)
637
638 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
639 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
640 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
641
642 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
643 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
644 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
645
646 enum i40e_rx_desc_fltstat_values {
647 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
648 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
649 I40E_RX_DESC_FLTSTAT_RSV = 2,
650 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
651 };
652
653 #define I40E_RXD_QW1_ERROR_SHIFT 19
654 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
655
656 enum i40e_rx_desc_error_bits {
657 /* Note: These are predefined bit offsets */
658 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
659 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
660 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
661 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
662 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
663 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
664 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
665 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
666 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
667 };
668
669 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
670 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
671 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
672 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
673 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
674 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
675 };
676
677 #define I40E_RXD_QW1_PTYPE_SHIFT 30
678 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
679
680 /* Packet type non-ip values */
681 enum i40e_rx_l2_ptype {
682 I40E_RX_PTYPE_L2_RESERVED = 0,
683 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
684 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
685 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
686 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
687 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
688 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
689 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
690 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
691 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
692 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
693 I40E_RX_PTYPE_L2_ARP = 11,
694 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
695 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
696 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
697 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
698 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
699 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
700 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
701 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
702 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
703 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
704 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
705 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
706 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
707 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
708 };
709
710 struct i40e_rx_ptype_decoded {
711 u32 ptype:8;
712 u32 known:1;
713 u32 outer_ip:1;
714 u32 outer_ip_ver:1;
715 u32 outer_frag:1;
716 u32 tunnel_type:3;
717 u32 tunnel_end_prot:2;
718 u32 tunnel_end_frag:1;
719 u32 inner_prot:4;
720 u32 payload_layer:3;
721 };
722
723 enum i40e_rx_ptype_outer_ip {
724 I40E_RX_PTYPE_OUTER_L2 = 0,
725 I40E_RX_PTYPE_OUTER_IP = 1
726 };
727
728 enum i40e_rx_ptype_outer_ip_ver {
729 I40E_RX_PTYPE_OUTER_NONE = 0,
730 I40E_RX_PTYPE_OUTER_IPV4 = 0,
731 I40E_RX_PTYPE_OUTER_IPV6 = 1
732 };
733
734 enum i40e_rx_ptype_outer_fragmented {
735 I40E_RX_PTYPE_NOT_FRAG = 0,
736 I40E_RX_PTYPE_FRAG = 1
737 };
738
739 enum i40e_rx_ptype_tunnel_type {
740 I40E_RX_PTYPE_TUNNEL_NONE = 0,
741 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
742 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
743 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
744 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
745 };
746
747 enum i40e_rx_ptype_tunnel_end_prot {
748 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
749 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
750 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
751 };
752
753 enum i40e_rx_ptype_inner_prot {
754 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
755 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
756 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
757 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
758 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
759 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
760 };
761
762 enum i40e_rx_ptype_payload_layer {
763 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
764 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
765 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
766 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
767 };
768
769 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
770 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
771 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
772
773 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
774 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
775 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
776
777 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
778 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
779
780 enum i40e_rx_desc_ext_status_bits {
781 /* Note: These are predefined bit offsets */
782 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
783 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
784 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
785 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
786 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
787 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
788 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
789 };
790
791 enum i40e_rx_desc_pe_status_bits {
792 /* Note: These are predefined bit offsets */
793 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
794 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
795 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
796 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
797 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
798 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
799 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
800 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
801 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
802 };
803
804 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
805 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
806
807 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
808 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
809 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
810
811 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
812 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
813 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
814
815 enum i40e_rx_prog_status_desc_status_bits {
816 /* Note: These are predefined bit offsets */
817 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
818 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
819 };
820
821 enum i40e_rx_prog_status_desc_prog_id_masks {
822 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
823 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
824 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
825 };
826
827 enum i40e_rx_prog_status_desc_error_bits {
828 /* Note: These are predefined bit offsets */
829 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
830 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
831 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
832 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
833 };
834
835 /* TX Descriptor */
836 struct i40e_tx_desc {
837 __le64 buffer_addr; /* Address of descriptor's data buf */
838 __le64 cmd_type_offset_bsz;
839 };
840
841 #define I40E_TXD_QW1_DTYPE_SHIFT 0
842 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
843
844 enum i40e_tx_desc_dtype_value {
845 I40E_TX_DESC_DTYPE_DATA = 0x0,
846 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
847 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
848 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
849 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
850 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
851 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
852 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
853 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
854 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
855 };
856
857 #define I40E_TXD_QW1_CMD_SHIFT 4
858 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
859
860 enum i40e_tx_desc_cmd_bits {
861 I40E_TX_DESC_CMD_EOP = 0x0001,
862 I40E_TX_DESC_CMD_RS = 0x0002,
863 I40E_TX_DESC_CMD_ICRC = 0x0004,
864 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
865 I40E_TX_DESC_CMD_DUMMY = 0x0010,
866 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
867 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
868 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
869 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
870 I40E_TX_DESC_CMD_FCOET = 0x0080,
871 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
872 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
873 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
874 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
875 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
876 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
877 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
878 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
879 };
880
881 #define I40E_TXD_QW1_OFFSET_SHIFT 16
882 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
883 I40E_TXD_QW1_OFFSET_SHIFT)
884
885 enum i40e_tx_desc_length_fields {
886 /* Note: These are predefined bit offsets */
887 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
888 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
889 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
890 };
891
892 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
893 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
894 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
895
896 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
897 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
898
899 /* Context descriptors */
900 struct i40e_tx_context_desc {
901 __le32 tunneling_params;
902 __le16 l2tag2;
903 __le16 rsvd;
904 __le64 type_cmd_tso_mss;
905 };
906
907 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
908 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
909
910 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
911 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
912
913 enum i40e_tx_ctx_desc_cmd_bits {
914 I40E_TX_CTX_DESC_TSO = 0x01,
915 I40E_TX_CTX_DESC_TSYN = 0x02,
916 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
917 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
918 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
919 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
920 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
921 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
922 I40E_TX_CTX_DESC_SWPE = 0x40
923 };
924
925 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
926 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
927 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
928
929 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
930 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
931 I40E_TXD_CTX_QW1_MSS_SHIFT)
932
933 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
934 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
935
936 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
937 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
938 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
939
940 enum i40e_tx_ctx_desc_eipt_offload {
941 I40E_TX_CTX_EXT_IP_NONE = 0x0,
942 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
943 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
944 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
945 };
946
947 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
948 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
949 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
950
951 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
952 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
953
954 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
955 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
956
957 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
958 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
959 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
960
961 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
962
963 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
964 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
965 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
966
967 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
968 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
969 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
970
971 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
972 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
973 struct i40e_filter_program_desc {
974 __le32 qindex_flex_ptype_vsi;
975 __le32 rsvd;
976 __le32 dtype_cmd_cntindex;
977 __le32 fd_id;
978 };
979 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
980 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
981 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
982 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
983 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
984 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
985 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
986 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
987 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
988
989 /* Packet Classifier Types for filters */
990 enum i40e_filter_pctype {
991 /* Note: Values 0-28 are reserved for future use.
992 * Value 29, 30, 32 are not supported on XL710 and X710.
993 */
994 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
995 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
996 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
997 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
998 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
999 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1000 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1001 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1002 /* Note: Values 37-38 are reserved for future use.
1003 * Value 39, 40, 42 are not supported on XL710 and X710.
1004 */
1005 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1006 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1007 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1008 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1009 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1010 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1011 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1012 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1013 /* Note: Value 47 is reserved for future use */
1014 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1015 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1016 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1017 /* Note: Values 51-62 are reserved for future use */
1018 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1019 };
1020
1021 enum i40e_filter_program_desc_dest {
1022 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1023 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1024 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1025 };
1026
1027 enum i40e_filter_program_desc_fd_status {
1028 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1029 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1030 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1031 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1032 };
1033
1034 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1035 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1036 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1037
1038 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1039 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1040 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1041
1042 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1043 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1044
1045 enum i40e_filter_program_desc_pcmd {
1046 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1047 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1048 };
1049
1050 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1051 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1052
1053 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1054 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1055
1056 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1057 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1058 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1059 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1060
1061 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1062 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1063 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1064
1065 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1066 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1067 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1068
1069 enum i40e_filter_type {
1070 I40E_FLOW_DIRECTOR_FLTR = 0,
1071 I40E_PE_QUAD_HASH_FLTR = 1,
1072 I40E_ETHERTYPE_FLTR,
1073 I40E_FCOE_CTX_FLTR,
1074 I40E_MAC_VLAN_FLTR,
1075 I40E_HASH_FLTR
1076 };
1077
1078 struct i40e_vsi_context {
1079 u16 seid;
1080 u16 uplink_seid;
1081 u16 vsi_number;
1082 u16 vsis_allocated;
1083 u16 vsis_unallocated;
1084 u16 flags;
1085 u8 pf_num;
1086 u8 vf_num;
1087 u8 connection_type;
1088 struct i40e_aqc_vsi_properties_data info;
1089 };
1090
1091 struct i40e_veb_context {
1092 u16 seid;
1093 u16 uplink_seid;
1094 u16 veb_number;
1095 u16 vebs_allocated;
1096 u16 vebs_unallocated;
1097 u16 flags;
1098 struct i40e_aqc_get_veb_parameters_completion info;
1099 };
1100
1101 /* Statistics collected by each port, VSI, VEB, and S-channel */
1102 struct i40e_eth_stats {
1103 u64 rx_bytes; /* gorc */
1104 u64 rx_unicast; /* uprc */
1105 u64 rx_multicast; /* mprc */
1106 u64 rx_broadcast; /* bprc */
1107 u64 rx_discards; /* rdpc */
1108 u64 rx_unknown_protocol; /* rupp */
1109 u64 tx_bytes; /* gotc */
1110 u64 tx_unicast; /* uptc */
1111 u64 tx_multicast; /* mptc */
1112 u64 tx_broadcast; /* bptc */
1113 u64 tx_discards; /* tdpc */
1114 u64 tx_errors; /* tepc */
1115 };
1116
1117 /* Statistics collected per VEB per TC */
1118 struct i40e_veb_tc_stats {
1119 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1120 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1121 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1122 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1123 };
1124
1125 #ifdef I40E_FCOE
1126 /* Statistics collected per function for FCoE */
1127 struct i40e_fcoe_stats {
1128 u64 rx_fcoe_packets; /* fcoeprc */
1129 u64 rx_fcoe_dwords; /* focedwrc */
1130 u64 rx_fcoe_dropped; /* fcoerpdc */
1131 u64 tx_fcoe_packets; /* fcoeptc */
1132 u64 tx_fcoe_dwords; /* focedwtc */
1133 u64 fcoe_bad_fccrc; /* fcoecrc */
1134 u64 fcoe_last_error; /* fcoelast */
1135 u64 fcoe_ddp_count; /* fcoeddpc */
1136 };
1137
1138 /* offset to per function FCoE statistics block */
1139 #define I40E_FCOE_VF_STAT_OFFSET 0
1140 #define I40E_FCOE_PF_STAT_OFFSET 128
1141 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1142
1143 #endif
1144 /* Statistics collected by the MAC */
1145 struct i40e_hw_port_stats {
1146 /* eth stats collected by the port */
1147 struct i40e_eth_stats eth;
1148
1149 /* additional port specific stats */
1150 u64 tx_dropped_link_down; /* tdold */
1151 u64 crc_errors; /* crcerrs */
1152 u64 illegal_bytes; /* illerrc */
1153 u64 error_bytes; /* errbc */
1154 u64 mac_local_faults; /* mlfc */
1155 u64 mac_remote_faults; /* mrfc */
1156 u64 rx_length_errors; /* rlec */
1157 u64 link_xon_rx; /* lxonrxc */
1158 u64 link_xoff_rx; /* lxoffrxc */
1159 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1160 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1161 u64 link_xon_tx; /* lxontxc */
1162 u64 link_xoff_tx; /* lxofftxc */
1163 u64 priority_xon_tx[8]; /* pxontxc[8] */
1164 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1165 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1166 u64 rx_size_64; /* prc64 */
1167 u64 rx_size_127; /* prc127 */
1168 u64 rx_size_255; /* prc255 */
1169 u64 rx_size_511; /* prc511 */
1170 u64 rx_size_1023; /* prc1023 */
1171 u64 rx_size_1522; /* prc1522 */
1172 u64 rx_size_big; /* prc9522 */
1173 u64 rx_undersize; /* ruc */
1174 u64 rx_fragments; /* rfc */
1175 u64 rx_oversize; /* roc */
1176 u64 rx_jabber; /* rjc */
1177 u64 tx_size_64; /* ptc64 */
1178 u64 tx_size_127; /* ptc127 */
1179 u64 tx_size_255; /* ptc255 */
1180 u64 tx_size_511; /* ptc511 */
1181 u64 tx_size_1023; /* ptc1023 */
1182 u64 tx_size_1522; /* ptc1522 */
1183 u64 tx_size_big; /* ptc9522 */
1184 u64 mac_short_packet_dropped; /* mspdc */
1185 u64 checksum_error; /* xec */
1186 /* flow director stats */
1187 u64 fd_atr_match;
1188 u64 fd_sb_match;
1189 u64 fd_atr_tunnel_match;
1190 u32 fd_atr_status;
1191 u32 fd_sb_status;
1192 /* EEE LPI */
1193 u32 tx_lpi_status;
1194 u32 rx_lpi_status;
1195 u64 tx_lpi_count; /* etlpic */
1196 u64 rx_lpi_count; /* erlpic */
1197 };
1198
1199 /* Checksum and Shadow RAM pointers */
1200 #define I40E_SR_NVM_CONTROL_WORD 0x00
1201 #define I40E_SR_EMP_MODULE_PTR 0x0F
1202 #define I40E_SR_PBA_FLAGS 0x15
1203 #define I40E_SR_PBA_BLOCK_PTR 0x16
1204 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1205 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1206 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1207 #define I40E_SR_NVM_EETRACK_LO 0x2D
1208 #define I40E_SR_NVM_EETRACK_HI 0x2E
1209 #define I40E_SR_VPD_PTR 0x2F
1210 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1211 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1212
1213 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1214 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1215 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1216 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1217 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1218
1219 /* Shadow RAM related */
1220 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1221 #define I40E_SR_WORDS_IN_1KB 512
1222 /* Checksum should be calculated such that after adding all the words,
1223 * including the checksum word itself, the sum should be 0xBABA.
1224 */
1225 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1226
1227 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1228
1229 #ifdef I40E_FCOE
1230 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1231
1232 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1233 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1234 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1235 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1236 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1237 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1238 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1239 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1240 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1241 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1242 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1243 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1244 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1245 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1246 };
1247
1248 /* FCoE DDP Context descriptor */
1249 struct i40e_fcoe_ddp_context_desc {
1250 __le64 rsvd;
1251 __le64 type_cmd_foff_lsize;
1252 };
1253
1254 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1255 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1256 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1257
1258 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1259 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1260 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1261
1262 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1263 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1264 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1265 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1266 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1267 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1268 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1269 };
1270
1271 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1272 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1273 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1274
1275 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1276 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1277 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1278
1279 /* FCoE DDP/DWO Queue Context descriptor */
1280 struct i40e_fcoe_queue_context_desc {
1281 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1282 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1283 };
1284
1285 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1286 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1287 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1288
1289 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1290 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1291 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1292
1293 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1294 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1295 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1296
1297 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1298 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1299 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1300
1301 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1302 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1303 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1304 };
1305
1306 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1307 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1308 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1309
1310 /* FCoE DDP/DWO Filter Context descriptor */
1311 struct i40e_fcoe_filter_context_desc {
1312 __le32 param;
1313 __le16 seqn;
1314
1315 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1316 __le16 rsvd_dmaindx;
1317
1318 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1319 __le64 flags_rsvd_lanq;
1320 };
1321
1322 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1323 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1324 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1325
1326 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1327 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1328 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1329 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1330 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1331 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1332 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1333 };
1334
1335 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1336 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1337 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1338
1339 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1340 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1341 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1342
1343 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1344 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1345 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1346
1347 #endif /* I40E_FCOE */
1348 enum i40e_switch_element_types {
1349 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1350 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1351 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1352 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1353 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1354 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1355 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1356 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1357 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1358 };
1359
1360 /* Supported EtherType filters */
1361 enum i40e_ether_type_index {
1362 I40E_ETHER_TYPE_1588 = 0,
1363 I40E_ETHER_TYPE_FIP = 1,
1364 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1365 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1366 I40E_ETHER_TYPE_LLDP = 4,
1367 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1368 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1369 I40E_ETHER_TYPE_QCN_CNM = 7,
1370 I40E_ETHER_TYPE_8021X = 8,
1371 I40E_ETHER_TYPE_ARP = 9,
1372 I40E_ETHER_TYPE_RSV1 = 10,
1373 I40E_ETHER_TYPE_RSV2 = 11,
1374 };
1375
1376 /* Filter context base size is 1K */
1377 #define I40E_HASH_FILTER_BASE_SIZE 1024
1378 /* Supported Hash filter values */
1379 enum i40e_hash_filter_size {
1380 I40E_HASH_FILTER_SIZE_1K = 0,
1381 I40E_HASH_FILTER_SIZE_2K = 1,
1382 I40E_HASH_FILTER_SIZE_4K = 2,
1383 I40E_HASH_FILTER_SIZE_8K = 3,
1384 I40E_HASH_FILTER_SIZE_16K = 4,
1385 I40E_HASH_FILTER_SIZE_32K = 5,
1386 I40E_HASH_FILTER_SIZE_64K = 6,
1387 I40E_HASH_FILTER_SIZE_128K = 7,
1388 I40E_HASH_FILTER_SIZE_256K = 8,
1389 I40E_HASH_FILTER_SIZE_512K = 9,
1390 I40E_HASH_FILTER_SIZE_1M = 10,
1391 };
1392
1393 /* DMA context base size is 0.5K */
1394 #define I40E_DMA_CNTX_BASE_SIZE 512
1395 /* Supported DMA context values */
1396 enum i40e_dma_cntx_size {
1397 I40E_DMA_CNTX_SIZE_512 = 0,
1398 I40E_DMA_CNTX_SIZE_1K = 1,
1399 I40E_DMA_CNTX_SIZE_2K = 2,
1400 I40E_DMA_CNTX_SIZE_4K = 3,
1401 I40E_DMA_CNTX_SIZE_8K = 4,
1402 I40E_DMA_CNTX_SIZE_16K = 5,
1403 I40E_DMA_CNTX_SIZE_32K = 6,
1404 I40E_DMA_CNTX_SIZE_64K = 7,
1405 I40E_DMA_CNTX_SIZE_128K = 8,
1406 I40E_DMA_CNTX_SIZE_256K = 9,
1407 };
1408
1409 /* Supported Hash look up table (LUT) sizes */
1410 enum i40e_hash_lut_size {
1411 I40E_HASH_LUT_SIZE_128 = 0,
1412 I40E_HASH_LUT_SIZE_512 = 1,
1413 };
1414
1415 /* Structure to hold a per PF filter control settings */
1416 struct i40e_filter_control_settings {
1417 /* number of PE Quad Hash filter buckets */
1418 enum i40e_hash_filter_size pe_filt_num;
1419 /* number of PE Quad Hash contexts */
1420 enum i40e_dma_cntx_size pe_cntx_num;
1421 /* number of FCoE filter buckets */
1422 enum i40e_hash_filter_size fcoe_filt_num;
1423 /* number of FCoE DDP contexts */
1424 enum i40e_dma_cntx_size fcoe_cntx_num;
1425 /* size of the Hash LUT */
1426 enum i40e_hash_lut_size hash_lut_size;
1427 /* enable FDIR filters for PF and its VFs */
1428 bool enable_fdir;
1429 /* enable Ethertype filters for PF and its VFs */
1430 bool enable_ethtype;
1431 /* enable MAC/VLAN filters for PF and its VFs */
1432 bool enable_macvlan;
1433 };
1434
1435 /* Structure to hold device level control filter counts */
1436 struct i40e_control_filter_stats {
1437 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1438 u16 etype_used; /* Used perfect EtherType filters */
1439 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1440 u16 etype_free; /* Un-used perfect EtherType filters */
1441 };
1442
1443 enum i40e_reset_type {
1444 I40E_RESET_POR = 0,
1445 I40E_RESET_CORER = 1,
1446 I40E_RESET_GLOBR = 2,
1447 I40E_RESET_EMPR = 3,
1448 };
1449
1450 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1451 #define I40E_NVM_LLDP_CFG_PTR 0xD
1452 struct i40e_lldp_variables {
1453 u16 length;
1454 u16 adminstatus;
1455 u16 msgfasttx;
1456 u16 msgtxinterval;
1457 u16 txparams;
1458 u16 timers;
1459 u16 crc8;
1460 };
1461
1462 /* Offsets into Alternate Ram */
1463 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1464 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1465 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1466 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1467 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1468 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1469
1470 /* Alternate Ram Bandwidth Masks */
1471 #define I40E_ALT_BW_VALUE_MASK 0xFF
1472 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1473 #define I40E_ALT_BW_VALID_MASK 0x80000000
1474
1475 /* RSS Hash Table Size */
1476 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1477 #endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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