1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_status.h"
28 #include "i40e_type.h"
29 #include "i40e_register.h"
30 #include "i40e_adminq.h"
31 #include "i40e_prototype.h"
34 * i40e_is_nvm_update_op - return true if this is an NVM update operation
35 * @desc: API request descriptor
37 static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc
*desc
)
39 return (desc
->opcode
== i40e_aqc_opc_nvm_erase
) ||
40 (desc
->opcode
== i40e_aqc_opc_nvm_update
);
44 * i40e_adminq_init_regs - Initialize AdminQ registers
45 * @hw: pointer to the hardware structure
47 * This assumes the alloc_asq and alloc_arq functions have already been called
49 static void i40e_adminq_init_regs(struct i40e_hw
*hw
)
51 /* set head and tail registers in our local struct */
53 hw
->aq
.asq
.tail
= I40E_VF_ATQT1
;
54 hw
->aq
.asq
.head
= I40E_VF_ATQH1
;
55 hw
->aq
.asq
.len
= I40E_VF_ATQLEN1
;
56 hw
->aq
.asq
.bal
= I40E_VF_ATQBAL1
;
57 hw
->aq
.asq
.bah
= I40E_VF_ATQBAH1
;
58 hw
->aq
.arq
.tail
= I40E_VF_ARQT1
;
59 hw
->aq
.arq
.head
= I40E_VF_ARQH1
;
60 hw
->aq
.arq
.len
= I40E_VF_ARQLEN1
;
61 hw
->aq
.arq
.bal
= I40E_VF_ARQBAL1
;
62 hw
->aq
.arq
.bah
= I40E_VF_ARQBAH1
;
67 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
68 * @hw: pointer to the hardware structure
70 static i40e_status
i40e_alloc_adminq_asq_ring(struct i40e_hw
*hw
)
74 ret_code
= i40e_allocate_dma_mem(hw
, &hw
->aq
.asq
.desc_buf
,
76 (hw
->aq
.num_asq_entries
*
77 sizeof(struct i40e_aq_desc
)),
78 I40E_ADMINQ_DESC_ALIGNMENT
);
82 ret_code
= i40e_allocate_virt_mem(hw
, &hw
->aq
.asq
.cmd_buf
,
83 (hw
->aq
.num_asq_entries
*
84 sizeof(struct i40e_asq_cmd_details
)));
86 i40e_free_dma_mem(hw
, &hw
->aq
.asq
.desc_buf
);
94 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
95 * @hw: pointer to the hardware structure
97 static i40e_status
i40e_alloc_adminq_arq_ring(struct i40e_hw
*hw
)
101 ret_code
= i40e_allocate_dma_mem(hw
, &hw
->aq
.arq
.desc_buf
,
103 (hw
->aq
.num_arq_entries
*
104 sizeof(struct i40e_aq_desc
)),
105 I40E_ADMINQ_DESC_ALIGNMENT
);
111 * i40e_free_adminq_asq - Free Admin Queue send rings
112 * @hw: pointer to the hardware structure
114 * This assumes the posted send buffers have already been cleaned
117 static void i40e_free_adminq_asq(struct i40e_hw
*hw
)
119 i40e_free_dma_mem(hw
, &hw
->aq
.asq
.desc_buf
);
123 * i40e_free_adminq_arq - Free Admin Queue receive rings
124 * @hw: pointer to the hardware structure
126 * This assumes the posted receive buffers have already been cleaned
129 static void i40e_free_adminq_arq(struct i40e_hw
*hw
)
131 i40e_free_dma_mem(hw
, &hw
->aq
.arq
.desc_buf
);
135 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
136 * @hw: pointer to the hardware structure
138 static i40e_status
i40e_alloc_arq_bufs(struct i40e_hw
*hw
)
140 i40e_status ret_code
;
141 struct i40e_aq_desc
*desc
;
142 struct i40e_dma_mem
*bi
;
145 /* We'll be allocating the buffer info memory first, then we can
146 * allocate the mapped buffers for the event processing
149 /* buffer_info structures do not need alignment */
150 ret_code
= i40e_allocate_virt_mem(hw
, &hw
->aq
.arq
.dma_head
,
151 (hw
->aq
.num_arq_entries
* sizeof(struct i40e_dma_mem
)));
154 hw
->aq
.arq
.r
.arq_bi
= (struct i40e_dma_mem
*)hw
->aq
.arq
.dma_head
.va
;
156 /* allocate the mapped buffers */
157 for (i
= 0; i
< hw
->aq
.num_arq_entries
; i
++) {
158 bi
= &hw
->aq
.arq
.r
.arq_bi
[i
];
159 ret_code
= i40e_allocate_dma_mem(hw
, bi
,
162 I40E_ADMINQ_DESC_ALIGNMENT
);
164 goto unwind_alloc_arq_bufs
;
166 /* now configure the descriptors for use */
167 desc
= I40E_ADMINQ_DESC(hw
->aq
.arq
, i
);
169 desc
->flags
= cpu_to_le16(I40E_AQ_FLAG_BUF
);
170 if (hw
->aq
.arq_buf_size
> I40E_AQ_LARGE_BUF
)
171 desc
->flags
|= cpu_to_le16(I40E_AQ_FLAG_LB
);
173 /* This is in accordance with Admin queue design, there is no
174 * register for buffer size configuration
176 desc
->datalen
= cpu_to_le16((u16
)bi
->size
);
178 desc
->cookie_high
= 0;
179 desc
->cookie_low
= 0;
180 desc
->params
.external
.addr_high
=
181 cpu_to_le32(upper_32_bits(bi
->pa
));
182 desc
->params
.external
.addr_low
=
183 cpu_to_le32(lower_32_bits(bi
->pa
));
184 desc
->params
.external
.param0
= 0;
185 desc
->params
.external
.param1
= 0;
191 unwind_alloc_arq_bufs
:
192 /* don't try to free the one that failed... */
195 i40e_free_dma_mem(hw
, &hw
->aq
.arq
.r
.arq_bi
[i
]);
196 i40e_free_virt_mem(hw
, &hw
->aq
.arq
.dma_head
);
202 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
203 * @hw: pointer to the hardware structure
205 static i40e_status
i40e_alloc_asq_bufs(struct i40e_hw
*hw
)
207 i40e_status ret_code
;
208 struct i40e_dma_mem
*bi
;
211 /* No mapped memory needed yet, just the buffer info structures */
212 ret_code
= i40e_allocate_virt_mem(hw
, &hw
->aq
.asq
.dma_head
,
213 (hw
->aq
.num_asq_entries
* sizeof(struct i40e_dma_mem
)));
216 hw
->aq
.asq
.r
.asq_bi
= (struct i40e_dma_mem
*)hw
->aq
.asq
.dma_head
.va
;
218 /* allocate the mapped buffers */
219 for (i
= 0; i
< hw
->aq
.num_asq_entries
; i
++) {
220 bi
= &hw
->aq
.asq
.r
.asq_bi
[i
];
221 ret_code
= i40e_allocate_dma_mem(hw
, bi
,
224 I40E_ADMINQ_DESC_ALIGNMENT
);
226 goto unwind_alloc_asq_bufs
;
231 unwind_alloc_asq_bufs
:
232 /* don't try to free the one that failed... */
235 i40e_free_dma_mem(hw
, &hw
->aq
.asq
.r
.asq_bi
[i
]);
236 i40e_free_virt_mem(hw
, &hw
->aq
.asq
.dma_head
);
242 * i40e_free_arq_bufs - Free receive queue buffer info elements
243 * @hw: pointer to the hardware structure
245 static void i40e_free_arq_bufs(struct i40e_hw
*hw
)
249 /* free descriptors */
250 for (i
= 0; i
< hw
->aq
.num_arq_entries
; i
++)
251 i40e_free_dma_mem(hw
, &hw
->aq
.arq
.r
.arq_bi
[i
]);
253 /* free the descriptor memory */
254 i40e_free_dma_mem(hw
, &hw
->aq
.arq
.desc_buf
);
256 /* free the dma header */
257 i40e_free_virt_mem(hw
, &hw
->aq
.arq
.dma_head
);
261 * i40e_free_asq_bufs - Free send queue buffer info elements
262 * @hw: pointer to the hardware structure
264 static void i40e_free_asq_bufs(struct i40e_hw
*hw
)
268 /* only unmap if the address is non-NULL */
269 for (i
= 0; i
< hw
->aq
.num_asq_entries
; i
++)
270 if (hw
->aq
.asq
.r
.asq_bi
[i
].pa
)
271 i40e_free_dma_mem(hw
, &hw
->aq
.asq
.r
.asq_bi
[i
]);
273 /* free the buffer info list */
274 i40e_free_virt_mem(hw
, &hw
->aq
.asq
.cmd_buf
);
276 /* free the descriptor memory */
277 i40e_free_dma_mem(hw
, &hw
->aq
.asq
.desc_buf
);
279 /* free the dma header */
280 i40e_free_virt_mem(hw
, &hw
->aq
.asq
.dma_head
);
284 * i40e_config_asq_regs - configure ASQ registers
285 * @hw: pointer to the hardware structure
287 * Configure base address and length registers for the transmit queue
289 static i40e_status
i40e_config_asq_regs(struct i40e_hw
*hw
)
291 i40e_status ret_code
= 0;
294 /* Clear Head and Tail */
295 wr32(hw
, hw
->aq
.asq
.head
, 0);
296 wr32(hw
, hw
->aq
.asq
.tail
, 0);
298 /* set starting point */
299 wr32(hw
, hw
->aq
.asq
.len
, (hw
->aq
.num_asq_entries
|
300 I40E_VF_ATQLEN1_ATQENABLE_MASK
));
301 wr32(hw
, hw
->aq
.asq
.bal
, lower_32_bits(hw
->aq
.asq
.desc_buf
.pa
));
302 wr32(hw
, hw
->aq
.asq
.bah
, upper_32_bits(hw
->aq
.asq
.desc_buf
.pa
));
304 /* Check one register to verify that config was applied */
305 reg
= rd32(hw
, hw
->aq
.asq
.bal
);
306 if (reg
!= lower_32_bits(hw
->aq
.asq
.desc_buf
.pa
))
307 ret_code
= I40E_ERR_ADMIN_QUEUE_ERROR
;
313 * i40e_config_arq_regs - ARQ register configuration
314 * @hw: pointer to the hardware structure
316 * Configure base address and length registers for the receive (event queue)
318 static i40e_status
i40e_config_arq_regs(struct i40e_hw
*hw
)
320 i40e_status ret_code
= 0;
323 /* Clear Head and Tail */
324 wr32(hw
, hw
->aq
.arq
.head
, 0);
325 wr32(hw
, hw
->aq
.arq
.tail
, 0);
327 /* set starting point */
328 wr32(hw
, hw
->aq
.arq
.len
, (hw
->aq
.num_arq_entries
|
329 I40E_VF_ARQLEN1_ARQENABLE_MASK
));
330 wr32(hw
, hw
->aq
.arq
.bal
, lower_32_bits(hw
->aq
.arq
.desc_buf
.pa
));
331 wr32(hw
, hw
->aq
.arq
.bah
, upper_32_bits(hw
->aq
.arq
.desc_buf
.pa
));
333 /* Update tail in the HW to post pre-allocated buffers */
334 wr32(hw
, hw
->aq
.arq
.tail
, hw
->aq
.num_arq_entries
- 1);
336 /* Check one register to verify that config was applied */
337 reg
= rd32(hw
, hw
->aq
.arq
.bal
);
338 if (reg
!= lower_32_bits(hw
->aq
.arq
.desc_buf
.pa
))
339 ret_code
= I40E_ERR_ADMIN_QUEUE_ERROR
;
345 * i40e_init_asq - main initialization routine for ASQ
346 * @hw: pointer to the hardware structure
348 * This is the main initialization routine for the Admin Send Queue
349 * Prior to calling this function, drivers *MUST* set the following fields
350 * in the hw->aq structure:
351 * - hw->aq.num_asq_entries
352 * - hw->aq.arq_buf_size
354 * Do *NOT* hold the lock when calling this as the memory allocation routines
355 * called are not going to be atomic context safe
357 static i40e_status
i40e_init_asq(struct i40e_hw
*hw
)
359 i40e_status ret_code
= 0;
361 if (hw
->aq
.asq
.count
> 0) {
362 /* queue already initialized */
363 ret_code
= I40E_ERR_NOT_READY
;
364 goto init_adminq_exit
;
367 /* verify input for valid configuration */
368 if ((hw
->aq
.num_asq_entries
== 0) ||
369 (hw
->aq
.asq_buf_size
== 0)) {
370 ret_code
= I40E_ERR_CONFIG
;
371 goto init_adminq_exit
;
374 hw
->aq
.asq
.next_to_use
= 0;
375 hw
->aq
.asq
.next_to_clean
= 0;
376 hw
->aq
.asq
.count
= hw
->aq
.num_asq_entries
;
378 /* allocate the ring memory */
379 ret_code
= i40e_alloc_adminq_asq_ring(hw
);
381 goto init_adminq_exit
;
383 /* allocate buffers in the rings */
384 ret_code
= i40e_alloc_asq_bufs(hw
);
386 goto init_adminq_free_rings
;
388 /* initialize base registers */
389 ret_code
= i40e_config_asq_regs(hw
);
391 goto init_adminq_free_rings
;
394 goto init_adminq_exit
;
396 init_adminq_free_rings
:
397 i40e_free_adminq_asq(hw
);
404 * i40e_init_arq - initialize ARQ
405 * @hw: pointer to the hardware structure
407 * The main initialization routine for the Admin Receive (Event) Queue.
408 * Prior to calling this function, drivers *MUST* set the following fields
409 * in the hw->aq structure:
410 * - hw->aq.num_asq_entries
411 * - hw->aq.arq_buf_size
413 * Do *NOT* hold the lock when calling this as the memory allocation routines
414 * called are not going to be atomic context safe
416 static i40e_status
i40e_init_arq(struct i40e_hw
*hw
)
418 i40e_status ret_code
= 0;
420 if (hw
->aq
.arq
.count
> 0) {
421 /* queue already initialized */
422 ret_code
= I40E_ERR_NOT_READY
;
423 goto init_adminq_exit
;
426 /* verify input for valid configuration */
427 if ((hw
->aq
.num_arq_entries
== 0) ||
428 (hw
->aq
.arq_buf_size
== 0)) {
429 ret_code
= I40E_ERR_CONFIG
;
430 goto init_adminq_exit
;
433 hw
->aq
.arq
.next_to_use
= 0;
434 hw
->aq
.arq
.next_to_clean
= 0;
435 hw
->aq
.arq
.count
= hw
->aq
.num_arq_entries
;
437 /* allocate the ring memory */
438 ret_code
= i40e_alloc_adminq_arq_ring(hw
);
440 goto init_adminq_exit
;
442 /* allocate buffers in the rings */
443 ret_code
= i40e_alloc_arq_bufs(hw
);
445 goto init_adminq_free_rings
;
447 /* initialize base registers */
448 ret_code
= i40e_config_arq_regs(hw
);
450 goto init_adminq_free_rings
;
453 goto init_adminq_exit
;
455 init_adminq_free_rings
:
456 i40e_free_adminq_arq(hw
);
463 * i40e_shutdown_asq - shutdown the ASQ
464 * @hw: pointer to the hardware structure
466 * The main shutdown routine for the Admin Send Queue
468 static i40e_status
i40e_shutdown_asq(struct i40e_hw
*hw
)
470 i40e_status ret_code
= 0;
472 if (hw
->aq
.asq
.count
== 0)
473 return I40E_ERR_NOT_READY
;
475 /* Stop firmware AdminQ processing */
476 wr32(hw
, hw
->aq
.asq
.head
, 0);
477 wr32(hw
, hw
->aq
.asq
.tail
, 0);
478 wr32(hw
, hw
->aq
.asq
.len
, 0);
479 wr32(hw
, hw
->aq
.asq
.bal
, 0);
480 wr32(hw
, hw
->aq
.asq
.bah
, 0);
482 /* make sure lock is available */
483 mutex_lock(&hw
->aq
.asq_mutex
);
485 hw
->aq
.asq
.count
= 0; /* to indicate uninitialized queue */
487 /* free ring buffers */
488 i40e_free_asq_bufs(hw
);
490 mutex_unlock(&hw
->aq
.asq_mutex
);
496 * i40e_shutdown_arq - shutdown ARQ
497 * @hw: pointer to the hardware structure
499 * The main shutdown routine for the Admin Receive Queue
501 static i40e_status
i40e_shutdown_arq(struct i40e_hw
*hw
)
503 i40e_status ret_code
= 0;
505 if (hw
->aq
.arq
.count
== 0)
506 return I40E_ERR_NOT_READY
;
508 /* Stop firmware AdminQ processing */
509 wr32(hw
, hw
->aq
.arq
.head
, 0);
510 wr32(hw
, hw
->aq
.arq
.tail
, 0);
511 wr32(hw
, hw
->aq
.arq
.len
, 0);
512 wr32(hw
, hw
->aq
.arq
.bal
, 0);
513 wr32(hw
, hw
->aq
.arq
.bah
, 0);
515 /* make sure lock is available */
516 mutex_lock(&hw
->aq
.arq_mutex
);
518 hw
->aq
.arq
.count
= 0; /* to indicate uninitialized queue */
520 /* free ring buffers */
521 i40e_free_arq_bufs(hw
);
523 mutex_unlock(&hw
->aq
.arq_mutex
);
529 * i40evf_init_adminq - main initialization routine for Admin Queue
530 * @hw: pointer to the hardware structure
532 * Prior to calling this function, drivers *MUST* set the following fields
533 * in the hw->aq structure:
534 * - hw->aq.num_asq_entries
535 * - hw->aq.num_arq_entries
536 * - hw->aq.arq_buf_size
537 * - hw->aq.asq_buf_size
539 i40e_status
i40evf_init_adminq(struct i40e_hw
*hw
)
541 i40e_status ret_code
;
543 /* verify input for valid configuration */
544 if ((hw
->aq
.num_arq_entries
== 0) ||
545 (hw
->aq
.num_asq_entries
== 0) ||
546 (hw
->aq
.arq_buf_size
== 0) ||
547 (hw
->aq
.asq_buf_size
== 0)) {
548 ret_code
= I40E_ERR_CONFIG
;
549 goto init_adminq_exit
;
552 /* initialize locks */
553 mutex_init(&hw
->aq
.asq_mutex
);
554 mutex_init(&hw
->aq
.arq_mutex
);
556 /* Set up register offsets */
557 i40e_adminq_init_regs(hw
);
559 /* setup ASQ command write back timeout */
560 hw
->aq
.asq_cmd_timeout
= I40E_ASQ_CMD_TIMEOUT
;
562 /* allocate the ASQ */
563 ret_code
= i40e_init_asq(hw
);
565 goto init_adminq_destroy_locks
;
567 /* allocate the ARQ */
568 ret_code
= i40e_init_arq(hw
);
570 goto init_adminq_free_asq
;
573 goto init_adminq_exit
;
575 init_adminq_free_asq
:
576 i40e_shutdown_asq(hw
);
577 init_adminq_destroy_locks
:
584 * i40evf_shutdown_adminq - shutdown routine for the Admin Queue
585 * @hw: pointer to the hardware structure
587 i40e_status
i40evf_shutdown_adminq(struct i40e_hw
*hw
)
589 i40e_status ret_code
= 0;
591 if (i40evf_check_asq_alive(hw
))
592 i40evf_aq_queue_shutdown(hw
, true);
594 i40e_shutdown_asq(hw
);
595 i40e_shutdown_arq(hw
);
597 /* destroy the locks */
603 * i40e_clean_asq - cleans Admin send queue
604 * @hw: pointer to the hardware structure
606 * returns the number of free desc
608 static u16
i40e_clean_asq(struct i40e_hw
*hw
)
610 struct i40e_adminq_ring
*asq
= &(hw
->aq
.asq
);
611 struct i40e_asq_cmd_details
*details
;
612 u16 ntc
= asq
->next_to_clean
;
613 struct i40e_aq_desc desc_cb
;
614 struct i40e_aq_desc
*desc
;
616 desc
= I40E_ADMINQ_DESC(*asq
, ntc
);
617 details
= I40E_ADMINQ_DETAILS(*asq
, ntc
);
618 while (rd32(hw
, hw
->aq
.asq
.head
) != ntc
) {
619 i40e_debug(hw
, I40E_DEBUG_AQ_MESSAGE
,
620 "%s: ntc %d head %d.\n", __func__
, ntc
,
621 rd32(hw
, hw
->aq
.asq
.head
));
623 if (details
->callback
) {
624 I40E_ADMINQ_CALLBACK cb_func
=
625 (I40E_ADMINQ_CALLBACK
)details
->callback
;
627 cb_func(hw
, &desc_cb
);
629 memset((void *)desc
, 0, sizeof(struct i40e_aq_desc
));
630 memset((void *)details
, 0,
631 sizeof(struct i40e_asq_cmd_details
));
633 if (ntc
== asq
->count
)
635 desc
= I40E_ADMINQ_DESC(*asq
, ntc
);
636 details
= I40E_ADMINQ_DETAILS(*asq
, ntc
);
639 asq
->next_to_clean
= ntc
;
641 return I40E_DESC_UNUSED(asq
);
645 * i40evf_asq_done - check if FW has processed the Admin Send Queue
646 * @hw: pointer to the hw struct
648 * Returns true if the firmware has processed all descriptors on the
649 * admin send queue. Returns false if there are still requests pending.
651 bool i40evf_asq_done(struct i40e_hw
*hw
)
653 /* AQ designers suggest use of head for better
654 * timing reliability than DD bit
656 return rd32(hw
, hw
->aq
.asq
.head
) == hw
->aq
.asq
.next_to_use
;
661 * i40evf_asq_send_command - send command to Admin Queue
662 * @hw: pointer to the hw struct
663 * @desc: prefilled descriptor describing the command (non DMA mem)
664 * @buff: buffer to use for indirect commands
665 * @buff_size: size of buffer for indirect commands
666 * @cmd_details: pointer to command details structure
668 * This is the main send command driver routine for the Admin Queue send
669 * queue. It runs the queue, cleans the queue, etc
671 i40e_status
i40evf_asq_send_command(struct i40e_hw
*hw
,
672 struct i40e_aq_desc
*desc
,
673 void *buff
, /* can be NULL */
675 struct i40e_asq_cmd_details
*cmd_details
)
677 i40e_status status
= 0;
678 struct i40e_dma_mem
*dma_buff
= NULL
;
679 struct i40e_asq_cmd_details
*details
;
680 struct i40e_aq_desc
*desc_on_ring
;
681 bool cmd_completed
= false;
685 val
= rd32(hw
, hw
->aq
.asq
.head
);
686 if (val
>= hw
->aq
.num_asq_entries
) {
687 i40e_debug(hw
, I40E_DEBUG_AQ_MESSAGE
,
688 "AQTX: head overrun at %d\n", val
);
689 status
= I40E_ERR_QUEUE_EMPTY
;
690 goto asq_send_command_exit
;
693 if (hw
->aq
.asq
.count
== 0) {
694 i40e_debug(hw
, I40E_DEBUG_AQ_MESSAGE
,
695 "AQTX: Admin queue not initialized.\n");
696 status
= I40E_ERR_QUEUE_EMPTY
;
697 goto asq_send_command_exit
;
700 details
= I40E_ADMINQ_DETAILS(hw
->aq
.asq
, hw
->aq
.asq
.next_to_use
);
702 *details
= *cmd_details
;
704 /* If the cmd_details are defined copy the cookie. The
705 * cpu_to_le32 is not needed here because the data is ignored
706 * by the FW, only used by the driver
708 if (details
->cookie
) {
710 cpu_to_le32(upper_32_bits(details
->cookie
));
712 cpu_to_le32(lower_32_bits(details
->cookie
));
715 memset(details
, 0, sizeof(struct i40e_asq_cmd_details
));
718 /* clear requested flags and then set additional flags if defined */
719 desc
->flags
&= ~cpu_to_le16(details
->flags_dis
);
720 desc
->flags
|= cpu_to_le16(details
->flags_ena
);
722 mutex_lock(&hw
->aq
.asq_mutex
);
724 if (buff_size
> hw
->aq
.asq_buf_size
) {
726 I40E_DEBUG_AQ_MESSAGE
,
727 "AQTX: Invalid buffer size: %d.\n",
729 status
= I40E_ERR_INVALID_SIZE
;
730 goto asq_send_command_error
;
733 if (details
->postpone
&& !details
->async
) {
735 I40E_DEBUG_AQ_MESSAGE
,
736 "AQTX: Async flag not set along with postpone flag");
737 status
= I40E_ERR_PARAM
;
738 goto asq_send_command_error
;
741 /* call clean and check queue available function to reclaim the
742 * descriptors that were processed by FW, the function returns the
743 * number of desc available
745 /* the clean function called here could be called in a separate thread
746 * in case of asynchronous completions
748 if (i40e_clean_asq(hw
) == 0) {
750 I40E_DEBUG_AQ_MESSAGE
,
751 "AQTX: Error queue is full.\n");
752 status
= I40E_ERR_ADMIN_QUEUE_FULL
;
753 goto asq_send_command_error
;
756 /* initialize the temp desc pointer with the right desc */
757 desc_on_ring
= I40E_ADMINQ_DESC(hw
->aq
.asq
, hw
->aq
.asq
.next_to_use
);
759 /* if the desc is available copy the temp desc to the right place */
760 *desc_on_ring
= *desc
;
762 /* if buff is not NULL assume indirect command */
764 dma_buff
= &(hw
->aq
.asq
.r
.asq_bi
[hw
->aq
.asq
.next_to_use
]);
765 /* copy the user buff into the respective DMA buff */
766 memcpy(dma_buff
->va
, buff
, buff_size
);
767 desc_on_ring
->datalen
= cpu_to_le16(buff_size
);
769 /* Update the address values in the desc with the pa value
770 * for respective buffer
772 desc_on_ring
->params
.external
.addr_high
=
773 cpu_to_le32(upper_32_bits(dma_buff
->pa
));
774 desc_on_ring
->params
.external
.addr_low
=
775 cpu_to_le32(lower_32_bits(dma_buff
->pa
));
779 i40e_debug(hw
, I40E_DEBUG_AQ_MESSAGE
, "AQTX: desc and buffer:\n");
780 i40evf_debug_aq(hw
, I40E_DEBUG_AQ_COMMAND
, (void *)desc_on_ring
,
782 (hw
->aq
.asq
.next_to_use
)++;
783 if (hw
->aq
.asq
.next_to_use
== hw
->aq
.asq
.count
)
784 hw
->aq
.asq
.next_to_use
= 0;
785 if (!details
->postpone
)
786 wr32(hw
, hw
->aq
.asq
.tail
, hw
->aq
.asq
.next_to_use
);
788 /* if cmd_details are not defined or async flag is not set,
789 * we need to wait for desc write back
791 if (!details
->async
&& !details
->postpone
) {
795 /* AQ designers suggest use of head for better
796 * timing reliability than DD bit
798 if (i40evf_asq_done(hw
))
800 usleep_range(1000, 2000);
802 } while (total_delay
< hw
->aq
.asq_cmd_timeout
);
805 /* if ready, copy the desc back to temp */
806 if (i40evf_asq_done(hw
)) {
807 *desc
= *desc_on_ring
;
809 memcpy(buff
, dma_buff
->va
, buff_size
);
810 retval
= le16_to_cpu(desc
->retval
);
813 I40E_DEBUG_AQ_MESSAGE
,
814 "AQTX: Command completed with error 0x%X.\n",
817 /* strip off FW internal code */
820 cmd_completed
= true;
821 if ((enum i40e_admin_queue_err
)retval
== I40E_AQ_RC_OK
)
824 status
= I40E_ERR_ADMIN_QUEUE_ERROR
;
825 hw
->aq
.asq_last_status
= (enum i40e_admin_queue_err
)retval
;
828 i40e_debug(hw
, I40E_DEBUG_AQ_MESSAGE
,
829 "AQTX: desc and buffer writeback:\n");
830 i40evf_debug_aq(hw
, I40E_DEBUG_AQ_COMMAND
, (void *)desc
, buff
,
833 /* update the error if time out occurred */
834 if ((!cmd_completed
) &&
835 (!details
->async
&& !details
->postpone
)) {
837 I40E_DEBUG_AQ_MESSAGE
,
838 "AQTX: Writeback timeout.\n");
839 status
= I40E_ERR_ADMIN_QUEUE_TIMEOUT
;
842 asq_send_command_error
:
843 mutex_unlock(&hw
->aq
.asq_mutex
);
844 asq_send_command_exit
:
849 * i40evf_fill_default_direct_cmd_desc - AQ descriptor helper function
850 * @desc: pointer to the temp descriptor (non DMA mem)
851 * @opcode: the opcode can be used to decide which flags to turn off or on
853 * Fill the desc with default values
855 void i40evf_fill_default_direct_cmd_desc(struct i40e_aq_desc
*desc
,
858 /* zero out the desc */
859 memset((void *)desc
, 0, sizeof(struct i40e_aq_desc
));
860 desc
->opcode
= cpu_to_le16(opcode
);
861 desc
->flags
= cpu_to_le16(I40E_AQ_FLAG_SI
);
865 * i40evf_clean_arq_element
866 * @hw: pointer to the hw struct
867 * @e: event info from the receive descriptor, includes any buffers
868 * @pending: number of events that could be left to process
870 * This function cleans one Admin Receive Queue element and returns
871 * the contents through e. It can also return how many events are
872 * left to process through 'pending'
874 i40e_status
i40evf_clean_arq_element(struct i40e_hw
*hw
,
875 struct i40e_arq_event_info
*e
,
878 i40e_status ret_code
= 0;
879 u16 ntc
= hw
->aq
.arq
.next_to_clean
;
880 struct i40e_aq_desc
*desc
;
881 struct i40e_dma_mem
*bi
;
887 /* take the lock before we start messing with the ring */
888 mutex_lock(&hw
->aq
.arq_mutex
);
890 /* set next_to_use to head */
891 ntu
= (rd32(hw
, hw
->aq
.arq
.head
) & I40E_VF_ARQH1_ARQH_MASK
);
893 /* nothing to do - shouldn't need to update ring's values */
894 ret_code
= I40E_ERR_ADMIN_QUEUE_NO_WORK
;
895 goto clean_arq_element_out
;
898 /* now clean the next descriptor */
899 desc
= I40E_ADMINQ_DESC(hw
->aq
.arq
, ntc
);
902 flags
= le16_to_cpu(desc
->flags
);
903 if (flags
& I40E_AQ_FLAG_ERR
) {
904 ret_code
= I40E_ERR_ADMIN_QUEUE_ERROR
;
905 hw
->aq
.arq_last_status
=
906 (enum i40e_admin_queue_err
)le16_to_cpu(desc
->retval
);
908 I40E_DEBUG_AQ_MESSAGE
,
909 "AQRX: Event received with error 0x%X.\n",
910 hw
->aq
.arq_last_status
);
914 datalen
= le16_to_cpu(desc
->datalen
);
915 e
->msg_len
= min(datalen
, e
->buf_len
);
916 if (e
->msg_buf
!= NULL
&& (e
->msg_len
!= 0))
917 memcpy(e
->msg_buf
, hw
->aq
.arq
.r
.arq_bi
[desc_idx
].va
,
920 i40e_debug(hw
, I40E_DEBUG_AQ_MESSAGE
, "AQRX: desc and buffer:\n");
921 i40evf_debug_aq(hw
, I40E_DEBUG_AQ_COMMAND
, (void *)desc
, e
->msg_buf
,
922 hw
->aq
.arq_buf_size
);
924 /* Restore the original datalen and buffer address in the desc,
925 * FW updates datalen to indicate the event message
928 bi
= &hw
->aq
.arq
.r
.arq_bi
[ntc
];
929 memset((void *)desc
, 0, sizeof(struct i40e_aq_desc
));
931 desc
->flags
= cpu_to_le16(I40E_AQ_FLAG_BUF
);
932 if (hw
->aq
.arq_buf_size
> I40E_AQ_LARGE_BUF
)
933 desc
->flags
|= cpu_to_le16(I40E_AQ_FLAG_LB
);
934 desc
->datalen
= cpu_to_le16((u16
)bi
->size
);
935 desc
->params
.external
.addr_high
= cpu_to_le32(upper_32_bits(bi
->pa
));
936 desc
->params
.external
.addr_low
= cpu_to_le32(lower_32_bits(bi
->pa
));
938 /* set tail = the last cleaned desc index. */
939 wr32(hw
, hw
->aq
.arq
.tail
, ntc
);
940 /* ntc is updated to tail + 1 */
942 if (ntc
== hw
->aq
.num_arq_entries
)
944 hw
->aq
.arq
.next_to_clean
= ntc
;
945 hw
->aq
.arq
.next_to_use
= ntu
;
947 clean_arq_element_out
:
948 /* Set pending if needed, unlock and return */
950 *pending
= (ntc
> ntu
? hw
->aq
.arq
.count
: 0) + (ntu
- ntc
);
951 mutex_unlock(&hw
->aq
.arq_mutex
);
956 void i40evf_resume_aq(struct i40e_hw
*hw
)
958 /* Registers are reset after PF reset */
959 hw
->aq
.asq
.next_to_use
= 0;
960 hw
->aq
.asq
.next_to_clean
= 0;
962 i40e_config_asq_regs(hw
);
964 hw
->aq
.arq
.next_to_use
= 0;
965 hw
->aq
.arq
.next_to_clean
= 0;
967 i40e_config_arq_regs(hw
);