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Merge tag 'iommu-updates-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro...
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_adminq_cmd.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
29
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0004
38
39 struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61 };
62
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
80
81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
92
93 /* error codes */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
118 };
119
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
122 /* aq commands */
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
127
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
131
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
134
135 /* LAA */
136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
138
139 /* PXE */
140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
141
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
148
149 i40e_aqc_opc_add_vsi = 0x0210,
150 i40e_aqc_opc_update_vsi_parameters = 0x0211,
151 i40e_aqc_opc_get_vsi_parameters = 0x0212,
152
153 i40e_aqc_opc_add_pv = 0x0220,
154 i40e_aqc_opc_update_pv_parameters = 0x0221,
155 i40e_aqc_opc_get_pv_parameters = 0x0222,
156
157 i40e_aqc_opc_add_veb = 0x0230,
158 i40e_aqc_opc_update_veb_parameters = 0x0231,
159 i40e_aqc_opc_get_veb_parameters = 0x0232,
160
161 i40e_aqc_opc_delete_element = 0x0243,
162
163 i40e_aqc_opc_add_macvlan = 0x0250,
164 i40e_aqc_opc_remove_macvlan = 0x0251,
165 i40e_aqc_opc_add_vlan = 0x0252,
166 i40e_aqc_opc_remove_vlan = 0x0253,
167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
168 i40e_aqc_opc_add_tag = 0x0255,
169 i40e_aqc_opc_remove_tag = 0x0256,
170 i40e_aqc_opc_add_multicast_etag = 0x0257,
171 i40e_aqc_opc_remove_multicast_etag = 0x0258,
172 i40e_aqc_opc_update_tag = 0x0259,
173 i40e_aqc_opc_add_control_packet_filter = 0x025A,
174 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
175 i40e_aqc_opc_add_cloud_filters = 0x025C,
176 i40e_aqc_opc_remove_cloud_filters = 0x025D,
177
178 i40e_aqc_opc_add_mirror_rule = 0x0260,
179 i40e_aqc_opc_delete_mirror_rule = 0x0261,
180
181 /* DCB commands */
182 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
183 i40e_aqc_opc_dcb_updated = 0x0302,
184
185 /* TX scheduler */
186 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
187 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
188 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
189 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
190 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
191 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
192
193 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
194 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
195 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
196 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
197 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
198 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
199 i40e_aqc_opc_query_port_ets_config = 0x0419,
200 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
201 i40e_aqc_opc_suspend_port_tx = 0x041B,
202 i40e_aqc_opc_resume_port_tx = 0x041C,
203 i40e_aqc_opc_configure_partition_bw = 0x041D,
204
205 /* hmc */
206 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
207 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
208
209 /* phy commands*/
210 i40e_aqc_opc_get_phy_abilities = 0x0600,
211 i40e_aqc_opc_set_phy_config = 0x0601,
212 i40e_aqc_opc_set_mac_config = 0x0603,
213 i40e_aqc_opc_set_link_restart_an = 0x0605,
214 i40e_aqc_opc_get_link_status = 0x0607,
215 i40e_aqc_opc_set_phy_int_mask = 0x0613,
216 i40e_aqc_opc_get_local_advt_reg = 0x0614,
217 i40e_aqc_opc_set_local_advt_reg = 0x0615,
218 i40e_aqc_opc_get_partner_advt = 0x0616,
219 i40e_aqc_opc_set_lb_modes = 0x0618,
220 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
221 i40e_aqc_opc_set_phy_debug = 0x0622,
222 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
223
224 /* NVM commands */
225 i40e_aqc_opc_nvm_read = 0x0701,
226 i40e_aqc_opc_nvm_erase = 0x0702,
227 i40e_aqc_opc_nvm_update = 0x0703,
228 i40e_aqc_opc_nvm_config_read = 0x0704,
229 i40e_aqc_opc_nvm_config_write = 0x0705,
230 i40e_aqc_opc_oem_post_update = 0x0720,
231
232 /* virtualization commands */
233 i40e_aqc_opc_send_msg_to_pf = 0x0801,
234 i40e_aqc_opc_send_msg_to_vf = 0x0802,
235 i40e_aqc_opc_send_msg_to_peer = 0x0803,
236
237 /* alternate structure */
238 i40e_aqc_opc_alternate_write = 0x0900,
239 i40e_aqc_opc_alternate_write_indirect = 0x0901,
240 i40e_aqc_opc_alternate_read = 0x0902,
241 i40e_aqc_opc_alternate_read_indirect = 0x0903,
242 i40e_aqc_opc_alternate_write_done = 0x0904,
243 i40e_aqc_opc_alternate_set_mode = 0x0905,
244 i40e_aqc_opc_alternate_clear_port = 0x0906,
245
246 /* LLDP commands */
247 i40e_aqc_opc_lldp_get_mib = 0x0A00,
248 i40e_aqc_opc_lldp_update_mib = 0x0A01,
249 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
250 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
251 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
252 i40e_aqc_opc_lldp_stop = 0x0A05,
253 i40e_aqc_opc_lldp_start = 0x0A06,
254
255 /* Tunnel commands */
256 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
257 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
258 i40e_aqc_opc_set_rss_key = 0x0B02,
259 i40e_aqc_opc_set_rss_lut = 0x0B03,
260 i40e_aqc_opc_get_rss_key = 0x0B04,
261 i40e_aqc_opc_get_rss_lut = 0x0B05,
262
263 /* Async Events */
264 i40e_aqc_opc_event_lan_overflow = 0x1001,
265
266 /* OEM commands */
267 i40e_aqc_opc_oem_parameter_change = 0xFE00,
268 i40e_aqc_opc_oem_device_status_change = 0xFE01,
269 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
270 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
271
272 /* debug commands */
273 i40e_aqc_opc_debug_read_reg = 0xFF03,
274 i40e_aqc_opc_debug_write_reg = 0xFF04,
275 i40e_aqc_opc_debug_modify_reg = 0xFF07,
276 i40e_aqc_opc_debug_dump_internals = 0xFF08,
277 };
278
279 /* command structures and indirect data structures */
280
281 /* Structure naming conventions:
282 * - no suffix for direct command descriptor structures
283 * - _data for indirect sent data
284 * - _resp for indirect return data (data which is both will use _data)
285 * - _completion for direct return data
286 * - _element_ for repeated elements (may also be _data or _resp)
287 *
288 * Command structures are expected to overlay the params.raw member of the basic
289 * descriptor, and as such cannot exceed 16 bytes in length.
290 */
291
292 /* This macro is used to generate a compilation error if a structure
293 * is not exactly the correct length. It gives a divide by zero error if the
294 * structure is not of the correct size, otherwise it creates an enum that is
295 * never used.
296 */
297 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
298 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
299
300 /* This macro is used extensively to ensure that command structures are 16
301 * bytes in length as they have to map to the raw array of that size.
302 */
303 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
304
305 /* internal (0x00XX) commands */
306
307 /* Get version (direct 0x0001) */
308 struct i40e_aqc_get_version {
309 __le32 rom_ver;
310 __le32 fw_build;
311 __le16 fw_major;
312 __le16 fw_minor;
313 __le16 api_major;
314 __le16 api_minor;
315 };
316
317 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
318
319 /* Send driver version (indirect 0x0002) */
320 struct i40e_aqc_driver_version {
321 u8 driver_major_ver;
322 u8 driver_minor_ver;
323 u8 driver_build_ver;
324 u8 driver_subbuild_ver;
325 u8 reserved[4];
326 __le32 address_high;
327 __le32 address_low;
328 };
329
330 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
331
332 /* Queue Shutdown (direct 0x0003) */
333 struct i40e_aqc_queue_shutdown {
334 __le32 driver_unloading;
335 #define I40E_AQ_DRIVER_UNLOADING 0x1
336 u8 reserved[12];
337 };
338
339 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
340
341 /* Set PF context (0x0004, direct) */
342 struct i40e_aqc_set_pf_context {
343 u8 pf_id;
344 u8 reserved[15];
345 };
346
347 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
348
349 /* Request resource ownership (direct 0x0008)
350 * Release resource ownership (direct 0x0009)
351 */
352 #define I40E_AQ_RESOURCE_NVM 1
353 #define I40E_AQ_RESOURCE_SDP 2
354 #define I40E_AQ_RESOURCE_ACCESS_READ 1
355 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
356 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
357 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
358
359 struct i40e_aqc_request_resource {
360 __le16 resource_id;
361 __le16 access_type;
362 __le32 timeout;
363 __le32 resource_number;
364 u8 reserved[4];
365 };
366
367 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
368
369 /* Get function capabilities (indirect 0x000A)
370 * Get device capabilities (indirect 0x000B)
371 */
372 struct i40e_aqc_list_capabilites {
373 u8 command_flags;
374 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
375 u8 pf_index;
376 u8 reserved[2];
377 __le32 count;
378 __le32 addr_high;
379 __le32 addr_low;
380 };
381
382 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
383
384 struct i40e_aqc_list_capabilities_element_resp {
385 __le16 id;
386 u8 major_rev;
387 u8 minor_rev;
388 __le32 number;
389 __le32 logical_id;
390 __le32 phys_id;
391 u8 reserved[16];
392 };
393
394 /* list of caps */
395
396 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
397 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
398 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
399 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
400 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
401 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
402 #define I40E_AQ_CAP_ID_SRIOV 0x0012
403 #define I40E_AQ_CAP_ID_VF 0x0013
404 #define I40E_AQ_CAP_ID_VMDQ 0x0014
405 #define I40E_AQ_CAP_ID_8021QBG 0x0015
406 #define I40E_AQ_CAP_ID_8021QBR 0x0016
407 #define I40E_AQ_CAP_ID_VSI 0x0017
408 #define I40E_AQ_CAP_ID_DCB 0x0018
409 #define I40E_AQ_CAP_ID_FCOE 0x0021
410 #define I40E_AQ_CAP_ID_ISCSI 0x0022
411 #define I40E_AQ_CAP_ID_RSS 0x0040
412 #define I40E_AQ_CAP_ID_RXQ 0x0041
413 #define I40E_AQ_CAP_ID_TXQ 0x0042
414 #define I40E_AQ_CAP_ID_MSIX 0x0043
415 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
416 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
417 #define I40E_AQ_CAP_ID_1588 0x0046
418 #define I40E_AQ_CAP_ID_IWARP 0x0051
419 #define I40E_AQ_CAP_ID_LED 0x0061
420 #define I40E_AQ_CAP_ID_SDP 0x0062
421 #define I40E_AQ_CAP_ID_MDIO 0x0063
422 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
423 #define I40E_AQ_CAP_ID_CEM 0x00F2
424
425 /* Set CPPM Configuration (direct 0x0103) */
426 struct i40e_aqc_cppm_configuration {
427 __le16 command_flags;
428 #define I40E_AQ_CPPM_EN_LTRC 0x0800
429 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
430 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
431 #define I40E_AQ_CPPM_EN_HPTC 0x4000
432 #define I40E_AQ_CPPM_EN_DMARC 0x8000
433 __le16 ttlx;
434 __le32 dmacr;
435 __le16 dmcth;
436 u8 hptc;
437 u8 reserved;
438 __le32 pfltrc;
439 };
440
441 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
442
443 /* Set ARP Proxy command / response (indirect 0x0104) */
444 struct i40e_aqc_arp_proxy_data {
445 __le16 command_flags;
446 #define I40E_AQ_ARP_INIT_IPV4 0x0008
447 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
448 #define I40E_AQ_ARP_ENA 0x0020
449 #define I40E_AQ_ARP_ADD_IPV4 0x0040
450 #define I40E_AQ_ARP_DEL_IPV4 0x0080
451 __le16 table_id;
452 __le32 pfpm_proxyfc;
453 __le32 ip_addr;
454 u8 mac_addr[6];
455 u8 reserved[2];
456 };
457
458 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
459
460 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
461 struct i40e_aqc_ns_proxy_data {
462 __le16 table_idx_mac_addr_0;
463 __le16 table_idx_mac_addr_1;
464 __le16 table_idx_ipv6_0;
465 __le16 table_idx_ipv6_1;
466 __le16 control;
467 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
468 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
469 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
470 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
471 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
472 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
473 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
474 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
475 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
476 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
477 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
478 u8 mac_addr_0[6];
479 u8 mac_addr_1[6];
480 u8 local_mac_addr[6];
481 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
482 u8 ipv6_addr_1[16];
483 };
484
485 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
486
487 /* Manage LAA Command (0x0106) - obsolete */
488 struct i40e_aqc_mng_laa {
489 __le16 command_flags;
490 #define I40E_AQ_LAA_FLAG_WR 0x8000
491 u8 reserved[2];
492 __le32 sal;
493 __le16 sah;
494 u8 reserved2[6];
495 };
496
497 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
498
499 /* Manage MAC Address Read Command (indirect 0x0107) */
500 struct i40e_aqc_mac_address_read {
501 __le16 command_flags;
502 #define I40E_AQC_LAN_ADDR_VALID 0x10
503 #define I40E_AQC_SAN_ADDR_VALID 0x20
504 #define I40E_AQC_PORT_ADDR_VALID 0x40
505 #define I40E_AQC_WOL_ADDR_VALID 0x80
506 #define I40E_AQC_MC_MAG_EN_VALID 0x100
507 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
508 u8 reserved[6];
509 __le32 addr_high;
510 __le32 addr_low;
511 };
512
513 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
514
515 struct i40e_aqc_mac_address_read_data {
516 u8 pf_lan_mac[6];
517 u8 pf_san_mac[6];
518 u8 port_mac[6];
519 u8 pf_wol_mac[6];
520 };
521
522 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
523
524 /* Manage MAC Address Write Command (0x0108) */
525 struct i40e_aqc_mac_address_write {
526 __le16 command_flags;
527 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
528 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
529 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
530 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
531 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
532
533 __le16 mac_sah;
534 __le32 mac_sal;
535 u8 reserved[8];
536 };
537
538 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
539
540 /* PXE commands (0x011x) */
541
542 /* Clear PXE Command and response (direct 0x0110) */
543 struct i40e_aqc_clear_pxe {
544 u8 rx_cnt;
545 u8 reserved[15];
546 };
547
548 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
549
550 /* Switch configuration commands (0x02xx) */
551
552 /* Used by many indirect commands that only pass an seid and a buffer in the
553 * command
554 */
555 struct i40e_aqc_switch_seid {
556 __le16 seid;
557 u8 reserved[6];
558 __le32 addr_high;
559 __le32 addr_low;
560 };
561
562 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
563
564 /* Get Switch Configuration command (indirect 0x0200)
565 * uses i40e_aqc_switch_seid for the descriptor
566 */
567 struct i40e_aqc_get_switch_config_header_resp {
568 __le16 num_reported;
569 __le16 num_total;
570 u8 reserved[12];
571 };
572
573 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
574
575 struct i40e_aqc_switch_config_element_resp {
576 u8 element_type;
577 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
578 #define I40E_AQ_SW_ELEM_TYPE_PF 2
579 #define I40E_AQ_SW_ELEM_TYPE_VF 3
580 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
581 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
582 #define I40E_AQ_SW_ELEM_TYPE_PV 16
583 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
584 #define I40E_AQ_SW_ELEM_TYPE_PA 18
585 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
586 u8 revision;
587 #define I40E_AQ_SW_ELEM_REV_1 1
588 __le16 seid;
589 __le16 uplink_seid;
590 __le16 downlink_seid;
591 u8 reserved[3];
592 u8 connection_type;
593 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
594 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
595 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
596 __le16 scheduler_id;
597 __le16 element_info;
598 };
599
600 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
601
602 /* Get Switch Configuration (indirect 0x0200)
603 * an array of elements are returned in the response buffer
604 * the first in the array is the header, remainder are elements
605 */
606 struct i40e_aqc_get_switch_config_resp {
607 struct i40e_aqc_get_switch_config_header_resp header;
608 struct i40e_aqc_switch_config_element_resp element[1];
609 };
610
611 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
612
613 /* Add Statistics (direct 0x0201)
614 * Remove Statistics (direct 0x0202)
615 */
616 struct i40e_aqc_add_remove_statistics {
617 __le16 seid;
618 __le16 vlan;
619 __le16 stat_index;
620 u8 reserved[10];
621 };
622
623 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
624
625 /* Set Port Parameters command (direct 0x0203) */
626 struct i40e_aqc_set_port_parameters {
627 __le16 command_flags;
628 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
629 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
630 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
631 __le16 bad_frame_vsi;
632 __le16 default_seid; /* reserved for command */
633 u8 reserved[10];
634 };
635
636 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
637
638 /* Get Switch Resource Allocation (indirect 0x0204) */
639 struct i40e_aqc_get_switch_resource_alloc {
640 u8 num_entries; /* reserved for command */
641 u8 reserved[7];
642 __le32 addr_high;
643 __le32 addr_low;
644 };
645
646 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
647
648 /* expect an array of these structs in the response buffer */
649 struct i40e_aqc_switch_resource_alloc_element_resp {
650 u8 resource_type;
651 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
652 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
653 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
654 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
655 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
656 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
657 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
658 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
659 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
660 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
661 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
662 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
663 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
664 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
665 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
666 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
667 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
668 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
669 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
670 u8 reserved1;
671 __le16 guaranteed;
672 __le16 total;
673 __le16 used;
674 __le16 total_unalloced;
675 u8 reserved2[6];
676 };
677
678 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
679
680 /* Add VSI (indirect 0x0210)
681 * this indirect command uses struct i40e_aqc_vsi_properties_data
682 * as the indirect buffer (128 bytes)
683 *
684 * Update VSI (indirect 0x211)
685 * uses the same data structure as Add VSI
686 *
687 * Get VSI (indirect 0x0212)
688 * uses the same completion and data structure as Add VSI
689 */
690 struct i40e_aqc_add_get_update_vsi {
691 __le16 uplink_seid;
692 u8 connection_type;
693 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
694 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
695 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
696 u8 reserved1;
697 u8 vf_id;
698 u8 reserved2;
699 __le16 vsi_flags;
700 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
701 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
702 #define I40E_AQ_VSI_TYPE_VF 0x0
703 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
704 #define I40E_AQ_VSI_TYPE_PF 0x2
705 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
706 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
707 __le32 addr_high;
708 __le32 addr_low;
709 };
710
711 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
712
713 struct i40e_aqc_add_get_update_vsi_completion {
714 __le16 seid;
715 __le16 vsi_number;
716 __le16 vsi_used;
717 __le16 vsi_free;
718 __le32 addr_high;
719 __le32 addr_low;
720 };
721
722 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
723
724 struct i40e_aqc_vsi_properties_data {
725 /* first 96 byte are written by SW */
726 __le16 valid_sections;
727 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
728 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
729 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
730 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
731 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
732 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
733 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
734 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
735 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
736 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
737 /* switch section */
738 __le16 switch_id; /* 12bit id combined with flags below */
739 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
740 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
741 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
742 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
743 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
744 u8 sw_reserved[2];
745 /* security section */
746 u8 sec_flags;
747 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
748 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
749 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
750 u8 sec_reserved;
751 /* VLAN section */
752 __le16 pvid; /* VLANS include priority bits */
753 __le16 fcoe_pvid;
754 u8 port_vlan_flags;
755 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
756 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
757 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
758 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
759 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
760 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
761 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
762 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
763 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
764 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
765 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
766 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
767 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
768 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
769 u8 pvlan_reserved[3];
770 /* ingress egress up sections */
771 __le32 ingress_table; /* bitmap, 3 bits per up */
772 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
773 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
774 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
775 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
776 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
777 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
778 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
779 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
780 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
781 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
782 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
783 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
784 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
785 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
786 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
787 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
788 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
789 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
790 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
791 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
792 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
793 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
794 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
795 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
796 __le32 egress_table; /* same defines as for ingress table */
797 /* cascaded PV section */
798 __le16 cas_pv_tag;
799 u8 cas_pv_flags;
800 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
801 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
802 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
803 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
804 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
805 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
806 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
807 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
808 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
809 u8 cas_pv_reserved;
810 /* queue mapping section */
811 __le16 mapping_flags;
812 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
813 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
814 __le16 queue_mapping[16];
815 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
816 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
817 __le16 tc_mapping[8];
818 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
819 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
820 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
821 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
822 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
823 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
824 /* queueing option section */
825 u8 queueing_opt_flags;
826 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
827 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
828 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
829 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
830 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
831 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
832 u8 queueing_opt_reserved[3];
833 /* scheduler section */
834 u8 up_enable_bits;
835 u8 sched_reserved;
836 /* outer up section */
837 __le32 outer_up_table; /* same structure and defines as ingress tbl */
838 u8 cmd_reserved[8];
839 /* last 32 bytes are written by FW */
840 __le16 qs_handle[8];
841 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
842 __le16 stat_counter_idx;
843 __le16 sched_id;
844 u8 resp_reserved[12];
845 };
846
847 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
848
849 /* Add Port Virtualizer (direct 0x0220)
850 * also used for update PV (direct 0x0221) but only flags are used
851 * (IS_CTRL_PORT only works on add PV)
852 */
853 struct i40e_aqc_add_update_pv {
854 __le16 command_flags;
855 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
856 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
857 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
858 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
859 __le16 uplink_seid;
860 __le16 connected_seid;
861 u8 reserved[10];
862 };
863
864 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
865
866 struct i40e_aqc_add_update_pv_completion {
867 /* reserved for update; for add also encodes error if rc == ENOSPC */
868 __le16 pv_seid;
869 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
870 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
871 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
872 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
873 u8 reserved[14];
874 };
875
876 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
877
878 /* Get PV Params (direct 0x0222)
879 * uses i40e_aqc_switch_seid for the descriptor
880 */
881
882 struct i40e_aqc_get_pv_params_completion {
883 __le16 seid;
884 __le16 default_stag;
885 __le16 pv_flags; /* same flags as add_pv */
886 #define I40E_AQC_GET_PV_PV_TYPE 0x1
887 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
888 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
889 u8 reserved[8];
890 __le16 default_port_seid;
891 };
892
893 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
894
895 /* Add VEB (direct 0x0230) */
896 struct i40e_aqc_add_veb {
897 __le16 uplink_seid;
898 __le16 downlink_seid;
899 __le16 veb_flags;
900 #define I40E_AQC_ADD_VEB_FLOATING 0x1
901 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
902 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
903 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
904 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
905 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
906 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
907 u8 enable_tcs;
908 u8 reserved[9];
909 };
910
911 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
912
913 struct i40e_aqc_add_veb_completion {
914 u8 reserved[6];
915 __le16 switch_seid;
916 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
917 __le16 veb_seid;
918 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
919 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
920 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
921 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
922 __le16 statistic_index;
923 __le16 vebs_used;
924 __le16 vebs_free;
925 };
926
927 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
928
929 /* Get VEB Parameters (direct 0x0232)
930 * uses i40e_aqc_switch_seid for the descriptor
931 */
932 struct i40e_aqc_get_veb_parameters_completion {
933 __le16 seid;
934 __le16 switch_id;
935 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
936 __le16 statistic_index;
937 __le16 vebs_used;
938 __le16 vebs_free;
939 u8 reserved[4];
940 };
941
942 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
943
944 /* Delete Element (direct 0x0243)
945 * uses the generic i40e_aqc_switch_seid
946 */
947
948 /* Add MAC-VLAN (indirect 0x0250) */
949
950 /* used for the command for most vlan commands */
951 struct i40e_aqc_macvlan {
952 __le16 num_addresses;
953 __le16 seid[3];
954 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
955 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
956 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
957 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
958 __le32 addr_high;
959 __le32 addr_low;
960 };
961
962 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
963
964 /* indirect data for command and response */
965 struct i40e_aqc_add_macvlan_element_data {
966 u8 mac_addr[6];
967 __le16 vlan_tag;
968 __le16 flags;
969 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
970 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
971 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
972 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
973 __le16 queue_number;
974 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
975 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
976 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
977 /* response section */
978 u8 match_method;
979 #define I40E_AQC_MM_PERFECT_MATCH 0x01
980 #define I40E_AQC_MM_HASH_MATCH 0x02
981 #define I40E_AQC_MM_ERR_NO_RES 0xFF
982 u8 reserved1[3];
983 };
984
985 struct i40e_aqc_add_remove_macvlan_completion {
986 __le16 perfect_mac_used;
987 __le16 perfect_mac_free;
988 __le16 unicast_hash_free;
989 __le16 multicast_hash_free;
990 __le32 addr_high;
991 __le32 addr_low;
992 };
993
994 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
995
996 /* Remove MAC-VLAN (indirect 0x0251)
997 * uses i40e_aqc_macvlan for the descriptor
998 * data points to an array of num_addresses of elements
999 */
1000
1001 struct i40e_aqc_remove_macvlan_element_data {
1002 u8 mac_addr[6];
1003 __le16 vlan_tag;
1004 u8 flags;
1005 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1006 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1007 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1008 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1009 u8 reserved[3];
1010 /* reply section */
1011 u8 error_code;
1012 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1013 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1014 u8 reply_reserved[3];
1015 };
1016
1017 /* Add VLAN (indirect 0x0252)
1018 * Remove VLAN (indirect 0x0253)
1019 * use the generic i40e_aqc_macvlan for the command
1020 */
1021 struct i40e_aqc_add_remove_vlan_element_data {
1022 __le16 vlan_tag;
1023 u8 vlan_flags;
1024 /* flags for add VLAN */
1025 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1026 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1027 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1028 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1029 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1030 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1031 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1032 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1033 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1034 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1035 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1036 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1037 /* flags for remove VLAN */
1038 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1039 u8 reserved;
1040 u8 result;
1041 /* flags for add VLAN */
1042 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1043 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1044 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1045 /* flags for remove VLAN */
1046 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1047 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1048 u8 reserved1[3];
1049 };
1050
1051 struct i40e_aqc_add_remove_vlan_completion {
1052 u8 reserved[4];
1053 __le16 vlans_used;
1054 __le16 vlans_free;
1055 __le32 addr_high;
1056 __le32 addr_low;
1057 };
1058
1059 /* Set VSI Promiscuous Modes (direct 0x0254) */
1060 struct i40e_aqc_set_vsi_promiscuous_modes {
1061 __le16 promiscuous_flags;
1062 __le16 valid_flags;
1063 /* flags used for both fields above */
1064 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1065 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1066 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1067 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1068 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1069 __le16 seid;
1070 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1071 __le16 vlan_tag;
1072 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1073 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1074 u8 reserved[8];
1075 };
1076
1077 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1078
1079 /* Add S/E-tag command (direct 0x0255)
1080 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1081 */
1082 struct i40e_aqc_add_tag {
1083 __le16 flags;
1084 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1085 __le16 seid;
1086 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1087 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1088 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1089 __le16 tag;
1090 __le16 queue_number;
1091 u8 reserved[8];
1092 };
1093
1094 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1095
1096 struct i40e_aqc_add_remove_tag_completion {
1097 u8 reserved[12];
1098 __le16 tags_used;
1099 __le16 tags_free;
1100 };
1101
1102 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1103
1104 /* Remove S/E-tag command (direct 0x0256)
1105 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1106 */
1107 struct i40e_aqc_remove_tag {
1108 __le16 seid;
1109 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1110 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1111 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1112 __le16 tag;
1113 u8 reserved[12];
1114 };
1115
1116 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1117
1118 /* Add multicast E-Tag (direct 0x0257)
1119 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1120 * and no external data
1121 */
1122 struct i40e_aqc_add_remove_mcast_etag {
1123 __le16 pv_seid;
1124 __le16 etag;
1125 u8 num_unicast_etags;
1126 u8 reserved[3];
1127 __le32 addr_high; /* address of array of 2-byte s-tags */
1128 __le32 addr_low;
1129 };
1130
1131 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1132
1133 struct i40e_aqc_add_remove_mcast_etag_completion {
1134 u8 reserved[4];
1135 __le16 mcast_etags_used;
1136 __le16 mcast_etags_free;
1137 __le32 addr_high;
1138 __le32 addr_low;
1139
1140 };
1141
1142 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1143
1144 /* Update S/E-Tag (direct 0x0259) */
1145 struct i40e_aqc_update_tag {
1146 __le16 seid;
1147 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1148 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1149 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1150 __le16 old_tag;
1151 __le16 new_tag;
1152 u8 reserved[10];
1153 };
1154
1155 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1156
1157 struct i40e_aqc_update_tag_completion {
1158 u8 reserved[12];
1159 __le16 tags_used;
1160 __le16 tags_free;
1161 };
1162
1163 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1164
1165 /* Add Control Packet filter (direct 0x025A)
1166 * Remove Control Packet filter (direct 0x025B)
1167 * uses the i40e_aqc_add_oveb_cloud,
1168 * and the generic direct completion structure
1169 */
1170 struct i40e_aqc_add_remove_control_packet_filter {
1171 u8 mac[6];
1172 __le16 etype;
1173 __le16 flags;
1174 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1175 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1176 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1177 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1178 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1179 __le16 seid;
1180 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1181 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1182 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1183 __le16 queue;
1184 u8 reserved[2];
1185 };
1186
1187 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1188
1189 struct i40e_aqc_add_remove_control_packet_filter_completion {
1190 __le16 mac_etype_used;
1191 __le16 etype_used;
1192 __le16 mac_etype_free;
1193 __le16 etype_free;
1194 u8 reserved[8];
1195 };
1196
1197 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1198
1199 /* Add Cloud filters (indirect 0x025C)
1200 * Remove Cloud filters (indirect 0x025D)
1201 * uses the i40e_aqc_add_remove_cloud_filters,
1202 * and the generic indirect completion structure
1203 */
1204 struct i40e_aqc_add_remove_cloud_filters {
1205 u8 num_filters;
1206 u8 reserved;
1207 __le16 seid;
1208 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1209 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1210 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1211 u8 reserved2[4];
1212 __le32 addr_high;
1213 __le32 addr_low;
1214 };
1215
1216 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1217
1218 struct i40e_aqc_add_remove_cloud_filters_element_data {
1219 u8 outer_mac[6];
1220 u8 inner_mac[6];
1221 __le16 inner_vlan;
1222 union {
1223 struct {
1224 u8 reserved[12];
1225 u8 data[4];
1226 } v4;
1227 struct {
1228 u8 data[16];
1229 } v6;
1230 } ipaddr;
1231 __le16 flags;
1232 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1233 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1234 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1235 /* 0x0000 reserved */
1236 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1237 /* 0x0002 reserved */
1238 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1239 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1240 /* 0x0005 reserved */
1241 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1242 /* 0x0007 reserved */
1243 /* 0x0008 reserved */
1244 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1245 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1246 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1247 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1248
1249 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1250 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1251 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1252 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1253 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1254
1255 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1256 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1257 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1261
1262 __le32 tenant_id;
1263 u8 reserved[4];
1264 __le16 queue_number;
1265 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1266 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1267 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1268 u8 reserved2[14];
1269 /* response section */
1270 u8 allocation_result;
1271 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1272 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1273 u8 response_reserved[7];
1274 };
1275
1276 struct i40e_aqc_remove_cloud_filters_completion {
1277 __le16 perfect_ovlan_used;
1278 __le16 perfect_ovlan_free;
1279 __le16 vlan_used;
1280 __le16 vlan_free;
1281 __le32 addr_high;
1282 __le32 addr_low;
1283 };
1284
1285 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1286
1287 /* Add Mirror Rule (indirect or direct 0x0260)
1288 * Delete Mirror Rule (indirect or direct 0x0261)
1289 * note: some rule types (4,5) do not use an external buffer.
1290 * take care to set the flags correctly.
1291 */
1292 struct i40e_aqc_add_delete_mirror_rule {
1293 __le16 seid;
1294 __le16 rule_type;
1295 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1296 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1297 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1298 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1299 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1300 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1301 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1302 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1303 __le16 num_entries;
1304 __le16 destination; /* VSI for add, rule id for delete */
1305 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1306 __le32 addr_low;
1307 };
1308
1309 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1310
1311 struct i40e_aqc_add_delete_mirror_rule_completion {
1312 u8 reserved[2];
1313 __le16 rule_id; /* only used on add */
1314 __le16 mirror_rules_used;
1315 __le16 mirror_rules_free;
1316 __le32 addr_high;
1317 __le32 addr_low;
1318 };
1319
1320 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1321
1322 /* DCB 0x03xx*/
1323
1324 /* PFC Ignore (direct 0x0301)
1325 * the command and response use the same descriptor structure
1326 */
1327 struct i40e_aqc_pfc_ignore {
1328 u8 tc_bitmap;
1329 u8 command_flags; /* unused on response */
1330 #define I40E_AQC_PFC_IGNORE_SET 0x80
1331 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1332 u8 reserved[14];
1333 };
1334
1335 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1336
1337 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1338 * with no parameters
1339 */
1340
1341 /* TX scheduler 0x04xx */
1342
1343 /* Almost all the indirect commands use
1344 * this generic struct to pass the SEID in param0
1345 */
1346 struct i40e_aqc_tx_sched_ind {
1347 __le16 vsi_seid;
1348 u8 reserved[6];
1349 __le32 addr_high;
1350 __le32 addr_low;
1351 };
1352
1353 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1354
1355 /* Several commands respond with a set of queue set handles */
1356 struct i40e_aqc_qs_handles_resp {
1357 __le16 qs_handles[8];
1358 };
1359
1360 /* Configure VSI BW limits (direct 0x0400) */
1361 struct i40e_aqc_configure_vsi_bw_limit {
1362 __le16 vsi_seid;
1363 u8 reserved[2];
1364 __le16 credit;
1365 u8 reserved1[2];
1366 u8 max_credit; /* 0-3, limit = 2^max */
1367 u8 reserved2[7];
1368 };
1369
1370 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1371
1372 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1373 * responds with i40e_aqc_qs_handles_resp
1374 */
1375 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1376 u8 tc_valid_bits;
1377 u8 reserved[15];
1378 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1379
1380 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1381 __le16 tc_bw_max[2];
1382 u8 reserved1[28];
1383 };
1384
1385 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1386
1387 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1388 * responds with i40e_aqc_qs_handles_resp
1389 */
1390 struct i40e_aqc_configure_vsi_tc_bw_data {
1391 u8 tc_valid_bits;
1392 u8 reserved[3];
1393 u8 tc_bw_credits[8];
1394 u8 reserved1[4];
1395 __le16 qs_handles[8];
1396 };
1397
1398 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1399
1400 /* Query vsi bw configuration (indirect 0x0408) */
1401 struct i40e_aqc_query_vsi_bw_config_resp {
1402 u8 tc_valid_bits;
1403 u8 tc_suspended_bits;
1404 u8 reserved[14];
1405 __le16 qs_handles[8];
1406 u8 reserved1[4];
1407 __le16 port_bw_limit;
1408 u8 reserved2[2];
1409 u8 max_bw; /* 0-3, limit = 2^max */
1410 u8 reserved3[23];
1411 };
1412
1413 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1414
1415 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1416 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1417 u8 tc_valid_bits;
1418 u8 reserved[3];
1419 u8 share_credits[8];
1420 __le16 credits[8];
1421
1422 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1423 __le16 tc_bw_max[2];
1424 };
1425
1426 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1427
1428 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1429 struct i40e_aqc_configure_switching_comp_bw_limit {
1430 __le16 seid;
1431 u8 reserved[2];
1432 __le16 credit;
1433 u8 reserved1[2];
1434 u8 max_bw; /* 0-3, limit = 2^max */
1435 u8 reserved2[7];
1436 };
1437
1438 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1439
1440 /* Enable Physical Port ETS (indirect 0x0413)
1441 * Modify Physical Port ETS (indirect 0x0414)
1442 * Disable Physical Port ETS (indirect 0x0415)
1443 */
1444 struct i40e_aqc_configure_switching_comp_ets_data {
1445 u8 reserved[4];
1446 u8 tc_valid_bits;
1447 u8 seepage;
1448 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1449 u8 tc_strict_priority_flags;
1450 u8 reserved1[17];
1451 u8 tc_bw_share_credits[8];
1452 u8 reserved2[96];
1453 };
1454
1455 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1456
1457 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1458 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1459 u8 tc_valid_bits;
1460 u8 reserved[15];
1461 __le16 tc_bw_credit[8];
1462
1463 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1464 __le16 tc_bw_max[2];
1465 u8 reserved1[28];
1466 };
1467
1468 I40E_CHECK_STRUCT_LEN(0x40,
1469 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1470
1471 /* Configure Switching Component Bandwidth Allocation per Tc
1472 * (indirect 0x0417)
1473 */
1474 struct i40e_aqc_configure_switching_comp_bw_config_data {
1475 u8 tc_valid_bits;
1476 u8 reserved[2];
1477 u8 absolute_credits; /* bool */
1478 u8 tc_bw_share_credits[8];
1479 u8 reserved1[20];
1480 };
1481
1482 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1483
1484 /* Query Switching Component Configuration (indirect 0x0418) */
1485 struct i40e_aqc_query_switching_comp_ets_config_resp {
1486 u8 tc_valid_bits;
1487 u8 reserved[35];
1488 __le16 port_bw_limit;
1489 u8 reserved1[2];
1490 u8 tc_bw_max; /* 0-3, limit = 2^max */
1491 u8 reserved2[23];
1492 };
1493
1494 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1495
1496 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1497 struct i40e_aqc_query_port_ets_config_resp {
1498 u8 reserved[4];
1499 u8 tc_valid_bits;
1500 u8 reserved1;
1501 u8 tc_strict_priority_bits;
1502 u8 reserved2;
1503 u8 tc_bw_share_credits[8];
1504 __le16 tc_bw_limits[8];
1505
1506 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1507 __le16 tc_bw_max[2];
1508 u8 reserved3[32];
1509 };
1510
1511 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1512
1513 /* Query Switching Component Bandwidth Allocation per Traffic Type
1514 * (indirect 0x041A)
1515 */
1516 struct i40e_aqc_query_switching_comp_bw_config_resp {
1517 u8 tc_valid_bits;
1518 u8 reserved[2];
1519 u8 absolute_credits_enable; /* bool */
1520 u8 tc_bw_share_credits[8];
1521 __le16 tc_bw_limits[8];
1522
1523 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1524 __le16 tc_bw_max[2];
1525 };
1526
1527 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1528
1529 /* Suspend/resume port TX traffic
1530 * (direct 0x041B and 0x041C) uses the generic SEID struct
1531 */
1532
1533 /* Configure partition BW
1534 * (indirect 0x041D)
1535 */
1536 struct i40e_aqc_configure_partition_bw_data {
1537 __le16 pf_valid_bits;
1538 u8 min_bw[16]; /* guaranteed bandwidth */
1539 u8 max_bw[16]; /* bandwidth limit */
1540 };
1541
1542 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1543
1544 /* Get and set the active HMC resource profile and status.
1545 * (direct 0x0500) and (direct 0x0501)
1546 */
1547 struct i40e_aq_get_set_hmc_resource_profile {
1548 u8 pm_profile;
1549 u8 pe_vf_enabled;
1550 u8 reserved[14];
1551 };
1552
1553 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1554
1555 enum i40e_aq_hmc_profile {
1556 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1557 I40E_HMC_PROFILE_DEFAULT = 1,
1558 I40E_HMC_PROFILE_FAVOR_VF = 2,
1559 I40E_HMC_PROFILE_EQUAL = 3,
1560 };
1561
1562 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1563 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1564
1565 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1566
1567 /* set in param0 for get phy abilities to report qualified modules */
1568 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1569 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1570
1571 enum i40e_aq_phy_type {
1572 I40E_PHY_TYPE_SGMII = 0x0,
1573 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1574 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1575 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1576 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1577 I40E_PHY_TYPE_XAUI = 0x5,
1578 I40E_PHY_TYPE_XFI = 0x6,
1579 I40E_PHY_TYPE_SFI = 0x7,
1580 I40E_PHY_TYPE_XLAUI = 0x8,
1581 I40E_PHY_TYPE_XLPPI = 0x9,
1582 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1583 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1584 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1585 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1586 I40E_PHY_TYPE_100BASE_TX = 0x11,
1587 I40E_PHY_TYPE_1000BASE_T = 0x12,
1588 I40E_PHY_TYPE_10GBASE_T = 0x13,
1589 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1590 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1591 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1592 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1593 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1594 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1595 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1596 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1597 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1598 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1599 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1600 I40E_PHY_TYPE_MAX
1601 };
1602
1603 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1604 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1605 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1606 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1607 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1608
1609 enum i40e_aq_link_speed {
1610 I40E_LINK_SPEED_UNKNOWN = 0,
1611 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1612 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1613 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1614 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1615 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1616 };
1617
1618 struct i40e_aqc_module_desc {
1619 u8 oui[3];
1620 u8 reserved1;
1621 u8 part_number[16];
1622 u8 revision[4];
1623 u8 reserved2[8];
1624 };
1625
1626 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1627
1628 struct i40e_aq_get_phy_abilities_resp {
1629 __le32 phy_type; /* bitmap using the above enum for offsets */
1630 u8 link_speed; /* bitmap using the above enum bit patterns */
1631 u8 abilities;
1632 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1633 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1634 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1635 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1636 #define I40E_AQ_PHY_AN_ENABLED 0x10
1637 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1638 __le16 eee_capability;
1639 #define I40E_AQ_EEE_100BASE_TX 0x0002
1640 #define I40E_AQ_EEE_1000BASE_T 0x0004
1641 #define I40E_AQ_EEE_10GBASE_T 0x0008
1642 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1643 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1644 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1645 __le32 eeer_val;
1646 u8 d3_lpan;
1647 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1648 u8 reserved[3];
1649 u8 phy_id[4];
1650 u8 module_type[3];
1651 u8 qualified_module_count;
1652 #define I40E_AQ_PHY_MAX_QMS 16
1653 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1654 };
1655
1656 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1657
1658 /* Set PHY Config (direct 0x0601) */
1659 struct i40e_aq_set_phy_config { /* same bits as above in all */
1660 __le32 phy_type;
1661 u8 link_speed;
1662 u8 abilities;
1663 /* bits 0-2 use the values from get_phy_abilities_resp */
1664 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1665 #define I40E_AQ_PHY_ENABLE_AN 0x10
1666 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1667 __le16 eee_capability;
1668 __le32 eeer;
1669 u8 low_power_ctrl;
1670 u8 reserved[3];
1671 };
1672
1673 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1674
1675 /* Set MAC Config command data structure (direct 0x0603) */
1676 struct i40e_aq_set_mac_config {
1677 __le16 max_frame_size;
1678 u8 params;
1679 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1680 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1681 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1682 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1693 u8 tx_timer_priority; /* bitmap */
1694 __le16 tx_timer_value;
1695 __le16 fc_refresh_threshold;
1696 u8 reserved[8];
1697 };
1698
1699 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1700
1701 /* Restart Auto-Negotiation (direct 0x605) */
1702 struct i40e_aqc_set_link_restart_an {
1703 u8 command;
1704 #define I40E_AQ_PHY_RESTART_AN 0x02
1705 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1706 u8 reserved[15];
1707 };
1708
1709 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1710
1711 /* Get Link Status cmd & response data structure (direct 0x0607) */
1712 struct i40e_aqc_get_link_status {
1713 __le16 command_flags; /* only field set on command */
1714 #define I40E_AQ_LSE_MASK 0x3
1715 #define I40E_AQ_LSE_NOP 0x0
1716 #define I40E_AQ_LSE_DISABLE 0x2
1717 #define I40E_AQ_LSE_ENABLE 0x3
1718 /* only response uses this flag */
1719 #define I40E_AQ_LSE_IS_ENABLED 0x1
1720 u8 phy_type; /* i40e_aq_phy_type */
1721 u8 link_speed; /* i40e_aq_link_speed */
1722 u8 link_info;
1723 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1724 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1725 #define I40E_AQ_LINK_FAULT 0x02
1726 #define I40E_AQ_LINK_FAULT_TX 0x04
1727 #define I40E_AQ_LINK_FAULT_RX 0x08
1728 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1729 #define I40E_AQ_LINK_UP_PORT 0x20
1730 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1731 #define I40E_AQ_SIGNAL_DETECT 0x80
1732 u8 an_info;
1733 #define I40E_AQ_AN_COMPLETED 0x01
1734 #define I40E_AQ_LP_AN_ABILITY 0x02
1735 #define I40E_AQ_PD_FAULT 0x04
1736 #define I40E_AQ_FEC_EN 0x08
1737 #define I40E_AQ_PHY_LOW_POWER 0x10
1738 #define I40E_AQ_LINK_PAUSE_TX 0x20
1739 #define I40E_AQ_LINK_PAUSE_RX 0x40
1740 #define I40E_AQ_QUALIFIED_MODULE 0x80
1741 u8 ext_info;
1742 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1743 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1744 #define I40E_AQ_LINK_TX_SHIFT 0x02
1745 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1746 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1747 #define I40E_AQ_LINK_TX_DRAINED 0x01
1748 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1749 #define I40E_AQ_LINK_FORCED_40G 0x10
1750 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1751 __le16 max_frame_size;
1752 u8 config;
1753 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1754 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1755 u8 reserved[5];
1756 };
1757
1758 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1759
1760 /* Set event mask command (direct 0x613) */
1761 struct i40e_aqc_set_phy_int_mask {
1762 u8 reserved[8];
1763 __le16 event_mask;
1764 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1765 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1766 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1767 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1768 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1769 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1770 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1771 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1772 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1773 u8 reserved1[6];
1774 };
1775
1776 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1777
1778 /* Get Local AN advt register (direct 0x0614)
1779 * Set Local AN advt register (direct 0x0615)
1780 * Get Link Partner AN advt register (direct 0x0616)
1781 */
1782 struct i40e_aqc_an_advt_reg {
1783 __le32 local_an_reg0;
1784 __le16 local_an_reg1;
1785 u8 reserved[10];
1786 };
1787
1788 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1789
1790 /* Set Loopback mode (0x0618) */
1791 struct i40e_aqc_set_lb_mode {
1792 __le16 lb_mode;
1793 #define I40E_AQ_LB_PHY_LOCAL 0x01
1794 #define I40E_AQ_LB_PHY_REMOTE 0x02
1795 #define I40E_AQ_LB_MAC_LOCAL 0x04
1796 u8 reserved[14];
1797 };
1798
1799 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1800
1801 /* Set PHY Debug command (0x0622) */
1802 struct i40e_aqc_set_phy_debug {
1803 u8 command_flags;
1804 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1805 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1806 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1807 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1808 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1809 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1810 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1811 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1812 u8 reserved[15];
1813 };
1814
1815 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1816
1817 enum i40e_aq_phy_reg_type {
1818 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1819 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1820 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1821 };
1822
1823 /* NVM Read command (indirect 0x0701)
1824 * NVM Erase commands (direct 0x0702)
1825 * NVM Update commands (indirect 0x0703)
1826 */
1827 struct i40e_aqc_nvm_update {
1828 u8 command_flags;
1829 #define I40E_AQ_NVM_LAST_CMD 0x01
1830 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1831 u8 module_pointer;
1832 __le16 length;
1833 __le32 offset;
1834 __le32 addr_high;
1835 __le32 addr_low;
1836 };
1837
1838 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1839
1840 /* NVM Config Read (indirect 0x0704) */
1841 struct i40e_aqc_nvm_config_read {
1842 __le16 cmd_flags;
1843 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1844 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1845 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1846 __le16 element_count;
1847 __le16 element_id; /* Feature/field ID */
1848 __le16 element_id_msw; /* MSWord of field ID */
1849 __le32 address_high;
1850 __le32 address_low;
1851 };
1852
1853 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1854
1855 /* NVM Config Write (indirect 0x0705) */
1856 struct i40e_aqc_nvm_config_write {
1857 __le16 cmd_flags;
1858 __le16 element_count;
1859 u8 reserved[4];
1860 __le32 address_high;
1861 __le32 address_low;
1862 };
1863
1864 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1865
1866 /* Used for 0x0704 as well as for 0x0705 commands */
1867 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1868 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1869 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1870 #define I40E_AQ_ANVM_FEATURE 0
1871 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1872 struct i40e_aqc_nvm_config_data_feature {
1873 __le16 feature_id;
1874 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1875 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1876 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1877 __le16 feature_options;
1878 __le16 feature_selection;
1879 };
1880
1881 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1882
1883 struct i40e_aqc_nvm_config_data_immediate_field {
1884 __le32 field_id;
1885 __le32 field_value;
1886 __le16 field_options;
1887 __le16 reserved;
1888 };
1889
1890 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1891
1892 /* OEM Post Update (indirect 0x0720)
1893 * no command data struct used
1894 */
1895 struct i40e_aqc_nvm_oem_post_update {
1896 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1897 u8 sel_data;
1898 u8 reserved[7];
1899 };
1900
1901 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1902
1903 struct i40e_aqc_nvm_oem_post_update_buffer {
1904 u8 str_len;
1905 u8 dev_addr;
1906 __le16 eeprom_addr;
1907 u8 data[36];
1908 };
1909
1910 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1911
1912 /* Send to PF command (indirect 0x0801) id is only used by PF
1913 * Send to VF command (indirect 0x0802) id is only used by PF
1914 * Send to Peer PF command (indirect 0x0803)
1915 */
1916 struct i40e_aqc_pf_vf_message {
1917 __le32 id;
1918 u8 reserved[4];
1919 __le32 addr_high;
1920 __le32 addr_low;
1921 };
1922
1923 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1924
1925 /* Alternate structure */
1926
1927 /* Direct write (direct 0x0900)
1928 * Direct read (direct 0x0902)
1929 */
1930 struct i40e_aqc_alternate_write {
1931 __le32 address0;
1932 __le32 data0;
1933 __le32 address1;
1934 __le32 data1;
1935 };
1936
1937 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1938
1939 /* Indirect write (indirect 0x0901)
1940 * Indirect read (indirect 0x0903)
1941 */
1942
1943 struct i40e_aqc_alternate_ind_write {
1944 __le32 address;
1945 __le32 length;
1946 __le32 addr_high;
1947 __le32 addr_low;
1948 };
1949
1950 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1951
1952 /* Done alternate write (direct 0x0904)
1953 * uses i40e_aq_desc
1954 */
1955 struct i40e_aqc_alternate_write_done {
1956 __le16 cmd_flags;
1957 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1958 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1959 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1960 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1961 u8 reserved[14];
1962 };
1963
1964 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1965
1966 /* Set OEM mode (direct 0x0905) */
1967 struct i40e_aqc_alternate_set_mode {
1968 __le32 mode;
1969 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1970 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1971 u8 reserved[12];
1972 };
1973
1974 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1975
1976 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1977
1978 /* async events 0x10xx */
1979
1980 /* Lan Queue Overflow Event (direct, 0x1001) */
1981 struct i40e_aqc_lan_overflow {
1982 __le32 prtdcb_rupto;
1983 __le32 otx_ctl;
1984 u8 reserved[8];
1985 };
1986
1987 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1988
1989 /* Get LLDP MIB (indirect 0x0A00) */
1990 struct i40e_aqc_lldp_get_mib {
1991 u8 type;
1992 u8 reserved1;
1993 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1994 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1995 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1996 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1997 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1998 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1999 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2000 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2001 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2002 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2003 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2004 __le16 local_len;
2005 __le16 remote_len;
2006 u8 reserved2[2];
2007 __le32 addr_high;
2008 __le32 addr_low;
2009 };
2010
2011 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2012
2013 /* Configure LLDP MIB Change Event (direct 0x0A01)
2014 * also used for the event (with type in the command field)
2015 */
2016 struct i40e_aqc_lldp_update_mib {
2017 u8 command;
2018 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2019 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2020 u8 reserved[7];
2021 __le32 addr_high;
2022 __le32 addr_low;
2023 };
2024
2025 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2026
2027 /* Add LLDP TLV (indirect 0x0A02)
2028 * Delete LLDP TLV (indirect 0x0A04)
2029 */
2030 struct i40e_aqc_lldp_add_tlv {
2031 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2032 u8 reserved1[1];
2033 __le16 len;
2034 u8 reserved2[4];
2035 __le32 addr_high;
2036 __le32 addr_low;
2037 };
2038
2039 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2040
2041 /* Update LLDP TLV (indirect 0x0A03) */
2042 struct i40e_aqc_lldp_update_tlv {
2043 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2044 u8 reserved;
2045 __le16 old_len;
2046 __le16 new_offset;
2047 __le16 new_len;
2048 __le32 addr_high;
2049 __le32 addr_low;
2050 };
2051
2052 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2053
2054 /* Stop LLDP (direct 0x0A05) */
2055 struct i40e_aqc_lldp_stop {
2056 u8 command;
2057 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2058 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2059 u8 reserved[15];
2060 };
2061
2062 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2063
2064 /* Start LLDP (direct 0x0A06) */
2065
2066 struct i40e_aqc_lldp_start {
2067 u8 command;
2068 #define I40E_AQ_LLDP_AGENT_START 0x1
2069 u8 reserved[15];
2070 };
2071
2072 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2073
2074 /* Apply MIB changes (0x0A07)
2075 * uses the generic struc as it contains no data
2076 */
2077
2078 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2079 struct i40e_aqc_add_udp_tunnel {
2080 __le16 udp_port;
2081 u8 reserved0[3];
2082 u8 protocol_type;
2083 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2084 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2085 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2086 u8 reserved1[10];
2087 };
2088
2089 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2090
2091 struct i40e_aqc_add_udp_tunnel_completion {
2092 __le16 udp_port;
2093 u8 filter_entry_index;
2094 u8 multiple_pfs;
2095 #define I40E_AQC_SINGLE_PF 0x0
2096 #define I40E_AQC_MULTIPLE_PFS 0x1
2097 u8 total_filters;
2098 u8 reserved[11];
2099 };
2100
2101 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2102
2103 /* remove UDP Tunnel command (0x0B01) */
2104 struct i40e_aqc_remove_udp_tunnel {
2105 u8 reserved[2];
2106 u8 index; /* 0 to 15 */
2107 u8 reserved2[13];
2108 };
2109
2110 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2111
2112 struct i40e_aqc_del_udp_tunnel_completion {
2113 __le16 udp_port;
2114 u8 index; /* 0 to 15 */
2115 u8 multiple_pfs;
2116 u8 total_filters_used;
2117 u8 reserved1[11];
2118 };
2119
2120 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2121
2122 struct i40e_aqc_get_set_rss_key {
2123 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2124 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2125 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2126 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2127 __le16 vsi_id;
2128 u8 reserved[6];
2129 __le32 addr_high;
2130 __le32 addr_low;
2131 };
2132
2133 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2134
2135 struct i40e_aqc_get_set_rss_key_data {
2136 u8 standard_rss_key[0x28];
2137 u8 extended_hash_key[0xc];
2138 };
2139
2140 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2141
2142 struct i40e_aqc_get_set_rss_lut {
2143 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2144 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2145 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2146 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2147 __le16 vsi_id;
2148 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2149 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2150 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2151
2152 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2153 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2154 __le16 flags;
2155 u8 reserved[4];
2156 __le32 addr_high;
2157 __le32 addr_low;
2158 };
2159
2160 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2161
2162 /* tunnel key structure 0x0B10 */
2163
2164 struct i40e_aqc_tunnel_key_structure_A0 {
2165 __le16 key1_off;
2166 __le16 key1_len;
2167 __le16 key2_off;
2168 __le16 key2_len;
2169 __le16 flags;
2170 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2171 /* response flags */
2172 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2173 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2174 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2175 u8 resreved[6];
2176 };
2177
2178 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2179
2180 struct i40e_aqc_tunnel_key_structure {
2181 u8 key1_off;
2182 u8 key2_off;
2183 u8 key1_len; /* 0 to 15 */
2184 u8 key2_len; /* 0 to 15 */
2185 u8 flags;
2186 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2187 /* response flags */
2188 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2189 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2190 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2191 u8 network_key_index;
2192 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2193 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2194 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2195 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2196 u8 reserved[10];
2197 };
2198
2199 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2200
2201 /* OEM mode commands (direct 0xFE0x) */
2202 struct i40e_aqc_oem_param_change {
2203 __le32 param_type;
2204 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2205 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2206 #define I40E_AQ_OEM_PARAM_MAC 2
2207 __le32 param_value1;
2208 __le16 param_value2;
2209 u8 reserved[6];
2210 };
2211
2212 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2213
2214 struct i40e_aqc_oem_state_change {
2215 __le32 state;
2216 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2217 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2218 u8 reserved[12];
2219 };
2220
2221 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2222
2223 /* Initialize OCSD (0xFE02, direct) */
2224 struct i40e_aqc_opc_oem_ocsd_initialize {
2225 u8 type_status;
2226 u8 reserved1[3];
2227 __le32 ocsd_memory_block_addr_high;
2228 __le32 ocsd_memory_block_addr_low;
2229 __le32 requested_update_interval;
2230 };
2231
2232 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2233
2234 /* Initialize OCBB (0xFE03, direct) */
2235 struct i40e_aqc_opc_oem_ocbb_initialize {
2236 u8 type_status;
2237 u8 reserved1[3];
2238 __le32 ocbb_memory_block_addr_high;
2239 __le32 ocbb_memory_block_addr_low;
2240 u8 reserved2[4];
2241 };
2242
2243 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2244
2245 /* debug commands */
2246
2247 /* get device id (0xFF00) uses the generic structure */
2248
2249 /* set test more (0xFF01, internal) */
2250
2251 struct i40e_acq_set_test_mode {
2252 u8 mode;
2253 #define I40E_AQ_TEST_PARTIAL 0
2254 #define I40E_AQ_TEST_FULL 1
2255 #define I40E_AQ_TEST_NVM 2
2256 u8 reserved[3];
2257 u8 command;
2258 #define I40E_AQ_TEST_OPEN 0
2259 #define I40E_AQ_TEST_CLOSE 1
2260 #define I40E_AQ_TEST_INC 2
2261 u8 reserved2[3];
2262 __le32 address_high;
2263 __le32 address_low;
2264 };
2265
2266 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2267
2268 /* Debug Read Register command (0xFF03)
2269 * Debug Write Register command (0xFF04)
2270 */
2271 struct i40e_aqc_debug_reg_read_write {
2272 __le32 reserved;
2273 __le32 address;
2274 __le32 value_high;
2275 __le32 value_low;
2276 };
2277
2278 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2279
2280 /* Scatter/gather Reg Read (indirect 0xFF05)
2281 * Scatter/gather Reg Write (indirect 0xFF06)
2282 */
2283
2284 /* i40e_aq_desc is used for the command */
2285 struct i40e_aqc_debug_reg_sg_element_data {
2286 __le32 address;
2287 __le32 value;
2288 };
2289
2290 /* Debug Modify register (direct 0xFF07) */
2291 struct i40e_aqc_debug_modify_reg {
2292 __le32 address;
2293 __le32 value;
2294 __le32 clear_mask;
2295 __le32 set_mask;
2296 };
2297
2298 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2299
2300 /* dump internal data (0xFF08, indirect) */
2301
2302 #define I40E_AQ_CLUSTER_ID_AUX 0
2303 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2304 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2305 #define I40E_AQ_CLUSTER_ID_HMC 3
2306 #define I40E_AQ_CLUSTER_ID_MAC0 4
2307 #define I40E_AQ_CLUSTER_ID_MAC1 5
2308 #define I40E_AQ_CLUSTER_ID_MAC2 6
2309 #define I40E_AQ_CLUSTER_ID_MAC3 7
2310 #define I40E_AQ_CLUSTER_ID_DCB 8
2311 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2312 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2313 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2314
2315 struct i40e_aqc_debug_dump_internals {
2316 u8 cluster_id;
2317 u8 table_id;
2318 __le16 data_size;
2319 __le32 idx;
2320 __le32 address_high;
2321 __le32 address_low;
2322 };
2323
2324 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2325
2326 struct i40e_aqc_debug_modify_internals {
2327 u8 cluster_id;
2328 u8 cluster_specific_params[7];
2329 __le32 address_high;
2330 __le32 address_low;
2331 };
2332
2333 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2334
2335 #endif /* _I40E_ADMINQ_CMD_H_ */
Linux kernel - Deliverables
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