projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'batman-adv-for-davem' of git://git.open-mesh.org/linux-merge
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_adminq_cmd.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
29
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0004
38
39 struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61 };
62
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
80
81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
92
93 /* error codes */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
118 };
119
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
122 /* aq commands */
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
127
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
131
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
134
135 /* LAA */
136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
138
139 /* PXE */
140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
141
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
148
149 i40e_aqc_opc_add_vsi = 0x0210,
150 i40e_aqc_opc_update_vsi_parameters = 0x0211,
151 i40e_aqc_opc_get_vsi_parameters = 0x0212,
152
153 i40e_aqc_opc_add_pv = 0x0220,
154 i40e_aqc_opc_update_pv_parameters = 0x0221,
155 i40e_aqc_opc_get_pv_parameters = 0x0222,
156
157 i40e_aqc_opc_add_veb = 0x0230,
158 i40e_aqc_opc_update_veb_parameters = 0x0231,
159 i40e_aqc_opc_get_veb_parameters = 0x0232,
160
161 i40e_aqc_opc_delete_element = 0x0243,
162
163 i40e_aqc_opc_add_macvlan = 0x0250,
164 i40e_aqc_opc_remove_macvlan = 0x0251,
165 i40e_aqc_opc_add_vlan = 0x0252,
166 i40e_aqc_opc_remove_vlan = 0x0253,
167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
168 i40e_aqc_opc_add_tag = 0x0255,
169 i40e_aqc_opc_remove_tag = 0x0256,
170 i40e_aqc_opc_add_multicast_etag = 0x0257,
171 i40e_aqc_opc_remove_multicast_etag = 0x0258,
172 i40e_aqc_opc_update_tag = 0x0259,
173 i40e_aqc_opc_add_control_packet_filter = 0x025A,
174 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
175 i40e_aqc_opc_add_cloud_filters = 0x025C,
176 i40e_aqc_opc_remove_cloud_filters = 0x025D,
177
178 i40e_aqc_opc_add_mirror_rule = 0x0260,
179 i40e_aqc_opc_delete_mirror_rule = 0x0261,
180
181 /* DCB commands */
182 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
183 i40e_aqc_opc_dcb_updated = 0x0302,
184
185 /* TX scheduler */
186 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
187 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
188 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
189 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
190 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
191 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
192
193 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
194 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
195 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
196 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
197 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
198 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
199 i40e_aqc_opc_query_port_ets_config = 0x0419,
200 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
201 i40e_aqc_opc_suspend_port_tx = 0x041B,
202 i40e_aqc_opc_resume_port_tx = 0x041C,
203 i40e_aqc_opc_configure_partition_bw = 0x041D,
204
205 /* hmc */
206 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
207 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
208
209 /* phy commands*/
210 i40e_aqc_opc_get_phy_abilities = 0x0600,
211 i40e_aqc_opc_set_phy_config = 0x0601,
212 i40e_aqc_opc_set_mac_config = 0x0603,
213 i40e_aqc_opc_set_link_restart_an = 0x0605,
214 i40e_aqc_opc_get_link_status = 0x0607,
215 i40e_aqc_opc_set_phy_int_mask = 0x0613,
216 i40e_aqc_opc_get_local_advt_reg = 0x0614,
217 i40e_aqc_opc_set_local_advt_reg = 0x0615,
218 i40e_aqc_opc_get_partner_advt = 0x0616,
219 i40e_aqc_opc_set_lb_modes = 0x0618,
220 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
221 i40e_aqc_opc_set_phy_debug = 0x0622,
222 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
223 i40e_aqc_opc_run_phy_activity = 0x0626,
224
225 /* NVM commands */
226 i40e_aqc_opc_nvm_read = 0x0701,
227 i40e_aqc_opc_nvm_erase = 0x0702,
228 i40e_aqc_opc_nvm_update = 0x0703,
229 i40e_aqc_opc_nvm_config_read = 0x0704,
230 i40e_aqc_opc_nvm_config_write = 0x0705,
231 i40e_aqc_opc_oem_post_update = 0x0720,
232
233 /* virtualization commands */
234 i40e_aqc_opc_send_msg_to_pf = 0x0801,
235 i40e_aqc_opc_send_msg_to_vf = 0x0802,
236 i40e_aqc_opc_send_msg_to_peer = 0x0803,
237
238 /* alternate structure */
239 i40e_aqc_opc_alternate_write = 0x0900,
240 i40e_aqc_opc_alternate_write_indirect = 0x0901,
241 i40e_aqc_opc_alternate_read = 0x0902,
242 i40e_aqc_opc_alternate_read_indirect = 0x0903,
243 i40e_aqc_opc_alternate_write_done = 0x0904,
244 i40e_aqc_opc_alternate_set_mode = 0x0905,
245 i40e_aqc_opc_alternate_clear_port = 0x0906,
246
247 /* LLDP commands */
248 i40e_aqc_opc_lldp_get_mib = 0x0A00,
249 i40e_aqc_opc_lldp_update_mib = 0x0A01,
250 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
251 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
252 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
253 i40e_aqc_opc_lldp_stop = 0x0A05,
254 i40e_aqc_opc_lldp_start = 0x0A06,
255
256 /* Tunnel commands */
257 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
258 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
259 i40e_aqc_opc_set_rss_key = 0x0B02,
260 i40e_aqc_opc_set_rss_lut = 0x0B03,
261 i40e_aqc_opc_get_rss_key = 0x0B04,
262 i40e_aqc_opc_get_rss_lut = 0x0B05,
263
264 /* Async Events */
265 i40e_aqc_opc_event_lan_overflow = 0x1001,
266
267 /* OEM commands */
268 i40e_aqc_opc_oem_parameter_change = 0xFE00,
269 i40e_aqc_opc_oem_device_status_change = 0xFE01,
270 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
271 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
272
273 /* debug commands */
274 i40e_aqc_opc_debug_read_reg = 0xFF03,
275 i40e_aqc_opc_debug_write_reg = 0xFF04,
276 i40e_aqc_opc_debug_modify_reg = 0xFF07,
277 i40e_aqc_opc_debug_dump_internals = 0xFF08,
278 };
279
280 /* command structures and indirect data structures */
281
282 /* Structure naming conventions:
283 * - no suffix for direct command descriptor structures
284 * - _data for indirect sent data
285 * - _resp for indirect return data (data which is both will use _data)
286 * - _completion for direct return data
287 * - _element_ for repeated elements (may also be _data or _resp)
288 *
289 * Command structures are expected to overlay the params.raw member of the basic
290 * descriptor, and as such cannot exceed 16 bytes in length.
291 */
292
293 /* This macro is used to generate a compilation error if a structure
294 * is not exactly the correct length. It gives a divide by zero error if the
295 * structure is not of the correct size, otherwise it creates an enum that is
296 * never used.
297 */
298 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
299 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
300
301 /* This macro is used extensively to ensure that command structures are 16
302 * bytes in length as they have to map to the raw array of that size.
303 */
304 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
305
306 /* internal (0x00XX) commands */
307
308 /* Get version (direct 0x0001) */
309 struct i40e_aqc_get_version {
310 __le32 rom_ver;
311 __le32 fw_build;
312 __le16 fw_major;
313 __le16 fw_minor;
314 __le16 api_major;
315 __le16 api_minor;
316 };
317
318 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
319
320 /* Send driver version (indirect 0x0002) */
321 struct i40e_aqc_driver_version {
322 u8 driver_major_ver;
323 u8 driver_minor_ver;
324 u8 driver_build_ver;
325 u8 driver_subbuild_ver;
326 u8 reserved[4];
327 __le32 address_high;
328 __le32 address_low;
329 };
330
331 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
332
333 /* Queue Shutdown (direct 0x0003) */
334 struct i40e_aqc_queue_shutdown {
335 __le32 driver_unloading;
336 #define I40E_AQ_DRIVER_UNLOADING 0x1
337 u8 reserved[12];
338 };
339
340 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
341
342 /* Set PF context (0x0004, direct) */
343 struct i40e_aqc_set_pf_context {
344 u8 pf_id;
345 u8 reserved[15];
346 };
347
348 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
349
350 /* Request resource ownership (direct 0x0008)
351 * Release resource ownership (direct 0x0009)
352 */
353 #define I40E_AQ_RESOURCE_NVM 1
354 #define I40E_AQ_RESOURCE_SDP 2
355 #define I40E_AQ_RESOURCE_ACCESS_READ 1
356 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
357 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
358 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
359
360 struct i40e_aqc_request_resource {
361 __le16 resource_id;
362 __le16 access_type;
363 __le32 timeout;
364 __le32 resource_number;
365 u8 reserved[4];
366 };
367
368 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
369
370 /* Get function capabilities (indirect 0x000A)
371 * Get device capabilities (indirect 0x000B)
372 */
373 struct i40e_aqc_list_capabilites {
374 u8 command_flags;
375 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
376 u8 pf_index;
377 u8 reserved[2];
378 __le32 count;
379 __le32 addr_high;
380 __le32 addr_low;
381 };
382
383 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
384
385 struct i40e_aqc_list_capabilities_element_resp {
386 __le16 id;
387 u8 major_rev;
388 u8 minor_rev;
389 __le32 number;
390 __le32 logical_id;
391 __le32 phys_id;
392 u8 reserved[16];
393 };
394
395 /* list of caps */
396
397 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
398 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
399 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
400 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
401 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
402 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
403 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
404 #define I40E_AQ_CAP_ID_SRIOV 0x0012
405 #define I40E_AQ_CAP_ID_VF 0x0013
406 #define I40E_AQ_CAP_ID_VMDQ 0x0014
407 #define I40E_AQ_CAP_ID_8021QBG 0x0015
408 #define I40E_AQ_CAP_ID_8021QBR 0x0016
409 #define I40E_AQ_CAP_ID_VSI 0x0017
410 #define I40E_AQ_CAP_ID_DCB 0x0018
411 #define I40E_AQ_CAP_ID_FCOE 0x0021
412 #define I40E_AQ_CAP_ID_ISCSI 0x0022
413 #define I40E_AQ_CAP_ID_RSS 0x0040
414 #define I40E_AQ_CAP_ID_RXQ 0x0041
415 #define I40E_AQ_CAP_ID_TXQ 0x0042
416 #define I40E_AQ_CAP_ID_MSIX 0x0043
417 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
418 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
419 #define I40E_AQ_CAP_ID_1588 0x0046
420 #define I40E_AQ_CAP_ID_IWARP 0x0051
421 #define I40E_AQ_CAP_ID_LED 0x0061
422 #define I40E_AQ_CAP_ID_SDP 0x0062
423 #define I40E_AQ_CAP_ID_MDIO 0x0063
424 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
425 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
426 #define I40E_AQ_CAP_ID_CEM 0x00F2
427
428 /* Set CPPM Configuration (direct 0x0103) */
429 struct i40e_aqc_cppm_configuration {
430 __le16 command_flags;
431 #define I40E_AQ_CPPM_EN_LTRC 0x0800
432 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
433 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
434 #define I40E_AQ_CPPM_EN_HPTC 0x4000
435 #define I40E_AQ_CPPM_EN_DMARC 0x8000
436 __le16 ttlx;
437 __le32 dmacr;
438 __le16 dmcth;
439 u8 hptc;
440 u8 reserved;
441 __le32 pfltrc;
442 };
443
444 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
445
446 /* Set ARP Proxy command / response (indirect 0x0104) */
447 struct i40e_aqc_arp_proxy_data {
448 __le16 command_flags;
449 #define I40E_AQ_ARP_INIT_IPV4 0x0008
450 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
451 #define I40E_AQ_ARP_ENA 0x0020
452 #define I40E_AQ_ARP_ADD_IPV4 0x0040
453 #define I40E_AQ_ARP_DEL_IPV4 0x0080
454 __le16 table_id;
455 __le32 pfpm_proxyfc;
456 __le32 ip_addr;
457 u8 mac_addr[6];
458 u8 reserved[2];
459 };
460
461 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
462
463 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
464 struct i40e_aqc_ns_proxy_data {
465 __le16 table_idx_mac_addr_0;
466 __le16 table_idx_mac_addr_1;
467 __le16 table_idx_ipv6_0;
468 __le16 table_idx_ipv6_1;
469 __le16 control;
470 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
471 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
472 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
473 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
474 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
475 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
476 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
477 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
478 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
479 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
480 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
481 u8 mac_addr_0[6];
482 u8 mac_addr_1[6];
483 u8 local_mac_addr[6];
484 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
485 u8 ipv6_addr_1[16];
486 };
487
488 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
489
490 /* Manage LAA Command (0x0106) - obsolete */
491 struct i40e_aqc_mng_laa {
492 __le16 command_flags;
493 #define I40E_AQ_LAA_FLAG_WR 0x8000
494 u8 reserved[2];
495 __le32 sal;
496 __le16 sah;
497 u8 reserved2[6];
498 };
499
500 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
501
502 /* Manage MAC Address Read Command (indirect 0x0107) */
503 struct i40e_aqc_mac_address_read {
504 __le16 command_flags;
505 #define I40E_AQC_LAN_ADDR_VALID 0x10
506 #define I40E_AQC_SAN_ADDR_VALID 0x20
507 #define I40E_AQC_PORT_ADDR_VALID 0x40
508 #define I40E_AQC_WOL_ADDR_VALID 0x80
509 #define I40E_AQC_MC_MAG_EN_VALID 0x100
510 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
511 u8 reserved[6];
512 __le32 addr_high;
513 __le32 addr_low;
514 };
515
516 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
517
518 struct i40e_aqc_mac_address_read_data {
519 u8 pf_lan_mac[6];
520 u8 pf_san_mac[6];
521 u8 port_mac[6];
522 u8 pf_wol_mac[6];
523 };
524
525 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
526
527 /* Manage MAC Address Write Command (0x0108) */
528 struct i40e_aqc_mac_address_write {
529 __le16 command_flags;
530 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
531 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
532 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
533 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
534 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
535
536 __le16 mac_sah;
537 __le32 mac_sal;
538 u8 reserved[8];
539 };
540
541 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
542
543 /* PXE commands (0x011x) */
544
545 /* Clear PXE Command and response (direct 0x0110) */
546 struct i40e_aqc_clear_pxe {
547 u8 rx_cnt;
548 u8 reserved[15];
549 };
550
551 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
552
553 /* Switch configuration commands (0x02xx) */
554
555 /* Used by many indirect commands that only pass an seid and a buffer in the
556 * command
557 */
558 struct i40e_aqc_switch_seid {
559 __le16 seid;
560 u8 reserved[6];
561 __le32 addr_high;
562 __le32 addr_low;
563 };
564
565 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
566
567 /* Get Switch Configuration command (indirect 0x0200)
568 * uses i40e_aqc_switch_seid for the descriptor
569 */
570 struct i40e_aqc_get_switch_config_header_resp {
571 __le16 num_reported;
572 __le16 num_total;
573 u8 reserved[12];
574 };
575
576 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
577
578 struct i40e_aqc_switch_config_element_resp {
579 u8 element_type;
580 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
581 #define I40E_AQ_SW_ELEM_TYPE_PF 2
582 #define I40E_AQ_SW_ELEM_TYPE_VF 3
583 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
584 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
585 #define I40E_AQ_SW_ELEM_TYPE_PV 16
586 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
587 #define I40E_AQ_SW_ELEM_TYPE_PA 18
588 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
589 u8 revision;
590 #define I40E_AQ_SW_ELEM_REV_1 1
591 __le16 seid;
592 __le16 uplink_seid;
593 __le16 downlink_seid;
594 u8 reserved[3];
595 u8 connection_type;
596 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
597 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
598 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
599 __le16 scheduler_id;
600 __le16 element_info;
601 };
602
603 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
604
605 /* Get Switch Configuration (indirect 0x0200)
606 * an array of elements are returned in the response buffer
607 * the first in the array is the header, remainder are elements
608 */
609 struct i40e_aqc_get_switch_config_resp {
610 struct i40e_aqc_get_switch_config_header_resp header;
611 struct i40e_aqc_switch_config_element_resp element[1];
612 };
613
614 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
615
616 /* Add Statistics (direct 0x0201)
617 * Remove Statistics (direct 0x0202)
618 */
619 struct i40e_aqc_add_remove_statistics {
620 __le16 seid;
621 __le16 vlan;
622 __le16 stat_index;
623 u8 reserved[10];
624 };
625
626 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
627
628 /* Set Port Parameters command (direct 0x0203) */
629 struct i40e_aqc_set_port_parameters {
630 __le16 command_flags;
631 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
632 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
633 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
634 __le16 bad_frame_vsi;
635 __le16 default_seid; /* reserved for command */
636 u8 reserved[10];
637 };
638
639 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
640
641 /* Get Switch Resource Allocation (indirect 0x0204) */
642 struct i40e_aqc_get_switch_resource_alloc {
643 u8 num_entries; /* reserved for command */
644 u8 reserved[7];
645 __le32 addr_high;
646 __le32 addr_low;
647 };
648
649 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
650
651 /* expect an array of these structs in the response buffer */
652 struct i40e_aqc_switch_resource_alloc_element_resp {
653 u8 resource_type;
654 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
655 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
656 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
657 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
658 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
659 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
660 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
661 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
662 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
663 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
664 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
665 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
666 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
667 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
668 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
669 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
670 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
671 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
672 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
673 u8 reserved1;
674 __le16 guaranteed;
675 __le16 total;
676 __le16 used;
677 __le16 total_unalloced;
678 u8 reserved2[6];
679 };
680
681 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
682
683 /* Add VSI (indirect 0x0210)
684 * this indirect command uses struct i40e_aqc_vsi_properties_data
685 * as the indirect buffer (128 bytes)
686 *
687 * Update VSI (indirect 0x211)
688 * uses the same data structure as Add VSI
689 *
690 * Get VSI (indirect 0x0212)
691 * uses the same completion and data structure as Add VSI
692 */
693 struct i40e_aqc_add_get_update_vsi {
694 __le16 uplink_seid;
695 u8 connection_type;
696 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
697 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
698 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
699 u8 reserved1;
700 u8 vf_id;
701 u8 reserved2;
702 __le16 vsi_flags;
703 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
704 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
705 #define I40E_AQ_VSI_TYPE_VF 0x0
706 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
707 #define I40E_AQ_VSI_TYPE_PF 0x2
708 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
709 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
710 __le32 addr_high;
711 __le32 addr_low;
712 };
713
714 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
715
716 struct i40e_aqc_add_get_update_vsi_completion {
717 __le16 seid;
718 __le16 vsi_number;
719 __le16 vsi_used;
720 __le16 vsi_free;
721 __le32 addr_high;
722 __le32 addr_low;
723 };
724
725 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
726
727 struct i40e_aqc_vsi_properties_data {
728 /* first 96 byte are written by SW */
729 __le16 valid_sections;
730 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
731 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
732 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
733 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
734 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
735 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
736 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
737 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
738 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
739 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
740 /* switch section */
741 __le16 switch_id; /* 12bit id combined with flags below */
742 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
743 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
744 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
745 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
746 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
747 u8 sw_reserved[2];
748 /* security section */
749 u8 sec_flags;
750 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
751 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
752 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
753 u8 sec_reserved;
754 /* VLAN section */
755 __le16 pvid; /* VLANS include priority bits */
756 __le16 fcoe_pvid;
757 u8 port_vlan_flags;
758 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
759 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
760 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
761 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
762 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
763 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
764 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
765 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
766 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
767 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
768 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
769 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
770 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
771 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
772 u8 pvlan_reserved[3];
773 /* ingress egress up sections */
774 __le32 ingress_table; /* bitmap, 3 bits per up */
775 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
776 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
777 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
778 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
779 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
780 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
781 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
782 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
783 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
784 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
785 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
786 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
787 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
788 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
789 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
790 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
791 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
792 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
793 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
794 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
795 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
796 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
797 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
798 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
799 __le32 egress_table; /* same defines as for ingress table */
800 /* cascaded PV section */
801 __le16 cas_pv_tag;
802 u8 cas_pv_flags;
803 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
804 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
805 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
806 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
807 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
808 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
809 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
810 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
811 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
812 u8 cas_pv_reserved;
813 /* queue mapping section */
814 __le16 mapping_flags;
815 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
816 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
817 __le16 queue_mapping[16];
818 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
819 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
820 __le16 tc_mapping[8];
821 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
822 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
823 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
824 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
825 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
826 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
827 /* queueing option section */
828 u8 queueing_opt_flags;
829 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
830 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
831 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
832 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
833 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
834 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
835 u8 queueing_opt_reserved[3];
836 /* scheduler section */
837 u8 up_enable_bits;
838 u8 sched_reserved;
839 /* outer up section */
840 __le32 outer_up_table; /* same structure and defines as ingress tbl */
841 u8 cmd_reserved[8];
842 /* last 32 bytes are written by FW */
843 __le16 qs_handle[8];
844 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
845 __le16 stat_counter_idx;
846 __le16 sched_id;
847 u8 resp_reserved[12];
848 };
849
850 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
851
852 /* Add Port Virtualizer (direct 0x0220)
853 * also used for update PV (direct 0x0221) but only flags are used
854 * (IS_CTRL_PORT only works on add PV)
855 */
856 struct i40e_aqc_add_update_pv {
857 __le16 command_flags;
858 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
859 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
860 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
861 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
862 __le16 uplink_seid;
863 __le16 connected_seid;
864 u8 reserved[10];
865 };
866
867 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
868
869 struct i40e_aqc_add_update_pv_completion {
870 /* reserved for update; for add also encodes error if rc == ENOSPC */
871 __le16 pv_seid;
872 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
873 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
874 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
875 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
876 u8 reserved[14];
877 };
878
879 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
880
881 /* Get PV Params (direct 0x0222)
882 * uses i40e_aqc_switch_seid for the descriptor
883 */
884
885 struct i40e_aqc_get_pv_params_completion {
886 __le16 seid;
887 __le16 default_stag;
888 __le16 pv_flags; /* same flags as add_pv */
889 #define I40E_AQC_GET_PV_PV_TYPE 0x1
890 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
891 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
892 u8 reserved[8];
893 __le16 default_port_seid;
894 };
895
896 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
897
898 /* Add VEB (direct 0x0230) */
899 struct i40e_aqc_add_veb {
900 __le16 uplink_seid;
901 __le16 downlink_seid;
902 __le16 veb_flags;
903 #define I40E_AQC_ADD_VEB_FLOATING 0x1
904 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
905 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
906 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
907 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
908 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
909 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
910 u8 enable_tcs;
911 u8 reserved[9];
912 };
913
914 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
915
916 struct i40e_aqc_add_veb_completion {
917 u8 reserved[6];
918 __le16 switch_seid;
919 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
920 __le16 veb_seid;
921 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
922 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
923 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
924 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
925 __le16 statistic_index;
926 __le16 vebs_used;
927 __le16 vebs_free;
928 };
929
930 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
931
932 /* Get VEB Parameters (direct 0x0232)
933 * uses i40e_aqc_switch_seid for the descriptor
934 */
935 struct i40e_aqc_get_veb_parameters_completion {
936 __le16 seid;
937 __le16 switch_id;
938 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
939 __le16 statistic_index;
940 __le16 vebs_used;
941 __le16 vebs_free;
942 u8 reserved[4];
943 };
944
945 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
946
947 /* Delete Element (direct 0x0243)
948 * uses the generic i40e_aqc_switch_seid
949 */
950
951 /* Add MAC-VLAN (indirect 0x0250) */
952
953 /* used for the command for most vlan commands */
954 struct i40e_aqc_macvlan {
955 __le16 num_addresses;
956 __le16 seid[3];
957 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
958 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
959 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
960 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
961 __le32 addr_high;
962 __le32 addr_low;
963 };
964
965 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
966
967 /* indirect data for command and response */
968 struct i40e_aqc_add_macvlan_element_data {
969 u8 mac_addr[6];
970 __le16 vlan_tag;
971 __le16 flags;
972 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
973 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
974 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
975 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
976 __le16 queue_number;
977 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
978 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
979 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
980 /* response section */
981 u8 match_method;
982 #define I40E_AQC_MM_PERFECT_MATCH 0x01
983 #define I40E_AQC_MM_HASH_MATCH 0x02
984 #define I40E_AQC_MM_ERR_NO_RES 0xFF
985 u8 reserved1[3];
986 };
987
988 struct i40e_aqc_add_remove_macvlan_completion {
989 __le16 perfect_mac_used;
990 __le16 perfect_mac_free;
991 __le16 unicast_hash_free;
992 __le16 multicast_hash_free;
993 __le32 addr_high;
994 __le32 addr_low;
995 };
996
997 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
998
999 /* Remove MAC-VLAN (indirect 0x0251)
1000 * uses i40e_aqc_macvlan for the descriptor
1001 * data points to an array of num_addresses of elements
1002 */
1003
1004 struct i40e_aqc_remove_macvlan_element_data {
1005 u8 mac_addr[6];
1006 __le16 vlan_tag;
1007 u8 flags;
1008 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1009 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1010 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1011 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1012 u8 reserved[3];
1013 /* reply section */
1014 u8 error_code;
1015 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1016 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1017 u8 reply_reserved[3];
1018 };
1019
1020 /* Add VLAN (indirect 0x0252)
1021 * Remove VLAN (indirect 0x0253)
1022 * use the generic i40e_aqc_macvlan for the command
1023 */
1024 struct i40e_aqc_add_remove_vlan_element_data {
1025 __le16 vlan_tag;
1026 u8 vlan_flags;
1027 /* flags for add VLAN */
1028 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1029 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1030 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1031 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1032 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1033 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1034 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1035 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1036 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1037 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1038 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1039 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1040 /* flags for remove VLAN */
1041 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1042 u8 reserved;
1043 u8 result;
1044 /* flags for add VLAN */
1045 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1046 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1047 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1048 /* flags for remove VLAN */
1049 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1050 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1051 u8 reserved1[3];
1052 };
1053
1054 struct i40e_aqc_add_remove_vlan_completion {
1055 u8 reserved[4];
1056 __le16 vlans_used;
1057 __le16 vlans_free;
1058 __le32 addr_high;
1059 __le32 addr_low;
1060 };
1061
1062 /* Set VSI Promiscuous Modes (direct 0x0254) */
1063 struct i40e_aqc_set_vsi_promiscuous_modes {
1064 __le16 promiscuous_flags;
1065 __le16 valid_flags;
1066 /* flags used for both fields above */
1067 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1068 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1069 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1070 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1071 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1072 __le16 seid;
1073 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1074 __le16 vlan_tag;
1075 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1076 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1077 u8 reserved[8];
1078 };
1079
1080 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1081
1082 /* Add S/E-tag command (direct 0x0255)
1083 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1084 */
1085 struct i40e_aqc_add_tag {
1086 __le16 flags;
1087 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1088 __le16 seid;
1089 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1090 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1091 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1092 __le16 tag;
1093 __le16 queue_number;
1094 u8 reserved[8];
1095 };
1096
1097 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1098
1099 struct i40e_aqc_add_remove_tag_completion {
1100 u8 reserved[12];
1101 __le16 tags_used;
1102 __le16 tags_free;
1103 };
1104
1105 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1106
1107 /* Remove S/E-tag command (direct 0x0256)
1108 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1109 */
1110 struct i40e_aqc_remove_tag {
1111 __le16 seid;
1112 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1113 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1114 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1115 __le16 tag;
1116 u8 reserved[12];
1117 };
1118
1119 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1120
1121 /* Add multicast E-Tag (direct 0x0257)
1122 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1123 * and no external data
1124 */
1125 struct i40e_aqc_add_remove_mcast_etag {
1126 __le16 pv_seid;
1127 __le16 etag;
1128 u8 num_unicast_etags;
1129 u8 reserved[3];
1130 __le32 addr_high; /* address of array of 2-byte s-tags */
1131 __le32 addr_low;
1132 };
1133
1134 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1135
1136 struct i40e_aqc_add_remove_mcast_etag_completion {
1137 u8 reserved[4];
1138 __le16 mcast_etags_used;
1139 __le16 mcast_etags_free;
1140 __le32 addr_high;
1141 __le32 addr_low;
1142
1143 };
1144
1145 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1146
1147 /* Update S/E-Tag (direct 0x0259) */
1148 struct i40e_aqc_update_tag {
1149 __le16 seid;
1150 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1151 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1152 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1153 __le16 old_tag;
1154 __le16 new_tag;
1155 u8 reserved[10];
1156 };
1157
1158 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1159
1160 struct i40e_aqc_update_tag_completion {
1161 u8 reserved[12];
1162 __le16 tags_used;
1163 __le16 tags_free;
1164 };
1165
1166 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1167
1168 /* Add Control Packet filter (direct 0x025A)
1169 * Remove Control Packet filter (direct 0x025B)
1170 * uses the i40e_aqc_add_oveb_cloud,
1171 * and the generic direct completion structure
1172 */
1173 struct i40e_aqc_add_remove_control_packet_filter {
1174 u8 mac[6];
1175 __le16 etype;
1176 __le16 flags;
1177 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1178 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1179 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1180 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1181 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1182 __le16 seid;
1183 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1184 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1185 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1186 __le16 queue;
1187 u8 reserved[2];
1188 };
1189
1190 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1191
1192 struct i40e_aqc_add_remove_control_packet_filter_completion {
1193 __le16 mac_etype_used;
1194 __le16 etype_used;
1195 __le16 mac_etype_free;
1196 __le16 etype_free;
1197 u8 reserved[8];
1198 };
1199
1200 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1201
1202 /* Add Cloud filters (indirect 0x025C)
1203 * Remove Cloud filters (indirect 0x025D)
1204 * uses the i40e_aqc_add_remove_cloud_filters,
1205 * and the generic indirect completion structure
1206 */
1207 struct i40e_aqc_add_remove_cloud_filters {
1208 u8 num_filters;
1209 u8 reserved;
1210 __le16 seid;
1211 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1212 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1213 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1214 u8 reserved2[4];
1215 __le32 addr_high;
1216 __le32 addr_low;
1217 };
1218
1219 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1220
1221 struct i40e_aqc_add_remove_cloud_filters_element_data {
1222 u8 outer_mac[6];
1223 u8 inner_mac[6];
1224 __le16 inner_vlan;
1225 union {
1226 struct {
1227 u8 reserved[12];
1228 u8 data[4];
1229 } v4;
1230 struct {
1231 u8 data[16];
1232 } v6;
1233 } ipaddr;
1234 __le16 flags;
1235 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1236 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1237 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1238 /* 0x0000 reserved */
1239 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1240 /* 0x0002 reserved */
1241 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1242 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1243 /* 0x0005 reserved */
1244 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1245 /* 0x0007 reserved */
1246 /* 0x0008 reserved */
1247 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1248 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1249 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1250 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1251
1252 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1253 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1254 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1255 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1256 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1257
1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1263 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1264
1265 __le32 tenant_id;
1266 u8 reserved[4];
1267 __le16 queue_number;
1268 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1269 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1270 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1271 u8 reserved2[14];
1272 /* response section */
1273 u8 allocation_result;
1274 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1275 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1276 u8 response_reserved[7];
1277 };
1278
1279 struct i40e_aqc_remove_cloud_filters_completion {
1280 __le16 perfect_ovlan_used;
1281 __le16 perfect_ovlan_free;
1282 __le16 vlan_used;
1283 __le16 vlan_free;
1284 __le32 addr_high;
1285 __le32 addr_low;
1286 };
1287
1288 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1289
1290 /* Add Mirror Rule (indirect or direct 0x0260)
1291 * Delete Mirror Rule (indirect or direct 0x0261)
1292 * note: some rule types (4,5) do not use an external buffer.
1293 * take care to set the flags correctly.
1294 */
1295 struct i40e_aqc_add_delete_mirror_rule {
1296 __le16 seid;
1297 __le16 rule_type;
1298 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1299 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1300 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1301 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1302 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1303 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1304 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1305 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1306 __le16 num_entries;
1307 __le16 destination; /* VSI for add, rule id for delete */
1308 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1309 __le32 addr_low;
1310 };
1311
1312 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1313
1314 struct i40e_aqc_add_delete_mirror_rule_completion {
1315 u8 reserved[2];
1316 __le16 rule_id; /* only used on add */
1317 __le16 mirror_rules_used;
1318 __le16 mirror_rules_free;
1319 __le32 addr_high;
1320 __le32 addr_low;
1321 };
1322
1323 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1324
1325 /* DCB 0x03xx*/
1326
1327 /* PFC Ignore (direct 0x0301)
1328 * the command and response use the same descriptor structure
1329 */
1330 struct i40e_aqc_pfc_ignore {
1331 u8 tc_bitmap;
1332 u8 command_flags; /* unused on response */
1333 #define I40E_AQC_PFC_IGNORE_SET 0x80
1334 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1335 u8 reserved[14];
1336 };
1337
1338 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1339
1340 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1341 * with no parameters
1342 */
1343
1344 /* TX scheduler 0x04xx */
1345
1346 /* Almost all the indirect commands use
1347 * this generic struct to pass the SEID in param0
1348 */
1349 struct i40e_aqc_tx_sched_ind {
1350 __le16 vsi_seid;
1351 u8 reserved[6];
1352 __le32 addr_high;
1353 __le32 addr_low;
1354 };
1355
1356 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1357
1358 /* Several commands respond with a set of queue set handles */
1359 struct i40e_aqc_qs_handles_resp {
1360 __le16 qs_handles[8];
1361 };
1362
1363 /* Configure VSI BW limits (direct 0x0400) */
1364 struct i40e_aqc_configure_vsi_bw_limit {
1365 __le16 vsi_seid;
1366 u8 reserved[2];
1367 __le16 credit;
1368 u8 reserved1[2];
1369 u8 max_credit; /* 0-3, limit = 2^max */
1370 u8 reserved2[7];
1371 };
1372
1373 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1374
1375 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1376 * responds with i40e_aqc_qs_handles_resp
1377 */
1378 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1379 u8 tc_valid_bits;
1380 u8 reserved[15];
1381 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1382
1383 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1384 __le16 tc_bw_max[2];
1385 u8 reserved1[28];
1386 };
1387
1388 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1389
1390 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1391 * responds with i40e_aqc_qs_handles_resp
1392 */
1393 struct i40e_aqc_configure_vsi_tc_bw_data {
1394 u8 tc_valid_bits;
1395 u8 reserved[3];
1396 u8 tc_bw_credits[8];
1397 u8 reserved1[4];
1398 __le16 qs_handles[8];
1399 };
1400
1401 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1402
1403 /* Query vsi bw configuration (indirect 0x0408) */
1404 struct i40e_aqc_query_vsi_bw_config_resp {
1405 u8 tc_valid_bits;
1406 u8 tc_suspended_bits;
1407 u8 reserved[14];
1408 __le16 qs_handles[8];
1409 u8 reserved1[4];
1410 __le16 port_bw_limit;
1411 u8 reserved2[2];
1412 u8 max_bw; /* 0-3, limit = 2^max */
1413 u8 reserved3[23];
1414 };
1415
1416 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1417
1418 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1419 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1420 u8 tc_valid_bits;
1421 u8 reserved[3];
1422 u8 share_credits[8];
1423 __le16 credits[8];
1424
1425 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1426 __le16 tc_bw_max[2];
1427 };
1428
1429 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1430
1431 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1432 struct i40e_aqc_configure_switching_comp_bw_limit {
1433 __le16 seid;
1434 u8 reserved[2];
1435 __le16 credit;
1436 u8 reserved1[2];
1437 u8 max_bw; /* 0-3, limit = 2^max */
1438 u8 reserved2[7];
1439 };
1440
1441 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1442
1443 /* Enable Physical Port ETS (indirect 0x0413)
1444 * Modify Physical Port ETS (indirect 0x0414)
1445 * Disable Physical Port ETS (indirect 0x0415)
1446 */
1447 struct i40e_aqc_configure_switching_comp_ets_data {
1448 u8 reserved[4];
1449 u8 tc_valid_bits;
1450 u8 seepage;
1451 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1452 u8 tc_strict_priority_flags;
1453 u8 reserved1[17];
1454 u8 tc_bw_share_credits[8];
1455 u8 reserved2[96];
1456 };
1457
1458 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1459
1460 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1461 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1462 u8 tc_valid_bits;
1463 u8 reserved[15];
1464 __le16 tc_bw_credit[8];
1465
1466 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1467 __le16 tc_bw_max[2];
1468 u8 reserved1[28];
1469 };
1470
1471 I40E_CHECK_STRUCT_LEN(0x40,
1472 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1473
1474 /* Configure Switching Component Bandwidth Allocation per Tc
1475 * (indirect 0x0417)
1476 */
1477 struct i40e_aqc_configure_switching_comp_bw_config_data {
1478 u8 tc_valid_bits;
1479 u8 reserved[2];
1480 u8 absolute_credits; /* bool */
1481 u8 tc_bw_share_credits[8];
1482 u8 reserved1[20];
1483 };
1484
1485 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1486
1487 /* Query Switching Component Configuration (indirect 0x0418) */
1488 struct i40e_aqc_query_switching_comp_ets_config_resp {
1489 u8 tc_valid_bits;
1490 u8 reserved[35];
1491 __le16 port_bw_limit;
1492 u8 reserved1[2];
1493 u8 tc_bw_max; /* 0-3, limit = 2^max */
1494 u8 reserved2[23];
1495 };
1496
1497 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1498
1499 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1500 struct i40e_aqc_query_port_ets_config_resp {
1501 u8 reserved[4];
1502 u8 tc_valid_bits;
1503 u8 reserved1;
1504 u8 tc_strict_priority_bits;
1505 u8 reserved2;
1506 u8 tc_bw_share_credits[8];
1507 __le16 tc_bw_limits[8];
1508
1509 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1510 __le16 tc_bw_max[2];
1511 u8 reserved3[32];
1512 };
1513
1514 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1515
1516 /* Query Switching Component Bandwidth Allocation per Traffic Type
1517 * (indirect 0x041A)
1518 */
1519 struct i40e_aqc_query_switching_comp_bw_config_resp {
1520 u8 tc_valid_bits;
1521 u8 reserved[2];
1522 u8 absolute_credits_enable; /* bool */
1523 u8 tc_bw_share_credits[8];
1524 __le16 tc_bw_limits[8];
1525
1526 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1527 __le16 tc_bw_max[2];
1528 };
1529
1530 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1531
1532 /* Suspend/resume port TX traffic
1533 * (direct 0x041B and 0x041C) uses the generic SEID struct
1534 */
1535
1536 /* Configure partition BW
1537 * (indirect 0x041D)
1538 */
1539 struct i40e_aqc_configure_partition_bw_data {
1540 __le16 pf_valid_bits;
1541 u8 min_bw[16]; /* guaranteed bandwidth */
1542 u8 max_bw[16]; /* bandwidth limit */
1543 };
1544
1545 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1546
1547 /* Get and set the active HMC resource profile and status.
1548 * (direct 0x0500) and (direct 0x0501)
1549 */
1550 struct i40e_aq_get_set_hmc_resource_profile {
1551 u8 pm_profile;
1552 u8 pe_vf_enabled;
1553 u8 reserved[14];
1554 };
1555
1556 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1557
1558 enum i40e_aq_hmc_profile {
1559 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1560 I40E_HMC_PROFILE_DEFAULT = 1,
1561 I40E_HMC_PROFILE_FAVOR_VF = 2,
1562 I40E_HMC_PROFILE_EQUAL = 3,
1563 };
1564
1565 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1566 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1567
1568 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1569
1570 /* set in param0 for get phy abilities to report qualified modules */
1571 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1572 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1573
1574 enum i40e_aq_phy_type {
1575 I40E_PHY_TYPE_SGMII = 0x0,
1576 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1577 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1578 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1579 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1580 I40E_PHY_TYPE_XAUI = 0x5,
1581 I40E_PHY_TYPE_XFI = 0x6,
1582 I40E_PHY_TYPE_SFI = 0x7,
1583 I40E_PHY_TYPE_XLAUI = 0x8,
1584 I40E_PHY_TYPE_XLPPI = 0x9,
1585 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1586 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1587 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1588 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1589 I40E_PHY_TYPE_100BASE_TX = 0x11,
1590 I40E_PHY_TYPE_1000BASE_T = 0x12,
1591 I40E_PHY_TYPE_10GBASE_T = 0x13,
1592 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1593 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1594 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1595 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1596 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1597 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1598 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1599 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1600 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1601 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1602 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1603 I40E_PHY_TYPE_MAX
1604 };
1605
1606 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1607 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1608 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1609 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1610 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1611
1612 enum i40e_aq_link_speed {
1613 I40E_LINK_SPEED_UNKNOWN = 0,
1614 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1615 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1616 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1617 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1618 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1619 };
1620
1621 struct i40e_aqc_module_desc {
1622 u8 oui[3];
1623 u8 reserved1;
1624 u8 part_number[16];
1625 u8 revision[4];
1626 u8 reserved2[8];
1627 };
1628
1629 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1630
1631 struct i40e_aq_get_phy_abilities_resp {
1632 __le32 phy_type; /* bitmap using the above enum for offsets */
1633 u8 link_speed; /* bitmap using the above enum bit patterns */
1634 u8 abilities;
1635 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1636 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1637 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1638 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1639 #define I40E_AQ_PHY_AN_ENABLED 0x10
1640 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1641 __le16 eee_capability;
1642 #define I40E_AQ_EEE_100BASE_TX 0x0002
1643 #define I40E_AQ_EEE_1000BASE_T 0x0004
1644 #define I40E_AQ_EEE_10GBASE_T 0x0008
1645 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1646 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1647 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1648 __le32 eeer_val;
1649 u8 d3_lpan;
1650 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1651 u8 reserved[3];
1652 u8 phy_id[4];
1653 u8 module_type[3];
1654 u8 qualified_module_count;
1655 #define I40E_AQ_PHY_MAX_QMS 16
1656 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1657 };
1658
1659 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1660
1661 /* Set PHY Config (direct 0x0601) */
1662 struct i40e_aq_set_phy_config { /* same bits as above in all */
1663 __le32 phy_type;
1664 u8 link_speed;
1665 u8 abilities;
1666 /* bits 0-2 use the values from get_phy_abilities_resp */
1667 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1668 #define I40E_AQ_PHY_ENABLE_AN 0x10
1669 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1670 __le16 eee_capability;
1671 __le32 eeer;
1672 u8 low_power_ctrl;
1673 u8 reserved[3];
1674 };
1675
1676 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1677
1678 /* Set MAC Config command data structure (direct 0x0603) */
1679 struct i40e_aq_set_mac_config {
1680 __le16 max_frame_size;
1681 u8 params;
1682 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1694 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1695 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1696 u8 tx_timer_priority; /* bitmap */
1697 __le16 tx_timer_value;
1698 __le16 fc_refresh_threshold;
1699 u8 reserved[8];
1700 };
1701
1702 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1703
1704 /* Restart Auto-Negotiation (direct 0x605) */
1705 struct i40e_aqc_set_link_restart_an {
1706 u8 command;
1707 #define I40E_AQ_PHY_RESTART_AN 0x02
1708 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1709 u8 reserved[15];
1710 };
1711
1712 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1713
1714 /* Get Link Status cmd & response data structure (direct 0x0607) */
1715 struct i40e_aqc_get_link_status {
1716 __le16 command_flags; /* only field set on command */
1717 #define I40E_AQ_LSE_MASK 0x3
1718 #define I40E_AQ_LSE_NOP 0x0
1719 #define I40E_AQ_LSE_DISABLE 0x2
1720 #define I40E_AQ_LSE_ENABLE 0x3
1721 /* only response uses this flag */
1722 #define I40E_AQ_LSE_IS_ENABLED 0x1
1723 u8 phy_type; /* i40e_aq_phy_type */
1724 u8 link_speed; /* i40e_aq_link_speed */
1725 u8 link_info;
1726 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1727 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1728 #define I40E_AQ_LINK_FAULT 0x02
1729 #define I40E_AQ_LINK_FAULT_TX 0x04
1730 #define I40E_AQ_LINK_FAULT_RX 0x08
1731 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1732 #define I40E_AQ_LINK_UP_PORT 0x20
1733 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1734 #define I40E_AQ_SIGNAL_DETECT 0x80
1735 u8 an_info;
1736 #define I40E_AQ_AN_COMPLETED 0x01
1737 #define I40E_AQ_LP_AN_ABILITY 0x02
1738 #define I40E_AQ_PD_FAULT 0x04
1739 #define I40E_AQ_FEC_EN 0x08
1740 #define I40E_AQ_PHY_LOW_POWER 0x10
1741 #define I40E_AQ_LINK_PAUSE_TX 0x20
1742 #define I40E_AQ_LINK_PAUSE_RX 0x40
1743 #define I40E_AQ_QUALIFIED_MODULE 0x80
1744 u8 ext_info;
1745 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1746 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1747 #define I40E_AQ_LINK_TX_SHIFT 0x02
1748 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1749 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1750 #define I40E_AQ_LINK_TX_DRAINED 0x01
1751 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1752 #define I40E_AQ_LINK_FORCED_40G 0x10
1753 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1754 __le16 max_frame_size;
1755 u8 config;
1756 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1757 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1758 u8 external_power_ability;
1759 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1760 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1761 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1762 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1763 u8 reserved[4];
1764 };
1765
1766 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1767
1768 /* Set event mask command (direct 0x613) */
1769 struct i40e_aqc_set_phy_int_mask {
1770 u8 reserved[8];
1771 __le16 event_mask;
1772 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1773 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1774 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1775 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1776 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1777 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1778 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1779 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1780 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1781 u8 reserved1[6];
1782 };
1783
1784 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1785
1786 /* Get Local AN advt register (direct 0x0614)
1787 * Set Local AN advt register (direct 0x0615)
1788 * Get Link Partner AN advt register (direct 0x0616)
1789 */
1790 struct i40e_aqc_an_advt_reg {
1791 __le32 local_an_reg0;
1792 __le16 local_an_reg1;
1793 u8 reserved[10];
1794 };
1795
1796 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1797
1798 /* Set Loopback mode (0x0618) */
1799 struct i40e_aqc_set_lb_mode {
1800 __le16 lb_mode;
1801 #define I40E_AQ_LB_PHY_LOCAL 0x01
1802 #define I40E_AQ_LB_PHY_REMOTE 0x02
1803 #define I40E_AQ_LB_MAC_LOCAL 0x04
1804 u8 reserved[14];
1805 };
1806
1807 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1808
1809 /* Set PHY Debug command (0x0622) */
1810 struct i40e_aqc_set_phy_debug {
1811 u8 command_flags;
1812 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1813 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1814 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1815 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1816 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1817 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1818 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1819 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1820 u8 reserved[15];
1821 };
1822
1823 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1824
1825 enum i40e_aq_phy_reg_type {
1826 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1827 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1828 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1829 };
1830
1831 /* Run PHY Activity (0x0626) */
1832 struct i40e_aqc_run_phy_activity {
1833 __le16 activity_id;
1834 u8 flags;
1835 u8 reserved1;
1836 __le32 control;
1837 __le32 data;
1838 u8 reserved2[4];
1839 };
1840
1841 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1842
1843 /* NVM Read command (indirect 0x0701)
1844 * NVM Erase commands (direct 0x0702)
1845 * NVM Update commands (indirect 0x0703)
1846 */
1847 struct i40e_aqc_nvm_update {
1848 u8 command_flags;
1849 #define I40E_AQ_NVM_LAST_CMD 0x01
1850 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1851 u8 module_pointer;
1852 __le16 length;
1853 __le32 offset;
1854 __le32 addr_high;
1855 __le32 addr_low;
1856 };
1857
1858 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1859
1860 /* NVM Config Read (indirect 0x0704) */
1861 struct i40e_aqc_nvm_config_read {
1862 __le16 cmd_flags;
1863 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1864 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1865 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1866 __le16 element_count;
1867 __le16 element_id; /* Feature/field ID */
1868 __le16 element_id_msw; /* MSWord of field ID */
1869 __le32 address_high;
1870 __le32 address_low;
1871 };
1872
1873 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1874
1875 /* NVM Config Write (indirect 0x0705) */
1876 struct i40e_aqc_nvm_config_write {
1877 __le16 cmd_flags;
1878 __le16 element_count;
1879 u8 reserved[4];
1880 __le32 address_high;
1881 __le32 address_low;
1882 };
1883
1884 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1885
1886 /* Used for 0x0704 as well as for 0x0705 commands */
1887 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1888 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1889 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1890 #define I40E_AQ_ANVM_FEATURE 0
1891 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1892 struct i40e_aqc_nvm_config_data_feature {
1893 __le16 feature_id;
1894 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1895 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1896 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1897 __le16 feature_options;
1898 __le16 feature_selection;
1899 };
1900
1901 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1902
1903 struct i40e_aqc_nvm_config_data_immediate_field {
1904 __le32 field_id;
1905 __le32 field_value;
1906 __le16 field_options;
1907 __le16 reserved;
1908 };
1909
1910 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1911
1912 /* OEM Post Update (indirect 0x0720)
1913 * no command data struct used
1914 */
1915 struct i40e_aqc_nvm_oem_post_update {
1916 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1917 u8 sel_data;
1918 u8 reserved[7];
1919 };
1920
1921 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1922
1923 struct i40e_aqc_nvm_oem_post_update_buffer {
1924 u8 str_len;
1925 u8 dev_addr;
1926 __le16 eeprom_addr;
1927 u8 data[36];
1928 };
1929
1930 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1931
1932 /* Send to PF command (indirect 0x0801) id is only used by PF
1933 * Send to VF command (indirect 0x0802) id is only used by PF
1934 * Send to Peer PF command (indirect 0x0803)
1935 */
1936 struct i40e_aqc_pf_vf_message {
1937 __le32 id;
1938 u8 reserved[4];
1939 __le32 addr_high;
1940 __le32 addr_low;
1941 };
1942
1943 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1944
1945 /* Alternate structure */
1946
1947 /* Direct write (direct 0x0900)
1948 * Direct read (direct 0x0902)
1949 */
1950 struct i40e_aqc_alternate_write {
1951 __le32 address0;
1952 __le32 data0;
1953 __le32 address1;
1954 __le32 data1;
1955 };
1956
1957 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1958
1959 /* Indirect write (indirect 0x0901)
1960 * Indirect read (indirect 0x0903)
1961 */
1962
1963 struct i40e_aqc_alternate_ind_write {
1964 __le32 address;
1965 __le32 length;
1966 __le32 addr_high;
1967 __le32 addr_low;
1968 };
1969
1970 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1971
1972 /* Done alternate write (direct 0x0904)
1973 * uses i40e_aq_desc
1974 */
1975 struct i40e_aqc_alternate_write_done {
1976 __le16 cmd_flags;
1977 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1978 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1979 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1980 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1981 u8 reserved[14];
1982 };
1983
1984 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1985
1986 /* Set OEM mode (direct 0x0905) */
1987 struct i40e_aqc_alternate_set_mode {
1988 __le32 mode;
1989 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1990 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1991 u8 reserved[12];
1992 };
1993
1994 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1995
1996 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1997
1998 /* async events 0x10xx */
1999
2000 /* Lan Queue Overflow Event (direct, 0x1001) */
2001 struct i40e_aqc_lan_overflow {
2002 __le32 prtdcb_rupto;
2003 __le32 otx_ctl;
2004 u8 reserved[8];
2005 };
2006
2007 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2008
2009 /* Get LLDP MIB (indirect 0x0A00) */
2010 struct i40e_aqc_lldp_get_mib {
2011 u8 type;
2012 u8 reserved1;
2013 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2014 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2015 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2016 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2017 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2018 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2019 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2020 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2021 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2022 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2023 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2024 __le16 local_len;
2025 __le16 remote_len;
2026 u8 reserved2[2];
2027 __le32 addr_high;
2028 __le32 addr_low;
2029 };
2030
2031 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2032
2033 /* Configure LLDP MIB Change Event (direct 0x0A01)
2034 * also used for the event (with type in the command field)
2035 */
2036 struct i40e_aqc_lldp_update_mib {
2037 u8 command;
2038 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2039 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2040 u8 reserved[7];
2041 __le32 addr_high;
2042 __le32 addr_low;
2043 };
2044
2045 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2046
2047 /* Add LLDP TLV (indirect 0x0A02)
2048 * Delete LLDP TLV (indirect 0x0A04)
2049 */
2050 struct i40e_aqc_lldp_add_tlv {
2051 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2052 u8 reserved1[1];
2053 __le16 len;
2054 u8 reserved2[4];
2055 __le32 addr_high;
2056 __le32 addr_low;
2057 };
2058
2059 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2060
2061 /* Update LLDP TLV (indirect 0x0A03) */
2062 struct i40e_aqc_lldp_update_tlv {
2063 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2064 u8 reserved;
2065 __le16 old_len;
2066 __le16 new_offset;
2067 __le16 new_len;
2068 __le32 addr_high;
2069 __le32 addr_low;
2070 };
2071
2072 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2073
2074 /* Stop LLDP (direct 0x0A05) */
2075 struct i40e_aqc_lldp_stop {
2076 u8 command;
2077 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2078 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2079 u8 reserved[15];
2080 };
2081
2082 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2083
2084 /* Start LLDP (direct 0x0A06) */
2085
2086 struct i40e_aqc_lldp_start {
2087 u8 command;
2088 #define I40E_AQ_LLDP_AGENT_START 0x1
2089 u8 reserved[15];
2090 };
2091
2092 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2093
2094 /* Apply MIB changes (0x0A07)
2095 * uses the generic struc as it contains no data
2096 */
2097
2098 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2099 struct i40e_aqc_add_udp_tunnel {
2100 __le16 udp_port;
2101 u8 reserved0[3];
2102 u8 protocol_type;
2103 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2104 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2105 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2106 u8 reserved1[10];
2107 };
2108
2109 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2110
2111 struct i40e_aqc_add_udp_tunnel_completion {
2112 __le16 udp_port;
2113 u8 filter_entry_index;
2114 u8 multiple_pfs;
2115 #define I40E_AQC_SINGLE_PF 0x0
2116 #define I40E_AQC_MULTIPLE_PFS 0x1
2117 u8 total_filters;
2118 u8 reserved[11];
2119 };
2120
2121 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2122
2123 /* remove UDP Tunnel command (0x0B01) */
2124 struct i40e_aqc_remove_udp_tunnel {
2125 u8 reserved[2];
2126 u8 index; /* 0 to 15 */
2127 u8 reserved2[13];
2128 };
2129
2130 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2131
2132 struct i40e_aqc_del_udp_tunnel_completion {
2133 __le16 udp_port;
2134 u8 index; /* 0 to 15 */
2135 u8 multiple_pfs;
2136 u8 total_filters_used;
2137 u8 reserved1[11];
2138 };
2139
2140 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2141
2142 struct i40e_aqc_get_set_rss_key {
2143 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2144 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2145 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2146 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2147 __le16 vsi_id;
2148 u8 reserved[6];
2149 __le32 addr_high;
2150 __le32 addr_low;
2151 };
2152
2153 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2154
2155 struct i40e_aqc_get_set_rss_key_data {
2156 u8 standard_rss_key[0x28];
2157 u8 extended_hash_key[0xc];
2158 };
2159
2160 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2161
2162 struct i40e_aqc_get_set_rss_lut {
2163 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2164 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2165 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2166 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2167 __le16 vsi_id;
2168 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2169 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2170 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2171
2172 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2173 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2174 __le16 flags;
2175 u8 reserved[4];
2176 __le32 addr_high;
2177 __le32 addr_low;
2178 };
2179
2180 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2181
2182 /* tunnel key structure 0x0B10 */
2183
2184 struct i40e_aqc_tunnel_key_structure_A0 {
2185 __le16 key1_off;
2186 __le16 key1_len;
2187 __le16 key2_off;
2188 __le16 key2_len;
2189 __le16 flags;
2190 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2191 /* response flags */
2192 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2193 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2194 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2195 u8 resreved[6];
2196 };
2197
2198 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2199
2200 struct i40e_aqc_tunnel_key_structure {
2201 u8 key1_off;
2202 u8 key2_off;
2203 u8 key1_len; /* 0 to 15 */
2204 u8 key2_len; /* 0 to 15 */
2205 u8 flags;
2206 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2207 /* response flags */
2208 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2209 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2210 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2211 u8 network_key_index;
2212 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2213 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2214 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2215 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2216 u8 reserved[10];
2217 };
2218
2219 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2220
2221 /* OEM mode commands (direct 0xFE0x) */
2222 struct i40e_aqc_oem_param_change {
2223 __le32 param_type;
2224 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2225 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2226 #define I40E_AQ_OEM_PARAM_MAC 2
2227 __le32 param_value1;
2228 __le16 param_value2;
2229 u8 reserved[6];
2230 };
2231
2232 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2233
2234 struct i40e_aqc_oem_state_change {
2235 __le32 state;
2236 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2237 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2238 u8 reserved[12];
2239 };
2240
2241 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2242
2243 /* Initialize OCSD (0xFE02, direct) */
2244 struct i40e_aqc_opc_oem_ocsd_initialize {
2245 u8 type_status;
2246 u8 reserved1[3];
2247 __le32 ocsd_memory_block_addr_high;
2248 __le32 ocsd_memory_block_addr_low;
2249 __le32 requested_update_interval;
2250 };
2251
2252 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2253
2254 /* Initialize OCBB (0xFE03, direct) */
2255 struct i40e_aqc_opc_oem_ocbb_initialize {
2256 u8 type_status;
2257 u8 reserved1[3];
2258 __le32 ocbb_memory_block_addr_high;
2259 __le32 ocbb_memory_block_addr_low;
2260 u8 reserved2[4];
2261 };
2262
2263 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2264
2265 /* debug commands */
2266
2267 /* get device id (0xFF00) uses the generic structure */
2268
2269 /* set test more (0xFF01, internal) */
2270
2271 struct i40e_acq_set_test_mode {
2272 u8 mode;
2273 #define I40E_AQ_TEST_PARTIAL 0
2274 #define I40E_AQ_TEST_FULL 1
2275 #define I40E_AQ_TEST_NVM 2
2276 u8 reserved[3];
2277 u8 command;
2278 #define I40E_AQ_TEST_OPEN 0
2279 #define I40E_AQ_TEST_CLOSE 1
2280 #define I40E_AQ_TEST_INC 2
2281 u8 reserved2[3];
2282 __le32 address_high;
2283 __le32 address_low;
2284 };
2285
2286 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2287
2288 /* Debug Read Register command (0xFF03)
2289 * Debug Write Register command (0xFF04)
2290 */
2291 struct i40e_aqc_debug_reg_read_write {
2292 __le32 reserved;
2293 __le32 address;
2294 __le32 value_high;
2295 __le32 value_low;
2296 };
2297
2298 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2299
2300 /* Scatter/gather Reg Read (indirect 0xFF05)
2301 * Scatter/gather Reg Write (indirect 0xFF06)
2302 */
2303
2304 /* i40e_aq_desc is used for the command */
2305 struct i40e_aqc_debug_reg_sg_element_data {
2306 __le32 address;
2307 __le32 value;
2308 };
2309
2310 /* Debug Modify register (direct 0xFF07) */
2311 struct i40e_aqc_debug_modify_reg {
2312 __le32 address;
2313 __le32 value;
2314 __le32 clear_mask;
2315 __le32 set_mask;
2316 };
2317
2318 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2319
2320 /* dump internal data (0xFF08, indirect) */
2321
2322 #define I40E_AQ_CLUSTER_ID_AUX 0
2323 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2324 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2325 #define I40E_AQ_CLUSTER_ID_HMC 3
2326 #define I40E_AQ_CLUSTER_ID_MAC0 4
2327 #define I40E_AQ_CLUSTER_ID_MAC1 5
2328 #define I40E_AQ_CLUSTER_ID_MAC2 6
2329 #define I40E_AQ_CLUSTER_ID_MAC3 7
2330 #define I40E_AQ_CLUSTER_ID_DCB 8
2331 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2332 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2333 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2334
2335 struct i40e_aqc_debug_dump_internals {
2336 u8 cluster_id;
2337 u8 table_id;
2338 __le16 data_size;
2339 __le32 idx;
2340 __le32 address_high;
2341 __le32 address_low;
2342 };
2343
2344 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2345
2346 struct i40e_aqc_debug_modify_internals {
2347 u8 cluster_id;
2348 u8 cluster_specific_params[7];
2349 __le32 address_high;
2350 __le32 address_low;
2351 };
2352
2353 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2354
2355 #endif /* _I40E_ADMINQ_CMD_H_ */
Linux kernel - Deliverables
This page took 0.103155 seconds and 6 git commands to generate.