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[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
29
30 #include "i40evf.h"
31 #include "i40e_prototype.h"
32
33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 u32 td_tag)
35 {
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41 }
42
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45 /**
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
49 **/
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
52 {
53 if (tx_buffer->skb) {
54 dev_kfree_skb_any(tx_buffer->skb);
55 if (dma_unmap_len(tx_buffer, len))
56 dma_unmap_single(ring->dev,
57 dma_unmap_addr(tx_buffer, dma),
58 dma_unmap_len(tx_buffer, len),
59 DMA_TO_DEVICE);
60 } else if (dma_unmap_len(tx_buffer, len)) {
61 dma_unmap_page(ring->dev,
62 dma_unmap_addr(tx_buffer, dma),
63 dma_unmap_len(tx_buffer, len),
64 DMA_TO_DEVICE);
65 }
66
67 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
68 kfree(tx_buffer->raw_buf);
69
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
74 }
75
76 /**
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
79 **/
80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81 {
82 unsigned long bi_size;
83 u16 i;
84
85 /* ring already cleared, nothing to do */
86 if (!tx_ring->tx_bi)
87 return;
88
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
95
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
98
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
101
102 if (!tx_ring->netdev)
103 return;
104
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
108 }
109
110 /**
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
113 *
114 * Free all transmit software resources
115 **/
116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117 {
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
121
122 if (tx_ring->desc) {
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
126 }
127 }
128
129 /**
130 * i40evf_get_tx_pending - how many Tx descriptors not processed
131 * @tx_ring: the ring of descriptors
132 * @in_sw: is tx_pending being checked in SW or HW
133 *
134 * Since there is no access to the ring head register
135 * in XL710, we need to use our local copies
136 **/
137 u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw)
138 {
139 u32 head, tail;
140
141 if (!in_sw)
142 head = i40e_get_head(ring);
143 else
144 head = ring->next_to_clean;
145 tail = readl(ring->tail);
146
147 if (head != tail)
148 return (head < tail) ?
149 tail - head : (tail + ring->count - head);
150
151 return 0;
152 }
153
154 #define WB_STRIDE 0x3
155
156 /**
157 * i40e_clean_tx_irq - Reclaim resources after transmit completes
158 * @vsi: the VSI we care about
159 * @tx_ring: Tx ring to clean
160 * @napi_budget: Used to determine if we are in netpoll
161 *
162 * Returns true if there's any budget left (e.g. the clean is finished)
163 **/
164 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
165 struct i40e_ring *tx_ring, int napi_budget)
166 {
167 u16 i = tx_ring->next_to_clean;
168 struct i40e_tx_buffer *tx_buf;
169 struct i40e_tx_desc *tx_head;
170 struct i40e_tx_desc *tx_desc;
171 unsigned int total_bytes = 0, total_packets = 0;
172 unsigned int budget = vsi->work_limit;
173
174 tx_buf = &tx_ring->tx_bi[i];
175 tx_desc = I40E_TX_DESC(tx_ring, i);
176 i -= tx_ring->count;
177
178 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
179
180 do {
181 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
182
183 /* if next_to_watch is not set then there is no work pending */
184 if (!eop_desc)
185 break;
186
187 /* prevent any other reads prior to eop_desc */
188 read_barrier_depends();
189
190 /* we have caught up to head, no work left to do */
191 if (tx_head == tx_desc)
192 break;
193
194 /* clear next_to_watch to prevent false hangs */
195 tx_buf->next_to_watch = NULL;
196
197 /* update the statistics for this packet */
198 total_bytes += tx_buf->bytecount;
199 total_packets += tx_buf->gso_segs;
200
201 /* free the skb */
202 napi_consume_skb(tx_buf->skb, napi_budget);
203
204 /* unmap skb header data */
205 dma_unmap_single(tx_ring->dev,
206 dma_unmap_addr(tx_buf, dma),
207 dma_unmap_len(tx_buf, len),
208 DMA_TO_DEVICE);
209
210 /* clear tx_buffer data */
211 tx_buf->skb = NULL;
212 dma_unmap_len_set(tx_buf, len, 0);
213
214 /* unmap remaining buffers */
215 while (tx_desc != eop_desc) {
216
217 tx_buf++;
218 tx_desc++;
219 i++;
220 if (unlikely(!i)) {
221 i -= tx_ring->count;
222 tx_buf = tx_ring->tx_bi;
223 tx_desc = I40E_TX_DESC(tx_ring, 0);
224 }
225
226 /* unmap any remaining paged data */
227 if (dma_unmap_len(tx_buf, len)) {
228 dma_unmap_page(tx_ring->dev,
229 dma_unmap_addr(tx_buf, dma),
230 dma_unmap_len(tx_buf, len),
231 DMA_TO_DEVICE);
232 dma_unmap_len_set(tx_buf, len, 0);
233 }
234 }
235
236 /* move us one more past the eop_desc for start of next pkt */
237 tx_buf++;
238 tx_desc++;
239 i++;
240 if (unlikely(!i)) {
241 i -= tx_ring->count;
242 tx_buf = tx_ring->tx_bi;
243 tx_desc = I40E_TX_DESC(tx_ring, 0);
244 }
245
246 prefetch(tx_desc);
247
248 /* update budget accounting */
249 budget--;
250 } while (likely(budget));
251
252 i += tx_ring->count;
253 tx_ring->next_to_clean = i;
254 u64_stats_update_begin(&tx_ring->syncp);
255 tx_ring->stats.bytes += total_bytes;
256 tx_ring->stats.packets += total_packets;
257 u64_stats_update_end(&tx_ring->syncp);
258 tx_ring->q_vector->tx.total_bytes += total_bytes;
259 tx_ring->q_vector->tx.total_packets += total_packets;
260
261 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
262 unsigned int j = 0;
263 /* check to see if there are < 4 descriptors
264 * waiting to be written back, then kick the hardware to force
265 * them to be written back in case we stay in NAPI.
266 * In this mode on X722 we do not enable Interrupt.
267 */
268 j = i40evf_get_tx_pending(tx_ring, false);
269
270 if (budget &&
271 ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
272 !test_bit(__I40E_DOWN, &vsi->state) &&
273 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
274 tx_ring->arm_wb = true;
275 }
276
277 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
278 tx_ring->queue_index),
279 total_packets, total_bytes);
280
281 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
282 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
283 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
284 /* Make sure that anybody stopping the queue after this
285 * sees the new next_to_clean.
286 */
287 smp_mb();
288 if (__netif_subqueue_stopped(tx_ring->netdev,
289 tx_ring->queue_index) &&
290 !test_bit(__I40E_DOWN, &vsi->state)) {
291 netif_wake_subqueue(tx_ring->netdev,
292 tx_ring->queue_index);
293 ++tx_ring->tx_stats.restart_queue;
294 }
295 }
296
297 return !!budget;
298 }
299
300 /**
301 * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
302 * @vsi: the VSI we care about
303 * @q_vector: the vector on which to enable writeback
304 *
305 **/
306 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
307 struct i40e_q_vector *q_vector)
308 {
309 u16 flags = q_vector->tx.ring[0].flags;
310 u32 val;
311
312 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
313 return;
314
315 if (q_vector->arm_wb_state)
316 return;
317
318 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
319 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
320
321 wr32(&vsi->back->hw,
322 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
323 vsi->base_vector - 1), val);
324 q_vector->arm_wb_state = true;
325 }
326
327 /**
328 * i40evf_force_wb - Issue SW Interrupt so HW does a wb
329 * @vsi: the VSI we care about
330 * @q_vector: the vector on which to force writeback
331 *
332 **/
333 void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
334 {
335 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
336 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
337 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
338 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
339 /* allow 00 to be written to the index */;
340
341 wr32(&vsi->back->hw,
342 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
343 val);
344 }
345
346 /**
347 * i40e_set_new_dynamic_itr - Find new ITR level
348 * @rc: structure containing ring performance data
349 *
350 * Returns true if ITR changed, false if not
351 *
352 * Stores a new ITR value based on packets and byte counts during
353 * the last interrupt. The advantage of per interrupt computation
354 * is faster updates and more accurate ITR for the current traffic
355 * pattern. Constants in this function were computed based on
356 * theoretical maximum wire speed and thresholds were set based on
357 * testing data as well as attempting to minimize response time
358 * while increasing bulk throughput.
359 **/
360 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
361 {
362 enum i40e_latency_range new_latency_range = rc->latency_range;
363 struct i40e_q_vector *qv = rc->ring->q_vector;
364 u32 new_itr = rc->itr;
365 int bytes_per_int;
366 int usecs;
367
368 if (rc->total_packets == 0 || !rc->itr)
369 return false;
370
371 /* simple throttlerate management
372 * 0-10MB/s lowest (50000 ints/s)
373 * 10-20MB/s low (20000 ints/s)
374 * 20-1249MB/s bulk (18000 ints/s)
375 * > 40000 Rx packets per second (8000 ints/s)
376 *
377 * The math works out because the divisor is in 10^(-6) which
378 * turns the bytes/us input value into MB/s values, but
379 * make sure to use usecs, as the register values written
380 * are in 2 usec increments in the ITR registers, and make sure
381 * to use the smoothed values that the countdown timer gives us.
382 */
383 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
384 bytes_per_int = rc->total_bytes / usecs;
385
386 switch (new_latency_range) {
387 case I40E_LOWEST_LATENCY:
388 if (bytes_per_int > 10)
389 new_latency_range = I40E_LOW_LATENCY;
390 break;
391 case I40E_LOW_LATENCY:
392 if (bytes_per_int > 20)
393 new_latency_range = I40E_BULK_LATENCY;
394 else if (bytes_per_int <= 10)
395 new_latency_range = I40E_LOWEST_LATENCY;
396 break;
397 case I40E_BULK_LATENCY:
398 case I40E_ULTRA_LATENCY:
399 default:
400 if (bytes_per_int <= 20)
401 new_latency_range = I40E_LOW_LATENCY;
402 break;
403 }
404
405 /* this is to adjust RX more aggressively when streaming small
406 * packets. The value of 40000 was picked as it is just beyond
407 * what the hardware can receive per second if in low latency
408 * mode.
409 */
410 #define RX_ULTRA_PACKET_RATE 40000
411
412 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
413 (&qv->rx == rc))
414 new_latency_range = I40E_ULTRA_LATENCY;
415
416 rc->latency_range = new_latency_range;
417
418 switch (new_latency_range) {
419 case I40E_LOWEST_LATENCY:
420 new_itr = I40E_ITR_50K;
421 break;
422 case I40E_LOW_LATENCY:
423 new_itr = I40E_ITR_20K;
424 break;
425 case I40E_BULK_LATENCY:
426 new_itr = I40E_ITR_18K;
427 break;
428 case I40E_ULTRA_LATENCY:
429 new_itr = I40E_ITR_8K;
430 break;
431 default:
432 break;
433 }
434
435 rc->total_bytes = 0;
436 rc->total_packets = 0;
437
438 if (new_itr != rc->itr) {
439 rc->itr = new_itr;
440 return true;
441 }
442
443 return false;
444 }
445
446 /**
447 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
448 * @tx_ring: the tx ring to set up
449 *
450 * Return 0 on success, negative on error
451 **/
452 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
453 {
454 struct device *dev = tx_ring->dev;
455 int bi_size;
456
457 if (!dev)
458 return -ENOMEM;
459
460 /* warn if we are about to overwrite the pointer */
461 WARN_ON(tx_ring->tx_bi);
462 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
463 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
464 if (!tx_ring->tx_bi)
465 goto err;
466
467 /* round up to nearest 4K */
468 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
469 /* add u32 for head writeback, align after this takes care of
470 * guaranteeing this is at least one cache line in size
471 */
472 tx_ring->size += sizeof(u32);
473 tx_ring->size = ALIGN(tx_ring->size, 4096);
474 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
475 &tx_ring->dma, GFP_KERNEL);
476 if (!tx_ring->desc) {
477 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
478 tx_ring->size);
479 goto err;
480 }
481
482 tx_ring->next_to_use = 0;
483 tx_ring->next_to_clean = 0;
484 return 0;
485
486 err:
487 kfree(tx_ring->tx_bi);
488 tx_ring->tx_bi = NULL;
489 return -ENOMEM;
490 }
491
492 /**
493 * i40evf_clean_rx_ring - Free Rx buffers
494 * @rx_ring: ring to be cleaned
495 **/
496 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
497 {
498 struct device *dev = rx_ring->dev;
499 struct i40e_rx_buffer *rx_bi;
500 unsigned long bi_size;
501 u16 i;
502
503 /* ring already cleared, nothing to do */
504 if (!rx_ring->rx_bi)
505 return;
506
507 if (ring_is_ps_enabled(rx_ring)) {
508 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
509
510 rx_bi = &rx_ring->rx_bi[0];
511 if (rx_bi->hdr_buf) {
512 dma_free_coherent(dev,
513 bufsz,
514 rx_bi->hdr_buf,
515 rx_bi->dma);
516 for (i = 0; i < rx_ring->count; i++) {
517 rx_bi = &rx_ring->rx_bi[i];
518 rx_bi->dma = 0;
519 rx_bi->hdr_buf = NULL;
520 }
521 }
522 }
523 /* Free all the Rx ring sk_buffs */
524 for (i = 0; i < rx_ring->count; i++) {
525 rx_bi = &rx_ring->rx_bi[i];
526 if (rx_bi->dma) {
527 dma_unmap_single(dev,
528 rx_bi->dma,
529 rx_ring->rx_buf_len,
530 DMA_FROM_DEVICE);
531 rx_bi->dma = 0;
532 }
533 if (rx_bi->skb) {
534 dev_kfree_skb(rx_bi->skb);
535 rx_bi->skb = NULL;
536 }
537 if (rx_bi->page) {
538 if (rx_bi->page_dma) {
539 dma_unmap_page(dev,
540 rx_bi->page_dma,
541 PAGE_SIZE,
542 DMA_FROM_DEVICE);
543 rx_bi->page_dma = 0;
544 }
545 __free_page(rx_bi->page);
546 rx_bi->page = NULL;
547 rx_bi->page_offset = 0;
548 }
549 }
550
551 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
552 memset(rx_ring->rx_bi, 0, bi_size);
553
554 /* Zero out the descriptor ring */
555 memset(rx_ring->desc, 0, rx_ring->size);
556
557 rx_ring->next_to_clean = 0;
558 rx_ring->next_to_use = 0;
559 }
560
561 /**
562 * i40evf_free_rx_resources - Free Rx resources
563 * @rx_ring: ring to clean the resources from
564 *
565 * Free all receive software resources
566 **/
567 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
568 {
569 i40evf_clean_rx_ring(rx_ring);
570 kfree(rx_ring->rx_bi);
571 rx_ring->rx_bi = NULL;
572
573 if (rx_ring->desc) {
574 dma_free_coherent(rx_ring->dev, rx_ring->size,
575 rx_ring->desc, rx_ring->dma);
576 rx_ring->desc = NULL;
577 }
578 }
579
580 /**
581 * i40evf_alloc_rx_headers - allocate rx header buffers
582 * @rx_ring: ring to alloc buffers
583 *
584 * Allocate rx header buffers for the entire ring. As these are static,
585 * this is only called when setting up a new ring.
586 **/
587 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
588 {
589 struct device *dev = rx_ring->dev;
590 struct i40e_rx_buffer *rx_bi;
591 dma_addr_t dma;
592 void *buffer;
593 int buf_size;
594 int i;
595
596 if (rx_ring->rx_bi[0].hdr_buf)
597 return;
598 /* Make sure the buffers don't cross cache line boundaries. */
599 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
600 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
601 &dma, GFP_KERNEL);
602 if (!buffer)
603 return;
604 for (i = 0; i < rx_ring->count; i++) {
605 rx_bi = &rx_ring->rx_bi[i];
606 rx_bi->dma = dma + (i * buf_size);
607 rx_bi->hdr_buf = buffer + (i * buf_size);
608 }
609 }
610
611 /**
612 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
613 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
614 *
615 * Returns 0 on success, negative on failure
616 **/
617 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
618 {
619 struct device *dev = rx_ring->dev;
620 int bi_size;
621
622 /* warn if we are about to overwrite the pointer */
623 WARN_ON(rx_ring->rx_bi);
624 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
625 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
626 if (!rx_ring->rx_bi)
627 goto err;
628
629 u64_stats_init(&rx_ring->syncp);
630
631 /* Round up to nearest 4K */
632 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
633 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
634 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
635 rx_ring->size = ALIGN(rx_ring->size, 4096);
636 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
637 &rx_ring->dma, GFP_KERNEL);
638
639 if (!rx_ring->desc) {
640 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
641 rx_ring->size);
642 goto err;
643 }
644
645 rx_ring->next_to_clean = 0;
646 rx_ring->next_to_use = 0;
647
648 return 0;
649 err:
650 kfree(rx_ring->rx_bi);
651 rx_ring->rx_bi = NULL;
652 return -ENOMEM;
653 }
654
655 /**
656 * i40e_release_rx_desc - Store the new tail and head values
657 * @rx_ring: ring to bump
658 * @val: new head index
659 **/
660 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
661 {
662 rx_ring->next_to_use = val;
663 /* Force memory writes to complete before letting h/w
664 * know there are new descriptors to fetch. (Only
665 * applicable for weak-ordered memory model archs,
666 * such as IA-64).
667 */
668 wmb();
669 writel(val, rx_ring->tail);
670 }
671
672 /**
673 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
674 * @rx_ring: ring to place buffers on
675 * @cleaned_count: number of buffers to replace
676 *
677 * Returns true if any errors on allocation
678 **/
679 bool i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
680 {
681 u16 i = rx_ring->next_to_use;
682 union i40e_rx_desc *rx_desc;
683 struct i40e_rx_buffer *bi;
684 const int current_node = numa_node_id();
685
686 /* do nothing if no valid netdev defined */
687 if (!rx_ring->netdev || !cleaned_count)
688 return false;
689
690 while (cleaned_count--) {
691 rx_desc = I40E_RX_DESC(rx_ring, i);
692 bi = &rx_ring->rx_bi[i];
693
694 if (bi->skb) /* desc is in use */
695 goto no_buffers;
696
697 /* If we've been moved to a different NUMA node, release the
698 * page so we can get a new one on the current node.
699 */
700 if (bi->page && page_to_nid(bi->page) != current_node) {
701 dma_unmap_page(rx_ring->dev,
702 bi->page_dma,
703 PAGE_SIZE,
704 DMA_FROM_DEVICE);
705 __free_page(bi->page);
706 bi->page = NULL;
707 bi->page_dma = 0;
708 rx_ring->rx_stats.realloc_count++;
709 } else if (bi->page) {
710 rx_ring->rx_stats.page_reuse_count++;
711 }
712
713 if (!bi->page) {
714 bi->page = alloc_page(GFP_ATOMIC);
715 if (!bi->page) {
716 rx_ring->rx_stats.alloc_page_failed++;
717 goto no_buffers;
718 }
719 bi->page_dma = dma_map_page(rx_ring->dev,
720 bi->page,
721 0,
722 PAGE_SIZE,
723 DMA_FROM_DEVICE);
724 if (dma_mapping_error(rx_ring->dev, bi->page_dma)) {
725 rx_ring->rx_stats.alloc_page_failed++;
726 __free_page(bi->page);
727 bi->page = NULL;
728 bi->page_dma = 0;
729 bi->page_offset = 0;
730 goto no_buffers;
731 }
732 bi->page_offset = 0;
733 }
734
735 /* Refresh the desc even if buffer_addrs didn't change
736 * because each write-back erases this info.
737 */
738 rx_desc->read.pkt_addr =
739 cpu_to_le64(bi->page_dma + bi->page_offset);
740 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
741 i++;
742 if (i == rx_ring->count)
743 i = 0;
744 }
745
746 if (rx_ring->next_to_use != i)
747 i40e_release_rx_desc(rx_ring, i);
748
749 return false;
750
751 no_buffers:
752 if (rx_ring->next_to_use != i)
753 i40e_release_rx_desc(rx_ring, i);
754
755 /* make sure to come back via polling to try again after
756 * allocation failure
757 */
758 return true;
759 }
760
761 /**
762 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
763 * @rx_ring: ring to place buffers on
764 * @cleaned_count: number of buffers to replace
765 *
766 * Returns true if any errors on allocation
767 **/
768 bool i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
769 {
770 u16 i = rx_ring->next_to_use;
771 union i40e_rx_desc *rx_desc;
772 struct i40e_rx_buffer *bi;
773 struct sk_buff *skb;
774
775 /* do nothing if no valid netdev defined */
776 if (!rx_ring->netdev || !cleaned_count)
777 return false;
778
779 while (cleaned_count--) {
780 rx_desc = I40E_RX_DESC(rx_ring, i);
781 bi = &rx_ring->rx_bi[i];
782 skb = bi->skb;
783
784 if (!skb) {
785 skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
786 rx_ring->rx_buf_len,
787 GFP_ATOMIC |
788 __GFP_NOWARN);
789 if (!skb) {
790 rx_ring->rx_stats.alloc_buff_failed++;
791 goto no_buffers;
792 }
793 /* initialize queue mapping */
794 skb_record_rx_queue(skb, rx_ring->queue_index);
795 bi->skb = skb;
796 }
797
798 if (!bi->dma) {
799 bi->dma = dma_map_single(rx_ring->dev,
800 skb->data,
801 rx_ring->rx_buf_len,
802 DMA_FROM_DEVICE);
803 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
804 rx_ring->rx_stats.alloc_buff_failed++;
805 bi->dma = 0;
806 dev_kfree_skb(bi->skb);
807 bi->skb = NULL;
808 goto no_buffers;
809 }
810 }
811
812 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
813 rx_desc->read.hdr_addr = 0;
814 i++;
815 if (i == rx_ring->count)
816 i = 0;
817 }
818
819 if (rx_ring->next_to_use != i)
820 i40e_release_rx_desc(rx_ring, i);
821
822 return false;
823
824 no_buffers:
825 if (rx_ring->next_to_use != i)
826 i40e_release_rx_desc(rx_ring, i);
827
828 /* make sure to come back via polling to try again after
829 * allocation failure
830 */
831 return true;
832 }
833
834 /**
835 * i40e_receive_skb - Send a completed packet up the stack
836 * @rx_ring: rx ring in play
837 * @skb: packet to send up
838 * @vlan_tag: vlan tag for packet
839 **/
840 static void i40e_receive_skb(struct i40e_ring *rx_ring,
841 struct sk_buff *skb, u16 vlan_tag)
842 {
843 struct i40e_q_vector *q_vector = rx_ring->q_vector;
844
845 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
846 (vlan_tag & VLAN_VID_MASK))
847 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
848
849 napi_gro_receive(&q_vector->napi, skb);
850 }
851
852 /**
853 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
854 * @vsi: the VSI we care about
855 * @skb: skb currently being received and modified
856 * @rx_status: status value of last descriptor in packet
857 * @rx_error: error value of last descriptor in packet
858 * @rx_ptype: ptype value of last descriptor in packet
859 **/
860 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
861 struct sk_buff *skb,
862 u32 rx_status,
863 u32 rx_error,
864 u16 rx_ptype)
865 {
866 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
867 bool ipv4, ipv6, ipv4_tunnel, ipv6_tunnel;
868
869 skb->ip_summed = CHECKSUM_NONE;
870
871 /* Rx csum enabled and ip headers found? */
872 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
873 return;
874
875 /* did the hardware decode the packet and checksum? */
876 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
877 return;
878
879 /* both known and outer_ip must be set for the below code to work */
880 if (!(decoded.known && decoded.outer_ip))
881 return;
882
883 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
884 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
885 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
886 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
887
888 if (ipv4 &&
889 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
890 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
891 goto checksum_fail;
892
893 /* likely incorrect csum if alternate IP extension headers found */
894 if (ipv6 &&
895 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
896 /* don't increment checksum err here, non-fatal err */
897 return;
898
899 /* there was some L4 error, count error and punt packet to the stack */
900 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
901 goto checksum_fail;
902
903 /* handle packets that were not able to be checksummed due
904 * to arrival speed, in this case the stack can compute
905 * the csum.
906 */
907 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
908 return;
909
910 /* The hardware supported by this driver does not validate outer
911 * checksums for tunneled VXLAN or GENEVE frames. I don't agree
912 * with it but the specification states that you "MAY validate", it
913 * doesn't make it a hard requirement so if we have validated the
914 * inner checksum report CHECKSUM_UNNECESSARY.
915 */
916
917 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
918 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
919 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
920 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
921
922 skb->ip_summed = CHECKSUM_UNNECESSARY;
923 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
924
925 return;
926
927 checksum_fail:
928 vsi->back->hw_csum_rx_error++;
929 }
930
931 /**
932 * i40e_ptype_to_htype - get a hash type
933 * @ptype: the ptype value from the descriptor
934 *
935 * Returns a hash type to be used by skb_set_hash
936 **/
937 static inline enum pkt_hash_types i40e_ptype_to_htype(u8 ptype)
938 {
939 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
940
941 if (!decoded.known)
942 return PKT_HASH_TYPE_NONE;
943
944 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
945 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
946 return PKT_HASH_TYPE_L4;
947 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
948 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
949 return PKT_HASH_TYPE_L3;
950 else
951 return PKT_HASH_TYPE_L2;
952 }
953
954 /**
955 * i40e_rx_hash - set the hash value in the skb
956 * @ring: descriptor ring
957 * @rx_desc: specific descriptor
958 **/
959 static inline void i40e_rx_hash(struct i40e_ring *ring,
960 union i40e_rx_desc *rx_desc,
961 struct sk_buff *skb,
962 u8 rx_ptype)
963 {
964 u32 hash;
965 const __le64 rss_mask =
966 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
967 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
968
969 if (ring->netdev->features & NETIF_F_RXHASH)
970 return;
971
972 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
973 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
974 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
975 }
976 }
977
978 /**
979 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
980 * @rx_ring: rx ring to clean
981 * @budget: how many cleans we're allowed
982 *
983 * Returns true if there's any budget left (e.g. the clean is finished)
984 **/
985 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, const int budget)
986 {
987 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
988 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
989 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
990 struct i40e_vsi *vsi = rx_ring->vsi;
991 u16 i = rx_ring->next_to_clean;
992 union i40e_rx_desc *rx_desc;
993 u32 rx_error, rx_status;
994 bool failure = false;
995 u8 rx_ptype;
996 u64 qword;
997 u32 copysize;
998
999 do {
1000 struct i40e_rx_buffer *rx_bi;
1001 struct sk_buff *skb;
1002 u16 vlan_tag;
1003 /* return some buffers to hardware, one at a time is too slow */
1004 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1005 failure = failure ||
1006 i40evf_alloc_rx_buffers_ps(rx_ring,
1007 cleaned_count);
1008 cleaned_count = 0;
1009 }
1010
1011 i = rx_ring->next_to_clean;
1012 rx_desc = I40E_RX_DESC(rx_ring, i);
1013 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1014 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1015 I40E_RXD_QW1_STATUS_SHIFT;
1016
1017 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1018 break;
1019
1020 /* This memory barrier is needed to keep us from reading
1021 * any other fields out of the rx_desc until we know the
1022 * DD bit is set.
1023 */
1024 dma_rmb();
1025 /* sync header buffer for reading */
1026 dma_sync_single_range_for_cpu(rx_ring->dev,
1027 rx_ring->rx_bi[0].dma,
1028 i * rx_ring->rx_hdr_len,
1029 rx_ring->rx_hdr_len,
1030 DMA_FROM_DEVICE);
1031 rx_bi = &rx_ring->rx_bi[i];
1032 skb = rx_bi->skb;
1033 if (likely(!skb)) {
1034 skb = __netdev_alloc_skb_ip_align(rx_ring->netdev,
1035 rx_ring->rx_hdr_len,
1036 GFP_ATOMIC |
1037 __GFP_NOWARN);
1038 if (!skb) {
1039 rx_ring->rx_stats.alloc_buff_failed++;
1040 failure = true;
1041 break;
1042 }
1043
1044 /* initialize queue mapping */
1045 skb_record_rx_queue(skb, rx_ring->queue_index);
1046 /* we are reusing so sync this buffer for CPU use */
1047 dma_sync_single_range_for_cpu(rx_ring->dev,
1048 rx_ring->rx_bi[0].dma,
1049 i * rx_ring->rx_hdr_len,
1050 rx_ring->rx_hdr_len,
1051 DMA_FROM_DEVICE);
1052 }
1053 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1054 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1055 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1056 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1057 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1058 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1059
1060 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1061 I40E_RXD_QW1_ERROR_SHIFT;
1062 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1063 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1064
1065 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1066 I40E_RXD_QW1_PTYPE_SHIFT;
1067 /* sync half-page for reading */
1068 dma_sync_single_range_for_cpu(rx_ring->dev,
1069 rx_bi->page_dma,
1070 rx_bi->page_offset,
1071 PAGE_SIZE / 2,
1072 DMA_FROM_DEVICE);
1073 prefetch(page_address(rx_bi->page) + rx_bi->page_offset);
1074 rx_bi->skb = NULL;
1075 cleaned_count++;
1076 copysize = 0;
1077 if (rx_hbo || rx_sph) {
1078 int len;
1079
1080 if (rx_hbo)
1081 len = I40E_RX_HDR_SIZE;
1082 else
1083 len = rx_header_len;
1084 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1085 } else if (skb->len == 0) {
1086 int len;
1087 unsigned char *va = page_address(rx_bi->page) +
1088 rx_bi->page_offset;
1089
1090 len = min(rx_packet_len, rx_ring->rx_hdr_len);
1091 memcpy(__skb_put(skb, len), va, len);
1092 copysize = len;
1093 rx_packet_len -= len;
1094 }
1095 /* Get the rest of the data if this was a header split */
1096 if (rx_packet_len) {
1097 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1098 rx_bi->page,
1099 rx_bi->page_offset + copysize,
1100 rx_packet_len, I40E_RXBUFFER_2048);
1101
1102 /* If the page count is more than 2, then both halves
1103 * of the page are used and we need to free it. Do it
1104 * here instead of in the alloc code. Otherwise one
1105 * of the half-pages might be released between now and
1106 * then, and we wouldn't know which one to use.
1107 * Don't call get_page and free_page since those are
1108 * both expensive atomic operations that just change
1109 * the refcount in opposite directions. Just give the
1110 * page to the stack; he can have our refcount.
1111 */
1112 if (page_count(rx_bi->page) > 2) {
1113 dma_unmap_page(rx_ring->dev,
1114 rx_bi->page_dma,
1115 PAGE_SIZE,
1116 DMA_FROM_DEVICE);
1117 rx_bi->page = NULL;
1118 rx_bi->page_dma = 0;
1119 rx_ring->rx_stats.realloc_count++;
1120 } else {
1121 get_page(rx_bi->page);
1122 /* switch to the other half-page here; the
1123 * allocation code programs the right addr
1124 * into HW. If we haven't used this half-page,
1125 * the address won't be changed, and HW can
1126 * just use it next time through.
1127 */
1128 rx_bi->page_offset ^= PAGE_SIZE / 2;
1129 }
1130
1131 }
1132 I40E_RX_INCREMENT(rx_ring, i);
1133
1134 if (unlikely(
1135 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1136 struct i40e_rx_buffer *next_buffer;
1137
1138 next_buffer = &rx_ring->rx_bi[i];
1139 next_buffer->skb = skb;
1140 rx_ring->rx_stats.non_eop_descs++;
1141 continue;
1142 }
1143
1144 /* ERR_MASK will only have valid bits if EOP set */
1145 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1146 dev_kfree_skb_any(skb);
1147 continue;
1148 }
1149
1150 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1151
1152 /* probably a little skewed due to removing CRC */
1153 total_rx_bytes += skb->len;
1154 total_rx_packets++;
1155
1156 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1157
1158 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1159
1160 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1161 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1162 : 0;
1163 #ifdef I40E_FCOE
1164 if (unlikely(
1165 i40e_rx_is_fcoe(rx_ptype) &&
1166 !i40e_fcoe_handle_offload(rx_ring, rx_desc, skb))) {
1167 dev_kfree_skb_any(skb);
1168 continue;
1169 }
1170 #endif
1171 i40e_receive_skb(rx_ring, skb, vlan_tag);
1172
1173 rx_desc->wb.qword1.status_error_len = 0;
1174
1175 } while (likely(total_rx_packets < budget));
1176
1177 u64_stats_update_begin(&rx_ring->syncp);
1178 rx_ring->stats.packets += total_rx_packets;
1179 rx_ring->stats.bytes += total_rx_bytes;
1180 u64_stats_update_end(&rx_ring->syncp);
1181 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1182 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1183
1184 return failure ? budget : total_rx_packets;
1185 }
1186
1187 /**
1188 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1189 * @rx_ring: rx ring to clean
1190 * @budget: how many cleans we're allowed
1191 *
1192 * Returns number of packets cleaned
1193 **/
1194 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1195 {
1196 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1197 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1198 struct i40e_vsi *vsi = rx_ring->vsi;
1199 union i40e_rx_desc *rx_desc;
1200 u32 rx_error, rx_status;
1201 u16 rx_packet_len;
1202 bool failure = false;
1203 u8 rx_ptype;
1204 u64 qword;
1205 u16 i;
1206
1207 do {
1208 struct i40e_rx_buffer *rx_bi;
1209 struct sk_buff *skb;
1210 u16 vlan_tag;
1211 /* return some buffers to hardware, one at a time is too slow */
1212 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1213 failure = failure ||
1214 i40evf_alloc_rx_buffers_1buf(rx_ring,
1215 cleaned_count);
1216 cleaned_count = 0;
1217 }
1218
1219 i = rx_ring->next_to_clean;
1220 rx_desc = I40E_RX_DESC(rx_ring, i);
1221 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1222 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1223 I40E_RXD_QW1_STATUS_SHIFT;
1224
1225 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1226 break;
1227
1228 /* This memory barrier is needed to keep us from reading
1229 * any other fields out of the rx_desc until we know the
1230 * DD bit is set.
1231 */
1232 dma_rmb();
1233
1234 rx_bi = &rx_ring->rx_bi[i];
1235 skb = rx_bi->skb;
1236 prefetch(skb->data);
1237
1238 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1239 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1240
1241 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1242 I40E_RXD_QW1_ERROR_SHIFT;
1243 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1244
1245 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1246 I40E_RXD_QW1_PTYPE_SHIFT;
1247 rx_bi->skb = NULL;
1248 cleaned_count++;
1249
1250 /* Get the header and possibly the whole packet
1251 * If this is an skb from previous receive dma will be 0
1252 */
1253 skb_put(skb, rx_packet_len);
1254 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1255 DMA_FROM_DEVICE);
1256 rx_bi->dma = 0;
1257
1258 I40E_RX_INCREMENT(rx_ring, i);
1259
1260 if (unlikely(
1261 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1262 rx_ring->rx_stats.non_eop_descs++;
1263 continue;
1264 }
1265
1266 /* ERR_MASK will only have valid bits if EOP set */
1267 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1268 dev_kfree_skb_any(skb);
1269 continue;
1270 }
1271
1272 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1273 /* probably a little skewed due to removing CRC */
1274 total_rx_bytes += skb->len;
1275 total_rx_packets++;
1276
1277 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1278
1279 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1280
1281 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1282 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1283 : 0;
1284 i40e_receive_skb(rx_ring, skb, vlan_tag);
1285
1286 rx_desc->wb.qword1.status_error_len = 0;
1287 } while (likely(total_rx_packets < budget));
1288
1289 u64_stats_update_begin(&rx_ring->syncp);
1290 rx_ring->stats.packets += total_rx_packets;
1291 rx_ring->stats.bytes += total_rx_bytes;
1292 u64_stats_update_end(&rx_ring->syncp);
1293 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1294 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1295
1296 return failure ? budget : total_rx_packets;
1297 }
1298
1299 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1300 {
1301 u32 val;
1302
1303 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1304 /* Don't clear PBA because that can cause lost interrupts that
1305 * came in while we were cleaning/polling
1306 */
1307 (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1308 (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1309
1310 return val;
1311 }
1312
1313 /* a small macro to shorten up some long lines */
1314 #define INTREG I40E_VFINT_DYN_CTLN1
1315
1316 /**
1317 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1318 * @vsi: the VSI we care about
1319 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1320 *
1321 **/
1322 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1323 struct i40e_q_vector *q_vector)
1324 {
1325 struct i40e_hw *hw = &vsi->back->hw;
1326 bool rx = false, tx = false;
1327 u32 rxval, txval;
1328 int vector;
1329
1330 vector = (q_vector->v_idx + vsi->base_vector);
1331
1332 /* avoid dynamic calculation if in countdown mode OR if
1333 * all dynamic is disabled
1334 */
1335 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1336
1337 if (q_vector->itr_countdown > 0 ||
1338 (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1339 !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1340 goto enable_int;
1341 }
1342
1343 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1344 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1345 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1346 }
1347
1348 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1349 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1350 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1351 }
1352
1353 if (rx || tx) {
1354 /* get the higher of the two ITR adjustments and
1355 * use the same value for both ITR registers
1356 * when in adaptive mode (Rx and/or Tx)
1357 */
1358 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1359
1360 q_vector->tx.itr = q_vector->rx.itr = itr;
1361 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1362 tx = true;
1363 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1364 rx = true;
1365 }
1366
1367 /* only need to enable the interrupt once, but need
1368 * to possibly update both ITR values
1369 */
1370 if (rx) {
1371 /* set the INTENA_MSK_MASK so that this first write
1372 * won't actually enable the interrupt, instead just
1373 * updating the ITR (it's bit 31 PF and VF)
1374 */
1375 rxval |= BIT(31);
1376 /* don't check _DOWN because interrupt isn't being enabled */
1377 wr32(hw, INTREG(vector - 1), rxval);
1378 }
1379
1380 enable_int:
1381 if (!test_bit(__I40E_DOWN, &vsi->state))
1382 wr32(hw, INTREG(vector - 1), txval);
1383
1384 if (q_vector->itr_countdown)
1385 q_vector->itr_countdown--;
1386 else
1387 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1388 }
1389
1390 /**
1391 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1392 * @napi: napi struct with our devices info in it
1393 * @budget: amount of work driver is allowed to do this pass, in packets
1394 *
1395 * This function will clean all queues associated with a q_vector.
1396 *
1397 * Returns the amount of work done
1398 **/
1399 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1400 {
1401 struct i40e_q_vector *q_vector =
1402 container_of(napi, struct i40e_q_vector, napi);
1403 struct i40e_vsi *vsi = q_vector->vsi;
1404 struct i40e_ring *ring;
1405 bool clean_complete = true;
1406 bool arm_wb = false;
1407 int budget_per_ring;
1408 int work_done = 0;
1409
1410 if (test_bit(__I40E_DOWN, &vsi->state)) {
1411 napi_complete(napi);
1412 return 0;
1413 }
1414
1415 /* Since the actual Tx work is minimal, we can give the Tx a larger
1416 * budget and be more aggressive about cleaning up the Tx descriptors.
1417 */
1418 i40e_for_each_ring(ring, q_vector->tx) {
1419 if (!i40e_clean_tx_irq(vsi, ring, budget)) {
1420 clean_complete = false;
1421 continue;
1422 }
1423 arm_wb |= ring->arm_wb;
1424 ring->arm_wb = false;
1425 }
1426
1427 /* Handle case where we are called by netpoll with a budget of 0 */
1428 if (budget <= 0)
1429 goto tx_only;
1430
1431 /* We attempt to distribute budget to each Rx queue fairly, but don't
1432 * allow the budget to go below 1 because that would exit polling early.
1433 */
1434 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1435
1436 i40e_for_each_ring(ring, q_vector->rx) {
1437 int cleaned;
1438
1439 if (ring_is_ps_enabled(ring))
1440 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1441 else
1442 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1443
1444 work_done += cleaned;
1445 /* if we clean as many as budgeted, we must not be done */
1446 if (cleaned >= budget_per_ring)
1447 clean_complete = false;
1448 }
1449
1450 /* If work not completed, return budget and polling will return */
1451 if (!clean_complete) {
1452 tx_only:
1453 if (arm_wb) {
1454 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1455 i40e_enable_wb_on_itr(vsi, q_vector);
1456 }
1457 return budget;
1458 }
1459
1460 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1461 q_vector->arm_wb_state = false;
1462
1463 /* Work is done so exit the polling mode and re-enable the interrupt */
1464 napi_complete_done(napi, work_done);
1465 i40e_update_enable_itr(vsi, q_vector);
1466 return 0;
1467 }
1468
1469 /**
1470 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1471 * @skb: send buffer
1472 * @tx_ring: ring to send buffer on
1473 * @flags: the tx flags to be set
1474 *
1475 * Checks the skb and set up correspondingly several generic transmit flags
1476 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1477 *
1478 * Returns error code indicate the frame should be dropped upon error and the
1479 * otherwise returns 0 to indicate the flags has been set properly.
1480 **/
1481 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1482 struct i40e_ring *tx_ring,
1483 u32 *flags)
1484 {
1485 __be16 protocol = skb->protocol;
1486 u32 tx_flags = 0;
1487
1488 if (protocol == htons(ETH_P_8021Q) &&
1489 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1490 /* When HW VLAN acceleration is turned off by the user the
1491 * stack sets the protocol to 8021q so that the driver
1492 * can take any steps required to support the SW only
1493 * VLAN handling. In our case the driver doesn't need
1494 * to take any further steps so just set the protocol
1495 * to the encapsulated ethertype.
1496 */
1497 skb->protocol = vlan_get_protocol(skb);
1498 goto out;
1499 }
1500
1501 /* if we have a HW VLAN tag being added, default to the HW one */
1502 if (skb_vlan_tag_present(skb)) {
1503 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1504 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1505 /* else if it is a SW VLAN, check the next protocol and store the tag */
1506 } else if (protocol == htons(ETH_P_8021Q)) {
1507 struct vlan_hdr *vhdr, _vhdr;
1508
1509 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1510 if (!vhdr)
1511 return -EINVAL;
1512
1513 protocol = vhdr->h_vlan_encapsulated_proto;
1514 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1515 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1516 }
1517
1518 out:
1519 *flags = tx_flags;
1520 return 0;
1521 }
1522
1523 /**
1524 * i40e_tso - set up the tso context descriptor
1525 * @skb: ptr to the skb we're sending
1526 * @hdr_len: ptr to the size of the packet header
1527 * @cd_type_cmd_tso_mss: Quad Word 1
1528 *
1529 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1530 **/
1531 static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1532 {
1533 u64 cd_cmd, cd_tso_len, cd_mss;
1534 union {
1535 struct iphdr *v4;
1536 struct ipv6hdr *v6;
1537 unsigned char *hdr;
1538 } ip;
1539 union {
1540 struct tcphdr *tcp;
1541 struct udphdr *udp;
1542 unsigned char *hdr;
1543 } l4;
1544 u32 paylen, l4_offset;
1545 int err;
1546
1547 if (skb->ip_summed != CHECKSUM_PARTIAL)
1548 return 0;
1549
1550 if (!skb_is_gso(skb))
1551 return 0;
1552
1553 err = skb_cow_head(skb, 0);
1554 if (err < 0)
1555 return err;
1556
1557 ip.hdr = skb_network_header(skb);
1558 l4.hdr = skb_transport_header(skb);
1559
1560 /* initialize outer IP header fields */
1561 if (ip.v4->version == 4) {
1562 ip.v4->tot_len = 0;
1563 ip.v4->check = 0;
1564 } else {
1565 ip.v6->payload_len = 0;
1566 }
1567
1568 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1569 SKB_GSO_IPIP |
1570 SKB_GSO_SIT |
1571 SKB_GSO_UDP_TUNNEL |
1572 SKB_GSO_UDP_TUNNEL_CSUM)) {
1573 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) {
1574 /* determine offset of outer transport header */
1575 l4_offset = l4.hdr - skb->data;
1576
1577 /* remove payload length from outer checksum */
1578 paylen = skb->len - l4_offset;
1579 csum_replace_by_diff(&l4.udp->check, htonl(paylen));
1580 }
1581
1582 /* reset pointers to inner headers */
1583 ip.hdr = skb_inner_network_header(skb);
1584 l4.hdr = skb_inner_transport_header(skb);
1585
1586 /* initialize inner IP header fields */
1587 if (ip.v4->version == 4) {
1588 ip.v4->tot_len = 0;
1589 ip.v4->check = 0;
1590 } else {
1591 ip.v6->payload_len = 0;
1592 }
1593 }
1594
1595 /* determine offset of inner transport header */
1596 l4_offset = l4.hdr - skb->data;
1597
1598 /* remove payload length from inner checksum */
1599 paylen = skb->len - l4_offset;
1600 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
1601
1602 /* compute length of segmentation header */
1603 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1604
1605 /* find the field values */
1606 cd_cmd = I40E_TX_CTX_DESC_TSO;
1607 cd_tso_len = skb->len - *hdr_len;
1608 cd_mss = skb_shinfo(skb)->gso_size;
1609 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1610 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1611 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1612 return 1;
1613 }
1614
1615 /**
1616 * i40e_tx_enable_csum - Enable Tx checksum offloads
1617 * @skb: send buffer
1618 * @tx_flags: pointer to Tx flags currently set
1619 * @td_cmd: Tx descriptor command bits to set
1620 * @td_offset: Tx descriptor header offsets to set
1621 * @tx_ring: Tx descriptor ring
1622 * @cd_tunneling: ptr to context desc bits
1623 **/
1624 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1625 u32 *td_cmd, u32 *td_offset,
1626 struct i40e_ring *tx_ring,
1627 u32 *cd_tunneling)
1628 {
1629 union {
1630 struct iphdr *v4;
1631 struct ipv6hdr *v6;
1632 unsigned char *hdr;
1633 } ip;
1634 union {
1635 struct tcphdr *tcp;
1636 struct udphdr *udp;
1637 unsigned char *hdr;
1638 } l4;
1639 unsigned char *exthdr;
1640 u32 offset, cmd = 0;
1641 __be16 frag_off;
1642 u8 l4_proto = 0;
1643
1644 if (skb->ip_summed != CHECKSUM_PARTIAL)
1645 return 0;
1646
1647 ip.hdr = skb_network_header(skb);
1648 l4.hdr = skb_transport_header(skb);
1649
1650 /* compute outer L2 header size */
1651 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1652
1653 if (skb->encapsulation) {
1654 u32 tunnel = 0;
1655 /* define outer network header type */
1656 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1657 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1658 I40E_TX_CTX_EXT_IP_IPV4 :
1659 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1660
1661 l4_proto = ip.v4->protocol;
1662 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1663 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
1664
1665 exthdr = ip.hdr + sizeof(*ip.v6);
1666 l4_proto = ip.v6->nexthdr;
1667 if (l4.hdr != exthdr)
1668 ipv6_skip_exthdr(skb, exthdr - skb->data,
1669 &l4_proto, &frag_off);
1670 }
1671
1672 /* define outer transport */
1673 switch (l4_proto) {
1674 case IPPROTO_UDP:
1675 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
1676 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1677 break;
1678 case IPPROTO_GRE:
1679 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
1680 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1681 break;
1682 case IPPROTO_IPIP:
1683 case IPPROTO_IPV6:
1684 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1685 l4.hdr = skb_inner_network_header(skb);
1686 break;
1687 default:
1688 if (*tx_flags & I40E_TX_FLAGS_TSO)
1689 return -1;
1690
1691 skb_checksum_help(skb);
1692 return 0;
1693 }
1694
1695 /* compute outer L3 header size */
1696 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
1697 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
1698
1699 /* switch IP header pointer from outer to inner header */
1700 ip.hdr = skb_inner_network_header(skb);
1701
1702 /* compute tunnel header size */
1703 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
1704 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1705
1706 /* indicate if we need to offload outer UDP header */
1707 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
1708 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
1709 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1710
1711 /* record tunnel offload values */
1712 *cd_tunneling |= tunnel;
1713
1714 /* switch L4 header pointer from outer to inner */
1715 l4.hdr = skb_inner_transport_header(skb);
1716 l4_proto = 0;
1717
1718 /* reset type as we transition from outer to inner headers */
1719 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
1720 if (ip.v4->version == 4)
1721 *tx_flags |= I40E_TX_FLAGS_IPV4;
1722 if (ip.v6->version == 6)
1723 *tx_flags |= I40E_TX_FLAGS_IPV6;
1724 }
1725
1726 /* Enable IP checksum offloads */
1727 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1728 l4_proto = ip.v4->protocol;
1729 /* the stack computes the IP header already, the only time we
1730 * need the hardware to recompute it is in the case of TSO.
1731 */
1732 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1733 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
1734 I40E_TX_DESC_CMD_IIPT_IPV4;
1735 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1736 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1737
1738 exthdr = ip.hdr + sizeof(*ip.v6);
1739 l4_proto = ip.v6->nexthdr;
1740 if (l4.hdr != exthdr)
1741 ipv6_skip_exthdr(skb, exthdr - skb->data,
1742 &l4_proto, &frag_off);
1743 }
1744
1745 /* compute inner L3 header size */
1746 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1747
1748 /* Enable L4 checksum offloads */
1749 switch (l4_proto) {
1750 case IPPROTO_TCP:
1751 /* enable checksum offloads */
1752 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1753 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1754 break;
1755 case IPPROTO_SCTP:
1756 /* enable SCTP checksum offload */
1757 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1758 offset |= (sizeof(struct sctphdr) >> 2) <<
1759 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1760 break;
1761 case IPPROTO_UDP:
1762 /* enable UDP checksum offload */
1763 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1764 offset |= (sizeof(struct udphdr) >> 2) <<
1765 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1766 break;
1767 default:
1768 if (*tx_flags & I40E_TX_FLAGS_TSO)
1769 return -1;
1770 skb_checksum_help(skb);
1771 return 0;
1772 }
1773
1774 *td_cmd |= cmd;
1775 *td_offset |= offset;
1776
1777 return 1;
1778 }
1779
1780 /**
1781 * i40e_create_tx_ctx Build the Tx context descriptor
1782 * @tx_ring: ring to create the descriptor on
1783 * @cd_type_cmd_tso_mss: Quad Word 1
1784 * @cd_tunneling: Quad Word 0 - bits 0-31
1785 * @cd_l2tag2: Quad Word 0 - bits 32-63
1786 **/
1787 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1788 const u64 cd_type_cmd_tso_mss,
1789 const u32 cd_tunneling, const u32 cd_l2tag2)
1790 {
1791 struct i40e_tx_context_desc *context_desc;
1792 int i = tx_ring->next_to_use;
1793
1794 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1795 !cd_tunneling && !cd_l2tag2)
1796 return;
1797
1798 /* grab the next descriptor */
1799 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1800
1801 i++;
1802 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1803
1804 /* cpu_to_le32 and assign to struct fields */
1805 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1806 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1807 context_desc->rsvd = cpu_to_le16(0);
1808 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1809 }
1810
1811 /**
1812 * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet
1813 * @skb: send buffer
1814 *
1815 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
1816 * and so we need to figure out the cases where we need to linearize the skb.
1817 *
1818 * For TSO we need to count the TSO header and segment payload separately.
1819 * As such we need to check cases where we have 7 fragments or more as we
1820 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
1821 * the segment payload in the first descriptor, and another 7 for the
1822 * fragments.
1823 **/
1824 bool __i40evf_chk_linearize(struct sk_buff *skb)
1825 {
1826 const struct skb_frag_struct *frag, *stale;
1827 int nr_frags, sum;
1828
1829 /* no need to check if number of frags is less than 7 */
1830 nr_frags = skb_shinfo(skb)->nr_frags;
1831 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
1832 return false;
1833
1834 /* We need to walk through the list and validate that each group
1835 * of 6 fragments totals at least gso_size. However we don't need
1836 * to perform such validation on the last 6 since the last 6 cannot
1837 * inherit any data from a descriptor after them.
1838 */
1839 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
1840 frag = &skb_shinfo(skb)->frags[0];
1841
1842 /* Initialize size to the negative value of gso_size minus 1. We
1843 * use this as the worst case scenerio in which the frag ahead
1844 * of us only provides one byte which is why we are limited to 6
1845 * descriptors for a single transmit as the header and previous
1846 * fragment are already consuming 2 descriptors.
1847 */
1848 sum = 1 - skb_shinfo(skb)->gso_size;
1849
1850 /* Add size of frags 0 through 4 to create our initial sum */
1851 sum += skb_frag_size(frag++);
1852 sum += skb_frag_size(frag++);
1853 sum += skb_frag_size(frag++);
1854 sum += skb_frag_size(frag++);
1855 sum += skb_frag_size(frag++);
1856
1857 /* Walk through fragments adding latest fragment, testing it, and
1858 * then removing stale fragments from the sum.
1859 */
1860 stale = &skb_shinfo(skb)->frags[0];
1861 for (;;) {
1862 sum += skb_frag_size(frag++);
1863
1864 /* if sum is negative we failed to make sufficient progress */
1865 if (sum < 0)
1866 return true;
1867
1868 /* use pre-decrement to avoid processing last fragment */
1869 if (!--nr_frags)
1870 break;
1871
1872 sum -= skb_frag_size(stale++);
1873 }
1874
1875 return false;
1876 }
1877
1878 /**
1879 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1880 * @tx_ring: the ring to be checked
1881 * @size: the size buffer we want to assure is available
1882 *
1883 * Returns -EBUSY if a stop is needed, else 0
1884 **/
1885 int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1886 {
1887 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1888 /* Memory barrier before checking head and tail */
1889 smp_mb();
1890
1891 /* Check again in a case another CPU has just made room available. */
1892 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1893 return -EBUSY;
1894
1895 /* A reprieve! - use start_queue because it doesn't call schedule */
1896 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1897 ++tx_ring->tx_stats.restart_queue;
1898 return 0;
1899 }
1900
1901 /**
1902 * i40evf_tx_map - Build the Tx descriptor
1903 * @tx_ring: ring to send buffer on
1904 * @skb: send buffer
1905 * @first: first buffer info buffer to use
1906 * @tx_flags: collected send information
1907 * @hdr_len: size of the packet header
1908 * @td_cmd: the command field in the descriptor
1909 * @td_offset: offset for checksum or crc
1910 **/
1911 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1912 struct i40e_tx_buffer *first, u32 tx_flags,
1913 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1914 {
1915 unsigned int data_len = skb->data_len;
1916 unsigned int size = skb_headlen(skb);
1917 struct skb_frag_struct *frag;
1918 struct i40e_tx_buffer *tx_bi;
1919 struct i40e_tx_desc *tx_desc;
1920 u16 i = tx_ring->next_to_use;
1921 u32 td_tag = 0;
1922 dma_addr_t dma;
1923 u16 gso_segs;
1924 u16 desc_count = 0;
1925 bool tail_bump = true;
1926 bool do_rs = false;
1927
1928 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1929 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1930 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1931 I40E_TX_FLAGS_VLAN_SHIFT;
1932 }
1933
1934 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1935 gso_segs = skb_shinfo(skb)->gso_segs;
1936 else
1937 gso_segs = 1;
1938
1939 /* multiply data chunks by size of headers */
1940 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1941 first->gso_segs = gso_segs;
1942 first->skb = skb;
1943 first->tx_flags = tx_flags;
1944
1945 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1946
1947 tx_desc = I40E_TX_DESC(tx_ring, i);
1948 tx_bi = first;
1949
1950 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1951 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
1952
1953 if (dma_mapping_error(tx_ring->dev, dma))
1954 goto dma_error;
1955
1956 /* record length, and DMA address */
1957 dma_unmap_len_set(tx_bi, len, size);
1958 dma_unmap_addr_set(tx_bi, dma, dma);
1959
1960 /* align size to end of page */
1961 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
1962 tx_desc->buffer_addr = cpu_to_le64(dma);
1963
1964 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1965 tx_desc->cmd_type_offset_bsz =
1966 build_ctob(td_cmd, td_offset,
1967 max_data, td_tag);
1968
1969 tx_desc++;
1970 i++;
1971 desc_count++;
1972
1973 if (i == tx_ring->count) {
1974 tx_desc = I40E_TX_DESC(tx_ring, 0);
1975 i = 0;
1976 }
1977
1978 dma += max_data;
1979 size -= max_data;
1980
1981 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
1982 tx_desc->buffer_addr = cpu_to_le64(dma);
1983 }
1984
1985 if (likely(!data_len))
1986 break;
1987
1988 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1989 size, td_tag);
1990
1991 tx_desc++;
1992 i++;
1993 desc_count++;
1994
1995 if (i == tx_ring->count) {
1996 tx_desc = I40E_TX_DESC(tx_ring, 0);
1997 i = 0;
1998 }
1999
2000 size = skb_frag_size(frag);
2001 data_len -= size;
2002
2003 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2004 DMA_TO_DEVICE);
2005
2006 tx_bi = &tx_ring->tx_bi[i];
2007 }
2008
2009 /* set next_to_watch value indicating a packet is present */
2010 first->next_to_watch = tx_desc;
2011
2012 i++;
2013 if (i == tx_ring->count)
2014 i = 0;
2015
2016 tx_ring->next_to_use = i;
2017
2018 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2019 tx_ring->queue_index),
2020 first->bytecount);
2021 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2022
2023 /* Algorithm to optimize tail and RS bit setting:
2024 * if xmit_more is supported
2025 * if xmit_more is true
2026 * do not update tail and do not mark RS bit.
2027 * if xmit_more is false and last xmit_more was false
2028 * if every packet spanned less than 4 desc
2029 * then set RS bit on 4th packet and update tail
2030 * on every packet
2031 * else
2032 * update tail and set RS bit on every packet.
2033 * if xmit_more is false and last_xmit_more was true
2034 * update tail and set RS bit.
2035 *
2036 * Optimization: wmb to be issued only in case of tail update.
2037 * Also optimize the Descriptor WB path for RS bit with the same
2038 * algorithm.
2039 *
2040 * Note: If there are less than 4 packets
2041 * pending and interrupts were disabled the service task will
2042 * trigger a force WB.
2043 */
2044 if (skb->xmit_more &&
2045 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2046 tx_ring->queue_index))) {
2047 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2048 tail_bump = false;
2049 } else if (!skb->xmit_more &&
2050 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2051 tx_ring->queue_index)) &&
2052 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2053 (tx_ring->packet_stride < WB_STRIDE) &&
2054 (desc_count < WB_STRIDE)) {
2055 tx_ring->packet_stride++;
2056 } else {
2057 tx_ring->packet_stride = 0;
2058 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2059 do_rs = true;
2060 }
2061 if (do_rs)
2062 tx_ring->packet_stride = 0;
2063
2064 tx_desc->cmd_type_offset_bsz =
2065 build_ctob(td_cmd, td_offset, size, td_tag) |
2066 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2067 I40E_TX_DESC_CMD_EOP) <<
2068 I40E_TXD_QW1_CMD_SHIFT);
2069
2070 /* notify HW of packet */
2071 if (!tail_bump)
2072 prefetchw(tx_desc + 1);
2073
2074 if (tail_bump) {
2075 /* Force memory writes to complete before letting h/w
2076 * know there are new descriptors to fetch. (Only
2077 * applicable for weak-ordered memory model archs,
2078 * such as IA-64).
2079 */
2080 wmb();
2081 writel(i, tx_ring->tail);
2082 }
2083
2084 return;
2085
2086 dma_error:
2087 dev_info(tx_ring->dev, "TX DMA map failed\n");
2088
2089 /* clear dma mappings for failed tx_bi map */
2090 for (;;) {
2091 tx_bi = &tx_ring->tx_bi[i];
2092 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2093 if (tx_bi == first)
2094 break;
2095 if (i == 0)
2096 i = tx_ring->count;
2097 i--;
2098 }
2099
2100 tx_ring->next_to_use = i;
2101 }
2102
2103 /**
2104 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2105 * @skb: send buffer
2106 * @tx_ring: ring to send buffer on
2107 *
2108 * Returns NETDEV_TX_OK if sent, else an error code
2109 **/
2110 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2111 struct i40e_ring *tx_ring)
2112 {
2113 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2114 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2115 struct i40e_tx_buffer *first;
2116 u32 td_offset = 0;
2117 u32 tx_flags = 0;
2118 __be16 protocol;
2119 u32 td_cmd = 0;
2120 u8 hdr_len = 0;
2121 int tso, count;
2122
2123 /* prefetch the data, we'll need it later */
2124 prefetch(skb->data);
2125
2126 count = i40e_xmit_descriptor_count(skb);
2127 if (i40e_chk_linearize(skb, count)) {
2128 if (__skb_linearize(skb))
2129 goto out_drop;
2130 count = i40e_txd_use_count(skb->len);
2131 tx_ring->tx_stats.tx_linearize++;
2132 }
2133
2134 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2135 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2136 * + 4 desc gap to avoid the cache line where head is,
2137 * + 1 desc for context descriptor,
2138 * otherwise try next time
2139 */
2140 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2141 tx_ring->tx_stats.tx_busy++;
2142 return NETDEV_TX_BUSY;
2143 }
2144
2145 /* prepare the xmit flags */
2146 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2147 goto out_drop;
2148
2149 /* obtain protocol of skb */
2150 protocol = vlan_get_protocol(skb);
2151
2152 /* record the location of the first descriptor for this packet */
2153 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2154
2155 /* setup IPv4/IPv6 offloads */
2156 if (protocol == htons(ETH_P_IP))
2157 tx_flags |= I40E_TX_FLAGS_IPV4;
2158 else if (protocol == htons(ETH_P_IPV6))
2159 tx_flags |= I40E_TX_FLAGS_IPV6;
2160
2161 tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss);
2162
2163 if (tso < 0)
2164 goto out_drop;
2165 else if (tso)
2166 tx_flags |= I40E_TX_FLAGS_TSO;
2167
2168 /* Always offload the checksum, since it's in the data descriptor */
2169 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2170 tx_ring, &cd_tunneling);
2171 if (tso < 0)
2172 goto out_drop;
2173
2174 skb_tx_timestamp(skb);
2175
2176 /* always enable CRC insertion offload */
2177 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2178
2179 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2180 cd_tunneling, cd_l2tag2);
2181
2182 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2183 td_cmd, td_offset);
2184
2185 return NETDEV_TX_OK;
2186
2187 out_drop:
2188 dev_kfree_skb_any(skb);
2189 return NETDEV_TX_OK;
2190 }
2191
2192 /**
2193 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2194 * @skb: send buffer
2195 * @netdev: network interface device structure
2196 *
2197 * Returns NETDEV_TX_OK if sent, else an error code
2198 **/
2199 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2200 {
2201 struct i40evf_adapter *adapter = netdev_priv(netdev);
2202 struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2203
2204 /* hardware can't handle really short frames, hardware padding works
2205 * beyond this point
2206 */
2207 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2208 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2209 return NETDEV_TX_OK;
2210 skb->len = I40E_MIN_TX_LEN;
2211 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2212 }
2213
2214 return i40e_xmit_frame_ring(skb, tx_ring);
2215 }
Linux kernel - Deliverables
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