1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
31 #include "i40e_prototype.h"
33 static inline __le64
build_ctob(u32 td_cmd
, u32 td_offset
, unsigned int size
,
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA
|
37 ((u64
)td_cmd
<< I40E_TXD_QW1_CMD_SHIFT
) |
38 ((u64
)td_offset
<< I40E_TXD_QW1_OFFSET_SHIFT
) |
39 ((u64
)size
<< I40E_TXD_QW1_TX_BUF_SZ_SHIFT
) |
40 ((u64
)td_tag
<< I40E_TXD_QW1_L2TAG1_SHIFT
));
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring
*ring
,
51 struct i40e_tx_buffer
*tx_buffer
)
54 if (tx_buffer
->tx_flags
& I40E_TX_FLAGS_FD_SB
)
55 kfree(tx_buffer
->raw_buf
);
57 dev_kfree_skb_any(tx_buffer
->skb
);
59 if (dma_unmap_len(tx_buffer
, len
))
60 dma_unmap_single(ring
->dev
,
61 dma_unmap_addr(tx_buffer
, dma
),
62 dma_unmap_len(tx_buffer
, len
),
64 } else if (dma_unmap_len(tx_buffer
, len
)) {
65 dma_unmap_page(ring
->dev
,
66 dma_unmap_addr(tx_buffer
, dma
),
67 dma_unmap_len(tx_buffer
, len
),
70 tx_buffer
->next_to_watch
= NULL
;
71 tx_buffer
->skb
= NULL
;
72 dma_unmap_len_set(tx_buffer
, len
, 0);
73 /* tx_buffer must be completely set up in the transmit path */
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
80 void i40evf_clean_tx_ring(struct i40e_ring
*tx_ring
)
82 unsigned long bi_size
;
85 /* ring already cleared, nothing to do */
89 /* Free all the Tx ring sk_buffs */
90 for (i
= 0; i
< tx_ring
->count
; i
++)
91 i40e_unmap_and_free_tx_resource(tx_ring
, &tx_ring
->tx_bi
[i
]);
93 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
94 memset(tx_ring
->tx_bi
, 0, bi_size
);
96 /* Zero out the descriptor ring */
97 memset(tx_ring
->desc
, 0, tx_ring
->size
);
99 tx_ring
->next_to_use
= 0;
100 tx_ring
->next_to_clean
= 0;
102 if (!tx_ring
->netdev
)
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring
->netdev
,
107 tx_ring
->queue_index
));
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
114 * Free all transmit software resources
116 void i40evf_free_tx_resources(struct i40e_ring
*tx_ring
)
118 i40evf_clean_tx_ring(tx_ring
);
119 kfree(tx_ring
->tx_bi
);
120 tx_ring
->tx_bi
= NULL
;
123 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
124 tx_ring
->desc
, tx_ring
->dma
);
125 tx_ring
->desc
= NULL
;
130 * i40e_get_head - Retrieve head from head writeback
131 * @tx_ring: tx ring to fetch head of
133 * Returns value of Tx ring head based on value stored
134 * in head write-back location
136 static inline u32
i40e_get_head(struct i40e_ring
*tx_ring
)
138 void *head
= (struct i40e_tx_desc
*)tx_ring
->desc
+ tx_ring
->count
;
140 return le32_to_cpu(*(volatile __le32
*)head
);
144 * i40e_get_tx_pending - how many tx descriptors not processed
145 * @tx_ring: the ring of descriptors
147 * Since there is no access to the ring head register
148 * in XL710, we need to use our local copies
150 static u32
i40e_get_tx_pending(struct i40e_ring
*ring
)
154 head
= i40e_get_head(ring
);
155 tail
= readl(ring
->tail
);
158 return (head
< tail
) ?
159 tail
- head
: (tail
+ ring
->count
- head
);
165 * i40e_check_tx_hang - Is there a hang in the Tx queue
166 * @tx_ring: the ring of descriptors
168 static bool i40e_check_tx_hang(struct i40e_ring
*tx_ring
)
170 u32 tx_done
= tx_ring
->stats
.packets
;
171 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
172 u32 tx_pending
= i40e_get_tx_pending(tx_ring
);
175 clear_check_for_tx_hang(tx_ring
);
177 /* Check for a hung queue, but be thorough. This verifies
178 * that a transmit has been completed since the previous
179 * check AND there is at least one packet pending. The
180 * ARMED bit is set to indicate a potential hang. The
181 * bit is cleared if a pause frame is received to remove
182 * false hang detection due to PFC or 802.3x frames. By
183 * requiring this to fail twice we avoid races with
184 * PFC clearing the ARMED bit and conditions where we
185 * run the check_tx_hang logic with a transmit completion
186 * pending but without time to complete it yet.
188 if ((tx_done_old
== tx_done
) && tx_pending
) {
189 /* make sure it is true for two checks in a row */
190 ret
= test_and_set_bit(__I40E_HANG_CHECK_ARMED
,
192 } else if (tx_done_old
== tx_done
&&
193 (tx_pending
< I40E_MIN_DESC_PENDING
) && (tx_pending
> 0)) {
194 /* update completed stats and disarm the hang check */
195 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
196 clear_bit(__I40E_HANG_CHECK_ARMED
, &tx_ring
->state
);
202 #define WB_STRIDE 0x3
205 * i40e_clean_tx_irq - Reclaim resources after transmit completes
206 * @tx_ring: tx ring to clean
207 * @budget: how many cleans we're allowed
209 * Returns true if there's any budget left (e.g. the clean is finished)
211 static bool i40e_clean_tx_irq(struct i40e_ring
*tx_ring
, int budget
)
213 u16 i
= tx_ring
->next_to_clean
;
214 struct i40e_tx_buffer
*tx_buf
;
215 struct i40e_tx_desc
*tx_head
;
216 struct i40e_tx_desc
*tx_desc
;
217 unsigned int total_packets
= 0;
218 unsigned int total_bytes
= 0;
220 tx_buf
= &tx_ring
->tx_bi
[i
];
221 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
224 tx_head
= I40E_TX_DESC(tx_ring
, i40e_get_head(tx_ring
));
227 struct i40e_tx_desc
*eop_desc
= tx_buf
->next_to_watch
;
229 /* if next_to_watch is not set then there is no work pending */
233 /* prevent any other reads prior to eop_desc */
234 read_barrier_depends();
236 /* we have caught up to head, no work left to do */
237 if (tx_head
== tx_desc
)
240 /* clear next_to_watch to prevent false hangs */
241 tx_buf
->next_to_watch
= NULL
;
243 /* update the statistics for this packet */
244 total_bytes
+= tx_buf
->bytecount
;
245 total_packets
+= tx_buf
->gso_segs
;
248 dev_kfree_skb_any(tx_buf
->skb
);
250 /* unmap skb header data */
251 dma_unmap_single(tx_ring
->dev
,
252 dma_unmap_addr(tx_buf
, dma
),
253 dma_unmap_len(tx_buf
, len
),
256 /* clear tx_buffer data */
258 dma_unmap_len_set(tx_buf
, len
, 0);
260 /* unmap remaining buffers */
261 while (tx_desc
!= eop_desc
) {
268 tx_buf
= tx_ring
->tx_bi
;
269 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
272 /* unmap any remaining paged data */
273 if (dma_unmap_len(tx_buf
, len
)) {
274 dma_unmap_page(tx_ring
->dev
,
275 dma_unmap_addr(tx_buf
, dma
),
276 dma_unmap_len(tx_buf
, len
),
278 dma_unmap_len_set(tx_buf
, len
, 0);
282 /* move us one more past the eop_desc for start of next pkt */
288 tx_buf
= tx_ring
->tx_bi
;
289 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
292 /* update budget accounting */
294 } while (likely(budget
));
297 tx_ring
->next_to_clean
= i
;
298 u64_stats_update_begin(&tx_ring
->syncp
);
299 tx_ring
->stats
.bytes
+= total_bytes
;
300 tx_ring
->stats
.packets
+= total_packets
;
301 u64_stats_update_end(&tx_ring
->syncp
);
302 tx_ring
->q_vector
->tx
.total_bytes
+= total_bytes
;
303 tx_ring
->q_vector
->tx
.total_packets
+= total_packets
;
306 !((i
& WB_STRIDE
) == WB_STRIDE
) &&
307 !test_bit(__I40E_DOWN
, &tx_ring
->vsi
->state
) &&
308 (I40E_DESC_UNUSED(tx_ring
) != tx_ring
->count
))
309 tx_ring
->arm_wb
= true;
311 tx_ring
->arm_wb
= false;
313 if (check_for_tx_hang(tx_ring
) && i40e_check_tx_hang(tx_ring
)) {
314 /* schedule immediate reset if we believe we hung */
315 dev_info(tx_ring
->dev
, "Detected Tx Unit Hang\n"
318 " next_to_use <%x>\n"
319 " next_to_clean <%x>\n",
321 tx_ring
->queue_index
,
322 tx_ring
->next_to_use
, i
);
323 dev_info(tx_ring
->dev
, "tx_bi[next_to_clean]\n"
324 " time_stamp <%lx>\n"
326 tx_ring
->tx_bi
[i
].time_stamp
, jiffies
);
328 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
330 dev_info(tx_ring
->dev
,
331 "tx hang detected on queue %d, resetting adapter\n",
332 tx_ring
->queue_index
);
334 tx_ring
->netdev
->netdev_ops
->ndo_tx_timeout(tx_ring
->netdev
);
336 /* the adapter is about to reset, no point in enabling stuff */
340 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring
->netdev
,
341 tx_ring
->queue_index
),
342 total_packets
, total_bytes
);
344 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
345 if (unlikely(total_packets
&& netif_carrier_ok(tx_ring
->netdev
) &&
346 (I40E_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
347 /* Make sure that anybody stopping the queue after this
348 * sees the new next_to_clean.
351 if (__netif_subqueue_stopped(tx_ring
->netdev
,
352 tx_ring
->queue_index
) &&
353 !test_bit(__I40E_DOWN
, &tx_ring
->vsi
->state
)) {
354 netif_wake_subqueue(tx_ring
->netdev
,
355 tx_ring
->queue_index
);
356 ++tx_ring
->tx_stats
.restart_queue
;
364 * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
365 * @vsi: the VSI we care about
366 * @q_vector: the vector on which to force writeback
369 static void i40e_force_wb(struct i40e_vsi
*vsi
, struct i40e_q_vector
*q_vector
)
371 u32 val
= I40E_VFINT_DYN_CTLN_INTENA_MASK
|
372 I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK
|
373 I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK
;
374 /* allow 00 to be written to the index */
377 I40E_VFINT_DYN_CTLN1(q_vector
->v_idx
+ vsi
->base_vector
- 1),
382 * i40e_set_new_dynamic_itr - Find new ITR level
383 * @rc: structure containing ring performance data
385 * Stores a new ITR value based on packets and byte counts during
386 * the last interrupt. The advantage of per interrupt computation
387 * is faster updates and more accurate ITR for the current traffic
388 * pattern. Constants in this function were computed based on
389 * theoretical maximum wire speed and thresholds were set based on
390 * testing data as well as attempting to minimize response time
391 * while increasing bulk throughput.
393 static void i40e_set_new_dynamic_itr(struct i40e_ring_container
*rc
)
395 enum i40e_latency_range new_latency_range
= rc
->latency_range
;
396 u32 new_itr
= rc
->itr
;
399 if (rc
->total_packets
== 0 || !rc
->itr
)
402 /* simple throttlerate management
403 * 0-10MB/s lowest (100000 ints/s)
404 * 10-20MB/s low (20000 ints/s)
405 * 20-1249MB/s bulk (8000 ints/s)
407 bytes_per_int
= rc
->total_bytes
/ rc
->itr
;
409 case I40E_LOWEST_LATENCY
:
410 if (bytes_per_int
> 10)
411 new_latency_range
= I40E_LOW_LATENCY
;
413 case I40E_LOW_LATENCY
:
414 if (bytes_per_int
> 20)
415 new_latency_range
= I40E_BULK_LATENCY
;
416 else if (bytes_per_int
<= 10)
417 new_latency_range
= I40E_LOWEST_LATENCY
;
419 case I40E_BULK_LATENCY
:
420 if (bytes_per_int
<= 20)
421 rc
->latency_range
= I40E_LOW_LATENCY
;
425 switch (new_latency_range
) {
426 case I40E_LOWEST_LATENCY
:
427 new_itr
= I40E_ITR_100K
;
429 case I40E_LOW_LATENCY
:
430 new_itr
= I40E_ITR_20K
;
432 case I40E_BULK_LATENCY
:
433 new_itr
= I40E_ITR_8K
;
439 if (new_itr
!= rc
->itr
) {
440 /* do an exponential smoothing */
441 new_itr
= (10 * new_itr
* rc
->itr
) /
442 ((9 * new_itr
) + rc
->itr
);
443 rc
->itr
= new_itr
& I40E_MAX_ITR
;
447 rc
->total_packets
= 0;
451 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
452 * @q_vector: the vector to adjust
454 static void i40e_update_dynamic_itr(struct i40e_q_vector
*q_vector
)
456 u16 vector
= q_vector
->vsi
->base_vector
+ q_vector
->v_idx
;
457 struct i40e_hw
*hw
= &q_vector
->vsi
->back
->hw
;
461 reg_addr
= I40E_VFINT_ITRN1(I40E_RX_ITR
, vector
- 1);
462 old_itr
= q_vector
->rx
.itr
;
463 i40e_set_new_dynamic_itr(&q_vector
->rx
);
464 if (old_itr
!= q_vector
->rx
.itr
)
465 wr32(hw
, reg_addr
, q_vector
->rx
.itr
);
467 reg_addr
= I40E_VFINT_ITRN1(I40E_TX_ITR
, vector
- 1);
468 old_itr
= q_vector
->tx
.itr
;
469 i40e_set_new_dynamic_itr(&q_vector
->tx
);
470 if (old_itr
!= q_vector
->tx
.itr
)
471 wr32(hw
, reg_addr
, q_vector
->tx
.itr
);
475 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
476 * @tx_ring: the tx ring to set up
478 * Return 0 on success, negative on error
480 int i40evf_setup_tx_descriptors(struct i40e_ring
*tx_ring
)
482 struct device
*dev
= tx_ring
->dev
;
488 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
489 tx_ring
->tx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
493 /* round up to nearest 4K */
494 tx_ring
->size
= tx_ring
->count
* sizeof(struct i40e_tx_desc
);
495 /* add u32 for head writeback, align after this takes care of
496 * guaranteeing this is at least one cache line in size
498 tx_ring
->size
+= sizeof(u32
);
499 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
500 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
501 &tx_ring
->dma
, GFP_KERNEL
);
502 if (!tx_ring
->desc
) {
503 dev_info(dev
, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
508 tx_ring
->next_to_use
= 0;
509 tx_ring
->next_to_clean
= 0;
513 kfree(tx_ring
->tx_bi
);
514 tx_ring
->tx_bi
= NULL
;
519 * i40evf_clean_rx_ring - Free Rx buffers
520 * @rx_ring: ring to be cleaned
522 void i40evf_clean_rx_ring(struct i40e_ring
*rx_ring
)
524 struct device
*dev
= rx_ring
->dev
;
525 struct i40e_rx_buffer
*rx_bi
;
526 unsigned long bi_size
;
529 /* ring already cleared, nothing to do */
533 if (ring_is_ps_enabled(rx_ring
)) {
534 int bufsz
= ALIGN(rx_ring
->rx_hdr_len
, 256) * rx_ring
->count
;
536 rx_bi
= &rx_ring
->rx_bi
[0];
537 if (rx_bi
->hdr_buf
) {
538 dma_free_coherent(dev
,
542 for (i
= 0; i
< rx_ring
->count
; i
++) {
543 rx_bi
= &rx_ring
->rx_bi
[i
];
549 /* Free all the Rx ring sk_buffs */
550 for (i
= 0; i
< rx_ring
->count
; i
++) {
551 rx_bi
= &rx_ring
->rx_bi
[i
];
553 dma_unmap_single(dev
,
560 dev_kfree_skb(rx_bi
->skb
);
564 if (rx_bi
->page_dma
) {
571 __free_page(rx_bi
->page
);
573 rx_bi
->page_offset
= 0;
577 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
578 memset(rx_ring
->rx_bi
, 0, bi_size
);
580 /* Zero out the descriptor ring */
581 memset(rx_ring
->desc
, 0, rx_ring
->size
);
583 rx_ring
->next_to_clean
= 0;
584 rx_ring
->next_to_use
= 0;
588 * i40evf_free_rx_resources - Free Rx resources
589 * @rx_ring: ring to clean the resources from
591 * Free all receive software resources
593 void i40evf_free_rx_resources(struct i40e_ring
*rx_ring
)
595 i40evf_clean_rx_ring(rx_ring
);
596 kfree(rx_ring
->rx_bi
);
597 rx_ring
->rx_bi
= NULL
;
600 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
601 rx_ring
->desc
, rx_ring
->dma
);
602 rx_ring
->desc
= NULL
;
607 * i40evf_alloc_rx_headers - allocate rx header buffers
608 * @rx_ring: ring to alloc buffers
610 * Allocate rx header buffers for the entire ring. As these are static,
611 * this is only called when setting up a new ring.
613 void i40evf_alloc_rx_headers(struct i40e_ring
*rx_ring
)
615 struct device
*dev
= rx_ring
->dev
;
616 struct i40e_rx_buffer
*rx_bi
;
622 if (rx_ring
->rx_bi
[0].hdr_buf
)
624 /* Make sure the buffers don't cross cache line boundaries. */
625 buf_size
= ALIGN(rx_ring
->rx_hdr_len
, 256);
626 buffer
= dma_alloc_coherent(dev
, buf_size
* rx_ring
->count
,
630 for (i
= 0; i
< rx_ring
->count
; i
++) {
631 rx_bi
= &rx_ring
->rx_bi
[i
];
632 rx_bi
->dma
= dma
+ (i
* buf_size
);
633 rx_bi
->hdr_buf
= buffer
+ (i
* buf_size
);
638 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
639 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
641 * Returns 0 on success, negative on failure
643 int i40evf_setup_rx_descriptors(struct i40e_ring
*rx_ring
)
645 struct device
*dev
= rx_ring
->dev
;
648 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
649 rx_ring
->rx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
653 u64_stats_init(&rx_ring
->syncp
);
655 /* Round up to nearest 4K */
656 rx_ring
->size
= ring_is_16byte_desc_enabled(rx_ring
)
657 ? rx_ring
->count
* sizeof(union i40e_16byte_rx_desc
)
658 : rx_ring
->count
* sizeof(union i40e_32byte_rx_desc
);
659 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
660 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
661 &rx_ring
->dma
, GFP_KERNEL
);
663 if (!rx_ring
->desc
) {
664 dev_info(dev
, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
669 rx_ring
->next_to_clean
= 0;
670 rx_ring
->next_to_use
= 0;
674 kfree(rx_ring
->rx_bi
);
675 rx_ring
->rx_bi
= NULL
;
680 * i40e_release_rx_desc - Store the new tail and head values
681 * @rx_ring: ring to bump
682 * @val: new head index
684 static inline void i40e_release_rx_desc(struct i40e_ring
*rx_ring
, u32 val
)
686 rx_ring
->next_to_use
= val
;
687 /* Force memory writes to complete before letting h/w
688 * know there are new descriptors to fetch. (Only
689 * applicable for weak-ordered memory model archs,
693 writel(val
, rx_ring
->tail
);
697 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
698 * @rx_ring: ring to place buffers on
699 * @cleaned_count: number of buffers to replace
701 void i40evf_alloc_rx_buffers_ps(struct i40e_ring
*rx_ring
, u16 cleaned_count
)
703 u16 i
= rx_ring
->next_to_use
;
704 union i40e_rx_desc
*rx_desc
;
705 struct i40e_rx_buffer
*bi
;
707 /* do nothing if no valid netdev defined */
708 if (!rx_ring
->netdev
|| !cleaned_count
)
711 while (cleaned_count
--) {
712 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
713 bi
= &rx_ring
->rx_bi
[i
];
715 if (bi
->skb
) /* desc is in use */
718 bi
->page
= alloc_page(GFP_ATOMIC
);
720 rx_ring
->rx_stats
.alloc_page_failed
++;
726 /* use a half page if we're re-using */
727 bi
->page_offset
^= PAGE_SIZE
/ 2;
728 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
733 if (dma_mapping_error(rx_ring
->dev
,
735 rx_ring
->rx_stats
.alloc_page_failed
++;
741 dma_sync_single_range_for_device(rx_ring
->dev
,
746 /* Refresh the desc even if buffer_addrs didn't change
747 * because each write-back erases this info.
749 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
750 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
752 if (i
== rx_ring
->count
)
757 if (rx_ring
->next_to_use
!= i
)
758 i40e_release_rx_desc(rx_ring
, i
);
762 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
763 * @rx_ring: ring to place buffers on
764 * @cleaned_count: number of buffers to replace
766 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring
*rx_ring
, u16 cleaned_count
)
768 u16 i
= rx_ring
->next_to_use
;
769 union i40e_rx_desc
*rx_desc
;
770 struct i40e_rx_buffer
*bi
;
773 /* do nothing if no valid netdev defined */
774 if (!rx_ring
->netdev
|| !cleaned_count
)
777 while (cleaned_count
--) {
778 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
779 bi
= &rx_ring
->rx_bi
[i
];
783 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
784 rx_ring
->rx_buf_len
);
786 rx_ring
->rx_stats
.alloc_buff_failed
++;
789 /* initialize queue mapping */
790 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
795 bi
->dma
= dma_map_single(rx_ring
->dev
,
799 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
800 rx_ring
->rx_stats
.alloc_buff_failed
++;
806 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
807 rx_desc
->read
.hdr_addr
= 0;
809 if (i
== rx_ring
->count
)
814 if (rx_ring
->next_to_use
!= i
)
815 i40e_release_rx_desc(rx_ring
, i
);
819 * i40e_receive_skb - Send a completed packet up the stack
820 * @rx_ring: rx ring in play
821 * @skb: packet to send up
822 * @vlan_tag: vlan tag for packet
824 static void i40e_receive_skb(struct i40e_ring
*rx_ring
,
825 struct sk_buff
*skb
, u16 vlan_tag
)
827 struct i40e_q_vector
*q_vector
= rx_ring
->q_vector
;
828 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
829 u64 flags
= vsi
->back
->flags
;
831 if (vlan_tag
& VLAN_VID_MASK
)
832 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlan_tag
);
834 if (flags
& I40E_FLAG_IN_NETPOLL
)
837 napi_gro_receive(&q_vector
->napi
, skb
);
841 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
842 * @vsi: the VSI we care about
843 * @skb: skb currently being received and modified
844 * @rx_status: status value of last descriptor in packet
845 * @rx_error: error value of last descriptor in packet
846 * @rx_ptype: ptype value of last descriptor in packet
848 static inline void i40e_rx_checksum(struct i40e_vsi
*vsi
,
854 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(rx_ptype
);
855 bool ipv4
= false, ipv6
= false;
856 bool ipv4_tunnel
, ipv6_tunnel
;
861 ipv4_tunnel
= (rx_ptype
>= I40E_RX_PTYPE_GRENAT4_MAC_PAY3
) &&
862 (rx_ptype
<= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4
);
863 ipv6_tunnel
= (rx_ptype
>= I40E_RX_PTYPE_GRENAT6_MAC_PAY3
) &&
864 (rx_ptype
<= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4
);
866 skb
->ip_summed
= CHECKSUM_NONE
;
868 /* Rx csum enabled and ip headers found? */
869 if (!(vsi
->netdev
->features
& NETIF_F_RXCSUM
))
872 /* did the hardware decode the packet and checksum? */
873 if (!(rx_status
& (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT
)))
876 /* both known and outer_ip must be set for the below code to work */
877 if (!(decoded
.known
&& decoded
.outer_ip
))
880 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
881 decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV4
)
883 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
884 decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV6
)
888 (rx_error
& ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT
) |
889 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT
))))
892 /* likely incorrect csum if alternate IP extension headers found */
894 rx_status
& (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT
))
895 /* don't increment checksum err here, non-fatal err */
898 /* there was some L4 error, count error and punt packet to the stack */
899 if (rx_error
& (1 << I40E_RX_DESC_ERROR_L4E_SHIFT
))
902 /* handle packets that were not able to be checksummed due
903 * to arrival speed, in this case the stack can compute
906 if (rx_error
& (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT
))
909 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
910 * it in the driver, hardware does not do it for us.
911 * Since L3L4P bit was set we assume a valid IHL value (>=5)
912 * so the total length of IPv4 header is IHL*4 bytes
913 * The UDP_0 bit *may* bet set if the *inner* header is UDP
916 (decoded
.inner_prot
!= I40E_RX_PTYPE_INNER_PROT_UDP
) &&
917 !(rx_status
& (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT
))) {
918 skb
->transport_header
= skb
->mac_header
+
919 sizeof(struct ethhdr
) +
920 (ip_hdr(skb
)->ihl
* 4);
922 /* Add 4 bytes for VLAN tagged packets */
923 skb
->transport_header
+= (skb
->protocol
== htons(ETH_P_8021Q
) ||
924 skb
->protocol
== htons(ETH_P_8021AD
))
927 rx_udp_csum
= udp_csum(skb
);
929 csum
= csum_tcpudp_magic(
930 iph
->saddr
, iph
->daddr
,
931 (skb
->len
- skb_transport_offset(skb
)),
932 IPPROTO_UDP
, rx_udp_csum
);
934 if (udp_hdr(skb
)->check
!= csum
)
938 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
939 skb
->csum_level
= ipv4_tunnel
|| ipv6_tunnel
;
944 vsi
->back
->hw_csum_rx_error
++;
948 * i40e_rx_hash - returns the hash value from the Rx descriptor
949 * @ring: descriptor ring
950 * @rx_desc: specific descriptor
952 static inline u32
i40e_rx_hash(struct i40e_ring
*ring
,
953 union i40e_rx_desc
*rx_desc
)
955 const __le64 rss_mask
=
956 cpu_to_le64((u64
)I40E_RX_DESC_FLTSTAT_RSS_HASH
<<
957 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT
);
959 if ((ring
->netdev
->features
& NETIF_F_RXHASH
) &&
960 (rx_desc
->wb
.qword1
.status_error_len
& rss_mask
) == rss_mask
)
961 return le32_to_cpu(rx_desc
->wb
.qword0
.hi_dword
.rss
);
967 * i40e_ptype_to_hash - get a hash type
968 * @ptype: the ptype value from the descriptor
970 * Returns a hash type to be used by skb_set_hash
972 static inline enum pkt_hash_types
i40e_ptype_to_hash(u8 ptype
)
974 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(ptype
);
977 return PKT_HASH_TYPE_NONE
;
979 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
980 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4
)
981 return PKT_HASH_TYPE_L4
;
982 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
983 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3
)
984 return PKT_HASH_TYPE_L3
;
986 return PKT_HASH_TYPE_L2
;
990 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
991 * @rx_ring: rx ring to clean
992 * @budget: how many cleans we're allowed
994 * Returns true if there's any budget left (e.g. the clean is finished)
996 static int i40e_clean_rx_irq_ps(struct i40e_ring
*rx_ring
, int budget
)
998 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
999 u16 rx_packet_len
, rx_header_len
, rx_sph
, rx_hbo
;
1000 u16 cleaned_count
= I40E_DESC_UNUSED(rx_ring
);
1001 const int current_node
= numa_node_id();
1002 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
1003 u16 i
= rx_ring
->next_to_clean
;
1004 union i40e_rx_desc
*rx_desc
;
1005 u32 rx_error
, rx_status
;
1010 struct i40e_rx_buffer
*rx_bi
;
1011 struct sk_buff
*skb
;
1013 /* return some buffers to hardware, one at a time is too slow */
1014 if (cleaned_count
>= I40E_RX_BUFFER_WRITE
) {
1015 i40evf_alloc_rx_buffers_ps(rx_ring
, cleaned_count
);
1019 i
= rx_ring
->next_to_clean
;
1020 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
1021 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
1022 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
1023 I40E_RXD_QW1_STATUS_SHIFT
;
1025 if (!(rx_status
& (1 << I40E_RX_DESC_STATUS_DD_SHIFT
)))
1028 /* This memory barrier is needed to keep us from reading
1029 * any other fields out of the rx_desc until we know the
1033 rx_bi
= &rx_ring
->rx_bi
[i
];
1036 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1037 rx_ring
->rx_hdr_len
);
1039 rx_ring
->rx_stats
.alloc_buff_failed
++;
1040 /* initialize queue mapping */
1041 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1042 /* we are reusing so sync this buffer for CPU use */
1043 dma_sync_single_range_for_cpu(rx_ring
->dev
,
1046 rx_ring
->rx_hdr_len
,
1049 rx_packet_len
= (qword
& I40E_RXD_QW1_LENGTH_PBUF_MASK
) >>
1050 I40E_RXD_QW1_LENGTH_PBUF_SHIFT
;
1051 rx_header_len
= (qword
& I40E_RXD_QW1_LENGTH_HBUF_MASK
) >>
1052 I40E_RXD_QW1_LENGTH_HBUF_SHIFT
;
1053 rx_sph
= (qword
& I40E_RXD_QW1_LENGTH_SPH_MASK
) >>
1054 I40E_RXD_QW1_LENGTH_SPH_SHIFT
;
1056 rx_error
= (qword
& I40E_RXD_QW1_ERROR_MASK
) >>
1057 I40E_RXD_QW1_ERROR_SHIFT
;
1058 rx_hbo
= rx_error
& (1 << I40E_RX_DESC_ERROR_HBO_SHIFT
);
1059 rx_error
&= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT
);
1061 rx_ptype
= (qword
& I40E_RXD_QW1_PTYPE_MASK
) >>
1062 I40E_RXD_QW1_PTYPE_SHIFT
;
1063 prefetch(rx_bi
->page
);
1066 if (rx_hbo
|| rx_sph
) {
1069 len
= I40E_RX_HDR_SIZE
;
1071 len
= rx_header_len
;
1072 memcpy(__skb_put(skb
, len
), rx_bi
->hdr_buf
, len
);
1073 } else if (skb
->len
== 0) {
1076 len
= (rx_packet_len
> skb_headlen(skb
) ?
1077 skb_headlen(skb
) : rx_packet_len
);
1078 memcpy(__skb_put(skb
, len
),
1079 rx_bi
->page
+ rx_bi
->page_offset
,
1081 rx_bi
->page_offset
+= len
;
1082 rx_packet_len
-= len
;
1085 /* Get the rest of the data if this was a header split */
1086 if (rx_packet_len
) {
1087 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1092 skb
->len
+= rx_packet_len
;
1093 skb
->data_len
+= rx_packet_len
;
1094 skb
->truesize
+= rx_packet_len
;
1096 if ((page_count(rx_bi
->page
) == 1) &&
1097 (page_to_nid(rx_bi
->page
) == current_node
))
1098 get_page(rx_bi
->page
);
1102 dma_unmap_page(rx_ring
->dev
,
1106 rx_bi
->page_dma
= 0;
1108 I40E_RX_INCREMENT(rx_ring
, i
);
1111 !(rx_status
& (1 << I40E_RX_DESC_STATUS_EOF_SHIFT
)))) {
1112 struct i40e_rx_buffer
*next_buffer
;
1114 next_buffer
= &rx_ring
->rx_bi
[i
];
1115 next_buffer
->skb
= skb
;
1116 rx_ring
->rx_stats
.non_eop_descs
++;
1120 /* ERR_MASK will only have valid bits if EOP set */
1121 if (unlikely(rx_error
& (1 << I40E_RX_DESC_ERROR_RXE_SHIFT
))) {
1122 dev_kfree_skb_any(skb
);
1123 /* TODO: shouldn't we increment a counter indicating the
1129 skb_set_hash(skb
, i40e_rx_hash(rx_ring
, rx_desc
),
1130 i40e_ptype_to_hash(rx_ptype
));
1131 /* probably a little skewed due to removing CRC */
1132 total_rx_bytes
+= skb
->len
;
1135 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1137 i40e_rx_checksum(vsi
, skb
, rx_status
, rx_error
, rx_ptype
);
1139 vlan_tag
= rx_status
& (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
)
1140 ? le16_to_cpu(rx_desc
->wb
.qword0
.lo_dword
.l2tag1
)
1143 if (!i40e_fcoe_handle_offload(rx_ring
, rx_desc
, skb
)) {
1144 dev_kfree_skb_any(skb
);
1148 skb_mark_napi_id(skb
, &rx_ring
->q_vector
->napi
);
1149 i40e_receive_skb(rx_ring
, skb
, vlan_tag
);
1151 rx_ring
->netdev
->last_rx
= jiffies
;
1152 rx_desc
->wb
.qword1
.status_error_len
= 0;
1154 } while (likely(total_rx_packets
< budget
));
1156 u64_stats_update_begin(&rx_ring
->syncp
);
1157 rx_ring
->stats
.packets
+= total_rx_packets
;
1158 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1159 u64_stats_update_end(&rx_ring
->syncp
);
1160 rx_ring
->q_vector
->rx
.total_packets
+= total_rx_packets
;
1161 rx_ring
->q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1163 return total_rx_packets
;
1167 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1168 * @rx_ring: rx ring to clean
1169 * @budget: how many cleans we're allowed
1171 * Returns number of packets cleaned
1173 static int i40e_clean_rx_irq_1buf(struct i40e_ring
*rx_ring
, int budget
)
1175 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1176 u16 cleaned_count
= I40E_DESC_UNUSED(rx_ring
);
1177 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
1178 union i40e_rx_desc
*rx_desc
;
1179 u32 rx_error
, rx_status
;
1186 struct i40e_rx_buffer
*rx_bi
;
1187 struct sk_buff
*skb
;
1189 /* return some buffers to hardware, one at a time is too slow */
1190 if (cleaned_count
>= I40E_RX_BUFFER_WRITE
) {
1191 i40evf_alloc_rx_buffers_1buf(rx_ring
, cleaned_count
);
1195 i
= rx_ring
->next_to_clean
;
1196 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
1197 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
1198 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
1199 I40E_RXD_QW1_STATUS_SHIFT
;
1201 if (!(rx_status
& (1 << I40E_RX_DESC_STATUS_DD_SHIFT
)))
1204 /* This memory barrier is needed to keep us from reading
1205 * any other fields out of the rx_desc until we know the
1210 rx_bi
= &rx_ring
->rx_bi
[i
];
1212 prefetch(skb
->data
);
1214 rx_packet_len
= (qword
& I40E_RXD_QW1_LENGTH_PBUF_MASK
) >>
1215 I40E_RXD_QW1_LENGTH_PBUF_SHIFT
;
1217 rx_error
= (qword
& I40E_RXD_QW1_ERROR_MASK
) >>
1218 I40E_RXD_QW1_ERROR_SHIFT
;
1219 rx_error
&= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT
);
1221 rx_ptype
= (qword
& I40E_RXD_QW1_PTYPE_MASK
) >>
1222 I40E_RXD_QW1_PTYPE_SHIFT
;
1226 /* Get the header and possibly the whole packet
1227 * If this is an skb from previous receive dma will be 0
1229 skb_put(skb
, rx_packet_len
);
1230 dma_unmap_single(rx_ring
->dev
, rx_bi
->dma
, rx_ring
->rx_buf_len
,
1234 I40E_RX_INCREMENT(rx_ring
, i
);
1237 !(rx_status
& (1 << I40E_RX_DESC_STATUS_EOF_SHIFT
)))) {
1238 rx_ring
->rx_stats
.non_eop_descs
++;
1242 /* ERR_MASK will only have valid bits if EOP set */
1243 if (unlikely(rx_error
& (1 << I40E_RX_DESC_ERROR_RXE_SHIFT
))) {
1244 dev_kfree_skb_any(skb
);
1245 /* TODO: shouldn't we increment a counter indicating the
1251 skb_set_hash(skb
, i40e_rx_hash(rx_ring
, rx_desc
),
1252 i40e_ptype_to_hash(rx_ptype
));
1253 /* probably a little skewed due to removing CRC */
1254 total_rx_bytes
+= skb
->len
;
1257 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1259 i40e_rx_checksum(vsi
, skb
, rx_status
, rx_error
, rx_ptype
);
1261 vlan_tag
= rx_status
& (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
)
1262 ? le16_to_cpu(rx_desc
->wb
.qword0
.lo_dword
.l2tag1
)
1264 i40e_receive_skb(rx_ring
, skb
, vlan_tag
);
1266 rx_ring
->netdev
->last_rx
= jiffies
;
1267 rx_desc
->wb
.qword1
.status_error_len
= 0;
1268 } while (likely(total_rx_packets
< budget
));
1270 u64_stats_update_begin(&rx_ring
->syncp
);
1271 rx_ring
->stats
.packets
+= total_rx_packets
;
1272 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1273 u64_stats_update_end(&rx_ring
->syncp
);
1274 rx_ring
->q_vector
->rx
.total_packets
+= total_rx_packets
;
1275 rx_ring
->q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1277 return total_rx_packets
;
1281 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1282 * @napi: napi struct with our devices info in it
1283 * @budget: amount of work driver is allowed to do this pass, in packets
1285 * This function will clean all queues associated with a q_vector.
1287 * Returns the amount of work done
1289 int i40evf_napi_poll(struct napi_struct
*napi
, int budget
)
1291 struct i40e_q_vector
*q_vector
=
1292 container_of(napi
, struct i40e_q_vector
, napi
);
1293 struct i40e_vsi
*vsi
= q_vector
->vsi
;
1294 struct i40e_ring
*ring
;
1295 bool clean_complete
= true;
1296 bool arm_wb
= false;
1297 int budget_per_ring
;
1300 if (test_bit(__I40E_DOWN
, &vsi
->state
)) {
1301 napi_complete(napi
);
1305 /* Since the actual Tx work is minimal, we can give the Tx a larger
1306 * budget and be more aggressive about cleaning up the Tx descriptors.
1308 i40e_for_each_ring(ring
, q_vector
->tx
) {
1309 clean_complete
&= i40e_clean_tx_irq(ring
, vsi
->work_limit
);
1310 arm_wb
|= ring
->arm_wb
;
1313 /* We attempt to distribute budget to each Rx queue fairly, but don't
1314 * allow the budget to go below 1 because that would exit polling early.
1316 budget_per_ring
= max(budget
/q_vector
->num_ringpairs
, 1);
1318 i40e_for_each_ring(ring
, q_vector
->rx
) {
1319 if (ring_is_ps_enabled(ring
))
1320 cleaned
= i40e_clean_rx_irq_ps(ring
, budget_per_ring
);
1322 cleaned
= i40e_clean_rx_irq_1buf(ring
, budget_per_ring
);
1323 /* if we didn't clean as many as budgeted, we must be done */
1324 clean_complete
&= (budget_per_ring
!= cleaned
);
1327 /* If work not completed, return budget and polling will return */
1328 if (!clean_complete
) {
1330 i40e_force_wb(vsi
, q_vector
);
1334 /* Work is done so exit the polling mode and re-enable the interrupt */
1335 napi_complete(napi
);
1336 if (ITR_IS_DYNAMIC(vsi
->rx_itr_setting
) ||
1337 ITR_IS_DYNAMIC(vsi
->tx_itr_setting
))
1338 i40e_update_dynamic_itr(q_vector
);
1340 if (!test_bit(__I40E_DOWN
, &vsi
->state
))
1341 i40evf_irq_enable_queues(vsi
->back
, 1 << q_vector
->v_idx
);
1347 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1349 * @tx_ring: ring to send buffer on
1350 * @flags: the tx flags to be set
1352 * Checks the skb and set up correspondingly several generic transmit flags
1353 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1355 * Returns error code indicate the frame should be dropped upon error and the
1356 * otherwise returns 0 to indicate the flags has been set properly.
1358 static int i40e_tx_prepare_vlan_flags(struct sk_buff
*skb
,
1359 struct i40e_ring
*tx_ring
,
1362 __be16 protocol
= skb
->protocol
;
1365 /* if we have a HW VLAN tag being added, default to the HW one */
1366 if (skb_vlan_tag_present(skb
)) {
1367 tx_flags
|= skb_vlan_tag_get(skb
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1368 tx_flags
|= I40E_TX_FLAGS_HW_VLAN
;
1369 /* else if it is a SW VLAN, check the next protocol and store the tag */
1370 } else if (protocol
== htons(ETH_P_8021Q
)) {
1371 struct vlan_hdr
*vhdr
, _vhdr
;
1372 vhdr
= skb_header_pointer(skb
, ETH_HLEN
, sizeof(_vhdr
), &_vhdr
);
1376 protocol
= vhdr
->h_vlan_encapsulated_proto
;
1377 tx_flags
|= ntohs(vhdr
->h_vlan_TCI
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1378 tx_flags
|= I40E_TX_FLAGS_SW_VLAN
;
1386 * i40e_tso - set up the tso context descriptor
1387 * @tx_ring: ptr to the ring to send
1388 * @skb: ptr to the skb we're sending
1389 * @tx_flags: the collected send information
1390 * @protocol: the send protocol
1391 * @hdr_len: ptr to the size of the packet header
1392 * @cd_tunneling: ptr to context descriptor bits
1394 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1396 static int i40e_tso(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1397 u32 tx_flags
, __be16 protocol
, u8
*hdr_len
,
1398 u64
*cd_type_cmd_tso_mss
, u32
*cd_tunneling
)
1400 u32 cd_cmd
, cd_tso_len
, cd_mss
;
1401 struct ipv6hdr
*ipv6h
;
1402 struct tcphdr
*tcph
;
1407 if (!skb_is_gso(skb
))
1410 err
= skb_cow_head(skb
, 0);
1414 iph
= skb
->encapsulation
? inner_ip_hdr(skb
) : ip_hdr(skb
);
1415 ipv6h
= skb
->encapsulation
? inner_ipv6_hdr(skb
) : ipv6_hdr(skb
);
1417 if (iph
->version
== 4) {
1418 tcph
= skb
->encapsulation
? inner_tcp_hdr(skb
) : tcp_hdr(skb
);
1421 tcph
->check
= ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
,
1423 } else if (ipv6h
->version
== 6) {
1424 tcph
= skb
->encapsulation
? inner_tcp_hdr(skb
) : tcp_hdr(skb
);
1425 ipv6h
->payload_len
= 0;
1426 tcph
->check
= ~csum_ipv6_magic(&ipv6h
->saddr
, &ipv6h
->daddr
,
1430 l4len
= skb
->encapsulation
? inner_tcp_hdrlen(skb
) : tcp_hdrlen(skb
);
1431 *hdr_len
= (skb
->encapsulation
1432 ? (skb_inner_transport_header(skb
) - skb
->data
)
1433 : skb_transport_offset(skb
)) + l4len
;
1435 /* find the field values */
1436 cd_cmd
= I40E_TX_CTX_DESC_TSO
;
1437 cd_tso_len
= skb
->len
- *hdr_len
;
1438 cd_mss
= skb_shinfo(skb
)->gso_size
;
1439 *cd_type_cmd_tso_mss
|= ((u64
)cd_cmd
<< I40E_TXD_CTX_QW1_CMD_SHIFT
) |
1441 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT
) |
1442 ((u64
)cd_mss
<< I40E_TXD_CTX_QW1_MSS_SHIFT
);
1447 * i40e_tx_enable_csum - Enable Tx checksum offloads
1449 * @tx_flags: Tx flags currently set
1450 * @td_cmd: Tx descriptor command bits to set
1451 * @td_offset: Tx descriptor header offsets to set
1452 * @cd_tunneling: ptr to context desc bits
1454 static void i40e_tx_enable_csum(struct sk_buff
*skb
, u32 tx_flags
,
1455 u32
*td_cmd
, u32
*td_offset
,
1456 struct i40e_ring
*tx_ring
,
1459 struct ipv6hdr
*this_ipv6_hdr
;
1460 unsigned int this_tcp_hdrlen
;
1461 struct iphdr
*this_ip_hdr
;
1462 u32 network_hdr_len
;
1465 if (skb
->encapsulation
) {
1466 network_hdr_len
= skb_inner_network_header_len(skb
);
1467 this_ip_hdr
= inner_ip_hdr(skb
);
1468 this_ipv6_hdr
= inner_ipv6_hdr(skb
);
1469 this_tcp_hdrlen
= inner_tcp_hdrlen(skb
);
1471 if (tx_flags
& I40E_TX_FLAGS_IPV4
) {
1473 if (tx_flags
& I40E_TX_FLAGS_TSO
) {
1474 *cd_tunneling
|= I40E_TX_CTX_EXT_IP_IPV4
;
1475 ip_hdr(skb
)->check
= 0;
1478 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
;
1480 } else if (tx_flags
& I40E_TX_FLAGS_IPV6
) {
1481 *cd_tunneling
|= I40E_TX_CTX_EXT_IP_IPV6
;
1482 if (tx_flags
& I40E_TX_FLAGS_TSO
)
1483 ip_hdr(skb
)->check
= 0;
1486 /* Now set the ctx descriptor fields */
1487 *cd_tunneling
|= (skb_network_header_len(skb
) >> 2) <<
1488 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT
|
1489 I40E_TXD_CTX_UDP_TUNNELING
|
1490 ((skb_inner_network_offset(skb
) -
1491 skb_transport_offset(skb
)) >> 1) <<
1492 I40E_TXD_CTX_QW0_NATLEN_SHIFT
;
1493 if (this_ip_hdr
->version
== 6) {
1494 tx_flags
&= ~I40E_TX_FLAGS_IPV4
;
1495 tx_flags
|= I40E_TX_FLAGS_IPV6
;
1500 network_hdr_len
= skb_network_header_len(skb
);
1501 this_ip_hdr
= ip_hdr(skb
);
1502 this_ipv6_hdr
= ipv6_hdr(skb
);
1503 this_tcp_hdrlen
= tcp_hdrlen(skb
);
1506 /* Enable IP checksum offloads */
1507 if (tx_flags
& I40E_TX_FLAGS_IPV4
) {
1508 l4_hdr
= this_ip_hdr
->protocol
;
1509 /* the stack computes the IP header already, the only time we
1510 * need the hardware to recompute it is in the case of TSO.
1512 if (tx_flags
& I40E_TX_FLAGS_TSO
) {
1513 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM
;
1514 this_ip_hdr
->check
= 0;
1516 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV4
;
1518 /* Now set the td_offset for IP header length */
1519 *td_offset
= (network_hdr_len
>> 2) <<
1520 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1521 } else if (tx_flags
& I40E_TX_FLAGS_IPV6
) {
1522 l4_hdr
= this_ipv6_hdr
->nexthdr
;
1523 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV6
;
1524 /* Now set the td_offset for IP header length */
1525 *td_offset
= (network_hdr_len
>> 2) <<
1526 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1528 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1529 *td_offset
|= (skb_network_offset(skb
) >> 1) <<
1530 I40E_TX_DESC_LENGTH_MACLEN_SHIFT
;
1532 /* Enable L4 checksum offloads */
1535 /* enable checksum offloads */
1536 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_TCP
;
1537 *td_offset
|= (this_tcp_hdrlen
>> 2) <<
1538 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1541 /* enable SCTP checksum offload */
1542 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_SCTP
;
1543 *td_offset
|= (sizeof(struct sctphdr
) >> 2) <<
1544 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1547 /* enable UDP checksum offload */
1548 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_UDP
;
1549 *td_offset
|= (sizeof(struct udphdr
) >> 2) <<
1550 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1558 * i40e_create_tx_ctx Build the Tx context descriptor
1559 * @tx_ring: ring to create the descriptor on
1560 * @cd_type_cmd_tso_mss: Quad Word 1
1561 * @cd_tunneling: Quad Word 0 - bits 0-31
1562 * @cd_l2tag2: Quad Word 0 - bits 32-63
1564 static void i40e_create_tx_ctx(struct i40e_ring
*tx_ring
,
1565 const u64 cd_type_cmd_tso_mss
,
1566 const u32 cd_tunneling
, const u32 cd_l2tag2
)
1568 struct i40e_tx_context_desc
*context_desc
;
1569 int i
= tx_ring
->next_to_use
;
1571 if ((cd_type_cmd_tso_mss
== I40E_TX_DESC_DTYPE_CONTEXT
) &&
1572 !cd_tunneling
&& !cd_l2tag2
)
1575 /* grab the next descriptor */
1576 context_desc
= I40E_TX_CTXTDESC(tx_ring
, i
);
1579 tx_ring
->next_to_use
= (i
< tx_ring
->count
) ? i
: 0;
1581 /* cpu_to_le32 and assign to struct fields */
1582 context_desc
->tunneling_params
= cpu_to_le32(cd_tunneling
);
1583 context_desc
->l2tag2
= cpu_to_le16(cd_l2tag2
);
1584 context_desc
->rsvd
= cpu_to_le16(0);
1585 context_desc
->type_cmd_tso_mss
= cpu_to_le64(cd_type_cmd_tso_mss
);
1589 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1591 * @tx_flags: collected send information
1592 * @hdr_len: size of the packet header
1594 * Note: Our HW can't scatter-gather more than 8 fragments to build
1595 * a packet on the wire and so we need to figure out the cases where we
1596 * need to linearize the skb.
1598 static bool i40e_chk_linearize(struct sk_buff
*skb
, u32 tx_flags
,
1601 struct skb_frag_struct
*frag
;
1602 bool linearize
= false;
1603 unsigned int size
= 0;
1607 num_frags
= skb_shinfo(skb
)->nr_frags
;
1608 gso_segs
= skb_shinfo(skb
)->gso_segs
;
1610 if (tx_flags
& (I40E_TX_FLAGS_TSO
| I40E_TX_FLAGS_FSO
)) {
1613 if (num_frags
< (I40E_MAX_BUFFER_TXD
))
1614 goto linearize_chk_done
;
1615 /* try the simple math, if we have too many frags per segment */
1616 if (DIV_ROUND_UP((num_frags
+ gso_segs
), gso_segs
) >
1617 I40E_MAX_BUFFER_TXD
) {
1619 goto linearize_chk_done
;
1621 frag
= &skb_shinfo(skb
)->frags
[0];
1623 /* we might still have more fragments per segment */
1625 size
+= skb_frag_size(frag
);
1627 if (j
== I40E_MAX_BUFFER_TXD
) {
1628 if (size
< skb_shinfo(skb
)->gso_size
) {
1633 size
-= skb_shinfo(skb
)->gso_size
;
1639 } while (num_frags
);
1641 if (num_frags
>= I40E_MAX_BUFFER_TXD
)
1650 * i40e_tx_map - Build the Tx descriptor
1651 * @tx_ring: ring to send buffer on
1653 * @first: first buffer info buffer to use
1654 * @tx_flags: collected send information
1655 * @hdr_len: size of the packet header
1656 * @td_cmd: the command field in the descriptor
1657 * @td_offset: offset for checksum or crc
1659 static void i40e_tx_map(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1660 struct i40e_tx_buffer
*first
, u32 tx_flags
,
1661 const u8 hdr_len
, u32 td_cmd
, u32 td_offset
)
1663 unsigned int data_len
= skb
->data_len
;
1664 unsigned int size
= skb_headlen(skb
);
1665 struct skb_frag_struct
*frag
;
1666 struct i40e_tx_buffer
*tx_bi
;
1667 struct i40e_tx_desc
*tx_desc
;
1668 u16 i
= tx_ring
->next_to_use
;
1673 if (tx_flags
& I40E_TX_FLAGS_HW_VLAN
) {
1674 td_cmd
|= I40E_TX_DESC_CMD_IL2TAG1
;
1675 td_tag
= (tx_flags
& I40E_TX_FLAGS_VLAN_MASK
) >>
1676 I40E_TX_FLAGS_VLAN_SHIFT
;
1679 if (tx_flags
& (I40E_TX_FLAGS_TSO
| I40E_TX_FLAGS_FSO
))
1680 gso_segs
= skb_shinfo(skb
)->gso_segs
;
1684 /* multiply data chunks by size of headers */
1685 first
->bytecount
= skb
->len
- hdr_len
+ (gso_segs
* hdr_len
);
1686 first
->gso_segs
= gso_segs
;
1688 first
->tx_flags
= tx_flags
;
1690 dma
= dma_map_single(tx_ring
->dev
, skb
->data
, size
, DMA_TO_DEVICE
);
1692 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
1695 for (frag
= &skb_shinfo(skb
)->frags
[0];; frag
++) {
1696 if (dma_mapping_error(tx_ring
->dev
, dma
))
1699 /* record length, and DMA address */
1700 dma_unmap_len_set(tx_bi
, len
, size
);
1701 dma_unmap_addr_set(tx_bi
, dma
, dma
);
1703 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1705 while (unlikely(size
> I40E_MAX_DATA_PER_TXD
)) {
1706 tx_desc
->cmd_type_offset_bsz
=
1707 build_ctob(td_cmd
, td_offset
,
1708 I40E_MAX_DATA_PER_TXD
, td_tag
);
1712 if (i
== tx_ring
->count
) {
1713 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1717 dma
+= I40E_MAX_DATA_PER_TXD
;
1718 size
-= I40E_MAX_DATA_PER_TXD
;
1720 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1723 if (likely(!data_len
))
1726 tx_desc
->cmd_type_offset_bsz
= build_ctob(td_cmd
, td_offset
,
1731 if (i
== tx_ring
->count
) {
1732 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1736 size
= skb_frag_size(frag
);
1739 dma
= skb_frag_dma_map(tx_ring
->dev
, frag
, 0, size
,
1742 tx_bi
= &tx_ring
->tx_bi
[i
];
1745 /* Place RS bit on last descriptor of any packet that spans across the
1746 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1748 #define WB_STRIDE 0x3
1749 if (((i
& WB_STRIDE
) != WB_STRIDE
) &&
1750 (first
<= &tx_ring
->tx_bi
[i
]) &&
1751 (first
>= &tx_ring
->tx_bi
[i
& ~WB_STRIDE
])) {
1752 tx_desc
->cmd_type_offset_bsz
=
1753 build_ctob(td_cmd
, td_offset
, size
, td_tag
) |
1754 cpu_to_le64((u64
)I40E_TX_DESC_CMD_EOP
<<
1755 I40E_TXD_QW1_CMD_SHIFT
);
1757 tx_desc
->cmd_type_offset_bsz
=
1758 build_ctob(td_cmd
, td_offset
, size
, td_tag
) |
1759 cpu_to_le64((u64
)I40E_TXD_CMD
<<
1760 I40E_TXD_QW1_CMD_SHIFT
);
1763 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring
->netdev
,
1764 tx_ring
->queue_index
),
1767 /* set the timestamp */
1768 first
->time_stamp
= jiffies
;
1770 /* Force memory writes to complete before letting h/w
1771 * know there are new descriptors to fetch. (Only
1772 * applicable for weak-ordered memory model archs,
1777 /* set next_to_watch value indicating a packet is present */
1778 first
->next_to_watch
= tx_desc
;
1781 if (i
== tx_ring
->count
)
1784 tx_ring
->next_to_use
= i
;
1786 /* notify HW of packet */
1787 writel(i
, tx_ring
->tail
);
1792 dev_info(tx_ring
->dev
, "TX DMA map failed\n");
1794 /* clear dma mappings for failed tx_bi map */
1796 tx_bi
= &tx_ring
->tx_bi
[i
];
1797 i40e_unmap_and_free_tx_resource(tx_ring
, tx_bi
);
1805 tx_ring
->next_to_use
= i
;
1809 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1810 * @tx_ring: the ring to be checked
1811 * @size: the size buffer we want to assure is available
1813 * Returns -EBUSY if a stop is needed, else 0
1815 static inline int __i40e_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1817 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1818 /* Memory barrier before checking head and tail */
1821 /* Check again in a case another CPU has just made room available. */
1822 if (likely(I40E_DESC_UNUSED(tx_ring
) < size
))
1825 /* A reprieve! - use start_queue because it doesn't call schedule */
1826 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1827 ++tx_ring
->tx_stats
.restart_queue
;
1832 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1833 * @tx_ring: the ring to be checked
1834 * @size: the size buffer we want to assure is available
1836 * Returns 0 if stop is not needed
1838 static int i40e_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1840 if (likely(I40E_DESC_UNUSED(tx_ring
) >= size
))
1842 return __i40e_maybe_stop_tx(tx_ring
, size
);
1846 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1848 * @tx_ring: ring to send buffer on
1850 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1851 * there is not enough descriptors available in this ring since we need at least
1854 static int i40e_xmit_descriptor_count(struct sk_buff
*skb
,
1855 struct i40e_ring
*tx_ring
)
1860 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1861 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1862 * + 4 desc gap to avoid the cache line where head is,
1863 * + 1 desc for context descriptor,
1864 * otherwise try next time
1866 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
1867 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
1869 count
+= TXD_USE_COUNT(skb_headlen(skb
));
1870 if (i40e_maybe_stop_tx(tx_ring
, count
+ 4 + 1)) {
1871 tx_ring
->tx_stats
.tx_busy
++;
1878 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1880 * @tx_ring: ring to send buffer on
1882 * Returns NETDEV_TX_OK if sent, else an error code
1884 static netdev_tx_t
i40e_xmit_frame_ring(struct sk_buff
*skb
,
1885 struct i40e_ring
*tx_ring
)
1887 u64 cd_type_cmd_tso_mss
= I40E_TX_DESC_DTYPE_CONTEXT
;
1888 u32 cd_tunneling
= 0, cd_l2tag2
= 0;
1889 struct i40e_tx_buffer
*first
;
1896 if (0 == i40e_xmit_descriptor_count(skb
, tx_ring
))
1897 return NETDEV_TX_BUSY
;
1899 /* prepare the xmit flags */
1900 if (i40e_tx_prepare_vlan_flags(skb
, tx_ring
, &tx_flags
))
1903 /* obtain protocol of skb */
1904 protocol
= vlan_get_protocol(skb
);
1906 /* record the location of the first descriptor for this packet */
1907 first
= &tx_ring
->tx_bi
[tx_ring
->next_to_use
];
1909 /* setup IPv4/IPv6 offloads */
1910 if (protocol
== htons(ETH_P_IP
))
1911 tx_flags
|= I40E_TX_FLAGS_IPV4
;
1912 else if (protocol
== htons(ETH_P_IPV6
))
1913 tx_flags
|= I40E_TX_FLAGS_IPV6
;
1915 tso
= i40e_tso(tx_ring
, skb
, tx_flags
, protocol
, &hdr_len
,
1916 &cd_type_cmd_tso_mss
, &cd_tunneling
);
1921 tx_flags
|= I40E_TX_FLAGS_TSO
;
1923 if (i40e_chk_linearize(skb
, tx_flags
, hdr_len
))
1924 if (skb_linearize(skb
))
1927 skb_tx_timestamp(skb
);
1929 /* always enable CRC insertion offload */
1930 td_cmd
|= I40E_TX_DESC_CMD_ICRC
;
1932 /* Always offload the checksum, since it's in the data descriptor */
1933 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1934 tx_flags
|= I40E_TX_FLAGS_CSUM
;
1936 i40e_tx_enable_csum(skb
, tx_flags
, &td_cmd
, &td_offset
,
1937 tx_ring
, &cd_tunneling
);
1940 i40e_create_tx_ctx(tx_ring
, cd_type_cmd_tso_mss
,
1941 cd_tunneling
, cd_l2tag2
);
1943 i40e_tx_map(tx_ring
, skb
, first
, tx_flags
, hdr_len
,
1946 i40e_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
1948 return NETDEV_TX_OK
;
1951 dev_kfree_skb_any(skb
);
1952 return NETDEV_TX_OK
;
1956 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1958 * @netdev: network interface device structure
1960 * Returns NETDEV_TX_OK if sent, else an error code
1962 netdev_tx_t
i40evf_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
1964 struct i40evf_adapter
*adapter
= netdev_priv(netdev
);
1965 struct i40e_ring
*tx_ring
= adapter
->tx_rings
[skb
->queue_mapping
];
1967 /* hardware can't handle really short frames, hardware padding works
1970 if (unlikely(skb
->len
< I40E_MIN_TX_LEN
)) {
1971 if (skb_pad(skb
, I40E_MIN_TX_LEN
- skb
->len
))
1972 return NETDEV_TX_OK
;
1973 skb
->len
= I40E_MIN_TX_LEN
;
1974 skb_set_tail_pointer(skb
, I40E_MIN_TX_LEN
);
1977 return i40e_xmit_frame_ring(skb
, tx_ring
);