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Merge tag 'pm+acpi-4.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include <linux/prefetch.h>
28
29 #include "i40evf.h"
30 #include "i40e_prototype.h"
31
32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34 {
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40 }
41
42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
43
44 /**
45 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
46 * @ring: the ring that owns the buffer
47 * @tx_buffer: the buffer to free
48 **/
49 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
50 struct i40e_tx_buffer *tx_buffer)
51 {
52 if (tx_buffer->skb) {
53 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
54 kfree(tx_buffer->raw_buf);
55 else
56 dev_kfree_skb_any(tx_buffer->skb);
57
58 if (dma_unmap_len(tx_buffer, len))
59 dma_unmap_single(ring->dev,
60 dma_unmap_addr(tx_buffer, dma),
61 dma_unmap_len(tx_buffer, len),
62 DMA_TO_DEVICE);
63 } else if (dma_unmap_len(tx_buffer, len)) {
64 dma_unmap_page(ring->dev,
65 dma_unmap_addr(tx_buffer, dma),
66 dma_unmap_len(tx_buffer, len),
67 DMA_TO_DEVICE);
68 }
69 tx_buffer->next_to_watch = NULL;
70 tx_buffer->skb = NULL;
71 dma_unmap_len_set(tx_buffer, len, 0);
72 /* tx_buffer must be completely set up in the transmit path */
73 }
74
75 /**
76 * i40evf_clean_tx_ring - Free any empty Tx buffers
77 * @tx_ring: ring to be cleaned
78 **/
79 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
80 {
81 unsigned long bi_size;
82 u16 i;
83
84 /* ring already cleared, nothing to do */
85 if (!tx_ring->tx_bi)
86 return;
87
88 /* Free all the Tx ring sk_buffs */
89 for (i = 0; i < tx_ring->count; i++)
90 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
91
92 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
93 memset(tx_ring->tx_bi, 0, bi_size);
94
95 /* Zero out the descriptor ring */
96 memset(tx_ring->desc, 0, tx_ring->size);
97
98 tx_ring->next_to_use = 0;
99 tx_ring->next_to_clean = 0;
100
101 if (!tx_ring->netdev)
102 return;
103
104 /* cleanup Tx queue statistics */
105 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
106 tx_ring->queue_index));
107 }
108
109 /**
110 * i40evf_free_tx_resources - Free Tx resources per queue
111 * @tx_ring: Tx descriptor ring for a specific queue
112 *
113 * Free all transmit software resources
114 **/
115 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
116 {
117 i40evf_clean_tx_ring(tx_ring);
118 kfree(tx_ring->tx_bi);
119 tx_ring->tx_bi = NULL;
120
121 if (tx_ring->desc) {
122 dma_free_coherent(tx_ring->dev, tx_ring->size,
123 tx_ring->desc, tx_ring->dma);
124 tx_ring->desc = NULL;
125 }
126 }
127
128 /**
129 * i40e_get_head - Retrieve head from head writeback
130 * @tx_ring: tx ring to fetch head of
131 *
132 * Returns value of Tx ring head based on value stored
133 * in head write-back location
134 **/
135 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
136 {
137 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
138
139 return le32_to_cpu(*(volatile __le32 *)head);
140 }
141
142 /**
143 * i40e_get_tx_pending - how many tx descriptors not processed
144 * @tx_ring: the ring of descriptors
145 *
146 * Since there is no access to the ring head register
147 * in XL710, we need to use our local copies
148 **/
149 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
150 {
151 u32 head, tail;
152
153 head = i40e_get_head(ring);
154 tail = readl(ring->tail);
155
156 if (head != tail)
157 return (head < tail) ?
158 tail - head : (tail + ring->count - head);
159
160 return 0;
161 }
162
163 /**
164 * i40e_check_tx_hang - Is there a hang in the Tx queue
165 * @tx_ring: the ring of descriptors
166 **/
167 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
168 {
169 u32 tx_done = tx_ring->stats.packets;
170 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
171 u32 tx_pending = i40e_get_tx_pending(tx_ring);
172 bool ret = false;
173
174 clear_check_for_tx_hang(tx_ring);
175
176 /* Check for a hung queue, but be thorough. This verifies
177 * that a transmit has been completed since the previous
178 * check AND there is at least one packet pending. The
179 * ARMED bit is set to indicate a potential hang. The
180 * bit is cleared if a pause frame is received to remove
181 * false hang detection due to PFC or 802.3x frames. By
182 * requiring this to fail twice we avoid races with
183 * PFC clearing the ARMED bit and conditions where we
184 * run the check_tx_hang logic with a transmit completion
185 * pending but without time to complete it yet.
186 */
187 if ((tx_done_old == tx_done) && tx_pending) {
188 /* make sure it is true for two checks in a row */
189 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
190 &tx_ring->state);
191 } else if (tx_done_old == tx_done &&
192 (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) {
193 /* update completed stats and disarm the hang check */
194 tx_ring->tx_stats.tx_done_old = tx_done;
195 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
196 }
197
198 return ret;
199 }
200
201 #define WB_STRIDE 0x3
202
203 /**
204 * i40e_clean_tx_irq - Reclaim resources after transmit completes
205 * @tx_ring: tx ring to clean
206 * @budget: how many cleans we're allowed
207 *
208 * Returns true if there's any budget left (e.g. the clean is finished)
209 **/
210 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
211 {
212 u16 i = tx_ring->next_to_clean;
213 struct i40e_tx_buffer *tx_buf;
214 struct i40e_tx_desc *tx_head;
215 struct i40e_tx_desc *tx_desc;
216 unsigned int total_packets = 0;
217 unsigned int total_bytes = 0;
218
219 tx_buf = &tx_ring->tx_bi[i];
220 tx_desc = I40E_TX_DESC(tx_ring, i);
221 i -= tx_ring->count;
222
223 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
224
225 do {
226 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
227
228 /* if next_to_watch is not set then there is no work pending */
229 if (!eop_desc)
230 break;
231
232 /* prevent any other reads prior to eop_desc */
233 read_barrier_depends();
234
235 /* we have caught up to head, no work left to do */
236 if (tx_head == tx_desc)
237 break;
238
239 /* clear next_to_watch to prevent false hangs */
240 tx_buf->next_to_watch = NULL;
241
242 /* update the statistics for this packet */
243 total_bytes += tx_buf->bytecount;
244 total_packets += tx_buf->gso_segs;
245
246 /* free the skb */
247 dev_kfree_skb_any(tx_buf->skb);
248
249 /* unmap skb header data */
250 dma_unmap_single(tx_ring->dev,
251 dma_unmap_addr(tx_buf, dma),
252 dma_unmap_len(tx_buf, len),
253 DMA_TO_DEVICE);
254
255 /* clear tx_buffer data */
256 tx_buf->skb = NULL;
257 dma_unmap_len_set(tx_buf, len, 0);
258
259 /* unmap remaining buffers */
260 while (tx_desc != eop_desc) {
261
262 tx_buf++;
263 tx_desc++;
264 i++;
265 if (unlikely(!i)) {
266 i -= tx_ring->count;
267 tx_buf = tx_ring->tx_bi;
268 tx_desc = I40E_TX_DESC(tx_ring, 0);
269 }
270
271 /* unmap any remaining paged data */
272 if (dma_unmap_len(tx_buf, len)) {
273 dma_unmap_page(tx_ring->dev,
274 dma_unmap_addr(tx_buf, dma),
275 dma_unmap_len(tx_buf, len),
276 DMA_TO_DEVICE);
277 dma_unmap_len_set(tx_buf, len, 0);
278 }
279 }
280
281 /* move us one more past the eop_desc for start of next pkt */
282 tx_buf++;
283 tx_desc++;
284 i++;
285 if (unlikely(!i)) {
286 i -= tx_ring->count;
287 tx_buf = tx_ring->tx_bi;
288 tx_desc = I40E_TX_DESC(tx_ring, 0);
289 }
290
291 /* update budget accounting */
292 budget--;
293 } while (likely(budget));
294
295 i += tx_ring->count;
296 tx_ring->next_to_clean = i;
297 u64_stats_update_begin(&tx_ring->syncp);
298 tx_ring->stats.bytes += total_bytes;
299 tx_ring->stats.packets += total_packets;
300 u64_stats_update_end(&tx_ring->syncp);
301 tx_ring->q_vector->tx.total_bytes += total_bytes;
302 tx_ring->q_vector->tx.total_packets += total_packets;
303
304 if (budget &&
305 !((i & WB_STRIDE) == WB_STRIDE) &&
306 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
307 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
308 tx_ring->arm_wb = true;
309 else
310 tx_ring->arm_wb = false;
311
312 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
313 /* schedule immediate reset if we believe we hung */
314 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
315 " VSI <%d>\n"
316 " Tx Queue <%d>\n"
317 " next_to_use <%x>\n"
318 " next_to_clean <%x>\n",
319 tx_ring->vsi->seid,
320 tx_ring->queue_index,
321 tx_ring->next_to_use, i);
322 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
323 " time_stamp <%lx>\n"
324 " jiffies <%lx>\n",
325 tx_ring->tx_bi[i].time_stamp, jiffies);
326
327 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
328
329 dev_info(tx_ring->dev,
330 "tx hang detected on queue %d, resetting adapter\n",
331 tx_ring->queue_index);
332
333 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
334
335 /* the adapter is about to reset, no point in enabling stuff */
336 return true;
337 }
338
339 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
340 tx_ring->queue_index),
341 total_packets, total_bytes);
342
343 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
344 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
345 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
346 /* Make sure that anybody stopping the queue after this
347 * sees the new next_to_clean.
348 */
349 smp_mb();
350 if (__netif_subqueue_stopped(tx_ring->netdev,
351 tx_ring->queue_index) &&
352 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
353 netif_wake_subqueue(tx_ring->netdev,
354 tx_ring->queue_index);
355 ++tx_ring->tx_stats.restart_queue;
356 }
357 }
358
359 return budget > 0;
360 }
361
362 /**
363 * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
364 * @vsi: the VSI we care about
365 * @q_vector: the vector on which to force writeback
366 *
367 **/
368 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
369 {
370 u32 val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
371 I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
372 I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
373 /* allow 00 to be written to the index */
374
375 wr32(&vsi->back->hw,
376 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
377 val);
378 }
379
380 /**
381 * i40e_set_new_dynamic_itr - Find new ITR level
382 * @rc: structure containing ring performance data
383 *
384 * Stores a new ITR value based on packets and byte counts during
385 * the last interrupt. The advantage of per interrupt computation
386 * is faster updates and more accurate ITR for the current traffic
387 * pattern. Constants in this function were computed based on
388 * theoretical maximum wire speed and thresholds were set based on
389 * testing data as well as attempting to minimize response time
390 * while increasing bulk throughput.
391 **/
392 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
393 {
394 enum i40e_latency_range new_latency_range = rc->latency_range;
395 u32 new_itr = rc->itr;
396 int bytes_per_int;
397
398 if (rc->total_packets == 0 || !rc->itr)
399 return;
400
401 /* simple throttlerate management
402 * 0-10MB/s lowest (100000 ints/s)
403 * 10-20MB/s low (20000 ints/s)
404 * 20-1249MB/s bulk (8000 ints/s)
405 */
406 bytes_per_int = rc->total_bytes / rc->itr;
407 switch (rc->itr) {
408 case I40E_LOWEST_LATENCY:
409 if (bytes_per_int > 10)
410 new_latency_range = I40E_LOW_LATENCY;
411 break;
412 case I40E_LOW_LATENCY:
413 if (bytes_per_int > 20)
414 new_latency_range = I40E_BULK_LATENCY;
415 else if (bytes_per_int <= 10)
416 new_latency_range = I40E_LOWEST_LATENCY;
417 break;
418 case I40E_BULK_LATENCY:
419 if (bytes_per_int <= 20)
420 rc->latency_range = I40E_LOW_LATENCY;
421 break;
422 }
423
424 switch (new_latency_range) {
425 case I40E_LOWEST_LATENCY:
426 new_itr = I40E_ITR_100K;
427 break;
428 case I40E_LOW_LATENCY:
429 new_itr = I40E_ITR_20K;
430 break;
431 case I40E_BULK_LATENCY:
432 new_itr = I40E_ITR_8K;
433 break;
434 default:
435 break;
436 }
437
438 if (new_itr != rc->itr) {
439 /* do an exponential smoothing */
440 new_itr = (10 * new_itr * rc->itr) /
441 ((9 * new_itr) + rc->itr);
442 rc->itr = new_itr & I40E_MAX_ITR;
443 }
444
445 rc->total_bytes = 0;
446 rc->total_packets = 0;
447 }
448
449 /**
450 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
451 * @q_vector: the vector to adjust
452 **/
453 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
454 {
455 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
456 struct i40e_hw *hw = &q_vector->vsi->back->hw;
457 u32 reg_addr;
458 u16 old_itr;
459
460 reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
461 old_itr = q_vector->rx.itr;
462 i40e_set_new_dynamic_itr(&q_vector->rx);
463 if (old_itr != q_vector->rx.itr)
464 wr32(hw, reg_addr, q_vector->rx.itr);
465
466 reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
467 old_itr = q_vector->tx.itr;
468 i40e_set_new_dynamic_itr(&q_vector->tx);
469 if (old_itr != q_vector->tx.itr)
470 wr32(hw, reg_addr, q_vector->tx.itr);
471 }
472
473 /**
474 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
475 * @tx_ring: the tx ring to set up
476 *
477 * Return 0 on success, negative on error
478 **/
479 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
480 {
481 struct device *dev = tx_ring->dev;
482 int bi_size;
483
484 if (!dev)
485 return -ENOMEM;
486
487 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
488 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
489 if (!tx_ring->tx_bi)
490 goto err;
491
492 /* round up to nearest 4K */
493 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
494 /* add u32 for head writeback, align after this takes care of
495 * guaranteeing this is at least one cache line in size
496 */
497 tx_ring->size += sizeof(u32);
498 tx_ring->size = ALIGN(tx_ring->size, 4096);
499 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
500 &tx_ring->dma, GFP_KERNEL);
501 if (!tx_ring->desc) {
502 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
503 tx_ring->size);
504 goto err;
505 }
506
507 tx_ring->next_to_use = 0;
508 tx_ring->next_to_clean = 0;
509 return 0;
510
511 err:
512 kfree(tx_ring->tx_bi);
513 tx_ring->tx_bi = NULL;
514 return -ENOMEM;
515 }
516
517 /**
518 * i40evf_clean_rx_ring - Free Rx buffers
519 * @rx_ring: ring to be cleaned
520 **/
521 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
522 {
523 struct device *dev = rx_ring->dev;
524 struct i40e_rx_buffer *rx_bi;
525 unsigned long bi_size;
526 u16 i;
527
528 /* ring already cleared, nothing to do */
529 if (!rx_ring->rx_bi)
530 return;
531
532 /* Free all the Rx ring sk_buffs */
533 for (i = 0; i < rx_ring->count; i++) {
534 rx_bi = &rx_ring->rx_bi[i];
535 if (rx_bi->dma) {
536 dma_unmap_single(dev,
537 rx_bi->dma,
538 rx_ring->rx_buf_len,
539 DMA_FROM_DEVICE);
540 rx_bi->dma = 0;
541 }
542 if (rx_bi->skb) {
543 dev_kfree_skb(rx_bi->skb);
544 rx_bi->skb = NULL;
545 }
546 if (rx_bi->page) {
547 if (rx_bi->page_dma) {
548 dma_unmap_page(dev,
549 rx_bi->page_dma,
550 PAGE_SIZE / 2,
551 DMA_FROM_DEVICE);
552 rx_bi->page_dma = 0;
553 }
554 __free_page(rx_bi->page);
555 rx_bi->page = NULL;
556 rx_bi->page_offset = 0;
557 }
558 }
559
560 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
561 memset(rx_ring->rx_bi, 0, bi_size);
562
563 /* Zero out the descriptor ring */
564 memset(rx_ring->desc, 0, rx_ring->size);
565
566 rx_ring->next_to_clean = 0;
567 rx_ring->next_to_use = 0;
568 }
569
570 /**
571 * i40evf_free_rx_resources - Free Rx resources
572 * @rx_ring: ring to clean the resources from
573 *
574 * Free all receive software resources
575 **/
576 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
577 {
578 i40evf_clean_rx_ring(rx_ring);
579 kfree(rx_ring->rx_bi);
580 rx_ring->rx_bi = NULL;
581
582 if (rx_ring->desc) {
583 dma_free_coherent(rx_ring->dev, rx_ring->size,
584 rx_ring->desc, rx_ring->dma);
585 rx_ring->desc = NULL;
586 }
587 }
588
589 /**
590 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
591 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
592 *
593 * Returns 0 on success, negative on failure
594 **/
595 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
596 {
597 struct device *dev = rx_ring->dev;
598 int bi_size;
599
600 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
601 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
602 if (!rx_ring->rx_bi)
603 goto err;
604
605 u64_stats_init(&rx_ring->syncp);
606
607 /* Round up to nearest 4K */
608 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
609 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
610 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
611 rx_ring->size = ALIGN(rx_ring->size, 4096);
612 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
613 &rx_ring->dma, GFP_KERNEL);
614
615 if (!rx_ring->desc) {
616 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
617 rx_ring->size);
618 goto err;
619 }
620
621 rx_ring->next_to_clean = 0;
622 rx_ring->next_to_use = 0;
623
624 return 0;
625 err:
626 kfree(rx_ring->rx_bi);
627 rx_ring->rx_bi = NULL;
628 return -ENOMEM;
629 }
630
631 /**
632 * i40e_release_rx_desc - Store the new tail and head values
633 * @rx_ring: ring to bump
634 * @val: new head index
635 **/
636 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
637 {
638 rx_ring->next_to_use = val;
639 /* Force memory writes to complete before letting h/w
640 * know there are new descriptors to fetch. (Only
641 * applicable for weak-ordered memory model archs,
642 * such as IA-64).
643 */
644 wmb();
645 writel(val, rx_ring->tail);
646 }
647
648 /**
649 * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
650 * @rx_ring: ring to place buffers on
651 * @cleaned_count: number of buffers to replace
652 **/
653 void i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
654 {
655 u16 i = rx_ring->next_to_use;
656 union i40e_rx_desc *rx_desc;
657 struct i40e_rx_buffer *bi;
658 struct sk_buff *skb;
659
660 /* do nothing if no valid netdev defined */
661 if (!rx_ring->netdev || !cleaned_count)
662 return;
663
664 while (cleaned_count--) {
665 rx_desc = I40E_RX_DESC(rx_ring, i);
666 bi = &rx_ring->rx_bi[i];
667 skb = bi->skb;
668
669 if (!skb) {
670 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
671 rx_ring->rx_buf_len);
672 if (!skb) {
673 rx_ring->rx_stats.alloc_buff_failed++;
674 goto no_buffers;
675 }
676 /* initialize queue mapping */
677 skb_record_rx_queue(skb, rx_ring->queue_index);
678 bi->skb = skb;
679 }
680
681 if (!bi->dma) {
682 bi->dma = dma_map_single(rx_ring->dev,
683 skb->data,
684 rx_ring->rx_buf_len,
685 DMA_FROM_DEVICE);
686 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
687 rx_ring->rx_stats.alloc_buff_failed++;
688 bi->dma = 0;
689 goto no_buffers;
690 }
691 }
692
693 if (ring_is_ps_enabled(rx_ring)) {
694 if (!bi->page) {
695 bi->page = alloc_page(GFP_ATOMIC);
696 if (!bi->page) {
697 rx_ring->rx_stats.alloc_page_failed++;
698 goto no_buffers;
699 }
700 }
701
702 if (!bi->page_dma) {
703 /* use a half page if we're re-using */
704 bi->page_offset ^= PAGE_SIZE / 2;
705 bi->page_dma = dma_map_page(rx_ring->dev,
706 bi->page,
707 bi->page_offset,
708 PAGE_SIZE / 2,
709 DMA_FROM_DEVICE);
710 if (dma_mapping_error(rx_ring->dev,
711 bi->page_dma)) {
712 rx_ring->rx_stats.alloc_page_failed++;
713 bi->page_dma = 0;
714 goto no_buffers;
715 }
716 }
717
718 /* Refresh the desc even if buffer_addrs didn't change
719 * because each write-back erases this info.
720 */
721 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
722 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
723 } else {
724 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
725 rx_desc->read.hdr_addr = 0;
726 }
727 i++;
728 if (i == rx_ring->count)
729 i = 0;
730 }
731
732 no_buffers:
733 if (rx_ring->next_to_use != i)
734 i40e_release_rx_desc(rx_ring, i);
735 }
736
737 /**
738 * i40e_receive_skb - Send a completed packet up the stack
739 * @rx_ring: rx ring in play
740 * @skb: packet to send up
741 * @vlan_tag: vlan tag for packet
742 **/
743 static void i40e_receive_skb(struct i40e_ring *rx_ring,
744 struct sk_buff *skb, u16 vlan_tag)
745 {
746 struct i40e_q_vector *q_vector = rx_ring->q_vector;
747 struct i40e_vsi *vsi = rx_ring->vsi;
748 u64 flags = vsi->back->flags;
749
750 if (vlan_tag & VLAN_VID_MASK)
751 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
752
753 if (flags & I40E_FLAG_IN_NETPOLL)
754 netif_rx(skb);
755 else
756 napi_gro_receive(&q_vector->napi, skb);
757 }
758
759 /**
760 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
761 * @vsi: the VSI we care about
762 * @skb: skb currently being received and modified
763 * @rx_status: status value of last descriptor in packet
764 * @rx_error: error value of last descriptor in packet
765 * @rx_ptype: ptype value of last descriptor in packet
766 **/
767 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
768 struct sk_buff *skb,
769 u32 rx_status,
770 u32 rx_error,
771 u16 rx_ptype)
772 {
773 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
774 bool ipv4 = false, ipv6 = false;
775 bool ipv4_tunnel, ipv6_tunnel;
776 __wsum rx_udp_csum;
777 struct iphdr *iph;
778 __sum16 csum;
779
780 ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
781 (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
782 ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
783 (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
784
785 skb->ip_summed = CHECKSUM_NONE;
786
787 /* Rx csum enabled and ip headers found? */
788 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
789 return;
790
791 /* did the hardware decode the packet and checksum? */
792 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
793 return;
794
795 /* both known and outer_ip must be set for the below code to work */
796 if (!(decoded.known && decoded.outer_ip))
797 return;
798
799 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
800 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
801 ipv4 = true;
802 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
803 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
804 ipv6 = true;
805
806 if (ipv4 &&
807 (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
808 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
809 goto checksum_fail;
810
811 /* likely incorrect csum if alternate IP extension headers found */
812 if (ipv6 &&
813 rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
814 /* don't increment checksum err here, non-fatal err */
815 return;
816
817 /* there was some L4 error, count error and punt packet to the stack */
818 if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
819 goto checksum_fail;
820
821 /* handle packets that were not able to be checksummed due
822 * to arrival speed, in this case the stack can compute
823 * the csum.
824 */
825 if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
826 return;
827
828 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
829 * it in the driver, hardware does not do it for us.
830 * Since L3L4P bit was set we assume a valid IHL value (>=5)
831 * so the total length of IPv4 header is IHL*4 bytes
832 * The UDP_0 bit *may* bet set if the *inner* header is UDP
833 */
834 if (ipv4_tunnel &&
835 (decoded.inner_prot != I40E_RX_PTYPE_INNER_PROT_UDP) &&
836 !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
837 skb->transport_header = skb->mac_header +
838 sizeof(struct ethhdr) +
839 (ip_hdr(skb)->ihl * 4);
840
841 /* Add 4 bytes for VLAN tagged packets */
842 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
843 skb->protocol == htons(ETH_P_8021AD))
844 ? VLAN_HLEN : 0;
845
846 rx_udp_csum = udp_csum(skb);
847 iph = ip_hdr(skb);
848 csum = csum_tcpudp_magic(
849 iph->saddr, iph->daddr,
850 (skb->len - skb_transport_offset(skb)),
851 IPPROTO_UDP, rx_udp_csum);
852
853 if (udp_hdr(skb)->check != csum)
854 goto checksum_fail;
855 }
856
857 skb->ip_summed = CHECKSUM_UNNECESSARY;
858 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
859
860 return;
861
862 checksum_fail:
863 vsi->back->hw_csum_rx_error++;
864 }
865
866 /**
867 * i40e_rx_hash - returns the hash value from the Rx descriptor
868 * @ring: descriptor ring
869 * @rx_desc: specific descriptor
870 **/
871 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
872 union i40e_rx_desc *rx_desc)
873 {
874 const __le64 rss_mask =
875 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
876 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
877
878 if ((ring->netdev->features & NETIF_F_RXHASH) &&
879 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
880 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
881 else
882 return 0;
883 }
884
885 /**
886 * i40e_ptype_to_hash - get a hash type
887 * @ptype: the ptype value from the descriptor
888 *
889 * Returns a hash type to be used by skb_set_hash
890 **/
891 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
892 {
893 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
894
895 if (!decoded.known)
896 return PKT_HASH_TYPE_NONE;
897
898 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
899 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
900 return PKT_HASH_TYPE_L4;
901 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
902 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
903 return PKT_HASH_TYPE_L3;
904 else
905 return PKT_HASH_TYPE_L2;
906 }
907
908 /**
909 * i40e_clean_rx_irq - Reclaim resources after receive completes
910 * @rx_ring: rx ring to clean
911 * @budget: how many cleans we're allowed
912 *
913 * Returns true if there's any budget left (e.g. the clean is finished)
914 **/
915 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
916 {
917 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
918 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
919 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
920 const int current_node = numa_node_id();
921 struct i40e_vsi *vsi = rx_ring->vsi;
922 u16 i = rx_ring->next_to_clean;
923 union i40e_rx_desc *rx_desc;
924 u32 rx_error, rx_status;
925 u8 rx_ptype;
926 u64 qword;
927
928 rx_desc = I40E_RX_DESC(rx_ring, i);
929 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
930 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
931 I40E_RXD_QW1_STATUS_SHIFT;
932
933 while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
934 union i40e_rx_desc *next_rxd;
935 struct i40e_rx_buffer *rx_bi;
936 struct sk_buff *skb;
937 u16 vlan_tag;
938 rx_bi = &rx_ring->rx_bi[i];
939 skb = rx_bi->skb;
940 prefetch(skb->data);
941
942 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
943 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
944 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
945 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
946 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
947 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
948
949 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
950 I40E_RXD_QW1_ERROR_SHIFT;
951 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
952 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
953
954 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
955 I40E_RXD_QW1_PTYPE_SHIFT;
956 rx_bi->skb = NULL;
957
958 /* This memory barrier is needed to keep us from reading
959 * any other fields out of the rx_desc until we know the
960 * STATUS_DD bit is set
961 */
962 rmb();
963
964 /* Get the header and possibly the whole packet
965 * If this is an skb from previous receive dma will be 0
966 */
967 if (rx_bi->dma) {
968 u16 len;
969
970 if (rx_hbo)
971 len = I40E_RX_HDR_SIZE;
972 else if (rx_sph)
973 len = rx_header_len;
974 else if (rx_packet_len)
975 len = rx_packet_len; /* 1buf/no split found */
976 else
977 len = rx_header_len; /* split always mode */
978
979 skb_put(skb, len);
980 dma_unmap_single(rx_ring->dev,
981 rx_bi->dma,
982 rx_ring->rx_buf_len,
983 DMA_FROM_DEVICE);
984 rx_bi->dma = 0;
985 }
986
987 /* Get the rest of the data if this was a header split */
988 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
989
990 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
991 rx_bi->page,
992 rx_bi->page_offset,
993 rx_packet_len);
994
995 skb->len += rx_packet_len;
996 skb->data_len += rx_packet_len;
997 skb->truesize += rx_packet_len;
998
999 if ((page_count(rx_bi->page) == 1) &&
1000 (page_to_nid(rx_bi->page) == current_node))
1001 get_page(rx_bi->page);
1002 else
1003 rx_bi->page = NULL;
1004
1005 dma_unmap_page(rx_ring->dev,
1006 rx_bi->page_dma,
1007 PAGE_SIZE / 2,
1008 DMA_FROM_DEVICE);
1009 rx_bi->page_dma = 0;
1010 }
1011 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
1012
1013 if (unlikely(
1014 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1015 struct i40e_rx_buffer *next_buffer;
1016
1017 next_buffer = &rx_ring->rx_bi[i];
1018
1019 if (ring_is_ps_enabled(rx_ring)) {
1020 rx_bi->skb = next_buffer->skb;
1021 rx_bi->dma = next_buffer->dma;
1022 next_buffer->skb = skb;
1023 next_buffer->dma = 0;
1024 }
1025 rx_ring->rx_stats.non_eop_descs++;
1026 goto next_desc;
1027 }
1028
1029 /* ERR_MASK will only have valid bits if EOP set */
1030 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1031 dev_kfree_skb_any(skb);
1032 /* TODO: shouldn't we increment a counter indicating the
1033 * drop?
1034 */
1035 goto next_desc;
1036 }
1037
1038 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1039 i40e_ptype_to_hash(rx_ptype));
1040 /* probably a little skewed due to removing CRC */
1041 total_rx_bytes += skb->len;
1042 total_rx_packets++;
1043
1044 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1045
1046 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1047
1048 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1049 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1050 : 0;
1051 i40e_receive_skb(rx_ring, skb, vlan_tag);
1052
1053 rx_ring->netdev->last_rx = jiffies;
1054 budget--;
1055 next_desc:
1056 rx_desc->wb.qword1.status_error_len = 0;
1057 if (!budget)
1058 break;
1059
1060 cleaned_count++;
1061 /* return some buffers to hardware, one at a time is too slow */
1062 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1063 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1064 cleaned_count = 0;
1065 }
1066
1067 /* use prefetched values */
1068 rx_desc = next_rxd;
1069 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1070 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1071 I40E_RXD_QW1_STATUS_SHIFT;
1072 }
1073
1074 rx_ring->next_to_clean = i;
1075 u64_stats_update_begin(&rx_ring->syncp);
1076 rx_ring->stats.packets += total_rx_packets;
1077 rx_ring->stats.bytes += total_rx_bytes;
1078 u64_stats_update_end(&rx_ring->syncp);
1079 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1080 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1081
1082 if (cleaned_count)
1083 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1084
1085 return budget > 0;
1086 }
1087
1088 /**
1089 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1090 * @napi: napi struct with our devices info in it
1091 * @budget: amount of work driver is allowed to do this pass, in packets
1092 *
1093 * This function will clean all queues associated with a q_vector.
1094 *
1095 * Returns the amount of work done
1096 **/
1097 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1098 {
1099 struct i40e_q_vector *q_vector =
1100 container_of(napi, struct i40e_q_vector, napi);
1101 struct i40e_vsi *vsi = q_vector->vsi;
1102 struct i40e_ring *ring;
1103 bool clean_complete = true;
1104 bool arm_wb = false;
1105 int budget_per_ring;
1106
1107 if (test_bit(__I40E_DOWN, &vsi->state)) {
1108 napi_complete(napi);
1109 return 0;
1110 }
1111
1112 /* Since the actual Tx work is minimal, we can give the Tx a larger
1113 * budget and be more aggressive about cleaning up the Tx descriptors.
1114 */
1115 i40e_for_each_ring(ring, q_vector->tx) {
1116 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1117 arm_wb |= ring->arm_wb;
1118 }
1119
1120 /* We attempt to distribute budget to each Rx queue fairly, but don't
1121 * allow the budget to go below 1 because that would exit polling early.
1122 */
1123 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1124
1125 i40e_for_each_ring(ring, q_vector->rx)
1126 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring);
1127
1128 /* If work not completed, return budget and polling will return */
1129 if (!clean_complete) {
1130 if (arm_wb)
1131 i40e_force_wb(vsi, q_vector);
1132 return budget;
1133 }
1134
1135 /* Work is done so exit the polling mode and re-enable the interrupt */
1136 napi_complete(napi);
1137 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1138 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1139 i40e_update_dynamic_itr(q_vector);
1140
1141 if (!test_bit(__I40E_DOWN, &vsi->state))
1142 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1143
1144 return 0;
1145 }
1146
1147 /**
1148 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1149 * @skb: send buffer
1150 * @tx_ring: ring to send buffer on
1151 * @flags: the tx flags to be set
1152 *
1153 * Checks the skb and set up correspondingly several generic transmit flags
1154 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1155 *
1156 * Returns error code indicate the frame should be dropped upon error and the
1157 * otherwise returns 0 to indicate the flags has been set properly.
1158 **/
1159 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1160 struct i40e_ring *tx_ring,
1161 u32 *flags)
1162 {
1163 __be16 protocol = skb->protocol;
1164 u32 tx_flags = 0;
1165
1166 /* if we have a HW VLAN tag being added, default to the HW one */
1167 if (skb_vlan_tag_present(skb)) {
1168 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1169 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1170 /* else if it is a SW VLAN, check the next protocol and store the tag */
1171 } else if (protocol == htons(ETH_P_8021Q)) {
1172 struct vlan_hdr *vhdr, _vhdr;
1173 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1174 if (!vhdr)
1175 return -EINVAL;
1176
1177 protocol = vhdr->h_vlan_encapsulated_proto;
1178 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1179 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1180 }
1181
1182 *flags = tx_flags;
1183 return 0;
1184 }
1185
1186 /**
1187 * i40e_tso - set up the tso context descriptor
1188 * @tx_ring: ptr to the ring to send
1189 * @skb: ptr to the skb we're sending
1190 * @tx_flags: the collected send information
1191 * @protocol: the send protocol
1192 * @hdr_len: ptr to the size of the packet header
1193 * @cd_tunneling: ptr to context descriptor bits
1194 *
1195 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1196 **/
1197 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1198 u32 tx_flags, __be16 protocol, u8 *hdr_len,
1199 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1200 {
1201 u32 cd_cmd, cd_tso_len, cd_mss;
1202 struct ipv6hdr *ipv6h;
1203 struct tcphdr *tcph;
1204 struct iphdr *iph;
1205 u32 l4len;
1206 int err;
1207
1208 if (!skb_is_gso(skb))
1209 return 0;
1210
1211 err = skb_cow_head(skb, 0);
1212 if (err < 0)
1213 return err;
1214
1215 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1216 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1217
1218 if (iph->version == 4) {
1219 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1220 iph->tot_len = 0;
1221 iph->check = 0;
1222 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1223 0, IPPROTO_TCP, 0);
1224 } else if (ipv6h->version == 6) {
1225 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1226 ipv6h->payload_len = 0;
1227 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1228 0, IPPROTO_TCP, 0);
1229 }
1230
1231 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1232 *hdr_len = (skb->encapsulation
1233 ? (skb_inner_transport_header(skb) - skb->data)
1234 : skb_transport_offset(skb)) + l4len;
1235
1236 /* find the field values */
1237 cd_cmd = I40E_TX_CTX_DESC_TSO;
1238 cd_tso_len = skb->len - *hdr_len;
1239 cd_mss = skb_shinfo(skb)->gso_size;
1240 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1241 ((u64)cd_tso_len <<
1242 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1243 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1244 return 1;
1245 }
1246
1247 /**
1248 * i40e_tx_enable_csum - Enable Tx checksum offloads
1249 * @skb: send buffer
1250 * @tx_flags: Tx flags currently set
1251 * @td_cmd: Tx descriptor command bits to set
1252 * @td_offset: Tx descriptor header offsets to set
1253 * @cd_tunneling: ptr to context desc bits
1254 **/
1255 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1256 u32 *td_cmd, u32 *td_offset,
1257 struct i40e_ring *tx_ring,
1258 u32 *cd_tunneling)
1259 {
1260 struct ipv6hdr *this_ipv6_hdr;
1261 unsigned int this_tcp_hdrlen;
1262 struct iphdr *this_ip_hdr;
1263 u32 network_hdr_len;
1264 u8 l4_hdr = 0;
1265
1266 if (skb->encapsulation) {
1267 network_hdr_len = skb_inner_network_header_len(skb);
1268 this_ip_hdr = inner_ip_hdr(skb);
1269 this_ipv6_hdr = inner_ipv6_hdr(skb);
1270 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1271
1272 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1273
1274 if (tx_flags & I40E_TX_FLAGS_TSO) {
1275 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1276 ip_hdr(skb)->check = 0;
1277 } else {
1278 *cd_tunneling |=
1279 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1280 }
1281 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1282 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1283 if (tx_flags & I40E_TX_FLAGS_TSO)
1284 ip_hdr(skb)->check = 0;
1285 }
1286
1287 /* Now set the ctx descriptor fields */
1288 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1289 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1290 I40E_TXD_CTX_UDP_TUNNELING |
1291 ((skb_inner_network_offset(skb) -
1292 skb_transport_offset(skb)) >> 1) <<
1293 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1294 if (this_ip_hdr->version == 6) {
1295 tx_flags &= ~I40E_TX_FLAGS_IPV4;
1296 tx_flags |= I40E_TX_FLAGS_IPV6;
1297 }
1298
1299
1300 } else {
1301 network_hdr_len = skb_network_header_len(skb);
1302 this_ip_hdr = ip_hdr(skb);
1303 this_ipv6_hdr = ipv6_hdr(skb);
1304 this_tcp_hdrlen = tcp_hdrlen(skb);
1305 }
1306
1307 /* Enable IP checksum offloads */
1308 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1309 l4_hdr = this_ip_hdr->protocol;
1310 /* the stack computes the IP header already, the only time we
1311 * need the hardware to recompute it is in the case of TSO.
1312 */
1313 if (tx_flags & I40E_TX_FLAGS_TSO) {
1314 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1315 this_ip_hdr->check = 0;
1316 } else {
1317 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1318 }
1319 /* Now set the td_offset for IP header length */
1320 *td_offset = (network_hdr_len >> 2) <<
1321 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1322 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1323 l4_hdr = this_ipv6_hdr->nexthdr;
1324 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1325 /* Now set the td_offset for IP header length */
1326 *td_offset = (network_hdr_len >> 2) <<
1327 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1328 }
1329 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1330 *td_offset |= (skb_network_offset(skb) >> 1) <<
1331 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1332
1333 /* Enable L4 checksum offloads */
1334 switch (l4_hdr) {
1335 case IPPROTO_TCP:
1336 /* enable checksum offloads */
1337 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1338 *td_offset |= (this_tcp_hdrlen >> 2) <<
1339 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1340 break;
1341 case IPPROTO_SCTP:
1342 /* enable SCTP checksum offload */
1343 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1344 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1345 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1346 break;
1347 case IPPROTO_UDP:
1348 /* enable UDP checksum offload */
1349 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1350 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1351 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1352 break;
1353 default:
1354 break;
1355 }
1356 }
1357
1358 /**
1359 * i40e_create_tx_ctx Build the Tx context descriptor
1360 * @tx_ring: ring to create the descriptor on
1361 * @cd_type_cmd_tso_mss: Quad Word 1
1362 * @cd_tunneling: Quad Word 0 - bits 0-31
1363 * @cd_l2tag2: Quad Word 0 - bits 32-63
1364 **/
1365 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1366 const u64 cd_type_cmd_tso_mss,
1367 const u32 cd_tunneling, const u32 cd_l2tag2)
1368 {
1369 struct i40e_tx_context_desc *context_desc;
1370 int i = tx_ring->next_to_use;
1371
1372 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1373 !cd_tunneling && !cd_l2tag2)
1374 return;
1375
1376 /* grab the next descriptor */
1377 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1378
1379 i++;
1380 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1381
1382 /* cpu_to_le32 and assign to struct fields */
1383 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1384 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1385 context_desc->rsvd = cpu_to_le16(0);
1386 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1387 }
1388
1389 /**
1390 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1391 * @skb: send buffer
1392 * @tx_flags: collected send information
1393 * @hdr_len: size of the packet header
1394 *
1395 * Note: Our HW can't scatter-gather more than 8 fragments to build
1396 * a packet on the wire and so we need to figure out the cases where we
1397 * need to linearize the skb.
1398 **/
1399 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags,
1400 const u8 hdr_len)
1401 {
1402 struct skb_frag_struct *frag;
1403 bool linearize = false;
1404 unsigned int size = 0;
1405 u16 num_frags;
1406 u16 gso_segs;
1407
1408 num_frags = skb_shinfo(skb)->nr_frags;
1409 gso_segs = skb_shinfo(skb)->gso_segs;
1410
1411 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1412 u16 j = 1;
1413
1414 if (num_frags < (I40E_MAX_BUFFER_TXD))
1415 goto linearize_chk_done;
1416 /* try the simple math, if we have too many frags per segment */
1417 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1418 I40E_MAX_BUFFER_TXD) {
1419 linearize = true;
1420 goto linearize_chk_done;
1421 }
1422 frag = &skb_shinfo(skb)->frags[0];
1423 size = hdr_len;
1424 /* we might still have more fragments per segment */
1425 do {
1426 size += skb_frag_size(frag);
1427 frag++; j++;
1428 if (j == I40E_MAX_BUFFER_TXD) {
1429 if (size < skb_shinfo(skb)->gso_size) {
1430 linearize = true;
1431 break;
1432 }
1433 j = 1;
1434 size -= skb_shinfo(skb)->gso_size;
1435 if (size)
1436 j++;
1437 size += hdr_len;
1438 }
1439 num_frags--;
1440 } while (num_frags);
1441 } else {
1442 if (num_frags >= I40E_MAX_BUFFER_TXD)
1443 linearize = true;
1444 }
1445
1446 linearize_chk_done:
1447 return linearize;
1448 }
1449
1450 /**
1451 * i40e_tx_map - Build the Tx descriptor
1452 * @tx_ring: ring to send buffer on
1453 * @skb: send buffer
1454 * @first: first buffer info buffer to use
1455 * @tx_flags: collected send information
1456 * @hdr_len: size of the packet header
1457 * @td_cmd: the command field in the descriptor
1458 * @td_offset: offset for checksum or crc
1459 **/
1460 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1461 struct i40e_tx_buffer *first, u32 tx_flags,
1462 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1463 {
1464 unsigned int data_len = skb->data_len;
1465 unsigned int size = skb_headlen(skb);
1466 struct skb_frag_struct *frag;
1467 struct i40e_tx_buffer *tx_bi;
1468 struct i40e_tx_desc *tx_desc;
1469 u16 i = tx_ring->next_to_use;
1470 u32 td_tag = 0;
1471 dma_addr_t dma;
1472 u16 gso_segs;
1473
1474 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1475 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1476 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1477 I40E_TX_FLAGS_VLAN_SHIFT;
1478 }
1479
1480 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1481 gso_segs = skb_shinfo(skb)->gso_segs;
1482 else
1483 gso_segs = 1;
1484
1485 /* multiply data chunks by size of headers */
1486 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1487 first->gso_segs = gso_segs;
1488 first->skb = skb;
1489 first->tx_flags = tx_flags;
1490
1491 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1492
1493 tx_desc = I40E_TX_DESC(tx_ring, i);
1494 tx_bi = first;
1495
1496 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1497 if (dma_mapping_error(tx_ring->dev, dma))
1498 goto dma_error;
1499
1500 /* record length, and DMA address */
1501 dma_unmap_len_set(tx_bi, len, size);
1502 dma_unmap_addr_set(tx_bi, dma, dma);
1503
1504 tx_desc->buffer_addr = cpu_to_le64(dma);
1505
1506 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1507 tx_desc->cmd_type_offset_bsz =
1508 build_ctob(td_cmd, td_offset,
1509 I40E_MAX_DATA_PER_TXD, td_tag);
1510
1511 tx_desc++;
1512 i++;
1513 if (i == tx_ring->count) {
1514 tx_desc = I40E_TX_DESC(tx_ring, 0);
1515 i = 0;
1516 }
1517
1518 dma += I40E_MAX_DATA_PER_TXD;
1519 size -= I40E_MAX_DATA_PER_TXD;
1520
1521 tx_desc->buffer_addr = cpu_to_le64(dma);
1522 }
1523
1524 if (likely(!data_len))
1525 break;
1526
1527 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1528 size, td_tag);
1529
1530 tx_desc++;
1531 i++;
1532 if (i == tx_ring->count) {
1533 tx_desc = I40E_TX_DESC(tx_ring, 0);
1534 i = 0;
1535 }
1536
1537 size = skb_frag_size(frag);
1538 data_len -= size;
1539
1540 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1541 DMA_TO_DEVICE);
1542
1543 tx_bi = &tx_ring->tx_bi[i];
1544 }
1545
1546 /* Place RS bit on last descriptor of any packet that spans across the
1547 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1548 */
1549 #define WB_STRIDE 0x3
1550 if (((i & WB_STRIDE) != WB_STRIDE) &&
1551 (first <= &tx_ring->tx_bi[i]) &&
1552 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1553 tx_desc->cmd_type_offset_bsz =
1554 build_ctob(td_cmd, td_offset, size, td_tag) |
1555 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1556 I40E_TXD_QW1_CMD_SHIFT);
1557 } else {
1558 tx_desc->cmd_type_offset_bsz =
1559 build_ctob(td_cmd, td_offset, size, td_tag) |
1560 cpu_to_le64((u64)I40E_TXD_CMD <<
1561 I40E_TXD_QW1_CMD_SHIFT);
1562 }
1563
1564 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1565 tx_ring->queue_index),
1566 first->bytecount);
1567
1568 /* set the timestamp */
1569 first->time_stamp = jiffies;
1570
1571 /* Force memory writes to complete before letting h/w
1572 * know there are new descriptors to fetch. (Only
1573 * applicable for weak-ordered memory model archs,
1574 * such as IA-64).
1575 */
1576 wmb();
1577
1578 /* set next_to_watch value indicating a packet is present */
1579 first->next_to_watch = tx_desc;
1580
1581 i++;
1582 if (i == tx_ring->count)
1583 i = 0;
1584
1585 tx_ring->next_to_use = i;
1586
1587 /* notify HW of packet */
1588 writel(i, tx_ring->tail);
1589
1590 return;
1591
1592 dma_error:
1593 dev_info(tx_ring->dev, "TX DMA map failed\n");
1594
1595 /* clear dma mappings for failed tx_bi map */
1596 for (;;) {
1597 tx_bi = &tx_ring->tx_bi[i];
1598 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1599 if (tx_bi == first)
1600 break;
1601 if (i == 0)
1602 i = tx_ring->count;
1603 i--;
1604 }
1605
1606 tx_ring->next_to_use = i;
1607 }
1608
1609 /**
1610 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1611 * @tx_ring: the ring to be checked
1612 * @size: the size buffer we want to assure is available
1613 *
1614 * Returns -EBUSY if a stop is needed, else 0
1615 **/
1616 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1617 {
1618 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1619 /* Memory barrier before checking head and tail */
1620 smp_mb();
1621
1622 /* Check again in a case another CPU has just made room available. */
1623 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1624 return -EBUSY;
1625
1626 /* A reprieve! - use start_queue because it doesn't call schedule */
1627 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1628 ++tx_ring->tx_stats.restart_queue;
1629 return 0;
1630 }
1631
1632 /**
1633 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1634 * @tx_ring: the ring to be checked
1635 * @size: the size buffer we want to assure is available
1636 *
1637 * Returns 0 if stop is not needed
1638 **/
1639 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1640 {
1641 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1642 return 0;
1643 return __i40e_maybe_stop_tx(tx_ring, size);
1644 }
1645
1646 /**
1647 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1648 * @skb: send buffer
1649 * @tx_ring: ring to send buffer on
1650 *
1651 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1652 * there is not enough descriptors available in this ring since we need at least
1653 * one descriptor.
1654 **/
1655 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1656 struct i40e_ring *tx_ring)
1657 {
1658 unsigned int f;
1659 int count = 0;
1660
1661 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1662 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1663 * + 4 desc gap to avoid the cache line where head is,
1664 * + 1 desc for context descriptor,
1665 * otherwise try next time
1666 */
1667 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1668 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1669
1670 count += TXD_USE_COUNT(skb_headlen(skb));
1671 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1672 tx_ring->tx_stats.tx_busy++;
1673 return 0;
1674 }
1675 return count;
1676 }
1677
1678 /**
1679 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1680 * @skb: send buffer
1681 * @tx_ring: ring to send buffer on
1682 *
1683 * Returns NETDEV_TX_OK if sent, else an error code
1684 **/
1685 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1686 struct i40e_ring *tx_ring)
1687 {
1688 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1689 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1690 struct i40e_tx_buffer *first;
1691 u32 td_offset = 0;
1692 u32 tx_flags = 0;
1693 __be16 protocol;
1694 u32 td_cmd = 0;
1695 u8 hdr_len = 0;
1696 int tso;
1697 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1698 return NETDEV_TX_BUSY;
1699
1700 /* prepare the xmit flags */
1701 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1702 goto out_drop;
1703
1704 /* obtain protocol of skb */
1705 protocol = vlan_get_protocol(skb);
1706
1707 /* record the location of the first descriptor for this packet */
1708 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1709
1710 /* setup IPv4/IPv6 offloads */
1711 if (protocol == htons(ETH_P_IP))
1712 tx_flags |= I40E_TX_FLAGS_IPV4;
1713 else if (protocol == htons(ETH_P_IPV6))
1714 tx_flags |= I40E_TX_FLAGS_IPV6;
1715
1716 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1717 &cd_type_cmd_tso_mss, &cd_tunneling);
1718
1719 if (tso < 0)
1720 goto out_drop;
1721 else if (tso)
1722 tx_flags |= I40E_TX_FLAGS_TSO;
1723
1724 if (i40e_chk_linearize(skb, tx_flags, hdr_len))
1725 if (skb_linearize(skb))
1726 goto out_drop;
1727
1728 skb_tx_timestamp(skb);
1729
1730 /* always enable CRC insertion offload */
1731 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1732
1733 /* Always offload the checksum, since it's in the data descriptor */
1734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1735 tx_flags |= I40E_TX_FLAGS_CSUM;
1736
1737 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1738 tx_ring, &cd_tunneling);
1739 }
1740
1741 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1742 cd_tunneling, cd_l2tag2);
1743
1744 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1745 td_cmd, td_offset);
1746
1747 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1748
1749 return NETDEV_TX_OK;
1750
1751 out_drop:
1752 dev_kfree_skb_any(skb);
1753 return NETDEV_TX_OK;
1754 }
1755
1756 /**
1757 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1758 * @skb: send buffer
1759 * @netdev: network interface device structure
1760 *
1761 * Returns NETDEV_TX_OK if sent, else an error code
1762 **/
1763 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1764 {
1765 struct i40evf_adapter *adapter = netdev_priv(netdev);
1766 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1767
1768 /* hardware can't handle really short frames, hardware padding works
1769 * beyond this point
1770 */
1771 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1772 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1773 return NETDEV_TX_OK;
1774 skb->len = I40E_MIN_TX_LEN;
1775 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1776 }
1777
1778 return i40e_xmit_frame_ring(skb, tx_ring);
1779 }
Linux kernel - Deliverables
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