1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
30 #include "i40e_prototype.h"
32 static inline __le64
build_ctob(u32 td_cmd
, u32 td_offset
, unsigned int size
,
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA
|
36 ((u64
)td_cmd
<< I40E_TXD_QW1_CMD_SHIFT
) |
37 ((u64
)td_offset
<< I40E_TXD_QW1_OFFSET_SHIFT
) |
38 ((u64
)size
<< I40E_TXD_QW1_TX_BUF_SZ_SHIFT
) |
39 ((u64
)td_tag
<< I40E_TXD_QW1_L2TAG1_SHIFT
));
42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
45 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
46 * @ring: the ring that owns the buffer
47 * @tx_buffer: the buffer to free
49 static void i40e_unmap_and_free_tx_resource(struct i40e_ring
*ring
,
50 struct i40e_tx_buffer
*tx_buffer
)
53 if (tx_buffer
->tx_flags
& I40E_TX_FLAGS_FD_SB
)
54 kfree(tx_buffer
->raw_buf
);
56 dev_kfree_skb_any(tx_buffer
->skb
);
58 if (dma_unmap_len(tx_buffer
, len
))
59 dma_unmap_single(ring
->dev
,
60 dma_unmap_addr(tx_buffer
, dma
),
61 dma_unmap_len(tx_buffer
, len
),
63 } else if (dma_unmap_len(tx_buffer
, len
)) {
64 dma_unmap_page(ring
->dev
,
65 dma_unmap_addr(tx_buffer
, dma
),
66 dma_unmap_len(tx_buffer
, len
),
69 tx_buffer
->next_to_watch
= NULL
;
70 tx_buffer
->skb
= NULL
;
71 dma_unmap_len_set(tx_buffer
, len
, 0);
72 /* tx_buffer must be completely set up in the transmit path */
76 * i40evf_clean_tx_ring - Free any empty Tx buffers
77 * @tx_ring: ring to be cleaned
79 void i40evf_clean_tx_ring(struct i40e_ring
*tx_ring
)
81 unsigned long bi_size
;
84 /* ring already cleared, nothing to do */
88 /* Free all the Tx ring sk_buffs */
89 for (i
= 0; i
< tx_ring
->count
; i
++)
90 i40e_unmap_and_free_tx_resource(tx_ring
, &tx_ring
->tx_bi
[i
]);
92 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
93 memset(tx_ring
->tx_bi
, 0, bi_size
);
95 /* Zero out the descriptor ring */
96 memset(tx_ring
->desc
, 0, tx_ring
->size
);
98 tx_ring
->next_to_use
= 0;
99 tx_ring
->next_to_clean
= 0;
101 if (!tx_ring
->netdev
)
104 /* cleanup Tx queue statistics */
105 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring
->netdev
,
106 tx_ring
->queue_index
));
110 * i40evf_free_tx_resources - Free Tx resources per queue
111 * @tx_ring: Tx descriptor ring for a specific queue
113 * Free all transmit software resources
115 void i40evf_free_tx_resources(struct i40e_ring
*tx_ring
)
117 i40evf_clean_tx_ring(tx_ring
);
118 kfree(tx_ring
->tx_bi
);
119 tx_ring
->tx_bi
= NULL
;
122 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
123 tx_ring
->desc
, tx_ring
->dma
);
124 tx_ring
->desc
= NULL
;
129 * i40e_get_head - Retrieve head from head writeback
130 * @tx_ring: tx ring to fetch head of
132 * Returns value of Tx ring head based on value stored
133 * in head write-back location
135 static inline u32
i40e_get_head(struct i40e_ring
*tx_ring
)
137 void *head
= (struct i40e_tx_desc
*)tx_ring
->desc
+ tx_ring
->count
;
139 return le32_to_cpu(*(volatile __le32
*)head
);
143 * i40e_get_tx_pending - how many tx descriptors not processed
144 * @tx_ring: the ring of descriptors
146 * Since there is no access to the ring head register
147 * in XL710, we need to use our local copies
149 static u32
i40e_get_tx_pending(struct i40e_ring
*ring
)
153 head
= i40e_get_head(ring
);
154 tail
= readl(ring
->tail
);
157 return (head
< tail
) ?
158 tail
- head
: (tail
+ ring
->count
- head
);
164 * i40e_check_tx_hang - Is there a hang in the Tx queue
165 * @tx_ring: the ring of descriptors
167 static bool i40e_check_tx_hang(struct i40e_ring
*tx_ring
)
169 u32 tx_done
= tx_ring
->stats
.packets
;
170 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
171 u32 tx_pending
= i40e_get_tx_pending(tx_ring
);
174 clear_check_for_tx_hang(tx_ring
);
176 /* Check for a hung queue, but be thorough. This verifies
177 * that a transmit has been completed since the previous
178 * check AND there is at least one packet pending. The
179 * ARMED bit is set to indicate a potential hang. The
180 * bit is cleared if a pause frame is received to remove
181 * false hang detection due to PFC or 802.3x frames. By
182 * requiring this to fail twice we avoid races with
183 * PFC clearing the ARMED bit and conditions where we
184 * run the check_tx_hang logic with a transmit completion
185 * pending but without time to complete it yet.
187 if ((tx_done_old
== tx_done
) && tx_pending
) {
188 /* make sure it is true for two checks in a row */
189 ret
= test_and_set_bit(__I40E_HANG_CHECK_ARMED
,
191 } else if (tx_done_old
== tx_done
&&
192 (tx_pending
< I40E_MIN_DESC_PENDING
) && (tx_pending
> 0)) {
193 /* update completed stats and disarm the hang check */
194 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
195 clear_bit(__I40E_HANG_CHECK_ARMED
, &tx_ring
->state
);
201 #define WB_STRIDE 0x3
204 * i40e_clean_tx_irq - Reclaim resources after transmit completes
205 * @tx_ring: tx ring to clean
206 * @budget: how many cleans we're allowed
208 * Returns true if there's any budget left (e.g. the clean is finished)
210 static bool i40e_clean_tx_irq(struct i40e_ring
*tx_ring
, int budget
)
212 u16 i
= tx_ring
->next_to_clean
;
213 struct i40e_tx_buffer
*tx_buf
;
214 struct i40e_tx_desc
*tx_head
;
215 struct i40e_tx_desc
*tx_desc
;
216 unsigned int total_packets
= 0;
217 unsigned int total_bytes
= 0;
219 tx_buf
= &tx_ring
->tx_bi
[i
];
220 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
223 tx_head
= I40E_TX_DESC(tx_ring
, i40e_get_head(tx_ring
));
226 struct i40e_tx_desc
*eop_desc
= tx_buf
->next_to_watch
;
228 /* if next_to_watch is not set then there is no work pending */
232 /* prevent any other reads prior to eop_desc */
233 read_barrier_depends();
235 /* we have caught up to head, no work left to do */
236 if (tx_head
== tx_desc
)
239 /* clear next_to_watch to prevent false hangs */
240 tx_buf
->next_to_watch
= NULL
;
242 /* update the statistics for this packet */
243 total_bytes
+= tx_buf
->bytecount
;
244 total_packets
+= tx_buf
->gso_segs
;
247 dev_kfree_skb_any(tx_buf
->skb
);
249 /* unmap skb header data */
250 dma_unmap_single(tx_ring
->dev
,
251 dma_unmap_addr(tx_buf
, dma
),
252 dma_unmap_len(tx_buf
, len
),
255 /* clear tx_buffer data */
257 dma_unmap_len_set(tx_buf
, len
, 0);
259 /* unmap remaining buffers */
260 while (tx_desc
!= eop_desc
) {
267 tx_buf
= tx_ring
->tx_bi
;
268 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
271 /* unmap any remaining paged data */
272 if (dma_unmap_len(tx_buf
, len
)) {
273 dma_unmap_page(tx_ring
->dev
,
274 dma_unmap_addr(tx_buf
, dma
),
275 dma_unmap_len(tx_buf
, len
),
277 dma_unmap_len_set(tx_buf
, len
, 0);
281 /* move us one more past the eop_desc for start of next pkt */
287 tx_buf
= tx_ring
->tx_bi
;
288 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
291 /* update budget accounting */
293 } while (likely(budget
));
296 tx_ring
->next_to_clean
= i
;
297 u64_stats_update_begin(&tx_ring
->syncp
);
298 tx_ring
->stats
.bytes
+= total_bytes
;
299 tx_ring
->stats
.packets
+= total_packets
;
300 u64_stats_update_end(&tx_ring
->syncp
);
301 tx_ring
->q_vector
->tx
.total_bytes
+= total_bytes
;
302 tx_ring
->q_vector
->tx
.total_packets
+= total_packets
;
305 !((i
& WB_STRIDE
) == WB_STRIDE
) &&
306 !test_bit(__I40E_DOWN
, &tx_ring
->vsi
->state
) &&
307 (I40E_DESC_UNUSED(tx_ring
) != tx_ring
->count
))
308 tx_ring
->arm_wb
= true;
310 tx_ring
->arm_wb
= false;
312 if (check_for_tx_hang(tx_ring
) && i40e_check_tx_hang(tx_ring
)) {
313 /* schedule immediate reset if we believe we hung */
314 dev_info(tx_ring
->dev
, "Detected Tx Unit Hang\n"
317 " next_to_use <%x>\n"
318 " next_to_clean <%x>\n",
320 tx_ring
->queue_index
,
321 tx_ring
->next_to_use
, i
);
322 dev_info(tx_ring
->dev
, "tx_bi[next_to_clean]\n"
323 " time_stamp <%lx>\n"
325 tx_ring
->tx_bi
[i
].time_stamp
, jiffies
);
327 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
329 dev_info(tx_ring
->dev
,
330 "tx hang detected on queue %d, resetting adapter\n",
331 tx_ring
->queue_index
);
333 tx_ring
->netdev
->netdev_ops
->ndo_tx_timeout(tx_ring
->netdev
);
335 /* the adapter is about to reset, no point in enabling stuff */
339 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring
->netdev
,
340 tx_ring
->queue_index
),
341 total_packets
, total_bytes
);
343 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
344 if (unlikely(total_packets
&& netif_carrier_ok(tx_ring
->netdev
) &&
345 (I40E_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
346 /* Make sure that anybody stopping the queue after this
347 * sees the new next_to_clean.
350 if (__netif_subqueue_stopped(tx_ring
->netdev
,
351 tx_ring
->queue_index
) &&
352 !test_bit(__I40E_DOWN
, &tx_ring
->vsi
->state
)) {
353 netif_wake_subqueue(tx_ring
->netdev
,
354 tx_ring
->queue_index
);
355 ++tx_ring
->tx_stats
.restart_queue
;
363 * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
364 * @vsi: the VSI we care about
365 * @q_vector: the vector on which to force writeback
368 static void i40e_force_wb(struct i40e_vsi
*vsi
, struct i40e_q_vector
*q_vector
)
370 u32 val
= I40E_VFINT_DYN_CTLN_INTENA_MASK
|
371 I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK
|
372 I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK
;
373 /* allow 00 to be written to the index */
376 I40E_VFINT_DYN_CTLN1(q_vector
->v_idx
+ vsi
->base_vector
- 1),
381 * i40e_set_new_dynamic_itr - Find new ITR level
382 * @rc: structure containing ring performance data
384 * Stores a new ITR value based on packets and byte counts during
385 * the last interrupt. The advantage of per interrupt computation
386 * is faster updates and more accurate ITR for the current traffic
387 * pattern. Constants in this function were computed based on
388 * theoretical maximum wire speed and thresholds were set based on
389 * testing data as well as attempting to minimize response time
390 * while increasing bulk throughput.
392 static void i40e_set_new_dynamic_itr(struct i40e_ring_container
*rc
)
394 enum i40e_latency_range new_latency_range
= rc
->latency_range
;
395 u32 new_itr
= rc
->itr
;
398 if (rc
->total_packets
== 0 || !rc
->itr
)
401 /* simple throttlerate management
402 * 0-10MB/s lowest (100000 ints/s)
403 * 10-20MB/s low (20000 ints/s)
404 * 20-1249MB/s bulk (8000 ints/s)
406 bytes_per_int
= rc
->total_bytes
/ rc
->itr
;
408 case I40E_LOWEST_LATENCY
:
409 if (bytes_per_int
> 10)
410 new_latency_range
= I40E_LOW_LATENCY
;
412 case I40E_LOW_LATENCY
:
413 if (bytes_per_int
> 20)
414 new_latency_range
= I40E_BULK_LATENCY
;
415 else if (bytes_per_int
<= 10)
416 new_latency_range
= I40E_LOWEST_LATENCY
;
418 case I40E_BULK_LATENCY
:
419 if (bytes_per_int
<= 20)
420 rc
->latency_range
= I40E_LOW_LATENCY
;
424 switch (new_latency_range
) {
425 case I40E_LOWEST_LATENCY
:
426 new_itr
= I40E_ITR_100K
;
428 case I40E_LOW_LATENCY
:
429 new_itr
= I40E_ITR_20K
;
431 case I40E_BULK_LATENCY
:
432 new_itr
= I40E_ITR_8K
;
438 if (new_itr
!= rc
->itr
) {
439 /* do an exponential smoothing */
440 new_itr
= (10 * new_itr
* rc
->itr
) /
441 ((9 * new_itr
) + rc
->itr
);
442 rc
->itr
= new_itr
& I40E_MAX_ITR
;
446 rc
->total_packets
= 0;
450 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
451 * @q_vector: the vector to adjust
453 static void i40e_update_dynamic_itr(struct i40e_q_vector
*q_vector
)
455 u16 vector
= q_vector
->vsi
->base_vector
+ q_vector
->v_idx
;
456 struct i40e_hw
*hw
= &q_vector
->vsi
->back
->hw
;
460 reg_addr
= I40E_VFINT_ITRN1(I40E_RX_ITR
, vector
- 1);
461 old_itr
= q_vector
->rx
.itr
;
462 i40e_set_new_dynamic_itr(&q_vector
->rx
);
463 if (old_itr
!= q_vector
->rx
.itr
)
464 wr32(hw
, reg_addr
, q_vector
->rx
.itr
);
466 reg_addr
= I40E_VFINT_ITRN1(I40E_TX_ITR
, vector
- 1);
467 old_itr
= q_vector
->tx
.itr
;
468 i40e_set_new_dynamic_itr(&q_vector
->tx
);
469 if (old_itr
!= q_vector
->tx
.itr
)
470 wr32(hw
, reg_addr
, q_vector
->tx
.itr
);
474 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
475 * @tx_ring: the tx ring to set up
477 * Return 0 on success, negative on error
479 int i40evf_setup_tx_descriptors(struct i40e_ring
*tx_ring
)
481 struct device
*dev
= tx_ring
->dev
;
487 bi_size
= sizeof(struct i40e_tx_buffer
) * tx_ring
->count
;
488 tx_ring
->tx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
492 /* round up to nearest 4K */
493 tx_ring
->size
= tx_ring
->count
* sizeof(struct i40e_tx_desc
);
494 /* add u32 for head writeback, align after this takes care of
495 * guaranteeing this is at least one cache line in size
497 tx_ring
->size
+= sizeof(u32
);
498 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
499 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
500 &tx_ring
->dma
, GFP_KERNEL
);
501 if (!tx_ring
->desc
) {
502 dev_info(dev
, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
507 tx_ring
->next_to_use
= 0;
508 tx_ring
->next_to_clean
= 0;
512 kfree(tx_ring
->tx_bi
);
513 tx_ring
->tx_bi
= NULL
;
518 * i40evf_clean_rx_ring - Free Rx buffers
519 * @rx_ring: ring to be cleaned
521 void i40evf_clean_rx_ring(struct i40e_ring
*rx_ring
)
523 struct device
*dev
= rx_ring
->dev
;
524 struct i40e_rx_buffer
*rx_bi
;
525 unsigned long bi_size
;
528 /* ring already cleared, nothing to do */
532 /* Free all the Rx ring sk_buffs */
533 for (i
= 0; i
< rx_ring
->count
; i
++) {
534 rx_bi
= &rx_ring
->rx_bi
[i
];
536 dma_unmap_single(dev
,
543 dev_kfree_skb(rx_bi
->skb
);
547 if (rx_bi
->page_dma
) {
554 __free_page(rx_bi
->page
);
556 rx_bi
->page_offset
= 0;
560 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
561 memset(rx_ring
->rx_bi
, 0, bi_size
);
563 /* Zero out the descriptor ring */
564 memset(rx_ring
->desc
, 0, rx_ring
->size
);
566 rx_ring
->next_to_clean
= 0;
567 rx_ring
->next_to_use
= 0;
571 * i40evf_free_rx_resources - Free Rx resources
572 * @rx_ring: ring to clean the resources from
574 * Free all receive software resources
576 void i40evf_free_rx_resources(struct i40e_ring
*rx_ring
)
578 i40evf_clean_rx_ring(rx_ring
);
579 kfree(rx_ring
->rx_bi
);
580 rx_ring
->rx_bi
= NULL
;
583 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
584 rx_ring
->desc
, rx_ring
->dma
);
585 rx_ring
->desc
= NULL
;
590 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
591 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
593 * Returns 0 on success, negative on failure
595 int i40evf_setup_rx_descriptors(struct i40e_ring
*rx_ring
)
597 struct device
*dev
= rx_ring
->dev
;
600 bi_size
= sizeof(struct i40e_rx_buffer
) * rx_ring
->count
;
601 rx_ring
->rx_bi
= kzalloc(bi_size
, GFP_KERNEL
);
605 u64_stats_init(&rx_ring
->syncp
);
607 /* Round up to nearest 4K */
608 rx_ring
->size
= ring_is_16byte_desc_enabled(rx_ring
)
609 ? rx_ring
->count
* sizeof(union i40e_16byte_rx_desc
)
610 : rx_ring
->count
* sizeof(union i40e_32byte_rx_desc
);
611 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
612 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
613 &rx_ring
->dma
, GFP_KERNEL
);
615 if (!rx_ring
->desc
) {
616 dev_info(dev
, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
621 rx_ring
->next_to_clean
= 0;
622 rx_ring
->next_to_use
= 0;
626 kfree(rx_ring
->rx_bi
);
627 rx_ring
->rx_bi
= NULL
;
632 * i40e_release_rx_desc - Store the new tail and head values
633 * @rx_ring: ring to bump
634 * @val: new head index
636 static inline void i40e_release_rx_desc(struct i40e_ring
*rx_ring
, u32 val
)
638 rx_ring
->next_to_use
= val
;
639 /* Force memory writes to complete before letting h/w
640 * know there are new descriptors to fetch. (Only
641 * applicable for weak-ordered memory model archs,
645 writel(val
, rx_ring
->tail
);
649 * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
650 * @rx_ring: ring to place buffers on
651 * @cleaned_count: number of buffers to replace
653 void i40evf_alloc_rx_buffers(struct i40e_ring
*rx_ring
, u16 cleaned_count
)
655 u16 i
= rx_ring
->next_to_use
;
656 union i40e_rx_desc
*rx_desc
;
657 struct i40e_rx_buffer
*bi
;
660 /* do nothing if no valid netdev defined */
661 if (!rx_ring
->netdev
|| !cleaned_count
)
664 while (cleaned_count
--) {
665 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
666 bi
= &rx_ring
->rx_bi
[i
];
670 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
671 rx_ring
->rx_buf_len
);
673 rx_ring
->rx_stats
.alloc_buff_failed
++;
676 /* initialize queue mapping */
677 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
682 bi
->dma
= dma_map_single(rx_ring
->dev
,
686 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
687 rx_ring
->rx_stats
.alloc_buff_failed
++;
693 if (ring_is_ps_enabled(rx_ring
)) {
695 bi
->page
= alloc_page(GFP_ATOMIC
);
697 rx_ring
->rx_stats
.alloc_page_failed
++;
703 /* use a half page if we're re-using */
704 bi
->page_offset
^= PAGE_SIZE
/ 2;
705 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
710 if (dma_mapping_error(rx_ring
->dev
,
712 rx_ring
->rx_stats
.alloc_page_failed
++;
718 /* Refresh the desc even if buffer_addrs didn't change
719 * because each write-back erases this info.
721 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
722 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
724 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
725 rx_desc
->read
.hdr_addr
= 0;
728 if (i
== rx_ring
->count
)
733 if (rx_ring
->next_to_use
!= i
)
734 i40e_release_rx_desc(rx_ring
, i
);
738 * i40e_receive_skb - Send a completed packet up the stack
739 * @rx_ring: rx ring in play
740 * @skb: packet to send up
741 * @vlan_tag: vlan tag for packet
743 static void i40e_receive_skb(struct i40e_ring
*rx_ring
,
744 struct sk_buff
*skb
, u16 vlan_tag
)
746 struct i40e_q_vector
*q_vector
= rx_ring
->q_vector
;
747 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
748 u64 flags
= vsi
->back
->flags
;
750 if (vlan_tag
& VLAN_VID_MASK
)
751 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlan_tag
);
753 if (flags
& I40E_FLAG_IN_NETPOLL
)
756 napi_gro_receive(&q_vector
->napi
, skb
);
760 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
761 * @vsi: the VSI we care about
762 * @skb: skb currently being received and modified
763 * @rx_status: status value of last descriptor in packet
764 * @rx_error: error value of last descriptor in packet
765 * @rx_ptype: ptype value of last descriptor in packet
767 static inline void i40e_rx_checksum(struct i40e_vsi
*vsi
,
773 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(rx_ptype
);
774 bool ipv4
= false, ipv6
= false;
775 bool ipv4_tunnel
, ipv6_tunnel
;
780 ipv4_tunnel
= (rx_ptype
> I40E_RX_PTYPE_GRENAT4_MAC_PAY3
) &&
781 (rx_ptype
< I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4
);
782 ipv6_tunnel
= (rx_ptype
> I40E_RX_PTYPE_GRENAT6_MAC_PAY3
) &&
783 (rx_ptype
< I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4
);
785 skb
->ip_summed
= CHECKSUM_NONE
;
787 /* Rx csum enabled and ip headers found? */
788 if (!(vsi
->netdev
->features
& NETIF_F_RXCSUM
))
791 /* did the hardware decode the packet and checksum? */
792 if (!(rx_status
& (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT
)))
795 /* both known and outer_ip must be set for the below code to work */
796 if (!(decoded
.known
&& decoded
.outer_ip
))
799 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
800 decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV4
)
802 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
803 decoded
.outer_ip_ver
== I40E_RX_PTYPE_OUTER_IPV6
)
807 (rx_error
& ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT
) |
808 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT
))))
811 /* likely incorrect csum if alternate IP extension headers found */
813 rx_status
& (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT
))
814 /* don't increment checksum err here, non-fatal err */
817 /* there was some L4 error, count error and punt packet to the stack */
818 if (rx_error
& (1 << I40E_RX_DESC_ERROR_L4E_SHIFT
))
821 /* handle packets that were not able to be checksummed due
822 * to arrival speed, in this case the stack can compute
825 if (rx_error
& (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT
))
828 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
829 * it in the driver, hardware does not do it for us.
830 * Since L3L4P bit was set we assume a valid IHL value (>=5)
831 * so the total length of IPv4 header is IHL*4 bytes
832 * The UDP_0 bit *may* bet set if the *inner* header is UDP
835 (decoded
.inner_prot
!= I40E_RX_PTYPE_INNER_PROT_UDP
) &&
836 !(rx_status
& (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT
))) {
837 skb
->transport_header
= skb
->mac_header
+
838 sizeof(struct ethhdr
) +
839 (ip_hdr(skb
)->ihl
* 4);
841 /* Add 4 bytes for VLAN tagged packets */
842 skb
->transport_header
+= (skb
->protocol
== htons(ETH_P_8021Q
) ||
843 skb
->protocol
== htons(ETH_P_8021AD
))
846 rx_udp_csum
= udp_csum(skb
);
848 csum
= csum_tcpudp_magic(
849 iph
->saddr
, iph
->daddr
,
850 (skb
->len
- skb_transport_offset(skb
)),
851 IPPROTO_UDP
, rx_udp_csum
);
853 if (udp_hdr(skb
)->check
!= csum
)
857 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
858 skb
->csum_level
= ipv4_tunnel
|| ipv6_tunnel
;
863 vsi
->back
->hw_csum_rx_error
++;
867 * i40e_rx_hash - returns the hash value from the Rx descriptor
868 * @ring: descriptor ring
869 * @rx_desc: specific descriptor
871 static inline u32
i40e_rx_hash(struct i40e_ring
*ring
,
872 union i40e_rx_desc
*rx_desc
)
874 const __le64 rss_mask
=
875 cpu_to_le64((u64
)I40E_RX_DESC_FLTSTAT_RSS_HASH
<<
876 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT
);
878 if ((ring
->netdev
->features
& NETIF_F_RXHASH
) &&
879 (rx_desc
->wb
.qword1
.status_error_len
& rss_mask
) == rss_mask
)
880 return le32_to_cpu(rx_desc
->wb
.qword0
.hi_dword
.rss
);
886 * i40e_ptype_to_hash - get a hash type
887 * @ptype: the ptype value from the descriptor
889 * Returns a hash type to be used by skb_set_hash
891 static inline enum pkt_hash_types
i40e_ptype_to_hash(u8 ptype
)
893 struct i40e_rx_ptype_decoded decoded
= decode_rx_desc_ptype(ptype
);
896 return PKT_HASH_TYPE_NONE
;
898 if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
899 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4
)
900 return PKT_HASH_TYPE_L4
;
901 else if (decoded
.outer_ip
== I40E_RX_PTYPE_OUTER_IP
&&
902 decoded
.payload_layer
== I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3
)
903 return PKT_HASH_TYPE_L3
;
905 return PKT_HASH_TYPE_L2
;
909 * i40e_clean_rx_irq - Reclaim resources after receive completes
910 * @rx_ring: rx ring to clean
911 * @budget: how many cleans we're allowed
913 * Returns true if there's any budget left (e.g. the clean is finished)
915 static int i40e_clean_rx_irq(struct i40e_ring
*rx_ring
, int budget
)
917 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
918 u16 rx_packet_len
, rx_header_len
, rx_sph
, rx_hbo
;
919 u16 cleaned_count
= I40E_DESC_UNUSED(rx_ring
);
920 const int current_node
= numa_node_id();
921 struct i40e_vsi
*vsi
= rx_ring
->vsi
;
922 u16 i
= rx_ring
->next_to_clean
;
923 union i40e_rx_desc
*rx_desc
;
924 u32 rx_error
, rx_status
;
928 rx_desc
= I40E_RX_DESC(rx_ring
, i
);
929 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
930 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
931 I40E_RXD_QW1_STATUS_SHIFT
;
933 while (rx_status
& (1 << I40E_RX_DESC_STATUS_DD_SHIFT
)) {
934 union i40e_rx_desc
*next_rxd
;
935 struct i40e_rx_buffer
*rx_bi
;
938 rx_bi
= &rx_ring
->rx_bi
[i
];
942 rx_packet_len
= (qword
& I40E_RXD_QW1_LENGTH_PBUF_MASK
) >>
943 I40E_RXD_QW1_LENGTH_PBUF_SHIFT
;
944 rx_header_len
= (qword
& I40E_RXD_QW1_LENGTH_HBUF_MASK
) >>
945 I40E_RXD_QW1_LENGTH_HBUF_SHIFT
;
946 rx_sph
= (qword
& I40E_RXD_QW1_LENGTH_SPH_MASK
) >>
947 I40E_RXD_QW1_LENGTH_SPH_SHIFT
;
949 rx_error
= (qword
& I40E_RXD_QW1_ERROR_MASK
) >>
950 I40E_RXD_QW1_ERROR_SHIFT
;
951 rx_hbo
= rx_error
& (1 << I40E_RX_DESC_ERROR_HBO_SHIFT
);
952 rx_error
&= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT
);
954 rx_ptype
= (qword
& I40E_RXD_QW1_PTYPE_MASK
) >>
955 I40E_RXD_QW1_PTYPE_SHIFT
;
958 /* This memory barrier is needed to keep us from reading
959 * any other fields out of the rx_desc until we know the
960 * STATUS_DD bit is set
964 /* Get the header and possibly the whole packet
965 * If this is an skb from previous receive dma will be 0
971 len
= I40E_RX_HDR_SIZE
;
974 else if (rx_packet_len
)
975 len
= rx_packet_len
; /* 1buf/no split found */
977 len
= rx_header_len
; /* split always mode */
980 dma_unmap_single(rx_ring
->dev
,
987 /* Get the rest of the data if this was a header split */
988 if (ring_is_ps_enabled(rx_ring
) && rx_packet_len
) {
990 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
995 skb
->len
+= rx_packet_len
;
996 skb
->data_len
+= rx_packet_len
;
997 skb
->truesize
+= rx_packet_len
;
999 if ((page_count(rx_bi
->page
) == 1) &&
1000 (page_to_nid(rx_bi
->page
) == current_node
))
1001 get_page(rx_bi
->page
);
1005 dma_unmap_page(rx_ring
->dev
,
1009 rx_bi
->page_dma
= 0;
1011 I40E_RX_NEXT_DESC_PREFETCH(rx_ring
, i
, next_rxd
);
1014 !(rx_status
& (1 << I40E_RX_DESC_STATUS_EOF_SHIFT
)))) {
1015 struct i40e_rx_buffer
*next_buffer
;
1017 next_buffer
= &rx_ring
->rx_bi
[i
];
1019 if (ring_is_ps_enabled(rx_ring
)) {
1020 rx_bi
->skb
= next_buffer
->skb
;
1021 rx_bi
->dma
= next_buffer
->dma
;
1022 next_buffer
->skb
= skb
;
1023 next_buffer
->dma
= 0;
1025 rx_ring
->rx_stats
.non_eop_descs
++;
1029 /* ERR_MASK will only have valid bits if EOP set */
1030 if (unlikely(rx_error
& (1 << I40E_RX_DESC_ERROR_RXE_SHIFT
))) {
1031 dev_kfree_skb_any(skb
);
1032 /* TODO: shouldn't we increment a counter indicating the
1038 skb_set_hash(skb
, i40e_rx_hash(rx_ring
, rx_desc
),
1039 i40e_ptype_to_hash(rx_ptype
));
1040 /* probably a little skewed due to removing CRC */
1041 total_rx_bytes
+= skb
->len
;
1044 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1046 i40e_rx_checksum(vsi
, skb
, rx_status
, rx_error
, rx_ptype
);
1048 vlan_tag
= rx_status
& (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
)
1049 ? le16_to_cpu(rx_desc
->wb
.qword0
.lo_dword
.l2tag1
)
1051 i40e_receive_skb(rx_ring
, skb
, vlan_tag
);
1053 rx_ring
->netdev
->last_rx
= jiffies
;
1056 rx_desc
->wb
.qword1
.status_error_len
= 0;
1061 /* return some buffers to hardware, one at a time is too slow */
1062 if (cleaned_count
>= I40E_RX_BUFFER_WRITE
) {
1063 i40evf_alloc_rx_buffers(rx_ring
, cleaned_count
);
1067 /* use prefetched values */
1069 qword
= le64_to_cpu(rx_desc
->wb
.qword1
.status_error_len
);
1070 rx_status
= (qword
& I40E_RXD_QW1_STATUS_MASK
) >>
1071 I40E_RXD_QW1_STATUS_SHIFT
;
1074 rx_ring
->next_to_clean
= i
;
1075 u64_stats_update_begin(&rx_ring
->syncp
);
1076 rx_ring
->stats
.packets
+= total_rx_packets
;
1077 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1078 u64_stats_update_end(&rx_ring
->syncp
);
1079 rx_ring
->q_vector
->rx
.total_packets
+= total_rx_packets
;
1080 rx_ring
->q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1083 i40evf_alloc_rx_buffers(rx_ring
, cleaned_count
);
1089 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1090 * @napi: napi struct with our devices info in it
1091 * @budget: amount of work driver is allowed to do this pass, in packets
1093 * This function will clean all queues associated with a q_vector.
1095 * Returns the amount of work done
1097 int i40evf_napi_poll(struct napi_struct
*napi
, int budget
)
1099 struct i40e_q_vector
*q_vector
=
1100 container_of(napi
, struct i40e_q_vector
, napi
);
1101 struct i40e_vsi
*vsi
= q_vector
->vsi
;
1102 struct i40e_ring
*ring
;
1103 bool clean_complete
= true;
1104 bool arm_wb
= false;
1105 int budget_per_ring
;
1107 if (test_bit(__I40E_DOWN
, &vsi
->state
)) {
1108 napi_complete(napi
);
1112 /* Since the actual Tx work is minimal, we can give the Tx a larger
1113 * budget and be more aggressive about cleaning up the Tx descriptors.
1115 i40e_for_each_ring(ring
, q_vector
->tx
) {
1116 clean_complete
&= i40e_clean_tx_irq(ring
, vsi
->work_limit
);
1117 arm_wb
|= ring
->arm_wb
;
1120 /* We attempt to distribute budget to each Rx queue fairly, but don't
1121 * allow the budget to go below 1 because that would exit polling early.
1123 budget_per_ring
= max(budget
/q_vector
->num_ringpairs
, 1);
1125 i40e_for_each_ring(ring
, q_vector
->rx
)
1126 clean_complete
&= i40e_clean_rx_irq(ring
, budget_per_ring
);
1128 /* If work not completed, return budget and polling will return */
1129 if (!clean_complete
) {
1131 i40e_force_wb(vsi
, q_vector
);
1135 /* Work is done so exit the polling mode and re-enable the interrupt */
1136 napi_complete(napi
);
1137 if (ITR_IS_DYNAMIC(vsi
->rx_itr_setting
) ||
1138 ITR_IS_DYNAMIC(vsi
->tx_itr_setting
))
1139 i40e_update_dynamic_itr(q_vector
);
1141 if (!test_bit(__I40E_DOWN
, &vsi
->state
))
1142 i40evf_irq_enable_queues(vsi
->back
, 1 << q_vector
->v_idx
);
1148 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1150 * @tx_ring: ring to send buffer on
1151 * @flags: the tx flags to be set
1153 * Checks the skb and set up correspondingly several generic transmit flags
1154 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1156 * Returns error code indicate the frame should be dropped upon error and the
1157 * otherwise returns 0 to indicate the flags has been set properly.
1159 static int i40e_tx_prepare_vlan_flags(struct sk_buff
*skb
,
1160 struct i40e_ring
*tx_ring
,
1163 __be16 protocol
= skb
->protocol
;
1166 /* if we have a HW VLAN tag being added, default to the HW one */
1167 if (skb_vlan_tag_present(skb
)) {
1168 tx_flags
|= skb_vlan_tag_get(skb
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1169 tx_flags
|= I40E_TX_FLAGS_HW_VLAN
;
1170 /* else if it is a SW VLAN, check the next protocol and store the tag */
1171 } else if (protocol
== htons(ETH_P_8021Q
)) {
1172 struct vlan_hdr
*vhdr
, _vhdr
;
1173 vhdr
= skb_header_pointer(skb
, ETH_HLEN
, sizeof(_vhdr
), &_vhdr
);
1177 protocol
= vhdr
->h_vlan_encapsulated_proto
;
1178 tx_flags
|= ntohs(vhdr
->h_vlan_TCI
) << I40E_TX_FLAGS_VLAN_SHIFT
;
1179 tx_flags
|= I40E_TX_FLAGS_SW_VLAN
;
1187 * i40e_tso - set up the tso context descriptor
1188 * @tx_ring: ptr to the ring to send
1189 * @skb: ptr to the skb we're sending
1190 * @tx_flags: the collected send information
1191 * @protocol: the send protocol
1192 * @hdr_len: ptr to the size of the packet header
1193 * @cd_tunneling: ptr to context descriptor bits
1195 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1197 static int i40e_tso(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1198 u32 tx_flags
, __be16 protocol
, u8
*hdr_len
,
1199 u64
*cd_type_cmd_tso_mss
, u32
*cd_tunneling
)
1201 u32 cd_cmd
, cd_tso_len
, cd_mss
;
1202 struct ipv6hdr
*ipv6h
;
1203 struct tcphdr
*tcph
;
1208 if (!skb_is_gso(skb
))
1211 err
= skb_cow_head(skb
, 0);
1215 iph
= skb
->encapsulation
? inner_ip_hdr(skb
) : ip_hdr(skb
);
1216 ipv6h
= skb
->encapsulation
? inner_ipv6_hdr(skb
) : ipv6_hdr(skb
);
1218 if (iph
->version
== 4) {
1219 tcph
= skb
->encapsulation
? inner_tcp_hdr(skb
) : tcp_hdr(skb
);
1222 tcph
->check
= ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
,
1224 } else if (ipv6h
->version
== 6) {
1225 tcph
= skb
->encapsulation
? inner_tcp_hdr(skb
) : tcp_hdr(skb
);
1226 ipv6h
->payload_len
= 0;
1227 tcph
->check
= ~csum_ipv6_magic(&ipv6h
->saddr
, &ipv6h
->daddr
,
1231 l4len
= skb
->encapsulation
? inner_tcp_hdrlen(skb
) : tcp_hdrlen(skb
);
1232 *hdr_len
= (skb
->encapsulation
1233 ? (skb_inner_transport_header(skb
) - skb
->data
)
1234 : skb_transport_offset(skb
)) + l4len
;
1236 /* find the field values */
1237 cd_cmd
= I40E_TX_CTX_DESC_TSO
;
1238 cd_tso_len
= skb
->len
- *hdr_len
;
1239 cd_mss
= skb_shinfo(skb
)->gso_size
;
1240 *cd_type_cmd_tso_mss
|= ((u64
)cd_cmd
<< I40E_TXD_CTX_QW1_CMD_SHIFT
) |
1242 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT
) |
1243 ((u64
)cd_mss
<< I40E_TXD_CTX_QW1_MSS_SHIFT
);
1248 * i40e_tx_enable_csum - Enable Tx checksum offloads
1250 * @tx_flags: Tx flags currently set
1251 * @td_cmd: Tx descriptor command bits to set
1252 * @td_offset: Tx descriptor header offsets to set
1253 * @cd_tunneling: ptr to context desc bits
1255 static void i40e_tx_enable_csum(struct sk_buff
*skb
, u32 tx_flags
,
1256 u32
*td_cmd
, u32
*td_offset
,
1257 struct i40e_ring
*tx_ring
,
1260 struct ipv6hdr
*this_ipv6_hdr
;
1261 unsigned int this_tcp_hdrlen
;
1262 struct iphdr
*this_ip_hdr
;
1263 u32 network_hdr_len
;
1266 if (skb
->encapsulation
) {
1267 network_hdr_len
= skb_inner_network_header_len(skb
);
1268 this_ip_hdr
= inner_ip_hdr(skb
);
1269 this_ipv6_hdr
= inner_ipv6_hdr(skb
);
1270 this_tcp_hdrlen
= inner_tcp_hdrlen(skb
);
1272 if (tx_flags
& I40E_TX_FLAGS_IPV4
) {
1274 if (tx_flags
& I40E_TX_FLAGS_TSO
) {
1275 *cd_tunneling
|= I40E_TX_CTX_EXT_IP_IPV4
;
1276 ip_hdr(skb
)->check
= 0;
1279 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
;
1281 } else if (tx_flags
& I40E_TX_FLAGS_IPV6
) {
1282 *cd_tunneling
|= I40E_TX_CTX_EXT_IP_IPV6
;
1283 if (tx_flags
& I40E_TX_FLAGS_TSO
)
1284 ip_hdr(skb
)->check
= 0;
1287 /* Now set the ctx descriptor fields */
1288 *cd_tunneling
|= (skb_network_header_len(skb
) >> 2) <<
1289 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT
|
1290 I40E_TXD_CTX_UDP_TUNNELING
|
1291 ((skb_inner_network_offset(skb
) -
1292 skb_transport_offset(skb
)) >> 1) <<
1293 I40E_TXD_CTX_QW0_NATLEN_SHIFT
;
1294 if (this_ip_hdr
->version
== 6) {
1295 tx_flags
&= ~I40E_TX_FLAGS_IPV4
;
1296 tx_flags
|= I40E_TX_FLAGS_IPV6
;
1301 network_hdr_len
= skb_network_header_len(skb
);
1302 this_ip_hdr
= ip_hdr(skb
);
1303 this_ipv6_hdr
= ipv6_hdr(skb
);
1304 this_tcp_hdrlen
= tcp_hdrlen(skb
);
1307 /* Enable IP checksum offloads */
1308 if (tx_flags
& I40E_TX_FLAGS_IPV4
) {
1309 l4_hdr
= this_ip_hdr
->protocol
;
1310 /* the stack computes the IP header already, the only time we
1311 * need the hardware to recompute it is in the case of TSO.
1313 if (tx_flags
& I40E_TX_FLAGS_TSO
) {
1314 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM
;
1315 this_ip_hdr
->check
= 0;
1317 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV4
;
1319 /* Now set the td_offset for IP header length */
1320 *td_offset
= (network_hdr_len
>> 2) <<
1321 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1322 } else if (tx_flags
& I40E_TX_FLAGS_IPV6
) {
1323 l4_hdr
= this_ipv6_hdr
->nexthdr
;
1324 *td_cmd
|= I40E_TX_DESC_CMD_IIPT_IPV6
;
1325 /* Now set the td_offset for IP header length */
1326 *td_offset
= (network_hdr_len
>> 2) <<
1327 I40E_TX_DESC_LENGTH_IPLEN_SHIFT
;
1329 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1330 *td_offset
|= (skb_network_offset(skb
) >> 1) <<
1331 I40E_TX_DESC_LENGTH_MACLEN_SHIFT
;
1333 /* Enable L4 checksum offloads */
1336 /* enable checksum offloads */
1337 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_TCP
;
1338 *td_offset
|= (this_tcp_hdrlen
>> 2) <<
1339 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1342 /* enable SCTP checksum offload */
1343 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_SCTP
;
1344 *td_offset
|= (sizeof(struct sctphdr
) >> 2) <<
1345 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1348 /* enable UDP checksum offload */
1349 *td_cmd
|= I40E_TX_DESC_CMD_L4T_EOFT_UDP
;
1350 *td_offset
|= (sizeof(struct udphdr
) >> 2) <<
1351 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
;
1359 * i40e_create_tx_ctx Build the Tx context descriptor
1360 * @tx_ring: ring to create the descriptor on
1361 * @cd_type_cmd_tso_mss: Quad Word 1
1362 * @cd_tunneling: Quad Word 0 - bits 0-31
1363 * @cd_l2tag2: Quad Word 0 - bits 32-63
1365 static void i40e_create_tx_ctx(struct i40e_ring
*tx_ring
,
1366 const u64 cd_type_cmd_tso_mss
,
1367 const u32 cd_tunneling
, const u32 cd_l2tag2
)
1369 struct i40e_tx_context_desc
*context_desc
;
1370 int i
= tx_ring
->next_to_use
;
1372 if ((cd_type_cmd_tso_mss
== I40E_TX_DESC_DTYPE_CONTEXT
) &&
1373 !cd_tunneling
&& !cd_l2tag2
)
1376 /* grab the next descriptor */
1377 context_desc
= I40E_TX_CTXTDESC(tx_ring
, i
);
1380 tx_ring
->next_to_use
= (i
< tx_ring
->count
) ? i
: 0;
1382 /* cpu_to_le32 and assign to struct fields */
1383 context_desc
->tunneling_params
= cpu_to_le32(cd_tunneling
);
1384 context_desc
->l2tag2
= cpu_to_le16(cd_l2tag2
);
1385 context_desc
->rsvd
= cpu_to_le16(0);
1386 context_desc
->type_cmd_tso_mss
= cpu_to_le64(cd_type_cmd_tso_mss
);
1390 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1392 * @tx_flags: collected send information
1393 * @hdr_len: size of the packet header
1395 * Note: Our HW can't scatter-gather more than 8 fragments to build
1396 * a packet on the wire and so we need to figure out the cases where we
1397 * need to linearize the skb.
1399 static bool i40e_chk_linearize(struct sk_buff
*skb
, u32 tx_flags
,
1402 struct skb_frag_struct
*frag
;
1403 bool linearize
= false;
1404 unsigned int size
= 0;
1408 num_frags
= skb_shinfo(skb
)->nr_frags
;
1409 gso_segs
= skb_shinfo(skb
)->gso_segs
;
1411 if (tx_flags
& (I40E_TX_FLAGS_TSO
| I40E_TX_FLAGS_FSO
)) {
1414 if (num_frags
< (I40E_MAX_BUFFER_TXD
))
1415 goto linearize_chk_done
;
1416 /* try the simple math, if we have too many frags per segment */
1417 if (DIV_ROUND_UP((num_frags
+ gso_segs
), gso_segs
) >
1418 I40E_MAX_BUFFER_TXD
) {
1420 goto linearize_chk_done
;
1422 frag
= &skb_shinfo(skb
)->frags
[0];
1424 /* we might still have more fragments per segment */
1426 size
+= skb_frag_size(frag
);
1428 if (j
== I40E_MAX_BUFFER_TXD
) {
1429 if (size
< skb_shinfo(skb
)->gso_size
) {
1434 size
-= skb_shinfo(skb
)->gso_size
;
1440 } while (num_frags
);
1442 if (num_frags
>= I40E_MAX_BUFFER_TXD
)
1451 * i40e_tx_map - Build the Tx descriptor
1452 * @tx_ring: ring to send buffer on
1454 * @first: first buffer info buffer to use
1455 * @tx_flags: collected send information
1456 * @hdr_len: size of the packet header
1457 * @td_cmd: the command field in the descriptor
1458 * @td_offset: offset for checksum or crc
1460 static void i40e_tx_map(struct i40e_ring
*tx_ring
, struct sk_buff
*skb
,
1461 struct i40e_tx_buffer
*first
, u32 tx_flags
,
1462 const u8 hdr_len
, u32 td_cmd
, u32 td_offset
)
1464 unsigned int data_len
= skb
->data_len
;
1465 unsigned int size
= skb_headlen(skb
);
1466 struct skb_frag_struct
*frag
;
1467 struct i40e_tx_buffer
*tx_bi
;
1468 struct i40e_tx_desc
*tx_desc
;
1469 u16 i
= tx_ring
->next_to_use
;
1474 if (tx_flags
& I40E_TX_FLAGS_HW_VLAN
) {
1475 td_cmd
|= I40E_TX_DESC_CMD_IL2TAG1
;
1476 td_tag
= (tx_flags
& I40E_TX_FLAGS_VLAN_MASK
) >>
1477 I40E_TX_FLAGS_VLAN_SHIFT
;
1480 if (tx_flags
& (I40E_TX_FLAGS_TSO
| I40E_TX_FLAGS_FSO
))
1481 gso_segs
= skb_shinfo(skb
)->gso_segs
;
1485 /* multiply data chunks by size of headers */
1486 first
->bytecount
= skb
->len
- hdr_len
+ (gso_segs
* hdr_len
);
1487 first
->gso_segs
= gso_segs
;
1489 first
->tx_flags
= tx_flags
;
1491 dma
= dma_map_single(tx_ring
->dev
, skb
->data
, size
, DMA_TO_DEVICE
);
1493 tx_desc
= I40E_TX_DESC(tx_ring
, i
);
1496 for (frag
= &skb_shinfo(skb
)->frags
[0];; frag
++) {
1497 if (dma_mapping_error(tx_ring
->dev
, dma
))
1500 /* record length, and DMA address */
1501 dma_unmap_len_set(tx_bi
, len
, size
);
1502 dma_unmap_addr_set(tx_bi
, dma
, dma
);
1504 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1506 while (unlikely(size
> I40E_MAX_DATA_PER_TXD
)) {
1507 tx_desc
->cmd_type_offset_bsz
=
1508 build_ctob(td_cmd
, td_offset
,
1509 I40E_MAX_DATA_PER_TXD
, td_tag
);
1513 if (i
== tx_ring
->count
) {
1514 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1518 dma
+= I40E_MAX_DATA_PER_TXD
;
1519 size
-= I40E_MAX_DATA_PER_TXD
;
1521 tx_desc
->buffer_addr
= cpu_to_le64(dma
);
1524 if (likely(!data_len
))
1527 tx_desc
->cmd_type_offset_bsz
= build_ctob(td_cmd
, td_offset
,
1532 if (i
== tx_ring
->count
) {
1533 tx_desc
= I40E_TX_DESC(tx_ring
, 0);
1537 size
= skb_frag_size(frag
);
1540 dma
= skb_frag_dma_map(tx_ring
->dev
, frag
, 0, size
,
1543 tx_bi
= &tx_ring
->tx_bi
[i
];
1546 /* Place RS bit on last descriptor of any packet that spans across the
1547 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1549 #define WB_STRIDE 0x3
1550 if (((i
& WB_STRIDE
) != WB_STRIDE
) &&
1551 (first
<= &tx_ring
->tx_bi
[i
]) &&
1552 (first
>= &tx_ring
->tx_bi
[i
& ~WB_STRIDE
])) {
1553 tx_desc
->cmd_type_offset_bsz
=
1554 build_ctob(td_cmd
, td_offset
, size
, td_tag
) |
1555 cpu_to_le64((u64
)I40E_TX_DESC_CMD_EOP
<<
1556 I40E_TXD_QW1_CMD_SHIFT
);
1558 tx_desc
->cmd_type_offset_bsz
=
1559 build_ctob(td_cmd
, td_offset
, size
, td_tag
) |
1560 cpu_to_le64((u64
)I40E_TXD_CMD
<<
1561 I40E_TXD_QW1_CMD_SHIFT
);
1564 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring
->netdev
,
1565 tx_ring
->queue_index
),
1568 /* set the timestamp */
1569 first
->time_stamp
= jiffies
;
1571 /* Force memory writes to complete before letting h/w
1572 * know there are new descriptors to fetch. (Only
1573 * applicable for weak-ordered memory model archs,
1578 /* set next_to_watch value indicating a packet is present */
1579 first
->next_to_watch
= tx_desc
;
1582 if (i
== tx_ring
->count
)
1585 tx_ring
->next_to_use
= i
;
1587 /* notify HW of packet */
1588 writel(i
, tx_ring
->tail
);
1593 dev_info(tx_ring
->dev
, "TX DMA map failed\n");
1595 /* clear dma mappings for failed tx_bi map */
1597 tx_bi
= &tx_ring
->tx_bi
[i
];
1598 i40e_unmap_and_free_tx_resource(tx_ring
, tx_bi
);
1606 tx_ring
->next_to_use
= i
;
1610 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1611 * @tx_ring: the ring to be checked
1612 * @size: the size buffer we want to assure is available
1614 * Returns -EBUSY if a stop is needed, else 0
1616 static inline int __i40e_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1618 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1619 /* Memory barrier before checking head and tail */
1622 /* Check again in a case another CPU has just made room available. */
1623 if (likely(I40E_DESC_UNUSED(tx_ring
) < size
))
1626 /* A reprieve! - use start_queue because it doesn't call schedule */
1627 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
1628 ++tx_ring
->tx_stats
.restart_queue
;
1633 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1634 * @tx_ring: the ring to be checked
1635 * @size: the size buffer we want to assure is available
1637 * Returns 0 if stop is not needed
1639 static int i40e_maybe_stop_tx(struct i40e_ring
*tx_ring
, int size
)
1641 if (likely(I40E_DESC_UNUSED(tx_ring
) >= size
))
1643 return __i40e_maybe_stop_tx(tx_ring
, size
);
1647 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1649 * @tx_ring: ring to send buffer on
1651 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1652 * there is not enough descriptors available in this ring since we need at least
1655 static int i40e_xmit_descriptor_count(struct sk_buff
*skb
,
1656 struct i40e_ring
*tx_ring
)
1661 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1662 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1663 * + 4 desc gap to avoid the cache line where head is,
1664 * + 1 desc for context descriptor,
1665 * otherwise try next time
1667 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
1668 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
1670 count
+= TXD_USE_COUNT(skb_headlen(skb
));
1671 if (i40e_maybe_stop_tx(tx_ring
, count
+ 4 + 1)) {
1672 tx_ring
->tx_stats
.tx_busy
++;
1679 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1681 * @tx_ring: ring to send buffer on
1683 * Returns NETDEV_TX_OK if sent, else an error code
1685 static netdev_tx_t
i40e_xmit_frame_ring(struct sk_buff
*skb
,
1686 struct i40e_ring
*tx_ring
)
1688 u64 cd_type_cmd_tso_mss
= I40E_TX_DESC_DTYPE_CONTEXT
;
1689 u32 cd_tunneling
= 0, cd_l2tag2
= 0;
1690 struct i40e_tx_buffer
*first
;
1697 if (0 == i40e_xmit_descriptor_count(skb
, tx_ring
))
1698 return NETDEV_TX_BUSY
;
1700 /* prepare the xmit flags */
1701 if (i40e_tx_prepare_vlan_flags(skb
, tx_ring
, &tx_flags
))
1704 /* obtain protocol of skb */
1705 protocol
= vlan_get_protocol(skb
);
1707 /* record the location of the first descriptor for this packet */
1708 first
= &tx_ring
->tx_bi
[tx_ring
->next_to_use
];
1710 /* setup IPv4/IPv6 offloads */
1711 if (protocol
== htons(ETH_P_IP
))
1712 tx_flags
|= I40E_TX_FLAGS_IPV4
;
1713 else if (protocol
== htons(ETH_P_IPV6
))
1714 tx_flags
|= I40E_TX_FLAGS_IPV6
;
1716 tso
= i40e_tso(tx_ring
, skb
, tx_flags
, protocol
, &hdr_len
,
1717 &cd_type_cmd_tso_mss
, &cd_tunneling
);
1722 tx_flags
|= I40E_TX_FLAGS_TSO
;
1724 if (i40e_chk_linearize(skb
, tx_flags
, hdr_len
))
1725 if (skb_linearize(skb
))
1728 skb_tx_timestamp(skb
);
1730 /* always enable CRC insertion offload */
1731 td_cmd
|= I40E_TX_DESC_CMD_ICRC
;
1733 /* Always offload the checksum, since it's in the data descriptor */
1734 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1735 tx_flags
|= I40E_TX_FLAGS_CSUM
;
1737 i40e_tx_enable_csum(skb
, tx_flags
, &td_cmd
, &td_offset
,
1738 tx_ring
, &cd_tunneling
);
1741 i40e_create_tx_ctx(tx_ring
, cd_type_cmd_tso_mss
,
1742 cd_tunneling
, cd_l2tag2
);
1744 i40e_tx_map(tx_ring
, skb
, first
, tx_flags
, hdr_len
,
1747 i40e_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
1749 return NETDEV_TX_OK
;
1752 dev_kfree_skb_any(skb
);
1753 return NETDEV_TX_OK
;
1757 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1759 * @netdev: network interface device structure
1761 * Returns NETDEV_TX_OK if sent, else an error code
1763 netdev_tx_t
i40evf_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
1765 struct i40evf_adapter
*adapter
= netdev_priv(netdev
);
1766 struct i40e_ring
*tx_ring
= adapter
->tx_rings
[skb
->queue_mapping
];
1768 /* hardware can't handle really short frames, hardware padding works
1771 if (unlikely(skb
->len
< I40E_MIN_TX_LEN
)) {
1772 if (skb_pad(skb
, I40E_MIN_TX_LEN
- skb
->len
))
1773 return NETDEV_TX_OK
;
1774 skb
->len
= I40E_MIN_TX_LEN
;
1775 skb_set_tail_pointer(skb
, I40E_MIN_TX_LEN
);
1778 return i40e_xmit_frame_ring(skb
, tx_ring
);