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i40e/i40evf: Add missing packet types for VXLAN encapsulated packet types
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
29
30 #include "i40evf.h"
31 #include "i40e_prototype.h"
32
33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 u32 td_tag)
35 {
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41 }
42
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45 /**
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
49 **/
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
52 {
53 if (tx_buffer->skb) {
54 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
55 kfree(tx_buffer->raw_buf);
56 else
57 dev_kfree_skb_any(tx_buffer->skb);
58
59 if (dma_unmap_len(tx_buffer, len))
60 dma_unmap_single(ring->dev,
61 dma_unmap_addr(tx_buffer, dma),
62 dma_unmap_len(tx_buffer, len),
63 DMA_TO_DEVICE);
64 } else if (dma_unmap_len(tx_buffer, len)) {
65 dma_unmap_page(ring->dev,
66 dma_unmap_addr(tx_buffer, dma),
67 dma_unmap_len(tx_buffer, len),
68 DMA_TO_DEVICE);
69 }
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
74 }
75
76 /**
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
79 **/
80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81 {
82 unsigned long bi_size;
83 u16 i;
84
85 /* ring already cleared, nothing to do */
86 if (!tx_ring->tx_bi)
87 return;
88
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
95
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
98
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
101
102 if (!tx_ring->netdev)
103 return;
104
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
108 }
109
110 /**
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
113 *
114 * Free all transmit software resources
115 **/
116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117 {
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
121
122 if (tx_ring->desc) {
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
126 }
127 }
128
129 /**
130 * i40e_get_tx_pending - how many tx descriptors not processed
131 * @tx_ring: the ring of descriptors
132 *
133 * Since there is no access to the ring head register
134 * in XL710, we need to use our local copies
135 **/
136 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
137 {
138 u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
139 ? ring->next_to_use
140 : ring->next_to_use + ring->count);
141 return ntu - ring->next_to_clean;
142 }
143
144 /**
145 * i40e_check_tx_hang - Is there a hang in the Tx queue
146 * @tx_ring: the ring of descriptors
147 **/
148 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
149 {
150 u32 tx_pending = i40e_get_tx_pending(tx_ring);
151 bool ret = false;
152
153 clear_check_for_tx_hang(tx_ring);
154
155 /* Check for a hung queue, but be thorough. This verifies
156 * that a transmit has been completed since the previous
157 * check AND there is at least one packet pending. The
158 * ARMED bit is set to indicate a potential hang. The
159 * bit is cleared if a pause frame is received to remove
160 * false hang detection due to PFC or 802.3x frames. By
161 * requiring this to fail twice we avoid races with
162 * PFC clearing the ARMED bit and conditions where we
163 * run the check_tx_hang logic with a transmit completion
164 * pending but without time to complete it yet.
165 */
166 if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
167 (tx_pending >= I40E_MIN_DESC_PENDING)) {
168 /* make sure it is true for two checks in a row */
169 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
170 &tx_ring->state);
171 } else if (!(tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) ||
172 !(tx_pending < I40E_MIN_DESC_PENDING) ||
173 !(tx_pending > 0)) {
174 /* update completed stats and disarm the hang check */
175 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
176 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
177 }
178
179 return ret;
180 }
181
182 /**
183 * i40e_get_head - Retrieve head from head writeback
184 * @tx_ring: tx ring to fetch head of
185 *
186 * Returns value of Tx ring head based on value stored
187 * in head write-back location
188 **/
189 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
190 {
191 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
192
193 return le32_to_cpu(*(volatile __le32 *)head);
194 }
195
196 #define WB_STRIDE 0x3
197
198 /**
199 * i40e_clean_tx_irq - Reclaim resources after transmit completes
200 * @tx_ring: tx ring to clean
201 * @budget: how many cleans we're allowed
202 *
203 * Returns true if there's any budget left (e.g. the clean is finished)
204 **/
205 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
206 {
207 u16 i = tx_ring->next_to_clean;
208 struct i40e_tx_buffer *tx_buf;
209 struct i40e_tx_desc *tx_head;
210 struct i40e_tx_desc *tx_desc;
211 unsigned int total_packets = 0;
212 unsigned int total_bytes = 0;
213
214 tx_buf = &tx_ring->tx_bi[i];
215 tx_desc = I40E_TX_DESC(tx_ring, i);
216 i -= tx_ring->count;
217
218 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
219
220 do {
221 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
222
223 /* if next_to_watch is not set then there is no work pending */
224 if (!eop_desc)
225 break;
226
227 /* prevent any other reads prior to eop_desc */
228 read_barrier_depends();
229
230 /* we have caught up to head, no work left to do */
231 if (tx_head == tx_desc)
232 break;
233
234 /* clear next_to_watch to prevent false hangs */
235 tx_buf->next_to_watch = NULL;
236
237 /* update the statistics for this packet */
238 total_bytes += tx_buf->bytecount;
239 total_packets += tx_buf->gso_segs;
240
241 /* free the skb */
242 dev_kfree_skb_any(tx_buf->skb);
243
244 /* unmap skb header data */
245 dma_unmap_single(tx_ring->dev,
246 dma_unmap_addr(tx_buf, dma),
247 dma_unmap_len(tx_buf, len),
248 DMA_TO_DEVICE);
249
250 /* clear tx_buffer data */
251 tx_buf->skb = NULL;
252 dma_unmap_len_set(tx_buf, len, 0);
253
254 /* unmap remaining buffers */
255 while (tx_desc != eop_desc) {
256
257 tx_buf++;
258 tx_desc++;
259 i++;
260 if (unlikely(!i)) {
261 i -= tx_ring->count;
262 tx_buf = tx_ring->tx_bi;
263 tx_desc = I40E_TX_DESC(tx_ring, 0);
264 }
265
266 /* unmap any remaining paged data */
267 if (dma_unmap_len(tx_buf, len)) {
268 dma_unmap_page(tx_ring->dev,
269 dma_unmap_addr(tx_buf, dma),
270 dma_unmap_len(tx_buf, len),
271 DMA_TO_DEVICE);
272 dma_unmap_len_set(tx_buf, len, 0);
273 }
274 }
275
276 /* move us one more past the eop_desc for start of next pkt */
277 tx_buf++;
278 tx_desc++;
279 i++;
280 if (unlikely(!i)) {
281 i -= tx_ring->count;
282 tx_buf = tx_ring->tx_bi;
283 tx_desc = I40E_TX_DESC(tx_ring, 0);
284 }
285
286 /* update budget accounting */
287 budget--;
288 } while (likely(budget));
289
290 i += tx_ring->count;
291 tx_ring->next_to_clean = i;
292 u64_stats_update_begin(&tx_ring->syncp);
293 tx_ring->stats.bytes += total_bytes;
294 tx_ring->stats.packets += total_packets;
295 u64_stats_update_end(&tx_ring->syncp);
296 tx_ring->q_vector->tx.total_bytes += total_bytes;
297 tx_ring->q_vector->tx.total_packets += total_packets;
298
299 if (budget &&
300 !((i & WB_STRIDE) == WB_STRIDE) &&
301 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
302 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
303 tx_ring->arm_wb = true;
304 else
305 tx_ring->arm_wb = false;
306
307 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
308 /* schedule immediate reset if we believe we hung */
309 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
310 " VSI <%d>\n"
311 " Tx Queue <%d>\n"
312 " next_to_use <%x>\n"
313 " next_to_clean <%x>\n",
314 tx_ring->vsi->seid,
315 tx_ring->queue_index,
316 tx_ring->next_to_use, i);
317 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
318 " time_stamp <%lx>\n"
319 " jiffies <%lx>\n",
320 tx_ring->tx_bi[i].time_stamp, jiffies);
321
322 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
323
324 dev_info(tx_ring->dev,
325 "tx hang detected on queue %d, resetting adapter\n",
326 tx_ring->queue_index);
327
328 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
329
330 /* the adapter is about to reset, no point in enabling stuff */
331 return true;
332 }
333
334 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
335 tx_ring->queue_index),
336 total_packets, total_bytes);
337
338 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
339 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
340 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
341 /* Make sure that anybody stopping the queue after this
342 * sees the new next_to_clean.
343 */
344 smp_mb();
345 if (__netif_subqueue_stopped(tx_ring->netdev,
346 tx_ring->queue_index) &&
347 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
348 netif_wake_subqueue(tx_ring->netdev,
349 tx_ring->queue_index);
350 ++tx_ring->tx_stats.restart_queue;
351 }
352 }
353
354 return budget > 0;
355 }
356
357 /**
358 * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
359 * @vsi: the VSI we care about
360 * @q_vector: the vector on which to force writeback
361 *
362 **/
363 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
364 {
365 u32 val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
366 I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
367 I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
368 /* allow 00 to be written to the index */
369
370 wr32(&vsi->back->hw,
371 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
372 val);
373 }
374
375 /**
376 * i40e_set_new_dynamic_itr - Find new ITR level
377 * @rc: structure containing ring performance data
378 *
379 * Stores a new ITR value based on packets and byte counts during
380 * the last interrupt. The advantage of per interrupt computation
381 * is faster updates and more accurate ITR for the current traffic
382 * pattern. Constants in this function were computed based on
383 * theoretical maximum wire speed and thresholds were set based on
384 * testing data as well as attempting to minimize response time
385 * while increasing bulk throughput.
386 **/
387 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
388 {
389 enum i40e_latency_range new_latency_range = rc->latency_range;
390 u32 new_itr = rc->itr;
391 int bytes_per_int;
392
393 if (rc->total_packets == 0 || !rc->itr)
394 return;
395
396 /* simple throttlerate management
397 * 0-10MB/s lowest (100000 ints/s)
398 * 10-20MB/s low (20000 ints/s)
399 * 20-1249MB/s bulk (8000 ints/s)
400 */
401 bytes_per_int = rc->total_bytes / rc->itr;
402 switch (rc->itr) {
403 case I40E_LOWEST_LATENCY:
404 if (bytes_per_int > 10)
405 new_latency_range = I40E_LOW_LATENCY;
406 break;
407 case I40E_LOW_LATENCY:
408 if (bytes_per_int > 20)
409 new_latency_range = I40E_BULK_LATENCY;
410 else if (bytes_per_int <= 10)
411 new_latency_range = I40E_LOWEST_LATENCY;
412 break;
413 case I40E_BULK_LATENCY:
414 if (bytes_per_int <= 20)
415 rc->latency_range = I40E_LOW_LATENCY;
416 break;
417 }
418
419 switch (new_latency_range) {
420 case I40E_LOWEST_LATENCY:
421 new_itr = I40E_ITR_100K;
422 break;
423 case I40E_LOW_LATENCY:
424 new_itr = I40E_ITR_20K;
425 break;
426 case I40E_BULK_LATENCY:
427 new_itr = I40E_ITR_8K;
428 break;
429 default:
430 break;
431 }
432
433 if (new_itr != rc->itr) {
434 /* do an exponential smoothing */
435 new_itr = (10 * new_itr * rc->itr) /
436 ((9 * new_itr) + rc->itr);
437 rc->itr = new_itr & I40E_MAX_ITR;
438 }
439
440 rc->total_bytes = 0;
441 rc->total_packets = 0;
442 }
443
444 /**
445 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
446 * @q_vector: the vector to adjust
447 **/
448 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
449 {
450 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
451 struct i40e_hw *hw = &q_vector->vsi->back->hw;
452 u32 reg_addr;
453 u16 old_itr;
454
455 reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
456 old_itr = q_vector->rx.itr;
457 i40e_set_new_dynamic_itr(&q_vector->rx);
458 if (old_itr != q_vector->rx.itr)
459 wr32(hw, reg_addr, q_vector->rx.itr);
460
461 reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
462 old_itr = q_vector->tx.itr;
463 i40e_set_new_dynamic_itr(&q_vector->tx);
464 if (old_itr != q_vector->tx.itr)
465 wr32(hw, reg_addr, q_vector->tx.itr);
466 }
467
468 /**
469 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
470 * @tx_ring: the tx ring to set up
471 *
472 * Return 0 on success, negative on error
473 **/
474 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
475 {
476 struct device *dev = tx_ring->dev;
477 int bi_size;
478
479 if (!dev)
480 return -ENOMEM;
481
482 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
483 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
484 if (!tx_ring->tx_bi)
485 goto err;
486
487 /* round up to nearest 4K */
488 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
489 /* add u32 for head writeback, align after this takes care of
490 * guaranteeing this is at least one cache line in size
491 */
492 tx_ring->size += sizeof(u32);
493 tx_ring->size = ALIGN(tx_ring->size, 4096);
494 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
495 &tx_ring->dma, GFP_KERNEL);
496 if (!tx_ring->desc) {
497 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
498 tx_ring->size);
499 goto err;
500 }
501
502 tx_ring->next_to_use = 0;
503 tx_ring->next_to_clean = 0;
504 return 0;
505
506 err:
507 kfree(tx_ring->tx_bi);
508 tx_ring->tx_bi = NULL;
509 return -ENOMEM;
510 }
511
512 /**
513 * i40evf_clean_rx_ring - Free Rx buffers
514 * @rx_ring: ring to be cleaned
515 **/
516 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
517 {
518 struct device *dev = rx_ring->dev;
519 struct i40e_rx_buffer *rx_bi;
520 unsigned long bi_size;
521 u16 i;
522
523 /* ring already cleared, nothing to do */
524 if (!rx_ring->rx_bi)
525 return;
526
527 if (ring_is_ps_enabled(rx_ring)) {
528 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
529
530 rx_bi = &rx_ring->rx_bi[0];
531 if (rx_bi->hdr_buf) {
532 dma_free_coherent(dev,
533 bufsz,
534 rx_bi->hdr_buf,
535 rx_bi->dma);
536 for (i = 0; i < rx_ring->count; i++) {
537 rx_bi = &rx_ring->rx_bi[i];
538 rx_bi->dma = 0;
539 rx_bi->hdr_buf = 0;
540 }
541 }
542 }
543 /* Free all the Rx ring sk_buffs */
544 for (i = 0; i < rx_ring->count; i++) {
545 rx_bi = &rx_ring->rx_bi[i];
546 if (rx_bi->dma) {
547 dma_unmap_single(dev,
548 rx_bi->dma,
549 rx_ring->rx_buf_len,
550 DMA_FROM_DEVICE);
551 rx_bi->dma = 0;
552 }
553 if (rx_bi->skb) {
554 dev_kfree_skb(rx_bi->skb);
555 rx_bi->skb = NULL;
556 }
557 if (rx_bi->page) {
558 if (rx_bi->page_dma) {
559 dma_unmap_page(dev,
560 rx_bi->page_dma,
561 PAGE_SIZE / 2,
562 DMA_FROM_DEVICE);
563 rx_bi->page_dma = 0;
564 }
565 __free_page(rx_bi->page);
566 rx_bi->page = NULL;
567 rx_bi->page_offset = 0;
568 }
569 }
570
571 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
572 memset(rx_ring->rx_bi, 0, bi_size);
573
574 /* Zero out the descriptor ring */
575 memset(rx_ring->desc, 0, rx_ring->size);
576
577 rx_ring->next_to_clean = 0;
578 rx_ring->next_to_use = 0;
579 }
580
581 /**
582 * i40evf_free_rx_resources - Free Rx resources
583 * @rx_ring: ring to clean the resources from
584 *
585 * Free all receive software resources
586 **/
587 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
588 {
589 i40evf_clean_rx_ring(rx_ring);
590 kfree(rx_ring->rx_bi);
591 rx_ring->rx_bi = NULL;
592
593 if (rx_ring->desc) {
594 dma_free_coherent(rx_ring->dev, rx_ring->size,
595 rx_ring->desc, rx_ring->dma);
596 rx_ring->desc = NULL;
597 }
598 }
599
600 /**
601 * i40evf_alloc_rx_headers - allocate rx header buffers
602 * @rx_ring: ring to alloc buffers
603 *
604 * Allocate rx header buffers for the entire ring. As these are static,
605 * this is only called when setting up a new ring.
606 **/
607 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
608 {
609 struct device *dev = rx_ring->dev;
610 struct i40e_rx_buffer *rx_bi;
611 dma_addr_t dma;
612 void *buffer;
613 int buf_size;
614 int i;
615
616 if (rx_ring->rx_bi[0].hdr_buf)
617 return;
618 /* Make sure the buffers don't cross cache line boundaries. */
619 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
620 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
621 &dma, GFP_KERNEL);
622 if (!buffer)
623 return;
624 for (i = 0; i < rx_ring->count; i++) {
625 rx_bi = &rx_ring->rx_bi[i];
626 rx_bi->dma = dma + (i * buf_size);
627 rx_bi->hdr_buf = buffer + (i * buf_size);
628 }
629 }
630
631 /**
632 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
633 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
634 *
635 * Returns 0 on success, negative on failure
636 **/
637 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
638 {
639 struct device *dev = rx_ring->dev;
640 int bi_size;
641
642 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
643 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
644 if (!rx_ring->rx_bi)
645 goto err;
646
647 u64_stats_init(&rx_ring->syncp);
648
649 /* Round up to nearest 4K */
650 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
651 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
652 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
653 rx_ring->size = ALIGN(rx_ring->size, 4096);
654 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
655 &rx_ring->dma, GFP_KERNEL);
656
657 if (!rx_ring->desc) {
658 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
659 rx_ring->size);
660 goto err;
661 }
662
663 rx_ring->next_to_clean = 0;
664 rx_ring->next_to_use = 0;
665
666 return 0;
667 err:
668 kfree(rx_ring->rx_bi);
669 rx_ring->rx_bi = NULL;
670 return -ENOMEM;
671 }
672
673 /**
674 * i40e_release_rx_desc - Store the new tail and head values
675 * @rx_ring: ring to bump
676 * @val: new head index
677 **/
678 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
679 {
680 rx_ring->next_to_use = val;
681 /* Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
686 wmb();
687 writel(val, rx_ring->tail);
688 }
689
690 /**
691 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
692 * @rx_ring: ring to place buffers on
693 * @cleaned_count: number of buffers to replace
694 **/
695 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
696 {
697 u16 i = rx_ring->next_to_use;
698 union i40e_rx_desc *rx_desc;
699 struct i40e_rx_buffer *bi;
700
701 /* do nothing if no valid netdev defined */
702 if (!rx_ring->netdev || !cleaned_count)
703 return;
704
705 while (cleaned_count--) {
706 rx_desc = I40E_RX_DESC(rx_ring, i);
707 bi = &rx_ring->rx_bi[i];
708
709 if (bi->skb) /* desc is in use */
710 goto no_buffers;
711 if (!bi->page) {
712 bi->page = alloc_page(GFP_ATOMIC);
713 if (!bi->page) {
714 rx_ring->rx_stats.alloc_page_failed++;
715 goto no_buffers;
716 }
717 }
718
719 if (!bi->page_dma) {
720 /* use a half page if we're re-using */
721 bi->page_offset ^= PAGE_SIZE / 2;
722 bi->page_dma = dma_map_page(rx_ring->dev,
723 bi->page,
724 bi->page_offset,
725 PAGE_SIZE / 2,
726 DMA_FROM_DEVICE);
727 if (dma_mapping_error(rx_ring->dev,
728 bi->page_dma)) {
729 rx_ring->rx_stats.alloc_page_failed++;
730 bi->page_dma = 0;
731 goto no_buffers;
732 }
733 }
734
735 dma_sync_single_range_for_device(rx_ring->dev,
736 bi->dma,
737 0,
738 rx_ring->rx_hdr_len,
739 DMA_FROM_DEVICE);
740 /* Refresh the desc even if buffer_addrs didn't change
741 * because each write-back erases this info.
742 */
743 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
744 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
745 i++;
746 if (i == rx_ring->count)
747 i = 0;
748 }
749
750 no_buffers:
751 if (rx_ring->next_to_use != i)
752 i40e_release_rx_desc(rx_ring, i);
753 }
754
755 /**
756 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
757 * @rx_ring: ring to place buffers on
758 * @cleaned_count: number of buffers to replace
759 **/
760 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
761 {
762 u16 i = rx_ring->next_to_use;
763 union i40e_rx_desc *rx_desc;
764 struct i40e_rx_buffer *bi;
765 struct sk_buff *skb;
766
767 /* do nothing if no valid netdev defined */
768 if (!rx_ring->netdev || !cleaned_count)
769 return;
770
771 while (cleaned_count--) {
772 rx_desc = I40E_RX_DESC(rx_ring, i);
773 bi = &rx_ring->rx_bi[i];
774 skb = bi->skb;
775
776 if (!skb) {
777 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
778 rx_ring->rx_buf_len);
779 if (!skb) {
780 rx_ring->rx_stats.alloc_buff_failed++;
781 goto no_buffers;
782 }
783 /* initialize queue mapping */
784 skb_record_rx_queue(skb, rx_ring->queue_index);
785 bi->skb = skb;
786 }
787
788 if (!bi->dma) {
789 bi->dma = dma_map_single(rx_ring->dev,
790 skb->data,
791 rx_ring->rx_buf_len,
792 DMA_FROM_DEVICE);
793 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
794 rx_ring->rx_stats.alloc_buff_failed++;
795 bi->dma = 0;
796 goto no_buffers;
797 }
798 }
799
800 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
801 rx_desc->read.hdr_addr = 0;
802 i++;
803 if (i == rx_ring->count)
804 i = 0;
805 }
806
807 no_buffers:
808 if (rx_ring->next_to_use != i)
809 i40e_release_rx_desc(rx_ring, i);
810 }
811
812 /**
813 * i40e_receive_skb - Send a completed packet up the stack
814 * @rx_ring: rx ring in play
815 * @skb: packet to send up
816 * @vlan_tag: vlan tag for packet
817 **/
818 static void i40e_receive_skb(struct i40e_ring *rx_ring,
819 struct sk_buff *skb, u16 vlan_tag)
820 {
821 struct i40e_q_vector *q_vector = rx_ring->q_vector;
822 struct i40e_vsi *vsi = rx_ring->vsi;
823 u64 flags = vsi->back->flags;
824
825 if (vlan_tag & VLAN_VID_MASK)
826 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
827
828 if (flags & I40E_FLAG_IN_NETPOLL)
829 netif_rx(skb);
830 else
831 napi_gro_receive(&q_vector->napi, skb);
832 }
833
834 /**
835 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
836 * @vsi: the VSI we care about
837 * @skb: skb currently being received and modified
838 * @rx_status: status value of last descriptor in packet
839 * @rx_error: error value of last descriptor in packet
840 * @rx_ptype: ptype value of last descriptor in packet
841 **/
842 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
843 struct sk_buff *skb,
844 u32 rx_status,
845 u32 rx_error,
846 u16 rx_ptype)
847 {
848 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
849 bool ipv4 = false, ipv6 = false;
850 bool ipv4_tunnel, ipv6_tunnel;
851 __wsum rx_udp_csum;
852 struct iphdr *iph;
853 __sum16 csum;
854
855 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
856 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
857 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
858 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
859
860 skb->ip_summed = CHECKSUM_NONE;
861
862 /* Rx csum enabled and ip headers found? */
863 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
864 return;
865
866 /* did the hardware decode the packet and checksum? */
867 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
868 return;
869
870 /* both known and outer_ip must be set for the below code to work */
871 if (!(decoded.known && decoded.outer_ip))
872 return;
873
874 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
875 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
876 ipv4 = true;
877 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
878 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
879 ipv6 = true;
880
881 if (ipv4 &&
882 (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
883 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
884 goto checksum_fail;
885
886 /* likely incorrect csum if alternate IP extension headers found */
887 if (ipv6 &&
888 rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
889 /* don't increment checksum err here, non-fatal err */
890 return;
891
892 /* there was some L4 error, count error and punt packet to the stack */
893 if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
894 goto checksum_fail;
895
896 /* handle packets that were not able to be checksummed due
897 * to arrival speed, in this case the stack can compute
898 * the csum.
899 */
900 if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
901 return;
902
903 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
904 * it in the driver, hardware does not do it for us.
905 * Since L3L4P bit was set we assume a valid IHL value (>=5)
906 * so the total length of IPv4 header is IHL*4 bytes
907 * The UDP_0 bit *may* bet set if the *inner* header is UDP
908 */
909 if (ipv4_tunnel &&
910 (decoded.inner_prot != I40E_RX_PTYPE_INNER_PROT_UDP) &&
911 !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
912 skb->transport_header = skb->mac_header +
913 sizeof(struct ethhdr) +
914 (ip_hdr(skb)->ihl * 4);
915
916 /* Add 4 bytes for VLAN tagged packets */
917 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
918 skb->protocol == htons(ETH_P_8021AD))
919 ? VLAN_HLEN : 0;
920
921 rx_udp_csum = udp_csum(skb);
922 iph = ip_hdr(skb);
923 csum = csum_tcpudp_magic(
924 iph->saddr, iph->daddr,
925 (skb->len - skb_transport_offset(skb)),
926 IPPROTO_UDP, rx_udp_csum);
927
928 if (udp_hdr(skb)->check != csum)
929 goto checksum_fail;
930 }
931
932 skb->ip_summed = CHECKSUM_UNNECESSARY;
933 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
934
935 return;
936
937 checksum_fail:
938 vsi->back->hw_csum_rx_error++;
939 }
940
941 /**
942 * i40e_rx_hash - returns the hash value from the Rx descriptor
943 * @ring: descriptor ring
944 * @rx_desc: specific descriptor
945 **/
946 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
947 union i40e_rx_desc *rx_desc)
948 {
949 const __le64 rss_mask =
950 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
951 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
952
953 if ((ring->netdev->features & NETIF_F_RXHASH) &&
954 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
955 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
956 else
957 return 0;
958 }
959
960 /**
961 * i40e_ptype_to_hash - get a hash type
962 * @ptype: the ptype value from the descriptor
963 *
964 * Returns a hash type to be used by skb_set_hash
965 **/
966 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
967 {
968 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
969
970 if (!decoded.known)
971 return PKT_HASH_TYPE_NONE;
972
973 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
974 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
975 return PKT_HASH_TYPE_L4;
976 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
977 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
978 return PKT_HASH_TYPE_L3;
979 else
980 return PKT_HASH_TYPE_L2;
981 }
982
983 /**
984 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
985 * @rx_ring: rx ring to clean
986 * @budget: how many cleans we're allowed
987 *
988 * Returns true if there's any budget left (e.g. the clean is finished)
989 **/
990 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
991 {
992 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
993 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
994 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
995 const int current_node = numa_node_id();
996 struct i40e_vsi *vsi = rx_ring->vsi;
997 u16 i = rx_ring->next_to_clean;
998 union i40e_rx_desc *rx_desc;
999 u32 rx_error, rx_status;
1000 u8 rx_ptype;
1001 u64 qword;
1002
1003 do {
1004 struct i40e_rx_buffer *rx_bi;
1005 struct sk_buff *skb;
1006 u16 vlan_tag;
1007 /* return some buffers to hardware, one at a time is too slow */
1008 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1009 i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1010 cleaned_count = 0;
1011 }
1012
1013 i = rx_ring->next_to_clean;
1014 rx_desc = I40E_RX_DESC(rx_ring, i);
1015 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1016 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1017 I40E_RXD_QW1_STATUS_SHIFT;
1018
1019 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1020 break;
1021
1022 /* This memory barrier is needed to keep us from reading
1023 * any other fields out of the rx_desc until we know the
1024 * DD bit is set.
1025 */
1026 rmb();
1027 rx_bi = &rx_ring->rx_bi[i];
1028 skb = rx_bi->skb;
1029 if (likely(!skb)) {
1030 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1031 rx_ring->rx_hdr_len);
1032 if (!skb)
1033 rx_ring->rx_stats.alloc_buff_failed++;
1034 /* initialize queue mapping */
1035 skb_record_rx_queue(skb, rx_ring->queue_index);
1036 /* we are reusing so sync this buffer for CPU use */
1037 dma_sync_single_range_for_cpu(rx_ring->dev,
1038 rx_bi->dma,
1039 0,
1040 rx_ring->rx_hdr_len,
1041 DMA_FROM_DEVICE);
1042 }
1043 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1044 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1045 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1046 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1047 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1048 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1049
1050 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1051 I40E_RXD_QW1_ERROR_SHIFT;
1052 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1053 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1054
1055 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1056 I40E_RXD_QW1_PTYPE_SHIFT;
1057 prefetch(rx_bi->page);
1058 rx_bi->skb = NULL;
1059 cleaned_count++;
1060 if (rx_hbo || rx_sph) {
1061 int len;
1062 if (rx_hbo)
1063 len = I40E_RX_HDR_SIZE;
1064 else
1065 len = rx_header_len;
1066 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1067 } else if (skb->len == 0) {
1068 int len;
1069
1070 len = (rx_packet_len > skb_headlen(skb) ?
1071 skb_headlen(skb) : rx_packet_len);
1072 memcpy(__skb_put(skb, len),
1073 rx_bi->page + rx_bi->page_offset,
1074 len);
1075 rx_bi->page_offset += len;
1076 rx_packet_len -= len;
1077 }
1078
1079 /* Get the rest of the data if this was a header split */
1080 if (rx_packet_len) {
1081 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1082 rx_bi->page,
1083 rx_bi->page_offset,
1084 rx_packet_len);
1085
1086 skb->len += rx_packet_len;
1087 skb->data_len += rx_packet_len;
1088 skb->truesize += rx_packet_len;
1089
1090 if ((page_count(rx_bi->page) == 1) &&
1091 (page_to_nid(rx_bi->page) == current_node))
1092 get_page(rx_bi->page);
1093 else
1094 rx_bi->page = NULL;
1095
1096 dma_unmap_page(rx_ring->dev,
1097 rx_bi->page_dma,
1098 PAGE_SIZE / 2,
1099 DMA_FROM_DEVICE);
1100 rx_bi->page_dma = 0;
1101 }
1102 I40E_RX_INCREMENT(rx_ring, i);
1103
1104 if (unlikely(
1105 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1106 struct i40e_rx_buffer *next_buffer;
1107
1108 next_buffer = &rx_ring->rx_bi[i];
1109 next_buffer->skb = skb;
1110 rx_ring->rx_stats.non_eop_descs++;
1111 continue;
1112 }
1113
1114 /* ERR_MASK will only have valid bits if EOP set */
1115 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1116 dev_kfree_skb_any(skb);
1117 /* TODO: shouldn't we increment a counter indicating the
1118 * drop?
1119 */
1120 continue;
1121 }
1122
1123 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1124 i40e_ptype_to_hash(rx_ptype));
1125 /* probably a little skewed due to removing CRC */
1126 total_rx_bytes += skb->len;
1127 total_rx_packets++;
1128
1129 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1130
1131 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1132
1133 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1134 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1135 : 0;
1136 #ifdef I40E_FCOE
1137 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1138 dev_kfree_skb_any(skb);
1139 continue;
1140 }
1141 #endif
1142 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1143 i40e_receive_skb(rx_ring, skb, vlan_tag);
1144
1145 rx_ring->netdev->last_rx = jiffies;
1146 rx_desc->wb.qword1.status_error_len = 0;
1147
1148 } while (likely(total_rx_packets < budget));
1149
1150 u64_stats_update_begin(&rx_ring->syncp);
1151 rx_ring->stats.packets += total_rx_packets;
1152 rx_ring->stats.bytes += total_rx_bytes;
1153 u64_stats_update_end(&rx_ring->syncp);
1154 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1155 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1156
1157 return total_rx_packets;
1158 }
1159
1160 /**
1161 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1162 * @rx_ring: rx ring to clean
1163 * @budget: how many cleans we're allowed
1164 *
1165 * Returns number of packets cleaned
1166 **/
1167 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1168 {
1169 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1170 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1171 struct i40e_vsi *vsi = rx_ring->vsi;
1172 union i40e_rx_desc *rx_desc;
1173 u32 rx_error, rx_status;
1174 u16 rx_packet_len;
1175 u8 rx_ptype;
1176 u64 qword;
1177 u16 i;
1178
1179 do {
1180 struct i40e_rx_buffer *rx_bi;
1181 struct sk_buff *skb;
1182 u16 vlan_tag;
1183 /* return some buffers to hardware, one at a time is too slow */
1184 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1185 i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1186 cleaned_count = 0;
1187 }
1188
1189 i = rx_ring->next_to_clean;
1190 rx_desc = I40E_RX_DESC(rx_ring, i);
1191 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1192 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1193 I40E_RXD_QW1_STATUS_SHIFT;
1194
1195 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1196 break;
1197
1198 /* This memory barrier is needed to keep us from reading
1199 * any other fields out of the rx_desc until we know the
1200 * DD bit is set.
1201 */
1202 rmb();
1203
1204 rx_bi = &rx_ring->rx_bi[i];
1205 skb = rx_bi->skb;
1206 prefetch(skb->data);
1207
1208 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1209 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1210
1211 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1212 I40E_RXD_QW1_ERROR_SHIFT;
1213 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1214
1215 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1216 I40E_RXD_QW1_PTYPE_SHIFT;
1217 rx_bi->skb = NULL;
1218 cleaned_count++;
1219
1220 /* Get the header and possibly the whole packet
1221 * If this is an skb from previous receive dma will be 0
1222 */
1223 skb_put(skb, rx_packet_len);
1224 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1225 DMA_FROM_DEVICE);
1226 rx_bi->dma = 0;
1227
1228 I40E_RX_INCREMENT(rx_ring, i);
1229
1230 if (unlikely(
1231 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1232 rx_ring->rx_stats.non_eop_descs++;
1233 continue;
1234 }
1235
1236 /* ERR_MASK will only have valid bits if EOP set */
1237 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1238 dev_kfree_skb_any(skb);
1239 /* TODO: shouldn't we increment a counter indicating the
1240 * drop?
1241 */
1242 continue;
1243 }
1244
1245 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1246 i40e_ptype_to_hash(rx_ptype));
1247 /* probably a little skewed due to removing CRC */
1248 total_rx_bytes += skb->len;
1249 total_rx_packets++;
1250
1251 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1252
1253 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1254
1255 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1256 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1257 : 0;
1258 i40e_receive_skb(rx_ring, skb, vlan_tag);
1259
1260 rx_ring->netdev->last_rx = jiffies;
1261 rx_desc->wb.qword1.status_error_len = 0;
1262 } while (likely(total_rx_packets < budget));
1263
1264 u64_stats_update_begin(&rx_ring->syncp);
1265 rx_ring->stats.packets += total_rx_packets;
1266 rx_ring->stats.bytes += total_rx_bytes;
1267 u64_stats_update_end(&rx_ring->syncp);
1268 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1269 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1270
1271 return total_rx_packets;
1272 }
1273
1274 /**
1275 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1276 * @napi: napi struct with our devices info in it
1277 * @budget: amount of work driver is allowed to do this pass, in packets
1278 *
1279 * This function will clean all queues associated with a q_vector.
1280 *
1281 * Returns the amount of work done
1282 **/
1283 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1284 {
1285 struct i40e_q_vector *q_vector =
1286 container_of(napi, struct i40e_q_vector, napi);
1287 struct i40e_vsi *vsi = q_vector->vsi;
1288 struct i40e_ring *ring;
1289 bool clean_complete = true;
1290 bool arm_wb = false;
1291 int budget_per_ring;
1292 int cleaned;
1293
1294 if (test_bit(__I40E_DOWN, &vsi->state)) {
1295 napi_complete(napi);
1296 return 0;
1297 }
1298
1299 /* Since the actual Tx work is minimal, we can give the Tx a larger
1300 * budget and be more aggressive about cleaning up the Tx descriptors.
1301 */
1302 i40e_for_each_ring(ring, q_vector->tx) {
1303 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1304 arm_wb |= ring->arm_wb;
1305 }
1306
1307 /* We attempt to distribute budget to each Rx queue fairly, but don't
1308 * allow the budget to go below 1 because that would exit polling early.
1309 */
1310 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1311
1312 i40e_for_each_ring(ring, q_vector->rx) {
1313 if (ring_is_ps_enabled(ring))
1314 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1315 else
1316 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1317 /* if we didn't clean as many as budgeted, we must be done */
1318 clean_complete &= (budget_per_ring != cleaned);
1319 }
1320
1321 /* If work not completed, return budget and polling will return */
1322 if (!clean_complete) {
1323 if (arm_wb)
1324 i40e_force_wb(vsi, q_vector);
1325 return budget;
1326 }
1327
1328 /* Work is done so exit the polling mode and re-enable the interrupt */
1329 napi_complete(napi);
1330 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1331 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1332 i40e_update_dynamic_itr(q_vector);
1333
1334 if (!test_bit(__I40E_DOWN, &vsi->state))
1335 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1336
1337 return 0;
1338 }
1339
1340 /**
1341 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1342 * @skb: send buffer
1343 * @tx_ring: ring to send buffer on
1344 * @flags: the tx flags to be set
1345 *
1346 * Checks the skb and set up correspondingly several generic transmit flags
1347 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1348 *
1349 * Returns error code indicate the frame should be dropped upon error and the
1350 * otherwise returns 0 to indicate the flags has been set properly.
1351 **/
1352 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1353 struct i40e_ring *tx_ring,
1354 u32 *flags)
1355 {
1356 __be16 protocol = skb->protocol;
1357 u32 tx_flags = 0;
1358
1359 /* if we have a HW VLAN tag being added, default to the HW one */
1360 if (skb_vlan_tag_present(skb)) {
1361 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1362 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1363 /* else if it is a SW VLAN, check the next protocol and store the tag */
1364 } else if (protocol == htons(ETH_P_8021Q)) {
1365 struct vlan_hdr *vhdr, _vhdr;
1366 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1367 if (!vhdr)
1368 return -EINVAL;
1369
1370 protocol = vhdr->h_vlan_encapsulated_proto;
1371 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1372 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1373 }
1374
1375 *flags = tx_flags;
1376 return 0;
1377 }
1378
1379 /**
1380 * i40e_tso - set up the tso context descriptor
1381 * @tx_ring: ptr to the ring to send
1382 * @skb: ptr to the skb we're sending
1383 * @tx_flags: the collected send information
1384 * @protocol: the send protocol
1385 * @hdr_len: ptr to the size of the packet header
1386 * @cd_tunneling: ptr to context descriptor bits
1387 *
1388 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1389 **/
1390 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1391 u32 tx_flags, __be16 protocol, u8 *hdr_len,
1392 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1393 {
1394 u32 cd_cmd, cd_tso_len, cd_mss;
1395 struct ipv6hdr *ipv6h;
1396 struct tcphdr *tcph;
1397 struct iphdr *iph;
1398 u32 l4len;
1399 int err;
1400
1401 if (!skb_is_gso(skb))
1402 return 0;
1403
1404 err = skb_cow_head(skb, 0);
1405 if (err < 0)
1406 return err;
1407
1408 if (protocol == htons(ETH_P_IP)) {
1409 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1410 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1411 iph->tot_len = 0;
1412 iph->check = 0;
1413 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1414 0, IPPROTO_TCP, 0);
1415 } else if (skb_is_gso_v6(skb)) {
1416
1417 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1418 : ipv6_hdr(skb);
1419 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1420 ipv6h->payload_len = 0;
1421 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1422 0, IPPROTO_TCP, 0);
1423 }
1424
1425 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1426 *hdr_len = (skb->encapsulation
1427 ? (skb_inner_transport_header(skb) - skb->data)
1428 : skb_transport_offset(skb)) + l4len;
1429
1430 /* find the field values */
1431 cd_cmd = I40E_TX_CTX_DESC_TSO;
1432 cd_tso_len = skb->len - *hdr_len;
1433 cd_mss = skb_shinfo(skb)->gso_size;
1434 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1435 ((u64)cd_tso_len <<
1436 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1437 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1438 return 1;
1439 }
1440
1441 /**
1442 * i40e_tx_enable_csum - Enable Tx checksum offloads
1443 * @skb: send buffer
1444 * @tx_flags: Tx flags currently set
1445 * @td_cmd: Tx descriptor command bits to set
1446 * @td_offset: Tx descriptor header offsets to set
1447 * @cd_tunneling: ptr to context desc bits
1448 **/
1449 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1450 u32 *td_cmd, u32 *td_offset,
1451 struct i40e_ring *tx_ring,
1452 u32 *cd_tunneling)
1453 {
1454 struct ipv6hdr *this_ipv6_hdr;
1455 unsigned int this_tcp_hdrlen;
1456 struct iphdr *this_ip_hdr;
1457 u32 network_hdr_len;
1458 u8 l4_hdr = 0;
1459
1460 if (skb->encapsulation) {
1461 network_hdr_len = skb_inner_network_header_len(skb);
1462 this_ip_hdr = inner_ip_hdr(skb);
1463 this_ipv6_hdr = inner_ipv6_hdr(skb);
1464 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1465
1466 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1467
1468 if (tx_flags & I40E_TX_FLAGS_TSO) {
1469 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1470 ip_hdr(skb)->check = 0;
1471 } else {
1472 *cd_tunneling |=
1473 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1474 }
1475 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1476 if (tx_flags & I40E_TX_FLAGS_TSO) {
1477 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1478 ip_hdr(skb)->check = 0;
1479 } else {
1480 *cd_tunneling |=
1481 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1482 }
1483 }
1484
1485 /* Now set the ctx descriptor fields */
1486 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1487 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1488 I40E_TXD_CTX_UDP_TUNNELING |
1489 ((skb_inner_network_offset(skb) -
1490 skb_transport_offset(skb)) >> 1) <<
1491 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1492
1493 } else {
1494 network_hdr_len = skb_network_header_len(skb);
1495 this_ip_hdr = ip_hdr(skb);
1496 this_ipv6_hdr = ipv6_hdr(skb);
1497 this_tcp_hdrlen = tcp_hdrlen(skb);
1498 }
1499
1500 /* Enable IP checksum offloads */
1501 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1502 l4_hdr = this_ip_hdr->protocol;
1503 /* the stack computes the IP header already, the only time we
1504 * need the hardware to recompute it is in the case of TSO.
1505 */
1506 if (tx_flags & I40E_TX_FLAGS_TSO) {
1507 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1508 this_ip_hdr->check = 0;
1509 } else {
1510 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1511 }
1512 /* Now set the td_offset for IP header length */
1513 *td_offset = (network_hdr_len >> 2) <<
1514 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1515 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1516 l4_hdr = this_ipv6_hdr->nexthdr;
1517 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1518 /* Now set the td_offset for IP header length */
1519 *td_offset = (network_hdr_len >> 2) <<
1520 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1521 }
1522 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1523 *td_offset |= (skb_network_offset(skb) >> 1) <<
1524 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1525
1526 /* Enable L4 checksum offloads */
1527 switch (l4_hdr) {
1528 case IPPROTO_TCP:
1529 /* enable checksum offloads */
1530 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1531 *td_offset |= (this_tcp_hdrlen >> 2) <<
1532 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1533 break;
1534 case IPPROTO_SCTP:
1535 /* enable SCTP checksum offload */
1536 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1537 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1538 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1539 break;
1540 case IPPROTO_UDP:
1541 /* enable UDP checksum offload */
1542 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1543 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1544 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1545 break;
1546 default:
1547 break;
1548 }
1549 }
1550
1551 /**
1552 * i40e_create_tx_ctx Build the Tx context descriptor
1553 * @tx_ring: ring to create the descriptor on
1554 * @cd_type_cmd_tso_mss: Quad Word 1
1555 * @cd_tunneling: Quad Word 0 - bits 0-31
1556 * @cd_l2tag2: Quad Word 0 - bits 32-63
1557 **/
1558 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1559 const u64 cd_type_cmd_tso_mss,
1560 const u32 cd_tunneling, const u32 cd_l2tag2)
1561 {
1562 struct i40e_tx_context_desc *context_desc;
1563 int i = tx_ring->next_to_use;
1564
1565 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1566 !cd_tunneling && !cd_l2tag2)
1567 return;
1568
1569 /* grab the next descriptor */
1570 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1571
1572 i++;
1573 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1574
1575 /* cpu_to_le32 and assign to struct fields */
1576 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1577 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1578 context_desc->rsvd = cpu_to_le16(0);
1579 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1580 }
1581
1582 /**
1583 * i40e_tx_map - Build the Tx descriptor
1584 * @tx_ring: ring to send buffer on
1585 * @skb: send buffer
1586 * @first: first buffer info buffer to use
1587 * @tx_flags: collected send information
1588 * @hdr_len: size of the packet header
1589 * @td_cmd: the command field in the descriptor
1590 * @td_offset: offset for checksum or crc
1591 **/
1592 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1593 struct i40e_tx_buffer *first, u32 tx_flags,
1594 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1595 {
1596 unsigned int data_len = skb->data_len;
1597 unsigned int size = skb_headlen(skb);
1598 struct skb_frag_struct *frag;
1599 struct i40e_tx_buffer *tx_bi;
1600 struct i40e_tx_desc *tx_desc;
1601 u16 i = tx_ring->next_to_use;
1602 u32 td_tag = 0;
1603 dma_addr_t dma;
1604 u16 gso_segs;
1605
1606 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1607 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1608 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1609 I40E_TX_FLAGS_VLAN_SHIFT;
1610 }
1611
1612 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1613 gso_segs = skb_shinfo(skb)->gso_segs;
1614 else
1615 gso_segs = 1;
1616
1617 /* multiply data chunks by size of headers */
1618 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1619 first->gso_segs = gso_segs;
1620 first->skb = skb;
1621 first->tx_flags = tx_flags;
1622
1623 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1624
1625 tx_desc = I40E_TX_DESC(tx_ring, i);
1626 tx_bi = first;
1627
1628 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1629 if (dma_mapping_error(tx_ring->dev, dma))
1630 goto dma_error;
1631
1632 /* record length, and DMA address */
1633 dma_unmap_len_set(tx_bi, len, size);
1634 dma_unmap_addr_set(tx_bi, dma, dma);
1635
1636 tx_desc->buffer_addr = cpu_to_le64(dma);
1637
1638 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1639 tx_desc->cmd_type_offset_bsz =
1640 build_ctob(td_cmd, td_offset,
1641 I40E_MAX_DATA_PER_TXD, td_tag);
1642
1643 tx_desc++;
1644 i++;
1645 if (i == tx_ring->count) {
1646 tx_desc = I40E_TX_DESC(tx_ring, 0);
1647 i = 0;
1648 }
1649
1650 dma += I40E_MAX_DATA_PER_TXD;
1651 size -= I40E_MAX_DATA_PER_TXD;
1652
1653 tx_desc->buffer_addr = cpu_to_le64(dma);
1654 }
1655
1656 if (likely(!data_len))
1657 break;
1658
1659 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1660 size, td_tag);
1661
1662 tx_desc++;
1663 i++;
1664 if (i == tx_ring->count) {
1665 tx_desc = I40E_TX_DESC(tx_ring, 0);
1666 i = 0;
1667 }
1668
1669 size = skb_frag_size(frag);
1670 data_len -= size;
1671
1672 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1673 DMA_TO_DEVICE);
1674
1675 tx_bi = &tx_ring->tx_bi[i];
1676 }
1677
1678 /* Place RS bit on last descriptor of any packet that spans across the
1679 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1680 */
1681 #define WB_STRIDE 0x3
1682 if (((i & WB_STRIDE) != WB_STRIDE) &&
1683 (first <= &tx_ring->tx_bi[i]) &&
1684 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1685 tx_desc->cmd_type_offset_bsz =
1686 build_ctob(td_cmd, td_offset, size, td_tag) |
1687 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1688 I40E_TXD_QW1_CMD_SHIFT);
1689 } else {
1690 tx_desc->cmd_type_offset_bsz =
1691 build_ctob(td_cmd, td_offset, size, td_tag) |
1692 cpu_to_le64((u64)I40E_TXD_CMD <<
1693 I40E_TXD_QW1_CMD_SHIFT);
1694 }
1695
1696 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1697 tx_ring->queue_index),
1698 first->bytecount);
1699
1700 /* set the timestamp */
1701 first->time_stamp = jiffies;
1702
1703 /* Force memory writes to complete before letting h/w
1704 * know there are new descriptors to fetch. (Only
1705 * applicable for weak-ordered memory model archs,
1706 * such as IA-64).
1707 */
1708 wmb();
1709
1710 /* set next_to_watch value indicating a packet is present */
1711 first->next_to_watch = tx_desc;
1712
1713 i++;
1714 if (i == tx_ring->count)
1715 i = 0;
1716
1717 tx_ring->next_to_use = i;
1718
1719 /* notify HW of packet */
1720 writel(i, tx_ring->tail);
1721
1722 return;
1723
1724 dma_error:
1725 dev_info(tx_ring->dev, "TX DMA map failed\n");
1726
1727 /* clear dma mappings for failed tx_bi map */
1728 for (;;) {
1729 tx_bi = &tx_ring->tx_bi[i];
1730 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1731 if (tx_bi == first)
1732 break;
1733 if (i == 0)
1734 i = tx_ring->count;
1735 i--;
1736 }
1737
1738 tx_ring->next_to_use = i;
1739 }
1740
1741 /**
1742 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1743 * @tx_ring: the ring to be checked
1744 * @size: the size buffer we want to assure is available
1745 *
1746 * Returns -EBUSY if a stop is needed, else 0
1747 **/
1748 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1749 {
1750 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1751 /* Memory barrier before checking head and tail */
1752 smp_mb();
1753
1754 /* Check again in a case another CPU has just made room available. */
1755 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1756 return -EBUSY;
1757
1758 /* A reprieve! - use start_queue because it doesn't call schedule */
1759 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1760 ++tx_ring->tx_stats.restart_queue;
1761 return 0;
1762 }
1763
1764 /**
1765 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1766 * @tx_ring: the ring to be checked
1767 * @size: the size buffer we want to assure is available
1768 *
1769 * Returns 0 if stop is not needed
1770 **/
1771 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1772 {
1773 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1774 return 0;
1775 return __i40e_maybe_stop_tx(tx_ring, size);
1776 }
1777
1778 /**
1779 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1780 * @skb: send buffer
1781 * @tx_ring: ring to send buffer on
1782 *
1783 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1784 * there is not enough descriptors available in this ring since we need at least
1785 * one descriptor.
1786 **/
1787 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1788 struct i40e_ring *tx_ring)
1789 {
1790 unsigned int f;
1791 int count = 0;
1792
1793 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1794 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1795 * + 4 desc gap to avoid the cache line where head is,
1796 * + 1 desc for context descriptor,
1797 * otherwise try next time
1798 */
1799 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1800 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1801
1802 count += TXD_USE_COUNT(skb_headlen(skb));
1803 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1804 tx_ring->tx_stats.tx_busy++;
1805 return 0;
1806 }
1807 return count;
1808 }
1809
1810 /**
1811 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1812 * @skb: send buffer
1813 * @tx_ring: ring to send buffer on
1814 *
1815 * Returns NETDEV_TX_OK if sent, else an error code
1816 **/
1817 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1818 struct i40e_ring *tx_ring)
1819 {
1820 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1821 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1822 struct i40e_tx_buffer *first;
1823 u32 td_offset = 0;
1824 u32 tx_flags = 0;
1825 __be16 protocol;
1826 u32 td_cmd = 0;
1827 u8 hdr_len = 0;
1828 int tso;
1829 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1830 return NETDEV_TX_BUSY;
1831
1832 /* prepare the xmit flags */
1833 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1834 goto out_drop;
1835
1836 /* obtain protocol of skb */
1837 protocol = vlan_get_protocol(skb);
1838
1839 /* record the location of the first descriptor for this packet */
1840 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1841
1842 /* setup IPv4/IPv6 offloads */
1843 if (protocol == htons(ETH_P_IP))
1844 tx_flags |= I40E_TX_FLAGS_IPV4;
1845 else if (protocol == htons(ETH_P_IPV6))
1846 tx_flags |= I40E_TX_FLAGS_IPV6;
1847
1848 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1849 &cd_type_cmd_tso_mss, &cd_tunneling);
1850
1851 if (tso < 0)
1852 goto out_drop;
1853 else if (tso)
1854 tx_flags |= I40E_TX_FLAGS_TSO;
1855
1856 skb_tx_timestamp(skb);
1857
1858 /* always enable CRC insertion offload */
1859 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1860
1861 /* Always offload the checksum, since it's in the data descriptor */
1862 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1863 tx_flags |= I40E_TX_FLAGS_CSUM;
1864
1865 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1866 tx_ring, &cd_tunneling);
1867 }
1868
1869 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1870 cd_tunneling, cd_l2tag2);
1871
1872 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1873 td_cmd, td_offset);
1874
1875 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1876
1877 return NETDEV_TX_OK;
1878
1879 out_drop:
1880 dev_kfree_skb_any(skb);
1881 return NETDEV_TX_OK;
1882 }
1883
1884 /**
1885 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1886 * @skb: send buffer
1887 * @netdev: network interface device structure
1888 *
1889 * Returns NETDEV_TX_OK if sent, else an error code
1890 **/
1891 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1892 {
1893 struct i40evf_adapter *adapter = netdev_priv(netdev);
1894 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1895
1896 /* hardware can't handle really short frames, hardware padding works
1897 * beyond this point
1898 */
1899 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1900 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1901 return NETDEV_TX_OK;
1902 skb->len = I40E_MIN_TX_LEN;
1903 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1904 }
1905
1906 return i40e_xmit_frame_ring(skb, tx_ring);
1907 }
Linux kernel - Deliverables
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