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sg_start_req(): use import_iovec()
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_type.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_TYPE_H_
28 #define _I40E_TYPE_H_
29
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
34 #include "i40e_hmc.h"
35 #include "i40e_lan_hmc.h"
36
37 /* Device IDs */
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_VF 0x154C
48 #define I40E_DEV_ID_VF_HV 0x1571
49
50 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
51 (d) == I40E_DEV_ID_QSFP_B || \
52 (d) == I40E_DEV_ID_QSFP_C)
53
54 /* I40E_MASK is a macro used on 32 bit registers */
55 #define I40E_MASK(mask, shift) (mask << shift)
56
57 #define I40E_MAX_VSI_QP 16
58 #define I40E_MAX_VF_VSI 3
59 #define I40E_MAX_CHAINED_RX_BUFFERS 5
60 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
61
62 /* Max default timeout in ms, */
63 #define I40E_MAX_NVM_TIMEOUT 18000
64
65 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
66 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
67
68 /* forward declaration */
69 struct i40e_hw;
70 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
71
72 /* Data type manipulation macros. */
73
74 #define I40E_DESC_UNUSED(R) \
75 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
76 (R)->next_to_clean - (R)->next_to_use - 1)
77
78 /* bitfields for Tx queue mapping in QTX_CTL */
79 #define I40E_QTX_CTL_VF_QUEUE 0x0
80 #define I40E_QTX_CTL_VM_QUEUE 0x1
81 #define I40E_QTX_CTL_PF_QUEUE 0x2
82
83 /* debug masks - set these bits in hw->debug_mask to control output */
84 enum i40e_debug_mask {
85 I40E_DEBUG_INIT = 0x00000001,
86 I40E_DEBUG_RELEASE = 0x00000002,
87
88 I40E_DEBUG_LINK = 0x00000010,
89 I40E_DEBUG_PHY = 0x00000020,
90 I40E_DEBUG_HMC = 0x00000040,
91 I40E_DEBUG_NVM = 0x00000080,
92 I40E_DEBUG_LAN = 0x00000100,
93 I40E_DEBUG_FLOW = 0x00000200,
94 I40E_DEBUG_DCB = 0x00000400,
95 I40E_DEBUG_DIAG = 0x00000800,
96 I40E_DEBUG_FD = 0x00001000,
97
98 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
99 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
100 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
101 I40E_DEBUG_AQ_COMMAND = 0x06000000,
102 I40E_DEBUG_AQ = 0x0F000000,
103
104 I40E_DEBUG_USER = 0xF0000000,
105
106 I40E_DEBUG_ALL = 0xFFFFFFFF
107 };
108
109 /* These are structs for managing the hardware information and the operations.
110 * The structures of function pointers are filled out at init time when we
111 * know for sure exactly which hardware we're working with. This gives us the
112 * flexibility of using the same main driver code but adapting to slightly
113 * different hardware needs as new parts are developed. For this architecture,
114 * the Firmware and AdminQ are intended to insulate the driver from most of the
115 * future changes, but these structures will also do part of the job.
116 */
117 enum i40e_mac_type {
118 I40E_MAC_UNKNOWN = 0,
119 I40E_MAC_X710,
120 I40E_MAC_XL710,
121 I40E_MAC_VF,
122 I40E_MAC_GENERIC,
123 };
124
125 enum i40e_media_type {
126 I40E_MEDIA_TYPE_UNKNOWN = 0,
127 I40E_MEDIA_TYPE_FIBER,
128 I40E_MEDIA_TYPE_BASET,
129 I40E_MEDIA_TYPE_BACKPLANE,
130 I40E_MEDIA_TYPE_CX4,
131 I40E_MEDIA_TYPE_DA,
132 I40E_MEDIA_TYPE_VIRTUAL
133 };
134
135 enum i40e_fc_mode {
136 I40E_FC_NONE = 0,
137 I40E_FC_RX_PAUSE,
138 I40E_FC_TX_PAUSE,
139 I40E_FC_FULL,
140 I40E_FC_PFC,
141 I40E_FC_DEFAULT
142 };
143
144 enum i40e_set_fc_aq_failures {
145 I40E_SET_FC_AQ_FAIL_NONE = 0,
146 I40E_SET_FC_AQ_FAIL_GET = 1,
147 I40E_SET_FC_AQ_FAIL_SET = 2,
148 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
149 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
150 };
151
152 enum i40e_vsi_type {
153 I40E_VSI_MAIN = 0,
154 I40E_VSI_VMDQ1,
155 I40E_VSI_VMDQ2,
156 I40E_VSI_CTRL,
157 I40E_VSI_FCOE,
158 I40E_VSI_MIRROR,
159 I40E_VSI_SRIOV,
160 I40E_VSI_FDIR,
161 I40E_VSI_TYPE_UNKNOWN
162 };
163
164 enum i40e_queue_type {
165 I40E_QUEUE_TYPE_RX = 0,
166 I40E_QUEUE_TYPE_TX,
167 I40E_QUEUE_TYPE_PE_CEQ,
168 I40E_QUEUE_TYPE_UNKNOWN
169 };
170
171 struct i40e_link_status {
172 enum i40e_aq_phy_type phy_type;
173 enum i40e_aq_link_speed link_speed;
174 u8 link_info;
175 u8 an_info;
176 u8 ext_info;
177 u8 loopback;
178 bool an_enabled;
179 /* is Link Status Event notification to SW enabled */
180 bool lse_enable;
181 u16 max_frame_size;
182 bool crc_enable;
183 u8 pacing;
184 };
185
186 struct i40e_phy_info {
187 struct i40e_link_status link_info;
188 struct i40e_link_status link_info_old;
189 u32 autoneg_advertised;
190 u32 phy_id;
191 u32 module_type;
192 bool get_link_info;
193 enum i40e_media_type media_type;
194 };
195
196 #define I40E_HW_CAP_MAX_GPIO 30
197 /* Capabilities of a PF or a VF or the whole device */
198 struct i40e_hw_capabilities {
199 u32 switch_mode;
200 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
201 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
202 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
203
204 u32 management_mode;
205 u32 npar_enable;
206 u32 os2bmc;
207 u32 valid_functions;
208 bool sr_iov_1_1;
209 bool vmdq;
210 bool evb_802_1_qbg; /* Edge Virtual Bridging */
211 bool evb_802_1_qbh; /* Bridge Port Extension */
212 bool dcb;
213 bool fcoe;
214 bool iscsi; /* Indicates iSCSI enabled */
215 bool mfp_mode_1;
216 bool mgmt_cem;
217 bool ieee_1588;
218 bool iwarp;
219 bool fd;
220 u32 fd_filters_guaranteed;
221 u32 fd_filters_best_effort;
222 bool rss;
223 u32 rss_table_size;
224 u32 rss_table_entry_width;
225 bool led[I40E_HW_CAP_MAX_GPIO];
226 bool sdp[I40E_HW_CAP_MAX_GPIO];
227 u32 nvm_image_type;
228 u32 num_flow_director_filters;
229 u32 num_vfs;
230 u32 vf_base_id;
231 u32 num_vsis;
232 u32 num_rx_qp;
233 u32 num_tx_qp;
234 u32 base_queue;
235 u32 num_msix_vectors;
236 u32 num_msix_vectors_vf;
237 u32 led_pin_num;
238 u32 sdp_pin_num;
239 u32 mdio_port_num;
240 u32 mdio_port_mode;
241 u8 rx_buf_chain_len;
242 u32 enabled_tcmap;
243 u32 maxtc;
244 };
245
246 struct i40e_mac_info {
247 enum i40e_mac_type type;
248 u8 addr[ETH_ALEN];
249 u8 perm_addr[ETH_ALEN];
250 u8 san_addr[ETH_ALEN];
251 u16 max_fcoeq;
252 };
253
254 enum i40e_aq_resources_ids {
255 I40E_NVM_RESOURCE_ID = 1
256 };
257
258 enum i40e_aq_resource_access_type {
259 I40E_RESOURCE_READ = 1,
260 I40E_RESOURCE_WRITE
261 };
262
263 struct i40e_nvm_info {
264 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
265 u32 timeout; /* [ms] */
266 u16 sr_size; /* Shadow RAM size in words */
267 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
268 u16 version; /* NVM package version */
269 u32 eetrack; /* NVM data version */
270 };
271
272 /* definitions used in NVM update support */
273
274 enum i40e_nvmupd_cmd {
275 I40E_NVMUPD_INVALID,
276 I40E_NVMUPD_READ_CON,
277 I40E_NVMUPD_READ_SNT,
278 I40E_NVMUPD_READ_LCB,
279 I40E_NVMUPD_READ_SA,
280 I40E_NVMUPD_WRITE_ERA,
281 I40E_NVMUPD_WRITE_CON,
282 I40E_NVMUPD_WRITE_SNT,
283 I40E_NVMUPD_WRITE_LCB,
284 I40E_NVMUPD_WRITE_SA,
285 I40E_NVMUPD_CSUM_CON,
286 I40E_NVMUPD_CSUM_SA,
287 I40E_NVMUPD_CSUM_LCB,
288 };
289
290 enum i40e_nvmupd_state {
291 I40E_NVMUPD_STATE_INIT,
292 I40E_NVMUPD_STATE_READING,
293 I40E_NVMUPD_STATE_WRITING
294 };
295
296 /* nvm_access definition and its masks/shifts need to be accessible to
297 * application, core driver, and shared code. Where is the right file?
298 */
299 #define I40E_NVM_READ 0xB
300 #define I40E_NVM_WRITE 0xC
301
302 #define I40E_NVM_MOD_PNT_MASK 0xFF
303
304 #define I40E_NVM_TRANS_SHIFT 8
305 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
306 #define I40E_NVM_CON 0x0
307 #define I40E_NVM_SNT 0x1
308 #define I40E_NVM_LCB 0x2
309 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
310 #define I40E_NVM_ERA 0x4
311 #define I40E_NVM_CSUM 0x8
312
313 #define I40E_NVM_ADAPT_SHIFT 16
314 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
315
316 #define I40E_NVMUPD_MAX_DATA 4096
317 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
318
319 struct i40e_nvm_access {
320 u32 command;
321 u32 config;
322 u32 offset; /* in bytes */
323 u32 data_size; /* in bytes */
324 u8 data[1];
325 };
326
327 /* PCI bus types */
328 enum i40e_bus_type {
329 i40e_bus_type_unknown = 0,
330 i40e_bus_type_pci,
331 i40e_bus_type_pcix,
332 i40e_bus_type_pci_express,
333 i40e_bus_type_reserved
334 };
335
336 /* PCI bus speeds */
337 enum i40e_bus_speed {
338 i40e_bus_speed_unknown = 0,
339 i40e_bus_speed_33 = 33,
340 i40e_bus_speed_66 = 66,
341 i40e_bus_speed_100 = 100,
342 i40e_bus_speed_120 = 120,
343 i40e_bus_speed_133 = 133,
344 i40e_bus_speed_2500 = 2500,
345 i40e_bus_speed_5000 = 5000,
346 i40e_bus_speed_8000 = 8000,
347 i40e_bus_speed_reserved
348 };
349
350 /* PCI bus widths */
351 enum i40e_bus_width {
352 i40e_bus_width_unknown = 0,
353 i40e_bus_width_pcie_x1 = 1,
354 i40e_bus_width_pcie_x2 = 2,
355 i40e_bus_width_pcie_x4 = 4,
356 i40e_bus_width_pcie_x8 = 8,
357 i40e_bus_width_32 = 32,
358 i40e_bus_width_64 = 64,
359 i40e_bus_width_reserved
360 };
361
362 /* Bus parameters */
363 struct i40e_bus_info {
364 enum i40e_bus_speed speed;
365 enum i40e_bus_width width;
366 enum i40e_bus_type type;
367
368 u16 func;
369 u16 device;
370 u16 lan_id;
371 };
372
373 /* Flow control (FC) parameters */
374 struct i40e_fc_info {
375 enum i40e_fc_mode current_mode; /* FC mode in effect */
376 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
377 };
378
379 #define I40E_MAX_TRAFFIC_CLASS 8
380 #define I40E_MAX_USER_PRIORITY 8
381 #define I40E_DCBX_MAX_APPS 32
382 #define I40E_LLDPDU_SIZE 1500
383
384 /* IEEE 802.1Qaz ETS Configuration data */
385 struct i40e_ieee_ets_config {
386 u8 willing;
387 u8 cbs;
388 u8 maxtcs;
389 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
390 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
391 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
392 };
393
394 /* IEEE 802.1Qaz ETS Recommendation data */
395 struct i40e_ieee_ets_recommend {
396 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
397 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
398 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
399 };
400
401 /* IEEE 802.1Qaz PFC Configuration data */
402 struct i40e_ieee_pfc_config {
403 u8 willing;
404 u8 mbc;
405 u8 pfccap;
406 u8 pfcenable;
407 };
408
409 /* IEEE 802.1Qaz Application Priority data */
410 struct i40e_ieee_app_priority_table {
411 u8 priority;
412 u8 selector;
413 u16 protocolid;
414 };
415
416 struct i40e_dcbx_config {
417 u32 numapps;
418 struct i40e_ieee_ets_config etscfg;
419 struct i40e_ieee_ets_recommend etsrec;
420 struct i40e_ieee_pfc_config pfc;
421 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
422 };
423
424 /* Port hardware description */
425 struct i40e_hw {
426 u8 __iomem *hw_addr;
427 void *back;
428
429 /* subsystem structs */
430 struct i40e_phy_info phy;
431 struct i40e_mac_info mac;
432 struct i40e_bus_info bus;
433 struct i40e_nvm_info nvm;
434 struct i40e_fc_info fc;
435
436 /* pci info */
437 u16 device_id;
438 u16 vendor_id;
439 u16 subsystem_device_id;
440 u16 subsystem_vendor_id;
441 u8 revision_id;
442 u8 port;
443 bool adapter_stopped;
444
445 /* capabilities for entire device and PCI func */
446 struct i40e_hw_capabilities dev_caps;
447 struct i40e_hw_capabilities func_caps;
448
449 /* Flow Director shared filter space */
450 u16 fdir_shared_filter_count;
451
452 /* device profile info */
453 u8 pf_id;
454 u16 main_vsi_seid;
455
456 /* for multi-function MACs */
457 u16 partition_id;
458 u16 num_partitions;
459 u16 num_ports;
460
461 /* Closest numa node to the device */
462 u16 numa_node;
463
464 /* Admin Queue info */
465 struct i40e_adminq_info aq;
466
467 /* state of nvm update process */
468 enum i40e_nvmupd_state nvmupd_state;
469
470 /* HMC info */
471 struct i40e_hmc_info hmc; /* HMC info struct */
472
473 /* LLDP/DCBX Status */
474 u16 dcbx_status;
475
476 /* DCBX info */
477 struct i40e_dcbx_config local_dcbx_config;
478 struct i40e_dcbx_config remote_dcbx_config;
479
480 /* debug mask */
481 u32 debug_mask;
482 };
483
484 static inline bool i40e_is_vf(struct i40e_hw *hw)
485 {
486 return hw->mac.type == I40E_MAC_VF;
487 }
488
489 struct i40e_driver_version {
490 u8 major_version;
491 u8 minor_version;
492 u8 build_version;
493 u8 subbuild_version;
494 u8 driver_string[32];
495 };
496
497 /* RX Descriptors */
498 union i40e_16byte_rx_desc {
499 struct {
500 __le64 pkt_addr; /* Packet buffer address */
501 __le64 hdr_addr; /* Header buffer address */
502 } read;
503 struct {
504 struct {
505 struct {
506 union {
507 __le16 mirroring_status;
508 __le16 fcoe_ctx_id;
509 } mirr_fcoe;
510 __le16 l2tag1;
511 } lo_dword;
512 union {
513 __le32 rss; /* RSS Hash */
514 __le32 fd_id; /* Flow director filter id */
515 __le32 fcoe_param; /* FCoE DDP Context id */
516 } hi_dword;
517 } qword0;
518 struct {
519 /* ext status/error/pktype/length */
520 __le64 status_error_len;
521 } qword1;
522 } wb; /* writeback */
523 };
524
525 union i40e_32byte_rx_desc {
526 struct {
527 __le64 pkt_addr; /* Packet buffer address */
528 __le64 hdr_addr; /* Header buffer address */
529 /* bit 0 of hdr_buffer_addr is DD bit */
530 __le64 rsvd1;
531 __le64 rsvd2;
532 } read;
533 struct {
534 struct {
535 struct {
536 union {
537 __le16 mirroring_status;
538 __le16 fcoe_ctx_id;
539 } mirr_fcoe;
540 __le16 l2tag1;
541 } lo_dword;
542 union {
543 __le32 rss; /* RSS Hash */
544 __le32 fcoe_param; /* FCoE DDP Context id */
545 /* Flow director filter id in case of
546 * Programming status desc WB
547 */
548 __le32 fd_id;
549 } hi_dword;
550 } qword0;
551 struct {
552 /* status/error/pktype/length */
553 __le64 status_error_len;
554 } qword1;
555 struct {
556 __le16 ext_status; /* extended status */
557 __le16 rsvd;
558 __le16 l2tag2_1;
559 __le16 l2tag2_2;
560 } qword2;
561 struct {
562 union {
563 __le32 flex_bytes_lo;
564 __le32 pe_status;
565 } lo_dword;
566 union {
567 __le32 flex_bytes_hi;
568 __le32 fd_id;
569 } hi_dword;
570 } qword3;
571 } wb; /* writeback */
572 };
573
574 enum i40e_rx_desc_status_bits {
575 /* Note: These are predefined bit offsets */
576 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
577 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
578 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
579 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
580 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
581 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
582 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
583 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
584 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
585 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
586 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
587 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
588 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
589 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
590 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
591 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
592 };
593
594 #define I40E_RXD_QW1_STATUS_SHIFT 0
595 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
596 << I40E_RXD_QW1_STATUS_SHIFT)
597
598 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
599 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
600 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
601
602 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
603 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
604 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
605
606 enum i40e_rx_desc_fltstat_values {
607 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
608 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
609 I40E_RX_DESC_FLTSTAT_RSV = 2,
610 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
611 };
612
613 #define I40E_RXD_QW1_ERROR_SHIFT 19
614 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
615
616 enum i40e_rx_desc_error_bits {
617 /* Note: These are predefined bit offsets */
618 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
619 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
620 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
621 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
622 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
623 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
624 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
625 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
626 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
627 };
628
629 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
630 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
631 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
632 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
633 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
634 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
635 };
636
637 #define I40E_RXD_QW1_PTYPE_SHIFT 30
638 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
639
640 /* Packet type non-ip values */
641 enum i40e_rx_l2_ptype {
642 I40E_RX_PTYPE_L2_RESERVED = 0,
643 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
644 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
645 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
646 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
647 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
648 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
649 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
650 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
651 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
652 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
653 I40E_RX_PTYPE_L2_ARP = 11,
654 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
655 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
656 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
657 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
658 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
659 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
660 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
661 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
662 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
663 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
664 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
665 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
666 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
667 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
668 };
669
670 struct i40e_rx_ptype_decoded {
671 u32 ptype:8;
672 u32 known:1;
673 u32 outer_ip:1;
674 u32 outer_ip_ver:1;
675 u32 outer_frag:1;
676 u32 tunnel_type:3;
677 u32 tunnel_end_prot:2;
678 u32 tunnel_end_frag:1;
679 u32 inner_prot:4;
680 u32 payload_layer:3;
681 };
682
683 enum i40e_rx_ptype_outer_ip {
684 I40E_RX_PTYPE_OUTER_L2 = 0,
685 I40E_RX_PTYPE_OUTER_IP = 1
686 };
687
688 enum i40e_rx_ptype_outer_ip_ver {
689 I40E_RX_PTYPE_OUTER_NONE = 0,
690 I40E_RX_PTYPE_OUTER_IPV4 = 0,
691 I40E_RX_PTYPE_OUTER_IPV6 = 1
692 };
693
694 enum i40e_rx_ptype_outer_fragmented {
695 I40E_RX_PTYPE_NOT_FRAG = 0,
696 I40E_RX_PTYPE_FRAG = 1
697 };
698
699 enum i40e_rx_ptype_tunnel_type {
700 I40E_RX_PTYPE_TUNNEL_NONE = 0,
701 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
702 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
703 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
704 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
705 };
706
707 enum i40e_rx_ptype_tunnel_end_prot {
708 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
709 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
710 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
711 };
712
713 enum i40e_rx_ptype_inner_prot {
714 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
715 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
716 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
717 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
718 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
719 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
720 };
721
722 enum i40e_rx_ptype_payload_layer {
723 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
724 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
725 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
726 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
727 };
728
729 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
730 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
731 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
732
733 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
734 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
735 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
736
737 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
738 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
739 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
740
741 enum i40e_rx_desc_ext_status_bits {
742 /* Note: These are predefined bit offsets */
743 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
744 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
745 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
746 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
747 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
748 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
749 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
750 };
751
752 enum i40e_rx_desc_pe_status_bits {
753 /* Note: These are predefined bit offsets */
754 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
755 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
756 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
757 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
758 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
759 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
760 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
761 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
762 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
763 };
764
765 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
766 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
767
768 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
769 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
770 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
771
772 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
773 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
774 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
775
776 enum i40e_rx_prog_status_desc_status_bits {
777 /* Note: These are predefined bit offsets */
778 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
779 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
780 };
781
782 enum i40e_rx_prog_status_desc_prog_id_masks {
783 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
784 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
785 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
786 };
787
788 enum i40e_rx_prog_status_desc_error_bits {
789 /* Note: These are predefined bit offsets */
790 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
791 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
792 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
793 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
794 };
795
796 /* TX Descriptor */
797 struct i40e_tx_desc {
798 __le64 buffer_addr; /* Address of descriptor's data buf */
799 __le64 cmd_type_offset_bsz;
800 };
801
802 #define I40E_TXD_QW1_DTYPE_SHIFT 0
803 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
804
805 enum i40e_tx_desc_dtype_value {
806 I40E_TX_DESC_DTYPE_DATA = 0x0,
807 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
808 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
809 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
810 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
811 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
812 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
813 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
814 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
815 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
816 };
817
818 #define I40E_TXD_QW1_CMD_SHIFT 4
819 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
820
821 enum i40e_tx_desc_cmd_bits {
822 I40E_TX_DESC_CMD_EOP = 0x0001,
823 I40E_TX_DESC_CMD_RS = 0x0002,
824 I40E_TX_DESC_CMD_ICRC = 0x0004,
825 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
826 I40E_TX_DESC_CMD_DUMMY = 0x0010,
827 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
828 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
829 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
830 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
831 I40E_TX_DESC_CMD_FCOET = 0x0080,
832 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
833 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
834 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
835 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
836 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
837 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
838 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
839 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
840 };
841
842 #define I40E_TXD_QW1_OFFSET_SHIFT 16
843 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
844 I40E_TXD_QW1_OFFSET_SHIFT)
845
846 enum i40e_tx_desc_length_fields {
847 /* Note: These are predefined bit offsets */
848 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
849 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
850 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
851 };
852
853 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
854 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
855 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
856
857 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
858 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
859
860 /* Context descriptors */
861 struct i40e_tx_context_desc {
862 __le32 tunneling_params;
863 __le16 l2tag2;
864 __le16 rsvd;
865 __le64 type_cmd_tso_mss;
866 };
867
868 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
869 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
870
871 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
872 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
873
874 enum i40e_tx_ctx_desc_cmd_bits {
875 I40E_TX_CTX_DESC_TSO = 0x01,
876 I40E_TX_CTX_DESC_TSYN = 0x02,
877 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
878 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
879 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
880 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
881 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
882 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
883 I40E_TX_CTX_DESC_SWPE = 0x40
884 };
885
886 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
887 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
888 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
889
890 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
891 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
892 I40E_TXD_CTX_QW1_MSS_SHIFT)
893
894 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
895 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
896
897 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
898 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
899 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
900
901 enum i40e_tx_ctx_desc_eipt_offload {
902 I40E_TX_CTX_EXT_IP_NONE = 0x0,
903 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
904 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
905 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
906 };
907
908 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
909 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
910 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
911
912 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
913 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
914
915 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
916 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
917
918 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
919 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
920 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
921
922 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
923
924 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
925 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
926 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
927
928 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
929 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
930 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
931
932 struct i40e_filter_program_desc {
933 __le32 qindex_flex_ptype_vsi;
934 __le32 rsvd;
935 __le32 dtype_cmd_cntindex;
936 __le32 fd_id;
937 };
938 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
939 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
940 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
941 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
942 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
943 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
944 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
945 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
946 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
947
948 /* Packet Classifier Types for filters */
949 enum i40e_filter_pctype {
950 /* Note: Values 0-30 are reserved for future use */
951 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
952 /* Note: Value 32 is reserved for future use */
953 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
954 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
955 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
956 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
957 /* Note: Values 37-40 are reserved for future use */
958 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
959 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
960 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
961 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
962 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
963 /* Note: Value 47 is reserved for future use */
964 I40E_FILTER_PCTYPE_FCOE_OX = 48,
965 I40E_FILTER_PCTYPE_FCOE_RX = 49,
966 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
967 /* Note: Values 51-62 are reserved for future use */
968 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
969 };
970
971 enum i40e_filter_program_desc_dest {
972 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
973 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
974 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
975 };
976
977 enum i40e_filter_program_desc_fd_status {
978 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
979 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
980 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
981 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
982 };
983
984 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
985 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
986 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
987
988 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
989 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
990 I40E_TXD_FLTR_QW1_CMD_SHIFT)
991
992 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
993 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
994
995 enum i40e_filter_program_desc_pcmd {
996 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
997 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
998 };
999
1000 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1001 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1002
1003 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1004 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
1005 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1006
1007 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1008 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1009 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1010 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1011
1012 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1013 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1014 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1015
1016 enum i40e_filter_type {
1017 I40E_FLOW_DIRECTOR_FLTR = 0,
1018 I40E_PE_QUAD_HASH_FLTR = 1,
1019 I40E_ETHERTYPE_FLTR,
1020 I40E_FCOE_CTX_FLTR,
1021 I40E_MAC_VLAN_FLTR,
1022 I40E_HASH_FLTR
1023 };
1024
1025 struct i40e_vsi_context {
1026 u16 seid;
1027 u16 uplink_seid;
1028 u16 vsi_number;
1029 u16 vsis_allocated;
1030 u16 vsis_unallocated;
1031 u16 flags;
1032 u8 pf_num;
1033 u8 vf_num;
1034 u8 connection_type;
1035 struct i40e_aqc_vsi_properties_data info;
1036 };
1037
1038 struct i40e_veb_context {
1039 u16 seid;
1040 u16 uplink_seid;
1041 u16 veb_number;
1042 u16 vebs_allocated;
1043 u16 vebs_unallocated;
1044 u16 flags;
1045 struct i40e_aqc_get_veb_parameters_completion info;
1046 };
1047
1048 /* Statistics collected by each port, VSI, VEB, and S-channel */
1049 struct i40e_eth_stats {
1050 u64 rx_bytes; /* gorc */
1051 u64 rx_unicast; /* uprc */
1052 u64 rx_multicast; /* mprc */
1053 u64 rx_broadcast; /* bprc */
1054 u64 rx_discards; /* rdpc */
1055 u64 rx_unknown_protocol; /* rupp */
1056 u64 tx_bytes; /* gotc */
1057 u64 tx_unicast; /* uptc */
1058 u64 tx_multicast; /* mptc */
1059 u64 tx_broadcast; /* bptc */
1060 u64 tx_discards; /* tdpc */
1061 u64 tx_errors; /* tepc */
1062 };
1063
1064 /* Statistics collected by the MAC */
1065 struct i40e_hw_port_stats {
1066 /* eth stats collected by the port */
1067 struct i40e_eth_stats eth;
1068
1069 /* additional port specific stats */
1070 u64 tx_dropped_link_down; /* tdold */
1071 u64 crc_errors; /* crcerrs */
1072 u64 illegal_bytes; /* illerrc */
1073 u64 error_bytes; /* errbc */
1074 u64 mac_local_faults; /* mlfc */
1075 u64 mac_remote_faults; /* mrfc */
1076 u64 rx_length_errors; /* rlec */
1077 u64 link_xon_rx; /* lxonrxc */
1078 u64 link_xoff_rx; /* lxoffrxc */
1079 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1080 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1081 u64 link_xon_tx; /* lxontxc */
1082 u64 link_xoff_tx; /* lxofftxc */
1083 u64 priority_xon_tx[8]; /* pxontxc[8] */
1084 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1085 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1086 u64 rx_size_64; /* prc64 */
1087 u64 rx_size_127; /* prc127 */
1088 u64 rx_size_255; /* prc255 */
1089 u64 rx_size_511; /* prc511 */
1090 u64 rx_size_1023; /* prc1023 */
1091 u64 rx_size_1522; /* prc1522 */
1092 u64 rx_size_big; /* prc9522 */
1093 u64 rx_undersize; /* ruc */
1094 u64 rx_fragments; /* rfc */
1095 u64 rx_oversize; /* roc */
1096 u64 rx_jabber; /* rjc */
1097 u64 tx_size_64; /* ptc64 */
1098 u64 tx_size_127; /* ptc127 */
1099 u64 tx_size_255; /* ptc255 */
1100 u64 tx_size_511; /* ptc511 */
1101 u64 tx_size_1023; /* ptc1023 */
1102 u64 tx_size_1522; /* ptc1522 */
1103 u64 tx_size_big; /* ptc9522 */
1104 u64 mac_short_packet_dropped; /* mspdc */
1105 u64 checksum_error; /* xec */
1106 /* flow director stats */
1107 u64 fd_atr_match;
1108 u64 fd_sb_match;
1109 /* EEE LPI */
1110 u32 tx_lpi_status;
1111 u32 rx_lpi_status;
1112 u64 tx_lpi_count; /* etlpic */
1113 u64 rx_lpi_count; /* erlpic */
1114 };
1115
1116 /* Checksum and Shadow RAM pointers */
1117 #define I40E_SR_NVM_CONTROL_WORD 0x00
1118 #define I40E_SR_EMP_MODULE_PTR 0x0F
1119 #define I40E_SR_NVM_IMAGE_VERSION 0x18
1120 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1121 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1122 #define I40E_SR_NVM_EETRACK_LO 0x2D
1123 #define I40E_SR_NVM_EETRACK_HI 0x2E
1124 #define I40E_SR_VPD_PTR 0x2F
1125 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1126 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1127
1128 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1129 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1130 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1131 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1132 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1133
1134 /* Shadow RAM related */
1135 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1136 #define I40E_SR_WORDS_IN_1KB 512
1137 /* Checksum should be calculated such that after adding all the words,
1138 * including the checksum word itself, the sum should be 0xBABA.
1139 */
1140 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1141
1142 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1143
1144 enum i40e_switch_element_types {
1145 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1146 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1147 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1148 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1149 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1150 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1151 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1152 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1153 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1154 };
1155
1156 /* Supported EtherType filters */
1157 enum i40e_ether_type_index {
1158 I40E_ETHER_TYPE_1588 = 0,
1159 I40E_ETHER_TYPE_FIP = 1,
1160 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1161 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1162 I40E_ETHER_TYPE_LLDP = 4,
1163 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1164 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1165 I40E_ETHER_TYPE_QCN_CNM = 7,
1166 I40E_ETHER_TYPE_8021X = 8,
1167 I40E_ETHER_TYPE_ARP = 9,
1168 I40E_ETHER_TYPE_RSV1 = 10,
1169 I40E_ETHER_TYPE_RSV2 = 11,
1170 };
1171
1172 /* Filter context base size is 1K */
1173 #define I40E_HASH_FILTER_BASE_SIZE 1024
1174 /* Supported Hash filter values */
1175 enum i40e_hash_filter_size {
1176 I40E_HASH_FILTER_SIZE_1K = 0,
1177 I40E_HASH_FILTER_SIZE_2K = 1,
1178 I40E_HASH_FILTER_SIZE_4K = 2,
1179 I40E_HASH_FILTER_SIZE_8K = 3,
1180 I40E_HASH_FILTER_SIZE_16K = 4,
1181 I40E_HASH_FILTER_SIZE_32K = 5,
1182 I40E_HASH_FILTER_SIZE_64K = 6,
1183 I40E_HASH_FILTER_SIZE_128K = 7,
1184 I40E_HASH_FILTER_SIZE_256K = 8,
1185 I40E_HASH_FILTER_SIZE_512K = 9,
1186 I40E_HASH_FILTER_SIZE_1M = 10,
1187 };
1188
1189 /* DMA context base size is 0.5K */
1190 #define I40E_DMA_CNTX_BASE_SIZE 512
1191 /* Supported DMA context values */
1192 enum i40e_dma_cntx_size {
1193 I40E_DMA_CNTX_SIZE_512 = 0,
1194 I40E_DMA_CNTX_SIZE_1K = 1,
1195 I40E_DMA_CNTX_SIZE_2K = 2,
1196 I40E_DMA_CNTX_SIZE_4K = 3,
1197 I40E_DMA_CNTX_SIZE_8K = 4,
1198 I40E_DMA_CNTX_SIZE_16K = 5,
1199 I40E_DMA_CNTX_SIZE_32K = 6,
1200 I40E_DMA_CNTX_SIZE_64K = 7,
1201 I40E_DMA_CNTX_SIZE_128K = 8,
1202 I40E_DMA_CNTX_SIZE_256K = 9,
1203 };
1204
1205 /* Supported Hash look up table (LUT) sizes */
1206 enum i40e_hash_lut_size {
1207 I40E_HASH_LUT_SIZE_128 = 0,
1208 I40E_HASH_LUT_SIZE_512 = 1,
1209 };
1210
1211 /* Structure to hold a per PF filter control settings */
1212 struct i40e_filter_control_settings {
1213 /* number of PE Quad Hash filter buckets */
1214 enum i40e_hash_filter_size pe_filt_num;
1215 /* number of PE Quad Hash contexts */
1216 enum i40e_dma_cntx_size pe_cntx_num;
1217 /* number of FCoE filter buckets */
1218 enum i40e_hash_filter_size fcoe_filt_num;
1219 /* number of FCoE DDP contexts */
1220 enum i40e_dma_cntx_size fcoe_cntx_num;
1221 /* size of the Hash LUT */
1222 enum i40e_hash_lut_size hash_lut_size;
1223 /* enable FDIR filters for PF and its VFs */
1224 bool enable_fdir;
1225 /* enable Ethertype filters for PF and its VFs */
1226 bool enable_ethtype;
1227 /* enable MAC/VLAN filters for PF and its VFs */
1228 bool enable_macvlan;
1229 };
1230
1231 /* Structure to hold device level control filter counts */
1232 struct i40e_control_filter_stats {
1233 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1234 u16 etype_used; /* Used perfect EtherType filters */
1235 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1236 u16 etype_free; /* Un-used perfect EtherType filters */
1237 };
1238
1239 enum i40e_reset_type {
1240 I40E_RESET_POR = 0,
1241 I40E_RESET_CORER = 1,
1242 I40E_RESET_GLOBR = 2,
1243 I40E_RESET_EMPR = 3,
1244 };
1245
1246 /* RSS Hash Table Size */
1247 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1248 #endif /* _I40E_TYPE_H_ */
Linux kernel - Deliverables
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