projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
igb: Cleanups to fix msleep warnings
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 /* e1000_82575
25 * e1000_82576
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/types.h>
31 #include <linux/if_ether.h>
32 #include <linux/i2c.h>
33
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
36 #include "e1000_i210.h"
37
38 static s32 igb_get_invariants_82575(struct e1000_hw *);
39 static s32 igb_acquire_phy_82575(struct e1000_hw *);
40 static void igb_release_phy_82575(struct e1000_hw *);
41 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42 static void igb_release_nvm_82575(struct e1000_hw *);
43 static s32 igb_check_for_link_82575(struct e1000_hw *);
44 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45 static s32 igb_init_hw_82575(struct e1000_hw *);
46 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
48 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
50 static s32 igb_reset_hw_82575(struct e1000_hw *);
51 static s32 igb_reset_hw_82580(struct e1000_hw *);
52 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
54 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
55 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
56 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
57 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
58 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
59 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
60 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
61 u16 *);
62 static s32 igb_get_phy_id_82575(struct e1000_hw *);
63 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
64 static bool igb_sgmii_active_82575(struct e1000_hw *);
65 static s32 igb_reset_init_script_82575(struct e1000_hw *);
66 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
67 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
68 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
69 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
70 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
71 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
72 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
73 static const u16 e1000_82580_rxpbs_table[] = {
74 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
75
76 /**
77 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
78 * @hw: pointer to the HW structure
79 *
80 * Called to determine if the I2C pins are being used for I2C or as an
81 * external MDIO interface since the two options are mutually exclusive.
82 **/
83 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
84 {
85 u32 reg = 0;
86 bool ext_mdio = false;
87
88 switch (hw->mac.type) {
89 case e1000_82575:
90 case e1000_82576:
91 reg = rd32(E1000_MDIC);
92 ext_mdio = !!(reg & E1000_MDIC_DEST);
93 break;
94 case e1000_82580:
95 case e1000_i350:
96 case e1000_i354:
97 case e1000_i210:
98 case e1000_i211:
99 reg = rd32(E1000_MDICNFG);
100 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
101 break;
102 default:
103 break;
104 }
105 return ext_mdio;
106 }
107
108 /**
109 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
110 * @hw: pointer to the HW structure
111 *
112 * Poll the M88E1112 interfaces to see which interface achieved link.
113 */
114 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
115 {
116 struct e1000_phy_info *phy = &hw->phy;
117 s32 ret_val;
118 u16 data;
119 u8 port = 0;
120
121 /* Check the copper medium. */
122 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
123 if (ret_val)
124 return ret_val;
125
126 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
127 if (ret_val)
128 return ret_val;
129
130 if (data & E1000_M88E1112_STATUS_LINK)
131 port = E1000_MEDIA_PORT_COPPER;
132
133 /* Check the other medium. */
134 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
135 if (ret_val)
136 return ret_val;
137
138 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
139 if (ret_val)
140 return ret_val;
141
142 /* reset page to 0 */
143 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
144 if (ret_val)
145 return ret_val;
146
147 if (data & E1000_M88E1112_STATUS_LINK)
148 port = E1000_MEDIA_PORT_OTHER;
149
150 /* Determine if a swap needs to happen. */
151 if (port && (hw->dev_spec._82575.media_port != port)) {
152 hw->dev_spec._82575.media_port = port;
153 hw->dev_spec._82575.media_changed = true;
154 } else {
155 ret_val = igb_check_for_link_82575(hw);
156 }
157
158 return E1000_SUCCESS;
159 }
160
161 /**
162 * igb_init_phy_params_82575 - Init PHY func ptrs.
163 * @hw: pointer to the HW structure
164 **/
165 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
166 {
167 struct e1000_phy_info *phy = &hw->phy;
168 s32 ret_val = 0;
169 u32 ctrl_ext;
170
171 if (hw->phy.media_type != e1000_media_type_copper) {
172 phy->type = e1000_phy_none;
173 goto out;
174 }
175
176 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
177 phy->reset_delay_us = 100;
178
179 ctrl_ext = rd32(E1000_CTRL_EXT);
180
181 if (igb_sgmii_active_82575(hw)) {
182 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
183 ctrl_ext |= E1000_CTRL_I2C_ENA;
184 } else {
185 phy->ops.reset = igb_phy_hw_reset;
186 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
187 }
188
189 wr32(E1000_CTRL_EXT, ctrl_ext);
190 igb_reset_mdicnfg_82580(hw);
191
192 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
193 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
194 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
195 } else {
196 switch (hw->mac.type) {
197 case e1000_82580:
198 case e1000_i350:
199 case e1000_i354:
200 phy->ops.read_reg = igb_read_phy_reg_82580;
201 phy->ops.write_reg = igb_write_phy_reg_82580;
202 break;
203 case e1000_i210:
204 case e1000_i211:
205 phy->ops.read_reg = igb_read_phy_reg_gs40g;
206 phy->ops.write_reg = igb_write_phy_reg_gs40g;
207 break;
208 default:
209 phy->ops.read_reg = igb_read_phy_reg_igp;
210 phy->ops.write_reg = igb_write_phy_reg_igp;
211 }
212 }
213
214 /* set lan id */
215 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
216 E1000_STATUS_FUNC_SHIFT;
217
218 /* Set phy->phy_addr and phy->id. */
219 ret_val = igb_get_phy_id_82575(hw);
220 if (ret_val)
221 return ret_val;
222
223 /* Verify phy id and set remaining function pointers */
224 switch (phy->id) {
225 case M88E1543_E_PHY_ID:
226 case I347AT4_E_PHY_ID:
227 case M88E1112_E_PHY_ID:
228 case M88E1111_I_PHY_ID:
229 phy->type = e1000_phy_m88;
230 phy->ops.check_polarity = igb_check_polarity_m88;
231 phy->ops.get_phy_info = igb_get_phy_info_m88;
232 if (phy->id != M88E1111_I_PHY_ID)
233 phy->ops.get_cable_length =
234 igb_get_cable_length_m88_gen2;
235 else
236 phy->ops.get_cable_length = igb_get_cable_length_m88;
237 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
238 /* Check if this PHY is confgured for media swap. */
239 if (phy->id == M88E1112_E_PHY_ID) {
240 u16 data;
241
242 ret_val = phy->ops.write_reg(hw,
243 E1000_M88E1112_PAGE_ADDR,
244 2);
245 if (ret_val)
246 goto out;
247
248 ret_val = phy->ops.read_reg(hw,
249 E1000_M88E1112_MAC_CTRL_1,
250 &data);
251 if (ret_val)
252 goto out;
253
254 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
255 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
256 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
257 data == E1000_M88E1112_AUTO_COPPER_BASEX)
258 hw->mac.ops.check_for_link =
259 igb_check_for_link_media_swap;
260 }
261 break;
262 case IGP03E1000_E_PHY_ID:
263 phy->type = e1000_phy_igp_3;
264 phy->ops.get_phy_info = igb_get_phy_info_igp;
265 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
266 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
267 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
268 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
269 break;
270 case I82580_I_PHY_ID:
271 case I350_I_PHY_ID:
272 phy->type = e1000_phy_82580;
273 phy->ops.force_speed_duplex =
274 igb_phy_force_speed_duplex_82580;
275 phy->ops.get_cable_length = igb_get_cable_length_82580;
276 phy->ops.get_phy_info = igb_get_phy_info_82580;
277 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
278 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
279 break;
280 case I210_I_PHY_ID:
281 phy->type = e1000_phy_i210;
282 phy->ops.check_polarity = igb_check_polarity_m88;
283 phy->ops.get_phy_info = igb_get_phy_info_m88;
284 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
285 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
286 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
287 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
288 break;
289 default:
290 ret_val = -E1000_ERR_PHY;
291 goto out;
292 }
293
294 out:
295 return ret_val;
296 }
297
298 /**
299 * igb_init_nvm_params_82575 - Init NVM func ptrs.
300 * @hw: pointer to the HW structure
301 **/
302 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
303 {
304 struct e1000_nvm_info *nvm = &hw->nvm;
305 u32 eecd = rd32(E1000_EECD);
306 u16 size;
307
308 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
309 E1000_EECD_SIZE_EX_SHIFT);
310
311 /* Added to a constant, "size" becomes the left-shift value
312 * for setting word_size.
313 */
314 size += NVM_WORD_SIZE_BASE_SHIFT;
315
316 /* Just in case size is out of range, cap it to the largest
317 * EEPROM size supported
318 */
319 if (size > 15)
320 size = 15;
321
322 nvm->word_size = 1 << size;
323 nvm->opcode_bits = 8;
324 nvm->delay_usec = 1;
325
326 switch (nvm->override) {
327 case e1000_nvm_override_spi_large:
328 nvm->page_size = 32;
329 nvm->address_bits = 16;
330 break;
331 case e1000_nvm_override_spi_small:
332 nvm->page_size = 8;
333 nvm->address_bits = 8;
334 break;
335 default:
336 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
337 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
338 16 : 8;
339 break;
340 }
341 if (nvm->word_size == (1 << 15))
342 nvm->page_size = 128;
343
344 nvm->type = e1000_nvm_eeprom_spi;
345
346 /* NVM Function Pointers */
347 nvm->ops.acquire = igb_acquire_nvm_82575;
348 nvm->ops.release = igb_release_nvm_82575;
349 nvm->ops.write = igb_write_nvm_spi;
350 nvm->ops.validate = igb_validate_nvm_checksum;
351 nvm->ops.update = igb_update_nvm_checksum;
352 if (nvm->word_size < (1 << 15))
353 nvm->ops.read = igb_read_nvm_eerd;
354 else
355 nvm->ops.read = igb_read_nvm_spi;
356
357 /* override generic family function pointers for specific descendants */
358 switch (hw->mac.type) {
359 case e1000_82580:
360 nvm->ops.validate = igb_validate_nvm_checksum_82580;
361 nvm->ops.update = igb_update_nvm_checksum_82580;
362 break;
363 case e1000_i354:
364 case e1000_i350:
365 nvm->ops.validate = igb_validate_nvm_checksum_i350;
366 nvm->ops.update = igb_update_nvm_checksum_i350;
367 break;
368 default:
369 break;
370 }
371
372 return 0;
373 }
374
375 /**
376 * igb_init_mac_params_82575 - Init MAC func ptrs.
377 * @hw: pointer to the HW structure
378 **/
379 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
380 {
381 struct e1000_mac_info *mac = &hw->mac;
382 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
383
384 /* Set mta register count */
385 mac->mta_reg_count = 128;
386 /* Set rar entry count */
387 switch (mac->type) {
388 case e1000_82576:
389 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
390 break;
391 case e1000_82580:
392 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
393 break;
394 case e1000_i350:
395 case e1000_i354:
396 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
397 break;
398 default:
399 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
400 break;
401 }
402 /* reset */
403 if (mac->type >= e1000_82580)
404 mac->ops.reset_hw = igb_reset_hw_82580;
405 else
406 mac->ops.reset_hw = igb_reset_hw_82575;
407
408 if (mac->type >= e1000_i210) {
409 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
410 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
411
412 } else {
413 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
414 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
415 }
416
417 /* Set if part includes ASF firmware */
418 mac->asf_firmware_present = true;
419 /* Set if manageability features are enabled. */
420 mac->arc_subsystem_valid =
421 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
422 ? true : false;
423 /* enable EEE on i350 parts and later parts */
424 if (mac->type >= e1000_i350)
425 dev_spec->eee_disable = false;
426 else
427 dev_spec->eee_disable = true;
428 /* Allow a single clear of the SW semaphore on I210 and newer */
429 if (mac->type >= e1000_i210)
430 dev_spec->clear_semaphore_once = true;
431 /* physical interface link setup */
432 mac->ops.setup_physical_interface =
433 (hw->phy.media_type == e1000_media_type_copper)
434 ? igb_setup_copper_link_82575
435 : igb_setup_serdes_link_82575;
436
437 if (mac->type == e1000_82580) {
438 switch (hw->device_id) {
439 /* feature not supported on these id's */
440 case E1000_DEV_ID_DH89XXCC_SGMII:
441 case E1000_DEV_ID_DH89XXCC_SERDES:
442 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
443 case E1000_DEV_ID_DH89XXCC_SFP:
444 break;
445 default:
446 hw->dev_spec._82575.mas_capable = true;
447 break;
448 }
449 }
450 return 0;
451 }
452
453 /**
454 * igb_set_sfp_media_type_82575 - derives SFP module media type.
455 * @hw: pointer to the HW structure
456 *
457 * The media type is chosen based on SFP module.
458 * compatibility flags retrieved from SFP ID EEPROM.
459 **/
460 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
461 {
462 s32 ret_val = E1000_ERR_CONFIG;
463 u32 ctrl_ext = 0;
464 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
465 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
466 u8 tranceiver_type = 0;
467 s32 timeout = 3;
468
469 /* Turn I2C interface ON and power on sfp cage */
470 ctrl_ext = rd32(E1000_CTRL_EXT);
471 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
472 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
473
474 wrfl();
475
476 /* Read SFP module data */
477 while (timeout) {
478 ret_val = igb_read_sfp_data_byte(hw,
479 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
480 &tranceiver_type);
481 if (ret_val == 0)
482 break;
483 msleep(100);
484 timeout--;
485 }
486 if (ret_val != 0)
487 goto out;
488
489 ret_val = igb_read_sfp_data_byte(hw,
490 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
491 (u8 *)eth_flags);
492 if (ret_val != 0)
493 goto out;
494
495 /* Check if there is some SFP module plugged and powered */
496 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
497 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
498 dev_spec->module_plugged = true;
499 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
500 hw->phy.media_type = e1000_media_type_internal_serdes;
501 } else if (eth_flags->e100_base_fx) {
502 dev_spec->sgmii_active = true;
503 hw->phy.media_type = e1000_media_type_internal_serdes;
504 } else if (eth_flags->e1000_base_t) {
505 dev_spec->sgmii_active = true;
506 hw->phy.media_type = e1000_media_type_copper;
507 } else {
508 hw->phy.media_type = e1000_media_type_unknown;
509 hw_dbg("PHY module has not been recognized\n");
510 goto out;
511 }
512 } else {
513 hw->phy.media_type = e1000_media_type_unknown;
514 }
515 ret_val = 0;
516 out:
517 /* Restore I2C interface setting */
518 wr32(E1000_CTRL_EXT, ctrl_ext);
519 return ret_val;
520 }
521
522 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
523 {
524 struct e1000_mac_info *mac = &hw->mac;
525 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
526 s32 ret_val;
527 u32 ctrl_ext = 0;
528 u32 link_mode = 0;
529
530 switch (hw->device_id) {
531 case E1000_DEV_ID_82575EB_COPPER:
532 case E1000_DEV_ID_82575EB_FIBER_SERDES:
533 case E1000_DEV_ID_82575GB_QUAD_COPPER:
534 mac->type = e1000_82575;
535 break;
536 case E1000_DEV_ID_82576:
537 case E1000_DEV_ID_82576_NS:
538 case E1000_DEV_ID_82576_NS_SERDES:
539 case E1000_DEV_ID_82576_FIBER:
540 case E1000_DEV_ID_82576_SERDES:
541 case E1000_DEV_ID_82576_QUAD_COPPER:
542 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
543 case E1000_DEV_ID_82576_SERDES_QUAD:
544 mac->type = e1000_82576;
545 break;
546 case E1000_DEV_ID_82580_COPPER:
547 case E1000_DEV_ID_82580_FIBER:
548 case E1000_DEV_ID_82580_QUAD_FIBER:
549 case E1000_DEV_ID_82580_SERDES:
550 case E1000_DEV_ID_82580_SGMII:
551 case E1000_DEV_ID_82580_COPPER_DUAL:
552 case E1000_DEV_ID_DH89XXCC_SGMII:
553 case E1000_DEV_ID_DH89XXCC_SERDES:
554 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
555 case E1000_DEV_ID_DH89XXCC_SFP:
556 mac->type = e1000_82580;
557 break;
558 case E1000_DEV_ID_I350_COPPER:
559 case E1000_DEV_ID_I350_FIBER:
560 case E1000_DEV_ID_I350_SERDES:
561 case E1000_DEV_ID_I350_SGMII:
562 mac->type = e1000_i350;
563 break;
564 case E1000_DEV_ID_I210_COPPER:
565 case E1000_DEV_ID_I210_FIBER:
566 case E1000_DEV_ID_I210_SERDES:
567 case E1000_DEV_ID_I210_SGMII:
568 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
569 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
570 mac->type = e1000_i210;
571 break;
572 case E1000_DEV_ID_I211_COPPER:
573 mac->type = e1000_i211;
574 break;
575 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
576 case E1000_DEV_ID_I354_SGMII:
577 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
578 mac->type = e1000_i354;
579 break;
580 default:
581 return -E1000_ERR_MAC_INIT;
582 break;
583 }
584
585 /* Set media type */
586 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
587 * based on the EEPROM. We cannot rely upon device ID. There
588 * is no distinguishable difference between fiber and internal
589 * SerDes mode on the 82575. There can be an external PHY attached
590 * on the SGMII interface. For this, we'll set sgmii_active to true.
591 */
592 hw->phy.media_type = e1000_media_type_copper;
593 dev_spec->sgmii_active = false;
594 dev_spec->module_plugged = false;
595
596 ctrl_ext = rd32(E1000_CTRL_EXT);
597
598 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
599 switch (link_mode) {
600 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
601 hw->phy.media_type = e1000_media_type_internal_serdes;
602 break;
603 case E1000_CTRL_EXT_LINK_MODE_SGMII:
604 /* Get phy control interface type set (MDIO vs. I2C)*/
605 if (igb_sgmii_uses_mdio_82575(hw)) {
606 hw->phy.media_type = e1000_media_type_copper;
607 dev_spec->sgmii_active = true;
608 break;
609 }
610 /* fall through for I2C based SGMII */
611 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
612 /* read media type from SFP EEPROM */
613 ret_val = igb_set_sfp_media_type_82575(hw);
614 if ((ret_val != 0) ||
615 (hw->phy.media_type == e1000_media_type_unknown)) {
616 /* If media type was not identified then return media
617 * type defined by the CTRL_EXT settings.
618 */
619 hw->phy.media_type = e1000_media_type_internal_serdes;
620
621 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
622 hw->phy.media_type = e1000_media_type_copper;
623 dev_spec->sgmii_active = true;
624 }
625
626 break;
627 }
628
629 /* do not change link mode for 100BaseFX */
630 if (dev_spec->eth_flags.e100_base_fx)
631 break;
632
633 /* change current link mode setting */
634 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
635
636 if (hw->phy.media_type == e1000_media_type_copper)
637 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
638 else
639 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
640
641 wr32(E1000_CTRL_EXT, ctrl_ext);
642
643 break;
644 default:
645 break;
646 }
647
648 /* mac initialization and operations */
649 ret_val = igb_init_mac_params_82575(hw);
650 if (ret_val)
651 goto out;
652
653 /* NVM initialization */
654 ret_val = igb_init_nvm_params_82575(hw);
655 switch (hw->mac.type) {
656 case e1000_i210:
657 case e1000_i211:
658 ret_val = igb_init_nvm_params_i210(hw);
659 break;
660 default:
661 break;
662 }
663
664 if (ret_val)
665 goto out;
666
667 /* if part supports SR-IOV then initialize mailbox parameters */
668 switch (mac->type) {
669 case e1000_82576:
670 case e1000_i350:
671 igb_init_mbx_params_pf(hw);
672 break;
673 default:
674 break;
675 }
676
677 /* setup PHY parameters */
678 ret_val = igb_init_phy_params_82575(hw);
679
680 out:
681 return ret_val;
682 }
683
684 /**
685 * igb_acquire_phy_82575 - Acquire rights to access PHY
686 * @hw: pointer to the HW structure
687 *
688 * Acquire access rights to the correct PHY. This is a
689 * function pointer entry point called by the api module.
690 **/
691 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
692 {
693 u16 mask = E1000_SWFW_PHY0_SM;
694
695 if (hw->bus.func == E1000_FUNC_1)
696 mask = E1000_SWFW_PHY1_SM;
697 else if (hw->bus.func == E1000_FUNC_2)
698 mask = E1000_SWFW_PHY2_SM;
699 else if (hw->bus.func == E1000_FUNC_3)
700 mask = E1000_SWFW_PHY3_SM;
701
702 return hw->mac.ops.acquire_swfw_sync(hw, mask);
703 }
704
705 /**
706 * igb_release_phy_82575 - Release rights to access PHY
707 * @hw: pointer to the HW structure
708 *
709 * A wrapper to release access rights to the correct PHY. This is a
710 * function pointer entry point called by the api module.
711 **/
712 static void igb_release_phy_82575(struct e1000_hw *hw)
713 {
714 u16 mask = E1000_SWFW_PHY0_SM;
715
716 if (hw->bus.func == E1000_FUNC_1)
717 mask = E1000_SWFW_PHY1_SM;
718 else if (hw->bus.func == E1000_FUNC_2)
719 mask = E1000_SWFW_PHY2_SM;
720 else if (hw->bus.func == E1000_FUNC_3)
721 mask = E1000_SWFW_PHY3_SM;
722
723 hw->mac.ops.release_swfw_sync(hw, mask);
724 }
725
726 /**
727 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
728 * @hw: pointer to the HW structure
729 * @offset: register offset to be read
730 * @data: pointer to the read data
731 *
732 * Reads the PHY register at offset using the serial gigabit media independent
733 * interface and stores the retrieved information in data.
734 **/
735 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
736 u16 *data)
737 {
738 s32 ret_val = -E1000_ERR_PARAM;
739
740 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
741 hw_dbg("PHY Address %u is out of range\n", offset);
742 goto out;
743 }
744
745 ret_val = hw->phy.ops.acquire(hw);
746 if (ret_val)
747 goto out;
748
749 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
750
751 hw->phy.ops.release(hw);
752
753 out:
754 return ret_val;
755 }
756
757 /**
758 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
759 * @hw: pointer to the HW structure
760 * @offset: register offset to write to
761 * @data: data to write at register offset
762 *
763 * Writes the data to PHY register at the offset using the serial gigabit
764 * media independent interface.
765 **/
766 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
767 u16 data)
768 {
769 s32 ret_val = -E1000_ERR_PARAM;
770
771
772 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
773 hw_dbg("PHY Address %d is out of range\n", offset);
774 goto out;
775 }
776
777 ret_val = hw->phy.ops.acquire(hw);
778 if (ret_val)
779 goto out;
780
781 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
782
783 hw->phy.ops.release(hw);
784
785 out:
786 return ret_val;
787 }
788
789 /**
790 * igb_get_phy_id_82575 - Retrieve PHY addr and id
791 * @hw: pointer to the HW structure
792 *
793 * Retrieves the PHY address and ID for both PHY's which do and do not use
794 * sgmi interface.
795 **/
796 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
797 {
798 struct e1000_phy_info *phy = &hw->phy;
799 s32 ret_val = 0;
800 u16 phy_id;
801 u32 ctrl_ext;
802 u32 mdic;
803
804 /* Extra read required for some PHY's on i354 */
805 if (hw->mac.type == e1000_i354)
806 igb_get_phy_id(hw);
807
808 /* For SGMII PHYs, we try the list of possible addresses until
809 * we find one that works. For non-SGMII PHYs
810 * (e.g. integrated copper PHYs), an address of 1 should
811 * work. The result of this function should mean phy->phy_addr
812 * and phy->id are set correctly.
813 */
814 if (!(igb_sgmii_active_82575(hw))) {
815 phy->addr = 1;
816 ret_val = igb_get_phy_id(hw);
817 goto out;
818 }
819
820 if (igb_sgmii_uses_mdio_82575(hw)) {
821 switch (hw->mac.type) {
822 case e1000_82575:
823 case e1000_82576:
824 mdic = rd32(E1000_MDIC);
825 mdic &= E1000_MDIC_PHY_MASK;
826 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
827 break;
828 case e1000_82580:
829 case e1000_i350:
830 case e1000_i354:
831 case e1000_i210:
832 case e1000_i211:
833 mdic = rd32(E1000_MDICNFG);
834 mdic &= E1000_MDICNFG_PHY_MASK;
835 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
836 break;
837 default:
838 ret_val = -E1000_ERR_PHY;
839 goto out;
840 break;
841 }
842 ret_val = igb_get_phy_id(hw);
843 goto out;
844 }
845
846 /* Power on sgmii phy if it is disabled */
847 ctrl_ext = rd32(E1000_CTRL_EXT);
848 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
849 wrfl();
850 msleep(300);
851
852 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
853 * Therefore, we need to test 1-7
854 */
855 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
856 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
857 if (ret_val == 0) {
858 hw_dbg("Vendor ID 0x%08X read at address %u\n",
859 phy_id, phy->addr);
860 /* At the time of this writing, The M88 part is
861 * the only supported SGMII PHY product.
862 */
863 if (phy_id == M88_VENDOR)
864 break;
865 } else {
866 hw_dbg("PHY address %u was unreadable\n", phy->addr);
867 }
868 }
869
870 /* A valid PHY type couldn't be found. */
871 if (phy->addr == 8) {
872 phy->addr = 0;
873 ret_val = -E1000_ERR_PHY;
874 goto out;
875 } else {
876 ret_val = igb_get_phy_id(hw);
877 }
878
879 /* restore previous sfp cage power state */
880 wr32(E1000_CTRL_EXT, ctrl_ext);
881
882 out:
883 return ret_val;
884 }
885
886 /**
887 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
888 * @hw: pointer to the HW structure
889 *
890 * Resets the PHY using the serial gigabit media independent interface.
891 **/
892 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
893 {
894 s32 ret_val;
895
896 /* This isn't a true "hard" reset, but is the only reset
897 * available to us at this time.
898 */
899
900 hw_dbg("Soft resetting SGMII attached PHY...\n");
901
902 /* SFP documentation requires the following to configure the SPF module
903 * to work on SGMII. No further documentation is given.
904 */
905 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
906 if (ret_val)
907 goto out;
908
909 ret_val = igb_phy_sw_reset(hw);
910
911 out:
912 return ret_val;
913 }
914
915 /**
916 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
917 * @hw: pointer to the HW structure
918 * @active: true to enable LPLU, false to disable
919 *
920 * Sets the LPLU D0 state according to the active flag. When
921 * activating LPLU this function also disables smart speed
922 * and vice versa. LPLU will not be activated unless the
923 * device autonegotiation advertisement meets standards of
924 * either 10 or 10/100 or 10/100/1000 at all duplexes.
925 * This is a function pointer entry point only called by
926 * PHY setup routines.
927 **/
928 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
929 {
930 struct e1000_phy_info *phy = &hw->phy;
931 s32 ret_val;
932 u16 data;
933
934 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
935 if (ret_val)
936 goto out;
937
938 if (active) {
939 data |= IGP02E1000_PM_D0_LPLU;
940 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
941 data);
942 if (ret_val)
943 goto out;
944
945 /* When LPLU is enabled, we should disable SmartSpeed */
946 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
947 &data);
948 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
949 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
950 data);
951 if (ret_val)
952 goto out;
953 } else {
954 data &= ~IGP02E1000_PM_D0_LPLU;
955 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
956 data);
957 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
958 * during Dx states where the power conservation is most
959 * important. During driver activity we should enable
960 * SmartSpeed, so performance is maintained.
961 */
962 if (phy->smart_speed == e1000_smart_speed_on) {
963 ret_val = phy->ops.read_reg(hw,
964 IGP01E1000_PHY_PORT_CONFIG, &data);
965 if (ret_val)
966 goto out;
967
968 data |= IGP01E1000_PSCFR_SMART_SPEED;
969 ret_val = phy->ops.write_reg(hw,
970 IGP01E1000_PHY_PORT_CONFIG, data);
971 if (ret_val)
972 goto out;
973 } else if (phy->smart_speed == e1000_smart_speed_off) {
974 ret_val = phy->ops.read_reg(hw,
975 IGP01E1000_PHY_PORT_CONFIG, &data);
976 if (ret_val)
977 goto out;
978
979 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
980 ret_val = phy->ops.write_reg(hw,
981 IGP01E1000_PHY_PORT_CONFIG, data);
982 if (ret_val)
983 goto out;
984 }
985 }
986
987 out:
988 return ret_val;
989 }
990
991 /**
992 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
993 * @hw: pointer to the HW structure
994 * @active: true to enable LPLU, false to disable
995 *
996 * Sets the LPLU D0 state according to the active flag. When
997 * activating LPLU this function also disables smart speed
998 * and vice versa. LPLU will not be activated unless the
999 * device autonegotiation advertisement meets standards of
1000 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1001 * This is a function pointer entry point only called by
1002 * PHY setup routines.
1003 **/
1004 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1005 {
1006 struct e1000_phy_info *phy = &hw->phy;
1007 s32 ret_val = 0;
1008 u16 data;
1009
1010 data = rd32(E1000_82580_PHY_POWER_MGMT);
1011
1012 if (active) {
1013 data |= E1000_82580_PM_D0_LPLU;
1014
1015 /* When LPLU is enabled, we should disable SmartSpeed */
1016 data &= ~E1000_82580_PM_SPD;
1017 } else {
1018 data &= ~E1000_82580_PM_D0_LPLU;
1019
1020 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1021 * during Dx states where the power conservation is most
1022 * important. During driver activity we should enable
1023 * SmartSpeed, so performance is maintained.
1024 */
1025 if (phy->smart_speed == e1000_smart_speed_on)
1026 data |= E1000_82580_PM_SPD;
1027 else if (phy->smart_speed == e1000_smart_speed_off)
1028 data &= ~E1000_82580_PM_SPD; }
1029
1030 wr32(E1000_82580_PHY_POWER_MGMT, data);
1031 return ret_val;
1032 }
1033
1034 /**
1035 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1036 * @hw: pointer to the HW structure
1037 * @active: boolean used to enable/disable lplu
1038 *
1039 * Success returns 0, Failure returns 1
1040 *
1041 * The low power link up (lplu) state is set to the power management level D3
1042 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1043 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1044 * is used during Dx states where the power conservation is most important.
1045 * During driver activity, SmartSpeed should be enabled so performance is
1046 * maintained.
1047 **/
1048 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1049 {
1050 struct e1000_phy_info *phy = &hw->phy;
1051 s32 ret_val = 0;
1052 u16 data;
1053
1054 data = rd32(E1000_82580_PHY_POWER_MGMT);
1055
1056 if (!active) {
1057 data &= ~E1000_82580_PM_D3_LPLU;
1058 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1059 * during Dx states where the power conservation is most
1060 * important. During driver activity we should enable
1061 * SmartSpeed, so performance is maintained.
1062 */
1063 if (phy->smart_speed == e1000_smart_speed_on)
1064 data |= E1000_82580_PM_SPD;
1065 else if (phy->smart_speed == e1000_smart_speed_off)
1066 data &= ~E1000_82580_PM_SPD;
1067 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1068 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1069 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1070 data |= E1000_82580_PM_D3_LPLU;
1071 /* When LPLU is enabled, we should disable SmartSpeed */
1072 data &= ~E1000_82580_PM_SPD;
1073 }
1074
1075 wr32(E1000_82580_PHY_POWER_MGMT, data);
1076 return ret_val;
1077 }
1078
1079 /**
1080 * igb_acquire_nvm_82575 - Request for access to EEPROM
1081 * @hw: pointer to the HW structure
1082 *
1083 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1084 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1085 * Return successful if access grant bit set, else clear the request for
1086 * EEPROM access and return -E1000_ERR_NVM (-1).
1087 **/
1088 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1089 {
1090 s32 ret_val;
1091
1092 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1093 if (ret_val)
1094 goto out;
1095
1096 ret_val = igb_acquire_nvm(hw);
1097
1098 if (ret_val)
1099 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1100
1101 out:
1102 return ret_val;
1103 }
1104
1105 /**
1106 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1107 * @hw: pointer to the HW structure
1108 *
1109 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1110 * then release the semaphores acquired.
1111 **/
1112 static void igb_release_nvm_82575(struct e1000_hw *hw)
1113 {
1114 igb_release_nvm(hw);
1115 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1116 }
1117
1118 /**
1119 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1120 * @hw: pointer to the HW structure
1121 * @mask: specifies which semaphore to acquire
1122 *
1123 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1124 * will also specify which port we're acquiring the lock for.
1125 **/
1126 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1127 {
1128 u32 swfw_sync;
1129 u32 swmask = mask;
1130 u32 fwmask = mask << 16;
1131 s32 ret_val = 0;
1132 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1133
1134 while (i < timeout) {
1135 if (igb_get_hw_semaphore(hw)) {
1136 ret_val = -E1000_ERR_SWFW_SYNC;
1137 goto out;
1138 }
1139
1140 swfw_sync = rd32(E1000_SW_FW_SYNC);
1141 if (!(swfw_sync & (fwmask | swmask)))
1142 break;
1143
1144 /* Firmware currently using resource (fwmask)
1145 * or other software thread using resource (swmask)
1146 */
1147 igb_put_hw_semaphore(hw);
1148 mdelay(5);
1149 i++;
1150 }
1151
1152 if (i == timeout) {
1153 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1154 ret_val = -E1000_ERR_SWFW_SYNC;
1155 goto out;
1156 }
1157
1158 swfw_sync |= swmask;
1159 wr32(E1000_SW_FW_SYNC, swfw_sync);
1160
1161 igb_put_hw_semaphore(hw);
1162
1163 out:
1164 return ret_val;
1165 }
1166
1167 /**
1168 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1169 * @hw: pointer to the HW structure
1170 * @mask: specifies which semaphore to acquire
1171 *
1172 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1173 * will also specify which port we're releasing the lock for.
1174 **/
1175 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1176 {
1177 u32 swfw_sync;
1178
1179 while (igb_get_hw_semaphore(hw) != 0)
1180 ; /* Empty */
1181
1182 swfw_sync = rd32(E1000_SW_FW_SYNC);
1183 swfw_sync &= ~mask;
1184 wr32(E1000_SW_FW_SYNC, swfw_sync);
1185
1186 igb_put_hw_semaphore(hw);
1187 }
1188
1189 /**
1190 * igb_get_cfg_done_82575 - Read config done bit
1191 * @hw: pointer to the HW structure
1192 *
1193 * Read the management control register for the config done bit for
1194 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1195 * to read the config done bit, so an error is *ONLY* logged and returns
1196 * 0. If we were to return with error, EEPROM-less silicon
1197 * would not be able to be reset or change link.
1198 **/
1199 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1200 {
1201 s32 timeout = PHY_CFG_TIMEOUT;
1202 s32 ret_val = 0;
1203 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1204
1205 if (hw->bus.func == 1)
1206 mask = E1000_NVM_CFG_DONE_PORT_1;
1207 else if (hw->bus.func == E1000_FUNC_2)
1208 mask = E1000_NVM_CFG_DONE_PORT_2;
1209 else if (hw->bus.func == E1000_FUNC_3)
1210 mask = E1000_NVM_CFG_DONE_PORT_3;
1211
1212 while (timeout) {
1213 if (rd32(E1000_EEMNGCTL) & mask)
1214 break;
1215 usleep_range(1000, 2000);
1216 timeout--;
1217 }
1218 if (!timeout)
1219 hw_dbg("MNG configuration cycle has not completed.\n");
1220
1221 /* If EEPROM is not marked present, init the PHY manually */
1222 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1223 (hw->phy.type == e1000_phy_igp_3))
1224 igb_phy_init_script_igp3(hw);
1225
1226 return ret_val;
1227 }
1228
1229 /**
1230 * igb_get_link_up_info_82575 - Get link speed/duplex info
1231 * @hw: pointer to the HW structure
1232 * @speed: stores the current speed
1233 * @duplex: stores the current duplex
1234 *
1235 * This is a wrapper function, if using the serial gigabit media independent
1236 * interface, use PCS to retrieve the link speed and duplex information.
1237 * Otherwise, use the generic function to get the link speed and duplex info.
1238 **/
1239 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1240 u16 *duplex)
1241 {
1242 s32 ret_val;
1243
1244 if (hw->phy.media_type != e1000_media_type_copper)
1245 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1246 duplex);
1247 else
1248 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1249 duplex);
1250
1251 return ret_val;
1252 }
1253
1254 /**
1255 * igb_check_for_link_82575 - Check for link
1256 * @hw: pointer to the HW structure
1257 *
1258 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1259 * use the generic interface for determining link.
1260 **/
1261 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1262 {
1263 s32 ret_val;
1264 u16 speed, duplex;
1265
1266 if (hw->phy.media_type != e1000_media_type_copper) {
1267 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1268 &duplex);
1269 /* Use this flag to determine if link needs to be checked or
1270 * not. If we have link clear the flag so that we do not
1271 * continue to check for link.
1272 */
1273 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1274
1275 /* Configure Flow Control now that Auto-Neg has completed.
1276 * First, we need to restore the desired flow control
1277 * settings because we may have had to re-autoneg with a
1278 * different link partner.
1279 */
1280 ret_val = igb_config_fc_after_link_up(hw);
1281 if (ret_val)
1282 hw_dbg("Error configuring flow control\n");
1283 } else {
1284 ret_val = igb_check_for_copper_link(hw);
1285 }
1286
1287 return ret_val;
1288 }
1289
1290 /**
1291 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1292 * @hw: pointer to the HW structure
1293 **/
1294 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1295 {
1296 u32 reg;
1297
1298
1299 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1300 !igb_sgmii_active_82575(hw))
1301 return;
1302
1303 /* Enable PCS to turn on link */
1304 reg = rd32(E1000_PCS_CFG0);
1305 reg |= E1000_PCS_CFG_PCS_EN;
1306 wr32(E1000_PCS_CFG0, reg);
1307
1308 /* Power up the laser */
1309 reg = rd32(E1000_CTRL_EXT);
1310 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1311 wr32(E1000_CTRL_EXT, reg);
1312
1313 /* flush the write to verify completion */
1314 wrfl();
1315 usleep_range(1000, 2000);
1316 }
1317
1318 /**
1319 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1320 * @hw: pointer to the HW structure
1321 * @speed: stores the current speed
1322 * @duplex: stores the current duplex
1323 *
1324 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1325 * duplex, then store the values in the pointers provided.
1326 **/
1327 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1328 u16 *duplex)
1329 {
1330 struct e1000_mac_info *mac = &hw->mac;
1331 u32 pcs, status;
1332
1333 /* Set up defaults for the return values of this function */
1334 mac->serdes_has_link = false;
1335 *speed = 0;
1336 *duplex = 0;
1337
1338 /* Read the PCS Status register for link state. For non-copper mode,
1339 * the status register is not accurate. The PCS status register is
1340 * used instead.
1341 */
1342 pcs = rd32(E1000_PCS_LSTAT);
1343
1344 /* The link up bit determines when link is up on autoneg. The sync ok
1345 * gets set once both sides sync up and agree upon link. Stable link
1346 * can be determined by checking for both link up and link sync ok
1347 */
1348 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1349 mac->serdes_has_link = true;
1350
1351 /* Detect and store PCS speed */
1352 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1353 *speed = SPEED_1000;
1354 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1355 *speed = SPEED_100;
1356 else
1357 *speed = SPEED_10;
1358
1359 /* Detect and store PCS duplex */
1360 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1361 *duplex = FULL_DUPLEX;
1362 else
1363 *duplex = HALF_DUPLEX;
1364
1365 /* Check if it is an I354 2.5Gb backplane connection. */
1366 if (mac->type == e1000_i354) {
1367 status = rd32(E1000_STATUS);
1368 if ((status & E1000_STATUS_2P5_SKU) &&
1369 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1370 *speed = SPEED_2500;
1371 *duplex = FULL_DUPLEX;
1372 hw_dbg("2500 Mbs, ");
1373 hw_dbg("Full Duplex\n");
1374 }
1375 }
1376
1377 }
1378
1379 return 0;
1380 }
1381
1382 /**
1383 * igb_shutdown_serdes_link_82575 - Remove link during power down
1384 * @hw: pointer to the HW structure
1385 *
1386 * In the case of fiber serdes, shut down optics and PCS on driver unload
1387 * when management pass thru is not enabled.
1388 **/
1389 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1390 {
1391 u32 reg;
1392
1393 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1394 igb_sgmii_active_82575(hw))
1395 return;
1396
1397 if (!igb_enable_mng_pass_thru(hw)) {
1398 /* Disable PCS to turn off link */
1399 reg = rd32(E1000_PCS_CFG0);
1400 reg &= ~E1000_PCS_CFG_PCS_EN;
1401 wr32(E1000_PCS_CFG0, reg);
1402
1403 /* shutdown the laser */
1404 reg = rd32(E1000_CTRL_EXT);
1405 reg |= E1000_CTRL_EXT_SDP3_DATA;
1406 wr32(E1000_CTRL_EXT, reg);
1407
1408 /* flush the write to verify completion */
1409 wrfl();
1410 usleep_range(1000, 2000);
1411 }
1412 }
1413
1414 /**
1415 * igb_reset_hw_82575 - Reset hardware
1416 * @hw: pointer to the HW structure
1417 *
1418 * This resets the hardware into a known state. This is a
1419 * function pointer entry point called by the api module.
1420 **/
1421 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1422 {
1423 u32 ctrl;
1424 s32 ret_val;
1425
1426 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1427 * on the last TLP read/write transaction when MAC is reset.
1428 */
1429 ret_val = igb_disable_pcie_master(hw);
1430 if (ret_val)
1431 hw_dbg("PCI-E Master disable polling has failed.\n");
1432
1433 /* set the completion timeout for interface */
1434 ret_val = igb_set_pcie_completion_timeout(hw);
1435 if (ret_val)
1436 hw_dbg("PCI-E Set completion timeout has failed.\n");
1437
1438 hw_dbg("Masking off all interrupts\n");
1439 wr32(E1000_IMC, 0xffffffff);
1440
1441 wr32(E1000_RCTL, 0);
1442 wr32(E1000_TCTL, E1000_TCTL_PSP);
1443 wrfl();
1444
1445 usleep_range(10000, 20000);
1446
1447 ctrl = rd32(E1000_CTRL);
1448
1449 hw_dbg("Issuing a global reset to MAC\n");
1450 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1451
1452 ret_val = igb_get_auto_rd_done(hw);
1453 if (ret_val) {
1454 /* When auto config read does not complete, do not
1455 * return with an error. This can happen in situations
1456 * where there is no eeprom and prevents getting link.
1457 */
1458 hw_dbg("Auto Read Done did not complete\n");
1459 }
1460
1461 /* If EEPROM is not present, run manual init scripts */
1462 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1463 igb_reset_init_script_82575(hw);
1464
1465 /* Clear any pending interrupt events. */
1466 wr32(E1000_IMC, 0xffffffff);
1467 rd32(E1000_ICR);
1468
1469 /* Install any alternate MAC address into RAR0 */
1470 ret_val = igb_check_alt_mac_addr(hw);
1471
1472 return ret_val;
1473 }
1474
1475 /**
1476 * igb_init_hw_82575 - Initialize hardware
1477 * @hw: pointer to the HW structure
1478 *
1479 * This inits the hardware readying it for operation.
1480 **/
1481 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1482 {
1483 struct e1000_mac_info *mac = &hw->mac;
1484 s32 ret_val;
1485 u16 i, rar_count = mac->rar_entry_count;
1486
1487 /* Initialize identification LED */
1488 ret_val = igb_id_led_init(hw);
1489 if (ret_val) {
1490 hw_dbg("Error initializing identification LED\n");
1491 /* This is not fatal and we should not stop init due to this */
1492 }
1493
1494 /* Disabling VLAN filtering */
1495 hw_dbg("Initializing the IEEE VLAN\n");
1496 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1497 igb_clear_vfta_i350(hw);
1498 else
1499 igb_clear_vfta(hw);
1500
1501 /* Setup the receive address */
1502 igb_init_rx_addrs(hw, rar_count);
1503
1504 /* Zero out the Multicast HASH table */
1505 hw_dbg("Zeroing the MTA\n");
1506 for (i = 0; i < mac->mta_reg_count; i++)
1507 array_wr32(E1000_MTA, i, 0);
1508
1509 /* Zero out the Unicast HASH table */
1510 hw_dbg("Zeroing the UTA\n");
1511 for (i = 0; i < mac->uta_reg_count; i++)
1512 array_wr32(E1000_UTA, i, 0);
1513
1514 /* Setup link and flow control */
1515 ret_val = igb_setup_link(hw);
1516
1517 /* Clear all of the statistics registers (clear on read). It is
1518 * important that we do this after we have tried to establish link
1519 * because the symbol error count will increment wildly if there
1520 * is no link.
1521 */
1522 igb_clear_hw_cntrs_82575(hw);
1523 return ret_val;
1524 }
1525
1526 /**
1527 * igb_setup_copper_link_82575 - Configure copper link settings
1528 * @hw: pointer to the HW structure
1529 *
1530 * Configures the link for auto-neg or forced speed and duplex. Then we check
1531 * for link, once link is established calls to configure collision distance
1532 * and flow control are called.
1533 **/
1534 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1535 {
1536 u32 ctrl;
1537 s32 ret_val;
1538 u32 phpm_reg;
1539
1540 ctrl = rd32(E1000_CTRL);
1541 ctrl |= E1000_CTRL_SLU;
1542 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1543 wr32(E1000_CTRL, ctrl);
1544
1545 /* Clear Go Link Disconnect bit on supported devices */
1546 switch (hw->mac.type) {
1547 case e1000_82580:
1548 case e1000_i350:
1549 case e1000_i210:
1550 case e1000_i211:
1551 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1552 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1553 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1554 break;
1555 default:
1556 break;
1557 }
1558
1559 ret_val = igb_setup_serdes_link_82575(hw);
1560 if (ret_val)
1561 goto out;
1562
1563 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1564 /* allow time for SFP cage time to power up phy */
1565 msleep(300);
1566
1567 ret_val = hw->phy.ops.reset(hw);
1568 if (ret_val) {
1569 hw_dbg("Error resetting the PHY.\n");
1570 goto out;
1571 }
1572 }
1573 switch (hw->phy.type) {
1574 case e1000_phy_i210:
1575 case e1000_phy_m88:
1576 switch (hw->phy.id) {
1577 case I347AT4_E_PHY_ID:
1578 case M88E1112_E_PHY_ID:
1579 case M88E1543_E_PHY_ID:
1580 case I210_I_PHY_ID:
1581 ret_val = igb_copper_link_setup_m88_gen2(hw);
1582 break;
1583 default:
1584 ret_val = igb_copper_link_setup_m88(hw);
1585 break;
1586 }
1587 break;
1588 case e1000_phy_igp_3:
1589 ret_val = igb_copper_link_setup_igp(hw);
1590 break;
1591 case e1000_phy_82580:
1592 ret_val = igb_copper_link_setup_82580(hw);
1593 break;
1594 default:
1595 ret_val = -E1000_ERR_PHY;
1596 break;
1597 }
1598
1599 if (ret_val)
1600 goto out;
1601
1602 ret_val = igb_setup_copper_link(hw);
1603 out:
1604 return ret_val;
1605 }
1606
1607 /**
1608 * igb_setup_serdes_link_82575 - Setup link for serdes
1609 * @hw: pointer to the HW structure
1610 *
1611 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1612 * used on copper connections where the serialized gigabit media independent
1613 * interface (sgmii), or serdes fiber is being used. Configures the link
1614 * for auto-negotiation or forces speed/duplex.
1615 **/
1616 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1617 {
1618 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1619 bool pcs_autoneg;
1620 s32 ret_val = E1000_SUCCESS;
1621 u16 data;
1622
1623 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1624 !igb_sgmii_active_82575(hw))
1625 return ret_val;
1626
1627
1628 /* On the 82575, SerDes loopback mode persists until it is
1629 * explicitly turned off or a power cycle is performed. A read to
1630 * the register does not indicate its status. Therefore, we ensure
1631 * loopback mode is disabled during initialization.
1632 */
1633 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1634
1635 /* power on the sfp cage if present and turn on I2C */
1636 ctrl_ext = rd32(E1000_CTRL_EXT);
1637 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1638 ctrl_ext |= E1000_CTRL_I2C_ENA;
1639 wr32(E1000_CTRL_EXT, ctrl_ext);
1640
1641 ctrl_reg = rd32(E1000_CTRL);
1642 ctrl_reg |= E1000_CTRL_SLU;
1643
1644 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1645 /* set both sw defined pins */
1646 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1647
1648 /* Set switch control to serdes energy detect */
1649 reg = rd32(E1000_CONNSW);
1650 reg |= E1000_CONNSW_ENRGSRC;
1651 wr32(E1000_CONNSW, reg);
1652 }
1653
1654 reg = rd32(E1000_PCS_LCTL);
1655
1656 /* default pcs_autoneg to the same setting as mac autoneg */
1657 pcs_autoneg = hw->mac.autoneg;
1658
1659 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1660 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1661 /* sgmii mode lets the phy handle forcing speed/duplex */
1662 pcs_autoneg = true;
1663 /* autoneg time out should be disabled for SGMII mode */
1664 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1665 break;
1666 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1667 /* disable PCS autoneg and support parallel detect only */
1668 pcs_autoneg = false;
1669 default:
1670 if (hw->mac.type == e1000_82575 ||
1671 hw->mac.type == e1000_82576) {
1672 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1673 if (ret_val) {
1674 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1675 return ret_val;
1676 }
1677
1678 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1679 pcs_autoneg = false;
1680 }
1681
1682 /* non-SGMII modes only supports a speed of 1000/Full for the
1683 * link so it is best to just force the MAC and let the pcs
1684 * link either autoneg or be forced to 1000/Full
1685 */
1686 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1687 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1688
1689 /* set speed of 1000/Full if speed/duplex is forced */
1690 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1691 break;
1692 }
1693
1694 wr32(E1000_CTRL, ctrl_reg);
1695
1696 /* New SerDes mode allows for forcing speed or autonegotiating speed
1697 * at 1gb. Autoneg should be default set by most drivers. This is the
1698 * mode that will be compatible with older link partners and switches.
1699 * However, both are supported by the hardware and some drivers/tools.
1700 */
1701 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1702 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1703
1704 if (pcs_autoneg) {
1705 /* Set PCS register for autoneg */
1706 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1707 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1708
1709 /* Disable force flow control for autoneg */
1710 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1711
1712 /* Configure flow control advertisement for autoneg */
1713 anadv_reg = rd32(E1000_PCS_ANADV);
1714 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1715 switch (hw->fc.requested_mode) {
1716 case e1000_fc_full:
1717 case e1000_fc_rx_pause:
1718 anadv_reg |= E1000_TXCW_ASM_DIR;
1719 anadv_reg |= E1000_TXCW_PAUSE;
1720 break;
1721 case e1000_fc_tx_pause:
1722 anadv_reg |= E1000_TXCW_ASM_DIR;
1723 break;
1724 default:
1725 break;
1726 }
1727 wr32(E1000_PCS_ANADV, anadv_reg);
1728
1729 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1730 } else {
1731 /* Set PCS register for forced link */
1732 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1733
1734 /* Force flow control for forced link */
1735 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1736
1737 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1738 }
1739
1740 wr32(E1000_PCS_LCTL, reg);
1741
1742 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1743 igb_force_mac_fc(hw);
1744
1745 return ret_val;
1746 }
1747
1748 /**
1749 * igb_sgmii_active_82575 - Return sgmii state
1750 * @hw: pointer to the HW structure
1751 *
1752 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1753 * which can be enabled for use in the embedded applications. Simply
1754 * return the current state of the sgmii interface.
1755 **/
1756 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1757 {
1758 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1759 return dev_spec->sgmii_active;
1760 }
1761
1762 /**
1763 * igb_reset_init_script_82575 - Inits HW defaults after reset
1764 * @hw: pointer to the HW structure
1765 *
1766 * Inits recommended HW defaults after a reset when there is no EEPROM
1767 * detected. This is only for the 82575.
1768 **/
1769 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1770 {
1771 if (hw->mac.type == e1000_82575) {
1772 hw_dbg("Running reset init script for 82575\n");
1773 /* SerDes configuration via SERDESCTRL */
1774 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1775 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1776 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1777 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1778
1779 /* CCM configuration via CCMCTL register */
1780 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1781 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1782
1783 /* PCIe lanes configuration */
1784 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1785 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1786 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1787 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1788
1789 /* PCIe PLL Configuration */
1790 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1791 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1792 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1793 }
1794
1795 return 0;
1796 }
1797
1798 /**
1799 * igb_read_mac_addr_82575 - Read device MAC address
1800 * @hw: pointer to the HW structure
1801 **/
1802 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1803 {
1804 s32 ret_val = 0;
1805
1806 /* If there's an alternate MAC address place it in RAR0
1807 * so that it will override the Si installed default perm
1808 * address.
1809 */
1810 ret_val = igb_check_alt_mac_addr(hw);
1811 if (ret_val)
1812 goto out;
1813
1814 ret_val = igb_read_mac_addr(hw);
1815
1816 out:
1817 return ret_val;
1818 }
1819
1820 /**
1821 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1822 * @hw: pointer to the HW structure
1823 *
1824 * In the case of a PHY power down to save power, or to turn off link during a
1825 * driver unload, or wake on lan is not enabled, remove the link.
1826 **/
1827 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1828 {
1829 /* If the management interface is not enabled, then power down */
1830 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1831 igb_power_down_phy_copper(hw);
1832 }
1833
1834 /**
1835 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1836 * @hw: pointer to the HW structure
1837 *
1838 * Clears the hardware counters by reading the counter registers.
1839 **/
1840 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1841 {
1842 igb_clear_hw_cntrs_base(hw);
1843
1844 rd32(E1000_PRC64);
1845 rd32(E1000_PRC127);
1846 rd32(E1000_PRC255);
1847 rd32(E1000_PRC511);
1848 rd32(E1000_PRC1023);
1849 rd32(E1000_PRC1522);
1850 rd32(E1000_PTC64);
1851 rd32(E1000_PTC127);
1852 rd32(E1000_PTC255);
1853 rd32(E1000_PTC511);
1854 rd32(E1000_PTC1023);
1855 rd32(E1000_PTC1522);
1856
1857 rd32(E1000_ALGNERRC);
1858 rd32(E1000_RXERRC);
1859 rd32(E1000_TNCRS);
1860 rd32(E1000_CEXTERR);
1861 rd32(E1000_TSCTC);
1862 rd32(E1000_TSCTFC);
1863
1864 rd32(E1000_MGTPRC);
1865 rd32(E1000_MGTPDC);
1866 rd32(E1000_MGTPTC);
1867
1868 rd32(E1000_IAC);
1869 rd32(E1000_ICRXOC);
1870
1871 rd32(E1000_ICRXPTC);
1872 rd32(E1000_ICRXATC);
1873 rd32(E1000_ICTXPTC);
1874 rd32(E1000_ICTXATC);
1875 rd32(E1000_ICTXQEC);
1876 rd32(E1000_ICTXQMTC);
1877 rd32(E1000_ICRXDMTC);
1878
1879 rd32(E1000_CBTMPC);
1880 rd32(E1000_HTDPMC);
1881 rd32(E1000_CBRMPC);
1882 rd32(E1000_RPTHC);
1883 rd32(E1000_HGPTC);
1884 rd32(E1000_HTCBDPC);
1885 rd32(E1000_HGORCL);
1886 rd32(E1000_HGORCH);
1887 rd32(E1000_HGOTCL);
1888 rd32(E1000_HGOTCH);
1889 rd32(E1000_LENERRS);
1890
1891 /* This register should not be read in copper configurations */
1892 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1893 igb_sgmii_active_82575(hw))
1894 rd32(E1000_SCVPC);
1895 }
1896
1897 /**
1898 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1899 * @hw: pointer to the HW structure
1900 *
1901 * After rx enable if managability is enabled then there is likely some
1902 * bad data at the start of the fifo and possibly in the DMA fifo. This
1903 * function clears the fifos and flushes any packets that came in as rx was
1904 * being enabled.
1905 **/
1906 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1907 {
1908 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1909 int i, ms_wait;
1910
1911 if (hw->mac.type != e1000_82575 ||
1912 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1913 return;
1914
1915 /* Disable all RX queues */
1916 for (i = 0; i < 4; i++) {
1917 rxdctl[i] = rd32(E1000_RXDCTL(i));
1918 wr32(E1000_RXDCTL(i),
1919 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1920 }
1921 /* Poll all queues to verify they have shut down */
1922 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1923 usleep_range(1000, 2000);
1924 rx_enabled = 0;
1925 for (i = 0; i < 4; i++)
1926 rx_enabled |= rd32(E1000_RXDCTL(i));
1927 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1928 break;
1929 }
1930
1931 if (ms_wait == 10)
1932 hw_dbg("Queue disable timed out after 10ms\n");
1933
1934 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1935 * incoming packets are rejected. Set enable and wait 2ms so that
1936 * any packet that was coming in as RCTL.EN was set is flushed
1937 */
1938 rfctl = rd32(E1000_RFCTL);
1939 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1940
1941 rlpml = rd32(E1000_RLPML);
1942 wr32(E1000_RLPML, 0);
1943
1944 rctl = rd32(E1000_RCTL);
1945 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1946 temp_rctl |= E1000_RCTL_LPE;
1947
1948 wr32(E1000_RCTL, temp_rctl);
1949 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1950 wrfl();
1951 usleep_range(2000, 3000);
1952
1953 /* Enable RX queues that were previously enabled and restore our
1954 * previous state
1955 */
1956 for (i = 0; i < 4; i++)
1957 wr32(E1000_RXDCTL(i), rxdctl[i]);
1958 wr32(E1000_RCTL, rctl);
1959 wrfl();
1960
1961 wr32(E1000_RLPML, rlpml);
1962 wr32(E1000_RFCTL, rfctl);
1963
1964 /* Flush receive errors generated by workaround */
1965 rd32(E1000_ROC);
1966 rd32(E1000_RNBC);
1967 rd32(E1000_MPC);
1968 }
1969
1970 /**
1971 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1972 * @hw: pointer to the HW structure
1973 *
1974 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1975 * however the hardware default for these parts is 500us to 1ms which is less
1976 * than the 10ms recommended by the pci-e spec. To address this we need to
1977 * increase the value to either 10ms to 200ms for capability version 1 config,
1978 * or 16ms to 55ms for version 2.
1979 **/
1980 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1981 {
1982 u32 gcr = rd32(E1000_GCR);
1983 s32 ret_val = 0;
1984 u16 pcie_devctl2;
1985
1986 /* only take action if timeout value is defaulted to 0 */
1987 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1988 goto out;
1989
1990 /* if capabilities version is type 1 we can write the
1991 * timeout of 10ms to 200ms through the GCR register
1992 */
1993 if (!(gcr & E1000_GCR_CAP_VER2)) {
1994 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1995 goto out;
1996 }
1997
1998 /* for version 2 capabilities we need to write the config space
1999 * directly in order to set the completion timeout value for
2000 * 16ms to 55ms
2001 */
2002 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2003 &pcie_devctl2);
2004 if (ret_val)
2005 goto out;
2006
2007 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2008
2009 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2010 &pcie_devctl2);
2011 out:
2012 /* disable completion timeout resend */
2013 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2014
2015 wr32(E1000_GCR, gcr);
2016 return ret_val;
2017 }
2018
2019 /**
2020 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2021 * @hw: pointer to the hardware struct
2022 * @enable: state to enter, either enabled or disabled
2023 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2024 *
2025 * enables/disables L2 switch anti-spoofing functionality.
2026 **/
2027 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2028 {
2029 u32 reg_val, reg_offset;
2030
2031 switch (hw->mac.type) {
2032 case e1000_82576:
2033 reg_offset = E1000_DTXSWC;
2034 break;
2035 case e1000_i350:
2036 case e1000_i354:
2037 reg_offset = E1000_TXSWC;
2038 break;
2039 default:
2040 return;
2041 }
2042
2043 reg_val = rd32(reg_offset);
2044 if (enable) {
2045 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2046 E1000_DTXSWC_VLAN_SPOOF_MASK);
2047 /* The PF can spoof - it has to in order to
2048 * support emulation mode NICs
2049 */
2050 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2051 } else {
2052 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2053 E1000_DTXSWC_VLAN_SPOOF_MASK);
2054 }
2055 wr32(reg_offset, reg_val);
2056 }
2057
2058 /**
2059 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2060 * @hw: pointer to the hardware struct
2061 * @enable: state to enter, either enabled or disabled
2062 *
2063 * enables/disables L2 switch loopback functionality.
2064 **/
2065 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2066 {
2067 u32 dtxswc;
2068
2069 switch (hw->mac.type) {
2070 case e1000_82576:
2071 dtxswc = rd32(E1000_DTXSWC);
2072 if (enable)
2073 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2074 else
2075 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2076 wr32(E1000_DTXSWC, dtxswc);
2077 break;
2078 case e1000_i354:
2079 case e1000_i350:
2080 dtxswc = rd32(E1000_TXSWC);
2081 if (enable)
2082 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2083 else
2084 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2085 wr32(E1000_TXSWC, dtxswc);
2086 break;
2087 default:
2088 /* Currently no other hardware supports loopback */
2089 break;
2090 }
2091
2092 }
2093
2094 /**
2095 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2096 * @hw: pointer to the hardware struct
2097 * @enable: state to enter, either enabled or disabled
2098 *
2099 * enables/disables replication of packets across multiple pools.
2100 **/
2101 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2102 {
2103 u32 vt_ctl = rd32(E1000_VT_CTL);
2104
2105 if (enable)
2106 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2107 else
2108 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2109
2110 wr32(E1000_VT_CTL, vt_ctl);
2111 }
2112
2113 /**
2114 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2115 * @hw: pointer to the HW structure
2116 * @offset: register offset to be read
2117 * @data: pointer to the read data
2118 *
2119 * Reads the MDI control register in the PHY at offset and stores the
2120 * information read to data.
2121 **/
2122 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2123 {
2124 s32 ret_val;
2125
2126 ret_val = hw->phy.ops.acquire(hw);
2127 if (ret_val)
2128 goto out;
2129
2130 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2131
2132 hw->phy.ops.release(hw);
2133
2134 out:
2135 return ret_val;
2136 }
2137
2138 /**
2139 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2140 * @hw: pointer to the HW structure
2141 * @offset: register offset to write to
2142 * @data: data to write to register at offset
2143 *
2144 * Writes data to MDI control register in the PHY at offset.
2145 **/
2146 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2147 {
2148 s32 ret_val;
2149
2150
2151 ret_val = hw->phy.ops.acquire(hw);
2152 if (ret_val)
2153 goto out;
2154
2155 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2156
2157 hw->phy.ops.release(hw);
2158
2159 out:
2160 return ret_val;
2161 }
2162
2163 /**
2164 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2165 * @hw: pointer to the HW structure
2166 *
2167 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2168 * the values found in the EEPROM. This addresses an issue in which these
2169 * bits are not restored from EEPROM after reset.
2170 **/
2171 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2172 {
2173 s32 ret_val = 0;
2174 u32 mdicnfg;
2175 u16 nvm_data = 0;
2176
2177 if (hw->mac.type != e1000_82580)
2178 goto out;
2179 if (!igb_sgmii_active_82575(hw))
2180 goto out;
2181
2182 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2183 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2184 &nvm_data);
2185 if (ret_val) {
2186 hw_dbg("NVM Read Error\n");
2187 goto out;
2188 }
2189
2190 mdicnfg = rd32(E1000_MDICNFG);
2191 if (nvm_data & NVM_WORD24_EXT_MDIO)
2192 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2193 if (nvm_data & NVM_WORD24_COM_MDIO)
2194 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2195 wr32(E1000_MDICNFG, mdicnfg);
2196 out:
2197 return ret_val;
2198 }
2199
2200 /**
2201 * igb_reset_hw_82580 - Reset hardware
2202 * @hw: pointer to the HW structure
2203 *
2204 * This resets function or entire device (all ports, etc.)
2205 * to a known state.
2206 **/
2207 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2208 {
2209 s32 ret_val = 0;
2210 /* BH SW mailbox bit in SW_FW_SYNC */
2211 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2212 u32 ctrl;
2213 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2214
2215 hw->dev_spec._82575.global_device_reset = false;
2216
2217 /* due to hw errata, global device reset doesn't always
2218 * work on 82580
2219 */
2220 if (hw->mac.type == e1000_82580)
2221 global_device_reset = false;
2222
2223 /* Get current control state. */
2224 ctrl = rd32(E1000_CTRL);
2225
2226 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2227 * on the last TLP read/write transaction when MAC is reset.
2228 */
2229 ret_val = igb_disable_pcie_master(hw);
2230 if (ret_val)
2231 hw_dbg("PCI-E Master disable polling has failed.\n");
2232
2233 hw_dbg("Masking off all interrupts\n");
2234 wr32(E1000_IMC, 0xffffffff);
2235 wr32(E1000_RCTL, 0);
2236 wr32(E1000_TCTL, E1000_TCTL_PSP);
2237 wrfl();
2238
2239 usleep_range(10000, 11000);
2240
2241 /* Determine whether or not a global dev reset is requested */
2242 if (global_device_reset &&
2243 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2244 global_device_reset = false;
2245
2246 if (global_device_reset &&
2247 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2248 ctrl |= E1000_CTRL_DEV_RST;
2249 else
2250 ctrl |= E1000_CTRL_RST;
2251
2252 wr32(E1000_CTRL, ctrl);
2253 wrfl();
2254
2255 /* Add delay to insure DEV_RST has time to complete */
2256 if (global_device_reset)
2257 usleep_range(5000, 6000);
2258
2259 ret_val = igb_get_auto_rd_done(hw);
2260 if (ret_val) {
2261 /* When auto config read does not complete, do not
2262 * return with an error. This can happen in situations
2263 * where there is no eeprom and prevents getting link.
2264 */
2265 hw_dbg("Auto Read Done did not complete\n");
2266 }
2267
2268 /* clear global device reset status bit */
2269 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2270
2271 /* Clear any pending interrupt events. */
2272 wr32(E1000_IMC, 0xffffffff);
2273 rd32(E1000_ICR);
2274
2275 ret_val = igb_reset_mdicnfg_82580(hw);
2276 if (ret_val)
2277 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2278
2279 /* Install any alternate MAC address into RAR0 */
2280 ret_val = igb_check_alt_mac_addr(hw);
2281
2282 /* Release semaphore */
2283 if (global_device_reset)
2284 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2285
2286 return ret_val;
2287 }
2288
2289 /**
2290 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2291 * @data: data received by reading RXPBS register
2292 *
2293 * The 82580 uses a table based approach for packet buffer allocation sizes.
2294 * This function converts the retrieved value into the correct table value
2295 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2296 * 0x0 36 72 144 1 2 4 8 16
2297 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2298 */
2299 u16 igb_rxpbs_adjust_82580(u32 data)
2300 {
2301 u16 ret_val = 0;
2302
2303 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2304 ret_val = e1000_82580_rxpbs_table[data];
2305
2306 return ret_val;
2307 }
2308
2309 /**
2310 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2311 * checksum
2312 * @hw: pointer to the HW structure
2313 * @offset: offset in words of the checksum protected region
2314 *
2315 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2316 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2317 **/
2318 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2319 u16 offset)
2320 {
2321 s32 ret_val = 0;
2322 u16 checksum = 0;
2323 u16 i, nvm_data;
2324
2325 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2326 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2327 if (ret_val) {
2328 hw_dbg("NVM Read Error\n");
2329 goto out;
2330 }
2331 checksum += nvm_data;
2332 }
2333
2334 if (checksum != (u16) NVM_SUM) {
2335 hw_dbg("NVM Checksum Invalid\n");
2336 ret_val = -E1000_ERR_NVM;
2337 goto out;
2338 }
2339
2340 out:
2341 return ret_val;
2342 }
2343
2344 /**
2345 * igb_update_nvm_checksum_with_offset - Update EEPROM
2346 * checksum
2347 * @hw: pointer to the HW structure
2348 * @offset: offset in words of the checksum protected region
2349 *
2350 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2351 * up to the checksum. Then calculates the EEPROM checksum and writes the
2352 * value to the EEPROM.
2353 **/
2354 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2355 {
2356 s32 ret_val;
2357 u16 checksum = 0;
2358 u16 i, nvm_data;
2359
2360 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2361 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2362 if (ret_val) {
2363 hw_dbg("NVM Read Error while updating checksum.\n");
2364 goto out;
2365 }
2366 checksum += nvm_data;
2367 }
2368 checksum = (u16) NVM_SUM - checksum;
2369 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2370 &checksum);
2371 if (ret_val)
2372 hw_dbg("NVM Write Error while updating checksum.\n");
2373
2374 out:
2375 return ret_val;
2376 }
2377
2378 /**
2379 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2380 * @hw: pointer to the HW structure
2381 *
2382 * Calculates the EEPROM section checksum by reading/adding each word of
2383 * the EEPROM and then verifies that the sum of the EEPROM is
2384 * equal to 0xBABA.
2385 **/
2386 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2387 {
2388 s32 ret_val = 0;
2389 u16 eeprom_regions_count = 1;
2390 u16 j, nvm_data;
2391 u16 nvm_offset;
2392
2393 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2394 if (ret_val) {
2395 hw_dbg("NVM Read Error\n");
2396 goto out;
2397 }
2398
2399 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2400 /* if checksums compatibility bit is set validate checksums
2401 * for all 4 ports.
2402 */
2403 eeprom_regions_count = 4;
2404 }
2405
2406 for (j = 0; j < eeprom_regions_count; j++) {
2407 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2408 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2409 nvm_offset);
2410 if (ret_val != 0)
2411 goto out;
2412 }
2413
2414 out:
2415 return ret_val;
2416 }
2417
2418 /**
2419 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2420 * @hw: pointer to the HW structure
2421 *
2422 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2423 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2424 * checksum and writes the value to the EEPROM.
2425 **/
2426 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2427 {
2428 s32 ret_val;
2429 u16 j, nvm_data;
2430 u16 nvm_offset;
2431
2432 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2433 if (ret_val) {
2434 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2435 goto out;
2436 }
2437
2438 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2439 /* set compatibility bit to validate checksums appropriately */
2440 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2441 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2442 &nvm_data);
2443 if (ret_val) {
2444 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2445 goto out;
2446 }
2447 }
2448
2449 for (j = 0; j < 4; j++) {
2450 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2451 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2452 if (ret_val)
2453 goto out;
2454 }
2455
2456 out:
2457 return ret_val;
2458 }
2459
2460 /**
2461 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2462 * @hw: pointer to the HW structure
2463 *
2464 * Calculates the EEPROM section checksum by reading/adding each word of
2465 * the EEPROM and then verifies that the sum of the EEPROM is
2466 * equal to 0xBABA.
2467 **/
2468 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2469 {
2470 s32 ret_val = 0;
2471 u16 j;
2472 u16 nvm_offset;
2473
2474 for (j = 0; j < 4; j++) {
2475 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2476 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2477 nvm_offset);
2478 if (ret_val != 0)
2479 goto out;
2480 }
2481
2482 out:
2483 return ret_val;
2484 }
2485
2486 /**
2487 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2488 * @hw: pointer to the HW structure
2489 *
2490 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2491 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2492 * checksum and writes the value to the EEPROM.
2493 **/
2494 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2495 {
2496 s32 ret_val = 0;
2497 u16 j;
2498 u16 nvm_offset;
2499
2500 for (j = 0; j < 4; j++) {
2501 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2502 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2503 if (ret_val != 0)
2504 goto out;
2505 }
2506
2507 out:
2508 return ret_val;
2509 }
2510
2511 /**
2512 * __igb_access_emi_reg - Read/write EMI register
2513 * @hw: pointer to the HW structure
2514 * @addr: EMI address to program
2515 * @data: pointer to value to read/write from/to the EMI address
2516 * @read: boolean flag to indicate read or write
2517 **/
2518 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2519 u16 *data, bool read)
2520 {
2521 s32 ret_val = E1000_SUCCESS;
2522
2523 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2524 if (ret_val)
2525 return ret_val;
2526
2527 if (read)
2528 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2529 else
2530 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2531
2532 return ret_val;
2533 }
2534
2535 /**
2536 * igb_read_emi_reg - Read Extended Management Interface register
2537 * @hw: pointer to the HW structure
2538 * @addr: EMI address to program
2539 * @data: value to be read from the EMI address
2540 **/
2541 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2542 {
2543 return __igb_access_emi_reg(hw, addr, data, true);
2544 }
2545
2546 /**
2547 * igb_set_eee_i350 - Enable/disable EEE support
2548 * @hw: pointer to the HW structure
2549 *
2550 * Enable/disable EEE based on setting in dev_spec structure.
2551 *
2552 **/
2553 s32 igb_set_eee_i350(struct e1000_hw *hw)
2554 {
2555 s32 ret_val = 0;
2556 u32 ipcnfg, eeer;
2557
2558 if ((hw->mac.type < e1000_i350) ||
2559 (hw->phy.media_type != e1000_media_type_copper))
2560 goto out;
2561 ipcnfg = rd32(E1000_IPCNFG);
2562 eeer = rd32(E1000_EEER);
2563
2564 /* enable or disable per user setting */
2565 if (!(hw->dev_spec._82575.eee_disable)) {
2566 u32 eee_su = rd32(E1000_EEE_SU);
2567
2568 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2569 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2570 E1000_EEER_LPI_FC);
2571
2572 /* This bit should not be set in normal operation. */
2573 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2574 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2575
2576 } else {
2577 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2578 E1000_IPCNFG_EEE_100M_AN);
2579 eeer &= ~(E1000_EEER_TX_LPI_EN |
2580 E1000_EEER_RX_LPI_EN |
2581 E1000_EEER_LPI_FC);
2582 }
2583 wr32(E1000_IPCNFG, ipcnfg);
2584 wr32(E1000_EEER, eeer);
2585 rd32(E1000_IPCNFG);
2586 rd32(E1000_EEER);
2587 out:
2588
2589 return ret_val;
2590 }
2591
2592 /**
2593 * igb_set_eee_i354 - Enable/disable EEE support
2594 * @hw: pointer to the HW structure
2595 *
2596 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2597 *
2598 **/
2599 s32 igb_set_eee_i354(struct e1000_hw *hw)
2600 {
2601 struct e1000_phy_info *phy = &hw->phy;
2602 s32 ret_val = 0;
2603 u16 phy_data;
2604
2605 if ((hw->phy.media_type != e1000_media_type_copper) ||
2606 (phy->id != M88E1543_E_PHY_ID))
2607 goto out;
2608
2609 if (!hw->dev_spec._82575.eee_disable) {
2610 /* Switch to PHY page 18. */
2611 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2612 if (ret_val)
2613 goto out;
2614
2615 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2616 &phy_data);
2617 if (ret_val)
2618 goto out;
2619
2620 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2621 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2622 phy_data);
2623 if (ret_val)
2624 goto out;
2625
2626 /* Return the PHY to page 0. */
2627 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2628 if (ret_val)
2629 goto out;
2630
2631 /* Turn on EEE advertisement. */
2632 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2633 E1000_EEE_ADV_DEV_I354,
2634 &phy_data);
2635 if (ret_val)
2636 goto out;
2637
2638 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2639 E1000_EEE_ADV_1000_SUPPORTED;
2640 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2641 E1000_EEE_ADV_DEV_I354,
2642 phy_data);
2643 } else {
2644 /* Turn off EEE advertisement. */
2645 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2646 E1000_EEE_ADV_DEV_I354,
2647 &phy_data);
2648 if (ret_val)
2649 goto out;
2650
2651 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2652 E1000_EEE_ADV_1000_SUPPORTED);
2653 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2654 E1000_EEE_ADV_DEV_I354,
2655 phy_data);
2656 }
2657
2658 out:
2659 return ret_val;
2660 }
2661
2662 /**
2663 * igb_get_eee_status_i354 - Get EEE status
2664 * @hw: pointer to the HW structure
2665 * @status: EEE status
2666 *
2667 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2668 * been received.
2669 **/
2670 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2671 {
2672 struct e1000_phy_info *phy = &hw->phy;
2673 s32 ret_val = 0;
2674 u16 phy_data;
2675
2676 /* Check if EEE is supported on this device. */
2677 if ((hw->phy.media_type != e1000_media_type_copper) ||
2678 (phy->id != M88E1543_E_PHY_ID))
2679 goto out;
2680
2681 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2682 E1000_PCS_STATUS_DEV_I354,
2683 &phy_data);
2684 if (ret_val)
2685 goto out;
2686
2687 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2688 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2689
2690 out:
2691 return ret_val;
2692 }
2693
2694 static const u8 e1000_emc_temp_data[4] = {
2695 E1000_EMC_INTERNAL_DATA,
2696 E1000_EMC_DIODE1_DATA,
2697 E1000_EMC_DIODE2_DATA,
2698 E1000_EMC_DIODE3_DATA
2699 };
2700 static const u8 e1000_emc_therm_limit[4] = {
2701 E1000_EMC_INTERNAL_THERM_LIMIT,
2702 E1000_EMC_DIODE1_THERM_LIMIT,
2703 E1000_EMC_DIODE2_THERM_LIMIT,
2704 E1000_EMC_DIODE3_THERM_LIMIT
2705 };
2706
2707 #ifdef CONFIG_IGB_HWMON
2708 /**
2709 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2710 * @hw: pointer to hardware structure
2711 *
2712 * Updates the temperatures in mac.thermal_sensor_data
2713 **/
2714 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2715 {
2716 s32 status = E1000_SUCCESS;
2717 u16 ets_offset;
2718 u16 ets_cfg;
2719 u16 ets_sensor;
2720 u8 num_sensors;
2721 u8 sensor_index;
2722 u8 sensor_location;
2723 u8 i;
2724 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2725
2726 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2727 return E1000_NOT_IMPLEMENTED;
2728
2729 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2730
2731 /* Return the internal sensor only if ETS is unsupported */
2732 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2733 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2734 return status;
2735
2736 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2737 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2738 != NVM_ETS_TYPE_EMC)
2739 return E1000_NOT_IMPLEMENTED;
2740
2741 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2742 if (num_sensors > E1000_MAX_SENSORS)
2743 num_sensors = E1000_MAX_SENSORS;
2744
2745 for (i = 1; i < num_sensors; i++) {
2746 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2747 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2748 NVM_ETS_DATA_INDEX_SHIFT);
2749 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2750 NVM_ETS_DATA_LOC_SHIFT);
2751
2752 if (sensor_location != 0)
2753 hw->phy.ops.read_i2c_byte(hw,
2754 e1000_emc_temp_data[sensor_index],
2755 E1000_I2C_THERMAL_SENSOR_ADDR,
2756 &data->sensor[i].temp);
2757 }
2758 return status;
2759 }
2760
2761 /**
2762 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2763 * @hw: pointer to hardware structure
2764 *
2765 * Sets the thermal sensor thresholds according to the NVM map
2766 * and save off the threshold and location values into mac.thermal_sensor_data
2767 **/
2768 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2769 {
2770 s32 status = E1000_SUCCESS;
2771 u16 ets_offset;
2772 u16 ets_cfg;
2773 u16 ets_sensor;
2774 u8 low_thresh_delta;
2775 u8 num_sensors;
2776 u8 sensor_index;
2777 u8 sensor_location;
2778 u8 therm_limit;
2779 u8 i;
2780 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2781
2782 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2783 return E1000_NOT_IMPLEMENTED;
2784
2785 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2786
2787 data->sensor[0].location = 0x1;
2788 data->sensor[0].caution_thresh =
2789 (rd32(E1000_THHIGHTC) & 0xFF);
2790 data->sensor[0].max_op_thresh =
2791 (rd32(E1000_THLOWTC) & 0xFF);
2792
2793 /* Return the internal sensor only if ETS is unsupported */
2794 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2795 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2796 return status;
2797
2798 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2799 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2800 != NVM_ETS_TYPE_EMC)
2801 return E1000_NOT_IMPLEMENTED;
2802
2803 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2804 NVM_ETS_LTHRES_DELTA_SHIFT);
2805 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2806
2807 for (i = 1; i <= num_sensors; i++) {
2808 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2809 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2810 NVM_ETS_DATA_INDEX_SHIFT);
2811 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2812 NVM_ETS_DATA_LOC_SHIFT);
2813 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2814
2815 hw->phy.ops.write_i2c_byte(hw,
2816 e1000_emc_therm_limit[sensor_index],
2817 E1000_I2C_THERMAL_SENSOR_ADDR,
2818 therm_limit);
2819
2820 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2821 data->sensor[i].location = sensor_location;
2822 data->sensor[i].caution_thresh = therm_limit;
2823 data->sensor[i].max_op_thresh = therm_limit -
2824 low_thresh_delta;
2825 }
2826 }
2827 return status;
2828 }
2829
2830 #endif
2831 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2832 .init_hw = igb_init_hw_82575,
2833 .check_for_link = igb_check_for_link_82575,
2834 .rar_set = igb_rar_set,
2835 .read_mac_addr = igb_read_mac_addr_82575,
2836 .get_speed_and_duplex = igb_get_link_up_info_82575,
2837 #ifdef CONFIG_IGB_HWMON
2838 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2839 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2840 #endif
2841 };
2842
2843 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2844 .acquire = igb_acquire_phy_82575,
2845 .get_cfg_done = igb_get_cfg_done_82575,
2846 .release = igb_release_phy_82575,
2847 .write_i2c_byte = igb_write_i2c_byte,
2848 .read_i2c_byte = igb_read_i2c_byte,
2849 };
2850
2851 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2852 .acquire = igb_acquire_nvm_82575,
2853 .read = igb_read_nvm_eerd,
2854 .release = igb_release_nvm_82575,
2855 .write = igb_write_nvm_spi,
2856 };
2857
2858 const struct e1000_info e1000_82575_info = {
2859 .get_invariants = igb_get_invariants_82575,
2860 .mac_ops = &e1000_mac_ops_82575,
2861 .phy_ops = &e1000_phy_ops_82575,
2862 .nvm_ops = &e1000_nvm_ops_82575,
2863 };
2864
Linux kernel - Deliverables
This page took 0.146742 seconds and 5 git commands to generate.