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igb: Update license text to remove FSF address and update copyright.
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25 *******************************************************************************/
26
27 /* e1000_82575
28 * e1000_82576
29 */
30
31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
33 #include <linux/types.h>
34 #include <linux/if_ether.h>
35 #include <linux/i2c.h>
36
37 #include "e1000_mac.h"
38 #include "e1000_82575.h"
39 #include "e1000_i210.h"
40
41 static s32 igb_get_invariants_82575(struct e1000_hw *);
42 static s32 igb_acquire_phy_82575(struct e1000_hw *);
43 static void igb_release_phy_82575(struct e1000_hw *);
44 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
45 static void igb_release_nvm_82575(struct e1000_hw *);
46 static s32 igb_check_for_link_82575(struct e1000_hw *);
47 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
48 static s32 igb_init_hw_82575(struct e1000_hw *);
49 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
50 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
51 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
52 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
53 static s32 igb_reset_hw_82575(struct e1000_hw *);
54 static s32 igb_reset_hw_82580(struct e1000_hw *);
55 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
56 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
57 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
58 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
59 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
60 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
61 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
62 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
63 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
64 u16 *);
65 static s32 igb_get_phy_id_82575(struct e1000_hw *);
66 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
67 static bool igb_sgmii_active_82575(struct e1000_hw *);
68 static s32 igb_reset_init_script_82575(struct e1000_hw *);
69 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
70 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
71 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
72 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
73 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
74 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
75 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
76 static const u16 e1000_82580_rxpbs_table[] =
77 { 36, 72, 144, 1, 2, 4, 8, 16,
78 35, 70, 140 };
79 #define E1000_82580_RXPBS_TABLE_SIZE \
80 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
81
82 /**
83 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
84 * @hw: pointer to the HW structure
85 *
86 * Called to determine if the I2C pins are being used for I2C or as an
87 * external MDIO interface since the two options are mutually exclusive.
88 **/
89 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
90 {
91 u32 reg = 0;
92 bool ext_mdio = false;
93
94 switch (hw->mac.type) {
95 case e1000_82575:
96 case e1000_82576:
97 reg = rd32(E1000_MDIC);
98 ext_mdio = !!(reg & E1000_MDIC_DEST);
99 break;
100 case e1000_82580:
101 case e1000_i350:
102 case e1000_i354:
103 case e1000_i210:
104 case e1000_i211:
105 reg = rd32(E1000_MDICNFG);
106 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
107 break;
108 default:
109 break;
110 }
111 return ext_mdio;
112 }
113
114 /**
115 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
116 * @hw: pointer to the HW structure
117 *
118 * Poll the M88E1112 interfaces to see which interface achieved link.
119 */
120 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
121 {
122 struct e1000_phy_info *phy = &hw->phy;
123 s32 ret_val;
124 u16 data;
125 u8 port = 0;
126
127 /* Check the copper medium. */
128 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
129 if (ret_val)
130 return ret_val;
131
132 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
133 if (ret_val)
134 return ret_val;
135
136 if (data & E1000_M88E1112_STATUS_LINK)
137 port = E1000_MEDIA_PORT_COPPER;
138
139 /* Check the other medium. */
140 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
141 if (ret_val)
142 return ret_val;
143
144 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
145 if (ret_val)
146 return ret_val;
147
148 /* reset page to 0 */
149 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
150 if (ret_val)
151 return ret_val;
152
153 if (data & E1000_M88E1112_STATUS_LINK)
154 port = E1000_MEDIA_PORT_OTHER;
155
156 /* Determine if a swap needs to happen. */
157 if (port && (hw->dev_spec._82575.media_port != port)) {
158 hw->dev_spec._82575.media_port = port;
159 hw->dev_spec._82575.media_changed = true;
160 } else {
161 ret_val = igb_check_for_link_82575(hw);
162 }
163
164 return E1000_SUCCESS;
165 }
166
167 /**
168 * igb_init_phy_params_82575 - Init PHY func ptrs.
169 * @hw: pointer to the HW structure
170 **/
171 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
172 {
173 struct e1000_phy_info *phy = &hw->phy;
174 s32 ret_val = 0;
175 u32 ctrl_ext;
176
177 if (hw->phy.media_type != e1000_media_type_copper) {
178 phy->type = e1000_phy_none;
179 goto out;
180 }
181
182 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
183 phy->reset_delay_us = 100;
184
185 ctrl_ext = rd32(E1000_CTRL_EXT);
186
187 if (igb_sgmii_active_82575(hw)) {
188 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
189 ctrl_ext |= E1000_CTRL_I2C_ENA;
190 } else {
191 phy->ops.reset = igb_phy_hw_reset;
192 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
193 }
194
195 wr32(E1000_CTRL_EXT, ctrl_ext);
196 igb_reset_mdicnfg_82580(hw);
197
198 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
199 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
200 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
201 } else {
202 switch (hw->mac.type) {
203 case e1000_82580:
204 case e1000_i350:
205 case e1000_i354:
206 phy->ops.read_reg = igb_read_phy_reg_82580;
207 phy->ops.write_reg = igb_write_phy_reg_82580;
208 break;
209 case e1000_i210:
210 case e1000_i211:
211 phy->ops.read_reg = igb_read_phy_reg_gs40g;
212 phy->ops.write_reg = igb_write_phy_reg_gs40g;
213 break;
214 default:
215 phy->ops.read_reg = igb_read_phy_reg_igp;
216 phy->ops.write_reg = igb_write_phy_reg_igp;
217 }
218 }
219
220 /* set lan id */
221 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
222 E1000_STATUS_FUNC_SHIFT;
223
224 /* Set phy->phy_addr and phy->id. */
225 ret_val = igb_get_phy_id_82575(hw);
226 if (ret_val)
227 return ret_val;
228
229 /* Verify phy id and set remaining function pointers */
230 switch (phy->id) {
231 case M88E1543_E_PHY_ID:
232 case I347AT4_E_PHY_ID:
233 case M88E1112_E_PHY_ID:
234 case M88E1111_I_PHY_ID:
235 phy->type = e1000_phy_m88;
236 phy->ops.check_polarity = igb_check_polarity_m88;
237 phy->ops.get_phy_info = igb_get_phy_info_m88;
238 if (phy->id != M88E1111_I_PHY_ID)
239 phy->ops.get_cable_length =
240 igb_get_cable_length_m88_gen2;
241 else
242 phy->ops.get_cable_length = igb_get_cable_length_m88;
243 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
244 /* Check if this PHY is confgured for media swap. */
245 if (phy->id == M88E1112_E_PHY_ID) {
246 u16 data;
247
248 ret_val = phy->ops.write_reg(hw,
249 E1000_M88E1112_PAGE_ADDR,
250 2);
251 if (ret_val)
252 goto out;
253
254 ret_val = phy->ops.read_reg(hw,
255 E1000_M88E1112_MAC_CTRL_1,
256 &data);
257 if (ret_val)
258 goto out;
259
260 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
261 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
262 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
263 data == E1000_M88E1112_AUTO_COPPER_BASEX)
264 hw->mac.ops.check_for_link =
265 igb_check_for_link_media_swap;
266 }
267 break;
268 case IGP03E1000_E_PHY_ID:
269 phy->type = e1000_phy_igp_3;
270 phy->ops.get_phy_info = igb_get_phy_info_igp;
271 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
272 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
273 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
274 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
275 break;
276 case I82580_I_PHY_ID:
277 case I350_I_PHY_ID:
278 phy->type = e1000_phy_82580;
279 phy->ops.force_speed_duplex =
280 igb_phy_force_speed_duplex_82580;
281 phy->ops.get_cable_length = igb_get_cable_length_82580;
282 phy->ops.get_phy_info = igb_get_phy_info_82580;
283 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
284 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
285 break;
286 case I210_I_PHY_ID:
287 phy->type = e1000_phy_i210;
288 phy->ops.check_polarity = igb_check_polarity_m88;
289 phy->ops.get_phy_info = igb_get_phy_info_m88;
290 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
291 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
292 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
293 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
294 break;
295 default:
296 ret_val = -E1000_ERR_PHY;
297 goto out;
298 }
299
300 out:
301 return ret_val;
302 }
303
304 /**
305 * igb_init_nvm_params_82575 - Init NVM func ptrs.
306 * @hw: pointer to the HW structure
307 **/
308 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
309 {
310 struct e1000_nvm_info *nvm = &hw->nvm;
311 u32 eecd = rd32(E1000_EECD);
312 u16 size;
313
314 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
315 E1000_EECD_SIZE_EX_SHIFT);
316
317 /* Added to a constant, "size" becomes the left-shift value
318 * for setting word_size.
319 */
320 size += NVM_WORD_SIZE_BASE_SHIFT;
321
322 /* Just in case size is out of range, cap it to the largest
323 * EEPROM size supported
324 */
325 if (size > 15)
326 size = 15;
327
328 nvm->word_size = 1 << size;
329 nvm->opcode_bits = 8;
330 nvm->delay_usec = 1;
331
332 switch (nvm->override) {
333 case e1000_nvm_override_spi_large:
334 nvm->page_size = 32;
335 nvm->address_bits = 16;
336 break;
337 case e1000_nvm_override_spi_small:
338 nvm->page_size = 8;
339 nvm->address_bits = 8;
340 break;
341 default:
342 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
343 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
344 16 : 8;
345 break;
346 }
347 if (nvm->word_size == (1 << 15))
348 nvm->page_size = 128;
349
350 nvm->type = e1000_nvm_eeprom_spi;
351
352 /* NVM Function Pointers */
353 nvm->ops.acquire = igb_acquire_nvm_82575;
354 nvm->ops.release = igb_release_nvm_82575;
355 nvm->ops.write = igb_write_nvm_spi;
356 nvm->ops.validate = igb_validate_nvm_checksum;
357 nvm->ops.update = igb_update_nvm_checksum;
358 if (nvm->word_size < (1 << 15))
359 nvm->ops.read = igb_read_nvm_eerd;
360 else
361 nvm->ops.read = igb_read_nvm_spi;
362
363 /* override generic family function pointers for specific descendants */
364 switch (hw->mac.type) {
365 case e1000_82580:
366 nvm->ops.validate = igb_validate_nvm_checksum_82580;
367 nvm->ops.update = igb_update_nvm_checksum_82580;
368 break;
369 case e1000_i354:
370 case e1000_i350:
371 nvm->ops.validate = igb_validate_nvm_checksum_i350;
372 nvm->ops.update = igb_update_nvm_checksum_i350;
373 break;
374 default:
375 break;
376 }
377
378 return 0;
379 }
380
381 /**
382 * igb_init_mac_params_82575 - Init MAC func ptrs.
383 * @hw: pointer to the HW structure
384 **/
385 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
386 {
387 struct e1000_mac_info *mac = &hw->mac;
388 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
389
390 /* Set mta register count */
391 mac->mta_reg_count = 128;
392 /* Set rar entry count */
393 switch (mac->type) {
394 case e1000_82576:
395 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
396 break;
397 case e1000_82580:
398 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
399 break;
400 case e1000_i350:
401 case e1000_i354:
402 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
403 break;
404 default:
405 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
406 break;
407 }
408 /* reset */
409 if (mac->type >= e1000_82580)
410 mac->ops.reset_hw = igb_reset_hw_82580;
411 else
412 mac->ops.reset_hw = igb_reset_hw_82575;
413
414 if (mac->type >= e1000_i210) {
415 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
416 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
417
418 } else {
419 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
420 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
421 }
422
423 /* Set if part includes ASF firmware */
424 mac->asf_firmware_present = true;
425 /* Set if manageability features are enabled. */
426 mac->arc_subsystem_valid =
427 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
428 ? true : false;
429 /* enable EEE on i350 parts and later parts */
430 if (mac->type >= e1000_i350)
431 dev_spec->eee_disable = false;
432 else
433 dev_spec->eee_disable = true;
434 /* Allow a single clear of the SW semaphore on I210 and newer */
435 if (mac->type >= e1000_i210)
436 dev_spec->clear_semaphore_once = true;
437 /* physical interface link setup */
438 mac->ops.setup_physical_interface =
439 (hw->phy.media_type == e1000_media_type_copper)
440 ? igb_setup_copper_link_82575
441 : igb_setup_serdes_link_82575;
442
443 if (mac->type == e1000_82580) {
444 switch (hw->device_id) {
445 /* feature not supported on these id's */
446 case E1000_DEV_ID_DH89XXCC_SGMII:
447 case E1000_DEV_ID_DH89XXCC_SERDES:
448 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
449 case E1000_DEV_ID_DH89XXCC_SFP:
450 break;
451 default:
452 hw->dev_spec._82575.mas_capable = true;
453 break;
454 }
455 }
456 return 0;
457 }
458
459 /**
460 * igb_set_sfp_media_type_82575 - derives SFP module media type.
461 * @hw: pointer to the HW structure
462 *
463 * The media type is chosen based on SFP module.
464 * compatibility flags retrieved from SFP ID EEPROM.
465 **/
466 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
467 {
468 s32 ret_val = E1000_ERR_CONFIG;
469 u32 ctrl_ext = 0;
470 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
471 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
472 u8 tranceiver_type = 0;
473 s32 timeout = 3;
474
475 /* Turn I2C interface ON and power on sfp cage */
476 ctrl_ext = rd32(E1000_CTRL_EXT);
477 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
478 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
479
480 wrfl();
481
482 /* Read SFP module data */
483 while (timeout) {
484 ret_val = igb_read_sfp_data_byte(hw,
485 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
486 &tranceiver_type);
487 if (ret_val == 0)
488 break;
489 msleep(100);
490 timeout--;
491 }
492 if (ret_val != 0)
493 goto out;
494
495 ret_val = igb_read_sfp_data_byte(hw,
496 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
497 (u8 *)eth_flags);
498 if (ret_val != 0)
499 goto out;
500
501 /* Check if there is some SFP module plugged and powered */
502 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
503 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
504 dev_spec->module_plugged = true;
505 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
506 hw->phy.media_type = e1000_media_type_internal_serdes;
507 } else if (eth_flags->e100_base_fx) {
508 dev_spec->sgmii_active = true;
509 hw->phy.media_type = e1000_media_type_internal_serdes;
510 } else if (eth_flags->e1000_base_t) {
511 dev_spec->sgmii_active = true;
512 hw->phy.media_type = e1000_media_type_copper;
513 } else {
514 hw->phy.media_type = e1000_media_type_unknown;
515 hw_dbg("PHY module has not been recognized\n");
516 goto out;
517 }
518 } else {
519 hw->phy.media_type = e1000_media_type_unknown;
520 }
521 ret_val = 0;
522 out:
523 /* Restore I2C interface setting */
524 wr32(E1000_CTRL_EXT, ctrl_ext);
525 return ret_val;
526 }
527
528 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
529 {
530 struct e1000_mac_info *mac = &hw->mac;
531 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
532 s32 ret_val;
533 u32 ctrl_ext = 0;
534 u32 link_mode = 0;
535
536 switch (hw->device_id) {
537 case E1000_DEV_ID_82575EB_COPPER:
538 case E1000_DEV_ID_82575EB_FIBER_SERDES:
539 case E1000_DEV_ID_82575GB_QUAD_COPPER:
540 mac->type = e1000_82575;
541 break;
542 case E1000_DEV_ID_82576:
543 case E1000_DEV_ID_82576_NS:
544 case E1000_DEV_ID_82576_NS_SERDES:
545 case E1000_DEV_ID_82576_FIBER:
546 case E1000_DEV_ID_82576_SERDES:
547 case E1000_DEV_ID_82576_QUAD_COPPER:
548 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
549 case E1000_DEV_ID_82576_SERDES_QUAD:
550 mac->type = e1000_82576;
551 break;
552 case E1000_DEV_ID_82580_COPPER:
553 case E1000_DEV_ID_82580_FIBER:
554 case E1000_DEV_ID_82580_QUAD_FIBER:
555 case E1000_DEV_ID_82580_SERDES:
556 case E1000_DEV_ID_82580_SGMII:
557 case E1000_DEV_ID_82580_COPPER_DUAL:
558 case E1000_DEV_ID_DH89XXCC_SGMII:
559 case E1000_DEV_ID_DH89XXCC_SERDES:
560 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
561 case E1000_DEV_ID_DH89XXCC_SFP:
562 mac->type = e1000_82580;
563 break;
564 case E1000_DEV_ID_I350_COPPER:
565 case E1000_DEV_ID_I350_FIBER:
566 case E1000_DEV_ID_I350_SERDES:
567 case E1000_DEV_ID_I350_SGMII:
568 mac->type = e1000_i350;
569 break;
570 case E1000_DEV_ID_I210_COPPER:
571 case E1000_DEV_ID_I210_FIBER:
572 case E1000_DEV_ID_I210_SERDES:
573 case E1000_DEV_ID_I210_SGMII:
574 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
575 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
576 mac->type = e1000_i210;
577 break;
578 case E1000_DEV_ID_I211_COPPER:
579 mac->type = e1000_i211;
580 break;
581 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
582 case E1000_DEV_ID_I354_SGMII:
583 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
584 mac->type = e1000_i354;
585 break;
586 default:
587 return -E1000_ERR_MAC_INIT;
588 break;
589 }
590
591 /* Set media type */
592 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
593 * based on the EEPROM. We cannot rely upon device ID. There
594 * is no distinguishable difference between fiber and internal
595 * SerDes mode on the 82575. There can be an external PHY attached
596 * on the SGMII interface. For this, we'll set sgmii_active to true.
597 */
598 hw->phy.media_type = e1000_media_type_copper;
599 dev_spec->sgmii_active = false;
600 dev_spec->module_plugged = false;
601
602 ctrl_ext = rd32(E1000_CTRL_EXT);
603
604 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
605 switch (link_mode) {
606 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
607 hw->phy.media_type = e1000_media_type_internal_serdes;
608 break;
609 case E1000_CTRL_EXT_LINK_MODE_SGMII:
610 /* Get phy control interface type set (MDIO vs. I2C)*/
611 if (igb_sgmii_uses_mdio_82575(hw)) {
612 hw->phy.media_type = e1000_media_type_copper;
613 dev_spec->sgmii_active = true;
614 break;
615 }
616 /* fall through for I2C based SGMII */
617 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
618 /* read media type from SFP EEPROM */
619 ret_val = igb_set_sfp_media_type_82575(hw);
620 if ((ret_val != 0) ||
621 (hw->phy.media_type == e1000_media_type_unknown)) {
622 /* If media type was not identified then return media
623 * type defined by the CTRL_EXT settings.
624 */
625 hw->phy.media_type = e1000_media_type_internal_serdes;
626
627 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
628 hw->phy.media_type = e1000_media_type_copper;
629 dev_spec->sgmii_active = true;
630 }
631
632 break;
633 }
634
635 /* do not change link mode for 100BaseFX */
636 if (dev_spec->eth_flags.e100_base_fx)
637 break;
638
639 /* change current link mode setting */
640 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
641
642 if (hw->phy.media_type == e1000_media_type_copper)
643 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
644 else
645 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
646
647 wr32(E1000_CTRL_EXT, ctrl_ext);
648
649 break;
650 default:
651 break;
652 }
653
654 /* mac initialization and operations */
655 ret_val = igb_init_mac_params_82575(hw);
656 if (ret_val)
657 goto out;
658
659 /* NVM initialization */
660 ret_val = igb_init_nvm_params_82575(hw);
661 switch (hw->mac.type) {
662 case e1000_i210:
663 case e1000_i211:
664 ret_val = igb_init_nvm_params_i210(hw);
665 break;
666 default:
667 break;
668 }
669
670 if (ret_val)
671 goto out;
672
673 /* if part supports SR-IOV then initialize mailbox parameters */
674 switch (mac->type) {
675 case e1000_82576:
676 case e1000_i350:
677 igb_init_mbx_params_pf(hw);
678 break;
679 default:
680 break;
681 }
682
683 /* setup PHY parameters */
684 ret_val = igb_init_phy_params_82575(hw);
685
686 out:
687 return ret_val;
688 }
689
690 /**
691 * igb_acquire_phy_82575 - Acquire rights to access PHY
692 * @hw: pointer to the HW structure
693 *
694 * Acquire access rights to the correct PHY. This is a
695 * function pointer entry point called by the api module.
696 **/
697 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
698 {
699 u16 mask = E1000_SWFW_PHY0_SM;
700
701 if (hw->bus.func == E1000_FUNC_1)
702 mask = E1000_SWFW_PHY1_SM;
703 else if (hw->bus.func == E1000_FUNC_2)
704 mask = E1000_SWFW_PHY2_SM;
705 else if (hw->bus.func == E1000_FUNC_3)
706 mask = E1000_SWFW_PHY3_SM;
707
708 return hw->mac.ops.acquire_swfw_sync(hw, mask);
709 }
710
711 /**
712 * igb_release_phy_82575 - Release rights to access PHY
713 * @hw: pointer to the HW structure
714 *
715 * A wrapper to release access rights to the correct PHY. This is a
716 * function pointer entry point called by the api module.
717 **/
718 static void igb_release_phy_82575(struct e1000_hw *hw)
719 {
720 u16 mask = E1000_SWFW_PHY0_SM;
721
722 if (hw->bus.func == E1000_FUNC_1)
723 mask = E1000_SWFW_PHY1_SM;
724 else if (hw->bus.func == E1000_FUNC_2)
725 mask = E1000_SWFW_PHY2_SM;
726 else if (hw->bus.func == E1000_FUNC_3)
727 mask = E1000_SWFW_PHY3_SM;
728
729 hw->mac.ops.release_swfw_sync(hw, mask);
730 }
731
732 /**
733 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
734 * @hw: pointer to the HW structure
735 * @offset: register offset to be read
736 * @data: pointer to the read data
737 *
738 * Reads the PHY register at offset using the serial gigabit media independent
739 * interface and stores the retrieved information in data.
740 **/
741 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
742 u16 *data)
743 {
744 s32 ret_val = -E1000_ERR_PARAM;
745
746 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
747 hw_dbg("PHY Address %u is out of range\n", offset);
748 goto out;
749 }
750
751 ret_val = hw->phy.ops.acquire(hw);
752 if (ret_val)
753 goto out;
754
755 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
756
757 hw->phy.ops.release(hw);
758
759 out:
760 return ret_val;
761 }
762
763 /**
764 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
765 * @hw: pointer to the HW structure
766 * @offset: register offset to write to
767 * @data: data to write at register offset
768 *
769 * Writes the data to PHY register at the offset using the serial gigabit
770 * media independent interface.
771 **/
772 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
773 u16 data)
774 {
775 s32 ret_val = -E1000_ERR_PARAM;
776
777
778 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
779 hw_dbg("PHY Address %d is out of range\n", offset);
780 goto out;
781 }
782
783 ret_val = hw->phy.ops.acquire(hw);
784 if (ret_val)
785 goto out;
786
787 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
788
789 hw->phy.ops.release(hw);
790
791 out:
792 return ret_val;
793 }
794
795 /**
796 * igb_get_phy_id_82575 - Retrieve PHY addr and id
797 * @hw: pointer to the HW structure
798 *
799 * Retrieves the PHY address and ID for both PHY's which do and do not use
800 * sgmi interface.
801 **/
802 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
803 {
804 struct e1000_phy_info *phy = &hw->phy;
805 s32 ret_val = 0;
806 u16 phy_id;
807 u32 ctrl_ext;
808 u32 mdic;
809
810 /* Extra read required for some PHY's on i354 */
811 if (hw->mac.type == e1000_i354)
812 igb_get_phy_id(hw);
813
814 /* For SGMII PHYs, we try the list of possible addresses until
815 * we find one that works. For non-SGMII PHYs
816 * (e.g. integrated copper PHYs), an address of 1 should
817 * work. The result of this function should mean phy->phy_addr
818 * and phy->id are set correctly.
819 */
820 if (!(igb_sgmii_active_82575(hw))) {
821 phy->addr = 1;
822 ret_val = igb_get_phy_id(hw);
823 goto out;
824 }
825
826 if (igb_sgmii_uses_mdio_82575(hw)) {
827 switch (hw->mac.type) {
828 case e1000_82575:
829 case e1000_82576:
830 mdic = rd32(E1000_MDIC);
831 mdic &= E1000_MDIC_PHY_MASK;
832 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
833 break;
834 case e1000_82580:
835 case e1000_i350:
836 case e1000_i354:
837 case e1000_i210:
838 case e1000_i211:
839 mdic = rd32(E1000_MDICNFG);
840 mdic &= E1000_MDICNFG_PHY_MASK;
841 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
842 break;
843 default:
844 ret_val = -E1000_ERR_PHY;
845 goto out;
846 break;
847 }
848 ret_val = igb_get_phy_id(hw);
849 goto out;
850 }
851
852 /* Power on sgmii phy if it is disabled */
853 ctrl_ext = rd32(E1000_CTRL_EXT);
854 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
855 wrfl();
856 msleep(300);
857
858 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
859 * Therefore, we need to test 1-7
860 */
861 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
862 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
863 if (ret_val == 0) {
864 hw_dbg("Vendor ID 0x%08X read at address %u\n",
865 phy_id, phy->addr);
866 /* At the time of this writing, The M88 part is
867 * the only supported SGMII PHY product.
868 */
869 if (phy_id == M88_VENDOR)
870 break;
871 } else {
872 hw_dbg("PHY address %u was unreadable\n", phy->addr);
873 }
874 }
875
876 /* A valid PHY type couldn't be found. */
877 if (phy->addr == 8) {
878 phy->addr = 0;
879 ret_val = -E1000_ERR_PHY;
880 goto out;
881 } else {
882 ret_val = igb_get_phy_id(hw);
883 }
884
885 /* restore previous sfp cage power state */
886 wr32(E1000_CTRL_EXT, ctrl_ext);
887
888 out:
889 return ret_val;
890 }
891
892 /**
893 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
894 * @hw: pointer to the HW structure
895 *
896 * Resets the PHY using the serial gigabit media independent interface.
897 **/
898 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
899 {
900 s32 ret_val;
901
902 /* This isn't a true "hard" reset, but is the only reset
903 * available to us at this time.
904 */
905
906 hw_dbg("Soft resetting SGMII attached PHY...\n");
907
908 /* SFP documentation requires the following to configure the SPF module
909 * to work on SGMII. No further documentation is given.
910 */
911 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
912 if (ret_val)
913 goto out;
914
915 ret_val = igb_phy_sw_reset(hw);
916
917 out:
918 return ret_val;
919 }
920
921 /**
922 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
923 * @hw: pointer to the HW structure
924 * @active: true to enable LPLU, false to disable
925 *
926 * Sets the LPLU D0 state according to the active flag. When
927 * activating LPLU this function also disables smart speed
928 * and vice versa. LPLU will not be activated unless the
929 * device autonegotiation advertisement meets standards of
930 * either 10 or 10/100 or 10/100/1000 at all duplexes.
931 * This is a function pointer entry point only called by
932 * PHY setup routines.
933 **/
934 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
935 {
936 struct e1000_phy_info *phy = &hw->phy;
937 s32 ret_val;
938 u16 data;
939
940 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
941 if (ret_val)
942 goto out;
943
944 if (active) {
945 data |= IGP02E1000_PM_D0_LPLU;
946 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
947 data);
948 if (ret_val)
949 goto out;
950
951 /* When LPLU is enabled, we should disable SmartSpeed */
952 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
953 &data);
954 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
955 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
956 data);
957 if (ret_val)
958 goto out;
959 } else {
960 data &= ~IGP02E1000_PM_D0_LPLU;
961 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
962 data);
963 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
964 * during Dx states where the power conservation is most
965 * important. During driver activity we should enable
966 * SmartSpeed, so performance is maintained.
967 */
968 if (phy->smart_speed == e1000_smart_speed_on) {
969 ret_val = phy->ops.read_reg(hw,
970 IGP01E1000_PHY_PORT_CONFIG, &data);
971 if (ret_val)
972 goto out;
973
974 data |= IGP01E1000_PSCFR_SMART_SPEED;
975 ret_val = phy->ops.write_reg(hw,
976 IGP01E1000_PHY_PORT_CONFIG, data);
977 if (ret_val)
978 goto out;
979 } else if (phy->smart_speed == e1000_smart_speed_off) {
980 ret_val = phy->ops.read_reg(hw,
981 IGP01E1000_PHY_PORT_CONFIG, &data);
982 if (ret_val)
983 goto out;
984
985 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
986 ret_val = phy->ops.write_reg(hw,
987 IGP01E1000_PHY_PORT_CONFIG, data);
988 if (ret_val)
989 goto out;
990 }
991 }
992
993 out:
994 return ret_val;
995 }
996
997 /**
998 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
999 * @hw: pointer to the HW structure
1000 * @active: true to enable LPLU, false to disable
1001 *
1002 * Sets the LPLU D0 state according to the active flag. When
1003 * activating LPLU this function also disables smart speed
1004 * and vice versa. LPLU will not be activated unless the
1005 * device autonegotiation advertisement meets standards of
1006 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1007 * This is a function pointer entry point only called by
1008 * PHY setup routines.
1009 **/
1010 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1011 {
1012 struct e1000_phy_info *phy = &hw->phy;
1013 s32 ret_val = 0;
1014 u16 data;
1015
1016 data = rd32(E1000_82580_PHY_POWER_MGMT);
1017
1018 if (active) {
1019 data |= E1000_82580_PM_D0_LPLU;
1020
1021 /* When LPLU is enabled, we should disable SmartSpeed */
1022 data &= ~E1000_82580_PM_SPD;
1023 } else {
1024 data &= ~E1000_82580_PM_D0_LPLU;
1025
1026 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1027 * during Dx states where the power conservation is most
1028 * important. During driver activity we should enable
1029 * SmartSpeed, so performance is maintained.
1030 */
1031 if (phy->smart_speed == e1000_smart_speed_on)
1032 data |= E1000_82580_PM_SPD;
1033 else if (phy->smart_speed == e1000_smart_speed_off)
1034 data &= ~E1000_82580_PM_SPD; }
1035
1036 wr32(E1000_82580_PHY_POWER_MGMT, data);
1037 return ret_val;
1038 }
1039
1040 /**
1041 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1042 * @hw: pointer to the HW structure
1043 * @active: boolean used to enable/disable lplu
1044 *
1045 * Success returns 0, Failure returns 1
1046 *
1047 * The low power link up (lplu) state is set to the power management level D3
1048 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1049 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1050 * is used during Dx states where the power conservation is most important.
1051 * During driver activity, SmartSpeed should be enabled so performance is
1052 * maintained.
1053 **/
1054 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1055 {
1056 struct e1000_phy_info *phy = &hw->phy;
1057 s32 ret_val = 0;
1058 u16 data;
1059
1060 data = rd32(E1000_82580_PHY_POWER_MGMT);
1061
1062 if (!active) {
1063 data &= ~E1000_82580_PM_D3_LPLU;
1064 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1065 * during Dx states where the power conservation is most
1066 * important. During driver activity we should enable
1067 * SmartSpeed, so performance is maintained.
1068 */
1069 if (phy->smart_speed == e1000_smart_speed_on)
1070 data |= E1000_82580_PM_SPD;
1071 else if (phy->smart_speed == e1000_smart_speed_off)
1072 data &= ~E1000_82580_PM_SPD;
1073 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1074 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1075 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1076 data |= E1000_82580_PM_D3_LPLU;
1077 /* When LPLU is enabled, we should disable SmartSpeed */
1078 data &= ~E1000_82580_PM_SPD;
1079 }
1080
1081 wr32(E1000_82580_PHY_POWER_MGMT, data);
1082 return ret_val;
1083 }
1084
1085 /**
1086 * igb_acquire_nvm_82575 - Request for access to EEPROM
1087 * @hw: pointer to the HW structure
1088 *
1089 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1090 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1091 * Return successful if access grant bit set, else clear the request for
1092 * EEPROM access and return -E1000_ERR_NVM (-1).
1093 **/
1094 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1095 {
1096 s32 ret_val;
1097
1098 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1099 if (ret_val)
1100 goto out;
1101
1102 ret_val = igb_acquire_nvm(hw);
1103
1104 if (ret_val)
1105 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1106
1107 out:
1108 return ret_val;
1109 }
1110
1111 /**
1112 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1113 * @hw: pointer to the HW structure
1114 *
1115 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1116 * then release the semaphores acquired.
1117 **/
1118 static void igb_release_nvm_82575(struct e1000_hw *hw)
1119 {
1120 igb_release_nvm(hw);
1121 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1122 }
1123
1124 /**
1125 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1126 * @hw: pointer to the HW structure
1127 * @mask: specifies which semaphore to acquire
1128 *
1129 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1130 * will also specify which port we're acquiring the lock for.
1131 **/
1132 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1133 {
1134 u32 swfw_sync;
1135 u32 swmask = mask;
1136 u32 fwmask = mask << 16;
1137 s32 ret_val = 0;
1138 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1139
1140 while (i < timeout) {
1141 if (igb_get_hw_semaphore(hw)) {
1142 ret_val = -E1000_ERR_SWFW_SYNC;
1143 goto out;
1144 }
1145
1146 swfw_sync = rd32(E1000_SW_FW_SYNC);
1147 if (!(swfw_sync & (fwmask | swmask)))
1148 break;
1149
1150 /* Firmware currently using resource (fwmask)
1151 * or other software thread using resource (swmask)
1152 */
1153 igb_put_hw_semaphore(hw);
1154 mdelay(5);
1155 i++;
1156 }
1157
1158 if (i == timeout) {
1159 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1160 ret_val = -E1000_ERR_SWFW_SYNC;
1161 goto out;
1162 }
1163
1164 swfw_sync |= swmask;
1165 wr32(E1000_SW_FW_SYNC, swfw_sync);
1166
1167 igb_put_hw_semaphore(hw);
1168
1169 out:
1170 return ret_val;
1171 }
1172
1173 /**
1174 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1175 * @hw: pointer to the HW structure
1176 * @mask: specifies which semaphore to acquire
1177 *
1178 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1179 * will also specify which port we're releasing the lock for.
1180 **/
1181 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1182 {
1183 u32 swfw_sync;
1184
1185 while (igb_get_hw_semaphore(hw) != 0);
1186 /* Empty */
1187
1188 swfw_sync = rd32(E1000_SW_FW_SYNC);
1189 swfw_sync &= ~mask;
1190 wr32(E1000_SW_FW_SYNC, swfw_sync);
1191
1192 igb_put_hw_semaphore(hw);
1193 }
1194
1195 /**
1196 * igb_get_cfg_done_82575 - Read config done bit
1197 * @hw: pointer to the HW structure
1198 *
1199 * Read the management control register for the config done bit for
1200 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1201 * to read the config done bit, so an error is *ONLY* logged and returns
1202 * 0. If we were to return with error, EEPROM-less silicon
1203 * would not be able to be reset or change link.
1204 **/
1205 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1206 {
1207 s32 timeout = PHY_CFG_TIMEOUT;
1208 s32 ret_val = 0;
1209 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1210
1211 if (hw->bus.func == 1)
1212 mask = E1000_NVM_CFG_DONE_PORT_1;
1213 else if (hw->bus.func == E1000_FUNC_2)
1214 mask = E1000_NVM_CFG_DONE_PORT_2;
1215 else if (hw->bus.func == E1000_FUNC_3)
1216 mask = E1000_NVM_CFG_DONE_PORT_3;
1217
1218 while (timeout) {
1219 if (rd32(E1000_EEMNGCTL) & mask)
1220 break;
1221 msleep(1);
1222 timeout--;
1223 }
1224 if (!timeout)
1225 hw_dbg("MNG configuration cycle has not completed.\n");
1226
1227 /* If EEPROM is not marked present, init the PHY manually */
1228 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1229 (hw->phy.type == e1000_phy_igp_3))
1230 igb_phy_init_script_igp3(hw);
1231
1232 return ret_val;
1233 }
1234
1235 /**
1236 * igb_get_link_up_info_82575 - Get link speed/duplex info
1237 * @hw: pointer to the HW structure
1238 * @speed: stores the current speed
1239 * @duplex: stores the current duplex
1240 *
1241 * This is a wrapper function, if using the serial gigabit media independent
1242 * interface, use PCS to retrieve the link speed and duplex information.
1243 * Otherwise, use the generic function to get the link speed and duplex info.
1244 **/
1245 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1246 u16 *duplex)
1247 {
1248 s32 ret_val;
1249
1250 if (hw->phy.media_type != e1000_media_type_copper)
1251 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1252 duplex);
1253 else
1254 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1255 duplex);
1256
1257 return ret_val;
1258 }
1259
1260 /**
1261 * igb_check_for_link_82575 - Check for link
1262 * @hw: pointer to the HW structure
1263 *
1264 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1265 * use the generic interface for determining link.
1266 **/
1267 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1268 {
1269 s32 ret_val;
1270 u16 speed, duplex;
1271
1272 if (hw->phy.media_type != e1000_media_type_copper) {
1273 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1274 &duplex);
1275 /* Use this flag to determine if link needs to be checked or
1276 * not. If we have link clear the flag so that we do not
1277 * continue to check for link.
1278 */
1279 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1280
1281 /* Configure Flow Control now that Auto-Neg has completed.
1282 * First, we need to restore the desired flow control
1283 * settings because we may have had to re-autoneg with a
1284 * different link partner.
1285 */
1286 ret_val = igb_config_fc_after_link_up(hw);
1287 if (ret_val)
1288 hw_dbg("Error configuring flow control\n");
1289 } else {
1290 ret_val = igb_check_for_copper_link(hw);
1291 }
1292
1293 return ret_val;
1294 }
1295
1296 /**
1297 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1298 * @hw: pointer to the HW structure
1299 **/
1300 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1301 {
1302 u32 reg;
1303
1304
1305 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1306 !igb_sgmii_active_82575(hw))
1307 return;
1308
1309 /* Enable PCS to turn on link */
1310 reg = rd32(E1000_PCS_CFG0);
1311 reg |= E1000_PCS_CFG_PCS_EN;
1312 wr32(E1000_PCS_CFG0, reg);
1313
1314 /* Power up the laser */
1315 reg = rd32(E1000_CTRL_EXT);
1316 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1317 wr32(E1000_CTRL_EXT, reg);
1318
1319 /* flush the write to verify completion */
1320 wrfl();
1321 msleep(1);
1322 }
1323
1324 /**
1325 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1326 * @hw: pointer to the HW structure
1327 * @speed: stores the current speed
1328 * @duplex: stores the current duplex
1329 *
1330 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1331 * duplex, then store the values in the pointers provided.
1332 **/
1333 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1334 u16 *duplex)
1335 {
1336 struct e1000_mac_info *mac = &hw->mac;
1337 u32 pcs, status;
1338
1339 /* Set up defaults for the return values of this function */
1340 mac->serdes_has_link = false;
1341 *speed = 0;
1342 *duplex = 0;
1343
1344 /* Read the PCS Status register for link state. For non-copper mode,
1345 * the status register is not accurate. The PCS status register is
1346 * used instead.
1347 */
1348 pcs = rd32(E1000_PCS_LSTAT);
1349
1350 /* The link up bit determines when link is up on autoneg. The sync ok
1351 * gets set once both sides sync up and agree upon link. Stable link
1352 * can be determined by checking for both link up and link sync ok
1353 */
1354 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1355 mac->serdes_has_link = true;
1356
1357 /* Detect and store PCS speed */
1358 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1359 *speed = SPEED_1000;
1360 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1361 *speed = SPEED_100;
1362 else
1363 *speed = SPEED_10;
1364
1365 /* Detect and store PCS duplex */
1366 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1367 *duplex = FULL_DUPLEX;
1368 else
1369 *duplex = HALF_DUPLEX;
1370
1371 /* Check if it is an I354 2.5Gb backplane connection. */
1372 if (mac->type == e1000_i354) {
1373 status = rd32(E1000_STATUS);
1374 if ((status & E1000_STATUS_2P5_SKU) &&
1375 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1376 *speed = SPEED_2500;
1377 *duplex = FULL_DUPLEX;
1378 hw_dbg("2500 Mbs, ");
1379 hw_dbg("Full Duplex\n");
1380 }
1381 }
1382
1383 }
1384
1385 return 0;
1386 }
1387
1388 /**
1389 * igb_shutdown_serdes_link_82575 - Remove link during power down
1390 * @hw: pointer to the HW structure
1391 *
1392 * In the case of fiber serdes, shut down optics and PCS on driver unload
1393 * when management pass thru is not enabled.
1394 **/
1395 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1396 {
1397 u32 reg;
1398
1399 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1400 igb_sgmii_active_82575(hw))
1401 return;
1402
1403 if (!igb_enable_mng_pass_thru(hw)) {
1404 /* Disable PCS to turn off link */
1405 reg = rd32(E1000_PCS_CFG0);
1406 reg &= ~E1000_PCS_CFG_PCS_EN;
1407 wr32(E1000_PCS_CFG0, reg);
1408
1409 /* shutdown the laser */
1410 reg = rd32(E1000_CTRL_EXT);
1411 reg |= E1000_CTRL_EXT_SDP3_DATA;
1412 wr32(E1000_CTRL_EXT, reg);
1413
1414 /* flush the write to verify completion */
1415 wrfl();
1416 msleep(1);
1417 }
1418 }
1419
1420 /**
1421 * igb_reset_hw_82575 - Reset hardware
1422 * @hw: pointer to the HW structure
1423 *
1424 * This resets the hardware into a known state. This is a
1425 * function pointer entry point called by the api module.
1426 **/
1427 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1428 {
1429 u32 ctrl;
1430 s32 ret_val;
1431
1432 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1433 * on the last TLP read/write transaction when MAC is reset.
1434 */
1435 ret_val = igb_disable_pcie_master(hw);
1436 if (ret_val)
1437 hw_dbg("PCI-E Master disable polling has failed.\n");
1438
1439 /* set the completion timeout for interface */
1440 ret_val = igb_set_pcie_completion_timeout(hw);
1441 if (ret_val) {
1442 hw_dbg("PCI-E Set completion timeout has failed.\n");
1443 }
1444
1445 hw_dbg("Masking off all interrupts\n");
1446 wr32(E1000_IMC, 0xffffffff);
1447
1448 wr32(E1000_RCTL, 0);
1449 wr32(E1000_TCTL, E1000_TCTL_PSP);
1450 wrfl();
1451
1452 msleep(10);
1453
1454 ctrl = rd32(E1000_CTRL);
1455
1456 hw_dbg("Issuing a global reset to MAC\n");
1457 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1458
1459 ret_val = igb_get_auto_rd_done(hw);
1460 if (ret_val) {
1461 /* When auto config read does not complete, do not
1462 * return with an error. This can happen in situations
1463 * where there is no eeprom and prevents getting link.
1464 */
1465 hw_dbg("Auto Read Done did not complete\n");
1466 }
1467
1468 /* If EEPROM is not present, run manual init scripts */
1469 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1470 igb_reset_init_script_82575(hw);
1471
1472 /* Clear any pending interrupt events. */
1473 wr32(E1000_IMC, 0xffffffff);
1474 rd32(E1000_ICR);
1475
1476 /* Install any alternate MAC address into RAR0 */
1477 ret_val = igb_check_alt_mac_addr(hw);
1478
1479 return ret_val;
1480 }
1481
1482 /**
1483 * igb_init_hw_82575 - Initialize hardware
1484 * @hw: pointer to the HW structure
1485 *
1486 * This inits the hardware readying it for operation.
1487 **/
1488 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1489 {
1490 struct e1000_mac_info *mac = &hw->mac;
1491 s32 ret_val;
1492 u16 i, rar_count = mac->rar_entry_count;
1493
1494 /* Initialize identification LED */
1495 ret_val = igb_id_led_init(hw);
1496 if (ret_val) {
1497 hw_dbg("Error initializing identification LED\n");
1498 /* This is not fatal and we should not stop init due to this */
1499 }
1500
1501 /* Disabling VLAN filtering */
1502 hw_dbg("Initializing the IEEE VLAN\n");
1503 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1504 igb_clear_vfta_i350(hw);
1505 else
1506 igb_clear_vfta(hw);
1507
1508 /* Setup the receive address */
1509 igb_init_rx_addrs(hw, rar_count);
1510
1511 /* Zero out the Multicast HASH table */
1512 hw_dbg("Zeroing the MTA\n");
1513 for (i = 0; i < mac->mta_reg_count; i++)
1514 array_wr32(E1000_MTA, i, 0);
1515
1516 /* Zero out the Unicast HASH table */
1517 hw_dbg("Zeroing the UTA\n");
1518 for (i = 0; i < mac->uta_reg_count; i++)
1519 array_wr32(E1000_UTA, i, 0);
1520
1521 /* Setup link and flow control */
1522 ret_val = igb_setup_link(hw);
1523
1524 /* Clear all of the statistics registers (clear on read). It is
1525 * important that we do this after we have tried to establish link
1526 * because the symbol error count will increment wildly if there
1527 * is no link.
1528 */
1529 igb_clear_hw_cntrs_82575(hw);
1530 return ret_val;
1531 }
1532
1533 /**
1534 * igb_setup_copper_link_82575 - Configure copper link settings
1535 * @hw: pointer to the HW structure
1536 *
1537 * Configures the link for auto-neg or forced speed and duplex. Then we check
1538 * for link, once link is established calls to configure collision distance
1539 * and flow control are called.
1540 **/
1541 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1542 {
1543 u32 ctrl;
1544 s32 ret_val;
1545 u32 phpm_reg;
1546
1547 ctrl = rd32(E1000_CTRL);
1548 ctrl |= E1000_CTRL_SLU;
1549 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1550 wr32(E1000_CTRL, ctrl);
1551
1552 /* Clear Go Link Disconnect bit on supported devices */
1553 switch (hw->mac.type) {
1554 case e1000_82580:
1555 case e1000_i350:
1556 case e1000_i210:
1557 case e1000_i211:
1558 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1559 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1560 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1561 break;
1562 default:
1563 break;
1564 }
1565
1566 ret_val = igb_setup_serdes_link_82575(hw);
1567 if (ret_val)
1568 goto out;
1569
1570 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1571 /* allow time for SFP cage time to power up phy */
1572 msleep(300);
1573
1574 ret_val = hw->phy.ops.reset(hw);
1575 if (ret_val) {
1576 hw_dbg("Error resetting the PHY.\n");
1577 goto out;
1578 }
1579 }
1580 switch (hw->phy.type) {
1581 case e1000_phy_i210:
1582 case e1000_phy_m88:
1583 switch (hw->phy.id) {
1584 case I347AT4_E_PHY_ID:
1585 case M88E1112_E_PHY_ID:
1586 case M88E1543_E_PHY_ID:
1587 case I210_I_PHY_ID:
1588 ret_val = igb_copper_link_setup_m88_gen2(hw);
1589 break;
1590 default:
1591 ret_val = igb_copper_link_setup_m88(hw);
1592 break;
1593 }
1594 break;
1595 case e1000_phy_igp_3:
1596 ret_val = igb_copper_link_setup_igp(hw);
1597 break;
1598 case e1000_phy_82580:
1599 ret_val = igb_copper_link_setup_82580(hw);
1600 break;
1601 default:
1602 ret_val = -E1000_ERR_PHY;
1603 break;
1604 }
1605
1606 if (ret_val)
1607 goto out;
1608
1609 ret_val = igb_setup_copper_link(hw);
1610 out:
1611 return ret_val;
1612 }
1613
1614 /**
1615 * igb_setup_serdes_link_82575 - Setup link for serdes
1616 * @hw: pointer to the HW structure
1617 *
1618 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1619 * used on copper connections where the serialized gigabit media independent
1620 * interface (sgmii), or serdes fiber is being used. Configures the link
1621 * for auto-negotiation or forces speed/duplex.
1622 **/
1623 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1624 {
1625 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1626 bool pcs_autoneg;
1627 s32 ret_val = E1000_SUCCESS;
1628 u16 data;
1629
1630 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1631 !igb_sgmii_active_82575(hw))
1632 return ret_val;
1633
1634
1635 /* On the 82575, SerDes loopback mode persists until it is
1636 * explicitly turned off or a power cycle is performed. A read to
1637 * the register does not indicate its status. Therefore, we ensure
1638 * loopback mode is disabled during initialization.
1639 */
1640 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1641
1642 /* power on the sfp cage if present and turn on I2C */
1643 ctrl_ext = rd32(E1000_CTRL_EXT);
1644 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1645 ctrl_ext |= E1000_CTRL_I2C_ENA;
1646 wr32(E1000_CTRL_EXT, ctrl_ext);
1647
1648 ctrl_reg = rd32(E1000_CTRL);
1649 ctrl_reg |= E1000_CTRL_SLU;
1650
1651 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1652 /* set both sw defined pins */
1653 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1654
1655 /* Set switch control to serdes energy detect */
1656 reg = rd32(E1000_CONNSW);
1657 reg |= E1000_CONNSW_ENRGSRC;
1658 wr32(E1000_CONNSW, reg);
1659 }
1660
1661 reg = rd32(E1000_PCS_LCTL);
1662
1663 /* default pcs_autoneg to the same setting as mac autoneg */
1664 pcs_autoneg = hw->mac.autoneg;
1665
1666 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1667 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1668 /* sgmii mode lets the phy handle forcing speed/duplex */
1669 pcs_autoneg = true;
1670 /* autoneg time out should be disabled for SGMII mode */
1671 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1672 break;
1673 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1674 /* disable PCS autoneg and support parallel detect only */
1675 pcs_autoneg = false;
1676 default:
1677 if (hw->mac.type == e1000_82575 ||
1678 hw->mac.type == e1000_82576) {
1679 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1680 if (ret_val) {
1681 printk(KERN_DEBUG "NVM Read Error\n\n");
1682 return ret_val;
1683 }
1684
1685 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1686 pcs_autoneg = false;
1687 }
1688
1689 /* non-SGMII modes only supports a speed of 1000/Full for the
1690 * link so it is best to just force the MAC and let the pcs
1691 * link either autoneg or be forced to 1000/Full
1692 */
1693 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1694 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1695
1696 /* set speed of 1000/Full if speed/duplex is forced */
1697 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1698 break;
1699 }
1700
1701 wr32(E1000_CTRL, ctrl_reg);
1702
1703 /* New SerDes mode allows for forcing speed or autonegotiating speed
1704 * at 1gb. Autoneg should be default set by most drivers. This is the
1705 * mode that will be compatible with older link partners and switches.
1706 * However, both are supported by the hardware and some drivers/tools.
1707 */
1708 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1709 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1710
1711 if (pcs_autoneg) {
1712 /* Set PCS register for autoneg */
1713 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1714 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1715
1716 /* Disable force flow control for autoneg */
1717 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1718
1719 /* Configure flow control advertisement for autoneg */
1720 anadv_reg = rd32(E1000_PCS_ANADV);
1721 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1722 switch (hw->fc.requested_mode) {
1723 case e1000_fc_full:
1724 case e1000_fc_rx_pause:
1725 anadv_reg |= E1000_TXCW_ASM_DIR;
1726 anadv_reg |= E1000_TXCW_PAUSE;
1727 break;
1728 case e1000_fc_tx_pause:
1729 anadv_reg |= E1000_TXCW_ASM_DIR;
1730 break;
1731 default:
1732 break;
1733 }
1734 wr32(E1000_PCS_ANADV, anadv_reg);
1735
1736 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1737 } else {
1738 /* Set PCS register for forced link */
1739 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1740
1741 /* Force flow control for forced link */
1742 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1743
1744 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1745 }
1746
1747 wr32(E1000_PCS_LCTL, reg);
1748
1749 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1750 igb_force_mac_fc(hw);
1751
1752 return ret_val;
1753 }
1754
1755 /**
1756 * igb_sgmii_active_82575 - Return sgmii state
1757 * @hw: pointer to the HW structure
1758 *
1759 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1760 * which can be enabled for use in the embedded applications. Simply
1761 * return the current state of the sgmii interface.
1762 **/
1763 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1764 {
1765 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1766 return dev_spec->sgmii_active;
1767 }
1768
1769 /**
1770 * igb_reset_init_script_82575 - Inits HW defaults after reset
1771 * @hw: pointer to the HW structure
1772 *
1773 * Inits recommended HW defaults after a reset when there is no EEPROM
1774 * detected. This is only for the 82575.
1775 **/
1776 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1777 {
1778 if (hw->mac.type == e1000_82575) {
1779 hw_dbg("Running reset init script for 82575\n");
1780 /* SerDes configuration via SERDESCTRL */
1781 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1782 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1783 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1784 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1785
1786 /* CCM configuration via CCMCTL register */
1787 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1788 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1789
1790 /* PCIe lanes configuration */
1791 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1792 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1793 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1794 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1795
1796 /* PCIe PLL Configuration */
1797 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1798 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1799 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1800 }
1801
1802 return 0;
1803 }
1804
1805 /**
1806 * igb_read_mac_addr_82575 - Read device MAC address
1807 * @hw: pointer to the HW structure
1808 **/
1809 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1810 {
1811 s32 ret_val = 0;
1812
1813 /* If there's an alternate MAC address place it in RAR0
1814 * so that it will override the Si installed default perm
1815 * address.
1816 */
1817 ret_val = igb_check_alt_mac_addr(hw);
1818 if (ret_val)
1819 goto out;
1820
1821 ret_val = igb_read_mac_addr(hw);
1822
1823 out:
1824 return ret_val;
1825 }
1826
1827 /**
1828 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1829 * @hw: pointer to the HW structure
1830 *
1831 * In the case of a PHY power down to save power, or to turn off link during a
1832 * driver unload, or wake on lan is not enabled, remove the link.
1833 **/
1834 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1835 {
1836 /* If the management interface is not enabled, then power down */
1837 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1838 igb_power_down_phy_copper(hw);
1839 }
1840
1841 /**
1842 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1843 * @hw: pointer to the HW structure
1844 *
1845 * Clears the hardware counters by reading the counter registers.
1846 **/
1847 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1848 {
1849 igb_clear_hw_cntrs_base(hw);
1850
1851 rd32(E1000_PRC64);
1852 rd32(E1000_PRC127);
1853 rd32(E1000_PRC255);
1854 rd32(E1000_PRC511);
1855 rd32(E1000_PRC1023);
1856 rd32(E1000_PRC1522);
1857 rd32(E1000_PTC64);
1858 rd32(E1000_PTC127);
1859 rd32(E1000_PTC255);
1860 rd32(E1000_PTC511);
1861 rd32(E1000_PTC1023);
1862 rd32(E1000_PTC1522);
1863
1864 rd32(E1000_ALGNERRC);
1865 rd32(E1000_RXERRC);
1866 rd32(E1000_TNCRS);
1867 rd32(E1000_CEXTERR);
1868 rd32(E1000_TSCTC);
1869 rd32(E1000_TSCTFC);
1870
1871 rd32(E1000_MGTPRC);
1872 rd32(E1000_MGTPDC);
1873 rd32(E1000_MGTPTC);
1874
1875 rd32(E1000_IAC);
1876 rd32(E1000_ICRXOC);
1877
1878 rd32(E1000_ICRXPTC);
1879 rd32(E1000_ICRXATC);
1880 rd32(E1000_ICTXPTC);
1881 rd32(E1000_ICTXATC);
1882 rd32(E1000_ICTXQEC);
1883 rd32(E1000_ICTXQMTC);
1884 rd32(E1000_ICRXDMTC);
1885
1886 rd32(E1000_CBTMPC);
1887 rd32(E1000_HTDPMC);
1888 rd32(E1000_CBRMPC);
1889 rd32(E1000_RPTHC);
1890 rd32(E1000_HGPTC);
1891 rd32(E1000_HTCBDPC);
1892 rd32(E1000_HGORCL);
1893 rd32(E1000_HGORCH);
1894 rd32(E1000_HGOTCL);
1895 rd32(E1000_HGOTCH);
1896 rd32(E1000_LENERRS);
1897
1898 /* This register should not be read in copper configurations */
1899 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1900 igb_sgmii_active_82575(hw))
1901 rd32(E1000_SCVPC);
1902 }
1903
1904 /**
1905 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1906 * @hw: pointer to the HW structure
1907 *
1908 * After rx enable if managability is enabled then there is likely some
1909 * bad data at the start of the fifo and possibly in the DMA fifo. This
1910 * function clears the fifos and flushes any packets that came in as rx was
1911 * being enabled.
1912 **/
1913 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1914 {
1915 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1916 int i, ms_wait;
1917
1918 if (hw->mac.type != e1000_82575 ||
1919 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1920 return;
1921
1922 /* Disable all RX queues */
1923 for (i = 0; i < 4; i++) {
1924 rxdctl[i] = rd32(E1000_RXDCTL(i));
1925 wr32(E1000_RXDCTL(i),
1926 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1927 }
1928 /* Poll all queues to verify they have shut down */
1929 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1930 msleep(1);
1931 rx_enabled = 0;
1932 for (i = 0; i < 4; i++)
1933 rx_enabled |= rd32(E1000_RXDCTL(i));
1934 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1935 break;
1936 }
1937
1938 if (ms_wait == 10)
1939 hw_dbg("Queue disable timed out after 10ms\n");
1940
1941 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1942 * incoming packets are rejected. Set enable and wait 2ms so that
1943 * any packet that was coming in as RCTL.EN was set is flushed
1944 */
1945 rfctl = rd32(E1000_RFCTL);
1946 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1947
1948 rlpml = rd32(E1000_RLPML);
1949 wr32(E1000_RLPML, 0);
1950
1951 rctl = rd32(E1000_RCTL);
1952 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1953 temp_rctl |= E1000_RCTL_LPE;
1954
1955 wr32(E1000_RCTL, temp_rctl);
1956 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1957 wrfl();
1958 msleep(2);
1959
1960 /* Enable RX queues that were previously enabled and restore our
1961 * previous state
1962 */
1963 for (i = 0; i < 4; i++)
1964 wr32(E1000_RXDCTL(i), rxdctl[i]);
1965 wr32(E1000_RCTL, rctl);
1966 wrfl();
1967
1968 wr32(E1000_RLPML, rlpml);
1969 wr32(E1000_RFCTL, rfctl);
1970
1971 /* Flush receive errors generated by workaround */
1972 rd32(E1000_ROC);
1973 rd32(E1000_RNBC);
1974 rd32(E1000_MPC);
1975 }
1976
1977 /**
1978 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1979 * @hw: pointer to the HW structure
1980 *
1981 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1982 * however the hardware default for these parts is 500us to 1ms which is less
1983 * than the 10ms recommended by the pci-e spec. To address this we need to
1984 * increase the value to either 10ms to 200ms for capability version 1 config,
1985 * or 16ms to 55ms for version 2.
1986 **/
1987 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1988 {
1989 u32 gcr = rd32(E1000_GCR);
1990 s32 ret_val = 0;
1991 u16 pcie_devctl2;
1992
1993 /* only take action if timeout value is defaulted to 0 */
1994 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1995 goto out;
1996
1997 /* if capabilities version is type 1 we can write the
1998 * timeout of 10ms to 200ms through the GCR register
1999 */
2000 if (!(gcr & E1000_GCR_CAP_VER2)) {
2001 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2002 goto out;
2003 }
2004
2005 /* for version 2 capabilities we need to write the config space
2006 * directly in order to set the completion timeout value for
2007 * 16ms to 55ms
2008 */
2009 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2010 &pcie_devctl2);
2011 if (ret_val)
2012 goto out;
2013
2014 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2015
2016 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2017 &pcie_devctl2);
2018 out:
2019 /* disable completion timeout resend */
2020 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2021
2022 wr32(E1000_GCR, gcr);
2023 return ret_val;
2024 }
2025
2026 /**
2027 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2028 * @hw: pointer to the hardware struct
2029 * @enable: state to enter, either enabled or disabled
2030 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2031 *
2032 * enables/disables L2 switch anti-spoofing functionality.
2033 **/
2034 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2035 {
2036 u32 reg_val, reg_offset;
2037
2038 switch (hw->mac.type) {
2039 case e1000_82576:
2040 reg_offset = E1000_DTXSWC;
2041 break;
2042 case e1000_i350:
2043 case e1000_i354:
2044 reg_offset = E1000_TXSWC;
2045 break;
2046 default:
2047 return;
2048 }
2049
2050 reg_val = rd32(reg_offset);
2051 if (enable) {
2052 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2053 E1000_DTXSWC_VLAN_SPOOF_MASK);
2054 /* The PF can spoof - it has to in order to
2055 * support emulation mode NICs
2056 */
2057 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2058 } else {
2059 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2060 E1000_DTXSWC_VLAN_SPOOF_MASK);
2061 }
2062 wr32(reg_offset, reg_val);
2063 }
2064
2065 /**
2066 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2067 * @hw: pointer to the hardware struct
2068 * @enable: state to enter, either enabled or disabled
2069 *
2070 * enables/disables L2 switch loopback functionality.
2071 **/
2072 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2073 {
2074 u32 dtxswc;
2075
2076 switch (hw->mac.type) {
2077 case e1000_82576:
2078 dtxswc = rd32(E1000_DTXSWC);
2079 if (enable)
2080 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2081 else
2082 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2083 wr32(E1000_DTXSWC, dtxswc);
2084 break;
2085 case e1000_i354:
2086 case e1000_i350:
2087 dtxswc = rd32(E1000_TXSWC);
2088 if (enable)
2089 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2090 else
2091 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2092 wr32(E1000_TXSWC, dtxswc);
2093 break;
2094 default:
2095 /* Currently no other hardware supports loopback */
2096 break;
2097 }
2098
2099 }
2100
2101 /**
2102 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2103 * @hw: pointer to the hardware struct
2104 * @enable: state to enter, either enabled or disabled
2105 *
2106 * enables/disables replication of packets across multiple pools.
2107 **/
2108 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2109 {
2110 u32 vt_ctl = rd32(E1000_VT_CTL);
2111
2112 if (enable)
2113 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2114 else
2115 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2116
2117 wr32(E1000_VT_CTL, vt_ctl);
2118 }
2119
2120 /**
2121 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2122 * @hw: pointer to the HW structure
2123 * @offset: register offset to be read
2124 * @data: pointer to the read data
2125 *
2126 * Reads the MDI control register in the PHY at offset and stores the
2127 * information read to data.
2128 **/
2129 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2130 {
2131 s32 ret_val;
2132
2133 ret_val = hw->phy.ops.acquire(hw);
2134 if (ret_val)
2135 goto out;
2136
2137 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2138
2139 hw->phy.ops.release(hw);
2140
2141 out:
2142 return ret_val;
2143 }
2144
2145 /**
2146 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2147 * @hw: pointer to the HW structure
2148 * @offset: register offset to write to
2149 * @data: data to write to register at offset
2150 *
2151 * Writes data to MDI control register in the PHY at offset.
2152 **/
2153 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2154 {
2155 s32 ret_val;
2156
2157
2158 ret_val = hw->phy.ops.acquire(hw);
2159 if (ret_val)
2160 goto out;
2161
2162 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2163
2164 hw->phy.ops.release(hw);
2165
2166 out:
2167 return ret_val;
2168 }
2169
2170 /**
2171 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2172 * @hw: pointer to the HW structure
2173 *
2174 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2175 * the values found in the EEPROM. This addresses an issue in which these
2176 * bits are not restored from EEPROM after reset.
2177 **/
2178 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2179 {
2180 s32 ret_val = 0;
2181 u32 mdicnfg;
2182 u16 nvm_data = 0;
2183
2184 if (hw->mac.type != e1000_82580)
2185 goto out;
2186 if (!igb_sgmii_active_82575(hw))
2187 goto out;
2188
2189 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2190 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2191 &nvm_data);
2192 if (ret_val) {
2193 hw_dbg("NVM Read Error\n");
2194 goto out;
2195 }
2196
2197 mdicnfg = rd32(E1000_MDICNFG);
2198 if (nvm_data & NVM_WORD24_EXT_MDIO)
2199 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2200 if (nvm_data & NVM_WORD24_COM_MDIO)
2201 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2202 wr32(E1000_MDICNFG, mdicnfg);
2203 out:
2204 return ret_val;
2205 }
2206
2207 /**
2208 * igb_reset_hw_82580 - Reset hardware
2209 * @hw: pointer to the HW structure
2210 *
2211 * This resets function or entire device (all ports, etc.)
2212 * to a known state.
2213 **/
2214 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2215 {
2216 s32 ret_val = 0;
2217 /* BH SW mailbox bit in SW_FW_SYNC */
2218 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2219 u32 ctrl;
2220 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2221
2222 hw->dev_spec._82575.global_device_reset = false;
2223
2224 /* due to hw errata, global device reset doesn't always
2225 * work on 82580
2226 */
2227 if (hw->mac.type == e1000_82580)
2228 global_device_reset = false;
2229
2230 /* Get current control state. */
2231 ctrl = rd32(E1000_CTRL);
2232
2233 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2234 * on the last TLP read/write transaction when MAC is reset.
2235 */
2236 ret_val = igb_disable_pcie_master(hw);
2237 if (ret_val)
2238 hw_dbg("PCI-E Master disable polling has failed.\n");
2239
2240 hw_dbg("Masking off all interrupts\n");
2241 wr32(E1000_IMC, 0xffffffff);
2242 wr32(E1000_RCTL, 0);
2243 wr32(E1000_TCTL, E1000_TCTL_PSP);
2244 wrfl();
2245
2246 msleep(10);
2247
2248 /* Determine whether or not a global dev reset is requested */
2249 if (global_device_reset &&
2250 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2251 global_device_reset = false;
2252
2253 if (global_device_reset &&
2254 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2255 ctrl |= E1000_CTRL_DEV_RST;
2256 else
2257 ctrl |= E1000_CTRL_RST;
2258
2259 wr32(E1000_CTRL, ctrl);
2260 wrfl();
2261
2262 /* Add delay to insure DEV_RST has time to complete */
2263 if (global_device_reset)
2264 msleep(5);
2265
2266 ret_val = igb_get_auto_rd_done(hw);
2267 if (ret_val) {
2268 /* When auto config read does not complete, do not
2269 * return with an error. This can happen in situations
2270 * where there is no eeprom and prevents getting link.
2271 */
2272 hw_dbg("Auto Read Done did not complete\n");
2273 }
2274
2275 /* clear global device reset status bit */
2276 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2277
2278 /* Clear any pending interrupt events. */
2279 wr32(E1000_IMC, 0xffffffff);
2280 rd32(E1000_ICR);
2281
2282 ret_val = igb_reset_mdicnfg_82580(hw);
2283 if (ret_val)
2284 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2285
2286 /* Install any alternate MAC address into RAR0 */
2287 ret_val = igb_check_alt_mac_addr(hw);
2288
2289 /* Release semaphore */
2290 if (global_device_reset)
2291 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2292
2293 return ret_val;
2294 }
2295
2296 /**
2297 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2298 * @data: data received by reading RXPBS register
2299 *
2300 * The 82580 uses a table based approach for packet buffer allocation sizes.
2301 * This function converts the retrieved value into the correct table value
2302 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2303 * 0x0 36 72 144 1 2 4 8 16
2304 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2305 */
2306 u16 igb_rxpbs_adjust_82580(u32 data)
2307 {
2308 u16 ret_val = 0;
2309
2310 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2311 ret_val = e1000_82580_rxpbs_table[data];
2312
2313 return ret_val;
2314 }
2315
2316 /**
2317 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2318 * checksum
2319 * @hw: pointer to the HW structure
2320 * @offset: offset in words of the checksum protected region
2321 *
2322 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2323 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2324 **/
2325 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2326 u16 offset)
2327 {
2328 s32 ret_val = 0;
2329 u16 checksum = 0;
2330 u16 i, nvm_data;
2331
2332 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2333 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2334 if (ret_val) {
2335 hw_dbg("NVM Read Error\n");
2336 goto out;
2337 }
2338 checksum += nvm_data;
2339 }
2340
2341 if (checksum != (u16) NVM_SUM) {
2342 hw_dbg("NVM Checksum Invalid\n");
2343 ret_val = -E1000_ERR_NVM;
2344 goto out;
2345 }
2346
2347 out:
2348 return ret_val;
2349 }
2350
2351 /**
2352 * igb_update_nvm_checksum_with_offset - Update EEPROM
2353 * checksum
2354 * @hw: pointer to the HW structure
2355 * @offset: offset in words of the checksum protected region
2356 *
2357 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2358 * up to the checksum. Then calculates the EEPROM checksum and writes the
2359 * value to the EEPROM.
2360 **/
2361 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2362 {
2363 s32 ret_val;
2364 u16 checksum = 0;
2365 u16 i, nvm_data;
2366
2367 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2368 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2369 if (ret_val) {
2370 hw_dbg("NVM Read Error while updating checksum.\n");
2371 goto out;
2372 }
2373 checksum += nvm_data;
2374 }
2375 checksum = (u16) NVM_SUM - checksum;
2376 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2377 &checksum);
2378 if (ret_val)
2379 hw_dbg("NVM Write Error while updating checksum.\n");
2380
2381 out:
2382 return ret_val;
2383 }
2384
2385 /**
2386 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2387 * @hw: pointer to the HW structure
2388 *
2389 * Calculates the EEPROM section checksum by reading/adding each word of
2390 * the EEPROM and then verifies that the sum of the EEPROM is
2391 * equal to 0xBABA.
2392 **/
2393 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2394 {
2395 s32 ret_val = 0;
2396 u16 eeprom_regions_count = 1;
2397 u16 j, nvm_data;
2398 u16 nvm_offset;
2399
2400 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2401 if (ret_val) {
2402 hw_dbg("NVM Read Error\n");
2403 goto out;
2404 }
2405
2406 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2407 /* if checksums compatibility bit is set validate checksums
2408 * for all 4 ports.
2409 */
2410 eeprom_regions_count = 4;
2411 }
2412
2413 for (j = 0; j < eeprom_regions_count; j++) {
2414 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2415 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2416 nvm_offset);
2417 if (ret_val != 0)
2418 goto out;
2419 }
2420
2421 out:
2422 return ret_val;
2423 }
2424
2425 /**
2426 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2427 * @hw: pointer to the HW structure
2428 *
2429 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2430 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2431 * checksum and writes the value to the EEPROM.
2432 **/
2433 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2434 {
2435 s32 ret_val;
2436 u16 j, nvm_data;
2437 u16 nvm_offset;
2438
2439 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2440 if (ret_val) {
2441 hw_dbg("NVM Read Error while updating checksum"
2442 " compatibility bit.\n");
2443 goto out;
2444 }
2445
2446 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2447 /* set compatibility bit to validate checksums appropriately */
2448 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2449 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2450 &nvm_data);
2451 if (ret_val) {
2452 hw_dbg("NVM Write Error while updating checksum"
2453 " compatibility bit.\n");
2454 goto out;
2455 }
2456 }
2457
2458 for (j = 0; j < 4; j++) {
2459 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2460 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2461 if (ret_val)
2462 goto out;
2463 }
2464
2465 out:
2466 return ret_val;
2467 }
2468
2469 /**
2470 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2471 * @hw: pointer to the HW structure
2472 *
2473 * Calculates the EEPROM section checksum by reading/adding each word of
2474 * the EEPROM and then verifies that the sum of the EEPROM is
2475 * equal to 0xBABA.
2476 **/
2477 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2478 {
2479 s32 ret_val = 0;
2480 u16 j;
2481 u16 nvm_offset;
2482
2483 for (j = 0; j < 4; j++) {
2484 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2485 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2486 nvm_offset);
2487 if (ret_val != 0)
2488 goto out;
2489 }
2490
2491 out:
2492 return ret_val;
2493 }
2494
2495 /**
2496 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2497 * @hw: pointer to the HW structure
2498 *
2499 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2500 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2501 * checksum and writes the value to the EEPROM.
2502 **/
2503 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2504 {
2505 s32 ret_val = 0;
2506 u16 j;
2507 u16 nvm_offset;
2508
2509 for (j = 0; j < 4; j++) {
2510 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2511 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2512 if (ret_val != 0)
2513 goto out;
2514 }
2515
2516 out:
2517 return ret_val;
2518 }
2519
2520 /**
2521 * __igb_access_emi_reg - Read/write EMI register
2522 * @hw: pointer to the HW structure
2523 * @addr: EMI address to program
2524 * @data: pointer to value to read/write from/to the EMI address
2525 * @read: boolean flag to indicate read or write
2526 **/
2527 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2528 u16 *data, bool read)
2529 {
2530 s32 ret_val = E1000_SUCCESS;
2531
2532 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2533 if (ret_val)
2534 return ret_val;
2535
2536 if (read)
2537 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2538 else
2539 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2540
2541 return ret_val;
2542 }
2543
2544 /**
2545 * igb_read_emi_reg - Read Extended Management Interface register
2546 * @hw: pointer to the HW structure
2547 * @addr: EMI address to program
2548 * @data: value to be read from the EMI address
2549 **/
2550 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2551 {
2552 return __igb_access_emi_reg(hw, addr, data, true);
2553 }
2554
2555 /**
2556 * igb_set_eee_i350 - Enable/disable EEE support
2557 * @hw: pointer to the HW structure
2558 *
2559 * Enable/disable EEE based on setting in dev_spec structure.
2560 *
2561 **/
2562 s32 igb_set_eee_i350(struct e1000_hw *hw)
2563 {
2564 s32 ret_val = 0;
2565 u32 ipcnfg, eeer;
2566
2567 if ((hw->mac.type < e1000_i350) ||
2568 (hw->phy.media_type != e1000_media_type_copper))
2569 goto out;
2570 ipcnfg = rd32(E1000_IPCNFG);
2571 eeer = rd32(E1000_EEER);
2572
2573 /* enable or disable per user setting */
2574 if (!(hw->dev_spec._82575.eee_disable)) {
2575 u32 eee_su = rd32(E1000_EEE_SU);
2576
2577 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2578 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2579 E1000_EEER_LPI_FC);
2580
2581 /* This bit should not be set in normal operation. */
2582 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2583 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2584
2585 } else {
2586 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2587 E1000_IPCNFG_EEE_100M_AN);
2588 eeer &= ~(E1000_EEER_TX_LPI_EN |
2589 E1000_EEER_RX_LPI_EN |
2590 E1000_EEER_LPI_FC);
2591 }
2592 wr32(E1000_IPCNFG, ipcnfg);
2593 wr32(E1000_EEER, eeer);
2594 rd32(E1000_IPCNFG);
2595 rd32(E1000_EEER);
2596 out:
2597
2598 return ret_val;
2599 }
2600
2601 /**
2602 * igb_set_eee_i354 - Enable/disable EEE support
2603 * @hw: pointer to the HW structure
2604 *
2605 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2606 *
2607 **/
2608 s32 igb_set_eee_i354(struct e1000_hw *hw)
2609 {
2610 struct e1000_phy_info *phy = &hw->phy;
2611 s32 ret_val = 0;
2612 u16 phy_data;
2613
2614 if ((hw->phy.media_type != e1000_media_type_copper) ||
2615 (phy->id != M88E1543_E_PHY_ID))
2616 goto out;
2617
2618 if (!hw->dev_spec._82575.eee_disable) {
2619 /* Switch to PHY page 18. */
2620 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2621 if (ret_val)
2622 goto out;
2623
2624 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2625 &phy_data);
2626 if (ret_val)
2627 goto out;
2628
2629 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2630 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2631 phy_data);
2632 if (ret_val)
2633 goto out;
2634
2635 /* Return the PHY to page 0. */
2636 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2637 if (ret_val)
2638 goto out;
2639
2640 /* Turn on EEE advertisement. */
2641 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2642 E1000_EEE_ADV_DEV_I354,
2643 &phy_data);
2644 if (ret_val)
2645 goto out;
2646
2647 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2648 E1000_EEE_ADV_1000_SUPPORTED;
2649 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2650 E1000_EEE_ADV_DEV_I354,
2651 phy_data);
2652 } else {
2653 /* Turn off EEE advertisement. */
2654 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2655 E1000_EEE_ADV_DEV_I354,
2656 &phy_data);
2657 if (ret_val)
2658 goto out;
2659
2660 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2661 E1000_EEE_ADV_1000_SUPPORTED);
2662 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2663 E1000_EEE_ADV_DEV_I354,
2664 phy_data);
2665 }
2666
2667 out:
2668 return ret_val;
2669 }
2670
2671 /**
2672 * igb_get_eee_status_i354 - Get EEE status
2673 * @hw: pointer to the HW structure
2674 * @status: EEE status
2675 *
2676 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2677 * been received.
2678 **/
2679 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2680 {
2681 struct e1000_phy_info *phy = &hw->phy;
2682 s32 ret_val = 0;
2683 u16 phy_data;
2684
2685 /* Check if EEE is supported on this device. */
2686 if ((hw->phy.media_type != e1000_media_type_copper) ||
2687 (phy->id != M88E1543_E_PHY_ID))
2688 goto out;
2689
2690 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2691 E1000_PCS_STATUS_DEV_I354,
2692 &phy_data);
2693 if (ret_val)
2694 goto out;
2695
2696 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2697 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2698
2699 out:
2700 return ret_val;
2701 }
2702
2703 static const u8 e1000_emc_temp_data[4] = {
2704 E1000_EMC_INTERNAL_DATA,
2705 E1000_EMC_DIODE1_DATA,
2706 E1000_EMC_DIODE2_DATA,
2707 E1000_EMC_DIODE3_DATA
2708 };
2709 static const u8 e1000_emc_therm_limit[4] = {
2710 E1000_EMC_INTERNAL_THERM_LIMIT,
2711 E1000_EMC_DIODE1_THERM_LIMIT,
2712 E1000_EMC_DIODE2_THERM_LIMIT,
2713 E1000_EMC_DIODE3_THERM_LIMIT
2714 };
2715
2716 /**
2717 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2718 * @hw: pointer to hardware structure
2719 *
2720 * Updates the temperatures in mac.thermal_sensor_data
2721 **/
2722 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2723 {
2724 s32 status = E1000_SUCCESS;
2725 u16 ets_offset;
2726 u16 ets_cfg;
2727 u16 ets_sensor;
2728 u8 num_sensors;
2729 u8 sensor_index;
2730 u8 sensor_location;
2731 u8 i;
2732 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2733
2734 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2735 return E1000_NOT_IMPLEMENTED;
2736
2737 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2738
2739 /* Return the internal sensor only if ETS is unsupported */
2740 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2741 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2742 return status;
2743
2744 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2745 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2746 != NVM_ETS_TYPE_EMC)
2747 return E1000_NOT_IMPLEMENTED;
2748
2749 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2750 if (num_sensors > E1000_MAX_SENSORS)
2751 num_sensors = E1000_MAX_SENSORS;
2752
2753 for (i = 1; i < num_sensors; i++) {
2754 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2755 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2756 NVM_ETS_DATA_INDEX_SHIFT);
2757 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2758 NVM_ETS_DATA_LOC_SHIFT);
2759
2760 if (sensor_location != 0)
2761 hw->phy.ops.read_i2c_byte(hw,
2762 e1000_emc_temp_data[sensor_index],
2763 E1000_I2C_THERMAL_SENSOR_ADDR,
2764 &data->sensor[i].temp);
2765 }
2766 return status;
2767 }
2768
2769 /**
2770 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2771 * @hw: pointer to hardware structure
2772 *
2773 * Sets the thermal sensor thresholds according to the NVM map
2774 * and save off the threshold and location values into mac.thermal_sensor_data
2775 **/
2776 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2777 {
2778 s32 status = E1000_SUCCESS;
2779 u16 ets_offset;
2780 u16 ets_cfg;
2781 u16 ets_sensor;
2782 u8 low_thresh_delta;
2783 u8 num_sensors;
2784 u8 sensor_index;
2785 u8 sensor_location;
2786 u8 therm_limit;
2787 u8 i;
2788 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2789
2790 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2791 return E1000_NOT_IMPLEMENTED;
2792
2793 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2794
2795 data->sensor[0].location = 0x1;
2796 data->sensor[0].caution_thresh =
2797 (rd32(E1000_THHIGHTC) & 0xFF);
2798 data->sensor[0].max_op_thresh =
2799 (rd32(E1000_THLOWTC) & 0xFF);
2800
2801 /* Return the internal sensor only if ETS is unsupported */
2802 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2803 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2804 return status;
2805
2806 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2807 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2808 != NVM_ETS_TYPE_EMC)
2809 return E1000_NOT_IMPLEMENTED;
2810
2811 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2812 NVM_ETS_LTHRES_DELTA_SHIFT);
2813 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2814
2815 for (i = 1; i <= num_sensors; i++) {
2816 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2817 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2818 NVM_ETS_DATA_INDEX_SHIFT);
2819 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2820 NVM_ETS_DATA_LOC_SHIFT);
2821 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2822
2823 hw->phy.ops.write_i2c_byte(hw,
2824 e1000_emc_therm_limit[sensor_index],
2825 E1000_I2C_THERMAL_SENSOR_ADDR,
2826 therm_limit);
2827
2828 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2829 data->sensor[i].location = sensor_location;
2830 data->sensor[i].caution_thresh = therm_limit;
2831 data->sensor[i].max_op_thresh = therm_limit -
2832 low_thresh_delta;
2833 }
2834 }
2835 return status;
2836 }
2837
2838 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2839 .init_hw = igb_init_hw_82575,
2840 .check_for_link = igb_check_for_link_82575,
2841 .rar_set = igb_rar_set,
2842 .read_mac_addr = igb_read_mac_addr_82575,
2843 .get_speed_and_duplex = igb_get_link_up_info_82575,
2844 #ifdef CONFIG_IGB_HWMON
2845 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2846 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2847 #endif
2848 };
2849
2850 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2851 .acquire = igb_acquire_phy_82575,
2852 .get_cfg_done = igb_get_cfg_done_82575,
2853 .release = igb_release_phy_82575,
2854 .write_i2c_byte = igb_write_i2c_byte,
2855 .read_i2c_byte = igb_read_i2c_byte,
2856 };
2857
2858 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2859 .acquire = igb_acquire_nvm_82575,
2860 .read = igb_read_nvm_eerd,
2861 .release = igb_release_nvm_82575,
2862 .write = igb_write_nvm_spi,
2863 };
2864
2865 const struct e1000_info e1000_82575_info = {
2866 .get_invariants = igb_get_invariants_82575,
2867 .mac_ops = &e1000_mac_ops_82575,
2868 .phy_ops = &e1000_phy_ops_82575,
2869 .nvm_ops = &e1000_nvm_ops_82575,
2870 };
2871
Linux kernel - Deliverables
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