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igb: Refractoring function pointers in igb_get_invariants function
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
37
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
41
42 static s32 igb_get_invariants_82575(struct e1000_hw *);
43 static s32 igb_acquire_phy_82575(struct e1000_hw *);
44 static void igb_release_phy_82575(struct e1000_hw *);
45 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46 static void igb_release_nvm_82575(struct e1000_hw *);
47 static s32 igb_check_for_link_82575(struct e1000_hw *);
48 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49 static s32 igb_init_hw_82575(struct e1000_hw *);
50 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
52 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
54 static s32 igb_reset_hw_82575(struct e1000_hw *);
55 static s32 igb_reset_hw_82580(struct e1000_hw *);
56 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
57 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
59 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
60 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
61 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
64 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
65 u16 *);
66 static s32 igb_get_phy_id_82575(struct e1000_hw *);
67 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68 static bool igb_sgmii_active_82575(struct e1000_hw *);
69 static s32 igb_reset_init_script_82575(struct e1000_hw *);
70 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
71 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
72 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
73 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
75 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
77 static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
79 35, 70, 140 };
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
82
83 /**
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
86 *
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
89 **/
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
91 {
92 u32 reg = 0;
93 bool ext_mdio = false;
94
95 switch (hw->mac.type) {
96 case e1000_82575:
97 case e1000_82576:
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
100 break;
101 case e1000_82580:
102 case e1000_i350:
103 case e1000_i210:
104 case e1000_i211:
105 reg = rd32(E1000_MDICNFG);
106 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
107 break;
108 default:
109 break;
110 }
111 return ext_mdio;
112 }
113
114 /**
115 * igb_init_phy_params_82575 - Init PHY func ptrs.
116 * @hw: pointer to the HW structure
117 **/
118 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
119 {
120 struct e1000_phy_info *phy = &hw->phy;
121 s32 ret_val = 0;
122 u32 ctrl_ext;
123
124 if (hw->phy.media_type != e1000_media_type_copper) {
125 phy->type = e1000_phy_none;
126 goto out;
127 }
128
129 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
130 phy->reset_delay_us = 100;
131
132 ctrl_ext = rd32(E1000_CTRL_EXT);
133
134 if (igb_sgmii_active_82575(hw)) {
135 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
136 ctrl_ext |= E1000_CTRL_I2C_ENA;
137 } else {
138 phy->ops.reset = igb_phy_hw_reset;
139 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
140 }
141
142 wr32(E1000_CTRL_EXT, ctrl_ext);
143 igb_reset_mdicnfg_82580(hw);
144
145 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
146 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
147 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
148 } else {
149 switch (hw->mac.type) {
150 case e1000_82580:
151 case e1000_i350:
152 phy->ops.read_reg = igb_read_phy_reg_82580;
153 phy->ops.write_reg = igb_write_phy_reg_82580;
154 break;
155 case e1000_i210:
156 case e1000_i211:
157 phy->ops.read_reg = igb_read_phy_reg_gs40g;
158 phy->ops.write_reg = igb_write_phy_reg_gs40g;
159 break;
160 default:
161 phy->ops.read_reg = igb_read_phy_reg_igp;
162 phy->ops.write_reg = igb_write_phy_reg_igp;
163 }
164 }
165
166 /* set lan id */
167 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
168 E1000_STATUS_FUNC_SHIFT;
169
170 /* Set phy->phy_addr and phy->id. */
171 ret_val = igb_get_phy_id_82575(hw);
172 if (ret_val)
173 return ret_val;
174
175 /* Verify phy id and set remaining function pointers */
176 switch (phy->id) {
177 case I347AT4_E_PHY_ID:
178 case M88E1112_E_PHY_ID:
179 case M88E1111_I_PHY_ID:
180 phy->type = e1000_phy_m88;
181 phy->ops.get_phy_info = igb_get_phy_info_m88;
182 if (phy->id == I347AT4_E_PHY_ID ||
183 phy->id == M88E1112_E_PHY_ID)
184 phy->ops.get_cable_length =
185 igb_get_cable_length_m88_gen2;
186 else
187 phy->ops.get_cable_length = igb_get_cable_length_m88;
188 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
189 break;
190 case IGP03E1000_E_PHY_ID:
191 phy->type = e1000_phy_igp_3;
192 phy->ops.get_phy_info = igb_get_phy_info_igp;
193 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
194 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
195 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
196 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
197 break;
198 case I82580_I_PHY_ID:
199 case I350_I_PHY_ID:
200 phy->type = e1000_phy_82580;
201 phy->ops.force_speed_duplex =
202 igb_phy_force_speed_duplex_82580;
203 phy->ops.get_cable_length = igb_get_cable_length_82580;
204 phy->ops.get_phy_info = igb_get_phy_info_82580;
205 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
206 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
207 break;
208 case I210_I_PHY_ID:
209 phy->type = e1000_phy_i210;
210 phy->ops.check_polarity = igb_check_polarity_m88;
211 phy->ops.get_phy_info = igb_get_phy_info_m88;
212 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
213 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
214 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
215 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
216 break;
217 default:
218 ret_val = -E1000_ERR_PHY;
219 goto out;
220 }
221
222 out:
223 return ret_val;
224 }
225
226 /**
227 * igb_init_nvm_params_82575 - Init NVM func ptrs.
228 * @hw: pointer to the HW structure
229 **/
230 s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
231 {
232 struct e1000_nvm_info *nvm = &hw->nvm;
233 u32 eecd = rd32(E1000_EECD);
234 u16 size;
235
236 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
237 E1000_EECD_SIZE_EX_SHIFT);
238 /* Added to a constant, "size" becomes the left-shift value
239 * for setting word_size.
240 */
241 size += NVM_WORD_SIZE_BASE_SHIFT;
242
243 /* Just in case size is out of range, cap it to the largest
244 * EEPROM size supported
245 */
246 if (size > 15)
247 size = 15;
248
249 nvm->word_size = 1 << size;
250 if (hw->mac.type < e1000_i210) {
251 nvm->opcode_bits = 8;
252 nvm->delay_usec = 1;
253
254 switch (nvm->override) {
255 case e1000_nvm_override_spi_large:
256 nvm->page_size = 32;
257 nvm->address_bits = 16;
258 break;
259 case e1000_nvm_override_spi_small:
260 nvm->page_size = 8;
261 nvm->address_bits = 8;
262 break;
263 default:
264 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
265 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
266 16 : 8;
267 break;
268 }
269 if (nvm->word_size == (1 << 15))
270 nvm->page_size = 128;
271
272 nvm->type = e1000_nvm_eeprom_spi;
273 } else {
274 nvm->type = e1000_nvm_flash_hw;
275 }
276
277 /* NVM Function Pointers */
278 switch (hw->mac.type) {
279 case e1000_82580:
280 nvm->ops.validate = igb_validate_nvm_checksum_82580;
281 nvm->ops.update = igb_update_nvm_checksum_82580;
282 nvm->ops.acquire = igb_acquire_nvm_82575;
283 nvm->ops.release = igb_release_nvm_82575;
284 if (nvm->word_size < (1 << 15))
285 nvm->ops.read = igb_read_nvm_eerd;
286 else
287 nvm->ops.read = igb_read_nvm_spi;
288 nvm->ops.write = igb_write_nvm_spi;
289 break;
290 case e1000_i350:
291 nvm->ops.validate = igb_validate_nvm_checksum_i350;
292 nvm->ops.update = igb_update_nvm_checksum_i350;
293 nvm->ops.acquire = igb_acquire_nvm_82575;
294 nvm->ops.release = igb_release_nvm_82575;
295 if (nvm->word_size < (1 << 15))
296 nvm->ops.read = igb_read_nvm_eerd;
297 else
298 nvm->ops.read = igb_read_nvm_spi;
299 nvm->ops.write = igb_write_nvm_spi;
300 break;
301 case e1000_i210:
302 nvm->ops.validate = igb_validate_nvm_checksum_i210;
303 nvm->ops.update = igb_update_nvm_checksum_i210;
304 nvm->ops.acquire = igb_acquire_nvm_i210;
305 nvm->ops.release = igb_release_nvm_i210;
306 nvm->ops.read = igb_read_nvm_srrd_i210;
307 nvm->ops.write = igb_write_nvm_srwr_i210;
308 nvm->ops.valid_led_default = igb_valid_led_default_i210;
309 break;
310 case e1000_i211:
311 nvm->ops.acquire = igb_acquire_nvm_i210;
312 nvm->ops.release = igb_release_nvm_i210;
313 nvm->ops.read = igb_read_nvm_i211;
314 nvm->ops.valid_led_default = igb_valid_led_default_i210;
315 nvm->ops.validate = NULL;
316 nvm->ops.update = NULL;
317 nvm->ops.write = NULL;
318 break;
319 default:
320 nvm->ops.validate = igb_validate_nvm_checksum;
321 nvm->ops.update = igb_update_nvm_checksum;
322 nvm->ops.acquire = igb_acquire_nvm_82575;
323 nvm->ops.release = igb_release_nvm_82575;
324 if (nvm->word_size < (1 << 15))
325 nvm->ops.read = igb_read_nvm_eerd;
326 else
327 nvm->ops.read = igb_read_nvm_spi;
328 nvm->ops.write = igb_write_nvm_spi;
329 break;
330 }
331
332 return 0;
333 }
334
335 /**
336 * igb_init_mac_params_82575 - Init MAC func ptrs.
337 * @hw: pointer to the HW structure
338 **/
339 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
340 {
341 struct e1000_mac_info *mac = &hw->mac;
342 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
343
344 /* Set mta register count */
345 mac->mta_reg_count = 128;
346 /* Set rar entry count */
347 switch (mac->type) {
348 case e1000_82576:
349 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
350 break;
351 case e1000_82580:
352 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
353 break;
354 case e1000_i350:
355 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
356 break;
357 default:
358 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
359 break;
360 }
361 /* reset */
362 if (mac->type >= e1000_82580)
363 mac->ops.reset_hw = igb_reset_hw_82580;
364 else
365 mac->ops.reset_hw = igb_reset_hw_82575;
366
367 if (mac->type >= e1000_i210) {
368 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
369 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
370
371 } else {
372 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
373 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
374 }
375
376 /* Set if part includes ASF firmware */
377 mac->asf_firmware_present = true;
378 /* Set if manageability features are enabled. */
379 mac->arc_subsystem_valid =
380 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
381 ? true : false;
382 /* enable EEE on i350 parts and later parts */
383 if (mac->type >= e1000_i350)
384 dev_spec->eee_disable = false;
385 else
386 dev_spec->eee_disable = true;
387 /* physical interface link setup */
388 mac->ops.setup_physical_interface =
389 (hw->phy.media_type == e1000_media_type_copper)
390 ? igb_setup_copper_link_82575
391 : igb_setup_serdes_link_82575;
392
393 return 0;
394 }
395
396 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
397 {
398 struct e1000_mac_info *mac = &hw->mac;
399 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
400 s32 ret_val;
401 u32 ctrl_ext = 0;
402
403 switch (hw->device_id) {
404 case E1000_DEV_ID_82575EB_COPPER:
405 case E1000_DEV_ID_82575EB_FIBER_SERDES:
406 case E1000_DEV_ID_82575GB_QUAD_COPPER:
407 mac->type = e1000_82575;
408 break;
409 case E1000_DEV_ID_82576:
410 case E1000_DEV_ID_82576_NS:
411 case E1000_DEV_ID_82576_NS_SERDES:
412 case E1000_DEV_ID_82576_FIBER:
413 case E1000_DEV_ID_82576_SERDES:
414 case E1000_DEV_ID_82576_QUAD_COPPER:
415 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
416 case E1000_DEV_ID_82576_SERDES_QUAD:
417 mac->type = e1000_82576;
418 break;
419 case E1000_DEV_ID_82580_COPPER:
420 case E1000_DEV_ID_82580_FIBER:
421 case E1000_DEV_ID_82580_QUAD_FIBER:
422 case E1000_DEV_ID_82580_SERDES:
423 case E1000_DEV_ID_82580_SGMII:
424 case E1000_DEV_ID_82580_COPPER_DUAL:
425 case E1000_DEV_ID_DH89XXCC_SGMII:
426 case E1000_DEV_ID_DH89XXCC_SERDES:
427 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
428 case E1000_DEV_ID_DH89XXCC_SFP:
429 mac->type = e1000_82580;
430 break;
431 case E1000_DEV_ID_I350_COPPER:
432 case E1000_DEV_ID_I350_FIBER:
433 case E1000_DEV_ID_I350_SERDES:
434 case E1000_DEV_ID_I350_SGMII:
435 mac->type = e1000_i350;
436 break;
437 case E1000_DEV_ID_I210_COPPER:
438 case E1000_DEV_ID_I210_COPPER_OEM1:
439 case E1000_DEV_ID_I210_COPPER_IT:
440 case E1000_DEV_ID_I210_FIBER:
441 case E1000_DEV_ID_I210_SERDES:
442 case E1000_DEV_ID_I210_SGMII:
443 mac->type = e1000_i210;
444 break;
445 case E1000_DEV_ID_I211_COPPER:
446 mac->type = e1000_i211;
447 break;
448 default:
449 return -E1000_ERR_MAC_INIT;
450 break;
451 }
452
453 /* Set media type */
454 /*
455 * The 82575 uses bits 22:23 for link mode. The mode can be changed
456 * based on the EEPROM. We cannot rely upon device ID. There
457 * is no distinguishable difference between fiber and internal
458 * SerDes mode on the 82575. There can be an external PHY attached
459 * on the SGMII interface. For this, we'll set sgmii_active to true.
460 */
461 hw->phy.media_type = e1000_media_type_copper;
462 dev_spec->sgmii_active = false;
463
464 ctrl_ext = rd32(E1000_CTRL_EXT);
465 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
466 case E1000_CTRL_EXT_LINK_MODE_SGMII:
467 dev_spec->sgmii_active = true;
468 break;
469 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
470 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
471 hw->phy.media_type = e1000_media_type_internal_serdes;
472 break;
473 default:
474 break;
475 }
476
477 /* mac initialization and operations */
478 ret_val = igb_init_mac_params_82575(hw);
479 if (ret_val)
480 goto out;
481
482 /* NVM initialization */
483 ret_val = igb_init_nvm_params_82575(hw);
484 if (ret_val)
485 goto out;
486
487 /* if part supports SR-IOV then initialize mailbox parameters */
488 switch (mac->type) {
489 case e1000_82576:
490 case e1000_i350:
491 igb_init_mbx_params_pf(hw);
492 break;
493 default:
494 break;
495 }
496
497 /* setup PHY parameters */
498 ret_val = igb_init_phy_params_82575(hw);
499
500 out:
501 return ret_val;
502 }
503
504 /**
505 * igb_acquire_phy_82575 - Acquire rights to access PHY
506 * @hw: pointer to the HW structure
507 *
508 * Acquire access rights to the correct PHY. This is a
509 * function pointer entry point called by the api module.
510 **/
511 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
512 {
513 u16 mask = E1000_SWFW_PHY0_SM;
514
515 if (hw->bus.func == E1000_FUNC_1)
516 mask = E1000_SWFW_PHY1_SM;
517 else if (hw->bus.func == E1000_FUNC_2)
518 mask = E1000_SWFW_PHY2_SM;
519 else if (hw->bus.func == E1000_FUNC_3)
520 mask = E1000_SWFW_PHY3_SM;
521
522 return hw->mac.ops.acquire_swfw_sync(hw, mask);
523 }
524
525 /**
526 * igb_release_phy_82575 - Release rights to access PHY
527 * @hw: pointer to the HW structure
528 *
529 * A wrapper to release access rights to the correct PHY. This is a
530 * function pointer entry point called by the api module.
531 **/
532 static void igb_release_phy_82575(struct e1000_hw *hw)
533 {
534 u16 mask = E1000_SWFW_PHY0_SM;
535
536 if (hw->bus.func == E1000_FUNC_1)
537 mask = E1000_SWFW_PHY1_SM;
538 else if (hw->bus.func == E1000_FUNC_2)
539 mask = E1000_SWFW_PHY2_SM;
540 else if (hw->bus.func == E1000_FUNC_3)
541 mask = E1000_SWFW_PHY3_SM;
542
543 hw->mac.ops.release_swfw_sync(hw, mask);
544 }
545
546 /**
547 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
548 * @hw: pointer to the HW structure
549 * @offset: register offset to be read
550 * @data: pointer to the read data
551 *
552 * Reads the PHY register at offset using the serial gigabit media independent
553 * interface and stores the retrieved information in data.
554 **/
555 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
556 u16 *data)
557 {
558 s32 ret_val = -E1000_ERR_PARAM;
559
560 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
561 hw_dbg("PHY Address %u is out of range\n", offset);
562 goto out;
563 }
564
565 ret_val = hw->phy.ops.acquire(hw);
566 if (ret_val)
567 goto out;
568
569 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
570
571 hw->phy.ops.release(hw);
572
573 out:
574 return ret_val;
575 }
576
577 /**
578 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
579 * @hw: pointer to the HW structure
580 * @offset: register offset to write to
581 * @data: data to write at register offset
582 *
583 * Writes the data to PHY register at the offset using the serial gigabit
584 * media independent interface.
585 **/
586 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
587 u16 data)
588 {
589 s32 ret_val = -E1000_ERR_PARAM;
590
591
592 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
593 hw_dbg("PHY Address %d is out of range\n", offset);
594 goto out;
595 }
596
597 ret_val = hw->phy.ops.acquire(hw);
598 if (ret_val)
599 goto out;
600
601 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
602
603 hw->phy.ops.release(hw);
604
605 out:
606 return ret_val;
607 }
608
609 /**
610 * igb_get_phy_id_82575 - Retrieve PHY addr and id
611 * @hw: pointer to the HW structure
612 *
613 * Retrieves the PHY address and ID for both PHY's which do and do not use
614 * sgmi interface.
615 **/
616 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
617 {
618 struct e1000_phy_info *phy = &hw->phy;
619 s32 ret_val = 0;
620 u16 phy_id;
621 u32 ctrl_ext;
622 u32 mdic;
623
624 /*
625 * For SGMII PHYs, we try the list of possible addresses until
626 * we find one that works. For non-SGMII PHYs
627 * (e.g. integrated copper PHYs), an address of 1 should
628 * work. The result of this function should mean phy->phy_addr
629 * and phy->id are set correctly.
630 */
631 if (!(igb_sgmii_active_82575(hw))) {
632 phy->addr = 1;
633 ret_val = igb_get_phy_id(hw);
634 goto out;
635 }
636
637 if (igb_sgmii_uses_mdio_82575(hw)) {
638 switch (hw->mac.type) {
639 case e1000_82575:
640 case e1000_82576:
641 mdic = rd32(E1000_MDIC);
642 mdic &= E1000_MDIC_PHY_MASK;
643 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
644 break;
645 case e1000_82580:
646 case e1000_i350:
647 case e1000_i210:
648 case e1000_i211:
649 mdic = rd32(E1000_MDICNFG);
650 mdic &= E1000_MDICNFG_PHY_MASK;
651 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
652 break;
653 default:
654 ret_val = -E1000_ERR_PHY;
655 goto out;
656 break;
657 }
658 ret_val = igb_get_phy_id(hw);
659 goto out;
660 }
661
662 /* Power on sgmii phy if it is disabled */
663 ctrl_ext = rd32(E1000_CTRL_EXT);
664 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
665 wrfl();
666 msleep(300);
667
668 /*
669 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
670 * Therefore, we need to test 1-7
671 */
672 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
673 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
674 if (ret_val == 0) {
675 hw_dbg("Vendor ID 0x%08X read at address %u\n",
676 phy_id, phy->addr);
677 /*
678 * At the time of this writing, The M88 part is
679 * the only supported SGMII PHY product.
680 */
681 if (phy_id == M88_VENDOR)
682 break;
683 } else {
684 hw_dbg("PHY address %u was unreadable\n", phy->addr);
685 }
686 }
687
688 /* A valid PHY type couldn't be found. */
689 if (phy->addr == 8) {
690 phy->addr = 0;
691 ret_val = -E1000_ERR_PHY;
692 goto out;
693 } else {
694 ret_val = igb_get_phy_id(hw);
695 }
696
697 /* restore previous sfp cage power state */
698 wr32(E1000_CTRL_EXT, ctrl_ext);
699
700 out:
701 return ret_val;
702 }
703
704 /**
705 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
706 * @hw: pointer to the HW structure
707 *
708 * Resets the PHY using the serial gigabit media independent interface.
709 **/
710 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
711 {
712 s32 ret_val;
713
714 /*
715 * This isn't a true "hard" reset, but is the only reset
716 * available to us at this time.
717 */
718
719 hw_dbg("Soft resetting SGMII attached PHY...\n");
720
721 /*
722 * SFP documentation requires the following to configure the SPF module
723 * to work on SGMII. No further documentation is given.
724 */
725 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
726 if (ret_val)
727 goto out;
728
729 ret_val = igb_phy_sw_reset(hw);
730
731 out:
732 return ret_val;
733 }
734
735 /**
736 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
737 * @hw: pointer to the HW structure
738 * @active: true to enable LPLU, false to disable
739 *
740 * Sets the LPLU D0 state according to the active flag. When
741 * activating LPLU this function also disables smart speed
742 * and vice versa. LPLU will not be activated unless the
743 * device autonegotiation advertisement meets standards of
744 * either 10 or 10/100 or 10/100/1000 at all duplexes.
745 * This is a function pointer entry point only called by
746 * PHY setup routines.
747 **/
748 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
749 {
750 struct e1000_phy_info *phy = &hw->phy;
751 s32 ret_val;
752 u16 data;
753
754 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
755 if (ret_val)
756 goto out;
757
758 if (active) {
759 data |= IGP02E1000_PM_D0_LPLU;
760 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
761 data);
762 if (ret_val)
763 goto out;
764
765 /* When LPLU is enabled, we should disable SmartSpeed */
766 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
767 &data);
768 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
769 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
770 data);
771 if (ret_val)
772 goto out;
773 } else {
774 data &= ~IGP02E1000_PM_D0_LPLU;
775 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
776 data);
777 /*
778 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
779 * during Dx states where the power conservation is most
780 * important. During driver activity we should enable
781 * SmartSpeed, so performance is maintained.
782 */
783 if (phy->smart_speed == e1000_smart_speed_on) {
784 ret_val = phy->ops.read_reg(hw,
785 IGP01E1000_PHY_PORT_CONFIG, &data);
786 if (ret_val)
787 goto out;
788
789 data |= IGP01E1000_PSCFR_SMART_SPEED;
790 ret_val = phy->ops.write_reg(hw,
791 IGP01E1000_PHY_PORT_CONFIG, data);
792 if (ret_val)
793 goto out;
794 } else if (phy->smart_speed == e1000_smart_speed_off) {
795 ret_val = phy->ops.read_reg(hw,
796 IGP01E1000_PHY_PORT_CONFIG, &data);
797 if (ret_val)
798 goto out;
799
800 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
801 ret_val = phy->ops.write_reg(hw,
802 IGP01E1000_PHY_PORT_CONFIG, data);
803 if (ret_val)
804 goto out;
805 }
806 }
807
808 out:
809 return ret_val;
810 }
811
812 /**
813 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
814 * @hw: pointer to the HW structure
815 * @active: true to enable LPLU, false to disable
816 *
817 * Sets the LPLU D0 state according to the active flag. When
818 * activating LPLU this function also disables smart speed
819 * and vice versa. LPLU will not be activated unless the
820 * device autonegotiation advertisement meets standards of
821 * either 10 or 10/100 or 10/100/1000 at all duplexes.
822 * This is a function pointer entry point only called by
823 * PHY setup routines.
824 **/
825 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
826 {
827 struct e1000_phy_info *phy = &hw->phy;
828 s32 ret_val = 0;
829 u16 data;
830
831 data = rd32(E1000_82580_PHY_POWER_MGMT);
832
833 if (active) {
834 data |= E1000_82580_PM_D0_LPLU;
835
836 /* When LPLU is enabled, we should disable SmartSpeed */
837 data &= ~E1000_82580_PM_SPD;
838 } else {
839 data &= ~E1000_82580_PM_D0_LPLU;
840
841 /*
842 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
843 * during Dx states where the power conservation is most
844 * important. During driver activity we should enable
845 * SmartSpeed, so performance is maintained.
846 */
847 if (phy->smart_speed == e1000_smart_speed_on)
848 data |= E1000_82580_PM_SPD;
849 else if (phy->smart_speed == e1000_smart_speed_off)
850 data &= ~E1000_82580_PM_SPD; }
851
852 wr32(E1000_82580_PHY_POWER_MGMT, data);
853 return ret_val;
854 }
855
856 /**
857 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
858 * @hw: pointer to the HW structure
859 * @active: boolean used to enable/disable lplu
860 *
861 * Success returns 0, Failure returns 1
862 *
863 * The low power link up (lplu) state is set to the power management level D3
864 * and SmartSpeed is disabled when active is true, else clear lplu for D3
865 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
866 * is used during Dx states where the power conservation is most important.
867 * During driver activity, SmartSpeed should be enabled so performance is
868 * maintained.
869 **/
870 s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
871 {
872 struct e1000_phy_info *phy = &hw->phy;
873 s32 ret_val = 0;
874 u16 data;
875
876 data = rd32(E1000_82580_PHY_POWER_MGMT);
877
878 if (!active) {
879 data &= ~E1000_82580_PM_D3_LPLU;
880 /*
881 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
882 * during Dx states where the power conservation is most
883 * important. During driver activity we should enable
884 * SmartSpeed, so performance is maintained.
885 */
886 if (phy->smart_speed == e1000_smart_speed_on)
887 data |= E1000_82580_PM_SPD;
888 else if (phy->smart_speed == e1000_smart_speed_off)
889 data &= ~E1000_82580_PM_SPD;
890 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
891 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
892 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
893 data |= E1000_82580_PM_D3_LPLU;
894 /* When LPLU is enabled, we should disable SmartSpeed */
895 data &= ~E1000_82580_PM_SPD;
896 }
897
898 wr32(E1000_82580_PHY_POWER_MGMT, data);
899 return ret_val;
900 }
901
902 /**
903 * igb_acquire_nvm_82575 - Request for access to EEPROM
904 * @hw: pointer to the HW structure
905 *
906 * Acquire the necessary semaphores for exclusive access to the EEPROM.
907 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
908 * Return successful if access grant bit set, else clear the request for
909 * EEPROM access and return -E1000_ERR_NVM (-1).
910 **/
911 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
912 {
913 s32 ret_val;
914
915 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
916 if (ret_val)
917 goto out;
918
919 ret_val = igb_acquire_nvm(hw);
920
921 if (ret_val)
922 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
923
924 out:
925 return ret_val;
926 }
927
928 /**
929 * igb_release_nvm_82575 - Release exclusive access to EEPROM
930 * @hw: pointer to the HW structure
931 *
932 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
933 * then release the semaphores acquired.
934 **/
935 static void igb_release_nvm_82575(struct e1000_hw *hw)
936 {
937 igb_release_nvm(hw);
938 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
939 }
940
941 /**
942 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
943 * @hw: pointer to the HW structure
944 * @mask: specifies which semaphore to acquire
945 *
946 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
947 * will also specify which port we're acquiring the lock for.
948 **/
949 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
950 {
951 u32 swfw_sync;
952 u32 swmask = mask;
953 u32 fwmask = mask << 16;
954 s32 ret_val = 0;
955 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
956
957 while (i < timeout) {
958 if (igb_get_hw_semaphore(hw)) {
959 ret_val = -E1000_ERR_SWFW_SYNC;
960 goto out;
961 }
962
963 swfw_sync = rd32(E1000_SW_FW_SYNC);
964 if (!(swfw_sync & (fwmask | swmask)))
965 break;
966
967 /*
968 * Firmware currently using resource (fwmask)
969 * or other software thread using resource (swmask)
970 */
971 igb_put_hw_semaphore(hw);
972 mdelay(5);
973 i++;
974 }
975
976 if (i == timeout) {
977 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
978 ret_val = -E1000_ERR_SWFW_SYNC;
979 goto out;
980 }
981
982 swfw_sync |= swmask;
983 wr32(E1000_SW_FW_SYNC, swfw_sync);
984
985 igb_put_hw_semaphore(hw);
986
987 out:
988 return ret_val;
989 }
990
991 /**
992 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
993 * @hw: pointer to the HW structure
994 * @mask: specifies which semaphore to acquire
995 *
996 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
997 * will also specify which port we're releasing the lock for.
998 **/
999 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1000 {
1001 u32 swfw_sync;
1002
1003 while (igb_get_hw_semaphore(hw) != 0);
1004 /* Empty */
1005
1006 swfw_sync = rd32(E1000_SW_FW_SYNC);
1007 swfw_sync &= ~mask;
1008 wr32(E1000_SW_FW_SYNC, swfw_sync);
1009
1010 igb_put_hw_semaphore(hw);
1011 }
1012
1013 /**
1014 * igb_get_cfg_done_82575 - Read config done bit
1015 * @hw: pointer to the HW structure
1016 *
1017 * Read the management control register for the config done bit for
1018 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1019 * to read the config done bit, so an error is *ONLY* logged and returns
1020 * 0. If we were to return with error, EEPROM-less silicon
1021 * would not be able to be reset or change link.
1022 **/
1023 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1024 {
1025 s32 timeout = PHY_CFG_TIMEOUT;
1026 s32 ret_val = 0;
1027 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1028
1029 if (hw->bus.func == 1)
1030 mask = E1000_NVM_CFG_DONE_PORT_1;
1031 else if (hw->bus.func == E1000_FUNC_2)
1032 mask = E1000_NVM_CFG_DONE_PORT_2;
1033 else if (hw->bus.func == E1000_FUNC_3)
1034 mask = E1000_NVM_CFG_DONE_PORT_3;
1035
1036 while (timeout) {
1037 if (rd32(E1000_EEMNGCTL) & mask)
1038 break;
1039 msleep(1);
1040 timeout--;
1041 }
1042 if (!timeout)
1043 hw_dbg("MNG configuration cycle has not completed.\n");
1044
1045 /* If EEPROM is not marked present, init the PHY manually */
1046 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1047 (hw->phy.type == e1000_phy_igp_3))
1048 igb_phy_init_script_igp3(hw);
1049
1050 return ret_val;
1051 }
1052
1053 /**
1054 * igb_check_for_link_82575 - Check for link
1055 * @hw: pointer to the HW structure
1056 *
1057 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1058 * use the generic interface for determining link.
1059 **/
1060 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1061 {
1062 s32 ret_val;
1063 u16 speed, duplex;
1064
1065 if (hw->phy.media_type != e1000_media_type_copper) {
1066 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1067 &duplex);
1068 /*
1069 * Use this flag to determine if link needs to be checked or
1070 * not. If we have link clear the flag so that we do not
1071 * continue to check for link.
1072 */
1073 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1074
1075 /* Configure Flow Control now that Auto-Neg has completed.
1076 * First, we need to restore the desired flow control
1077 * settings because we may have had to re-autoneg with a
1078 * different link partner.
1079 */
1080 ret_val = igb_config_fc_after_link_up(hw);
1081 if (ret_val)
1082 hw_dbg("Error configuring flow control\n");
1083 } else {
1084 ret_val = igb_check_for_copper_link(hw);
1085 }
1086
1087 return ret_val;
1088 }
1089
1090 /**
1091 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1092 * @hw: pointer to the HW structure
1093 **/
1094 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1095 {
1096 u32 reg;
1097
1098
1099 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1100 !igb_sgmii_active_82575(hw))
1101 return;
1102
1103 /* Enable PCS to turn on link */
1104 reg = rd32(E1000_PCS_CFG0);
1105 reg |= E1000_PCS_CFG_PCS_EN;
1106 wr32(E1000_PCS_CFG0, reg);
1107
1108 /* Power up the laser */
1109 reg = rd32(E1000_CTRL_EXT);
1110 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1111 wr32(E1000_CTRL_EXT, reg);
1112
1113 /* flush the write to verify completion */
1114 wrfl();
1115 msleep(1);
1116 }
1117
1118 /**
1119 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1120 * @hw: pointer to the HW structure
1121 * @speed: stores the current speed
1122 * @duplex: stores the current duplex
1123 *
1124 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1125 * duplex, then store the values in the pointers provided.
1126 **/
1127 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1128 u16 *duplex)
1129 {
1130 struct e1000_mac_info *mac = &hw->mac;
1131 u32 pcs;
1132
1133 /* Set up defaults for the return values of this function */
1134 mac->serdes_has_link = false;
1135 *speed = 0;
1136 *duplex = 0;
1137
1138 /*
1139 * Read the PCS Status register for link state. For non-copper mode,
1140 * the status register is not accurate. The PCS status register is
1141 * used instead.
1142 */
1143 pcs = rd32(E1000_PCS_LSTAT);
1144
1145 /*
1146 * The link up bit determines when link is up on autoneg. The sync ok
1147 * gets set once both sides sync up and agree upon link. Stable link
1148 * can be determined by checking for both link up and link sync ok
1149 */
1150 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1151 mac->serdes_has_link = true;
1152
1153 /* Detect and store PCS speed */
1154 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1155 *speed = SPEED_1000;
1156 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1157 *speed = SPEED_100;
1158 } else {
1159 *speed = SPEED_10;
1160 }
1161
1162 /* Detect and store PCS duplex */
1163 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1164 *duplex = FULL_DUPLEX;
1165 } else {
1166 *duplex = HALF_DUPLEX;
1167 }
1168 }
1169
1170 return 0;
1171 }
1172
1173 /**
1174 * igb_shutdown_serdes_link_82575 - Remove link during power down
1175 * @hw: pointer to the HW structure
1176 *
1177 * In the case of fiber serdes, shut down optics and PCS on driver unload
1178 * when management pass thru is not enabled.
1179 **/
1180 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1181 {
1182 u32 reg;
1183
1184 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1185 igb_sgmii_active_82575(hw))
1186 return;
1187
1188 if (!igb_enable_mng_pass_thru(hw)) {
1189 /* Disable PCS to turn off link */
1190 reg = rd32(E1000_PCS_CFG0);
1191 reg &= ~E1000_PCS_CFG_PCS_EN;
1192 wr32(E1000_PCS_CFG0, reg);
1193
1194 /* shutdown the laser */
1195 reg = rd32(E1000_CTRL_EXT);
1196 reg |= E1000_CTRL_EXT_SDP3_DATA;
1197 wr32(E1000_CTRL_EXT, reg);
1198
1199 /* flush the write to verify completion */
1200 wrfl();
1201 msleep(1);
1202 }
1203 }
1204
1205 /**
1206 * igb_reset_hw_82575 - Reset hardware
1207 * @hw: pointer to the HW structure
1208 *
1209 * This resets the hardware into a known state. This is a
1210 * function pointer entry point called by the api module.
1211 **/
1212 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1213 {
1214 u32 ctrl, icr;
1215 s32 ret_val;
1216
1217 /*
1218 * Prevent the PCI-E bus from sticking if there is no TLP connection
1219 * on the last TLP read/write transaction when MAC is reset.
1220 */
1221 ret_val = igb_disable_pcie_master(hw);
1222 if (ret_val)
1223 hw_dbg("PCI-E Master disable polling has failed.\n");
1224
1225 /* set the completion timeout for interface */
1226 ret_val = igb_set_pcie_completion_timeout(hw);
1227 if (ret_val) {
1228 hw_dbg("PCI-E Set completion timeout has failed.\n");
1229 }
1230
1231 hw_dbg("Masking off all interrupts\n");
1232 wr32(E1000_IMC, 0xffffffff);
1233
1234 wr32(E1000_RCTL, 0);
1235 wr32(E1000_TCTL, E1000_TCTL_PSP);
1236 wrfl();
1237
1238 msleep(10);
1239
1240 ctrl = rd32(E1000_CTRL);
1241
1242 hw_dbg("Issuing a global reset to MAC\n");
1243 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1244
1245 ret_val = igb_get_auto_rd_done(hw);
1246 if (ret_val) {
1247 /*
1248 * When auto config read does not complete, do not
1249 * return with an error. This can happen in situations
1250 * where there is no eeprom and prevents getting link.
1251 */
1252 hw_dbg("Auto Read Done did not complete\n");
1253 }
1254
1255 /* If EEPROM is not present, run manual init scripts */
1256 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1257 igb_reset_init_script_82575(hw);
1258
1259 /* Clear any pending interrupt events. */
1260 wr32(E1000_IMC, 0xffffffff);
1261 icr = rd32(E1000_ICR);
1262
1263 /* Install any alternate MAC address into RAR0 */
1264 ret_val = igb_check_alt_mac_addr(hw);
1265
1266 return ret_val;
1267 }
1268
1269 /**
1270 * igb_init_hw_82575 - Initialize hardware
1271 * @hw: pointer to the HW structure
1272 *
1273 * This inits the hardware readying it for operation.
1274 **/
1275 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1276 {
1277 struct e1000_mac_info *mac = &hw->mac;
1278 s32 ret_val;
1279 u16 i, rar_count = mac->rar_entry_count;
1280
1281 /* Initialize identification LED */
1282 ret_val = igb_id_led_init(hw);
1283 if (ret_val) {
1284 hw_dbg("Error initializing identification LED\n");
1285 /* This is not fatal and we should not stop init due to this */
1286 }
1287
1288 /* Disabling VLAN filtering */
1289 hw_dbg("Initializing the IEEE VLAN\n");
1290 if (hw->mac.type == e1000_i350)
1291 igb_clear_vfta_i350(hw);
1292 else
1293 igb_clear_vfta(hw);
1294
1295 /* Setup the receive address */
1296 igb_init_rx_addrs(hw, rar_count);
1297
1298 /* Zero out the Multicast HASH table */
1299 hw_dbg("Zeroing the MTA\n");
1300 for (i = 0; i < mac->mta_reg_count; i++)
1301 array_wr32(E1000_MTA, i, 0);
1302
1303 /* Zero out the Unicast HASH table */
1304 hw_dbg("Zeroing the UTA\n");
1305 for (i = 0; i < mac->uta_reg_count; i++)
1306 array_wr32(E1000_UTA, i, 0);
1307
1308 /* Setup link and flow control */
1309 ret_val = igb_setup_link(hw);
1310
1311 /*
1312 * Clear all of the statistics registers (clear on read). It is
1313 * important that we do this after we have tried to establish link
1314 * because the symbol error count will increment wildly if there
1315 * is no link.
1316 */
1317 igb_clear_hw_cntrs_82575(hw);
1318 return ret_val;
1319 }
1320
1321 /**
1322 * igb_setup_copper_link_82575 - Configure copper link settings
1323 * @hw: pointer to the HW structure
1324 *
1325 * Configures the link for auto-neg or forced speed and duplex. Then we check
1326 * for link, once link is established calls to configure collision distance
1327 * and flow control are called.
1328 **/
1329 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1330 {
1331 u32 ctrl;
1332 s32 ret_val;
1333 u32 phpm_reg;
1334
1335 ctrl = rd32(E1000_CTRL);
1336 ctrl |= E1000_CTRL_SLU;
1337 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1338 wr32(E1000_CTRL, ctrl);
1339
1340 /* Clear Go Link Disconnect bit */
1341 if (hw->mac.type >= e1000_82580) {
1342 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1343 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1344 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1345 }
1346
1347 ret_val = igb_setup_serdes_link_82575(hw);
1348 if (ret_val)
1349 goto out;
1350
1351 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1352 /* allow time for SFP cage time to power up phy */
1353 msleep(300);
1354
1355 ret_val = hw->phy.ops.reset(hw);
1356 if (ret_val) {
1357 hw_dbg("Error resetting the PHY.\n");
1358 goto out;
1359 }
1360 }
1361 switch (hw->phy.type) {
1362 case e1000_phy_i210:
1363 case e1000_phy_m88:
1364 if (hw->phy.id == I347AT4_E_PHY_ID ||
1365 hw->phy.id == M88E1112_E_PHY_ID)
1366 ret_val = igb_copper_link_setup_m88_gen2(hw);
1367 else
1368 ret_val = igb_copper_link_setup_m88(hw);
1369 break;
1370 case e1000_phy_igp_3:
1371 ret_val = igb_copper_link_setup_igp(hw);
1372 break;
1373 case e1000_phy_82580:
1374 ret_val = igb_copper_link_setup_82580(hw);
1375 break;
1376 default:
1377 ret_val = -E1000_ERR_PHY;
1378 break;
1379 }
1380
1381 if (ret_val)
1382 goto out;
1383
1384 ret_val = igb_setup_copper_link(hw);
1385 out:
1386 return ret_val;
1387 }
1388
1389 /**
1390 * igb_setup_serdes_link_82575 - Setup link for serdes
1391 * @hw: pointer to the HW structure
1392 *
1393 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1394 * used on copper connections where the serialized gigabit media independent
1395 * interface (sgmii), or serdes fiber is being used. Configures the link
1396 * for auto-negotiation or forces speed/duplex.
1397 **/
1398 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1399 {
1400 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1401 bool pcs_autoneg;
1402 s32 ret_val = E1000_SUCCESS;
1403 u16 data;
1404
1405 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1406 !igb_sgmii_active_82575(hw))
1407 return ret_val;
1408
1409
1410 /*
1411 * On the 82575, SerDes loopback mode persists until it is
1412 * explicitly turned off or a power cycle is performed. A read to
1413 * the register does not indicate its status. Therefore, we ensure
1414 * loopback mode is disabled during initialization.
1415 */
1416 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1417
1418 /* power on the sfp cage if present */
1419 ctrl_ext = rd32(E1000_CTRL_EXT);
1420 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1421 wr32(E1000_CTRL_EXT, ctrl_ext);
1422
1423 ctrl_reg = rd32(E1000_CTRL);
1424 ctrl_reg |= E1000_CTRL_SLU;
1425
1426 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1427 /* set both sw defined pins */
1428 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1429
1430 /* Set switch control to serdes energy detect */
1431 reg = rd32(E1000_CONNSW);
1432 reg |= E1000_CONNSW_ENRGSRC;
1433 wr32(E1000_CONNSW, reg);
1434 }
1435
1436 reg = rd32(E1000_PCS_LCTL);
1437
1438 /* default pcs_autoneg to the same setting as mac autoneg */
1439 pcs_autoneg = hw->mac.autoneg;
1440
1441 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1442 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1443 /* sgmii mode lets the phy handle forcing speed/duplex */
1444 pcs_autoneg = true;
1445 /* autoneg time out should be disabled for SGMII mode */
1446 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1447 break;
1448 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1449 /* disable PCS autoneg and support parallel detect only */
1450 pcs_autoneg = false;
1451 default:
1452 if (hw->mac.type == e1000_82575 ||
1453 hw->mac.type == e1000_82576) {
1454 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1455 if (ret_val) {
1456 printk(KERN_DEBUG "NVM Read Error\n\n");
1457 return ret_val;
1458 }
1459
1460 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1461 pcs_autoneg = false;
1462 }
1463
1464 /*
1465 * non-SGMII modes only supports a speed of 1000/Full for the
1466 * link so it is best to just force the MAC and let the pcs
1467 * link either autoneg or be forced to 1000/Full
1468 */
1469 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1470 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1471
1472 /* set speed of 1000/Full if speed/duplex is forced */
1473 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1474 break;
1475 }
1476
1477 wr32(E1000_CTRL, ctrl_reg);
1478
1479 /*
1480 * New SerDes mode allows for forcing speed or autonegotiating speed
1481 * at 1gb. Autoneg should be default set by most drivers. This is the
1482 * mode that will be compatible with older link partners and switches.
1483 * However, both are supported by the hardware and some drivers/tools.
1484 */
1485 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1486 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1487
1488 if (pcs_autoneg) {
1489 /* Set PCS register for autoneg */
1490 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1491 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1492
1493 /* Disable force flow control for autoneg */
1494 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1495
1496 /* Configure flow control advertisement for autoneg */
1497 anadv_reg = rd32(E1000_PCS_ANADV);
1498 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1499 switch (hw->fc.requested_mode) {
1500 case e1000_fc_full:
1501 case e1000_fc_rx_pause:
1502 anadv_reg |= E1000_TXCW_ASM_DIR;
1503 anadv_reg |= E1000_TXCW_PAUSE;
1504 break;
1505 case e1000_fc_tx_pause:
1506 anadv_reg |= E1000_TXCW_ASM_DIR;
1507 break;
1508 default:
1509 break;
1510 }
1511 wr32(E1000_PCS_ANADV, anadv_reg);
1512
1513 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1514 } else {
1515 /* Set PCS register for forced link */
1516 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1517
1518 /* Force flow control for forced link */
1519 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1520
1521 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1522 }
1523
1524 wr32(E1000_PCS_LCTL, reg);
1525
1526 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1527 igb_force_mac_fc(hw);
1528
1529 return ret_val;
1530 }
1531
1532 /**
1533 * igb_sgmii_active_82575 - Return sgmii state
1534 * @hw: pointer to the HW structure
1535 *
1536 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1537 * which can be enabled for use in the embedded applications. Simply
1538 * return the current state of the sgmii interface.
1539 **/
1540 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1541 {
1542 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1543 return dev_spec->sgmii_active;
1544 }
1545
1546 /**
1547 * igb_reset_init_script_82575 - Inits HW defaults after reset
1548 * @hw: pointer to the HW structure
1549 *
1550 * Inits recommended HW defaults after a reset when there is no EEPROM
1551 * detected. This is only for the 82575.
1552 **/
1553 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1554 {
1555 if (hw->mac.type == e1000_82575) {
1556 hw_dbg("Running reset init script for 82575\n");
1557 /* SerDes configuration via SERDESCTRL */
1558 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1559 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1560 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1561 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1562
1563 /* CCM configuration via CCMCTL register */
1564 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1565 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1566
1567 /* PCIe lanes configuration */
1568 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1569 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1570 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1571 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1572
1573 /* PCIe PLL Configuration */
1574 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1575 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1576 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1577 }
1578
1579 return 0;
1580 }
1581
1582 /**
1583 * igb_read_mac_addr_82575 - Read device MAC address
1584 * @hw: pointer to the HW structure
1585 **/
1586 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1587 {
1588 s32 ret_val = 0;
1589
1590 /*
1591 * If there's an alternate MAC address place it in RAR0
1592 * so that it will override the Si installed default perm
1593 * address.
1594 */
1595 ret_val = igb_check_alt_mac_addr(hw);
1596 if (ret_val)
1597 goto out;
1598
1599 ret_val = igb_read_mac_addr(hw);
1600
1601 out:
1602 return ret_val;
1603 }
1604
1605 /**
1606 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1607 * @hw: pointer to the HW structure
1608 *
1609 * In the case of a PHY power down to save power, or to turn off link during a
1610 * driver unload, or wake on lan is not enabled, remove the link.
1611 **/
1612 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1613 {
1614 /* If the management interface is not enabled, then power down */
1615 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1616 igb_power_down_phy_copper(hw);
1617 }
1618
1619 /**
1620 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1621 * @hw: pointer to the HW structure
1622 *
1623 * Clears the hardware counters by reading the counter registers.
1624 **/
1625 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1626 {
1627 igb_clear_hw_cntrs_base(hw);
1628
1629 rd32(E1000_PRC64);
1630 rd32(E1000_PRC127);
1631 rd32(E1000_PRC255);
1632 rd32(E1000_PRC511);
1633 rd32(E1000_PRC1023);
1634 rd32(E1000_PRC1522);
1635 rd32(E1000_PTC64);
1636 rd32(E1000_PTC127);
1637 rd32(E1000_PTC255);
1638 rd32(E1000_PTC511);
1639 rd32(E1000_PTC1023);
1640 rd32(E1000_PTC1522);
1641
1642 rd32(E1000_ALGNERRC);
1643 rd32(E1000_RXERRC);
1644 rd32(E1000_TNCRS);
1645 rd32(E1000_CEXTERR);
1646 rd32(E1000_TSCTC);
1647 rd32(E1000_TSCTFC);
1648
1649 rd32(E1000_MGTPRC);
1650 rd32(E1000_MGTPDC);
1651 rd32(E1000_MGTPTC);
1652
1653 rd32(E1000_IAC);
1654 rd32(E1000_ICRXOC);
1655
1656 rd32(E1000_ICRXPTC);
1657 rd32(E1000_ICRXATC);
1658 rd32(E1000_ICTXPTC);
1659 rd32(E1000_ICTXATC);
1660 rd32(E1000_ICTXQEC);
1661 rd32(E1000_ICTXQMTC);
1662 rd32(E1000_ICRXDMTC);
1663
1664 rd32(E1000_CBTMPC);
1665 rd32(E1000_HTDPMC);
1666 rd32(E1000_CBRMPC);
1667 rd32(E1000_RPTHC);
1668 rd32(E1000_HGPTC);
1669 rd32(E1000_HTCBDPC);
1670 rd32(E1000_HGORCL);
1671 rd32(E1000_HGORCH);
1672 rd32(E1000_HGOTCL);
1673 rd32(E1000_HGOTCH);
1674 rd32(E1000_LENERRS);
1675
1676 /* This register should not be read in copper configurations */
1677 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1678 igb_sgmii_active_82575(hw))
1679 rd32(E1000_SCVPC);
1680 }
1681
1682 /**
1683 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1684 * @hw: pointer to the HW structure
1685 *
1686 * After rx enable if managability is enabled then there is likely some
1687 * bad data at the start of the fifo and possibly in the DMA fifo. This
1688 * function clears the fifos and flushes any packets that came in as rx was
1689 * being enabled.
1690 **/
1691 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1692 {
1693 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1694 int i, ms_wait;
1695
1696 if (hw->mac.type != e1000_82575 ||
1697 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1698 return;
1699
1700 /* Disable all RX queues */
1701 for (i = 0; i < 4; i++) {
1702 rxdctl[i] = rd32(E1000_RXDCTL(i));
1703 wr32(E1000_RXDCTL(i),
1704 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1705 }
1706 /* Poll all queues to verify they have shut down */
1707 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1708 msleep(1);
1709 rx_enabled = 0;
1710 for (i = 0; i < 4; i++)
1711 rx_enabled |= rd32(E1000_RXDCTL(i));
1712 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1713 break;
1714 }
1715
1716 if (ms_wait == 10)
1717 hw_dbg("Queue disable timed out after 10ms\n");
1718
1719 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1720 * incoming packets are rejected. Set enable and wait 2ms so that
1721 * any packet that was coming in as RCTL.EN was set is flushed
1722 */
1723 rfctl = rd32(E1000_RFCTL);
1724 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1725
1726 rlpml = rd32(E1000_RLPML);
1727 wr32(E1000_RLPML, 0);
1728
1729 rctl = rd32(E1000_RCTL);
1730 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1731 temp_rctl |= E1000_RCTL_LPE;
1732
1733 wr32(E1000_RCTL, temp_rctl);
1734 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1735 wrfl();
1736 msleep(2);
1737
1738 /* Enable RX queues that were previously enabled and restore our
1739 * previous state
1740 */
1741 for (i = 0; i < 4; i++)
1742 wr32(E1000_RXDCTL(i), rxdctl[i]);
1743 wr32(E1000_RCTL, rctl);
1744 wrfl();
1745
1746 wr32(E1000_RLPML, rlpml);
1747 wr32(E1000_RFCTL, rfctl);
1748
1749 /* Flush receive errors generated by workaround */
1750 rd32(E1000_ROC);
1751 rd32(E1000_RNBC);
1752 rd32(E1000_MPC);
1753 }
1754
1755 /**
1756 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1757 * @hw: pointer to the HW structure
1758 *
1759 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1760 * however the hardware default for these parts is 500us to 1ms which is less
1761 * than the 10ms recommended by the pci-e spec. To address this we need to
1762 * increase the value to either 10ms to 200ms for capability version 1 config,
1763 * or 16ms to 55ms for version 2.
1764 **/
1765 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1766 {
1767 u32 gcr = rd32(E1000_GCR);
1768 s32 ret_val = 0;
1769 u16 pcie_devctl2;
1770
1771 /* only take action if timeout value is defaulted to 0 */
1772 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1773 goto out;
1774
1775 /*
1776 * if capababilities version is type 1 we can write the
1777 * timeout of 10ms to 200ms through the GCR register
1778 */
1779 if (!(gcr & E1000_GCR_CAP_VER2)) {
1780 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1781 goto out;
1782 }
1783
1784 /*
1785 * for version 2 capabilities we need to write the config space
1786 * directly in order to set the completion timeout value for
1787 * 16ms to 55ms
1788 */
1789 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1790 &pcie_devctl2);
1791 if (ret_val)
1792 goto out;
1793
1794 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1795
1796 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1797 &pcie_devctl2);
1798 out:
1799 /* disable completion timeout resend */
1800 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1801
1802 wr32(E1000_GCR, gcr);
1803 return ret_val;
1804 }
1805
1806 /**
1807 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1808 * @hw: pointer to the hardware struct
1809 * @enable: state to enter, either enabled or disabled
1810 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1811 *
1812 * enables/disables L2 switch anti-spoofing functionality.
1813 **/
1814 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1815 {
1816 u32 dtxswc;
1817
1818 switch (hw->mac.type) {
1819 case e1000_82576:
1820 case e1000_i350:
1821 dtxswc = rd32(E1000_DTXSWC);
1822 if (enable) {
1823 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1824 E1000_DTXSWC_VLAN_SPOOF_MASK);
1825 /* The PF can spoof - it has to in order to
1826 * support emulation mode NICs */
1827 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1828 } else {
1829 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1830 E1000_DTXSWC_VLAN_SPOOF_MASK);
1831 }
1832 wr32(E1000_DTXSWC, dtxswc);
1833 break;
1834 default:
1835 break;
1836 }
1837 }
1838
1839 /**
1840 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1841 * @hw: pointer to the hardware struct
1842 * @enable: state to enter, either enabled or disabled
1843 *
1844 * enables/disables L2 switch loopback functionality.
1845 **/
1846 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1847 {
1848 u32 dtxswc;
1849
1850 switch (hw->mac.type) {
1851 case e1000_82576:
1852 dtxswc = rd32(E1000_DTXSWC);
1853 if (enable)
1854 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1855 else
1856 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1857 wr32(E1000_DTXSWC, dtxswc);
1858 break;
1859 case e1000_i350:
1860 dtxswc = rd32(E1000_TXSWC);
1861 if (enable)
1862 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1863 else
1864 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1865 wr32(E1000_TXSWC, dtxswc);
1866 break;
1867 default:
1868 /* Currently no other hardware supports loopback */
1869 break;
1870 }
1871
1872
1873 }
1874
1875 /**
1876 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1877 * @hw: pointer to the hardware struct
1878 * @enable: state to enter, either enabled or disabled
1879 *
1880 * enables/disables replication of packets across multiple pools.
1881 **/
1882 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1883 {
1884 u32 vt_ctl = rd32(E1000_VT_CTL);
1885
1886 if (enable)
1887 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1888 else
1889 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1890
1891 wr32(E1000_VT_CTL, vt_ctl);
1892 }
1893
1894 /**
1895 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1896 * @hw: pointer to the HW structure
1897 * @offset: register offset to be read
1898 * @data: pointer to the read data
1899 *
1900 * Reads the MDI control register in the PHY at offset and stores the
1901 * information read to data.
1902 **/
1903 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1904 {
1905 s32 ret_val;
1906
1907
1908 ret_val = hw->phy.ops.acquire(hw);
1909 if (ret_val)
1910 goto out;
1911
1912 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1913
1914 hw->phy.ops.release(hw);
1915
1916 out:
1917 return ret_val;
1918 }
1919
1920 /**
1921 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1922 * @hw: pointer to the HW structure
1923 * @offset: register offset to write to
1924 * @data: data to write to register at offset
1925 *
1926 * Writes data to MDI control register in the PHY at offset.
1927 **/
1928 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1929 {
1930 s32 ret_val;
1931
1932
1933 ret_val = hw->phy.ops.acquire(hw);
1934 if (ret_val)
1935 goto out;
1936
1937 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1938
1939 hw->phy.ops.release(hw);
1940
1941 out:
1942 return ret_val;
1943 }
1944
1945 /**
1946 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1947 * @hw: pointer to the HW structure
1948 *
1949 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1950 * the values found in the EEPROM. This addresses an issue in which these
1951 * bits are not restored from EEPROM after reset.
1952 **/
1953 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1954 {
1955 s32 ret_val = 0;
1956 u32 mdicnfg;
1957 u16 nvm_data = 0;
1958
1959 if (hw->mac.type != e1000_82580)
1960 goto out;
1961 if (!igb_sgmii_active_82575(hw))
1962 goto out;
1963
1964 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1965 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1966 &nvm_data);
1967 if (ret_val) {
1968 hw_dbg("NVM Read Error\n");
1969 goto out;
1970 }
1971
1972 mdicnfg = rd32(E1000_MDICNFG);
1973 if (nvm_data & NVM_WORD24_EXT_MDIO)
1974 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1975 if (nvm_data & NVM_WORD24_COM_MDIO)
1976 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1977 wr32(E1000_MDICNFG, mdicnfg);
1978 out:
1979 return ret_val;
1980 }
1981
1982 /**
1983 * igb_reset_hw_82580 - Reset hardware
1984 * @hw: pointer to the HW structure
1985 *
1986 * This resets function or entire device (all ports, etc.)
1987 * to a known state.
1988 **/
1989 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1990 {
1991 s32 ret_val = 0;
1992 /* BH SW mailbox bit in SW_FW_SYNC */
1993 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1994 u32 ctrl, icr;
1995 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1996
1997
1998 hw->dev_spec._82575.global_device_reset = false;
1999
2000 /* due to hw errata, global device reset doesn't always
2001 * work on 82580
2002 */
2003 if (hw->mac.type == e1000_82580)
2004 global_device_reset = false;
2005
2006 /* Get current control state. */
2007 ctrl = rd32(E1000_CTRL);
2008
2009 /*
2010 * Prevent the PCI-E bus from sticking if there is no TLP connection
2011 * on the last TLP read/write transaction when MAC is reset.
2012 */
2013 ret_val = igb_disable_pcie_master(hw);
2014 if (ret_val)
2015 hw_dbg("PCI-E Master disable polling has failed.\n");
2016
2017 hw_dbg("Masking off all interrupts\n");
2018 wr32(E1000_IMC, 0xffffffff);
2019 wr32(E1000_RCTL, 0);
2020 wr32(E1000_TCTL, E1000_TCTL_PSP);
2021 wrfl();
2022
2023 msleep(10);
2024
2025 /* Determine whether or not a global dev reset is requested */
2026 if (global_device_reset &&
2027 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2028 global_device_reset = false;
2029
2030 if (global_device_reset &&
2031 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2032 ctrl |= E1000_CTRL_DEV_RST;
2033 else
2034 ctrl |= E1000_CTRL_RST;
2035
2036 wr32(E1000_CTRL, ctrl);
2037 wrfl();
2038
2039 /* Add delay to insure DEV_RST has time to complete */
2040 if (global_device_reset)
2041 msleep(5);
2042
2043 ret_val = igb_get_auto_rd_done(hw);
2044 if (ret_val) {
2045 /*
2046 * When auto config read does not complete, do not
2047 * return with an error. This can happen in situations
2048 * where there is no eeprom and prevents getting link.
2049 */
2050 hw_dbg("Auto Read Done did not complete\n");
2051 }
2052
2053 /* If EEPROM is not present, run manual init scripts */
2054 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
2055 igb_reset_init_script_82575(hw);
2056
2057 /* clear global device reset status bit */
2058 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2059
2060 /* Clear any pending interrupt events. */
2061 wr32(E1000_IMC, 0xffffffff);
2062 icr = rd32(E1000_ICR);
2063
2064 ret_val = igb_reset_mdicnfg_82580(hw);
2065 if (ret_val)
2066 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2067
2068 /* Install any alternate MAC address into RAR0 */
2069 ret_val = igb_check_alt_mac_addr(hw);
2070
2071 /* Release semaphore */
2072 if (global_device_reset)
2073 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2074
2075 return ret_val;
2076 }
2077
2078 /**
2079 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2080 * @data: data received by reading RXPBS register
2081 *
2082 * The 82580 uses a table based approach for packet buffer allocation sizes.
2083 * This function converts the retrieved value into the correct table value
2084 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2085 * 0x0 36 72 144 1 2 4 8 16
2086 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2087 */
2088 u16 igb_rxpbs_adjust_82580(u32 data)
2089 {
2090 u16 ret_val = 0;
2091
2092 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2093 ret_val = e1000_82580_rxpbs_table[data];
2094
2095 return ret_val;
2096 }
2097
2098 /**
2099 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2100 * checksum
2101 * @hw: pointer to the HW structure
2102 * @offset: offset in words of the checksum protected region
2103 *
2104 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2105 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2106 **/
2107 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2108 u16 offset)
2109 {
2110 s32 ret_val = 0;
2111 u16 checksum = 0;
2112 u16 i, nvm_data;
2113
2114 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2115 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2116 if (ret_val) {
2117 hw_dbg("NVM Read Error\n");
2118 goto out;
2119 }
2120 checksum += nvm_data;
2121 }
2122
2123 if (checksum != (u16) NVM_SUM) {
2124 hw_dbg("NVM Checksum Invalid\n");
2125 ret_val = -E1000_ERR_NVM;
2126 goto out;
2127 }
2128
2129 out:
2130 return ret_val;
2131 }
2132
2133 /**
2134 * igb_update_nvm_checksum_with_offset - Update EEPROM
2135 * checksum
2136 * @hw: pointer to the HW structure
2137 * @offset: offset in words of the checksum protected region
2138 *
2139 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2140 * up to the checksum. Then calculates the EEPROM checksum and writes the
2141 * value to the EEPROM.
2142 **/
2143 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2144 {
2145 s32 ret_val;
2146 u16 checksum = 0;
2147 u16 i, nvm_data;
2148
2149 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2150 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2151 if (ret_val) {
2152 hw_dbg("NVM Read Error while updating checksum.\n");
2153 goto out;
2154 }
2155 checksum += nvm_data;
2156 }
2157 checksum = (u16) NVM_SUM - checksum;
2158 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2159 &checksum);
2160 if (ret_val)
2161 hw_dbg("NVM Write Error while updating checksum.\n");
2162
2163 out:
2164 return ret_val;
2165 }
2166
2167 /**
2168 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2169 * @hw: pointer to the HW structure
2170 *
2171 * Calculates the EEPROM section checksum by reading/adding each word of
2172 * the EEPROM and then verifies that the sum of the EEPROM is
2173 * equal to 0xBABA.
2174 **/
2175 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2176 {
2177 s32 ret_val = 0;
2178 u16 eeprom_regions_count = 1;
2179 u16 j, nvm_data;
2180 u16 nvm_offset;
2181
2182 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2183 if (ret_val) {
2184 hw_dbg("NVM Read Error\n");
2185 goto out;
2186 }
2187
2188 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2189 /* if checksums compatibility bit is set validate checksums
2190 * for all 4 ports. */
2191 eeprom_regions_count = 4;
2192 }
2193
2194 for (j = 0; j < eeprom_regions_count; j++) {
2195 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2196 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2197 nvm_offset);
2198 if (ret_val != 0)
2199 goto out;
2200 }
2201
2202 out:
2203 return ret_val;
2204 }
2205
2206 /**
2207 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2208 * @hw: pointer to the HW structure
2209 *
2210 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2211 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2212 * checksum and writes the value to the EEPROM.
2213 **/
2214 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2215 {
2216 s32 ret_val;
2217 u16 j, nvm_data;
2218 u16 nvm_offset;
2219
2220 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2221 if (ret_val) {
2222 hw_dbg("NVM Read Error while updating checksum"
2223 " compatibility bit.\n");
2224 goto out;
2225 }
2226
2227 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2228 /* set compatibility bit to validate checksums appropriately */
2229 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2230 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2231 &nvm_data);
2232 if (ret_val) {
2233 hw_dbg("NVM Write Error while updating checksum"
2234 " compatibility bit.\n");
2235 goto out;
2236 }
2237 }
2238
2239 for (j = 0; j < 4; j++) {
2240 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2241 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2242 if (ret_val)
2243 goto out;
2244 }
2245
2246 out:
2247 return ret_val;
2248 }
2249
2250 /**
2251 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2252 * @hw: pointer to the HW structure
2253 *
2254 * Calculates the EEPROM section checksum by reading/adding each word of
2255 * the EEPROM and then verifies that the sum of the EEPROM is
2256 * equal to 0xBABA.
2257 **/
2258 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2259 {
2260 s32 ret_val = 0;
2261 u16 j;
2262 u16 nvm_offset;
2263
2264 for (j = 0; j < 4; j++) {
2265 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2266 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2267 nvm_offset);
2268 if (ret_val != 0)
2269 goto out;
2270 }
2271
2272 out:
2273 return ret_val;
2274 }
2275
2276 /**
2277 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2278 * @hw: pointer to the HW structure
2279 *
2280 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2281 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2282 * checksum and writes the value to the EEPROM.
2283 **/
2284 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2285 {
2286 s32 ret_val = 0;
2287 u16 j;
2288 u16 nvm_offset;
2289
2290 for (j = 0; j < 4; j++) {
2291 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2292 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2293 if (ret_val != 0)
2294 goto out;
2295 }
2296
2297 out:
2298 return ret_val;
2299 }
2300
2301 /**
2302 * igb_set_eee_i350 - Enable/disable EEE support
2303 * @hw: pointer to the HW structure
2304 *
2305 * Enable/disable EEE based on setting in dev_spec structure.
2306 *
2307 **/
2308 s32 igb_set_eee_i350(struct e1000_hw *hw)
2309 {
2310 s32 ret_val = 0;
2311 u32 ipcnfg, eeer;
2312
2313 if ((hw->mac.type < e1000_i350) ||
2314 (hw->phy.media_type != e1000_media_type_copper))
2315 goto out;
2316 ipcnfg = rd32(E1000_IPCNFG);
2317 eeer = rd32(E1000_EEER);
2318
2319 /* enable or disable per user setting */
2320 if (!(hw->dev_spec._82575.eee_disable)) {
2321 u32 eee_su = rd32(E1000_EEE_SU);
2322
2323 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2324 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2325 E1000_EEER_LPI_FC);
2326
2327 /* This bit should not be set in normal operation. */
2328 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2329 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2330
2331
2332 } else {
2333 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2334 E1000_IPCNFG_EEE_100M_AN);
2335 eeer &= ~(E1000_EEER_TX_LPI_EN |
2336 E1000_EEER_RX_LPI_EN |
2337 E1000_EEER_LPI_FC);
2338 }
2339 wr32(E1000_IPCNFG, ipcnfg);
2340 wr32(E1000_EEER, eeer);
2341 rd32(E1000_IPCNFG);
2342 rd32(E1000_EEER);
2343 out:
2344
2345 return ret_val;
2346 }
2347
2348 static const u8 e1000_emc_temp_data[4] = {
2349 E1000_EMC_INTERNAL_DATA,
2350 E1000_EMC_DIODE1_DATA,
2351 E1000_EMC_DIODE2_DATA,
2352 E1000_EMC_DIODE3_DATA
2353 };
2354 static const u8 e1000_emc_therm_limit[4] = {
2355 E1000_EMC_INTERNAL_THERM_LIMIT,
2356 E1000_EMC_DIODE1_THERM_LIMIT,
2357 E1000_EMC_DIODE2_THERM_LIMIT,
2358 E1000_EMC_DIODE3_THERM_LIMIT
2359 };
2360
2361 /* igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2362 * @hw: pointer to hardware structure
2363 *
2364 * Updates the temperatures in mac.thermal_sensor_data
2365 */
2366 s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2367 {
2368 s32 status = E1000_SUCCESS;
2369 u16 ets_offset;
2370 u16 ets_cfg;
2371 u16 ets_sensor;
2372 u8 num_sensors;
2373 u8 sensor_index;
2374 u8 sensor_location;
2375 u8 i;
2376 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2377
2378 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2379 return E1000_NOT_IMPLEMENTED;
2380
2381 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2382
2383 /* Return the internal sensor only if ETS is unsupported */
2384 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2385 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2386 return status;
2387
2388 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2389 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2390 != NVM_ETS_TYPE_EMC)
2391 return E1000_NOT_IMPLEMENTED;
2392
2393 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2394 if (num_sensors > E1000_MAX_SENSORS)
2395 num_sensors = E1000_MAX_SENSORS;
2396
2397 for (i = 1; i < num_sensors; i++) {
2398 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2399 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2400 NVM_ETS_DATA_INDEX_SHIFT);
2401 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2402 NVM_ETS_DATA_LOC_SHIFT);
2403
2404 if (sensor_location != 0)
2405 hw->phy.ops.read_i2c_byte(hw,
2406 e1000_emc_temp_data[sensor_index],
2407 E1000_I2C_THERMAL_SENSOR_ADDR,
2408 &data->sensor[i].temp);
2409 }
2410 return status;
2411 }
2412
2413 /* igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2414 * @hw: pointer to hardware structure
2415 *
2416 * Sets the thermal sensor thresholds according to the NVM map
2417 * and save off the threshold and location values into mac.thermal_sensor_data
2418 */
2419 s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2420 {
2421 s32 status = E1000_SUCCESS;
2422 u16 ets_offset;
2423 u16 ets_cfg;
2424 u16 ets_sensor;
2425 u8 low_thresh_delta;
2426 u8 num_sensors;
2427 u8 sensor_index;
2428 u8 sensor_location;
2429 u8 therm_limit;
2430 u8 i;
2431 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2432
2433 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2434 return E1000_NOT_IMPLEMENTED;
2435
2436 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2437
2438 data->sensor[0].location = 0x1;
2439 data->sensor[0].caution_thresh =
2440 (rd32(E1000_THHIGHTC) & 0xFF);
2441 data->sensor[0].max_op_thresh =
2442 (rd32(E1000_THLOWTC) & 0xFF);
2443
2444 /* Return the internal sensor only if ETS is unsupported */
2445 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2446 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2447 return status;
2448
2449 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2450 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2451 != NVM_ETS_TYPE_EMC)
2452 return E1000_NOT_IMPLEMENTED;
2453
2454 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2455 NVM_ETS_LTHRES_DELTA_SHIFT);
2456 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2457
2458 for (i = 1; i <= num_sensors; i++) {
2459 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2460 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2461 NVM_ETS_DATA_INDEX_SHIFT);
2462 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2463 NVM_ETS_DATA_LOC_SHIFT);
2464 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2465
2466 hw->phy.ops.write_i2c_byte(hw,
2467 e1000_emc_therm_limit[sensor_index],
2468 E1000_I2C_THERMAL_SENSOR_ADDR,
2469 therm_limit);
2470
2471 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2472 data->sensor[i].location = sensor_location;
2473 data->sensor[i].caution_thresh = therm_limit;
2474 data->sensor[i].max_op_thresh = therm_limit -
2475 low_thresh_delta;
2476 }
2477 }
2478 return status;
2479 }
2480
2481 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2482 .init_hw = igb_init_hw_82575,
2483 .check_for_link = igb_check_for_link_82575,
2484 .rar_set = igb_rar_set,
2485 .read_mac_addr = igb_read_mac_addr_82575,
2486 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
2487 #ifdef CONFIG_IGB_HWMON
2488 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2489 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2490 #endif
2491 };
2492
2493 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2494 .acquire = igb_acquire_phy_82575,
2495 .get_cfg_done = igb_get_cfg_done_82575,
2496 .release = igb_release_phy_82575,
2497 .write_i2c_byte = igb_write_i2c_byte,
2498 .read_i2c_byte = igb_read_i2c_byte,
2499 };
2500
2501 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2502 .acquire = igb_acquire_nvm_82575,
2503 .read = igb_read_nvm_eerd,
2504 .release = igb_release_nvm_82575,
2505 .write = igb_write_nvm_spi,
2506 };
2507
2508 const struct e1000_info e1000_82575_info = {
2509 .get_invariants = igb_get_invariants_82575,
2510 .mac_ops = &e1000_mac_ops_82575,
2511 .phy_ops = &e1000_phy_ops_82575,
2512 .nvm_ops = &e1000_nvm_ops_82575,
2513 };
2514
Linux kernel - Deliverables
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