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[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
37
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
41
42 static s32 igb_get_invariants_82575(struct e1000_hw *);
43 static s32 igb_acquire_phy_82575(struct e1000_hw *);
44 static void igb_release_phy_82575(struct e1000_hw *);
45 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46 static void igb_release_nvm_82575(struct e1000_hw *);
47 static s32 igb_check_for_link_82575(struct e1000_hw *);
48 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49 static s32 igb_init_hw_82575(struct e1000_hw *);
50 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
52 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
54 static s32 igb_reset_hw_82575(struct e1000_hw *);
55 static s32 igb_reset_hw_82580(struct e1000_hw *);
56 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
57 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
59 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
60 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
61 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
64 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
65 u16 *);
66 static s32 igb_get_phy_id_82575(struct e1000_hw *);
67 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68 static bool igb_sgmii_active_82575(struct e1000_hw *);
69 static s32 igb_reset_init_script_82575(struct e1000_hw *);
70 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
71 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
72 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
73 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
75 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
77 static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
79 35, 70, 140 };
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
82
83 /**
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
86 *
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
89 **/
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
91 {
92 u32 reg = 0;
93 bool ext_mdio = false;
94
95 switch (hw->mac.type) {
96 case e1000_82575:
97 case e1000_82576:
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
100 break;
101 case e1000_82580:
102 case e1000_i350:
103 case e1000_i210:
104 case e1000_i211:
105 reg = rd32(E1000_MDICNFG);
106 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
107 break;
108 default:
109 break;
110 }
111 return ext_mdio;
112 }
113
114 /**
115 * igb_init_phy_params_82575 - Init PHY func ptrs.
116 * @hw: pointer to the HW structure
117 **/
118 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
119 {
120 struct e1000_phy_info *phy = &hw->phy;
121 s32 ret_val = 0;
122 u32 ctrl_ext;
123
124 if (hw->phy.media_type != e1000_media_type_copper) {
125 phy->type = e1000_phy_none;
126 goto out;
127 }
128
129 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
130 phy->reset_delay_us = 100;
131
132 ctrl_ext = rd32(E1000_CTRL_EXT);
133
134 if (igb_sgmii_active_82575(hw)) {
135 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
136 ctrl_ext |= E1000_CTRL_I2C_ENA;
137 } else {
138 phy->ops.reset = igb_phy_hw_reset;
139 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
140 }
141
142 wr32(E1000_CTRL_EXT, ctrl_ext);
143 igb_reset_mdicnfg_82580(hw);
144
145 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
146 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
147 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
148 } else {
149 switch (hw->mac.type) {
150 case e1000_82580:
151 case e1000_i350:
152 phy->ops.read_reg = igb_read_phy_reg_82580;
153 phy->ops.write_reg = igb_write_phy_reg_82580;
154 break;
155 case e1000_i210:
156 case e1000_i211:
157 phy->ops.read_reg = igb_read_phy_reg_gs40g;
158 phy->ops.write_reg = igb_write_phy_reg_gs40g;
159 break;
160 default:
161 phy->ops.read_reg = igb_read_phy_reg_igp;
162 phy->ops.write_reg = igb_write_phy_reg_igp;
163 }
164 }
165
166 /* set lan id */
167 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
168 E1000_STATUS_FUNC_SHIFT;
169
170 /* Set phy->phy_addr and phy->id. */
171 ret_val = igb_get_phy_id_82575(hw);
172 if (ret_val)
173 return ret_val;
174
175 /* Verify phy id and set remaining function pointers */
176 switch (phy->id) {
177 case I347AT4_E_PHY_ID:
178 case M88E1112_E_PHY_ID:
179 case M88E1111_I_PHY_ID:
180 phy->type = e1000_phy_m88;
181 phy->ops.get_phy_info = igb_get_phy_info_m88;
182 if (phy->id == I347AT4_E_PHY_ID ||
183 phy->id == M88E1112_E_PHY_ID)
184 phy->ops.get_cable_length =
185 igb_get_cable_length_m88_gen2;
186 else
187 phy->ops.get_cable_length = igb_get_cable_length_m88;
188 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
189 break;
190 case IGP03E1000_E_PHY_ID:
191 phy->type = e1000_phy_igp_3;
192 phy->ops.get_phy_info = igb_get_phy_info_igp;
193 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
194 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
195 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
196 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
197 break;
198 case I82580_I_PHY_ID:
199 case I350_I_PHY_ID:
200 phy->type = e1000_phy_82580;
201 phy->ops.force_speed_duplex =
202 igb_phy_force_speed_duplex_82580;
203 phy->ops.get_cable_length = igb_get_cable_length_82580;
204 phy->ops.get_phy_info = igb_get_phy_info_82580;
205 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
206 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
207 break;
208 case I210_I_PHY_ID:
209 phy->type = e1000_phy_i210;
210 phy->ops.check_polarity = igb_check_polarity_m88;
211 phy->ops.get_phy_info = igb_get_phy_info_m88;
212 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
213 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
214 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
215 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
216 break;
217 default:
218 ret_val = -E1000_ERR_PHY;
219 goto out;
220 }
221
222 out:
223 return ret_val;
224 }
225
226 /**
227 * igb_init_nvm_params_82575 - Init NVM func ptrs.
228 * @hw: pointer to the HW structure
229 **/
230 s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
231 {
232 struct e1000_nvm_info *nvm = &hw->nvm;
233 u32 eecd = rd32(E1000_EECD);
234 u16 size;
235
236 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
237 E1000_EECD_SIZE_EX_SHIFT);
238 /* Added to a constant, "size" becomes the left-shift value
239 * for setting word_size.
240 */
241 size += NVM_WORD_SIZE_BASE_SHIFT;
242
243 /* Just in case size is out of range, cap it to the largest
244 * EEPROM size supported
245 */
246 if (size > 15)
247 size = 15;
248
249 nvm->word_size = 1 << size;
250 if (hw->mac.type < e1000_i210) {
251 nvm->opcode_bits = 8;
252 nvm->delay_usec = 1;
253
254 switch (nvm->override) {
255 case e1000_nvm_override_spi_large:
256 nvm->page_size = 32;
257 nvm->address_bits = 16;
258 break;
259 case e1000_nvm_override_spi_small:
260 nvm->page_size = 8;
261 nvm->address_bits = 8;
262 break;
263 default:
264 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
265 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
266 16 : 8;
267 break;
268 }
269 if (nvm->word_size == (1 << 15))
270 nvm->page_size = 128;
271
272 nvm->type = e1000_nvm_eeprom_spi;
273 } else {
274 nvm->type = e1000_nvm_flash_hw;
275 }
276
277 /* NVM Function Pointers */
278 switch (hw->mac.type) {
279 case e1000_82580:
280 nvm->ops.validate = igb_validate_nvm_checksum_82580;
281 nvm->ops.update = igb_update_nvm_checksum_82580;
282 nvm->ops.acquire = igb_acquire_nvm_82575;
283 nvm->ops.release = igb_release_nvm_82575;
284 if (nvm->word_size < (1 << 15))
285 nvm->ops.read = igb_read_nvm_eerd;
286 else
287 nvm->ops.read = igb_read_nvm_spi;
288 nvm->ops.write = igb_write_nvm_spi;
289 break;
290 case e1000_i350:
291 nvm->ops.validate = igb_validate_nvm_checksum_i350;
292 nvm->ops.update = igb_update_nvm_checksum_i350;
293 nvm->ops.acquire = igb_acquire_nvm_82575;
294 nvm->ops.release = igb_release_nvm_82575;
295 if (nvm->word_size < (1 << 15))
296 nvm->ops.read = igb_read_nvm_eerd;
297 else
298 nvm->ops.read = igb_read_nvm_spi;
299 nvm->ops.write = igb_write_nvm_spi;
300 break;
301 case e1000_i210:
302 nvm->ops.validate = igb_validate_nvm_checksum_i210;
303 nvm->ops.update = igb_update_nvm_checksum_i210;
304 nvm->ops.acquire = igb_acquire_nvm_i210;
305 nvm->ops.release = igb_release_nvm_i210;
306 nvm->ops.read = igb_read_nvm_srrd_i210;
307 nvm->ops.write = igb_write_nvm_srwr_i210;
308 nvm->ops.valid_led_default = igb_valid_led_default_i210;
309 break;
310 case e1000_i211:
311 nvm->ops.acquire = igb_acquire_nvm_i210;
312 nvm->ops.release = igb_release_nvm_i210;
313 nvm->ops.read = igb_read_nvm_i211;
314 nvm->ops.valid_led_default = igb_valid_led_default_i210;
315 nvm->ops.validate = NULL;
316 nvm->ops.update = NULL;
317 nvm->ops.write = NULL;
318 break;
319 default:
320 nvm->ops.validate = igb_validate_nvm_checksum;
321 nvm->ops.update = igb_update_nvm_checksum;
322 nvm->ops.acquire = igb_acquire_nvm_82575;
323 nvm->ops.release = igb_release_nvm_82575;
324 if (nvm->word_size < (1 << 15))
325 nvm->ops.read = igb_read_nvm_eerd;
326 else
327 nvm->ops.read = igb_read_nvm_spi;
328 nvm->ops.write = igb_write_nvm_spi;
329 break;
330 }
331
332 return 0;
333 }
334
335 /**
336 * igb_init_mac_params_82575 - Init MAC func ptrs.
337 * @hw: pointer to the HW structure
338 **/
339 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
340 {
341 struct e1000_mac_info *mac = &hw->mac;
342 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
343
344 /* Set mta register count */
345 mac->mta_reg_count = 128;
346 /* Set rar entry count */
347 switch (mac->type) {
348 case e1000_82576:
349 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
350 break;
351 case e1000_82580:
352 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
353 break;
354 case e1000_i350:
355 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
356 break;
357 default:
358 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
359 break;
360 }
361 /* reset */
362 if (mac->type >= e1000_82580)
363 mac->ops.reset_hw = igb_reset_hw_82580;
364 else
365 mac->ops.reset_hw = igb_reset_hw_82575;
366
367 if (mac->type >= e1000_i210) {
368 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
369 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
370
371 } else {
372 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
373 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
374 }
375
376 /* Set if part includes ASF firmware */
377 mac->asf_firmware_present = true;
378 /* Set if manageability features are enabled. */
379 mac->arc_subsystem_valid =
380 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
381 ? true : false;
382 /* enable EEE on i350 parts and later parts */
383 if (mac->type >= e1000_i350)
384 dev_spec->eee_disable = false;
385 else
386 dev_spec->eee_disable = true;
387 /* physical interface link setup */
388 mac->ops.setup_physical_interface =
389 (hw->phy.media_type == e1000_media_type_copper)
390 ? igb_setup_copper_link_82575
391 : igb_setup_serdes_link_82575;
392
393 return 0;
394 }
395
396 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
397 {
398 struct e1000_phy_info *phy = &hw->phy;
399 struct e1000_nvm_info *nvm = &hw->nvm;
400 struct e1000_mac_info *mac = &hw->mac;
401 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
402 u32 eecd;
403 s32 ret_val;
404 u16 size;
405 u32 ctrl_ext = 0;
406
407 switch (hw->device_id) {
408 case E1000_DEV_ID_82575EB_COPPER:
409 case E1000_DEV_ID_82575EB_FIBER_SERDES:
410 case E1000_DEV_ID_82575GB_QUAD_COPPER:
411 mac->type = e1000_82575;
412 break;
413 case E1000_DEV_ID_82576:
414 case E1000_DEV_ID_82576_NS:
415 case E1000_DEV_ID_82576_NS_SERDES:
416 case E1000_DEV_ID_82576_FIBER:
417 case E1000_DEV_ID_82576_SERDES:
418 case E1000_DEV_ID_82576_QUAD_COPPER:
419 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
420 case E1000_DEV_ID_82576_SERDES_QUAD:
421 mac->type = e1000_82576;
422 break;
423 case E1000_DEV_ID_82580_COPPER:
424 case E1000_DEV_ID_82580_FIBER:
425 case E1000_DEV_ID_82580_QUAD_FIBER:
426 case E1000_DEV_ID_82580_SERDES:
427 case E1000_DEV_ID_82580_SGMII:
428 case E1000_DEV_ID_82580_COPPER_DUAL:
429 case E1000_DEV_ID_DH89XXCC_SGMII:
430 case E1000_DEV_ID_DH89XXCC_SERDES:
431 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
432 case E1000_DEV_ID_DH89XXCC_SFP:
433 mac->type = e1000_82580;
434 break;
435 case E1000_DEV_ID_I350_COPPER:
436 case E1000_DEV_ID_I350_FIBER:
437 case E1000_DEV_ID_I350_SERDES:
438 case E1000_DEV_ID_I350_SGMII:
439 mac->type = e1000_i350;
440 break;
441 case E1000_DEV_ID_I210_COPPER:
442 case E1000_DEV_ID_I210_COPPER_OEM1:
443 case E1000_DEV_ID_I210_COPPER_IT:
444 case E1000_DEV_ID_I210_FIBER:
445 case E1000_DEV_ID_I210_SERDES:
446 case E1000_DEV_ID_I210_SGMII:
447 mac->type = e1000_i210;
448 break;
449 case E1000_DEV_ID_I211_COPPER:
450 mac->type = e1000_i211;
451 break;
452 default:
453 return -E1000_ERR_MAC_INIT;
454 break;
455 }
456
457 /* Set media type */
458 /*
459 * The 82575 uses bits 22:23 for link mode. The mode can be changed
460 * based on the EEPROM. We cannot rely upon device ID. There
461 * is no distinguishable difference between fiber and internal
462 * SerDes mode on the 82575. There can be an external PHY attached
463 * on the SGMII interface. For this, we'll set sgmii_active to true.
464 */
465 phy->media_type = e1000_media_type_copper;
466 dev_spec->sgmii_active = false;
467
468 ctrl_ext = rd32(E1000_CTRL_EXT);
469 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
470 case E1000_CTRL_EXT_LINK_MODE_SGMII:
471 dev_spec->sgmii_active = true;
472 break;
473 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
474 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
475 hw->phy.media_type = e1000_media_type_internal_serdes;
476 break;
477 default:
478 break;
479 }
480
481 /* Set mta register count */
482 mac->mta_reg_count = 128;
483 /* Set rar entry count */
484 switch (mac->type) {
485 case e1000_82576:
486 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
487 break;
488 case e1000_82580:
489 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
490 break;
491 case e1000_i350:
492 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
493 break;
494 default:
495 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
496 break;
497 }
498 /* reset */
499 if (mac->type >= e1000_82580)
500 mac->ops.reset_hw = igb_reset_hw_82580;
501 else
502 mac->ops.reset_hw = igb_reset_hw_82575;
503
504 if (mac->type >= e1000_i210) {
505 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
506 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
507 } else {
508 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
509 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
510 }
511
512 /* Set if part includes ASF firmware */
513 mac->asf_firmware_present = true;
514 /* Set if manageability features are enabled. */
515 mac->arc_subsystem_valid =
516 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
517 ? true : false;
518 /* enable EEE on i350 parts and later parts */
519 if (mac->type >= e1000_i350)
520 dev_spec->eee_disable = false;
521 else
522 dev_spec->eee_disable = true;
523 /* physical interface link setup */
524 mac->ops.setup_physical_interface =
525 (hw->phy.media_type == e1000_media_type_copper)
526 ? igb_setup_copper_link_82575
527 : igb_setup_serdes_link_82575;
528
529 /* NVM initialization */
530 eecd = rd32(E1000_EECD);
531 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
532 E1000_EECD_SIZE_EX_SHIFT);
533
534 /*
535 * Added to a constant, "size" becomes the left-shift value
536 * for setting word_size.
537 */
538 size += NVM_WORD_SIZE_BASE_SHIFT;
539
540 /*
541 * Check for invalid size
542 */
543 if ((hw->mac.type == e1000_82576) && (size > 15)) {
544 pr_notice("The NVM size is not valid, defaulting to 32K\n");
545 size = 15;
546 }
547
548 nvm->word_size = 1 << size;
549 if (hw->mac.type < e1000_i210) {
550 nvm->opcode_bits = 8;
551 nvm->delay_usec = 1;
552 switch (nvm->override) {
553 case e1000_nvm_override_spi_large:
554 nvm->page_size = 32;
555 nvm->address_bits = 16;
556 break;
557 case e1000_nvm_override_spi_small:
558 nvm->page_size = 8;
559 nvm->address_bits = 8;
560 break;
561 default:
562 nvm->page_size = eecd
563 & E1000_EECD_ADDR_BITS ? 32 : 8;
564 nvm->address_bits = eecd
565 & E1000_EECD_ADDR_BITS ? 16 : 8;
566 break;
567 }
568 if (nvm->word_size == (1 << 15))
569 nvm->page_size = 128;
570
571 nvm->type = e1000_nvm_eeprom_spi;
572 } else
573 nvm->type = e1000_nvm_flash_hw;
574
575 /* NVM Function Pointers */
576 switch (hw->mac.type) {
577 case e1000_82580:
578 nvm->ops.validate = igb_validate_nvm_checksum_82580;
579 nvm->ops.update = igb_update_nvm_checksum_82580;
580 nvm->ops.acquire = igb_acquire_nvm_82575;
581 nvm->ops.release = igb_release_nvm_82575;
582 if (nvm->word_size < (1 << 15))
583 nvm->ops.read = igb_read_nvm_eerd;
584 else
585 nvm->ops.read = igb_read_nvm_spi;
586 nvm->ops.write = igb_write_nvm_spi;
587 break;
588 case e1000_i350:
589 nvm->ops.validate = igb_validate_nvm_checksum_i350;
590 nvm->ops.update = igb_update_nvm_checksum_i350;
591 nvm->ops.acquire = igb_acquire_nvm_82575;
592 nvm->ops.release = igb_release_nvm_82575;
593 if (nvm->word_size < (1 << 15))
594 nvm->ops.read = igb_read_nvm_eerd;
595 else
596 nvm->ops.read = igb_read_nvm_spi;
597 nvm->ops.write = igb_write_nvm_spi;
598 break;
599 case e1000_i210:
600 nvm->ops.validate = igb_validate_nvm_checksum_i210;
601 nvm->ops.update = igb_update_nvm_checksum_i210;
602 nvm->ops.acquire = igb_acquire_nvm_i210;
603 nvm->ops.release = igb_release_nvm_i210;
604 nvm->ops.read = igb_read_nvm_srrd_i210;
605 nvm->ops.write = igb_write_nvm_srwr_i210;
606 nvm->ops.valid_led_default = igb_valid_led_default_i210;
607 break;
608 case e1000_i211:
609 nvm->ops.acquire = igb_acquire_nvm_i210;
610 nvm->ops.release = igb_release_nvm_i210;
611 nvm->ops.read = igb_read_nvm_i211;
612 nvm->ops.valid_led_default = igb_valid_led_default_i210;
613 nvm->ops.validate = NULL;
614 nvm->ops.update = NULL;
615 nvm->ops.write = NULL;
616 break;
617 default:
618 nvm->ops.validate = igb_validate_nvm_checksum;
619 nvm->ops.update = igb_update_nvm_checksum;
620 nvm->ops.acquire = igb_acquire_nvm_82575;
621 nvm->ops.release = igb_release_nvm_82575;
622 if (nvm->word_size < (1 << 15))
623 nvm->ops.read = igb_read_nvm_eerd;
624 else
625 nvm->ops.read = igb_read_nvm_spi;
626 nvm->ops.write = igb_write_nvm_spi;
627 break;
628 }
629
630 /* if part supports SR-IOV then initialize mailbox parameters */
631 switch (mac->type) {
632 case e1000_82576:
633 case e1000_i350:
634 igb_init_mbx_params_pf(hw);
635 break;
636 default:
637 break;
638 }
639
640 /* setup PHY parameters */
641 if (phy->media_type != e1000_media_type_copper) {
642 phy->type = e1000_phy_none;
643 return 0;
644 }
645
646 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
647 phy->reset_delay_us = 100;
648
649 ctrl_ext = rd32(E1000_CTRL_EXT);
650
651 /* PHY function pointers */
652 if (igb_sgmii_active_82575(hw)) {
653 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
654 ctrl_ext |= E1000_CTRL_I2C_ENA;
655 } else {
656 phy->ops.reset = igb_phy_hw_reset;
657 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
658 }
659
660 wr32(E1000_CTRL_EXT, ctrl_ext);
661 igb_reset_mdicnfg_82580(hw);
662
663 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
664 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
665 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
666 } else if ((hw->mac.type == e1000_82580)
667 || (hw->mac.type == e1000_i350)) {
668 phy->ops.read_reg = igb_read_phy_reg_82580;
669 phy->ops.write_reg = igb_write_phy_reg_82580;
670 } else if (hw->phy.type >= e1000_phy_i210) {
671 phy->ops.read_reg = igb_read_phy_reg_gs40g;
672 phy->ops.write_reg = igb_write_phy_reg_gs40g;
673 } else {
674 phy->ops.read_reg = igb_read_phy_reg_igp;
675 phy->ops.write_reg = igb_write_phy_reg_igp;
676 }
677
678 /* set lan id */
679 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
680 E1000_STATUS_FUNC_SHIFT;
681
682 /* Set phy->phy_addr and phy->id. */
683 ret_val = igb_get_phy_id_82575(hw);
684 if (ret_val)
685 return ret_val;
686
687 /* Verify phy id and set remaining function pointers */
688 switch (phy->id) {
689 case I347AT4_E_PHY_ID:
690 case M88E1112_E_PHY_ID:
691 case M88E1111_I_PHY_ID:
692 phy->type = e1000_phy_m88;
693 phy->ops.get_phy_info = igb_get_phy_info_m88;
694
695 if (phy->id == I347AT4_E_PHY_ID ||
696 phy->id == M88E1112_E_PHY_ID)
697 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
698 else
699 phy->ops.get_cable_length = igb_get_cable_length_m88;
700
701 if (phy->id == I210_I_PHY_ID) {
702 phy->ops.get_cable_length =
703 igb_get_cable_length_m88_gen2;
704 phy->ops.set_d0_lplu_state =
705 igb_set_d0_lplu_state_82580;
706 phy->ops.set_d3_lplu_state =
707 igb_set_d3_lplu_state_82580;
708 }
709 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
710 break;
711 case IGP03E1000_E_PHY_ID:
712 phy->type = e1000_phy_igp_3;
713 phy->ops.get_phy_info = igb_get_phy_info_igp;
714 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
715 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
716 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
717 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
718 break;
719 case I82580_I_PHY_ID:
720 case I350_I_PHY_ID:
721 phy->type = e1000_phy_82580;
722 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
723 phy->ops.get_cable_length = igb_get_cable_length_82580;
724 phy->ops.get_phy_info = igb_get_phy_info_82580;
725 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
726 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
727 break;
728 case I210_I_PHY_ID:
729 phy->type = e1000_phy_i210;
730 phy->ops.get_phy_info = igb_get_phy_info_m88;
731 phy->ops.check_polarity = igb_check_polarity_m88;
732 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
733 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
734 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
735 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
736 break;
737 default:
738 return -E1000_ERR_PHY;
739 }
740
741 return 0;
742 }
743
744 /**
745 * igb_acquire_phy_82575 - Acquire rights to access PHY
746 * @hw: pointer to the HW structure
747 *
748 * Acquire access rights to the correct PHY. This is a
749 * function pointer entry point called by the api module.
750 **/
751 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
752 {
753 u16 mask = E1000_SWFW_PHY0_SM;
754
755 if (hw->bus.func == E1000_FUNC_1)
756 mask = E1000_SWFW_PHY1_SM;
757 else if (hw->bus.func == E1000_FUNC_2)
758 mask = E1000_SWFW_PHY2_SM;
759 else if (hw->bus.func == E1000_FUNC_3)
760 mask = E1000_SWFW_PHY3_SM;
761
762 return hw->mac.ops.acquire_swfw_sync(hw, mask);
763 }
764
765 /**
766 * igb_release_phy_82575 - Release rights to access PHY
767 * @hw: pointer to the HW structure
768 *
769 * A wrapper to release access rights to the correct PHY. This is a
770 * function pointer entry point called by the api module.
771 **/
772 static void igb_release_phy_82575(struct e1000_hw *hw)
773 {
774 u16 mask = E1000_SWFW_PHY0_SM;
775
776 if (hw->bus.func == E1000_FUNC_1)
777 mask = E1000_SWFW_PHY1_SM;
778 else if (hw->bus.func == E1000_FUNC_2)
779 mask = E1000_SWFW_PHY2_SM;
780 else if (hw->bus.func == E1000_FUNC_3)
781 mask = E1000_SWFW_PHY3_SM;
782
783 hw->mac.ops.release_swfw_sync(hw, mask);
784 }
785
786 /**
787 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
788 * @hw: pointer to the HW structure
789 * @offset: register offset to be read
790 * @data: pointer to the read data
791 *
792 * Reads the PHY register at offset using the serial gigabit media independent
793 * interface and stores the retrieved information in data.
794 **/
795 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
796 u16 *data)
797 {
798 s32 ret_val = -E1000_ERR_PARAM;
799
800 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
801 hw_dbg("PHY Address %u is out of range\n", offset);
802 goto out;
803 }
804
805 ret_val = hw->phy.ops.acquire(hw);
806 if (ret_val)
807 goto out;
808
809 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
810
811 hw->phy.ops.release(hw);
812
813 out:
814 return ret_val;
815 }
816
817 /**
818 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
819 * @hw: pointer to the HW structure
820 * @offset: register offset to write to
821 * @data: data to write at register offset
822 *
823 * Writes the data to PHY register at the offset using the serial gigabit
824 * media independent interface.
825 **/
826 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
827 u16 data)
828 {
829 s32 ret_val = -E1000_ERR_PARAM;
830
831
832 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
833 hw_dbg("PHY Address %d is out of range\n", offset);
834 goto out;
835 }
836
837 ret_val = hw->phy.ops.acquire(hw);
838 if (ret_val)
839 goto out;
840
841 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
842
843 hw->phy.ops.release(hw);
844
845 out:
846 return ret_val;
847 }
848
849 /**
850 * igb_get_phy_id_82575 - Retrieve PHY addr and id
851 * @hw: pointer to the HW structure
852 *
853 * Retrieves the PHY address and ID for both PHY's which do and do not use
854 * sgmi interface.
855 **/
856 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
857 {
858 struct e1000_phy_info *phy = &hw->phy;
859 s32 ret_val = 0;
860 u16 phy_id;
861 u32 ctrl_ext;
862 u32 mdic;
863
864 /*
865 * For SGMII PHYs, we try the list of possible addresses until
866 * we find one that works. For non-SGMII PHYs
867 * (e.g. integrated copper PHYs), an address of 1 should
868 * work. The result of this function should mean phy->phy_addr
869 * and phy->id are set correctly.
870 */
871 if (!(igb_sgmii_active_82575(hw))) {
872 phy->addr = 1;
873 ret_val = igb_get_phy_id(hw);
874 goto out;
875 }
876
877 if (igb_sgmii_uses_mdio_82575(hw)) {
878 switch (hw->mac.type) {
879 case e1000_82575:
880 case e1000_82576:
881 mdic = rd32(E1000_MDIC);
882 mdic &= E1000_MDIC_PHY_MASK;
883 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
884 break;
885 case e1000_82580:
886 case e1000_i350:
887 case e1000_i210:
888 case e1000_i211:
889 mdic = rd32(E1000_MDICNFG);
890 mdic &= E1000_MDICNFG_PHY_MASK;
891 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
892 break;
893 default:
894 ret_val = -E1000_ERR_PHY;
895 goto out;
896 break;
897 }
898 ret_val = igb_get_phy_id(hw);
899 goto out;
900 }
901
902 /* Power on sgmii phy if it is disabled */
903 ctrl_ext = rd32(E1000_CTRL_EXT);
904 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
905 wrfl();
906 msleep(300);
907
908 /*
909 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
910 * Therefore, we need to test 1-7
911 */
912 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
913 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
914 if (ret_val == 0) {
915 hw_dbg("Vendor ID 0x%08X read at address %u\n",
916 phy_id, phy->addr);
917 /*
918 * At the time of this writing, The M88 part is
919 * the only supported SGMII PHY product.
920 */
921 if (phy_id == M88_VENDOR)
922 break;
923 } else {
924 hw_dbg("PHY address %u was unreadable\n", phy->addr);
925 }
926 }
927
928 /* A valid PHY type couldn't be found. */
929 if (phy->addr == 8) {
930 phy->addr = 0;
931 ret_val = -E1000_ERR_PHY;
932 goto out;
933 } else {
934 ret_val = igb_get_phy_id(hw);
935 }
936
937 /* restore previous sfp cage power state */
938 wr32(E1000_CTRL_EXT, ctrl_ext);
939
940 out:
941 return ret_val;
942 }
943
944 /**
945 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
946 * @hw: pointer to the HW structure
947 *
948 * Resets the PHY using the serial gigabit media independent interface.
949 **/
950 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
951 {
952 s32 ret_val;
953
954 /*
955 * This isn't a true "hard" reset, but is the only reset
956 * available to us at this time.
957 */
958
959 hw_dbg("Soft resetting SGMII attached PHY...\n");
960
961 /*
962 * SFP documentation requires the following to configure the SPF module
963 * to work on SGMII. No further documentation is given.
964 */
965 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
966 if (ret_val)
967 goto out;
968
969 ret_val = igb_phy_sw_reset(hw);
970
971 out:
972 return ret_val;
973 }
974
975 /**
976 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
977 * @hw: pointer to the HW structure
978 * @active: true to enable LPLU, false to disable
979 *
980 * Sets the LPLU D0 state according to the active flag. When
981 * activating LPLU this function also disables smart speed
982 * and vice versa. LPLU will not be activated unless the
983 * device autonegotiation advertisement meets standards of
984 * either 10 or 10/100 or 10/100/1000 at all duplexes.
985 * This is a function pointer entry point only called by
986 * PHY setup routines.
987 **/
988 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
989 {
990 struct e1000_phy_info *phy = &hw->phy;
991 s32 ret_val;
992 u16 data;
993
994 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
995 if (ret_val)
996 goto out;
997
998 if (active) {
999 data |= IGP02E1000_PM_D0_LPLU;
1000 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1001 data);
1002 if (ret_val)
1003 goto out;
1004
1005 /* When LPLU is enabled, we should disable SmartSpeed */
1006 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1007 &data);
1008 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1009 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1010 data);
1011 if (ret_val)
1012 goto out;
1013 } else {
1014 data &= ~IGP02E1000_PM_D0_LPLU;
1015 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1016 data);
1017 /*
1018 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1019 * during Dx states where the power conservation is most
1020 * important. During driver activity we should enable
1021 * SmartSpeed, so performance is maintained.
1022 */
1023 if (phy->smart_speed == e1000_smart_speed_on) {
1024 ret_val = phy->ops.read_reg(hw,
1025 IGP01E1000_PHY_PORT_CONFIG, &data);
1026 if (ret_val)
1027 goto out;
1028
1029 data |= IGP01E1000_PSCFR_SMART_SPEED;
1030 ret_val = phy->ops.write_reg(hw,
1031 IGP01E1000_PHY_PORT_CONFIG, data);
1032 if (ret_val)
1033 goto out;
1034 } else if (phy->smart_speed == e1000_smart_speed_off) {
1035 ret_val = phy->ops.read_reg(hw,
1036 IGP01E1000_PHY_PORT_CONFIG, &data);
1037 if (ret_val)
1038 goto out;
1039
1040 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1041 ret_val = phy->ops.write_reg(hw,
1042 IGP01E1000_PHY_PORT_CONFIG, data);
1043 if (ret_val)
1044 goto out;
1045 }
1046 }
1047
1048 out:
1049 return ret_val;
1050 }
1051
1052 /**
1053 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1054 * @hw: pointer to the HW structure
1055 * @active: true to enable LPLU, false to disable
1056 *
1057 * Sets the LPLU D0 state according to the active flag. When
1058 * activating LPLU this function also disables smart speed
1059 * and vice versa. LPLU will not be activated unless the
1060 * device autonegotiation advertisement meets standards of
1061 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1062 * This is a function pointer entry point only called by
1063 * PHY setup routines.
1064 **/
1065 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1066 {
1067 struct e1000_phy_info *phy = &hw->phy;
1068 s32 ret_val = 0;
1069 u16 data;
1070
1071 data = rd32(E1000_82580_PHY_POWER_MGMT);
1072
1073 if (active) {
1074 data |= E1000_82580_PM_D0_LPLU;
1075
1076 /* When LPLU is enabled, we should disable SmartSpeed */
1077 data &= ~E1000_82580_PM_SPD;
1078 } else {
1079 data &= ~E1000_82580_PM_D0_LPLU;
1080
1081 /*
1082 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1083 * during Dx states where the power conservation is most
1084 * important. During driver activity we should enable
1085 * SmartSpeed, so performance is maintained.
1086 */
1087 if (phy->smart_speed == e1000_smart_speed_on)
1088 data |= E1000_82580_PM_SPD;
1089 else if (phy->smart_speed == e1000_smart_speed_off)
1090 data &= ~E1000_82580_PM_SPD; }
1091
1092 wr32(E1000_82580_PHY_POWER_MGMT, data);
1093 return ret_val;
1094 }
1095
1096 /**
1097 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1098 * @hw: pointer to the HW structure
1099 * @active: boolean used to enable/disable lplu
1100 *
1101 * Success returns 0, Failure returns 1
1102 *
1103 * The low power link up (lplu) state is set to the power management level D3
1104 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1105 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1106 * is used during Dx states where the power conservation is most important.
1107 * During driver activity, SmartSpeed should be enabled so performance is
1108 * maintained.
1109 **/
1110 s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1111 {
1112 struct e1000_phy_info *phy = &hw->phy;
1113 s32 ret_val = 0;
1114 u16 data;
1115
1116 data = rd32(E1000_82580_PHY_POWER_MGMT);
1117
1118 if (!active) {
1119 data &= ~E1000_82580_PM_D3_LPLU;
1120 /*
1121 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1122 * during Dx states where the power conservation is most
1123 * important. During driver activity we should enable
1124 * SmartSpeed, so performance is maintained.
1125 */
1126 if (phy->smart_speed == e1000_smart_speed_on)
1127 data |= E1000_82580_PM_SPD;
1128 else if (phy->smart_speed == e1000_smart_speed_off)
1129 data &= ~E1000_82580_PM_SPD;
1130 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1131 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1132 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1133 data |= E1000_82580_PM_D3_LPLU;
1134 /* When LPLU is enabled, we should disable SmartSpeed */
1135 data &= ~E1000_82580_PM_SPD;
1136 }
1137
1138 wr32(E1000_82580_PHY_POWER_MGMT, data);
1139 return ret_val;
1140 }
1141
1142 /**
1143 * igb_acquire_nvm_82575 - Request for access to EEPROM
1144 * @hw: pointer to the HW structure
1145 *
1146 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1147 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1148 * Return successful if access grant bit set, else clear the request for
1149 * EEPROM access and return -E1000_ERR_NVM (-1).
1150 **/
1151 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1152 {
1153 s32 ret_val;
1154
1155 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1156 if (ret_val)
1157 goto out;
1158
1159 ret_val = igb_acquire_nvm(hw);
1160
1161 if (ret_val)
1162 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1163
1164 out:
1165 return ret_val;
1166 }
1167
1168 /**
1169 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1170 * @hw: pointer to the HW structure
1171 *
1172 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1173 * then release the semaphores acquired.
1174 **/
1175 static void igb_release_nvm_82575(struct e1000_hw *hw)
1176 {
1177 igb_release_nvm(hw);
1178 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1179 }
1180
1181 /**
1182 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1183 * @hw: pointer to the HW structure
1184 * @mask: specifies which semaphore to acquire
1185 *
1186 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1187 * will also specify which port we're acquiring the lock for.
1188 **/
1189 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1190 {
1191 u32 swfw_sync;
1192 u32 swmask = mask;
1193 u32 fwmask = mask << 16;
1194 s32 ret_val = 0;
1195 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1196
1197 while (i < timeout) {
1198 if (igb_get_hw_semaphore(hw)) {
1199 ret_val = -E1000_ERR_SWFW_SYNC;
1200 goto out;
1201 }
1202
1203 swfw_sync = rd32(E1000_SW_FW_SYNC);
1204 if (!(swfw_sync & (fwmask | swmask)))
1205 break;
1206
1207 /*
1208 * Firmware currently using resource (fwmask)
1209 * or other software thread using resource (swmask)
1210 */
1211 igb_put_hw_semaphore(hw);
1212 mdelay(5);
1213 i++;
1214 }
1215
1216 if (i == timeout) {
1217 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1218 ret_val = -E1000_ERR_SWFW_SYNC;
1219 goto out;
1220 }
1221
1222 swfw_sync |= swmask;
1223 wr32(E1000_SW_FW_SYNC, swfw_sync);
1224
1225 igb_put_hw_semaphore(hw);
1226
1227 out:
1228 return ret_val;
1229 }
1230
1231 /**
1232 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1233 * @hw: pointer to the HW structure
1234 * @mask: specifies which semaphore to acquire
1235 *
1236 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1237 * will also specify which port we're releasing the lock for.
1238 **/
1239 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1240 {
1241 u32 swfw_sync;
1242
1243 while (igb_get_hw_semaphore(hw) != 0);
1244 /* Empty */
1245
1246 swfw_sync = rd32(E1000_SW_FW_SYNC);
1247 swfw_sync &= ~mask;
1248 wr32(E1000_SW_FW_SYNC, swfw_sync);
1249
1250 igb_put_hw_semaphore(hw);
1251 }
1252
1253 /**
1254 * igb_get_cfg_done_82575 - Read config done bit
1255 * @hw: pointer to the HW structure
1256 *
1257 * Read the management control register for the config done bit for
1258 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1259 * to read the config done bit, so an error is *ONLY* logged and returns
1260 * 0. If we were to return with error, EEPROM-less silicon
1261 * would not be able to be reset or change link.
1262 **/
1263 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1264 {
1265 s32 timeout = PHY_CFG_TIMEOUT;
1266 s32 ret_val = 0;
1267 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1268
1269 if (hw->bus.func == 1)
1270 mask = E1000_NVM_CFG_DONE_PORT_1;
1271 else if (hw->bus.func == E1000_FUNC_2)
1272 mask = E1000_NVM_CFG_DONE_PORT_2;
1273 else if (hw->bus.func == E1000_FUNC_3)
1274 mask = E1000_NVM_CFG_DONE_PORT_3;
1275
1276 while (timeout) {
1277 if (rd32(E1000_EEMNGCTL) & mask)
1278 break;
1279 msleep(1);
1280 timeout--;
1281 }
1282 if (!timeout)
1283 hw_dbg("MNG configuration cycle has not completed.\n");
1284
1285 /* If EEPROM is not marked present, init the PHY manually */
1286 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1287 (hw->phy.type == e1000_phy_igp_3))
1288 igb_phy_init_script_igp3(hw);
1289
1290 return ret_val;
1291 }
1292
1293 /**
1294 * igb_check_for_link_82575 - Check for link
1295 * @hw: pointer to the HW structure
1296 *
1297 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1298 * use the generic interface for determining link.
1299 **/
1300 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1301 {
1302 s32 ret_val;
1303 u16 speed, duplex;
1304
1305 if (hw->phy.media_type != e1000_media_type_copper) {
1306 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1307 &duplex);
1308 /*
1309 * Use this flag to determine if link needs to be checked or
1310 * not. If we have link clear the flag so that we do not
1311 * continue to check for link.
1312 */
1313 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1314
1315 /* Configure Flow Control now that Auto-Neg has completed.
1316 * First, we need to restore the desired flow control
1317 * settings because we may have had to re-autoneg with a
1318 * different link partner.
1319 */
1320 ret_val = igb_config_fc_after_link_up(hw);
1321 if (ret_val)
1322 hw_dbg("Error configuring flow control\n");
1323 } else {
1324 ret_val = igb_check_for_copper_link(hw);
1325 }
1326
1327 return ret_val;
1328 }
1329
1330 /**
1331 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1332 * @hw: pointer to the HW structure
1333 **/
1334 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1335 {
1336 u32 reg;
1337
1338
1339 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1340 !igb_sgmii_active_82575(hw))
1341 return;
1342
1343 /* Enable PCS to turn on link */
1344 reg = rd32(E1000_PCS_CFG0);
1345 reg |= E1000_PCS_CFG_PCS_EN;
1346 wr32(E1000_PCS_CFG0, reg);
1347
1348 /* Power up the laser */
1349 reg = rd32(E1000_CTRL_EXT);
1350 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1351 wr32(E1000_CTRL_EXT, reg);
1352
1353 /* flush the write to verify completion */
1354 wrfl();
1355 msleep(1);
1356 }
1357
1358 /**
1359 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1360 * @hw: pointer to the HW structure
1361 * @speed: stores the current speed
1362 * @duplex: stores the current duplex
1363 *
1364 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1365 * duplex, then store the values in the pointers provided.
1366 **/
1367 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1368 u16 *duplex)
1369 {
1370 struct e1000_mac_info *mac = &hw->mac;
1371 u32 pcs;
1372
1373 /* Set up defaults for the return values of this function */
1374 mac->serdes_has_link = false;
1375 *speed = 0;
1376 *duplex = 0;
1377
1378 /*
1379 * Read the PCS Status register for link state. For non-copper mode,
1380 * the status register is not accurate. The PCS status register is
1381 * used instead.
1382 */
1383 pcs = rd32(E1000_PCS_LSTAT);
1384
1385 /*
1386 * The link up bit determines when link is up on autoneg. The sync ok
1387 * gets set once both sides sync up and agree upon link. Stable link
1388 * can be determined by checking for both link up and link sync ok
1389 */
1390 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1391 mac->serdes_has_link = true;
1392
1393 /* Detect and store PCS speed */
1394 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1395 *speed = SPEED_1000;
1396 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1397 *speed = SPEED_100;
1398 } else {
1399 *speed = SPEED_10;
1400 }
1401
1402 /* Detect and store PCS duplex */
1403 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1404 *duplex = FULL_DUPLEX;
1405 } else {
1406 *duplex = HALF_DUPLEX;
1407 }
1408 }
1409
1410 return 0;
1411 }
1412
1413 /**
1414 * igb_shutdown_serdes_link_82575 - Remove link during power down
1415 * @hw: pointer to the HW structure
1416 *
1417 * In the case of fiber serdes, shut down optics and PCS on driver unload
1418 * when management pass thru is not enabled.
1419 **/
1420 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1421 {
1422 u32 reg;
1423
1424 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1425 igb_sgmii_active_82575(hw))
1426 return;
1427
1428 if (!igb_enable_mng_pass_thru(hw)) {
1429 /* Disable PCS to turn off link */
1430 reg = rd32(E1000_PCS_CFG0);
1431 reg &= ~E1000_PCS_CFG_PCS_EN;
1432 wr32(E1000_PCS_CFG0, reg);
1433
1434 /* shutdown the laser */
1435 reg = rd32(E1000_CTRL_EXT);
1436 reg |= E1000_CTRL_EXT_SDP3_DATA;
1437 wr32(E1000_CTRL_EXT, reg);
1438
1439 /* flush the write to verify completion */
1440 wrfl();
1441 msleep(1);
1442 }
1443 }
1444
1445 /**
1446 * igb_reset_hw_82575 - Reset hardware
1447 * @hw: pointer to the HW structure
1448 *
1449 * This resets the hardware into a known state. This is a
1450 * function pointer entry point called by the api module.
1451 **/
1452 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1453 {
1454 u32 ctrl, icr;
1455 s32 ret_val;
1456
1457 /*
1458 * Prevent the PCI-E bus from sticking if there is no TLP connection
1459 * on the last TLP read/write transaction when MAC is reset.
1460 */
1461 ret_val = igb_disable_pcie_master(hw);
1462 if (ret_val)
1463 hw_dbg("PCI-E Master disable polling has failed.\n");
1464
1465 /* set the completion timeout for interface */
1466 ret_val = igb_set_pcie_completion_timeout(hw);
1467 if (ret_val) {
1468 hw_dbg("PCI-E Set completion timeout has failed.\n");
1469 }
1470
1471 hw_dbg("Masking off all interrupts\n");
1472 wr32(E1000_IMC, 0xffffffff);
1473
1474 wr32(E1000_RCTL, 0);
1475 wr32(E1000_TCTL, E1000_TCTL_PSP);
1476 wrfl();
1477
1478 msleep(10);
1479
1480 ctrl = rd32(E1000_CTRL);
1481
1482 hw_dbg("Issuing a global reset to MAC\n");
1483 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1484
1485 ret_val = igb_get_auto_rd_done(hw);
1486 if (ret_val) {
1487 /*
1488 * When auto config read does not complete, do not
1489 * return with an error. This can happen in situations
1490 * where there is no eeprom and prevents getting link.
1491 */
1492 hw_dbg("Auto Read Done did not complete\n");
1493 }
1494
1495 /* If EEPROM is not present, run manual init scripts */
1496 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1497 igb_reset_init_script_82575(hw);
1498
1499 /* Clear any pending interrupt events. */
1500 wr32(E1000_IMC, 0xffffffff);
1501 icr = rd32(E1000_ICR);
1502
1503 /* Install any alternate MAC address into RAR0 */
1504 ret_val = igb_check_alt_mac_addr(hw);
1505
1506 return ret_val;
1507 }
1508
1509 /**
1510 * igb_init_hw_82575 - Initialize hardware
1511 * @hw: pointer to the HW structure
1512 *
1513 * This inits the hardware readying it for operation.
1514 **/
1515 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1516 {
1517 struct e1000_mac_info *mac = &hw->mac;
1518 s32 ret_val;
1519 u16 i, rar_count = mac->rar_entry_count;
1520
1521 /* Initialize identification LED */
1522 ret_val = igb_id_led_init(hw);
1523 if (ret_val) {
1524 hw_dbg("Error initializing identification LED\n");
1525 /* This is not fatal and we should not stop init due to this */
1526 }
1527
1528 /* Disabling VLAN filtering */
1529 hw_dbg("Initializing the IEEE VLAN\n");
1530 if (hw->mac.type == e1000_i350)
1531 igb_clear_vfta_i350(hw);
1532 else
1533 igb_clear_vfta(hw);
1534
1535 /* Setup the receive address */
1536 igb_init_rx_addrs(hw, rar_count);
1537
1538 /* Zero out the Multicast HASH table */
1539 hw_dbg("Zeroing the MTA\n");
1540 for (i = 0; i < mac->mta_reg_count; i++)
1541 array_wr32(E1000_MTA, i, 0);
1542
1543 /* Zero out the Unicast HASH table */
1544 hw_dbg("Zeroing the UTA\n");
1545 for (i = 0; i < mac->uta_reg_count; i++)
1546 array_wr32(E1000_UTA, i, 0);
1547
1548 /* Setup link and flow control */
1549 ret_val = igb_setup_link(hw);
1550
1551 /*
1552 * Clear all of the statistics registers (clear on read). It is
1553 * important that we do this after we have tried to establish link
1554 * because the symbol error count will increment wildly if there
1555 * is no link.
1556 */
1557 igb_clear_hw_cntrs_82575(hw);
1558 return ret_val;
1559 }
1560
1561 /**
1562 * igb_setup_copper_link_82575 - Configure copper link settings
1563 * @hw: pointer to the HW structure
1564 *
1565 * Configures the link for auto-neg or forced speed and duplex. Then we check
1566 * for link, once link is established calls to configure collision distance
1567 * and flow control are called.
1568 **/
1569 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1570 {
1571 u32 ctrl;
1572 s32 ret_val;
1573 u32 phpm_reg;
1574
1575 ctrl = rd32(E1000_CTRL);
1576 ctrl |= E1000_CTRL_SLU;
1577 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1578 wr32(E1000_CTRL, ctrl);
1579
1580 /* Clear Go Link Disconnect bit */
1581 if (hw->mac.type >= e1000_82580) {
1582 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1583 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1584 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1585 }
1586
1587 ret_val = igb_setup_serdes_link_82575(hw);
1588 if (ret_val)
1589 goto out;
1590
1591 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1592 /* allow time for SFP cage time to power up phy */
1593 msleep(300);
1594
1595 ret_val = hw->phy.ops.reset(hw);
1596 if (ret_val) {
1597 hw_dbg("Error resetting the PHY.\n");
1598 goto out;
1599 }
1600 }
1601 switch (hw->phy.type) {
1602 case e1000_phy_i210:
1603 case e1000_phy_m88:
1604 if (hw->phy.id == I347AT4_E_PHY_ID ||
1605 hw->phy.id == M88E1112_E_PHY_ID)
1606 ret_val = igb_copper_link_setup_m88_gen2(hw);
1607 else
1608 ret_val = igb_copper_link_setup_m88(hw);
1609 break;
1610 case e1000_phy_igp_3:
1611 ret_val = igb_copper_link_setup_igp(hw);
1612 break;
1613 case e1000_phy_82580:
1614 ret_val = igb_copper_link_setup_82580(hw);
1615 break;
1616 default:
1617 ret_val = -E1000_ERR_PHY;
1618 break;
1619 }
1620
1621 if (ret_val)
1622 goto out;
1623
1624 ret_val = igb_setup_copper_link(hw);
1625 out:
1626 return ret_val;
1627 }
1628
1629 /**
1630 * igb_setup_serdes_link_82575 - Setup link for serdes
1631 * @hw: pointer to the HW structure
1632 *
1633 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1634 * used on copper connections where the serialized gigabit media independent
1635 * interface (sgmii), or serdes fiber is being used. Configures the link
1636 * for auto-negotiation or forces speed/duplex.
1637 **/
1638 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1639 {
1640 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1641 bool pcs_autoneg;
1642 s32 ret_val = E1000_SUCCESS;
1643 u16 data;
1644
1645 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1646 !igb_sgmii_active_82575(hw))
1647 return ret_val;
1648
1649
1650 /*
1651 * On the 82575, SerDes loopback mode persists until it is
1652 * explicitly turned off or a power cycle is performed. A read to
1653 * the register does not indicate its status. Therefore, we ensure
1654 * loopback mode is disabled during initialization.
1655 */
1656 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1657
1658 /* power on the sfp cage if present */
1659 ctrl_ext = rd32(E1000_CTRL_EXT);
1660 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1661 wr32(E1000_CTRL_EXT, ctrl_ext);
1662
1663 ctrl_reg = rd32(E1000_CTRL);
1664 ctrl_reg |= E1000_CTRL_SLU;
1665
1666 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1667 /* set both sw defined pins */
1668 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1669
1670 /* Set switch control to serdes energy detect */
1671 reg = rd32(E1000_CONNSW);
1672 reg |= E1000_CONNSW_ENRGSRC;
1673 wr32(E1000_CONNSW, reg);
1674 }
1675
1676 reg = rd32(E1000_PCS_LCTL);
1677
1678 /* default pcs_autoneg to the same setting as mac autoneg */
1679 pcs_autoneg = hw->mac.autoneg;
1680
1681 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1682 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1683 /* sgmii mode lets the phy handle forcing speed/duplex */
1684 pcs_autoneg = true;
1685 /* autoneg time out should be disabled for SGMII mode */
1686 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1687 break;
1688 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1689 /* disable PCS autoneg and support parallel detect only */
1690 pcs_autoneg = false;
1691 default:
1692 if (hw->mac.type == e1000_82575 ||
1693 hw->mac.type == e1000_82576) {
1694 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1695 if (ret_val) {
1696 printk(KERN_DEBUG "NVM Read Error\n\n");
1697 return ret_val;
1698 }
1699
1700 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1701 pcs_autoneg = false;
1702 }
1703
1704 /*
1705 * non-SGMII modes only supports a speed of 1000/Full for the
1706 * link so it is best to just force the MAC and let the pcs
1707 * link either autoneg or be forced to 1000/Full
1708 */
1709 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1710 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1711
1712 /* set speed of 1000/Full if speed/duplex is forced */
1713 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1714 break;
1715 }
1716
1717 wr32(E1000_CTRL, ctrl_reg);
1718
1719 /*
1720 * New SerDes mode allows for forcing speed or autonegotiating speed
1721 * at 1gb. Autoneg should be default set by most drivers. This is the
1722 * mode that will be compatible with older link partners and switches.
1723 * However, both are supported by the hardware and some drivers/tools.
1724 */
1725 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1726 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1727
1728 if (pcs_autoneg) {
1729 /* Set PCS register for autoneg */
1730 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1731 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1732
1733 /* Disable force flow control for autoneg */
1734 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1735
1736 /* Configure flow control advertisement for autoneg */
1737 anadv_reg = rd32(E1000_PCS_ANADV);
1738 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1739 switch (hw->fc.requested_mode) {
1740 case e1000_fc_full:
1741 case e1000_fc_rx_pause:
1742 anadv_reg |= E1000_TXCW_ASM_DIR;
1743 anadv_reg |= E1000_TXCW_PAUSE;
1744 break;
1745 case e1000_fc_tx_pause:
1746 anadv_reg |= E1000_TXCW_ASM_DIR;
1747 break;
1748 default:
1749 break;
1750 }
1751 wr32(E1000_PCS_ANADV, anadv_reg);
1752
1753 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1754 } else {
1755 /* Set PCS register for forced link */
1756 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1757
1758 /* Force flow control for forced link */
1759 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1760
1761 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1762 }
1763
1764 wr32(E1000_PCS_LCTL, reg);
1765
1766 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1767 igb_force_mac_fc(hw);
1768
1769 return ret_val;
1770 }
1771
1772 /**
1773 * igb_sgmii_active_82575 - Return sgmii state
1774 * @hw: pointer to the HW structure
1775 *
1776 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1777 * which can be enabled for use in the embedded applications. Simply
1778 * return the current state of the sgmii interface.
1779 **/
1780 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1781 {
1782 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1783 return dev_spec->sgmii_active;
1784 }
1785
1786 /**
1787 * igb_reset_init_script_82575 - Inits HW defaults after reset
1788 * @hw: pointer to the HW structure
1789 *
1790 * Inits recommended HW defaults after a reset when there is no EEPROM
1791 * detected. This is only for the 82575.
1792 **/
1793 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1794 {
1795 if (hw->mac.type == e1000_82575) {
1796 hw_dbg("Running reset init script for 82575\n");
1797 /* SerDes configuration via SERDESCTRL */
1798 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1799 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1800 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1801 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1802
1803 /* CCM configuration via CCMCTL register */
1804 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1805 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1806
1807 /* PCIe lanes configuration */
1808 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1809 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1810 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1811 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1812
1813 /* PCIe PLL Configuration */
1814 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1815 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1816 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1817 }
1818
1819 return 0;
1820 }
1821
1822 /**
1823 * igb_read_mac_addr_82575 - Read device MAC address
1824 * @hw: pointer to the HW structure
1825 **/
1826 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1827 {
1828 s32 ret_val = 0;
1829
1830 /*
1831 * If there's an alternate MAC address place it in RAR0
1832 * so that it will override the Si installed default perm
1833 * address.
1834 */
1835 ret_val = igb_check_alt_mac_addr(hw);
1836 if (ret_val)
1837 goto out;
1838
1839 ret_val = igb_read_mac_addr(hw);
1840
1841 out:
1842 return ret_val;
1843 }
1844
1845 /**
1846 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1847 * @hw: pointer to the HW structure
1848 *
1849 * In the case of a PHY power down to save power, or to turn off link during a
1850 * driver unload, or wake on lan is not enabled, remove the link.
1851 **/
1852 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1853 {
1854 /* If the management interface is not enabled, then power down */
1855 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1856 igb_power_down_phy_copper(hw);
1857 }
1858
1859 /**
1860 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1861 * @hw: pointer to the HW structure
1862 *
1863 * Clears the hardware counters by reading the counter registers.
1864 **/
1865 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1866 {
1867 igb_clear_hw_cntrs_base(hw);
1868
1869 rd32(E1000_PRC64);
1870 rd32(E1000_PRC127);
1871 rd32(E1000_PRC255);
1872 rd32(E1000_PRC511);
1873 rd32(E1000_PRC1023);
1874 rd32(E1000_PRC1522);
1875 rd32(E1000_PTC64);
1876 rd32(E1000_PTC127);
1877 rd32(E1000_PTC255);
1878 rd32(E1000_PTC511);
1879 rd32(E1000_PTC1023);
1880 rd32(E1000_PTC1522);
1881
1882 rd32(E1000_ALGNERRC);
1883 rd32(E1000_RXERRC);
1884 rd32(E1000_TNCRS);
1885 rd32(E1000_CEXTERR);
1886 rd32(E1000_TSCTC);
1887 rd32(E1000_TSCTFC);
1888
1889 rd32(E1000_MGTPRC);
1890 rd32(E1000_MGTPDC);
1891 rd32(E1000_MGTPTC);
1892
1893 rd32(E1000_IAC);
1894 rd32(E1000_ICRXOC);
1895
1896 rd32(E1000_ICRXPTC);
1897 rd32(E1000_ICRXATC);
1898 rd32(E1000_ICTXPTC);
1899 rd32(E1000_ICTXATC);
1900 rd32(E1000_ICTXQEC);
1901 rd32(E1000_ICTXQMTC);
1902 rd32(E1000_ICRXDMTC);
1903
1904 rd32(E1000_CBTMPC);
1905 rd32(E1000_HTDPMC);
1906 rd32(E1000_CBRMPC);
1907 rd32(E1000_RPTHC);
1908 rd32(E1000_HGPTC);
1909 rd32(E1000_HTCBDPC);
1910 rd32(E1000_HGORCL);
1911 rd32(E1000_HGORCH);
1912 rd32(E1000_HGOTCL);
1913 rd32(E1000_HGOTCH);
1914 rd32(E1000_LENERRS);
1915
1916 /* This register should not be read in copper configurations */
1917 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1918 igb_sgmii_active_82575(hw))
1919 rd32(E1000_SCVPC);
1920 }
1921
1922 /**
1923 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1924 * @hw: pointer to the HW structure
1925 *
1926 * After rx enable if managability is enabled then there is likely some
1927 * bad data at the start of the fifo and possibly in the DMA fifo. This
1928 * function clears the fifos and flushes any packets that came in as rx was
1929 * being enabled.
1930 **/
1931 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1932 {
1933 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1934 int i, ms_wait;
1935
1936 if (hw->mac.type != e1000_82575 ||
1937 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1938 return;
1939
1940 /* Disable all RX queues */
1941 for (i = 0; i < 4; i++) {
1942 rxdctl[i] = rd32(E1000_RXDCTL(i));
1943 wr32(E1000_RXDCTL(i),
1944 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1945 }
1946 /* Poll all queues to verify they have shut down */
1947 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1948 msleep(1);
1949 rx_enabled = 0;
1950 for (i = 0; i < 4; i++)
1951 rx_enabled |= rd32(E1000_RXDCTL(i));
1952 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1953 break;
1954 }
1955
1956 if (ms_wait == 10)
1957 hw_dbg("Queue disable timed out after 10ms\n");
1958
1959 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1960 * incoming packets are rejected. Set enable and wait 2ms so that
1961 * any packet that was coming in as RCTL.EN was set is flushed
1962 */
1963 rfctl = rd32(E1000_RFCTL);
1964 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1965
1966 rlpml = rd32(E1000_RLPML);
1967 wr32(E1000_RLPML, 0);
1968
1969 rctl = rd32(E1000_RCTL);
1970 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1971 temp_rctl |= E1000_RCTL_LPE;
1972
1973 wr32(E1000_RCTL, temp_rctl);
1974 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1975 wrfl();
1976 msleep(2);
1977
1978 /* Enable RX queues that were previously enabled and restore our
1979 * previous state
1980 */
1981 for (i = 0; i < 4; i++)
1982 wr32(E1000_RXDCTL(i), rxdctl[i]);
1983 wr32(E1000_RCTL, rctl);
1984 wrfl();
1985
1986 wr32(E1000_RLPML, rlpml);
1987 wr32(E1000_RFCTL, rfctl);
1988
1989 /* Flush receive errors generated by workaround */
1990 rd32(E1000_ROC);
1991 rd32(E1000_RNBC);
1992 rd32(E1000_MPC);
1993 }
1994
1995 /**
1996 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1997 * @hw: pointer to the HW structure
1998 *
1999 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2000 * however the hardware default for these parts is 500us to 1ms which is less
2001 * than the 10ms recommended by the pci-e spec. To address this we need to
2002 * increase the value to either 10ms to 200ms for capability version 1 config,
2003 * or 16ms to 55ms for version 2.
2004 **/
2005 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2006 {
2007 u32 gcr = rd32(E1000_GCR);
2008 s32 ret_val = 0;
2009 u16 pcie_devctl2;
2010
2011 /* only take action if timeout value is defaulted to 0 */
2012 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2013 goto out;
2014
2015 /*
2016 * if capababilities version is type 1 we can write the
2017 * timeout of 10ms to 200ms through the GCR register
2018 */
2019 if (!(gcr & E1000_GCR_CAP_VER2)) {
2020 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2021 goto out;
2022 }
2023
2024 /*
2025 * for version 2 capabilities we need to write the config space
2026 * directly in order to set the completion timeout value for
2027 * 16ms to 55ms
2028 */
2029 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2030 &pcie_devctl2);
2031 if (ret_val)
2032 goto out;
2033
2034 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2035
2036 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2037 &pcie_devctl2);
2038 out:
2039 /* disable completion timeout resend */
2040 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2041
2042 wr32(E1000_GCR, gcr);
2043 return ret_val;
2044 }
2045
2046 /**
2047 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2048 * @hw: pointer to the hardware struct
2049 * @enable: state to enter, either enabled or disabled
2050 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2051 *
2052 * enables/disables L2 switch anti-spoofing functionality.
2053 **/
2054 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2055 {
2056 u32 dtxswc;
2057
2058 switch (hw->mac.type) {
2059 case e1000_82576:
2060 case e1000_i350:
2061 dtxswc = rd32(E1000_DTXSWC);
2062 if (enable) {
2063 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2064 E1000_DTXSWC_VLAN_SPOOF_MASK);
2065 /* The PF can spoof - it has to in order to
2066 * support emulation mode NICs */
2067 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2068 } else {
2069 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2070 E1000_DTXSWC_VLAN_SPOOF_MASK);
2071 }
2072 wr32(E1000_DTXSWC, dtxswc);
2073 break;
2074 default:
2075 break;
2076 }
2077 }
2078
2079 /**
2080 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2081 * @hw: pointer to the hardware struct
2082 * @enable: state to enter, either enabled or disabled
2083 *
2084 * enables/disables L2 switch loopback functionality.
2085 **/
2086 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2087 {
2088 u32 dtxswc;
2089
2090 switch (hw->mac.type) {
2091 case e1000_82576:
2092 dtxswc = rd32(E1000_DTXSWC);
2093 if (enable)
2094 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2095 else
2096 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2097 wr32(E1000_DTXSWC, dtxswc);
2098 break;
2099 case e1000_i350:
2100 dtxswc = rd32(E1000_TXSWC);
2101 if (enable)
2102 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2103 else
2104 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2105 wr32(E1000_TXSWC, dtxswc);
2106 break;
2107 default:
2108 /* Currently no other hardware supports loopback */
2109 break;
2110 }
2111
2112
2113 }
2114
2115 /**
2116 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2117 * @hw: pointer to the hardware struct
2118 * @enable: state to enter, either enabled or disabled
2119 *
2120 * enables/disables replication of packets across multiple pools.
2121 **/
2122 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2123 {
2124 u32 vt_ctl = rd32(E1000_VT_CTL);
2125
2126 if (enable)
2127 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2128 else
2129 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2130
2131 wr32(E1000_VT_CTL, vt_ctl);
2132 }
2133
2134 /**
2135 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2136 * @hw: pointer to the HW structure
2137 * @offset: register offset to be read
2138 * @data: pointer to the read data
2139 *
2140 * Reads the MDI control register in the PHY at offset and stores the
2141 * information read to data.
2142 **/
2143 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2144 {
2145 s32 ret_val;
2146
2147
2148 ret_val = hw->phy.ops.acquire(hw);
2149 if (ret_val)
2150 goto out;
2151
2152 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2153
2154 hw->phy.ops.release(hw);
2155
2156 out:
2157 return ret_val;
2158 }
2159
2160 /**
2161 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2162 * @hw: pointer to the HW structure
2163 * @offset: register offset to write to
2164 * @data: data to write to register at offset
2165 *
2166 * Writes data to MDI control register in the PHY at offset.
2167 **/
2168 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2169 {
2170 s32 ret_val;
2171
2172
2173 ret_val = hw->phy.ops.acquire(hw);
2174 if (ret_val)
2175 goto out;
2176
2177 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2178
2179 hw->phy.ops.release(hw);
2180
2181 out:
2182 return ret_val;
2183 }
2184
2185 /**
2186 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2187 * @hw: pointer to the HW structure
2188 *
2189 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2190 * the values found in the EEPROM. This addresses an issue in which these
2191 * bits are not restored from EEPROM after reset.
2192 **/
2193 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2194 {
2195 s32 ret_val = 0;
2196 u32 mdicnfg;
2197 u16 nvm_data = 0;
2198
2199 if (hw->mac.type != e1000_82580)
2200 goto out;
2201 if (!igb_sgmii_active_82575(hw))
2202 goto out;
2203
2204 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2205 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2206 &nvm_data);
2207 if (ret_val) {
2208 hw_dbg("NVM Read Error\n");
2209 goto out;
2210 }
2211
2212 mdicnfg = rd32(E1000_MDICNFG);
2213 if (nvm_data & NVM_WORD24_EXT_MDIO)
2214 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2215 if (nvm_data & NVM_WORD24_COM_MDIO)
2216 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2217 wr32(E1000_MDICNFG, mdicnfg);
2218 out:
2219 return ret_val;
2220 }
2221
2222 /**
2223 * igb_reset_hw_82580 - Reset hardware
2224 * @hw: pointer to the HW structure
2225 *
2226 * This resets function or entire device (all ports, etc.)
2227 * to a known state.
2228 **/
2229 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2230 {
2231 s32 ret_val = 0;
2232 /* BH SW mailbox bit in SW_FW_SYNC */
2233 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2234 u32 ctrl, icr;
2235 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2236
2237
2238 hw->dev_spec._82575.global_device_reset = false;
2239
2240 /* due to hw errata, global device reset doesn't always
2241 * work on 82580
2242 */
2243 if (hw->mac.type == e1000_82580)
2244 global_device_reset = false;
2245
2246 /* Get current control state. */
2247 ctrl = rd32(E1000_CTRL);
2248
2249 /*
2250 * Prevent the PCI-E bus from sticking if there is no TLP connection
2251 * on the last TLP read/write transaction when MAC is reset.
2252 */
2253 ret_val = igb_disable_pcie_master(hw);
2254 if (ret_val)
2255 hw_dbg("PCI-E Master disable polling has failed.\n");
2256
2257 hw_dbg("Masking off all interrupts\n");
2258 wr32(E1000_IMC, 0xffffffff);
2259 wr32(E1000_RCTL, 0);
2260 wr32(E1000_TCTL, E1000_TCTL_PSP);
2261 wrfl();
2262
2263 msleep(10);
2264
2265 /* Determine whether or not a global dev reset is requested */
2266 if (global_device_reset &&
2267 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2268 global_device_reset = false;
2269
2270 if (global_device_reset &&
2271 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2272 ctrl |= E1000_CTRL_DEV_RST;
2273 else
2274 ctrl |= E1000_CTRL_RST;
2275
2276 wr32(E1000_CTRL, ctrl);
2277 wrfl();
2278
2279 /* Add delay to insure DEV_RST has time to complete */
2280 if (global_device_reset)
2281 msleep(5);
2282
2283 ret_val = igb_get_auto_rd_done(hw);
2284 if (ret_val) {
2285 /*
2286 * When auto config read does not complete, do not
2287 * return with an error. This can happen in situations
2288 * where there is no eeprom and prevents getting link.
2289 */
2290 hw_dbg("Auto Read Done did not complete\n");
2291 }
2292
2293 /* If EEPROM is not present, run manual init scripts */
2294 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
2295 igb_reset_init_script_82575(hw);
2296
2297 /* clear global device reset status bit */
2298 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2299
2300 /* Clear any pending interrupt events. */
2301 wr32(E1000_IMC, 0xffffffff);
2302 icr = rd32(E1000_ICR);
2303
2304 ret_val = igb_reset_mdicnfg_82580(hw);
2305 if (ret_val)
2306 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2307
2308 /* Install any alternate MAC address into RAR0 */
2309 ret_val = igb_check_alt_mac_addr(hw);
2310
2311 /* Release semaphore */
2312 if (global_device_reset)
2313 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2314
2315 return ret_val;
2316 }
2317
2318 /**
2319 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2320 * @data: data received by reading RXPBS register
2321 *
2322 * The 82580 uses a table based approach for packet buffer allocation sizes.
2323 * This function converts the retrieved value into the correct table value
2324 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2325 * 0x0 36 72 144 1 2 4 8 16
2326 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2327 */
2328 u16 igb_rxpbs_adjust_82580(u32 data)
2329 {
2330 u16 ret_val = 0;
2331
2332 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2333 ret_val = e1000_82580_rxpbs_table[data];
2334
2335 return ret_val;
2336 }
2337
2338 /**
2339 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2340 * checksum
2341 * @hw: pointer to the HW structure
2342 * @offset: offset in words of the checksum protected region
2343 *
2344 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2345 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2346 **/
2347 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2348 u16 offset)
2349 {
2350 s32 ret_val = 0;
2351 u16 checksum = 0;
2352 u16 i, nvm_data;
2353
2354 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2355 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2356 if (ret_val) {
2357 hw_dbg("NVM Read Error\n");
2358 goto out;
2359 }
2360 checksum += nvm_data;
2361 }
2362
2363 if (checksum != (u16) NVM_SUM) {
2364 hw_dbg("NVM Checksum Invalid\n");
2365 ret_val = -E1000_ERR_NVM;
2366 goto out;
2367 }
2368
2369 out:
2370 return ret_val;
2371 }
2372
2373 /**
2374 * igb_update_nvm_checksum_with_offset - Update EEPROM
2375 * checksum
2376 * @hw: pointer to the HW structure
2377 * @offset: offset in words of the checksum protected region
2378 *
2379 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2380 * up to the checksum. Then calculates the EEPROM checksum and writes the
2381 * value to the EEPROM.
2382 **/
2383 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2384 {
2385 s32 ret_val;
2386 u16 checksum = 0;
2387 u16 i, nvm_data;
2388
2389 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2390 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2391 if (ret_val) {
2392 hw_dbg("NVM Read Error while updating checksum.\n");
2393 goto out;
2394 }
2395 checksum += nvm_data;
2396 }
2397 checksum = (u16) NVM_SUM - checksum;
2398 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2399 &checksum);
2400 if (ret_val)
2401 hw_dbg("NVM Write Error while updating checksum.\n");
2402
2403 out:
2404 return ret_val;
2405 }
2406
2407 /**
2408 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2409 * @hw: pointer to the HW structure
2410 *
2411 * Calculates the EEPROM section checksum by reading/adding each word of
2412 * the EEPROM and then verifies that the sum of the EEPROM is
2413 * equal to 0xBABA.
2414 **/
2415 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2416 {
2417 s32 ret_val = 0;
2418 u16 eeprom_regions_count = 1;
2419 u16 j, nvm_data;
2420 u16 nvm_offset;
2421
2422 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2423 if (ret_val) {
2424 hw_dbg("NVM Read Error\n");
2425 goto out;
2426 }
2427
2428 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2429 /* if checksums compatibility bit is set validate checksums
2430 * for all 4 ports. */
2431 eeprom_regions_count = 4;
2432 }
2433
2434 for (j = 0; j < eeprom_regions_count; j++) {
2435 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2436 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2437 nvm_offset);
2438 if (ret_val != 0)
2439 goto out;
2440 }
2441
2442 out:
2443 return ret_val;
2444 }
2445
2446 /**
2447 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2448 * @hw: pointer to the HW structure
2449 *
2450 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2451 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2452 * checksum and writes the value to the EEPROM.
2453 **/
2454 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2455 {
2456 s32 ret_val;
2457 u16 j, nvm_data;
2458 u16 nvm_offset;
2459
2460 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2461 if (ret_val) {
2462 hw_dbg("NVM Read Error while updating checksum"
2463 " compatibility bit.\n");
2464 goto out;
2465 }
2466
2467 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2468 /* set compatibility bit to validate checksums appropriately */
2469 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2470 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2471 &nvm_data);
2472 if (ret_val) {
2473 hw_dbg("NVM Write Error while updating checksum"
2474 " compatibility bit.\n");
2475 goto out;
2476 }
2477 }
2478
2479 for (j = 0; j < 4; j++) {
2480 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2481 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2482 if (ret_val)
2483 goto out;
2484 }
2485
2486 out:
2487 return ret_val;
2488 }
2489
2490 /**
2491 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2492 * @hw: pointer to the HW structure
2493 *
2494 * Calculates the EEPROM section checksum by reading/adding each word of
2495 * the EEPROM and then verifies that the sum of the EEPROM is
2496 * equal to 0xBABA.
2497 **/
2498 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2499 {
2500 s32 ret_val = 0;
2501 u16 j;
2502 u16 nvm_offset;
2503
2504 for (j = 0; j < 4; j++) {
2505 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2506 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2507 nvm_offset);
2508 if (ret_val != 0)
2509 goto out;
2510 }
2511
2512 out:
2513 return ret_val;
2514 }
2515
2516 /**
2517 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2518 * @hw: pointer to the HW structure
2519 *
2520 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2521 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2522 * checksum and writes the value to the EEPROM.
2523 **/
2524 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2525 {
2526 s32 ret_val = 0;
2527 u16 j;
2528 u16 nvm_offset;
2529
2530 for (j = 0; j < 4; j++) {
2531 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2532 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2533 if (ret_val != 0)
2534 goto out;
2535 }
2536
2537 out:
2538 return ret_val;
2539 }
2540
2541 /**
2542 * igb_set_eee_i350 - Enable/disable EEE support
2543 * @hw: pointer to the HW structure
2544 *
2545 * Enable/disable EEE based on setting in dev_spec structure.
2546 *
2547 **/
2548 s32 igb_set_eee_i350(struct e1000_hw *hw)
2549 {
2550 s32 ret_val = 0;
2551 u32 ipcnfg, eeer;
2552
2553 if ((hw->mac.type < e1000_i350) ||
2554 (hw->phy.media_type != e1000_media_type_copper))
2555 goto out;
2556 ipcnfg = rd32(E1000_IPCNFG);
2557 eeer = rd32(E1000_EEER);
2558
2559 /* enable or disable per user setting */
2560 if (!(hw->dev_spec._82575.eee_disable)) {
2561 u32 eee_su = rd32(E1000_EEE_SU);
2562
2563 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2564 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2565 E1000_EEER_LPI_FC);
2566
2567 /* This bit should not be set in normal operation. */
2568 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2569 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2570
2571
2572 } else {
2573 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2574 E1000_IPCNFG_EEE_100M_AN);
2575 eeer &= ~(E1000_EEER_TX_LPI_EN |
2576 E1000_EEER_RX_LPI_EN |
2577 E1000_EEER_LPI_FC);
2578 }
2579 wr32(E1000_IPCNFG, ipcnfg);
2580 wr32(E1000_EEER, eeer);
2581 rd32(E1000_IPCNFG);
2582 rd32(E1000_EEER);
2583 out:
2584
2585 return ret_val;
2586 }
2587
2588 static const u8 e1000_emc_temp_data[4] = {
2589 E1000_EMC_INTERNAL_DATA,
2590 E1000_EMC_DIODE1_DATA,
2591 E1000_EMC_DIODE2_DATA,
2592 E1000_EMC_DIODE3_DATA
2593 };
2594 static const u8 e1000_emc_therm_limit[4] = {
2595 E1000_EMC_INTERNAL_THERM_LIMIT,
2596 E1000_EMC_DIODE1_THERM_LIMIT,
2597 E1000_EMC_DIODE2_THERM_LIMIT,
2598 E1000_EMC_DIODE3_THERM_LIMIT
2599 };
2600
2601 /* igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2602 * @hw: pointer to hardware structure
2603 *
2604 * Updates the temperatures in mac.thermal_sensor_data
2605 */
2606 s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2607 {
2608 s32 status = E1000_SUCCESS;
2609 u16 ets_offset;
2610 u16 ets_cfg;
2611 u16 ets_sensor;
2612 u8 num_sensors;
2613 u8 sensor_index;
2614 u8 sensor_location;
2615 u8 i;
2616 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2617
2618 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2619 return E1000_NOT_IMPLEMENTED;
2620
2621 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2622
2623 /* Return the internal sensor only if ETS is unsupported */
2624 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2625 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2626 return status;
2627
2628 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2629 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2630 != NVM_ETS_TYPE_EMC)
2631 return E1000_NOT_IMPLEMENTED;
2632
2633 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2634 if (num_sensors > E1000_MAX_SENSORS)
2635 num_sensors = E1000_MAX_SENSORS;
2636
2637 for (i = 1; i < num_sensors; i++) {
2638 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2639 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2640 NVM_ETS_DATA_INDEX_SHIFT);
2641 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2642 NVM_ETS_DATA_LOC_SHIFT);
2643
2644 if (sensor_location != 0)
2645 hw->phy.ops.read_i2c_byte(hw,
2646 e1000_emc_temp_data[sensor_index],
2647 E1000_I2C_THERMAL_SENSOR_ADDR,
2648 &data->sensor[i].temp);
2649 }
2650 return status;
2651 }
2652
2653 /* igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2654 * @hw: pointer to hardware structure
2655 *
2656 * Sets the thermal sensor thresholds according to the NVM map
2657 * and save off the threshold and location values into mac.thermal_sensor_data
2658 */
2659 s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2660 {
2661 s32 status = E1000_SUCCESS;
2662 u16 ets_offset;
2663 u16 ets_cfg;
2664 u16 ets_sensor;
2665 u8 low_thresh_delta;
2666 u8 num_sensors;
2667 u8 sensor_index;
2668 u8 sensor_location;
2669 u8 therm_limit;
2670 u8 i;
2671 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2672
2673 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2674 return E1000_NOT_IMPLEMENTED;
2675
2676 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2677
2678 data->sensor[0].location = 0x1;
2679 data->sensor[0].caution_thresh =
2680 (rd32(E1000_THHIGHTC) & 0xFF);
2681 data->sensor[0].max_op_thresh =
2682 (rd32(E1000_THLOWTC) & 0xFF);
2683
2684 /* Return the internal sensor only if ETS is unsupported */
2685 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2686 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2687 return status;
2688
2689 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2690 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2691 != NVM_ETS_TYPE_EMC)
2692 return E1000_NOT_IMPLEMENTED;
2693
2694 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2695 NVM_ETS_LTHRES_DELTA_SHIFT);
2696 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2697
2698 for (i = 1; i <= num_sensors; i++) {
2699 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2700 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2701 NVM_ETS_DATA_INDEX_SHIFT);
2702 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2703 NVM_ETS_DATA_LOC_SHIFT);
2704 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2705
2706 hw->phy.ops.write_i2c_byte(hw,
2707 e1000_emc_therm_limit[sensor_index],
2708 E1000_I2C_THERMAL_SENSOR_ADDR,
2709 therm_limit);
2710
2711 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2712 data->sensor[i].location = sensor_location;
2713 data->sensor[i].caution_thresh = therm_limit;
2714 data->sensor[i].max_op_thresh = therm_limit -
2715 low_thresh_delta;
2716 }
2717 }
2718 return status;
2719 }
2720
2721 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2722 .init_hw = igb_init_hw_82575,
2723 .check_for_link = igb_check_for_link_82575,
2724 .rar_set = igb_rar_set,
2725 .read_mac_addr = igb_read_mac_addr_82575,
2726 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
2727 #ifdef CONFIG_IGB_HWMON
2728 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2729 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2730 #endif
2731 };
2732
2733 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2734 .acquire = igb_acquire_phy_82575,
2735 .get_cfg_done = igb_get_cfg_done_82575,
2736 .release = igb_release_phy_82575,
2737 .write_i2c_byte = igb_write_i2c_byte,
2738 .read_i2c_byte = igb_read_i2c_byte,
2739 };
2740
2741 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2742 .acquire = igb_acquire_nvm_82575,
2743 .read = igb_read_nvm_eerd,
2744 .release = igb_release_nvm_82575,
2745 .write = igb_write_nvm_spi,
2746 };
2747
2748 const struct e1000_info e1000_82575_info = {
2749 .get_invariants = igb_get_invariants_82575,
2750 .mac_ops = &e1000_mac_ops_82575,
2751 .phy_ops = &e1000_phy_ops_82575,
2752 .nvm_ops = &e1000_nvm_ops_82575,
2753 };
2754
Linux kernel - Deliverables
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