1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
42 static s32
igb_get_invariants_82575(struct e1000_hw
*);
43 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
44 static void igb_release_phy_82575(struct e1000_hw
*);
45 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
46 static void igb_release_nvm_82575(struct e1000_hw
*);
47 static s32
igb_check_for_link_82575(struct e1000_hw
*);
48 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
49 static s32
igb_init_hw_82575(struct e1000_hw
*);
50 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
51 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
52 static s32
igb_read_phy_reg_82580(struct e1000_hw
*, u32
, u16
*);
53 static s32
igb_write_phy_reg_82580(struct e1000_hw
*, u32
, u16
);
54 static s32
igb_reset_hw_82575(struct e1000_hw
*);
55 static s32
igb_reset_hw_82580(struct e1000_hw
*);
56 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
57 static s32
igb_set_d0_lplu_state_82580(struct e1000_hw
*, bool);
58 static s32
igb_set_d3_lplu_state_82580(struct e1000_hw
*, bool);
59 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
60 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*);
61 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
63 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
64 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
66 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
67 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
68 static bool igb_sgmii_active_82575(struct e1000_hw
*);
69 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
70 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
71 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
);
72 static s32
igb_reset_mdicnfg_82580(struct e1000_hw
*hw
);
73 static s32
igb_validate_nvm_checksum_82580(struct e1000_hw
*hw
);
74 static s32
igb_update_nvm_checksum_82580(struct e1000_hw
*hw
);
75 static s32
igb_validate_nvm_checksum_i350(struct e1000_hw
*hw
);
76 static s32
igb_update_nvm_checksum_i350(struct e1000_hw
*hw
);
77 static const u16 e1000_82580_rxpbs_table
[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw
*hw
)
93 bool ext_mdio
= false;
95 switch (hw
->mac
.type
) {
98 reg
= rd32(E1000_MDIC
);
99 ext_mdio
= !!(reg
& E1000_MDIC_DEST
);
106 reg
= rd32(E1000_MDICNFG
);
107 ext_mdio
= !!(reg
& E1000_MDICNFG_EXT_MDIO
);
116 * igb_init_phy_params_82575 - Init PHY func ptrs.
117 * @hw: pointer to the HW structure
119 static s32
igb_init_phy_params_82575(struct e1000_hw
*hw
)
121 struct e1000_phy_info
*phy
= &hw
->phy
;
125 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
126 phy
->type
= e1000_phy_none
;
130 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
131 phy
->reset_delay_us
= 100;
133 ctrl_ext
= rd32(E1000_CTRL_EXT
);
135 if (igb_sgmii_active_82575(hw
)) {
136 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
137 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
139 phy
->ops
.reset
= igb_phy_hw_reset
;
140 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
143 wr32(E1000_CTRL_EXT
, ctrl_ext
);
144 igb_reset_mdicnfg_82580(hw
);
146 if (igb_sgmii_active_82575(hw
) && !igb_sgmii_uses_mdio_82575(hw
)) {
147 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
148 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
150 switch (hw
->mac
.type
) {
154 phy
->ops
.read_reg
= igb_read_phy_reg_82580
;
155 phy
->ops
.write_reg
= igb_write_phy_reg_82580
;
159 phy
->ops
.read_reg
= igb_read_phy_reg_gs40g
;
160 phy
->ops
.write_reg
= igb_write_phy_reg_gs40g
;
163 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
164 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
169 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
170 E1000_STATUS_FUNC_SHIFT
;
172 /* Set phy->phy_addr and phy->id. */
173 ret_val
= igb_get_phy_id_82575(hw
);
177 /* Verify phy id and set remaining function pointers */
179 case M88E1545_E_PHY_ID
:
180 case I347AT4_E_PHY_ID
:
181 case M88E1112_E_PHY_ID
:
182 case M88E1111_I_PHY_ID
:
183 phy
->type
= e1000_phy_m88
;
184 phy
->ops
.check_polarity
= igb_check_polarity_m88
;
185 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
186 if (phy
->id
!= M88E1111_I_PHY_ID
)
187 phy
->ops
.get_cable_length
=
188 igb_get_cable_length_m88_gen2
;
190 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
191 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
193 case IGP03E1000_E_PHY_ID
:
194 phy
->type
= e1000_phy_igp_3
;
195 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
196 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
197 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
198 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
199 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
201 case I82580_I_PHY_ID
:
203 phy
->type
= e1000_phy_82580
;
204 phy
->ops
.force_speed_duplex
=
205 igb_phy_force_speed_duplex_82580
;
206 phy
->ops
.get_cable_length
= igb_get_cable_length_82580
;
207 phy
->ops
.get_phy_info
= igb_get_phy_info_82580
;
208 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
209 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
212 phy
->type
= e1000_phy_i210
;
213 phy
->ops
.check_polarity
= igb_check_polarity_m88
;
214 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
215 phy
->ops
.get_cable_length
= igb_get_cable_length_m88_gen2
;
216 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
217 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
218 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
221 ret_val
= -E1000_ERR_PHY
;
230 * igb_init_nvm_params_82575 - Init NVM func ptrs.
231 * @hw: pointer to the HW structure
233 static s32
igb_init_nvm_params_82575(struct e1000_hw
*hw
)
235 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
236 u32 eecd
= rd32(E1000_EECD
);
239 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
240 E1000_EECD_SIZE_EX_SHIFT
);
242 /* Added to a constant, "size" becomes the left-shift value
243 * for setting word_size.
245 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
247 /* Just in case size is out of range, cap it to the largest
248 * EEPROM size supported
253 nvm
->word_size
= 1 << size
;
254 nvm
->opcode_bits
= 8;
257 switch (nvm
->override
) {
258 case e1000_nvm_override_spi_large
:
260 nvm
->address_bits
= 16;
262 case e1000_nvm_override_spi_small
:
264 nvm
->address_bits
= 8;
267 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
268 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
?
272 if (nvm
->word_size
== (1 << 15))
273 nvm
->page_size
= 128;
275 nvm
->type
= e1000_nvm_eeprom_spi
;
277 /* NVM Function Pointers */
278 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
279 nvm
->ops
.release
= igb_release_nvm_82575
;
280 nvm
->ops
.write
= igb_write_nvm_spi
;
281 nvm
->ops
.validate
= igb_validate_nvm_checksum
;
282 nvm
->ops
.update
= igb_update_nvm_checksum
;
283 if (nvm
->word_size
< (1 << 15))
284 nvm
->ops
.read
= igb_read_nvm_eerd
;
286 nvm
->ops
.read
= igb_read_nvm_spi
;
288 /* override generic family function pointers for specific descendants */
289 switch (hw
->mac
.type
) {
291 nvm
->ops
.validate
= igb_validate_nvm_checksum_82580
;
292 nvm
->ops
.update
= igb_update_nvm_checksum_82580
;
296 nvm
->ops
.validate
= igb_validate_nvm_checksum_i350
;
297 nvm
->ops
.update
= igb_update_nvm_checksum_i350
;
307 * igb_init_mac_params_82575 - Init MAC func ptrs.
308 * @hw: pointer to the HW structure
310 static s32
igb_init_mac_params_82575(struct e1000_hw
*hw
)
312 struct e1000_mac_info
*mac
= &hw
->mac
;
313 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
315 /* Set mta register count */
316 mac
->mta_reg_count
= 128;
317 /* Set rar entry count */
320 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
323 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82580
;
327 mac
->rar_entry_count
= E1000_RAR_ENTRIES_I350
;
330 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
334 if (mac
->type
>= e1000_82580
)
335 mac
->ops
.reset_hw
= igb_reset_hw_82580
;
337 mac
->ops
.reset_hw
= igb_reset_hw_82575
;
339 if (mac
->type
>= e1000_i210
) {
340 mac
->ops
.acquire_swfw_sync
= igb_acquire_swfw_sync_i210
;
341 mac
->ops
.release_swfw_sync
= igb_release_swfw_sync_i210
;
344 mac
->ops
.acquire_swfw_sync
= igb_acquire_swfw_sync_82575
;
345 mac
->ops
.release_swfw_sync
= igb_release_swfw_sync_82575
;
348 /* Set if part includes ASF firmware */
349 mac
->asf_firmware_present
= true;
350 /* Set if manageability features are enabled. */
351 mac
->arc_subsystem_valid
=
352 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
354 /* enable EEE on i350 parts and later parts */
355 if (mac
->type
>= e1000_i350
)
356 dev_spec
->eee_disable
= false;
358 dev_spec
->eee_disable
= true;
359 /* Allow a single clear of the SW semaphore on I210 and newer */
360 if (mac
->type
>= e1000_i210
)
361 dev_spec
->clear_semaphore_once
= true;
362 /* physical interface link setup */
363 mac
->ops
.setup_physical_interface
=
364 (hw
->phy
.media_type
== e1000_media_type_copper
)
365 ? igb_setup_copper_link_82575
366 : igb_setup_serdes_link_82575
;
372 * igb_set_sfp_media_type_82575 - derives SFP module media type.
373 * @hw: pointer to the HW structure
375 * The media type is chosen based on SFP module.
376 * compatibility flags retrieved from SFP ID EEPROM.
378 static s32
igb_set_sfp_media_type_82575(struct e1000_hw
*hw
)
380 s32 ret_val
= E1000_ERR_CONFIG
;
382 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
383 struct e1000_sfp_flags
*eth_flags
= &dev_spec
->eth_flags
;
384 u8 tranceiver_type
= 0;
387 /* Turn I2C interface ON and power on sfp cage */
388 ctrl_ext
= rd32(E1000_CTRL_EXT
);
389 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
390 wr32(E1000_CTRL_EXT
, ctrl_ext
| E1000_CTRL_I2C_ENA
);
394 /* Read SFP module data */
396 ret_val
= igb_read_sfp_data_byte(hw
,
397 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET
),
407 ret_val
= igb_read_sfp_data_byte(hw
,
408 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET
),
413 /* Check if there is some SFP module plugged and powered */
414 if ((tranceiver_type
== E1000_SFF_IDENTIFIER_SFP
) ||
415 (tranceiver_type
== E1000_SFF_IDENTIFIER_SFF
)) {
416 dev_spec
->module_plugged
= true;
417 if (eth_flags
->e1000_base_lx
|| eth_flags
->e1000_base_sx
) {
418 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
419 } else if (eth_flags
->e100_base_fx
) {
420 dev_spec
->sgmii_active
= true;
421 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
422 } else if (eth_flags
->e1000_base_t
) {
423 dev_spec
->sgmii_active
= true;
424 hw
->phy
.media_type
= e1000_media_type_copper
;
426 hw
->phy
.media_type
= e1000_media_type_unknown
;
427 hw_dbg("PHY module has not been recognized\n");
431 hw
->phy
.media_type
= e1000_media_type_unknown
;
435 /* Restore I2C interface setting */
436 wr32(E1000_CTRL_EXT
, ctrl_ext
);
440 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
442 struct e1000_mac_info
*mac
= &hw
->mac
;
443 struct e1000_dev_spec_82575
* dev_spec
= &hw
->dev_spec
._82575
;
448 switch (hw
->device_id
) {
449 case E1000_DEV_ID_82575EB_COPPER
:
450 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
451 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
452 mac
->type
= e1000_82575
;
454 case E1000_DEV_ID_82576
:
455 case E1000_DEV_ID_82576_NS
:
456 case E1000_DEV_ID_82576_NS_SERDES
:
457 case E1000_DEV_ID_82576_FIBER
:
458 case E1000_DEV_ID_82576_SERDES
:
459 case E1000_DEV_ID_82576_QUAD_COPPER
:
460 case E1000_DEV_ID_82576_QUAD_COPPER_ET2
:
461 case E1000_DEV_ID_82576_SERDES_QUAD
:
462 mac
->type
= e1000_82576
;
464 case E1000_DEV_ID_82580_COPPER
:
465 case E1000_DEV_ID_82580_FIBER
:
466 case E1000_DEV_ID_82580_QUAD_FIBER
:
467 case E1000_DEV_ID_82580_SERDES
:
468 case E1000_DEV_ID_82580_SGMII
:
469 case E1000_DEV_ID_82580_COPPER_DUAL
:
470 case E1000_DEV_ID_DH89XXCC_SGMII
:
471 case E1000_DEV_ID_DH89XXCC_SERDES
:
472 case E1000_DEV_ID_DH89XXCC_BACKPLANE
:
473 case E1000_DEV_ID_DH89XXCC_SFP
:
474 mac
->type
= e1000_82580
;
476 case E1000_DEV_ID_I350_COPPER
:
477 case E1000_DEV_ID_I350_FIBER
:
478 case E1000_DEV_ID_I350_SERDES
:
479 case E1000_DEV_ID_I350_SGMII
:
480 mac
->type
= e1000_i350
;
482 case E1000_DEV_ID_I210_COPPER
:
483 case E1000_DEV_ID_I210_FIBER
:
484 case E1000_DEV_ID_I210_SERDES
:
485 case E1000_DEV_ID_I210_SGMII
:
486 mac
->type
= e1000_i210
;
488 case E1000_DEV_ID_I211_COPPER
:
489 mac
->type
= e1000_i211
;
491 case E1000_DEV_ID_I354_BACKPLANE_1GBPS
:
492 case E1000_DEV_ID_I354_SGMII
:
493 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS
:
494 mac
->type
= e1000_i354
;
497 return -E1000_ERR_MAC_INIT
;
502 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
503 * based on the EEPROM. We cannot rely upon device ID. There
504 * is no distinguishable difference between fiber and internal
505 * SerDes mode on the 82575. There can be an external PHY attached
506 * on the SGMII interface. For this, we'll set sgmii_active to true.
508 hw
->phy
.media_type
= e1000_media_type_copper
;
509 dev_spec
->sgmii_active
= false;
510 dev_spec
->module_plugged
= false;
512 ctrl_ext
= rd32(E1000_CTRL_EXT
);
514 link_mode
= ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
;
516 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
517 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
519 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
520 /* Get phy control interface type set (MDIO vs. I2C)*/
521 if (igb_sgmii_uses_mdio_82575(hw
)) {
522 hw
->phy
.media_type
= e1000_media_type_copper
;
523 dev_spec
->sgmii_active
= true;
526 /* fall through for I2C based SGMII */
527 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
:
528 /* read media type from SFP EEPROM */
529 ret_val
= igb_set_sfp_media_type_82575(hw
);
530 if ((ret_val
!= 0) ||
531 (hw
->phy
.media_type
== e1000_media_type_unknown
)) {
532 /* If media type was not identified then return media
533 * type defined by the CTRL_EXT settings.
535 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
537 if (link_mode
== E1000_CTRL_EXT_LINK_MODE_SGMII
) {
538 hw
->phy
.media_type
= e1000_media_type_copper
;
539 dev_spec
->sgmii_active
= true;
545 /* do not change link mode for 100BaseFX */
546 if (dev_spec
->eth_flags
.e100_base_fx
)
549 /* change current link mode setting */
550 ctrl_ext
&= ~E1000_CTRL_EXT_LINK_MODE_MASK
;
552 if (hw
->phy
.media_type
== e1000_media_type_copper
)
553 ctrl_ext
|= E1000_CTRL_EXT_LINK_MODE_SGMII
;
555 ctrl_ext
|= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
;
557 wr32(E1000_CTRL_EXT
, ctrl_ext
);
564 /* mac initialization and operations */
565 ret_val
= igb_init_mac_params_82575(hw
);
569 /* NVM initialization */
570 ret_val
= igb_init_nvm_params_82575(hw
);
571 switch (hw
->mac
.type
) {
574 ret_val
= igb_init_nvm_params_i210(hw
);
583 /* if part supports SR-IOV then initialize mailbox parameters */
587 igb_init_mbx_params_pf(hw
);
593 /* setup PHY parameters */
594 ret_val
= igb_init_phy_params_82575(hw
);
601 * igb_acquire_phy_82575 - Acquire rights to access PHY
602 * @hw: pointer to the HW structure
604 * Acquire access rights to the correct PHY. This is a
605 * function pointer entry point called by the api module.
607 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
609 u16 mask
= E1000_SWFW_PHY0_SM
;
611 if (hw
->bus
.func
== E1000_FUNC_1
)
612 mask
= E1000_SWFW_PHY1_SM
;
613 else if (hw
->bus
.func
== E1000_FUNC_2
)
614 mask
= E1000_SWFW_PHY2_SM
;
615 else if (hw
->bus
.func
== E1000_FUNC_3
)
616 mask
= E1000_SWFW_PHY3_SM
;
618 return hw
->mac
.ops
.acquire_swfw_sync(hw
, mask
);
622 * igb_release_phy_82575 - Release rights to access PHY
623 * @hw: pointer to the HW structure
625 * A wrapper to release access rights to the correct PHY. This is a
626 * function pointer entry point called by the api module.
628 static void igb_release_phy_82575(struct e1000_hw
*hw
)
630 u16 mask
= E1000_SWFW_PHY0_SM
;
632 if (hw
->bus
.func
== E1000_FUNC_1
)
633 mask
= E1000_SWFW_PHY1_SM
;
634 else if (hw
->bus
.func
== E1000_FUNC_2
)
635 mask
= E1000_SWFW_PHY2_SM
;
636 else if (hw
->bus
.func
== E1000_FUNC_3
)
637 mask
= E1000_SWFW_PHY3_SM
;
639 hw
->mac
.ops
.release_swfw_sync(hw
, mask
);
643 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
644 * @hw: pointer to the HW structure
645 * @offset: register offset to be read
646 * @data: pointer to the read data
648 * Reads the PHY register at offset using the serial gigabit media independent
649 * interface and stores the retrieved information in data.
651 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
654 s32 ret_val
= -E1000_ERR_PARAM
;
656 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
657 hw_dbg("PHY Address %u is out of range\n", offset
);
661 ret_val
= hw
->phy
.ops
.acquire(hw
);
665 ret_val
= igb_read_phy_reg_i2c(hw
, offset
, data
);
667 hw
->phy
.ops
.release(hw
);
674 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
675 * @hw: pointer to the HW structure
676 * @offset: register offset to write to
677 * @data: data to write at register offset
679 * Writes the data to PHY register at the offset using the serial gigabit
680 * media independent interface.
682 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
685 s32 ret_val
= -E1000_ERR_PARAM
;
688 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
689 hw_dbg("PHY Address %d is out of range\n", offset
);
693 ret_val
= hw
->phy
.ops
.acquire(hw
);
697 ret_val
= igb_write_phy_reg_i2c(hw
, offset
, data
);
699 hw
->phy
.ops
.release(hw
);
706 * igb_get_phy_id_82575 - Retrieve PHY addr and id
707 * @hw: pointer to the HW structure
709 * Retrieves the PHY address and ID for both PHY's which do and do not use
712 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
714 struct e1000_phy_info
*phy
= &hw
->phy
;
720 /* For SGMII PHYs, we try the list of possible addresses until
721 * we find one that works. For non-SGMII PHYs
722 * (e.g. integrated copper PHYs), an address of 1 should
723 * work. The result of this function should mean phy->phy_addr
724 * and phy->id are set correctly.
726 if (!(igb_sgmii_active_82575(hw
))) {
728 ret_val
= igb_get_phy_id(hw
);
732 if (igb_sgmii_uses_mdio_82575(hw
)) {
733 switch (hw
->mac
.type
) {
736 mdic
= rd32(E1000_MDIC
);
737 mdic
&= E1000_MDIC_PHY_MASK
;
738 phy
->addr
= mdic
>> E1000_MDIC_PHY_SHIFT
;
745 mdic
= rd32(E1000_MDICNFG
);
746 mdic
&= E1000_MDICNFG_PHY_MASK
;
747 phy
->addr
= mdic
>> E1000_MDICNFG_PHY_SHIFT
;
750 ret_val
= -E1000_ERR_PHY
;
754 ret_val
= igb_get_phy_id(hw
);
758 /* Power on sgmii phy if it is disabled */
759 ctrl_ext
= rd32(E1000_CTRL_EXT
);
760 wr32(E1000_CTRL_EXT
, ctrl_ext
& ~E1000_CTRL_EXT_SDP3_DATA
);
764 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
765 * Therefore, we need to test 1-7
767 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
768 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
770 hw_dbg("Vendor ID 0x%08X read at address %u\n",
772 /* At the time of this writing, The M88 part is
773 * the only supported SGMII PHY product.
775 if (phy_id
== M88_VENDOR
)
778 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
782 /* A valid PHY type couldn't be found. */
783 if (phy
->addr
== 8) {
785 ret_val
= -E1000_ERR_PHY
;
788 ret_val
= igb_get_phy_id(hw
);
791 /* restore previous sfp cage power state */
792 wr32(E1000_CTRL_EXT
, ctrl_ext
);
799 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
800 * @hw: pointer to the HW structure
802 * Resets the PHY using the serial gigabit media independent interface.
804 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
808 /* This isn't a true "hard" reset, but is the only reset
809 * available to us at this time.
812 hw_dbg("Soft resetting SGMII attached PHY...\n");
814 /* SFP documentation requires the following to configure the SPF module
815 * to work on SGMII. No further documentation is given.
817 ret_val
= hw
->phy
.ops
.write_reg(hw
, 0x1B, 0x8084);
821 ret_val
= igb_phy_sw_reset(hw
);
828 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
829 * @hw: pointer to the HW structure
830 * @active: true to enable LPLU, false to disable
832 * Sets the LPLU D0 state according to the active flag. When
833 * activating LPLU this function also disables smart speed
834 * and vice versa. LPLU will not be activated unless the
835 * device autonegotiation advertisement meets standards of
836 * either 10 or 10/100 or 10/100/1000 at all duplexes.
837 * This is a function pointer entry point only called by
838 * PHY setup routines.
840 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
842 struct e1000_phy_info
*phy
= &hw
->phy
;
846 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
851 data
|= IGP02E1000_PM_D0_LPLU
;
852 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
857 /* When LPLU is enabled, we should disable SmartSpeed */
858 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
860 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
861 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
866 data
&= ~IGP02E1000_PM_D0_LPLU
;
867 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
869 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
870 * during Dx states where the power conservation is most
871 * important. During driver activity we should enable
872 * SmartSpeed, so performance is maintained.
874 if (phy
->smart_speed
== e1000_smart_speed_on
) {
875 ret_val
= phy
->ops
.read_reg(hw
,
876 IGP01E1000_PHY_PORT_CONFIG
, &data
);
880 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
881 ret_val
= phy
->ops
.write_reg(hw
,
882 IGP01E1000_PHY_PORT_CONFIG
, data
);
885 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
886 ret_val
= phy
->ops
.read_reg(hw
,
887 IGP01E1000_PHY_PORT_CONFIG
, &data
);
891 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
892 ret_val
= phy
->ops
.write_reg(hw
,
893 IGP01E1000_PHY_PORT_CONFIG
, data
);
904 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
905 * @hw: pointer to the HW structure
906 * @active: true to enable LPLU, false to disable
908 * Sets the LPLU D0 state according to the active flag. When
909 * activating LPLU this function also disables smart speed
910 * and vice versa. LPLU will not be activated unless the
911 * device autonegotiation advertisement meets standards of
912 * either 10 or 10/100 or 10/100/1000 at all duplexes.
913 * This is a function pointer entry point only called by
914 * PHY setup routines.
916 static s32
igb_set_d0_lplu_state_82580(struct e1000_hw
*hw
, bool active
)
918 struct e1000_phy_info
*phy
= &hw
->phy
;
922 data
= rd32(E1000_82580_PHY_POWER_MGMT
);
925 data
|= E1000_82580_PM_D0_LPLU
;
927 /* When LPLU is enabled, we should disable SmartSpeed */
928 data
&= ~E1000_82580_PM_SPD
;
930 data
&= ~E1000_82580_PM_D0_LPLU
;
932 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
933 * during Dx states where the power conservation is most
934 * important. During driver activity we should enable
935 * SmartSpeed, so performance is maintained.
937 if (phy
->smart_speed
== e1000_smart_speed_on
)
938 data
|= E1000_82580_PM_SPD
;
939 else if (phy
->smart_speed
== e1000_smart_speed_off
)
940 data
&= ~E1000_82580_PM_SPD
; }
942 wr32(E1000_82580_PHY_POWER_MGMT
, data
);
947 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
948 * @hw: pointer to the HW structure
949 * @active: boolean used to enable/disable lplu
951 * Success returns 0, Failure returns 1
953 * The low power link up (lplu) state is set to the power management level D3
954 * and SmartSpeed is disabled when active is true, else clear lplu for D3
955 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
956 * is used during Dx states where the power conservation is most important.
957 * During driver activity, SmartSpeed should be enabled so performance is
960 static s32
igb_set_d3_lplu_state_82580(struct e1000_hw
*hw
, bool active
)
962 struct e1000_phy_info
*phy
= &hw
->phy
;
966 data
= rd32(E1000_82580_PHY_POWER_MGMT
);
969 data
&= ~E1000_82580_PM_D3_LPLU
;
970 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
971 * during Dx states where the power conservation is most
972 * important. During driver activity we should enable
973 * SmartSpeed, so performance is maintained.
975 if (phy
->smart_speed
== e1000_smart_speed_on
)
976 data
|= E1000_82580_PM_SPD
;
977 else if (phy
->smart_speed
== e1000_smart_speed_off
)
978 data
&= ~E1000_82580_PM_SPD
;
979 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
980 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
981 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
982 data
|= E1000_82580_PM_D3_LPLU
;
983 /* When LPLU is enabled, we should disable SmartSpeed */
984 data
&= ~E1000_82580_PM_SPD
;
987 wr32(E1000_82580_PHY_POWER_MGMT
, data
);
992 * igb_acquire_nvm_82575 - Request for access to EEPROM
993 * @hw: pointer to the HW structure
995 * Acquire the necessary semaphores for exclusive access to the EEPROM.
996 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
997 * Return successful if access grant bit set, else clear the request for
998 * EEPROM access and return -E1000_ERR_NVM (-1).
1000 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
1004 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1008 ret_val
= igb_acquire_nvm(hw
);
1011 hw
->mac
.ops
.release_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1018 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1019 * @hw: pointer to the HW structure
1021 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1022 * then release the semaphores acquired.
1024 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
1026 igb_release_nvm(hw
);
1027 hw
->mac
.ops
.release_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1031 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1032 * @hw: pointer to the HW structure
1033 * @mask: specifies which semaphore to acquire
1035 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1036 * will also specify which port we're acquiring the lock for.
1038 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
1042 u32 fwmask
= mask
<< 16;
1044 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
1046 while (i
< timeout
) {
1047 if (igb_get_hw_semaphore(hw
)) {
1048 ret_val
= -E1000_ERR_SWFW_SYNC
;
1052 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
1053 if (!(swfw_sync
& (fwmask
| swmask
)))
1056 /* Firmware currently using resource (fwmask)
1057 * or other software thread using resource (swmask)
1059 igb_put_hw_semaphore(hw
);
1065 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1066 ret_val
= -E1000_ERR_SWFW_SYNC
;
1070 swfw_sync
|= swmask
;
1071 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
1073 igb_put_hw_semaphore(hw
);
1080 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1081 * @hw: pointer to the HW structure
1082 * @mask: specifies which semaphore to acquire
1084 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1085 * will also specify which port we're releasing the lock for.
1087 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
1091 while (igb_get_hw_semaphore(hw
) != 0);
1094 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
1096 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
1098 igb_put_hw_semaphore(hw
);
1102 * igb_get_cfg_done_82575 - Read config done bit
1103 * @hw: pointer to the HW structure
1105 * Read the management control register for the config done bit for
1106 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1107 * to read the config done bit, so an error is *ONLY* logged and returns
1108 * 0. If we were to return with error, EEPROM-less silicon
1109 * would not be able to be reset or change link.
1111 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
1113 s32 timeout
= PHY_CFG_TIMEOUT
;
1115 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
1117 if (hw
->bus
.func
== 1)
1118 mask
= E1000_NVM_CFG_DONE_PORT_1
;
1119 else if (hw
->bus
.func
== E1000_FUNC_2
)
1120 mask
= E1000_NVM_CFG_DONE_PORT_2
;
1121 else if (hw
->bus
.func
== E1000_FUNC_3
)
1122 mask
= E1000_NVM_CFG_DONE_PORT_3
;
1125 if (rd32(E1000_EEMNGCTL
) & mask
)
1131 hw_dbg("MNG configuration cycle has not completed.\n");
1133 /* If EEPROM is not marked present, init the PHY manually */
1134 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
1135 (hw
->phy
.type
== e1000_phy_igp_3
))
1136 igb_phy_init_script_igp3(hw
);
1142 * igb_check_for_link_82575 - Check for link
1143 * @hw: pointer to the HW structure
1145 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1146 * use the generic interface for determining link.
1148 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
1153 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
1154 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
1156 /* Use this flag to determine if link needs to be checked or
1157 * not. If we have link clear the flag so that we do not
1158 * continue to check for link.
1160 hw
->mac
.get_link_status
= !hw
->mac
.serdes_has_link
;
1162 /* Configure Flow Control now that Auto-Neg has completed.
1163 * First, we need to restore the desired flow control
1164 * settings because we may have had to re-autoneg with a
1165 * different link partner.
1167 ret_val
= igb_config_fc_after_link_up(hw
);
1169 hw_dbg("Error configuring flow control\n");
1171 ret_val
= igb_check_for_copper_link(hw
);
1178 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1179 * @hw: pointer to the HW structure
1181 void igb_power_up_serdes_link_82575(struct e1000_hw
*hw
)
1186 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1187 !igb_sgmii_active_82575(hw
))
1190 /* Enable PCS to turn on link */
1191 reg
= rd32(E1000_PCS_CFG0
);
1192 reg
|= E1000_PCS_CFG_PCS_EN
;
1193 wr32(E1000_PCS_CFG0
, reg
);
1195 /* Power up the laser */
1196 reg
= rd32(E1000_CTRL_EXT
);
1197 reg
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1198 wr32(E1000_CTRL_EXT
, reg
);
1200 /* flush the write to verify completion */
1206 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1207 * @hw: pointer to the HW structure
1208 * @speed: stores the current speed
1209 * @duplex: stores the current duplex
1211 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1212 * duplex, then store the values in the pointers provided.
1214 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
1217 struct e1000_mac_info
*mac
= &hw
->mac
;
1220 /* Set up defaults for the return values of this function */
1221 mac
->serdes_has_link
= false;
1225 /* Read the PCS Status register for link state. For non-copper mode,
1226 * the status register is not accurate. The PCS status register is
1229 pcs
= rd32(E1000_PCS_LSTAT
);
1231 /* The link up bit determines when link is up on autoneg. The sync ok
1232 * gets set once both sides sync up and agree upon link. Stable link
1233 * can be determined by checking for both link up and link sync ok
1235 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
1236 mac
->serdes_has_link
= true;
1238 /* Detect and store PCS speed */
1239 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
1240 *speed
= SPEED_1000
;
1241 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
1247 /* Detect and store PCS duplex */
1248 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
1249 *duplex
= FULL_DUPLEX
;
1251 *duplex
= HALF_DUPLEX
;
1259 * igb_shutdown_serdes_link_82575 - Remove link during power down
1260 * @hw: pointer to the HW structure
1262 * In the case of fiber serdes, shut down optics and PCS on driver unload
1263 * when management pass thru is not enabled.
1265 void igb_shutdown_serdes_link_82575(struct e1000_hw
*hw
)
1269 if (hw
->phy
.media_type
!= e1000_media_type_internal_serdes
&&
1270 igb_sgmii_active_82575(hw
))
1273 if (!igb_enable_mng_pass_thru(hw
)) {
1274 /* Disable PCS to turn off link */
1275 reg
= rd32(E1000_PCS_CFG0
);
1276 reg
&= ~E1000_PCS_CFG_PCS_EN
;
1277 wr32(E1000_PCS_CFG0
, reg
);
1279 /* shutdown the laser */
1280 reg
= rd32(E1000_CTRL_EXT
);
1281 reg
|= E1000_CTRL_EXT_SDP3_DATA
;
1282 wr32(E1000_CTRL_EXT
, reg
);
1284 /* flush the write to verify completion */
1291 * igb_reset_hw_82575 - Reset hardware
1292 * @hw: pointer to the HW structure
1294 * This resets the hardware into a known state. This is a
1295 * function pointer entry point called by the api module.
1297 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
1302 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1303 * on the last TLP read/write transaction when MAC is reset.
1305 ret_val
= igb_disable_pcie_master(hw
);
1307 hw_dbg("PCI-E Master disable polling has failed.\n");
1309 /* set the completion timeout for interface */
1310 ret_val
= igb_set_pcie_completion_timeout(hw
);
1312 hw_dbg("PCI-E Set completion timeout has failed.\n");
1315 hw_dbg("Masking off all interrupts\n");
1316 wr32(E1000_IMC
, 0xffffffff);
1318 wr32(E1000_RCTL
, 0);
1319 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
1324 ctrl
= rd32(E1000_CTRL
);
1326 hw_dbg("Issuing a global reset to MAC\n");
1327 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
1329 ret_val
= igb_get_auto_rd_done(hw
);
1331 /* When auto config read does not complete, do not
1332 * return with an error. This can happen in situations
1333 * where there is no eeprom and prevents getting link.
1335 hw_dbg("Auto Read Done did not complete\n");
1338 /* If EEPROM is not present, run manual init scripts */
1339 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
1340 igb_reset_init_script_82575(hw
);
1342 /* Clear any pending interrupt events. */
1343 wr32(E1000_IMC
, 0xffffffff);
1346 /* Install any alternate MAC address into RAR0 */
1347 ret_val
= igb_check_alt_mac_addr(hw
);
1353 * igb_init_hw_82575 - Initialize hardware
1354 * @hw: pointer to the HW structure
1356 * This inits the hardware readying it for operation.
1358 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
1360 struct e1000_mac_info
*mac
= &hw
->mac
;
1362 u16 i
, rar_count
= mac
->rar_entry_count
;
1364 /* Initialize identification LED */
1365 ret_val
= igb_id_led_init(hw
);
1367 hw_dbg("Error initializing identification LED\n");
1368 /* This is not fatal and we should not stop init due to this */
1371 /* Disabling VLAN filtering */
1372 hw_dbg("Initializing the IEEE VLAN\n");
1373 if ((hw
->mac
.type
== e1000_i350
) || (hw
->mac
.type
== e1000_i354
))
1374 igb_clear_vfta_i350(hw
);
1378 /* Setup the receive address */
1379 igb_init_rx_addrs(hw
, rar_count
);
1381 /* Zero out the Multicast HASH table */
1382 hw_dbg("Zeroing the MTA\n");
1383 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
1384 array_wr32(E1000_MTA
, i
, 0);
1386 /* Zero out the Unicast HASH table */
1387 hw_dbg("Zeroing the UTA\n");
1388 for (i
= 0; i
< mac
->uta_reg_count
; i
++)
1389 array_wr32(E1000_UTA
, i
, 0);
1391 /* Setup link and flow control */
1392 ret_val
= igb_setup_link(hw
);
1394 /* Clear all of the statistics registers (clear on read). It is
1395 * important that we do this after we have tried to establish link
1396 * because the symbol error count will increment wildly if there
1399 igb_clear_hw_cntrs_82575(hw
);
1404 * igb_setup_copper_link_82575 - Configure copper link settings
1405 * @hw: pointer to the HW structure
1407 * Configures the link for auto-neg or forced speed and duplex. Then we check
1408 * for link, once link is established calls to configure collision distance
1409 * and flow control are called.
1411 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
1417 ctrl
= rd32(E1000_CTRL
);
1418 ctrl
|= E1000_CTRL_SLU
;
1419 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1420 wr32(E1000_CTRL
, ctrl
);
1422 /* Clear Go Link Disconnect bit */
1423 if (hw
->mac
.type
>= e1000_82580
) {
1424 phpm_reg
= rd32(E1000_82580_PHY_POWER_MGMT
);
1425 phpm_reg
&= ~E1000_82580_PM_GO_LINKD
;
1426 wr32(E1000_82580_PHY_POWER_MGMT
, phpm_reg
);
1429 ret_val
= igb_setup_serdes_link_82575(hw
);
1433 if (igb_sgmii_active_82575(hw
) && !hw
->phy
.reset_disable
) {
1434 /* allow time for SFP cage time to power up phy */
1437 ret_val
= hw
->phy
.ops
.reset(hw
);
1439 hw_dbg("Error resetting the PHY.\n");
1443 switch (hw
->phy
.type
) {
1444 case e1000_phy_i210
:
1446 switch (hw
->phy
.id
) {
1447 case I347AT4_E_PHY_ID
:
1448 case M88E1112_E_PHY_ID
:
1449 case M88E1545_E_PHY_ID
:
1451 ret_val
= igb_copper_link_setup_m88_gen2(hw
);
1454 ret_val
= igb_copper_link_setup_m88(hw
);
1458 case e1000_phy_igp_3
:
1459 ret_val
= igb_copper_link_setup_igp(hw
);
1461 case e1000_phy_82580
:
1462 ret_val
= igb_copper_link_setup_82580(hw
);
1465 ret_val
= -E1000_ERR_PHY
;
1472 ret_val
= igb_setup_copper_link(hw
);
1478 * igb_setup_serdes_link_82575 - Setup link for serdes
1479 * @hw: pointer to the HW structure
1481 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1482 * used on copper connections where the serialized gigabit media independent
1483 * interface (sgmii), or serdes fiber is being used. Configures the link
1484 * for auto-negotiation or forces speed/duplex.
1486 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*hw
)
1488 u32 ctrl_ext
, ctrl_reg
, reg
, anadv_reg
;
1490 s32 ret_val
= E1000_SUCCESS
;
1493 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1494 !igb_sgmii_active_82575(hw
))
1498 /* On the 82575, SerDes loopback mode persists until it is
1499 * explicitly turned off or a power cycle is performed. A read to
1500 * the register does not indicate its status. Therefore, we ensure
1501 * loopback mode is disabled during initialization.
1503 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1505 /* power on the sfp cage if present and turn on I2C */
1506 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1507 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1508 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
1509 wr32(E1000_CTRL_EXT
, ctrl_ext
);
1511 ctrl_reg
= rd32(E1000_CTRL
);
1512 ctrl_reg
|= E1000_CTRL_SLU
;
1514 if (hw
->mac
.type
== e1000_82575
|| hw
->mac
.type
== e1000_82576
) {
1515 /* set both sw defined pins */
1516 ctrl_reg
|= E1000_CTRL_SWDPIN0
| E1000_CTRL_SWDPIN1
;
1518 /* Set switch control to serdes energy detect */
1519 reg
= rd32(E1000_CONNSW
);
1520 reg
|= E1000_CONNSW_ENRGSRC
;
1521 wr32(E1000_CONNSW
, reg
);
1524 reg
= rd32(E1000_PCS_LCTL
);
1526 /* default pcs_autoneg to the same setting as mac autoneg */
1527 pcs_autoneg
= hw
->mac
.autoneg
;
1529 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
1530 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
1531 /* sgmii mode lets the phy handle forcing speed/duplex */
1533 /* autoneg time out should be disabled for SGMII mode */
1534 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1536 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
1537 /* disable PCS autoneg and support parallel detect only */
1538 pcs_autoneg
= false;
1540 if (hw
->mac
.type
== e1000_82575
||
1541 hw
->mac
.type
== e1000_82576
) {
1542 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPAT
, 1, &data
);
1544 printk(KERN_DEBUG
"NVM Read Error\n\n");
1548 if (data
& E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT
)
1549 pcs_autoneg
= false;
1552 /* non-SGMII modes only supports a speed of 1000/Full for the
1553 * link so it is best to just force the MAC and let the pcs
1554 * link either autoneg or be forced to 1000/Full
1556 ctrl_reg
|= E1000_CTRL_SPD_1000
| E1000_CTRL_FRCSPD
|
1557 E1000_CTRL_FD
| E1000_CTRL_FRCDPX
;
1559 /* set speed of 1000/Full if speed/duplex is forced */
1560 reg
|= E1000_PCS_LCTL_FSV_1000
| E1000_PCS_LCTL_FDV_FULL
;
1564 wr32(E1000_CTRL
, ctrl_reg
);
1566 /* New SerDes mode allows for forcing speed or autonegotiating speed
1567 * at 1gb. Autoneg should be default set by most drivers. This is the
1568 * mode that will be compatible with older link partners and switches.
1569 * However, both are supported by the hardware and some drivers/tools.
1571 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1572 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1575 /* Set PCS register for autoneg */
1576 reg
|= E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1577 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1579 /* Disable force flow control for autoneg */
1580 reg
&= ~E1000_PCS_LCTL_FORCE_FCTRL
;
1582 /* Configure flow control advertisement for autoneg */
1583 anadv_reg
= rd32(E1000_PCS_ANADV
);
1584 anadv_reg
&= ~(E1000_TXCW_ASM_DIR
| E1000_TXCW_PAUSE
);
1585 switch (hw
->fc
.requested_mode
) {
1587 case e1000_fc_rx_pause
:
1588 anadv_reg
|= E1000_TXCW_ASM_DIR
;
1589 anadv_reg
|= E1000_TXCW_PAUSE
;
1591 case e1000_fc_tx_pause
:
1592 anadv_reg
|= E1000_TXCW_ASM_DIR
;
1597 wr32(E1000_PCS_ANADV
, anadv_reg
);
1599 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg
);
1601 /* Set PCS register for forced link */
1602 reg
|= E1000_PCS_LCTL_FSD
; /* Force Speed */
1604 /* Force flow control for forced link */
1605 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1607 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg
);
1610 wr32(E1000_PCS_LCTL
, reg
);
1612 if (!pcs_autoneg
&& !igb_sgmii_active_82575(hw
))
1613 igb_force_mac_fc(hw
);
1619 * igb_sgmii_active_82575 - Return sgmii state
1620 * @hw: pointer to the HW structure
1622 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1623 * which can be enabled for use in the embedded applications. Simply
1624 * return the current state of the sgmii interface.
1626 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1628 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
1629 return dev_spec
->sgmii_active
;
1633 * igb_reset_init_script_82575 - Inits HW defaults after reset
1634 * @hw: pointer to the HW structure
1636 * Inits recommended HW defaults after a reset when there is no EEPROM
1637 * detected. This is only for the 82575.
1639 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1641 if (hw
->mac
.type
== e1000_82575
) {
1642 hw_dbg("Running reset init script for 82575\n");
1643 /* SerDes configuration via SERDESCTRL */
1644 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1645 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1646 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1647 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1649 /* CCM configuration via CCMCTL register */
1650 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1651 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1653 /* PCIe lanes configuration */
1654 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1655 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1656 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1657 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1659 /* PCIe PLL Configuration */
1660 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1661 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1662 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1669 * igb_read_mac_addr_82575 - Read device MAC address
1670 * @hw: pointer to the HW structure
1672 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1676 /* If there's an alternate MAC address place it in RAR0
1677 * so that it will override the Si installed default perm
1680 ret_val
= igb_check_alt_mac_addr(hw
);
1684 ret_val
= igb_read_mac_addr(hw
);
1691 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1692 * @hw: pointer to the HW structure
1694 * In the case of a PHY power down to save power, or to turn off link during a
1695 * driver unload, or wake on lan is not enabled, remove the link.
1697 void igb_power_down_phy_copper_82575(struct e1000_hw
*hw
)
1699 /* If the management interface is not enabled, then power down */
1700 if (!(igb_enable_mng_pass_thru(hw
) || igb_check_reset_block(hw
)))
1701 igb_power_down_phy_copper(hw
);
1705 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1706 * @hw: pointer to the HW structure
1708 * Clears the hardware counters by reading the counter registers.
1710 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1712 igb_clear_hw_cntrs_base(hw
);
1718 rd32(E1000_PRC1023
);
1719 rd32(E1000_PRC1522
);
1724 rd32(E1000_PTC1023
);
1725 rd32(E1000_PTC1522
);
1727 rd32(E1000_ALGNERRC
);
1730 rd32(E1000_CEXTERR
);
1741 rd32(E1000_ICRXPTC
);
1742 rd32(E1000_ICRXATC
);
1743 rd32(E1000_ICTXPTC
);
1744 rd32(E1000_ICTXATC
);
1745 rd32(E1000_ICTXQEC
);
1746 rd32(E1000_ICTXQMTC
);
1747 rd32(E1000_ICRXDMTC
);
1754 rd32(E1000_HTCBDPC
);
1759 rd32(E1000_LENERRS
);
1761 /* This register should not be read in copper configurations */
1762 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
||
1763 igb_sgmii_active_82575(hw
))
1768 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1769 * @hw: pointer to the HW structure
1771 * After rx enable if managability is enabled then there is likely some
1772 * bad data at the start of the fifo and possibly in the DMA fifo. This
1773 * function clears the fifos and flushes any packets that came in as rx was
1776 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1778 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1781 if (hw
->mac
.type
!= e1000_82575
||
1782 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1785 /* Disable all RX queues */
1786 for (i
= 0; i
< 4; i
++) {
1787 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1788 wr32(E1000_RXDCTL(i
),
1789 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1791 /* Poll all queues to verify they have shut down */
1792 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1795 for (i
= 0; i
< 4; i
++)
1796 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1797 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1802 hw_dbg("Queue disable timed out after 10ms\n");
1804 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1805 * incoming packets are rejected. Set enable and wait 2ms so that
1806 * any packet that was coming in as RCTL.EN was set is flushed
1808 rfctl
= rd32(E1000_RFCTL
);
1809 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1811 rlpml
= rd32(E1000_RLPML
);
1812 wr32(E1000_RLPML
, 0);
1814 rctl
= rd32(E1000_RCTL
);
1815 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1816 temp_rctl
|= E1000_RCTL_LPE
;
1818 wr32(E1000_RCTL
, temp_rctl
);
1819 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1823 /* Enable RX queues that were previously enabled and restore our
1826 for (i
= 0; i
< 4; i
++)
1827 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1828 wr32(E1000_RCTL
, rctl
);
1831 wr32(E1000_RLPML
, rlpml
);
1832 wr32(E1000_RFCTL
, rfctl
);
1834 /* Flush receive errors generated by workaround */
1841 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1842 * @hw: pointer to the HW structure
1844 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1845 * however the hardware default for these parts is 500us to 1ms which is less
1846 * than the 10ms recommended by the pci-e spec. To address this we need to
1847 * increase the value to either 10ms to 200ms for capability version 1 config,
1848 * or 16ms to 55ms for version 2.
1850 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
)
1852 u32 gcr
= rd32(E1000_GCR
);
1856 /* only take action if timeout value is defaulted to 0 */
1857 if (gcr
& E1000_GCR_CMPL_TMOUT_MASK
)
1860 /* if capabilities version is type 1 we can write the
1861 * timeout of 10ms to 200ms through the GCR register
1863 if (!(gcr
& E1000_GCR_CAP_VER2
)) {
1864 gcr
|= E1000_GCR_CMPL_TMOUT_10ms
;
1868 /* for version 2 capabilities we need to write the config space
1869 * directly in order to set the completion timeout value for
1872 ret_val
= igb_read_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1877 pcie_devctl2
|= PCIE_DEVICE_CONTROL2_16ms
;
1879 ret_val
= igb_write_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1882 /* disable completion timeout resend */
1883 gcr
&= ~E1000_GCR_CMPL_TMOUT_RESEND
;
1885 wr32(E1000_GCR
, gcr
);
1890 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1891 * @hw: pointer to the hardware struct
1892 * @enable: state to enter, either enabled or disabled
1893 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1895 * enables/disables L2 switch anti-spoofing functionality.
1897 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw
*hw
, bool enable
, int pf
)
1899 u32 reg_val
, reg_offset
;
1901 switch (hw
->mac
.type
) {
1903 reg_offset
= E1000_DTXSWC
;
1907 reg_offset
= E1000_TXSWC
;
1913 reg_val
= rd32(reg_offset
);
1915 reg_val
|= (E1000_DTXSWC_MAC_SPOOF_MASK
|
1916 E1000_DTXSWC_VLAN_SPOOF_MASK
);
1917 /* The PF can spoof - it has to in order to
1918 * support emulation mode NICs
1920 reg_val
^= (1 << pf
| 1 << (pf
+ MAX_NUM_VFS
));
1922 reg_val
&= ~(E1000_DTXSWC_MAC_SPOOF_MASK
|
1923 E1000_DTXSWC_VLAN_SPOOF_MASK
);
1925 wr32(reg_offset
, reg_val
);
1929 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1930 * @hw: pointer to the hardware struct
1931 * @enable: state to enter, either enabled or disabled
1933 * enables/disables L2 switch loopback functionality.
1935 void igb_vmdq_set_loopback_pf(struct e1000_hw
*hw
, bool enable
)
1939 switch (hw
->mac
.type
) {
1941 dtxswc
= rd32(E1000_DTXSWC
);
1943 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1945 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1946 wr32(E1000_DTXSWC
, dtxswc
);
1950 dtxswc
= rd32(E1000_TXSWC
);
1952 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1954 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1955 wr32(E1000_TXSWC
, dtxswc
);
1958 /* Currently no other hardware supports loopback */
1965 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1966 * @hw: pointer to the hardware struct
1967 * @enable: state to enter, either enabled or disabled
1969 * enables/disables replication of packets across multiple pools.
1971 void igb_vmdq_set_replication_pf(struct e1000_hw
*hw
, bool enable
)
1973 u32 vt_ctl
= rd32(E1000_VT_CTL
);
1976 vt_ctl
|= E1000_VT_CTL_VM_REPL_EN
;
1978 vt_ctl
&= ~E1000_VT_CTL_VM_REPL_EN
;
1980 wr32(E1000_VT_CTL
, vt_ctl
);
1984 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1985 * @hw: pointer to the HW structure
1986 * @offset: register offset to be read
1987 * @data: pointer to the read data
1989 * Reads the MDI control register in the PHY at offset and stores the
1990 * information read to data.
1992 static s32
igb_read_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
1996 ret_val
= hw
->phy
.ops
.acquire(hw
);
2000 ret_val
= igb_read_phy_reg_mdic(hw
, offset
, data
);
2002 hw
->phy
.ops
.release(hw
);
2009 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2010 * @hw: pointer to the HW structure
2011 * @offset: register offset to write to
2012 * @data: data to write to register at offset
2014 * Writes data to MDI control register in the PHY at offset.
2016 static s32
igb_write_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2021 ret_val
= hw
->phy
.ops
.acquire(hw
);
2025 ret_val
= igb_write_phy_reg_mdic(hw
, offset
, data
);
2027 hw
->phy
.ops
.release(hw
);
2034 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2035 * @hw: pointer to the HW structure
2037 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2038 * the values found in the EEPROM. This addresses an issue in which these
2039 * bits are not restored from EEPROM after reset.
2041 static s32
igb_reset_mdicnfg_82580(struct e1000_hw
*hw
)
2047 if (hw
->mac
.type
!= e1000_82580
)
2049 if (!igb_sgmii_active_82575(hw
))
2052 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_A
+
2053 NVM_82580_LAN_FUNC_OFFSET(hw
->bus
.func
), 1,
2056 hw_dbg("NVM Read Error\n");
2060 mdicnfg
= rd32(E1000_MDICNFG
);
2061 if (nvm_data
& NVM_WORD24_EXT_MDIO
)
2062 mdicnfg
|= E1000_MDICNFG_EXT_MDIO
;
2063 if (nvm_data
& NVM_WORD24_COM_MDIO
)
2064 mdicnfg
|= E1000_MDICNFG_COM_MDIO
;
2065 wr32(E1000_MDICNFG
, mdicnfg
);
2071 * igb_reset_hw_82580 - Reset hardware
2072 * @hw: pointer to the HW structure
2074 * This resets function or entire device (all ports, etc.)
2077 static s32
igb_reset_hw_82580(struct e1000_hw
*hw
)
2080 /* BH SW mailbox bit in SW_FW_SYNC */
2081 u16 swmbsw_mask
= E1000_SW_SYNCH_MB
;
2083 bool global_device_reset
= hw
->dev_spec
._82575
.global_device_reset
;
2085 hw
->dev_spec
._82575
.global_device_reset
= false;
2087 /* due to hw errata, global device reset doesn't always
2090 if (hw
->mac
.type
== e1000_82580
)
2091 global_device_reset
= false;
2093 /* Get current control state. */
2094 ctrl
= rd32(E1000_CTRL
);
2096 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2097 * on the last TLP read/write transaction when MAC is reset.
2099 ret_val
= igb_disable_pcie_master(hw
);
2101 hw_dbg("PCI-E Master disable polling has failed.\n");
2103 hw_dbg("Masking off all interrupts\n");
2104 wr32(E1000_IMC
, 0xffffffff);
2105 wr32(E1000_RCTL
, 0);
2106 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
2111 /* Determine whether or not a global dev reset is requested */
2112 if (global_device_reset
&&
2113 hw
->mac
.ops
.acquire_swfw_sync(hw
, swmbsw_mask
))
2114 global_device_reset
= false;
2116 if (global_device_reset
&&
2117 !(rd32(E1000_STATUS
) & E1000_STAT_DEV_RST_SET
))
2118 ctrl
|= E1000_CTRL_DEV_RST
;
2120 ctrl
|= E1000_CTRL_RST
;
2122 wr32(E1000_CTRL
, ctrl
);
2125 /* Add delay to insure DEV_RST has time to complete */
2126 if (global_device_reset
)
2129 ret_val
= igb_get_auto_rd_done(hw
);
2131 /* When auto config read does not complete, do not
2132 * return with an error. This can happen in situations
2133 * where there is no eeprom and prevents getting link.
2135 hw_dbg("Auto Read Done did not complete\n");
2138 /* clear global device reset status bit */
2139 wr32(E1000_STATUS
, E1000_STAT_DEV_RST_SET
);
2141 /* Clear any pending interrupt events. */
2142 wr32(E1000_IMC
, 0xffffffff);
2145 ret_val
= igb_reset_mdicnfg_82580(hw
);
2147 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2149 /* Install any alternate MAC address into RAR0 */
2150 ret_val
= igb_check_alt_mac_addr(hw
);
2152 /* Release semaphore */
2153 if (global_device_reset
)
2154 hw
->mac
.ops
.release_swfw_sync(hw
, swmbsw_mask
);
2160 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2161 * @data: data received by reading RXPBS register
2163 * The 82580 uses a table based approach for packet buffer allocation sizes.
2164 * This function converts the retrieved value into the correct table value
2165 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2166 * 0x0 36 72 144 1 2 4 8 16
2167 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2169 u16
igb_rxpbs_adjust_82580(u32 data
)
2173 if (data
< E1000_82580_RXPBS_TABLE_SIZE
)
2174 ret_val
= e1000_82580_rxpbs_table
[data
];
2180 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2182 * @hw: pointer to the HW structure
2183 * @offset: offset in words of the checksum protected region
2185 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2186 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2188 static s32
igb_validate_nvm_checksum_with_offset(struct e1000_hw
*hw
,
2195 for (i
= offset
; i
< ((NVM_CHECKSUM_REG
+ offset
) + 1); i
++) {
2196 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
2198 hw_dbg("NVM Read Error\n");
2201 checksum
+= nvm_data
;
2204 if (checksum
!= (u16
) NVM_SUM
) {
2205 hw_dbg("NVM Checksum Invalid\n");
2206 ret_val
= -E1000_ERR_NVM
;
2215 * igb_update_nvm_checksum_with_offset - Update EEPROM
2217 * @hw: pointer to the HW structure
2218 * @offset: offset in words of the checksum protected region
2220 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2221 * up to the checksum. Then calculates the EEPROM checksum and writes the
2222 * value to the EEPROM.
2224 static s32
igb_update_nvm_checksum_with_offset(struct e1000_hw
*hw
, u16 offset
)
2230 for (i
= offset
; i
< (NVM_CHECKSUM_REG
+ offset
); i
++) {
2231 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
2233 hw_dbg("NVM Read Error while updating checksum.\n");
2236 checksum
+= nvm_data
;
2238 checksum
= (u16
) NVM_SUM
- checksum
;
2239 ret_val
= hw
->nvm
.ops
.write(hw
, (NVM_CHECKSUM_REG
+ offset
), 1,
2242 hw_dbg("NVM Write Error while updating checksum.\n");
2249 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2250 * @hw: pointer to the HW structure
2252 * Calculates the EEPROM section checksum by reading/adding each word of
2253 * the EEPROM and then verifies that the sum of the EEPROM is
2256 static s32
igb_validate_nvm_checksum_82580(struct e1000_hw
*hw
)
2259 u16 eeprom_regions_count
= 1;
2263 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPATIBILITY_REG_3
, 1, &nvm_data
);
2265 hw_dbg("NVM Read Error\n");
2269 if (nvm_data
& NVM_COMPATIBILITY_BIT_MASK
) {
2270 /* if checksums compatibility bit is set validate checksums
2273 eeprom_regions_count
= 4;
2276 for (j
= 0; j
< eeprom_regions_count
; j
++) {
2277 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2278 ret_val
= igb_validate_nvm_checksum_with_offset(hw
,
2289 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2290 * @hw: pointer to the HW structure
2292 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2293 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2294 * checksum and writes the value to the EEPROM.
2296 static s32
igb_update_nvm_checksum_82580(struct e1000_hw
*hw
)
2302 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPATIBILITY_REG_3
, 1, &nvm_data
);
2304 hw_dbg("NVM Read Error while updating checksum"
2305 " compatibility bit.\n");
2309 if ((nvm_data
& NVM_COMPATIBILITY_BIT_MASK
) == 0) {
2310 /* set compatibility bit to validate checksums appropriately */
2311 nvm_data
= nvm_data
| NVM_COMPATIBILITY_BIT_MASK
;
2312 ret_val
= hw
->nvm
.ops
.write(hw
, NVM_COMPATIBILITY_REG_3
, 1,
2315 hw_dbg("NVM Write Error while updating checksum"
2316 " compatibility bit.\n");
2321 for (j
= 0; j
< 4; j
++) {
2322 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2323 ret_val
= igb_update_nvm_checksum_with_offset(hw
, nvm_offset
);
2333 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2334 * @hw: pointer to the HW structure
2336 * Calculates the EEPROM section checksum by reading/adding each word of
2337 * the EEPROM and then verifies that the sum of the EEPROM is
2340 static s32
igb_validate_nvm_checksum_i350(struct e1000_hw
*hw
)
2346 for (j
= 0; j
< 4; j
++) {
2347 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2348 ret_val
= igb_validate_nvm_checksum_with_offset(hw
,
2359 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2360 * @hw: pointer to the HW structure
2362 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2363 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2364 * checksum and writes the value to the EEPROM.
2366 static s32
igb_update_nvm_checksum_i350(struct e1000_hw
*hw
)
2372 for (j
= 0; j
< 4; j
++) {
2373 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2374 ret_val
= igb_update_nvm_checksum_with_offset(hw
, nvm_offset
);
2384 * __igb_access_emi_reg - Read/write EMI register
2385 * @hw: pointer to the HW structure
2386 * @addr: EMI address to program
2387 * @data: pointer to value to read/write from/to the EMI address
2388 * @read: boolean flag to indicate read or write
2390 static s32
__igb_access_emi_reg(struct e1000_hw
*hw
, u16 address
,
2391 u16
*data
, bool read
)
2393 s32 ret_val
= E1000_SUCCESS
;
2395 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_EMIADD
, address
);
2400 ret_val
= hw
->phy
.ops
.read_reg(hw
, E1000_EMIDATA
, data
);
2402 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_EMIDATA
, *data
);
2408 * igb_read_emi_reg - Read Extended Management Interface register
2409 * @hw: pointer to the HW structure
2410 * @addr: EMI address to program
2411 * @data: value to be read from the EMI address
2413 s32
igb_read_emi_reg(struct e1000_hw
*hw
, u16 addr
, u16
*data
)
2415 return __igb_access_emi_reg(hw
, addr
, data
, true);
2419 * igb_set_eee_i350 - Enable/disable EEE support
2420 * @hw: pointer to the HW structure
2422 * Enable/disable EEE based on setting in dev_spec structure.
2425 s32
igb_set_eee_i350(struct e1000_hw
*hw
)
2430 if ((hw
->mac
.type
< e1000_i350
) ||
2431 (hw
->phy
.media_type
!= e1000_media_type_copper
))
2433 ipcnfg
= rd32(E1000_IPCNFG
);
2434 eeer
= rd32(E1000_EEER
);
2436 /* enable or disable per user setting */
2437 if (!(hw
->dev_spec
._82575
.eee_disable
)) {
2438 u32 eee_su
= rd32(E1000_EEE_SU
);
2440 ipcnfg
|= (E1000_IPCNFG_EEE_1G_AN
| E1000_IPCNFG_EEE_100M_AN
);
2441 eeer
|= (E1000_EEER_TX_LPI_EN
| E1000_EEER_RX_LPI_EN
|
2444 /* This bit should not be set in normal operation. */
2445 if (eee_su
& E1000_EEE_SU_LPI_CLK_STP
)
2446 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2449 ipcnfg
&= ~(E1000_IPCNFG_EEE_1G_AN
|
2450 E1000_IPCNFG_EEE_100M_AN
);
2451 eeer
&= ~(E1000_EEER_TX_LPI_EN
|
2452 E1000_EEER_RX_LPI_EN
|
2455 wr32(E1000_IPCNFG
, ipcnfg
);
2456 wr32(E1000_EEER
, eeer
);
2465 * igb_set_eee_i354 - Enable/disable EEE support
2466 * @hw: pointer to the HW structure
2468 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2471 s32
igb_set_eee_i354(struct e1000_hw
*hw
)
2473 struct e1000_phy_info
*phy
= &hw
->phy
;
2477 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
2478 (phy
->id
!= M88E1545_E_PHY_ID
))
2481 if (!hw
->dev_spec
._82575
.eee_disable
) {
2482 /* Switch to PHY page 18. */
2483 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_PAGE_ADDR
, 18);
2487 ret_val
= phy
->ops
.read_reg(hw
, E1000_M88E1545_EEE_CTRL_1
,
2492 phy_data
|= E1000_M88E1545_EEE_CTRL_1_MS
;
2493 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_EEE_CTRL_1
,
2498 /* Return the PHY to page 0. */
2499 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_PAGE_ADDR
, 0);
2503 /* Turn on EEE advertisement. */
2504 ret_val
= igb_read_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2505 E1000_EEE_ADV_DEV_I354
,
2510 phy_data
|= E1000_EEE_ADV_100_SUPPORTED
|
2511 E1000_EEE_ADV_1000_SUPPORTED
;
2512 ret_val
= igb_write_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2513 E1000_EEE_ADV_DEV_I354
,
2516 /* Turn off EEE advertisement. */
2517 ret_val
= igb_read_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2518 E1000_EEE_ADV_DEV_I354
,
2523 phy_data
&= ~(E1000_EEE_ADV_100_SUPPORTED
|
2524 E1000_EEE_ADV_1000_SUPPORTED
);
2525 ret_val
= igb_write_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2526 E1000_EEE_ADV_DEV_I354
,
2535 * igb_get_eee_status_i354 - Get EEE status
2536 * @hw: pointer to the HW structure
2537 * @status: EEE status
2539 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2542 s32
igb_get_eee_status_i354(struct e1000_hw
*hw
, bool *status
)
2544 struct e1000_phy_info
*phy
= &hw
->phy
;
2548 /* Check if EEE is supported on this device. */
2549 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
2550 (phy
->id
!= M88E1545_E_PHY_ID
))
2553 ret_val
= igb_read_xmdio_reg(hw
, E1000_PCS_STATUS_ADDR_I354
,
2554 E1000_PCS_STATUS_DEV_I354
,
2559 *status
= phy_data
& (E1000_PCS_STATUS_TX_LPI_RCVD
|
2560 E1000_PCS_STATUS_RX_LPI_RCVD
) ? true : false;
2566 static const u8 e1000_emc_temp_data
[4] = {
2567 E1000_EMC_INTERNAL_DATA
,
2568 E1000_EMC_DIODE1_DATA
,
2569 E1000_EMC_DIODE2_DATA
,
2570 E1000_EMC_DIODE3_DATA
2572 static const u8 e1000_emc_therm_limit
[4] = {
2573 E1000_EMC_INTERNAL_THERM_LIMIT
,
2574 E1000_EMC_DIODE1_THERM_LIMIT
,
2575 E1000_EMC_DIODE2_THERM_LIMIT
,
2576 E1000_EMC_DIODE3_THERM_LIMIT
2580 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2581 * @hw: pointer to hardware structure
2583 * Updates the temperatures in mac.thermal_sensor_data
2585 s32
igb_get_thermal_sensor_data_generic(struct e1000_hw
*hw
)
2587 s32 status
= E1000_SUCCESS
;
2595 struct e1000_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
2597 if ((hw
->mac
.type
!= e1000_i350
) || (hw
->bus
.func
!= 0))
2598 return E1000_NOT_IMPLEMENTED
;
2600 data
->sensor
[0].temp
= (rd32(E1000_THMJT
) & 0xFF);
2602 /* Return the internal sensor only if ETS is unsupported */
2603 hw
->nvm
.ops
.read(hw
, NVM_ETS_CFG
, 1, &ets_offset
);
2604 if ((ets_offset
== 0x0000) || (ets_offset
== 0xFFFF))
2607 hw
->nvm
.ops
.read(hw
, ets_offset
, 1, &ets_cfg
);
2608 if (((ets_cfg
& NVM_ETS_TYPE_MASK
) >> NVM_ETS_TYPE_SHIFT
)
2609 != NVM_ETS_TYPE_EMC
)
2610 return E1000_NOT_IMPLEMENTED
;
2612 num_sensors
= (ets_cfg
& NVM_ETS_NUM_SENSORS_MASK
);
2613 if (num_sensors
> E1000_MAX_SENSORS
)
2614 num_sensors
= E1000_MAX_SENSORS
;
2616 for (i
= 1; i
< num_sensors
; i
++) {
2617 hw
->nvm
.ops
.read(hw
, (ets_offset
+ i
), 1, &ets_sensor
);
2618 sensor_index
= ((ets_sensor
& NVM_ETS_DATA_INDEX_MASK
) >>
2619 NVM_ETS_DATA_INDEX_SHIFT
);
2620 sensor_location
= ((ets_sensor
& NVM_ETS_DATA_LOC_MASK
) >>
2621 NVM_ETS_DATA_LOC_SHIFT
);
2623 if (sensor_location
!= 0)
2624 hw
->phy
.ops
.read_i2c_byte(hw
,
2625 e1000_emc_temp_data
[sensor_index
],
2626 E1000_I2C_THERMAL_SENSOR_ADDR
,
2627 &data
->sensor
[i
].temp
);
2633 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2634 * @hw: pointer to hardware structure
2636 * Sets the thermal sensor thresholds according to the NVM map
2637 * and save off the threshold and location values into mac.thermal_sensor_data
2639 s32
igb_init_thermal_sensor_thresh_generic(struct e1000_hw
*hw
)
2641 s32 status
= E1000_SUCCESS
;
2645 u8 low_thresh_delta
;
2651 struct e1000_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
2653 if ((hw
->mac
.type
!= e1000_i350
) || (hw
->bus
.func
!= 0))
2654 return E1000_NOT_IMPLEMENTED
;
2656 memset(data
, 0, sizeof(struct e1000_thermal_sensor_data
));
2658 data
->sensor
[0].location
= 0x1;
2659 data
->sensor
[0].caution_thresh
=
2660 (rd32(E1000_THHIGHTC
) & 0xFF);
2661 data
->sensor
[0].max_op_thresh
=
2662 (rd32(E1000_THLOWTC
) & 0xFF);
2664 /* Return the internal sensor only if ETS is unsupported */
2665 hw
->nvm
.ops
.read(hw
, NVM_ETS_CFG
, 1, &ets_offset
);
2666 if ((ets_offset
== 0x0000) || (ets_offset
== 0xFFFF))
2669 hw
->nvm
.ops
.read(hw
, ets_offset
, 1, &ets_cfg
);
2670 if (((ets_cfg
& NVM_ETS_TYPE_MASK
) >> NVM_ETS_TYPE_SHIFT
)
2671 != NVM_ETS_TYPE_EMC
)
2672 return E1000_NOT_IMPLEMENTED
;
2674 low_thresh_delta
= ((ets_cfg
& NVM_ETS_LTHRES_DELTA_MASK
) >>
2675 NVM_ETS_LTHRES_DELTA_SHIFT
);
2676 num_sensors
= (ets_cfg
& NVM_ETS_NUM_SENSORS_MASK
);
2678 for (i
= 1; i
<= num_sensors
; i
++) {
2679 hw
->nvm
.ops
.read(hw
, (ets_offset
+ i
), 1, &ets_sensor
);
2680 sensor_index
= ((ets_sensor
& NVM_ETS_DATA_INDEX_MASK
) >>
2681 NVM_ETS_DATA_INDEX_SHIFT
);
2682 sensor_location
= ((ets_sensor
& NVM_ETS_DATA_LOC_MASK
) >>
2683 NVM_ETS_DATA_LOC_SHIFT
);
2684 therm_limit
= ets_sensor
& NVM_ETS_DATA_HTHRESH_MASK
;
2686 hw
->phy
.ops
.write_i2c_byte(hw
,
2687 e1000_emc_therm_limit
[sensor_index
],
2688 E1000_I2C_THERMAL_SENSOR_ADDR
,
2691 if ((i
< E1000_MAX_SENSORS
) && (sensor_location
!= 0)) {
2692 data
->sensor
[i
].location
= sensor_location
;
2693 data
->sensor
[i
].caution_thresh
= therm_limit
;
2694 data
->sensor
[i
].max_op_thresh
= therm_limit
-
2701 static struct e1000_mac_operations e1000_mac_ops_82575
= {
2702 .init_hw
= igb_init_hw_82575
,
2703 .check_for_link
= igb_check_for_link_82575
,
2704 .rar_set
= igb_rar_set
,
2705 .read_mac_addr
= igb_read_mac_addr_82575
,
2706 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
2707 #ifdef CONFIG_IGB_HWMON
2708 .get_thermal_sensor_data
= igb_get_thermal_sensor_data_generic
,
2709 .init_thermal_sensor_thresh
= igb_init_thermal_sensor_thresh_generic
,
2713 static struct e1000_phy_operations e1000_phy_ops_82575
= {
2714 .acquire
= igb_acquire_phy_82575
,
2715 .get_cfg_done
= igb_get_cfg_done_82575
,
2716 .release
= igb_release_phy_82575
,
2717 .write_i2c_byte
= igb_write_i2c_byte
,
2718 .read_i2c_byte
= igb_read_i2c_byte
,
2721 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
2722 .acquire
= igb_acquire_nvm_82575
,
2723 .read
= igb_read_nvm_eerd
,
2724 .release
= igb_release_nvm_82575
,
2725 .write
= igb_write_nvm_spi
,
2728 const struct e1000_info e1000_82575_info
= {
2729 .get_invariants
= igb_get_invariants_82575
,
2730 .mac_ops
= &e1000_mac_ops_82575
,
2731 .phy_ops
= &e1000_phy_ops_82575
,
2732 .nvm_ops
= &e1000_nvm_ops_82575
,