1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
42 static s32
igb_get_invariants_82575(struct e1000_hw
*);
43 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
44 static void igb_release_phy_82575(struct e1000_hw
*);
45 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
46 static void igb_release_nvm_82575(struct e1000_hw
*);
47 static s32
igb_check_for_link_82575(struct e1000_hw
*);
48 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
49 static s32
igb_init_hw_82575(struct e1000_hw
*);
50 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
51 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
52 static s32
igb_read_phy_reg_82580(struct e1000_hw
*, u32
, u16
*);
53 static s32
igb_write_phy_reg_82580(struct e1000_hw
*, u32
, u16
);
54 static s32
igb_reset_hw_82575(struct e1000_hw
*);
55 static s32
igb_reset_hw_82580(struct e1000_hw
*);
56 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
57 static s32
igb_set_d0_lplu_state_82580(struct e1000_hw
*, bool);
58 static s32
igb_set_d3_lplu_state_82580(struct e1000_hw
*, bool);
59 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
60 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*);
61 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
63 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
64 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
66 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
67 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
68 static bool igb_sgmii_active_82575(struct e1000_hw
*);
69 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
70 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
71 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
);
72 static s32
igb_reset_mdicnfg_82580(struct e1000_hw
*hw
);
73 static s32
igb_validate_nvm_checksum_82580(struct e1000_hw
*hw
);
74 static s32
igb_update_nvm_checksum_82580(struct e1000_hw
*hw
);
75 static s32
igb_validate_nvm_checksum_i350(struct e1000_hw
*hw
);
76 static s32
igb_update_nvm_checksum_i350(struct e1000_hw
*hw
);
77 static const u16 e1000_82580_rxpbs_table
[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw
*hw
)
93 bool ext_mdio
= false;
95 switch (hw
->mac
.type
) {
98 reg
= rd32(E1000_MDIC
);
99 ext_mdio
= !!(reg
& E1000_MDIC_DEST
);
105 reg
= rd32(E1000_MDICNFG
);
106 ext_mdio
= !!(reg
& E1000_MDICNFG_EXT_MDIO
);
115 * igb_init_phy_params_82575 - Init PHY func ptrs.
116 * @hw: pointer to the HW structure
118 static s32
igb_init_phy_params_82575(struct e1000_hw
*hw
)
120 struct e1000_phy_info
*phy
= &hw
->phy
;
124 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
125 phy
->type
= e1000_phy_none
;
129 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
130 phy
->reset_delay_us
= 100;
132 ctrl_ext
= rd32(E1000_CTRL_EXT
);
134 if (igb_sgmii_active_82575(hw
)) {
135 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
136 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
138 phy
->ops
.reset
= igb_phy_hw_reset
;
139 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
142 wr32(E1000_CTRL_EXT
, ctrl_ext
);
143 igb_reset_mdicnfg_82580(hw
);
145 if (igb_sgmii_active_82575(hw
) && !igb_sgmii_uses_mdio_82575(hw
)) {
146 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
147 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
149 switch (hw
->mac
.type
) {
152 phy
->ops
.read_reg
= igb_read_phy_reg_82580
;
153 phy
->ops
.write_reg
= igb_write_phy_reg_82580
;
157 phy
->ops
.read_reg
= igb_read_phy_reg_gs40g
;
158 phy
->ops
.write_reg
= igb_write_phy_reg_gs40g
;
161 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
162 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
167 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
168 E1000_STATUS_FUNC_SHIFT
;
170 /* Set phy->phy_addr and phy->id. */
171 ret_val
= igb_get_phy_id_82575(hw
);
175 /* Verify phy id and set remaining function pointers */
177 case I347AT4_E_PHY_ID
:
178 case M88E1112_E_PHY_ID
:
179 case M88E1111_I_PHY_ID
:
180 phy
->type
= e1000_phy_m88
;
181 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
182 if (phy
->id
== I347AT4_E_PHY_ID
||
183 phy
->id
== M88E1112_E_PHY_ID
)
184 phy
->ops
.get_cable_length
=
185 igb_get_cable_length_m88_gen2
;
187 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
188 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
190 case IGP03E1000_E_PHY_ID
:
191 phy
->type
= e1000_phy_igp_3
;
192 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
193 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
194 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
195 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
196 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
198 case I82580_I_PHY_ID
:
200 phy
->type
= e1000_phy_82580
;
201 phy
->ops
.force_speed_duplex
=
202 igb_phy_force_speed_duplex_82580
;
203 phy
->ops
.get_cable_length
= igb_get_cable_length_82580
;
204 phy
->ops
.get_phy_info
= igb_get_phy_info_82580
;
205 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
206 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
209 phy
->type
= e1000_phy_i210
;
210 phy
->ops
.check_polarity
= igb_check_polarity_m88
;
211 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
212 phy
->ops
.get_cable_length
= igb_get_cable_length_m88_gen2
;
213 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
214 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
215 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
218 ret_val
= -E1000_ERR_PHY
;
227 * igb_init_nvm_params_82575 - Init NVM func ptrs.
228 * @hw: pointer to the HW structure
230 s32
igb_init_nvm_params_82575(struct e1000_hw
*hw
)
232 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
233 u32 eecd
= rd32(E1000_EECD
);
236 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
237 E1000_EECD_SIZE_EX_SHIFT
);
238 /* Added to a constant, "size" becomes the left-shift value
239 * for setting word_size.
241 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
243 /* Just in case size is out of range, cap it to the largest
244 * EEPROM size supported
249 nvm
->word_size
= 1 << size
;
250 if (hw
->mac
.type
< e1000_i210
) {
251 nvm
->opcode_bits
= 8;
254 switch (nvm
->override
) {
255 case e1000_nvm_override_spi_large
:
257 nvm
->address_bits
= 16;
259 case e1000_nvm_override_spi_small
:
261 nvm
->address_bits
= 8;
264 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
265 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
?
269 if (nvm
->word_size
== (1 << 15))
270 nvm
->page_size
= 128;
272 nvm
->type
= e1000_nvm_eeprom_spi
;
274 nvm
->type
= e1000_nvm_flash_hw
;
277 /* NVM Function Pointers */
278 switch (hw
->mac
.type
) {
280 nvm
->ops
.validate
= igb_validate_nvm_checksum_82580
;
281 nvm
->ops
.update
= igb_update_nvm_checksum_82580
;
282 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
283 nvm
->ops
.release
= igb_release_nvm_82575
;
284 if (nvm
->word_size
< (1 << 15))
285 nvm
->ops
.read
= igb_read_nvm_eerd
;
287 nvm
->ops
.read
= igb_read_nvm_spi
;
288 nvm
->ops
.write
= igb_write_nvm_spi
;
291 nvm
->ops
.validate
= igb_validate_nvm_checksum_i350
;
292 nvm
->ops
.update
= igb_update_nvm_checksum_i350
;
293 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
294 nvm
->ops
.release
= igb_release_nvm_82575
;
295 if (nvm
->word_size
< (1 << 15))
296 nvm
->ops
.read
= igb_read_nvm_eerd
;
298 nvm
->ops
.read
= igb_read_nvm_spi
;
299 nvm
->ops
.write
= igb_write_nvm_spi
;
302 nvm
->ops
.validate
= igb_validate_nvm_checksum_i210
;
303 nvm
->ops
.update
= igb_update_nvm_checksum_i210
;
304 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
305 nvm
->ops
.release
= igb_release_nvm_i210
;
306 nvm
->ops
.read
= igb_read_nvm_srrd_i210
;
307 nvm
->ops
.write
= igb_write_nvm_srwr_i210
;
308 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
311 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
312 nvm
->ops
.release
= igb_release_nvm_i210
;
313 nvm
->ops
.read
= igb_read_nvm_i211
;
314 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
315 nvm
->ops
.validate
= NULL
;
316 nvm
->ops
.update
= NULL
;
317 nvm
->ops
.write
= NULL
;
320 nvm
->ops
.validate
= igb_validate_nvm_checksum
;
321 nvm
->ops
.update
= igb_update_nvm_checksum
;
322 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
323 nvm
->ops
.release
= igb_release_nvm_82575
;
324 if (nvm
->word_size
< (1 << 15))
325 nvm
->ops
.read
= igb_read_nvm_eerd
;
327 nvm
->ops
.read
= igb_read_nvm_spi
;
328 nvm
->ops
.write
= igb_write_nvm_spi
;
335 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
337 struct e1000_phy_info
*phy
= &hw
->phy
;
338 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
339 struct e1000_mac_info
*mac
= &hw
->mac
;
340 struct e1000_dev_spec_82575
* dev_spec
= &hw
->dev_spec
._82575
;
346 switch (hw
->device_id
) {
347 case E1000_DEV_ID_82575EB_COPPER
:
348 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
349 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
350 mac
->type
= e1000_82575
;
352 case E1000_DEV_ID_82576
:
353 case E1000_DEV_ID_82576_NS
:
354 case E1000_DEV_ID_82576_NS_SERDES
:
355 case E1000_DEV_ID_82576_FIBER
:
356 case E1000_DEV_ID_82576_SERDES
:
357 case E1000_DEV_ID_82576_QUAD_COPPER
:
358 case E1000_DEV_ID_82576_QUAD_COPPER_ET2
:
359 case E1000_DEV_ID_82576_SERDES_QUAD
:
360 mac
->type
= e1000_82576
;
362 case E1000_DEV_ID_82580_COPPER
:
363 case E1000_DEV_ID_82580_FIBER
:
364 case E1000_DEV_ID_82580_QUAD_FIBER
:
365 case E1000_DEV_ID_82580_SERDES
:
366 case E1000_DEV_ID_82580_SGMII
:
367 case E1000_DEV_ID_82580_COPPER_DUAL
:
368 case E1000_DEV_ID_DH89XXCC_SGMII
:
369 case E1000_DEV_ID_DH89XXCC_SERDES
:
370 case E1000_DEV_ID_DH89XXCC_BACKPLANE
:
371 case E1000_DEV_ID_DH89XXCC_SFP
:
372 mac
->type
= e1000_82580
;
374 case E1000_DEV_ID_I350_COPPER
:
375 case E1000_DEV_ID_I350_FIBER
:
376 case E1000_DEV_ID_I350_SERDES
:
377 case E1000_DEV_ID_I350_SGMII
:
378 mac
->type
= e1000_i350
;
380 case E1000_DEV_ID_I210_COPPER
:
381 case E1000_DEV_ID_I210_COPPER_OEM1
:
382 case E1000_DEV_ID_I210_COPPER_IT
:
383 case E1000_DEV_ID_I210_FIBER
:
384 case E1000_DEV_ID_I210_SERDES
:
385 case E1000_DEV_ID_I210_SGMII
:
386 mac
->type
= e1000_i210
;
388 case E1000_DEV_ID_I211_COPPER
:
389 mac
->type
= e1000_i211
;
392 return -E1000_ERR_MAC_INIT
;
398 * The 82575 uses bits 22:23 for link mode. The mode can be changed
399 * based on the EEPROM. We cannot rely upon device ID. There
400 * is no distinguishable difference between fiber and internal
401 * SerDes mode on the 82575. There can be an external PHY attached
402 * on the SGMII interface. For this, we'll set sgmii_active to true.
404 phy
->media_type
= e1000_media_type_copper
;
405 dev_spec
->sgmii_active
= false;
407 ctrl_ext
= rd32(E1000_CTRL_EXT
);
408 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
409 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
410 dev_spec
->sgmii_active
= true;
412 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
413 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
:
414 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
420 /* Set mta register count */
421 mac
->mta_reg_count
= 128;
422 /* Set rar entry count */
425 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
428 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82580
;
431 mac
->rar_entry_count
= E1000_RAR_ENTRIES_I350
;
434 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
438 if (mac
->type
>= e1000_82580
)
439 mac
->ops
.reset_hw
= igb_reset_hw_82580
;
441 mac
->ops
.reset_hw
= igb_reset_hw_82575
;
443 if (mac
->type
>= e1000_i210
) {
444 mac
->ops
.acquire_swfw_sync
= igb_acquire_swfw_sync_i210
;
445 mac
->ops
.release_swfw_sync
= igb_release_swfw_sync_i210
;
447 mac
->ops
.acquire_swfw_sync
= igb_acquire_swfw_sync_82575
;
448 mac
->ops
.release_swfw_sync
= igb_release_swfw_sync_82575
;
451 /* Set if part includes ASF firmware */
452 mac
->asf_firmware_present
= true;
453 /* Set if manageability features are enabled. */
454 mac
->arc_subsystem_valid
=
455 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
457 /* enable EEE on i350 parts and later parts */
458 if (mac
->type
>= e1000_i350
)
459 dev_spec
->eee_disable
= false;
461 dev_spec
->eee_disable
= true;
462 /* physical interface link setup */
463 mac
->ops
.setup_physical_interface
=
464 (hw
->phy
.media_type
== e1000_media_type_copper
)
465 ? igb_setup_copper_link_82575
466 : igb_setup_serdes_link_82575
;
468 /* NVM initialization */
469 eecd
= rd32(E1000_EECD
);
470 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
471 E1000_EECD_SIZE_EX_SHIFT
);
474 * Added to a constant, "size" becomes the left-shift value
475 * for setting word_size.
477 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
480 * Check for invalid size
482 if ((hw
->mac
.type
== e1000_82576
) && (size
> 15)) {
483 pr_notice("The NVM size is not valid, defaulting to 32K\n");
487 nvm
->word_size
= 1 << size
;
488 if (hw
->mac
.type
< e1000_i210
) {
489 nvm
->opcode_bits
= 8;
491 switch (nvm
->override
) {
492 case e1000_nvm_override_spi_large
:
494 nvm
->address_bits
= 16;
496 case e1000_nvm_override_spi_small
:
498 nvm
->address_bits
= 8;
501 nvm
->page_size
= eecd
502 & E1000_EECD_ADDR_BITS
? 32 : 8;
503 nvm
->address_bits
= eecd
504 & E1000_EECD_ADDR_BITS
? 16 : 8;
507 if (nvm
->word_size
== (1 << 15))
508 nvm
->page_size
= 128;
510 nvm
->type
= e1000_nvm_eeprom_spi
;
512 nvm
->type
= e1000_nvm_flash_hw
;
514 /* NVM Function Pointers */
515 switch (hw
->mac
.type
) {
517 nvm
->ops
.validate
= igb_validate_nvm_checksum_82580
;
518 nvm
->ops
.update
= igb_update_nvm_checksum_82580
;
519 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
520 nvm
->ops
.release
= igb_release_nvm_82575
;
521 if (nvm
->word_size
< (1 << 15))
522 nvm
->ops
.read
= igb_read_nvm_eerd
;
524 nvm
->ops
.read
= igb_read_nvm_spi
;
525 nvm
->ops
.write
= igb_write_nvm_spi
;
528 nvm
->ops
.validate
= igb_validate_nvm_checksum_i350
;
529 nvm
->ops
.update
= igb_update_nvm_checksum_i350
;
530 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
531 nvm
->ops
.release
= igb_release_nvm_82575
;
532 if (nvm
->word_size
< (1 << 15))
533 nvm
->ops
.read
= igb_read_nvm_eerd
;
535 nvm
->ops
.read
= igb_read_nvm_spi
;
536 nvm
->ops
.write
= igb_write_nvm_spi
;
539 nvm
->ops
.validate
= igb_validate_nvm_checksum_i210
;
540 nvm
->ops
.update
= igb_update_nvm_checksum_i210
;
541 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
542 nvm
->ops
.release
= igb_release_nvm_i210
;
543 nvm
->ops
.read
= igb_read_nvm_srrd_i210
;
544 nvm
->ops
.write
= igb_write_nvm_srwr_i210
;
545 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
548 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
549 nvm
->ops
.release
= igb_release_nvm_i210
;
550 nvm
->ops
.read
= igb_read_nvm_i211
;
551 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
552 nvm
->ops
.validate
= NULL
;
553 nvm
->ops
.update
= NULL
;
554 nvm
->ops
.write
= NULL
;
557 nvm
->ops
.validate
= igb_validate_nvm_checksum
;
558 nvm
->ops
.update
= igb_update_nvm_checksum
;
559 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
560 nvm
->ops
.release
= igb_release_nvm_82575
;
561 if (nvm
->word_size
< (1 << 15))
562 nvm
->ops
.read
= igb_read_nvm_eerd
;
564 nvm
->ops
.read
= igb_read_nvm_spi
;
565 nvm
->ops
.write
= igb_write_nvm_spi
;
569 /* if part supports SR-IOV then initialize mailbox parameters */
573 igb_init_mbx_params_pf(hw
);
579 /* setup PHY parameters */
580 if (phy
->media_type
!= e1000_media_type_copper
) {
581 phy
->type
= e1000_phy_none
;
585 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
586 phy
->reset_delay_us
= 100;
588 ctrl_ext
= rd32(E1000_CTRL_EXT
);
590 /* PHY function pointers */
591 if (igb_sgmii_active_82575(hw
)) {
592 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
593 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
595 phy
->ops
.reset
= igb_phy_hw_reset
;
596 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
599 wr32(E1000_CTRL_EXT
, ctrl_ext
);
600 igb_reset_mdicnfg_82580(hw
);
602 if (igb_sgmii_active_82575(hw
) && !igb_sgmii_uses_mdio_82575(hw
)) {
603 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
604 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
605 } else if ((hw
->mac
.type
== e1000_82580
)
606 || (hw
->mac
.type
== e1000_i350
)) {
607 phy
->ops
.read_reg
= igb_read_phy_reg_82580
;
608 phy
->ops
.write_reg
= igb_write_phy_reg_82580
;
609 } else if (hw
->phy
.type
>= e1000_phy_i210
) {
610 phy
->ops
.read_reg
= igb_read_phy_reg_gs40g
;
611 phy
->ops
.write_reg
= igb_write_phy_reg_gs40g
;
613 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
614 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
618 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
619 E1000_STATUS_FUNC_SHIFT
;
621 /* Set phy->phy_addr and phy->id. */
622 ret_val
= igb_get_phy_id_82575(hw
);
626 /* Verify phy id and set remaining function pointers */
628 case I347AT4_E_PHY_ID
:
629 case M88E1112_E_PHY_ID
:
630 case M88E1111_I_PHY_ID
:
631 phy
->type
= e1000_phy_m88
;
632 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
634 if (phy
->id
== I347AT4_E_PHY_ID
||
635 phy
->id
== M88E1112_E_PHY_ID
)
636 phy
->ops
.get_cable_length
= igb_get_cable_length_m88_gen2
;
638 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
640 if (phy
->id
== I210_I_PHY_ID
) {
641 phy
->ops
.get_cable_length
=
642 igb_get_cable_length_m88_gen2
;
643 phy
->ops
.set_d0_lplu_state
=
644 igb_set_d0_lplu_state_82580
;
645 phy
->ops
.set_d3_lplu_state
=
646 igb_set_d3_lplu_state_82580
;
648 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
650 case IGP03E1000_E_PHY_ID
:
651 phy
->type
= e1000_phy_igp_3
;
652 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
653 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
654 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
655 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
656 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
658 case I82580_I_PHY_ID
:
660 phy
->type
= e1000_phy_82580
;
661 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_82580
;
662 phy
->ops
.get_cable_length
= igb_get_cable_length_82580
;
663 phy
->ops
.get_phy_info
= igb_get_phy_info_82580
;
664 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
665 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
668 phy
->type
= e1000_phy_i210
;
669 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
670 phy
->ops
.check_polarity
= igb_check_polarity_m88
;
671 phy
->ops
.get_cable_length
= igb_get_cable_length_m88_gen2
;
672 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
673 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
674 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
677 return -E1000_ERR_PHY
;
684 * igb_acquire_phy_82575 - Acquire rights to access PHY
685 * @hw: pointer to the HW structure
687 * Acquire access rights to the correct PHY. This is a
688 * function pointer entry point called by the api module.
690 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
692 u16 mask
= E1000_SWFW_PHY0_SM
;
694 if (hw
->bus
.func
== E1000_FUNC_1
)
695 mask
= E1000_SWFW_PHY1_SM
;
696 else if (hw
->bus
.func
== E1000_FUNC_2
)
697 mask
= E1000_SWFW_PHY2_SM
;
698 else if (hw
->bus
.func
== E1000_FUNC_3
)
699 mask
= E1000_SWFW_PHY3_SM
;
701 return hw
->mac
.ops
.acquire_swfw_sync(hw
, mask
);
705 * igb_release_phy_82575 - Release rights to access PHY
706 * @hw: pointer to the HW structure
708 * A wrapper to release access rights to the correct PHY. This is a
709 * function pointer entry point called by the api module.
711 static void igb_release_phy_82575(struct e1000_hw
*hw
)
713 u16 mask
= E1000_SWFW_PHY0_SM
;
715 if (hw
->bus
.func
== E1000_FUNC_1
)
716 mask
= E1000_SWFW_PHY1_SM
;
717 else if (hw
->bus
.func
== E1000_FUNC_2
)
718 mask
= E1000_SWFW_PHY2_SM
;
719 else if (hw
->bus
.func
== E1000_FUNC_3
)
720 mask
= E1000_SWFW_PHY3_SM
;
722 hw
->mac
.ops
.release_swfw_sync(hw
, mask
);
726 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
727 * @hw: pointer to the HW structure
728 * @offset: register offset to be read
729 * @data: pointer to the read data
731 * Reads the PHY register at offset using the serial gigabit media independent
732 * interface and stores the retrieved information in data.
734 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
737 s32 ret_val
= -E1000_ERR_PARAM
;
739 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
740 hw_dbg("PHY Address %u is out of range\n", offset
);
744 ret_val
= hw
->phy
.ops
.acquire(hw
);
748 ret_val
= igb_read_phy_reg_i2c(hw
, offset
, data
);
750 hw
->phy
.ops
.release(hw
);
757 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
758 * @hw: pointer to the HW structure
759 * @offset: register offset to write to
760 * @data: data to write at register offset
762 * Writes the data to PHY register at the offset using the serial gigabit
763 * media independent interface.
765 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
768 s32 ret_val
= -E1000_ERR_PARAM
;
771 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
772 hw_dbg("PHY Address %d is out of range\n", offset
);
776 ret_val
= hw
->phy
.ops
.acquire(hw
);
780 ret_val
= igb_write_phy_reg_i2c(hw
, offset
, data
);
782 hw
->phy
.ops
.release(hw
);
789 * igb_get_phy_id_82575 - Retrieve PHY addr and id
790 * @hw: pointer to the HW structure
792 * Retrieves the PHY address and ID for both PHY's which do and do not use
795 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
797 struct e1000_phy_info
*phy
= &hw
->phy
;
804 * For SGMII PHYs, we try the list of possible addresses until
805 * we find one that works. For non-SGMII PHYs
806 * (e.g. integrated copper PHYs), an address of 1 should
807 * work. The result of this function should mean phy->phy_addr
808 * and phy->id are set correctly.
810 if (!(igb_sgmii_active_82575(hw
))) {
812 ret_val
= igb_get_phy_id(hw
);
816 if (igb_sgmii_uses_mdio_82575(hw
)) {
817 switch (hw
->mac
.type
) {
820 mdic
= rd32(E1000_MDIC
);
821 mdic
&= E1000_MDIC_PHY_MASK
;
822 phy
->addr
= mdic
>> E1000_MDIC_PHY_SHIFT
;
828 mdic
= rd32(E1000_MDICNFG
);
829 mdic
&= E1000_MDICNFG_PHY_MASK
;
830 phy
->addr
= mdic
>> E1000_MDICNFG_PHY_SHIFT
;
833 ret_val
= -E1000_ERR_PHY
;
837 ret_val
= igb_get_phy_id(hw
);
841 /* Power on sgmii phy if it is disabled */
842 ctrl_ext
= rd32(E1000_CTRL_EXT
);
843 wr32(E1000_CTRL_EXT
, ctrl_ext
& ~E1000_CTRL_EXT_SDP3_DATA
);
848 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
849 * Therefore, we need to test 1-7
851 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
852 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
854 hw_dbg("Vendor ID 0x%08X read at address %u\n",
857 * At the time of this writing, The M88 part is
858 * the only supported SGMII PHY product.
860 if (phy_id
== M88_VENDOR
)
863 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
867 /* A valid PHY type couldn't be found. */
868 if (phy
->addr
== 8) {
870 ret_val
= -E1000_ERR_PHY
;
873 ret_val
= igb_get_phy_id(hw
);
876 /* restore previous sfp cage power state */
877 wr32(E1000_CTRL_EXT
, ctrl_ext
);
884 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
885 * @hw: pointer to the HW structure
887 * Resets the PHY using the serial gigabit media independent interface.
889 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
894 * This isn't a true "hard" reset, but is the only reset
895 * available to us at this time.
898 hw_dbg("Soft resetting SGMII attached PHY...\n");
901 * SFP documentation requires the following to configure the SPF module
902 * to work on SGMII. No further documentation is given.
904 ret_val
= hw
->phy
.ops
.write_reg(hw
, 0x1B, 0x8084);
908 ret_val
= igb_phy_sw_reset(hw
);
915 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
916 * @hw: pointer to the HW structure
917 * @active: true to enable LPLU, false to disable
919 * Sets the LPLU D0 state according to the active flag. When
920 * activating LPLU this function also disables smart speed
921 * and vice versa. LPLU will not be activated unless the
922 * device autonegotiation advertisement meets standards of
923 * either 10 or 10/100 or 10/100/1000 at all duplexes.
924 * This is a function pointer entry point only called by
925 * PHY setup routines.
927 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
929 struct e1000_phy_info
*phy
= &hw
->phy
;
933 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
938 data
|= IGP02E1000_PM_D0_LPLU
;
939 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
944 /* When LPLU is enabled, we should disable SmartSpeed */
945 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
947 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
948 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
953 data
&= ~IGP02E1000_PM_D0_LPLU
;
954 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
957 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
958 * during Dx states where the power conservation is most
959 * important. During driver activity we should enable
960 * SmartSpeed, so performance is maintained.
962 if (phy
->smart_speed
== e1000_smart_speed_on
) {
963 ret_val
= phy
->ops
.read_reg(hw
,
964 IGP01E1000_PHY_PORT_CONFIG
, &data
);
968 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
969 ret_val
= phy
->ops
.write_reg(hw
,
970 IGP01E1000_PHY_PORT_CONFIG
, data
);
973 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
974 ret_val
= phy
->ops
.read_reg(hw
,
975 IGP01E1000_PHY_PORT_CONFIG
, &data
);
979 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
980 ret_val
= phy
->ops
.write_reg(hw
,
981 IGP01E1000_PHY_PORT_CONFIG
, data
);
992 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
993 * @hw: pointer to the HW structure
994 * @active: true to enable LPLU, false to disable
996 * Sets the LPLU D0 state according to the active flag. When
997 * activating LPLU this function also disables smart speed
998 * and vice versa. LPLU will not be activated unless the
999 * device autonegotiation advertisement meets standards of
1000 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1001 * This is a function pointer entry point only called by
1002 * PHY setup routines.
1004 static s32
igb_set_d0_lplu_state_82580(struct e1000_hw
*hw
, bool active
)
1006 struct e1000_phy_info
*phy
= &hw
->phy
;
1010 data
= rd32(E1000_82580_PHY_POWER_MGMT
);
1013 data
|= E1000_82580_PM_D0_LPLU
;
1015 /* When LPLU is enabled, we should disable SmartSpeed */
1016 data
&= ~E1000_82580_PM_SPD
;
1018 data
&= ~E1000_82580_PM_D0_LPLU
;
1021 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1022 * during Dx states where the power conservation is most
1023 * important. During driver activity we should enable
1024 * SmartSpeed, so performance is maintained.
1026 if (phy
->smart_speed
== e1000_smart_speed_on
)
1027 data
|= E1000_82580_PM_SPD
;
1028 else if (phy
->smart_speed
== e1000_smart_speed_off
)
1029 data
&= ~E1000_82580_PM_SPD
; }
1031 wr32(E1000_82580_PHY_POWER_MGMT
, data
);
1036 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1037 * @hw: pointer to the HW structure
1038 * @active: boolean used to enable/disable lplu
1040 * Success returns 0, Failure returns 1
1042 * The low power link up (lplu) state is set to the power management level D3
1043 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1044 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1045 * is used during Dx states where the power conservation is most important.
1046 * During driver activity, SmartSpeed should be enabled so performance is
1049 s32
igb_set_d3_lplu_state_82580(struct e1000_hw
*hw
, bool active
)
1051 struct e1000_phy_info
*phy
= &hw
->phy
;
1055 data
= rd32(E1000_82580_PHY_POWER_MGMT
);
1058 data
&= ~E1000_82580_PM_D3_LPLU
;
1060 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1061 * during Dx states where the power conservation is most
1062 * important. During driver activity we should enable
1063 * SmartSpeed, so performance is maintained.
1065 if (phy
->smart_speed
== e1000_smart_speed_on
)
1066 data
|= E1000_82580_PM_SPD
;
1067 else if (phy
->smart_speed
== e1000_smart_speed_off
)
1068 data
&= ~E1000_82580_PM_SPD
;
1069 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1070 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1071 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1072 data
|= E1000_82580_PM_D3_LPLU
;
1073 /* When LPLU is enabled, we should disable SmartSpeed */
1074 data
&= ~E1000_82580_PM_SPD
;
1077 wr32(E1000_82580_PHY_POWER_MGMT
, data
);
1082 * igb_acquire_nvm_82575 - Request for access to EEPROM
1083 * @hw: pointer to the HW structure
1085 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1086 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1087 * Return successful if access grant bit set, else clear the request for
1088 * EEPROM access and return -E1000_ERR_NVM (-1).
1090 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
1094 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1098 ret_val
= igb_acquire_nvm(hw
);
1101 hw
->mac
.ops
.release_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1108 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1109 * @hw: pointer to the HW structure
1111 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1112 * then release the semaphores acquired.
1114 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
1116 igb_release_nvm(hw
);
1117 hw
->mac
.ops
.release_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
1121 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1122 * @hw: pointer to the HW structure
1123 * @mask: specifies which semaphore to acquire
1125 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1126 * will also specify which port we're acquiring the lock for.
1128 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
1132 u32 fwmask
= mask
<< 16;
1134 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
1136 while (i
< timeout
) {
1137 if (igb_get_hw_semaphore(hw
)) {
1138 ret_val
= -E1000_ERR_SWFW_SYNC
;
1142 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
1143 if (!(swfw_sync
& (fwmask
| swmask
)))
1147 * Firmware currently using resource (fwmask)
1148 * or other software thread using resource (swmask)
1150 igb_put_hw_semaphore(hw
);
1156 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1157 ret_val
= -E1000_ERR_SWFW_SYNC
;
1161 swfw_sync
|= swmask
;
1162 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
1164 igb_put_hw_semaphore(hw
);
1171 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1172 * @hw: pointer to the HW structure
1173 * @mask: specifies which semaphore to acquire
1175 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1176 * will also specify which port we're releasing the lock for.
1178 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
1182 while (igb_get_hw_semaphore(hw
) != 0);
1185 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
1187 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
1189 igb_put_hw_semaphore(hw
);
1193 * igb_get_cfg_done_82575 - Read config done bit
1194 * @hw: pointer to the HW structure
1196 * Read the management control register for the config done bit for
1197 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1198 * to read the config done bit, so an error is *ONLY* logged and returns
1199 * 0. If we were to return with error, EEPROM-less silicon
1200 * would not be able to be reset or change link.
1202 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
1204 s32 timeout
= PHY_CFG_TIMEOUT
;
1206 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
1208 if (hw
->bus
.func
== 1)
1209 mask
= E1000_NVM_CFG_DONE_PORT_1
;
1210 else if (hw
->bus
.func
== E1000_FUNC_2
)
1211 mask
= E1000_NVM_CFG_DONE_PORT_2
;
1212 else if (hw
->bus
.func
== E1000_FUNC_3
)
1213 mask
= E1000_NVM_CFG_DONE_PORT_3
;
1216 if (rd32(E1000_EEMNGCTL
) & mask
)
1222 hw_dbg("MNG configuration cycle has not completed.\n");
1224 /* If EEPROM is not marked present, init the PHY manually */
1225 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
1226 (hw
->phy
.type
== e1000_phy_igp_3
))
1227 igb_phy_init_script_igp3(hw
);
1233 * igb_check_for_link_82575 - Check for link
1234 * @hw: pointer to the HW structure
1236 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1237 * use the generic interface for determining link.
1239 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
1244 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
1245 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
1248 * Use this flag to determine if link needs to be checked or
1249 * not. If we have link clear the flag so that we do not
1250 * continue to check for link.
1252 hw
->mac
.get_link_status
= !hw
->mac
.serdes_has_link
;
1254 /* Configure Flow Control now that Auto-Neg has completed.
1255 * First, we need to restore the desired flow control
1256 * settings because we may have had to re-autoneg with a
1257 * different link partner.
1259 ret_val
= igb_config_fc_after_link_up(hw
);
1261 hw_dbg("Error configuring flow control\n");
1263 ret_val
= igb_check_for_copper_link(hw
);
1270 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1271 * @hw: pointer to the HW structure
1273 void igb_power_up_serdes_link_82575(struct e1000_hw
*hw
)
1278 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1279 !igb_sgmii_active_82575(hw
))
1282 /* Enable PCS to turn on link */
1283 reg
= rd32(E1000_PCS_CFG0
);
1284 reg
|= E1000_PCS_CFG_PCS_EN
;
1285 wr32(E1000_PCS_CFG0
, reg
);
1287 /* Power up the laser */
1288 reg
= rd32(E1000_CTRL_EXT
);
1289 reg
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1290 wr32(E1000_CTRL_EXT
, reg
);
1292 /* flush the write to verify completion */
1298 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1299 * @hw: pointer to the HW structure
1300 * @speed: stores the current speed
1301 * @duplex: stores the current duplex
1303 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1304 * duplex, then store the values in the pointers provided.
1306 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
1309 struct e1000_mac_info
*mac
= &hw
->mac
;
1312 /* Set up defaults for the return values of this function */
1313 mac
->serdes_has_link
= false;
1318 * Read the PCS Status register for link state. For non-copper mode,
1319 * the status register is not accurate. The PCS status register is
1322 pcs
= rd32(E1000_PCS_LSTAT
);
1325 * The link up bit determines when link is up on autoneg. The sync ok
1326 * gets set once both sides sync up and agree upon link. Stable link
1327 * can be determined by checking for both link up and link sync ok
1329 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
1330 mac
->serdes_has_link
= true;
1332 /* Detect and store PCS speed */
1333 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
1334 *speed
= SPEED_1000
;
1335 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
1341 /* Detect and store PCS duplex */
1342 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
1343 *duplex
= FULL_DUPLEX
;
1345 *duplex
= HALF_DUPLEX
;
1353 * igb_shutdown_serdes_link_82575 - Remove link during power down
1354 * @hw: pointer to the HW structure
1356 * In the case of fiber serdes, shut down optics and PCS on driver unload
1357 * when management pass thru is not enabled.
1359 void igb_shutdown_serdes_link_82575(struct e1000_hw
*hw
)
1363 if (hw
->phy
.media_type
!= e1000_media_type_internal_serdes
&&
1364 igb_sgmii_active_82575(hw
))
1367 if (!igb_enable_mng_pass_thru(hw
)) {
1368 /* Disable PCS to turn off link */
1369 reg
= rd32(E1000_PCS_CFG0
);
1370 reg
&= ~E1000_PCS_CFG_PCS_EN
;
1371 wr32(E1000_PCS_CFG0
, reg
);
1373 /* shutdown the laser */
1374 reg
= rd32(E1000_CTRL_EXT
);
1375 reg
|= E1000_CTRL_EXT_SDP3_DATA
;
1376 wr32(E1000_CTRL_EXT
, reg
);
1378 /* flush the write to verify completion */
1385 * igb_reset_hw_82575 - Reset hardware
1386 * @hw: pointer to the HW structure
1388 * This resets the hardware into a known state. This is a
1389 * function pointer entry point called by the api module.
1391 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
1397 * Prevent the PCI-E bus from sticking if there is no TLP connection
1398 * on the last TLP read/write transaction when MAC is reset.
1400 ret_val
= igb_disable_pcie_master(hw
);
1402 hw_dbg("PCI-E Master disable polling has failed.\n");
1404 /* set the completion timeout for interface */
1405 ret_val
= igb_set_pcie_completion_timeout(hw
);
1407 hw_dbg("PCI-E Set completion timeout has failed.\n");
1410 hw_dbg("Masking off all interrupts\n");
1411 wr32(E1000_IMC
, 0xffffffff);
1413 wr32(E1000_RCTL
, 0);
1414 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
1419 ctrl
= rd32(E1000_CTRL
);
1421 hw_dbg("Issuing a global reset to MAC\n");
1422 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
1424 ret_val
= igb_get_auto_rd_done(hw
);
1427 * When auto config read does not complete, do not
1428 * return with an error. This can happen in situations
1429 * where there is no eeprom and prevents getting link.
1431 hw_dbg("Auto Read Done did not complete\n");
1434 /* If EEPROM is not present, run manual init scripts */
1435 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
1436 igb_reset_init_script_82575(hw
);
1438 /* Clear any pending interrupt events. */
1439 wr32(E1000_IMC
, 0xffffffff);
1440 icr
= rd32(E1000_ICR
);
1442 /* Install any alternate MAC address into RAR0 */
1443 ret_val
= igb_check_alt_mac_addr(hw
);
1449 * igb_init_hw_82575 - Initialize hardware
1450 * @hw: pointer to the HW structure
1452 * This inits the hardware readying it for operation.
1454 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
1456 struct e1000_mac_info
*mac
= &hw
->mac
;
1458 u16 i
, rar_count
= mac
->rar_entry_count
;
1460 /* Initialize identification LED */
1461 ret_val
= igb_id_led_init(hw
);
1463 hw_dbg("Error initializing identification LED\n");
1464 /* This is not fatal and we should not stop init due to this */
1467 /* Disabling VLAN filtering */
1468 hw_dbg("Initializing the IEEE VLAN\n");
1469 if (hw
->mac
.type
== e1000_i350
)
1470 igb_clear_vfta_i350(hw
);
1474 /* Setup the receive address */
1475 igb_init_rx_addrs(hw
, rar_count
);
1477 /* Zero out the Multicast HASH table */
1478 hw_dbg("Zeroing the MTA\n");
1479 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
1480 array_wr32(E1000_MTA
, i
, 0);
1482 /* Zero out the Unicast HASH table */
1483 hw_dbg("Zeroing the UTA\n");
1484 for (i
= 0; i
< mac
->uta_reg_count
; i
++)
1485 array_wr32(E1000_UTA
, i
, 0);
1487 /* Setup link and flow control */
1488 ret_val
= igb_setup_link(hw
);
1491 * Clear all of the statistics registers (clear on read). It is
1492 * important that we do this after we have tried to establish link
1493 * because the symbol error count will increment wildly if there
1496 igb_clear_hw_cntrs_82575(hw
);
1501 * igb_setup_copper_link_82575 - Configure copper link settings
1502 * @hw: pointer to the HW structure
1504 * Configures the link for auto-neg or forced speed and duplex. Then we check
1505 * for link, once link is established calls to configure collision distance
1506 * and flow control are called.
1508 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
1514 ctrl
= rd32(E1000_CTRL
);
1515 ctrl
|= E1000_CTRL_SLU
;
1516 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1517 wr32(E1000_CTRL
, ctrl
);
1519 /* Clear Go Link Disconnect bit */
1520 if (hw
->mac
.type
>= e1000_82580
) {
1521 phpm_reg
= rd32(E1000_82580_PHY_POWER_MGMT
);
1522 phpm_reg
&= ~E1000_82580_PM_GO_LINKD
;
1523 wr32(E1000_82580_PHY_POWER_MGMT
, phpm_reg
);
1526 ret_val
= igb_setup_serdes_link_82575(hw
);
1530 if (igb_sgmii_active_82575(hw
) && !hw
->phy
.reset_disable
) {
1531 /* allow time for SFP cage time to power up phy */
1534 ret_val
= hw
->phy
.ops
.reset(hw
);
1536 hw_dbg("Error resetting the PHY.\n");
1540 switch (hw
->phy
.type
) {
1541 case e1000_phy_i210
:
1543 if (hw
->phy
.id
== I347AT4_E_PHY_ID
||
1544 hw
->phy
.id
== M88E1112_E_PHY_ID
)
1545 ret_val
= igb_copper_link_setup_m88_gen2(hw
);
1547 ret_val
= igb_copper_link_setup_m88(hw
);
1549 case e1000_phy_igp_3
:
1550 ret_val
= igb_copper_link_setup_igp(hw
);
1552 case e1000_phy_82580
:
1553 ret_val
= igb_copper_link_setup_82580(hw
);
1556 ret_val
= -E1000_ERR_PHY
;
1563 ret_val
= igb_setup_copper_link(hw
);
1569 * igb_setup_serdes_link_82575 - Setup link for serdes
1570 * @hw: pointer to the HW structure
1572 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1573 * used on copper connections where the serialized gigabit media independent
1574 * interface (sgmii), or serdes fiber is being used. Configures the link
1575 * for auto-negotiation or forces speed/duplex.
1577 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*hw
)
1579 u32 ctrl_ext
, ctrl_reg
, reg
, anadv_reg
;
1581 s32 ret_val
= E1000_SUCCESS
;
1584 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1585 !igb_sgmii_active_82575(hw
))
1590 * On the 82575, SerDes loopback mode persists until it is
1591 * explicitly turned off or a power cycle is performed. A read to
1592 * the register does not indicate its status. Therefore, we ensure
1593 * loopback mode is disabled during initialization.
1595 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1597 /* power on the sfp cage if present */
1598 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1599 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1600 wr32(E1000_CTRL_EXT
, ctrl_ext
);
1602 ctrl_reg
= rd32(E1000_CTRL
);
1603 ctrl_reg
|= E1000_CTRL_SLU
;
1605 if (hw
->mac
.type
== e1000_82575
|| hw
->mac
.type
== e1000_82576
) {
1606 /* set both sw defined pins */
1607 ctrl_reg
|= E1000_CTRL_SWDPIN0
| E1000_CTRL_SWDPIN1
;
1609 /* Set switch control to serdes energy detect */
1610 reg
= rd32(E1000_CONNSW
);
1611 reg
|= E1000_CONNSW_ENRGSRC
;
1612 wr32(E1000_CONNSW
, reg
);
1615 reg
= rd32(E1000_PCS_LCTL
);
1617 /* default pcs_autoneg to the same setting as mac autoneg */
1618 pcs_autoneg
= hw
->mac
.autoneg
;
1620 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
1621 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
1622 /* sgmii mode lets the phy handle forcing speed/duplex */
1624 /* autoneg time out should be disabled for SGMII mode */
1625 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1627 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
1628 /* disable PCS autoneg and support parallel detect only */
1629 pcs_autoneg
= false;
1631 if (hw
->mac
.type
== e1000_82575
||
1632 hw
->mac
.type
== e1000_82576
) {
1633 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPAT
, 1, &data
);
1635 printk(KERN_DEBUG
"NVM Read Error\n\n");
1639 if (data
& E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT
)
1640 pcs_autoneg
= false;
1644 * non-SGMII modes only supports a speed of 1000/Full for the
1645 * link so it is best to just force the MAC and let the pcs
1646 * link either autoneg or be forced to 1000/Full
1648 ctrl_reg
|= E1000_CTRL_SPD_1000
| E1000_CTRL_FRCSPD
|
1649 E1000_CTRL_FD
| E1000_CTRL_FRCDPX
;
1651 /* set speed of 1000/Full if speed/duplex is forced */
1652 reg
|= E1000_PCS_LCTL_FSV_1000
| E1000_PCS_LCTL_FDV_FULL
;
1656 wr32(E1000_CTRL
, ctrl_reg
);
1659 * New SerDes mode allows for forcing speed or autonegotiating speed
1660 * at 1gb. Autoneg should be default set by most drivers. This is the
1661 * mode that will be compatible with older link partners and switches.
1662 * However, both are supported by the hardware and some drivers/tools.
1664 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1665 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1668 /* Set PCS register for autoneg */
1669 reg
|= E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1670 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1672 /* Disable force flow control for autoneg */
1673 reg
&= ~E1000_PCS_LCTL_FORCE_FCTRL
;
1675 /* Configure flow control advertisement for autoneg */
1676 anadv_reg
= rd32(E1000_PCS_ANADV
);
1677 anadv_reg
&= ~(E1000_TXCW_ASM_DIR
| E1000_TXCW_PAUSE
);
1678 switch (hw
->fc
.requested_mode
) {
1680 case e1000_fc_rx_pause
:
1681 anadv_reg
|= E1000_TXCW_ASM_DIR
;
1682 anadv_reg
|= E1000_TXCW_PAUSE
;
1684 case e1000_fc_tx_pause
:
1685 anadv_reg
|= E1000_TXCW_ASM_DIR
;
1690 wr32(E1000_PCS_ANADV
, anadv_reg
);
1692 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg
);
1694 /* Set PCS register for forced link */
1695 reg
|= E1000_PCS_LCTL_FSD
; /* Force Speed */
1697 /* Force flow control for forced link */
1698 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1700 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg
);
1703 wr32(E1000_PCS_LCTL
, reg
);
1705 if (!pcs_autoneg
&& !igb_sgmii_active_82575(hw
))
1706 igb_force_mac_fc(hw
);
1712 * igb_sgmii_active_82575 - Return sgmii state
1713 * @hw: pointer to the HW structure
1715 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1716 * which can be enabled for use in the embedded applications. Simply
1717 * return the current state of the sgmii interface.
1719 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1721 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
1722 return dev_spec
->sgmii_active
;
1726 * igb_reset_init_script_82575 - Inits HW defaults after reset
1727 * @hw: pointer to the HW structure
1729 * Inits recommended HW defaults after a reset when there is no EEPROM
1730 * detected. This is only for the 82575.
1732 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1734 if (hw
->mac
.type
== e1000_82575
) {
1735 hw_dbg("Running reset init script for 82575\n");
1736 /* SerDes configuration via SERDESCTRL */
1737 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1738 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1739 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1740 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1742 /* CCM configuration via CCMCTL register */
1743 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1744 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1746 /* PCIe lanes configuration */
1747 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1748 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1749 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1750 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1752 /* PCIe PLL Configuration */
1753 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1754 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1755 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1762 * igb_read_mac_addr_82575 - Read device MAC address
1763 * @hw: pointer to the HW structure
1765 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1770 * If there's an alternate MAC address place it in RAR0
1771 * so that it will override the Si installed default perm
1774 ret_val
= igb_check_alt_mac_addr(hw
);
1778 ret_val
= igb_read_mac_addr(hw
);
1785 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1786 * @hw: pointer to the HW structure
1788 * In the case of a PHY power down to save power, or to turn off link during a
1789 * driver unload, or wake on lan is not enabled, remove the link.
1791 void igb_power_down_phy_copper_82575(struct e1000_hw
*hw
)
1793 /* If the management interface is not enabled, then power down */
1794 if (!(igb_enable_mng_pass_thru(hw
) || igb_check_reset_block(hw
)))
1795 igb_power_down_phy_copper(hw
);
1799 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1800 * @hw: pointer to the HW structure
1802 * Clears the hardware counters by reading the counter registers.
1804 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1806 igb_clear_hw_cntrs_base(hw
);
1812 rd32(E1000_PRC1023
);
1813 rd32(E1000_PRC1522
);
1818 rd32(E1000_PTC1023
);
1819 rd32(E1000_PTC1522
);
1821 rd32(E1000_ALGNERRC
);
1824 rd32(E1000_CEXTERR
);
1835 rd32(E1000_ICRXPTC
);
1836 rd32(E1000_ICRXATC
);
1837 rd32(E1000_ICTXPTC
);
1838 rd32(E1000_ICTXATC
);
1839 rd32(E1000_ICTXQEC
);
1840 rd32(E1000_ICTXQMTC
);
1841 rd32(E1000_ICRXDMTC
);
1848 rd32(E1000_HTCBDPC
);
1853 rd32(E1000_LENERRS
);
1855 /* This register should not be read in copper configurations */
1856 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
||
1857 igb_sgmii_active_82575(hw
))
1862 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1863 * @hw: pointer to the HW structure
1865 * After rx enable if managability is enabled then there is likely some
1866 * bad data at the start of the fifo and possibly in the DMA fifo. This
1867 * function clears the fifos and flushes any packets that came in as rx was
1870 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1872 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1875 if (hw
->mac
.type
!= e1000_82575
||
1876 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1879 /* Disable all RX queues */
1880 for (i
= 0; i
< 4; i
++) {
1881 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1882 wr32(E1000_RXDCTL(i
),
1883 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1885 /* Poll all queues to verify they have shut down */
1886 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1889 for (i
= 0; i
< 4; i
++)
1890 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1891 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1896 hw_dbg("Queue disable timed out after 10ms\n");
1898 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1899 * incoming packets are rejected. Set enable and wait 2ms so that
1900 * any packet that was coming in as RCTL.EN was set is flushed
1902 rfctl
= rd32(E1000_RFCTL
);
1903 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1905 rlpml
= rd32(E1000_RLPML
);
1906 wr32(E1000_RLPML
, 0);
1908 rctl
= rd32(E1000_RCTL
);
1909 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1910 temp_rctl
|= E1000_RCTL_LPE
;
1912 wr32(E1000_RCTL
, temp_rctl
);
1913 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1917 /* Enable RX queues that were previously enabled and restore our
1920 for (i
= 0; i
< 4; i
++)
1921 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1922 wr32(E1000_RCTL
, rctl
);
1925 wr32(E1000_RLPML
, rlpml
);
1926 wr32(E1000_RFCTL
, rfctl
);
1928 /* Flush receive errors generated by workaround */
1935 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1936 * @hw: pointer to the HW structure
1938 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1939 * however the hardware default for these parts is 500us to 1ms which is less
1940 * than the 10ms recommended by the pci-e spec. To address this we need to
1941 * increase the value to either 10ms to 200ms for capability version 1 config,
1942 * or 16ms to 55ms for version 2.
1944 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
)
1946 u32 gcr
= rd32(E1000_GCR
);
1950 /* only take action if timeout value is defaulted to 0 */
1951 if (gcr
& E1000_GCR_CMPL_TMOUT_MASK
)
1955 * if capababilities version is type 1 we can write the
1956 * timeout of 10ms to 200ms through the GCR register
1958 if (!(gcr
& E1000_GCR_CAP_VER2
)) {
1959 gcr
|= E1000_GCR_CMPL_TMOUT_10ms
;
1964 * for version 2 capabilities we need to write the config space
1965 * directly in order to set the completion timeout value for
1968 ret_val
= igb_read_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1973 pcie_devctl2
|= PCIE_DEVICE_CONTROL2_16ms
;
1975 ret_val
= igb_write_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1978 /* disable completion timeout resend */
1979 gcr
&= ~E1000_GCR_CMPL_TMOUT_RESEND
;
1981 wr32(E1000_GCR
, gcr
);
1986 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1987 * @hw: pointer to the hardware struct
1988 * @enable: state to enter, either enabled or disabled
1989 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1991 * enables/disables L2 switch anti-spoofing functionality.
1993 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw
*hw
, bool enable
, int pf
)
1997 switch (hw
->mac
.type
) {
2000 dtxswc
= rd32(E1000_DTXSWC
);
2002 dtxswc
|= (E1000_DTXSWC_MAC_SPOOF_MASK
|
2003 E1000_DTXSWC_VLAN_SPOOF_MASK
);
2004 /* The PF can spoof - it has to in order to
2005 * support emulation mode NICs */
2006 dtxswc
^= (1 << pf
| 1 << (pf
+ MAX_NUM_VFS
));
2008 dtxswc
&= ~(E1000_DTXSWC_MAC_SPOOF_MASK
|
2009 E1000_DTXSWC_VLAN_SPOOF_MASK
);
2011 wr32(E1000_DTXSWC
, dtxswc
);
2019 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2020 * @hw: pointer to the hardware struct
2021 * @enable: state to enter, either enabled or disabled
2023 * enables/disables L2 switch loopback functionality.
2025 void igb_vmdq_set_loopback_pf(struct e1000_hw
*hw
, bool enable
)
2029 switch (hw
->mac
.type
) {
2031 dtxswc
= rd32(E1000_DTXSWC
);
2033 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
2035 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
2036 wr32(E1000_DTXSWC
, dtxswc
);
2039 dtxswc
= rd32(E1000_TXSWC
);
2041 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
2043 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
2044 wr32(E1000_TXSWC
, dtxswc
);
2047 /* Currently no other hardware supports loopback */
2055 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2056 * @hw: pointer to the hardware struct
2057 * @enable: state to enter, either enabled or disabled
2059 * enables/disables replication of packets across multiple pools.
2061 void igb_vmdq_set_replication_pf(struct e1000_hw
*hw
, bool enable
)
2063 u32 vt_ctl
= rd32(E1000_VT_CTL
);
2066 vt_ctl
|= E1000_VT_CTL_VM_REPL_EN
;
2068 vt_ctl
&= ~E1000_VT_CTL_VM_REPL_EN
;
2070 wr32(E1000_VT_CTL
, vt_ctl
);
2074 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2075 * @hw: pointer to the HW structure
2076 * @offset: register offset to be read
2077 * @data: pointer to the read data
2079 * Reads the MDI control register in the PHY at offset and stores the
2080 * information read to data.
2082 static s32
igb_read_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2087 ret_val
= hw
->phy
.ops
.acquire(hw
);
2091 ret_val
= igb_read_phy_reg_mdic(hw
, offset
, data
);
2093 hw
->phy
.ops
.release(hw
);
2100 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2101 * @hw: pointer to the HW structure
2102 * @offset: register offset to write to
2103 * @data: data to write to register at offset
2105 * Writes data to MDI control register in the PHY at offset.
2107 static s32
igb_write_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2112 ret_val
= hw
->phy
.ops
.acquire(hw
);
2116 ret_val
= igb_write_phy_reg_mdic(hw
, offset
, data
);
2118 hw
->phy
.ops
.release(hw
);
2125 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2126 * @hw: pointer to the HW structure
2128 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2129 * the values found in the EEPROM. This addresses an issue in which these
2130 * bits are not restored from EEPROM after reset.
2132 static s32
igb_reset_mdicnfg_82580(struct e1000_hw
*hw
)
2138 if (hw
->mac
.type
!= e1000_82580
)
2140 if (!igb_sgmii_active_82575(hw
))
2143 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_A
+
2144 NVM_82580_LAN_FUNC_OFFSET(hw
->bus
.func
), 1,
2147 hw_dbg("NVM Read Error\n");
2151 mdicnfg
= rd32(E1000_MDICNFG
);
2152 if (nvm_data
& NVM_WORD24_EXT_MDIO
)
2153 mdicnfg
|= E1000_MDICNFG_EXT_MDIO
;
2154 if (nvm_data
& NVM_WORD24_COM_MDIO
)
2155 mdicnfg
|= E1000_MDICNFG_COM_MDIO
;
2156 wr32(E1000_MDICNFG
, mdicnfg
);
2162 * igb_reset_hw_82580 - Reset hardware
2163 * @hw: pointer to the HW structure
2165 * This resets function or entire device (all ports, etc.)
2168 static s32
igb_reset_hw_82580(struct e1000_hw
*hw
)
2171 /* BH SW mailbox bit in SW_FW_SYNC */
2172 u16 swmbsw_mask
= E1000_SW_SYNCH_MB
;
2174 bool global_device_reset
= hw
->dev_spec
._82575
.global_device_reset
;
2177 hw
->dev_spec
._82575
.global_device_reset
= false;
2179 /* due to hw errata, global device reset doesn't always
2182 if (hw
->mac
.type
== e1000_82580
)
2183 global_device_reset
= false;
2185 /* Get current control state. */
2186 ctrl
= rd32(E1000_CTRL
);
2189 * Prevent the PCI-E bus from sticking if there is no TLP connection
2190 * on the last TLP read/write transaction when MAC is reset.
2192 ret_val
= igb_disable_pcie_master(hw
);
2194 hw_dbg("PCI-E Master disable polling has failed.\n");
2196 hw_dbg("Masking off all interrupts\n");
2197 wr32(E1000_IMC
, 0xffffffff);
2198 wr32(E1000_RCTL
, 0);
2199 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
2204 /* Determine whether or not a global dev reset is requested */
2205 if (global_device_reset
&&
2206 hw
->mac
.ops
.acquire_swfw_sync(hw
, swmbsw_mask
))
2207 global_device_reset
= false;
2209 if (global_device_reset
&&
2210 !(rd32(E1000_STATUS
) & E1000_STAT_DEV_RST_SET
))
2211 ctrl
|= E1000_CTRL_DEV_RST
;
2213 ctrl
|= E1000_CTRL_RST
;
2215 wr32(E1000_CTRL
, ctrl
);
2218 /* Add delay to insure DEV_RST has time to complete */
2219 if (global_device_reset
)
2222 ret_val
= igb_get_auto_rd_done(hw
);
2225 * When auto config read does not complete, do not
2226 * return with an error. This can happen in situations
2227 * where there is no eeprom and prevents getting link.
2229 hw_dbg("Auto Read Done did not complete\n");
2232 /* If EEPROM is not present, run manual init scripts */
2233 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
2234 igb_reset_init_script_82575(hw
);
2236 /* clear global device reset status bit */
2237 wr32(E1000_STATUS
, E1000_STAT_DEV_RST_SET
);
2239 /* Clear any pending interrupt events. */
2240 wr32(E1000_IMC
, 0xffffffff);
2241 icr
= rd32(E1000_ICR
);
2243 ret_val
= igb_reset_mdicnfg_82580(hw
);
2245 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2247 /* Install any alternate MAC address into RAR0 */
2248 ret_val
= igb_check_alt_mac_addr(hw
);
2250 /* Release semaphore */
2251 if (global_device_reset
)
2252 hw
->mac
.ops
.release_swfw_sync(hw
, swmbsw_mask
);
2258 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2259 * @data: data received by reading RXPBS register
2261 * The 82580 uses a table based approach for packet buffer allocation sizes.
2262 * This function converts the retrieved value into the correct table value
2263 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2264 * 0x0 36 72 144 1 2 4 8 16
2265 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2267 u16
igb_rxpbs_adjust_82580(u32 data
)
2271 if (data
< E1000_82580_RXPBS_TABLE_SIZE
)
2272 ret_val
= e1000_82580_rxpbs_table
[data
];
2278 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2280 * @hw: pointer to the HW structure
2281 * @offset: offset in words of the checksum protected region
2283 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2284 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2286 static s32
igb_validate_nvm_checksum_with_offset(struct e1000_hw
*hw
,
2293 for (i
= offset
; i
< ((NVM_CHECKSUM_REG
+ offset
) + 1); i
++) {
2294 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
2296 hw_dbg("NVM Read Error\n");
2299 checksum
+= nvm_data
;
2302 if (checksum
!= (u16
) NVM_SUM
) {
2303 hw_dbg("NVM Checksum Invalid\n");
2304 ret_val
= -E1000_ERR_NVM
;
2313 * igb_update_nvm_checksum_with_offset - Update EEPROM
2315 * @hw: pointer to the HW structure
2316 * @offset: offset in words of the checksum protected region
2318 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2319 * up to the checksum. Then calculates the EEPROM checksum and writes the
2320 * value to the EEPROM.
2322 static s32
igb_update_nvm_checksum_with_offset(struct e1000_hw
*hw
, u16 offset
)
2328 for (i
= offset
; i
< (NVM_CHECKSUM_REG
+ offset
); i
++) {
2329 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
2331 hw_dbg("NVM Read Error while updating checksum.\n");
2334 checksum
+= nvm_data
;
2336 checksum
= (u16
) NVM_SUM
- checksum
;
2337 ret_val
= hw
->nvm
.ops
.write(hw
, (NVM_CHECKSUM_REG
+ offset
), 1,
2340 hw_dbg("NVM Write Error while updating checksum.\n");
2347 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2348 * @hw: pointer to the HW structure
2350 * Calculates the EEPROM section checksum by reading/adding each word of
2351 * the EEPROM and then verifies that the sum of the EEPROM is
2354 static s32
igb_validate_nvm_checksum_82580(struct e1000_hw
*hw
)
2357 u16 eeprom_regions_count
= 1;
2361 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPATIBILITY_REG_3
, 1, &nvm_data
);
2363 hw_dbg("NVM Read Error\n");
2367 if (nvm_data
& NVM_COMPATIBILITY_BIT_MASK
) {
2368 /* if checksums compatibility bit is set validate checksums
2369 * for all 4 ports. */
2370 eeprom_regions_count
= 4;
2373 for (j
= 0; j
< eeprom_regions_count
; j
++) {
2374 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2375 ret_val
= igb_validate_nvm_checksum_with_offset(hw
,
2386 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2387 * @hw: pointer to the HW structure
2389 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2390 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2391 * checksum and writes the value to the EEPROM.
2393 static s32
igb_update_nvm_checksum_82580(struct e1000_hw
*hw
)
2399 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPATIBILITY_REG_3
, 1, &nvm_data
);
2401 hw_dbg("NVM Read Error while updating checksum"
2402 " compatibility bit.\n");
2406 if ((nvm_data
& NVM_COMPATIBILITY_BIT_MASK
) == 0) {
2407 /* set compatibility bit to validate checksums appropriately */
2408 nvm_data
= nvm_data
| NVM_COMPATIBILITY_BIT_MASK
;
2409 ret_val
= hw
->nvm
.ops
.write(hw
, NVM_COMPATIBILITY_REG_3
, 1,
2412 hw_dbg("NVM Write Error while updating checksum"
2413 " compatibility bit.\n");
2418 for (j
= 0; j
< 4; j
++) {
2419 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2420 ret_val
= igb_update_nvm_checksum_with_offset(hw
, nvm_offset
);
2430 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2431 * @hw: pointer to the HW structure
2433 * Calculates the EEPROM section checksum by reading/adding each word of
2434 * the EEPROM and then verifies that the sum of the EEPROM is
2437 static s32
igb_validate_nvm_checksum_i350(struct e1000_hw
*hw
)
2443 for (j
= 0; j
< 4; j
++) {
2444 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2445 ret_val
= igb_validate_nvm_checksum_with_offset(hw
,
2456 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2457 * @hw: pointer to the HW structure
2459 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2460 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2461 * checksum and writes the value to the EEPROM.
2463 static s32
igb_update_nvm_checksum_i350(struct e1000_hw
*hw
)
2469 for (j
= 0; j
< 4; j
++) {
2470 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2471 ret_val
= igb_update_nvm_checksum_with_offset(hw
, nvm_offset
);
2481 * igb_set_eee_i350 - Enable/disable EEE support
2482 * @hw: pointer to the HW structure
2484 * Enable/disable EEE based on setting in dev_spec structure.
2487 s32
igb_set_eee_i350(struct e1000_hw
*hw
)
2492 if ((hw
->mac
.type
< e1000_i350
) ||
2493 (hw
->phy
.media_type
!= e1000_media_type_copper
))
2495 ipcnfg
= rd32(E1000_IPCNFG
);
2496 eeer
= rd32(E1000_EEER
);
2498 /* enable or disable per user setting */
2499 if (!(hw
->dev_spec
._82575
.eee_disable
)) {
2500 u32 eee_su
= rd32(E1000_EEE_SU
);
2502 ipcnfg
|= (E1000_IPCNFG_EEE_1G_AN
| E1000_IPCNFG_EEE_100M_AN
);
2503 eeer
|= (E1000_EEER_TX_LPI_EN
| E1000_EEER_RX_LPI_EN
|
2506 /* This bit should not be set in normal operation. */
2507 if (eee_su
& E1000_EEE_SU_LPI_CLK_STP
)
2508 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2512 ipcnfg
&= ~(E1000_IPCNFG_EEE_1G_AN
|
2513 E1000_IPCNFG_EEE_100M_AN
);
2514 eeer
&= ~(E1000_EEER_TX_LPI_EN
|
2515 E1000_EEER_RX_LPI_EN
|
2518 wr32(E1000_IPCNFG
, ipcnfg
);
2519 wr32(E1000_EEER
, eeer
);
2527 static const u8 e1000_emc_temp_data
[4] = {
2528 E1000_EMC_INTERNAL_DATA
,
2529 E1000_EMC_DIODE1_DATA
,
2530 E1000_EMC_DIODE2_DATA
,
2531 E1000_EMC_DIODE3_DATA
2533 static const u8 e1000_emc_therm_limit
[4] = {
2534 E1000_EMC_INTERNAL_THERM_LIMIT
,
2535 E1000_EMC_DIODE1_THERM_LIMIT
,
2536 E1000_EMC_DIODE2_THERM_LIMIT
,
2537 E1000_EMC_DIODE3_THERM_LIMIT
2540 /* igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2541 * @hw: pointer to hardware structure
2543 * Updates the temperatures in mac.thermal_sensor_data
2545 s32
igb_get_thermal_sensor_data_generic(struct e1000_hw
*hw
)
2547 s32 status
= E1000_SUCCESS
;
2555 struct e1000_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
2557 if ((hw
->mac
.type
!= e1000_i350
) || (hw
->bus
.func
!= 0))
2558 return E1000_NOT_IMPLEMENTED
;
2560 data
->sensor
[0].temp
= (rd32(E1000_THMJT
) & 0xFF);
2562 /* Return the internal sensor only if ETS is unsupported */
2563 hw
->nvm
.ops
.read(hw
, NVM_ETS_CFG
, 1, &ets_offset
);
2564 if ((ets_offset
== 0x0000) || (ets_offset
== 0xFFFF))
2567 hw
->nvm
.ops
.read(hw
, ets_offset
, 1, &ets_cfg
);
2568 if (((ets_cfg
& NVM_ETS_TYPE_MASK
) >> NVM_ETS_TYPE_SHIFT
)
2569 != NVM_ETS_TYPE_EMC
)
2570 return E1000_NOT_IMPLEMENTED
;
2572 num_sensors
= (ets_cfg
& NVM_ETS_NUM_SENSORS_MASK
);
2573 if (num_sensors
> E1000_MAX_SENSORS
)
2574 num_sensors
= E1000_MAX_SENSORS
;
2576 for (i
= 1; i
< num_sensors
; i
++) {
2577 hw
->nvm
.ops
.read(hw
, (ets_offset
+ i
), 1, &ets_sensor
);
2578 sensor_index
= ((ets_sensor
& NVM_ETS_DATA_INDEX_MASK
) >>
2579 NVM_ETS_DATA_INDEX_SHIFT
);
2580 sensor_location
= ((ets_sensor
& NVM_ETS_DATA_LOC_MASK
) >>
2581 NVM_ETS_DATA_LOC_SHIFT
);
2583 if (sensor_location
!= 0)
2584 hw
->phy
.ops
.read_i2c_byte(hw
,
2585 e1000_emc_temp_data
[sensor_index
],
2586 E1000_I2C_THERMAL_SENSOR_ADDR
,
2587 &data
->sensor
[i
].temp
);
2592 /* igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2593 * @hw: pointer to hardware structure
2595 * Sets the thermal sensor thresholds according to the NVM map
2596 * and save off the threshold and location values into mac.thermal_sensor_data
2598 s32
igb_init_thermal_sensor_thresh_generic(struct e1000_hw
*hw
)
2600 s32 status
= E1000_SUCCESS
;
2604 u8 low_thresh_delta
;
2610 struct e1000_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
2612 if ((hw
->mac
.type
!= e1000_i350
) || (hw
->bus
.func
!= 0))
2613 return E1000_NOT_IMPLEMENTED
;
2615 memset(data
, 0, sizeof(struct e1000_thermal_sensor_data
));
2617 data
->sensor
[0].location
= 0x1;
2618 data
->sensor
[0].caution_thresh
=
2619 (rd32(E1000_THHIGHTC
) & 0xFF);
2620 data
->sensor
[0].max_op_thresh
=
2621 (rd32(E1000_THLOWTC
) & 0xFF);
2623 /* Return the internal sensor only if ETS is unsupported */
2624 hw
->nvm
.ops
.read(hw
, NVM_ETS_CFG
, 1, &ets_offset
);
2625 if ((ets_offset
== 0x0000) || (ets_offset
== 0xFFFF))
2628 hw
->nvm
.ops
.read(hw
, ets_offset
, 1, &ets_cfg
);
2629 if (((ets_cfg
& NVM_ETS_TYPE_MASK
) >> NVM_ETS_TYPE_SHIFT
)
2630 != NVM_ETS_TYPE_EMC
)
2631 return E1000_NOT_IMPLEMENTED
;
2633 low_thresh_delta
= ((ets_cfg
& NVM_ETS_LTHRES_DELTA_MASK
) >>
2634 NVM_ETS_LTHRES_DELTA_SHIFT
);
2635 num_sensors
= (ets_cfg
& NVM_ETS_NUM_SENSORS_MASK
);
2637 for (i
= 1; i
<= num_sensors
; i
++) {
2638 hw
->nvm
.ops
.read(hw
, (ets_offset
+ i
), 1, &ets_sensor
);
2639 sensor_index
= ((ets_sensor
& NVM_ETS_DATA_INDEX_MASK
) >>
2640 NVM_ETS_DATA_INDEX_SHIFT
);
2641 sensor_location
= ((ets_sensor
& NVM_ETS_DATA_LOC_MASK
) >>
2642 NVM_ETS_DATA_LOC_SHIFT
);
2643 therm_limit
= ets_sensor
& NVM_ETS_DATA_HTHRESH_MASK
;
2645 hw
->phy
.ops
.write_i2c_byte(hw
,
2646 e1000_emc_therm_limit
[sensor_index
],
2647 E1000_I2C_THERMAL_SENSOR_ADDR
,
2650 if ((i
< E1000_MAX_SENSORS
) && (sensor_location
!= 0)) {
2651 data
->sensor
[i
].location
= sensor_location
;
2652 data
->sensor
[i
].caution_thresh
= therm_limit
;
2653 data
->sensor
[i
].max_op_thresh
= therm_limit
-
2660 static struct e1000_mac_operations e1000_mac_ops_82575
= {
2661 .init_hw
= igb_init_hw_82575
,
2662 .check_for_link
= igb_check_for_link_82575
,
2663 .rar_set
= igb_rar_set
,
2664 .read_mac_addr
= igb_read_mac_addr_82575
,
2665 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
2666 #ifdef CONFIG_IGB_HWMON
2667 .get_thermal_sensor_data
= igb_get_thermal_sensor_data_generic
,
2668 .init_thermal_sensor_thresh
= igb_init_thermal_sensor_thresh_generic
,
2672 static struct e1000_phy_operations e1000_phy_ops_82575
= {
2673 .acquire
= igb_acquire_phy_82575
,
2674 .get_cfg_done
= igb_get_cfg_done_82575
,
2675 .release
= igb_release_phy_82575
,
2676 .write_i2c_byte
= igb_write_i2c_byte
,
2677 .read_i2c_byte
= igb_read_i2c_byte
,
2680 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
2681 .acquire
= igb_acquire_nvm_82575
,
2682 .read
= igb_read_nvm_eerd
,
2683 .release
= igb_release_nvm_82575
,
2684 .write
= igb_write_nvm_spi
,
2687 const struct e1000_info e1000_82575_info
= {
2688 .get_invariants
= igb_get_invariants_82575
,
2689 .mac_ops
= &e1000_mac_ops_82575
,
2690 .phy_ops
= &e1000_phy_ops_82575
,
2691 .nvm_ops
= &e1000_nvm_ops_82575
,