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x86: Move call to print_modules() out of show_regs()
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36
37 #include "e1000_mac.h"
38 #include "e1000_82575.h"
39 #include "e1000_i210.h"
40
41 static s32 igb_get_invariants_82575(struct e1000_hw *);
42 static s32 igb_acquire_phy_82575(struct e1000_hw *);
43 static void igb_release_phy_82575(struct e1000_hw *);
44 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
45 static void igb_release_nvm_82575(struct e1000_hw *);
46 static s32 igb_check_for_link_82575(struct e1000_hw *);
47 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
48 static s32 igb_init_hw_82575(struct e1000_hw *);
49 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
50 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
51 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
52 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
53 static s32 igb_reset_hw_82575(struct e1000_hw *);
54 static s32 igb_reset_hw_82580(struct e1000_hw *);
55 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
56 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
57 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
58 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
59 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
60 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
61 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
62 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
63 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
64 u16 *);
65 static s32 igb_get_phy_id_82575(struct e1000_hw *);
66 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
67 static bool igb_sgmii_active_82575(struct e1000_hw *);
68 static s32 igb_reset_init_script_82575(struct e1000_hw *);
69 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
70 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
71 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
72 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
73 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
74 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
75 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
76 static const u16 e1000_82580_rxpbs_table[] =
77 { 36, 72, 144, 1, 2, 4, 8, 16,
78 35, 70, 140 };
79 #define E1000_82580_RXPBS_TABLE_SIZE \
80 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
81
82 /**
83 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
84 * @hw: pointer to the HW structure
85 *
86 * Called to determine if the I2C pins are being used for I2C or as an
87 * external MDIO interface since the two options are mutually exclusive.
88 **/
89 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
90 {
91 u32 reg = 0;
92 bool ext_mdio = false;
93
94 switch (hw->mac.type) {
95 case e1000_82575:
96 case e1000_82576:
97 reg = rd32(E1000_MDIC);
98 ext_mdio = !!(reg & E1000_MDIC_DEST);
99 break;
100 case e1000_82580:
101 case e1000_i350:
102 case e1000_i210:
103 case e1000_i211:
104 reg = rd32(E1000_MDICNFG);
105 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
106 break;
107 default:
108 break;
109 }
110 return ext_mdio;
111 }
112
113 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
114 {
115 struct e1000_phy_info *phy = &hw->phy;
116 struct e1000_nvm_info *nvm = &hw->nvm;
117 struct e1000_mac_info *mac = &hw->mac;
118 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
119 u32 eecd;
120 s32 ret_val;
121 u16 size;
122 u32 ctrl_ext = 0;
123
124 switch (hw->device_id) {
125 case E1000_DEV_ID_82575EB_COPPER:
126 case E1000_DEV_ID_82575EB_FIBER_SERDES:
127 case E1000_DEV_ID_82575GB_QUAD_COPPER:
128 mac->type = e1000_82575;
129 break;
130 case E1000_DEV_ID_82576:
131 case E1000_DEV_ID_82576_NS:
132 case E1000_DEV_ID_82576_NS_SERDES:
133 case E1000_DEV_ID_82576_FIBER:
134 case E1000_DEV_ID_82576_SERDES:
135 case E1000_DEV_ID_82576_QUAD_COPPER:
136 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
137 case E1000_DEV_ID_82576_SERDES_QUAD:
138 mac->type = e1000_82576;
139 break;
140 case E1000_DEV_ID_82580_COPPER:
141 case E1000_DEV_ID_82580_FIBER:
142 case E1000_DEV_ID_82580_QUAD_FIBER:
143 case E1000_DEV_ID_82580_SERDES:
144 case E1000_DEV_ID_82580_SGMII:
145 case E1000_DEV_ID_82580_COPPER_DUAL:
146 case E1000_DEV_ID_DH89XXCC_SGMII:
147 case E1000_DEV_ID_DH89XXCC_SERDES:
148 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
149 case E1000_DEV_ID_DH89XXCC_SFP:
150 mac->type = e1000_82580;
151 break;
152 case E1000_DEV_ID_I350_COPPER:
153 case E1000_DEV_ID_I350_FIBER:
154 case E1000_DEV_ID_I350_SERDES:
155 case E1000_DEV_ID_I350_SGMII:
156 mac->type = e1000_i350;
157 break;
158 case E1000_DEV_ID_I210_COPPER:
159 case E1000_DEV_ID_I210_COPPER_OEM1:
160 case E1000_DEV_ID_I210_COPPER_IT:
161 case E1000_DEV_ID_I210_FIBER:
162 case E1000_DEV_ID_I210_SERDES:
163 case E1000_DEV_ID_I210_SGMII:
164 mac->type = e1000_i210;
165 break;
166 case E1000_DEV_ID_I211_COPPER:
167 mac->type = e1000_i211;
168 break;
169 default:
170 return -E1000_ERR_MAC_INIT;
171 break;
172 }
173
174 /* Set media type */
175 /*
176 * The 82575 uses bits 22:23 for link mode. The mode can be changed
177 * based on the EEPROM. We cannot rely upon device ID. There
178 * is no distinguishable difference between fiber and internal
179 * SerDes mode on the 82575. There can be an external PHY attached
180 * on the SGMII interface. For this, we'll set sgmii_active to true.
181 */
182 phy->media_type = e1000_media_type_copper;
183 dev_spec->sgmii_active = false;
184
185 ctrl_ext = rd32(E1000_CTRL_EXT);
186 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
187 case E1000_CTRL_EXT_LINK_MODE_SGMII:
188 dev_spec->sgmii_active = true;
189 break;
190 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
191 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
192 hw->phy.media_type = e1000_media_type_internal_serdes;
193 break;
194 default:
195 break;
196 }
197
198 /* Set mta register count */
199 mac->mta_reg_count = 128;
200 /* Set rar entry count */
201 switch (mac->type) {
202 case e1000_82576:
203 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
204 break;
205 case e1000_82580:
206 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
207 break;
208 case e1000_i350:
209 case e1000_i210:
210 case e1000_i211:
211 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
212 break;
213 default:
214 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
215 break;
216 }
217 /* reset */
218 if (mac->type >= e1000_82580)
219 mac->ops.reset_hw = igb_reset_hw_82580;
220 else
221 mac->ops.reset_hw = igb_reset_hw_82575;
222
223 if (mac->type >= e1000_i210) {
224 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
225 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
226 } else {
227 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
228 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
229 }
230
231 /* Set if part includes ASF firmware */
232 mac->asf_firmware_present = true;
233 /* Set if manageability features are enabled. */
234 mac->arc_subsystem_valid =
235 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
236 ? true : false;
237 /* enable EEE on i350 parts and later parts */
238 if (mac->type >= e1000_i350)
239 dev_spec->eee_disable = false;
240 else
241 dev_spec->eee_disable = true;
242 /* physical interface link setup */
243 mac->ops.setup_physical_interface =
244 (hw->phy.media_type == e1000_media_type_copper)
245 ? igb_setup_copper_link_82575
246 : igb_setup_serdes_link_82575;
247
248 /* NVM initialization */
249 eecd = rd32(E1000_EECD);
250 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
251 E1000_EECD_SIZE_EX_SHIFT);
252
253 /*
254 * Added to a constant, "size" becomes the left-shift value
255 * for setting word_size.
256 */
257 size += NVM_WORD_SIZE_BASE_SHIFT;
258
259 nvm->word_size = 1 << size;
260 if (hw->mac.type < e1000_i210) {
261 nvm->opcode_bits = 8;
262 nvm->delay_usec = 1;
263 switch (nvm->override) {
264 case e1000_nvm_override_spi_large:
265 nvm->page_size = 32;
266 nvm->address_bits = 16;
267 break;
268 case e1000_nvm_override_spi_small:
269 nvm->page_size = 8;
270 nvm->address_bits = 8;
271 break;
272 default:
273 nvm->page_size = eecd
274 & E1000_EECD_ADDR_BITS ? 32 : 8;
275 nvm->address_bits = eecd
276 & E1000_EECD_ADDR_BITS ? 16 : 8;
277 break;
278 }
279 if (nvm->word_size == (1 << 15))
280 nvm->page_size = 128;
281
282 nvm->type = e1000_nvm_eeprom_spi;
283 } else
284 nvm->type = e1000_nvm_flash_hw;
285
286 /*
287 * Check for invalid size
288 */
289 if ((hw->mac.type == e1000_82576) && (size > 15)) {
290 pr_notice("The NVM size is not valid, defaulting to 32K\n");
291 size = 15;
292 }
293
294 /* NVM Function Pointers */
295 switch (hw->mac.type) {
296 case e1000_82580:
297 nvm->ops.validate = igb_validate_nvm_checksum_82580;
298 nvm->ops.update = igb_update_nvm_checksum_82580;
299 nvm->ops.acquire = igb_acquire_nvm_82575;
300 nvm->ops.release = igb_release_nvm_82575;
301 if (nvm->word_size < (1 << 15))
302 nvm->ops.read = igb_read_nvm_eerd;
303 else
304 nvm->ops.read = igb_read_nvm_spi;
305 nvm->ops.write = igb_write_nvm_spi;
306 break;
307 case e1000_i350:
308 nvm->ops.validate = igb_validate_nvm_checksum_i350;
309 nvm->ops.update = igb_update_nvm_checksum_i350;
310 nvm->ops.acquire = igb_acquire_nvm_82575;
311 nvm->ops.release = igb_release_nvm_82575;
312 if (nvm->word_size < (1 << 15))
313 nvm->ops.read = igb_read_nvm_eerd;
314 else
315 nvm->ops.read = igb_read_nvm_spi;
316 nvm->ops.write = igb_write_nvm_spi;
317 break;
318 case e1000_i210:
319 nvm->ops.validate = igb_validate_nvm_checksum_i210;
320 nvm->ops.update = igb_update_nvm_checksum_i210;
321 nvm->ops.acquire = igb_acquire_nvm_i210;
322 nvm->ops.release = igb_release_nvm_i210;
323 nvm->ops.read = igb_read_nvm_srrd_i210;
324 nvm->ops.valid_led_default = igb_valid_led_default_i210;
325 break;
326 case e1000_i211:
327 nvm->ops.acquire = igb_acquire_nvm_i210;
328 nvm->ops.release = igb_release_nvm_i210;
329 nvm->ops.read = igb_read_nvm_i211;
330 nvm->ops.valid_led_default = igb_valid_led_default_i210;
331 nvm->ops.validate = NULL;
332 nvm->ops.update = NULL;
333 nvm->ops.write = NULL;
334 break;
335 default:
336 nvm->ops.validate = igb_validate_nvm_checksum;
337 nvm->ops.update = igb_update_nvm_checksum;
338 nvm->ops.acquire = igb_acquire_nvm_82575;
339 nvm->ops.release = igb_release_nvm_82575;
340 if (nvm->word_size < (1 << 15))
341 nvm->ops.read = igb_read_nvm_eerd;
342 else
343 nvm->ops.read = igb_read_nvm_spi;
344 nvm->ops.write = igb_write_nvm_spi;
345 break;
346 }
347
348 /* if part supports SR-IOV then initialize mailbox parameters */
349 switch (mac->type) {
350 case e1000_82576:
351 case e1000_i350:
352 igb_init_mbx_params_pf(hw);
353 break;
354 default:
355 break;
356 }
357
358 /* setup PHY parameters */
359 if (phy->media_type != e1000_media_type_copper) {
360 phy->type = e1000_phy_none;
361 return 0;
362 }
363
364 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
365 phy->reset_delay_us = 100;
366
367 ctrl_ext = rd32(E1000_CTRL_EXT);
368
369 /* PHY function pointers */
370 if (igb_sgmii_active_82575(hw)) {
371 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
372 ctrl_ext |= E1000_CTRL_I2C_ENA;
373 } else {
374 phy->ops.reset = igb_phy_hw_reset;
375 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
376 }
377
378 wr32(E1000_CTRL_EXT, ctrl_ext);
379 igb_reset_mdicnfg_82580(hw);
380
381 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
382 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
383 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
384 } else if ((hw->mac.type == e1000_82580)
385 || (hw->mac.type == e1000_i350)) {
386 phy->ops.read_reg = igb_read_phy_reg_82580;
387 phy->ops.write_reg = igb_write_phy_reg_82580;
388 } else if (hw->phy.type >= e1000_phy_i210) {
389 phy->ops.read_reg = igb_read_phy_reg_gs40g;
390 phy->ops.write_reg = igb_write_phy_reg_gs40g;
391 } else {
392 phy->ops.read_reg = igb_read_phy_reg_igp;
393 phy->ops.write_reg = igb_write_phy_reg_igp;
394 }
395
396 /* set lan id */
397 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
398 E1000_STATUS_FUNC_SHIFT;
399
400 /* Set phy->phy_addr and phy->id. */
401 ret_val = igb_get_phy_id_82575(hw);
402 if (ret_val)
403 return ret_val;
404
405 /* Verify phy id and set remaining function pointers */
406 switch (phy->id) {
407 case I347AT4_E_PHY_ID:
408 case M88E1112_E_PHY_ID:
409 case M88E1111_I_PHY_ID:
410 phy->type = e1000_phy_m88;
411 phy->ops.get_phy_info = igb_get_phy_info_m88;
412
413 if (phy->id == I347AT4_E_PHY_ID ||
414 phy->id == M88E1112_E_PHY_ID)
415 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
416 else
417 phy->ops.get_cable_length = igb_get_cable_length_m88;
418
419 if (phy->id == I210_I_PHY_ID) {
420 phy->ops.get_cable_length =
421 igb_get_cable_length_m88_gen2;
422 phy->ops.set_d0_lplu_state =
423 igb_set_d0_lplu_state_82580;
424 phy->ops.set_d3_lplu_state =
425 igb_set_d3_lplu_state_82580;
426 }
427 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
428 break;
429 case IGP03E1000_E_PHY_ID:
430 phy->type = e1000_phy_igp_3;
431 phy->ops.get_phy_info = igb_get_phy_info_igp;
432 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
433 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
434 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
435 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
436 break;
437 case I82580_I_PHY_ID:
438 case I350_I_PHY_ID:
439 phy->type = e1000_phy_82580;
440 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
441 phy->ops.get_cable_length = igb_get_cable_length_82580;
442 phy->ops.get_phy_info = igb_get_phy_info_82580;
443 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
444 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
445 break;
446 case I210_I_PHY_ID:
447 phy->type = e1000_phy_i210;
448 phy->ops.get_phy_info = igb_get_phy_info_m88;
449 phy->ops.check_polarity = igb_check_polarity_m88;
450 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
451 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
452 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
453 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
454 break;
455 default:
456 return -E1000_ERR_PHY;
457 }
458
459 return 0;
460 }
461
462 /**
463 * igb_acquire_phy_82575 - Acquire rights to access PHY
464 * @hw: pointer to the HW structure
465 *
466 * Acquire access rights to the correct PHY. This is a
467 * function pointer entry point called by the api module.
468 **/
469 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
470 {
471 u16 mask = E1000_SWFW_PHY0_SM;
472
473 if (hw->bus.func == E1000_FUNC_1)
474 mask = E1000_SWFW_PHY1_SM;
475 else if (hw->bus.func == E1000_FUNC_2)
476 mask = E1000_SWFW_PHY2_SM;
477 else if (hw->bus.func == E1000_FUNC_3)
478 mask = E1000_SWFW_PHY3_SM;
479
480 return hw->mac.ops.acquire_swfw_sync(hw, mask);
481 }
482
483 /**
484 * igb_release_phy_82575 - Release rights to access PHY
485 * @hw: pointer to the HW structure
486 *
487 * A wrapper to release access rights to the correct PHY. This is a
488 * function pointer entry point called by the api module.
489 **/
490 static void igb_release_phy_82575(struct e1000_hw *hw)
491 {
492 u16 mask = E1000_SWFW_PHY0_SM;
493
494 if (hw->bus.func == E1000_FUNC_1)
495 mask = E1000_SWFW_PHY1_SM;
496 else if (hw->bus.func == E1000_FUNC_2)
497 mask = E1000_SWFW_PHY2_SM;
498 else if (hw->bus.func == E1000_FUNC_3)
499 mask = E1000_SWFW_PHY3_SM;
500
501 hw->mac.ops.release_swfw_sync(hw, mask);
502 }
503
504 /**
505 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
506 * @hw: pointer to the HW structure
507 * @offset: register offset to be read
508 * @data: pointer to the read data
509 *
510 * Reads the PHY register at offset using the serial gigabit media independent
511 * interface and stores the retrieved information in data.
512 **/
513 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
514 u16 *data)
515 {
516 s32 ret_val = -E1000_ERR_PARAM;
517
518 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
519 hw_dbg("PHY Address %u is out of range\n", offset);
520 goto out;
521 }
522
523 ret_val = hw->phy.ops.acquire(hw);
524 if (ret_val)
525 goto out;
526
527 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
528
529 hw->phy.ops.release(hw);
530
531 out:
532 return ret_val;
533 }
534
535 /**
536 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
537 * @hw: pointer to the HW structure
538 * @offset: register offset to write to
539 * @data: data to write at register offset
540 *
541 * Writes the data to PHY register at the offset using the serial gigabit
542 * media independent interface.
543 **/
544 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
545 u16 data)
546 {
547 s32 ret_val = -E1000_ERR_PARAM;
548
549
550 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
551 hw_dbg("PHY Address %d is out of range\n", offset);
552 goto out;
553 }
554
555 ret_val = hw->phy.ops.acquire(hw);
556 if (ret_val)
557 goto out;
558
559 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
560
561 hw->phy.ops.release(hw);
562
563 out:
564 return ret_val;
565 }
566
567 /**
568 * igb_get_phy_id_82575 - Retrieve PHY addr and id
569 * @hw: pointer to the HW structure
570 *
571 * Retrieves the PHY address and ID for both PHY's which do and do not use
572 * sgmi interface.
573 **/
574 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
575 {
576 struct e1000_phy_info *phy = &hw->phy;
577 s32 ret_val = 0;
578 u16 phy_id;
579 u32 ctrl_ext;
580 u32 mdic;
581
582 /*
583 * For SGMII PHYs, we try the list of possible addresses until
584 * we find one that works. For non-SGMII PHYs
585 * (e.g. integrated copper PHYs), an address of 1 should
586 * work. The result of this function should mean phy->phy_addr
587 * and phy->id are set correctly.
588 */
589 if (!(igb_sgmii_active_82575(hw))) {
590 phy->addr = 1;
591 ret_val = igb_get_phy_id(hw);
592 goto out;
593 }
594
595 if (igb_sgmii_uses_mdio_82575(hw)) {
596 switch (hw->mac.type) {
597 case e1000_82575:
598 case e1000_82576:
599 mdic = rd32(E1000_MDIC);
600 mdic &= E1000_MDIC_PHY_MASK;
601 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
602 break;
603 case e1000_82580:
604 case e1000_i350:
605 case e1000_i210:
606 case e1000_i211:
607 mdic = rd32(E1000_MDICNFG);
608 mdic &= E1000_MDICNFG_PHY_MASK;
609 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
610 break;
611 default:
612 ret_val = -E1000_ERR_PHY;
613 goto out;
614 break;
615 }
616 ret_val = igb_get_phy_id(hw);
617 goto out;
618 }
619
620 /* Power on sgmii phy if it is disabled */
621 ctrl_ext = rd32(E1000_CTRL_EXT);
622 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
623 wrfl();
624 msleep(300);
625
626 /*
627 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
628 * Therefore, we need to test 1-7
629 */
630 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
631 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
632 if (ret_val == 0) {
633 hw_dbg("Vendor ID 0x%08X read at address %u\n",
634 phy_id, phy->addr);
635 /*
636 * At the time of this writing, The M88 part is
637 * the only supported SGMII PHY product.
638 */
639 if (phy_id == M88_VENDOR)
640 break;
641 } else {
642 hw_dbg("PHY address %u was unreadable\n", phy->addr);
643 }
644 }
645
646 /* A valid PHY type couldn't be found. */
647 if (phy->addr == 8) {
648 phy->addr = 0;
649 ret_val = -E1000_ERR_PHY;
650 goto out;
651 } else {
652 ret_val = igb_get_phy_id(hw);
653 }
654
655 /* restore previous sfp cage power state */
656 wr32(E1000_CTRL_EXT, ctrl_ext);
657
658 out:
659 return ret_val;
660 }
661
662 /**
663 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
664 * @hw: pointer to the HW structure
665 *
666 * Resets the PHY using the serial gigabit media independent interface.
667 **/
668 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
669 {
670 s32 ret_val;
671
672 /*
673 * This isn't a true "hard" reset, but is the only reset
674 * available to us at this time.
675 */
676
677 hw_dbg("Soft resetting SGMII attached PHY...\n");
678
679 /*
680 * SFP documentation requires the following to configure the SPF module
681 * to work on SGMII. No further documentation is given.
682 */
683 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
684 if (ret_val)
685 goto out;
686
687 ret_val = igb_phy_sw_reset(hw);
688
689 out:
690 return ret_val;
691 }
692
693 /**
694 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
695 * @hw: pointer to the HW structure
696 * @active: true to enable LPLU, false to disable
697 *
698 * Sets the LPLU D0 state according to the active flag. When
699 * activating LPLU this function also disables smart speed
700 * and vice versa. LPLU will not be activated unless the
701 * device autonegotiation advertisement meets standards of
702 * either 10 or 10/100 or 10/100/1000 at all duplexes.
703 * This is a function pointer entry point only called by
704 * PHY setup routines.
705 **/
706 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
707 {
708 struct e1000_phy_info *phy = &hw->phy;
709 s32 ret_val;
710 u16 data;
711
712 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
713 if (ret_val)
714 goto out;
715
716 if (active) {
717 data |= IGP02E1000_PM_D0_LPLU;
718 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
719 data);
720 if (ret_val)
721 goto out;
722
723 /* When LPLU is enabled, we should disable SmartSpeed */
724 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
725 &data);
726 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
727 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
728 data);
729 if (ret_val)
730 goto out;
731 } else {
732 data &= ~IGP02E1000_PM_D0_LPLU;
733 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
734 data);
735 /*
736 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
737 * during Dx states where the power conservation is most
738 * important. During driver activity we should enable
739 * SmartSpeed, so performance is maintained.
740 */
741 if (phy->smart_speed == e1000_smart_speed_on) {
742 ret_val = phy->ops.read_reg(hw,
743 IGP01E1000_PHY_PORT_CONFIG, &data);
744 if (ret_val)
745 goto out;
746
747 data |= IGP01E1000_PSCFR_SMART_SPEED;
748 ret_val = phy->ops.write_reg(hw,
749 IGP01E1000_PHY_PORT_CONFIG, data);
750 if (ret_val)
751 goto out;
752 } else if (phy->smart_speed == e1000_smart_speed_off) {
753 ret_val = phy->ops.read_reg(hw,
754 IGP01E1000_PHY_PORT_CONFIG, &data);
755 if (ret_val)
756 goto out;
757
758 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
759 ret_val = phy->ops.write_reg(hw,
760 IGP01E1000_PHY_PORT_CONFIG, data);
761 if (ret_val)
762 goto out;
763 }
764 }
765
766 out:
767 return ret_val;
768 }
769
770 /**
771 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
772 * @hw: pointer to the HW structure
773 * @active: true to enable LPLU, false to disable
774 *
775 * Sets the LPLU D0 state according to the active flag. When
776 * activating LPLU this function also disables smart speed
777 * and vice versa. LPLU will not be activated unless the
778 * device autonegotiation advertisement meets standards of
779 * either 10 or 10/100 or 10/100/1000 at all duplexes.
780 * This is a function pointer entry point only called by
781 * PHY setup routines.
782 **/
783 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
784 {
785 struct e1000_phy_info *phy = &hw->phy;
786 s32 ret_val = 0;
787 u16 data;
788
789 data = rd32(E1000_82580_PHY_POWER_MGMT);
790
791 if (active) {
792 data |= E1000_82580_PM_D0_LPLU;
793
794 /* When LPLU is enabled, we should disable SmartSpeed */
795 data &= ~E1000_82580_PM_SPD;
796 } else {
797 data &= ~E1000_82580_PM_D0_LPLU;
798
799 /*
800 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
801 * during Dx states where the power conservation is most
802 * important. During driver activity we should enable
803 * SmartSpeed, so performance is maintained.
804 */
805 if (phy->smart_speed == e1000_smart_speed_on)
806 data |= E1000_82580_PM_SPD;
807 else if (phy->smart_speed == e1000_smart_speed_off)
808 data &= ~E1000_82580_PM_SPD; }
809
810 wr32(E1000_82580_PHY_POWER_MGMT, data);
811 return ret_val;
812 }
813
814 /**
815 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
816 * @hw: pointer to the HW structure
817 * @active: boolean used to enable/disable lplu
818 *
819 * Success returns 0, Failure returns 1
820 *
821 * The low power link up (lplu) state is set to the power management level D3
822 * and SmartSpeed is disabled when active is true, else clear lplu for D3
823 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
824 * is used during Dx states where the power conservation is most important.
825 * During driver activity, SmartSpeed should be enabled so performance is
826 * maintained.
827 **/
828 s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
829 {
830 struct e1000_phy_info *phy = &hw->phy;
831 s32 ret_val = 0;
832 u16 data;
833
834 data = rd32(E1000_82580_PHY_POWER_MGMT);
835
836 if (!active) {
837 data &= ~E1000_82580_PM_D3_LPLU;
838 /*
839 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
840 * during Dx states where the power conservation is most
841 * important. During driver activity we should enable
842 * SmartSpeed, so performance is maintained.
843 */
844 if (phy->smart_speed == e1000_smart_speed_on)
845 data |= E1000_82580_PM_SPD;
846 else if (phy->smart_speed == e1000_smart_speed_off)
847 data &= ~E1000_82580_PM_SPD;
848 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
849 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
850 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
851 data |= E1000_82580_PM_D3_LPLU;
852 /* When LPLU is enabled, we should disable SmartSpeed */
853 data &= ~E1000_82580_PM_SPD;
854 }
855
856 wr32(E1000_82580_PHY_POWER_MGMT, data);
857 return ret_val;
858 }
859
860 /**
861 * igb_acquire_nvm_82575 - Request for access to EEPROM
862 * @hw: pointer to the HW structure
863 *
864 * Acquire the necessary semaphores for exclusive access to the EEPROM.
865 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
866 * Return successful if access grant bit set, else clear the request for
867 * EEPROM access and return -E1000_ERR_NVM (-1).
868 **/
869 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
870 {
871 s32 ret_val;
872
873 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
874 if (ret_val)
875 goto out;
876
877 ret_val = igb_acquire_nvm(hw);
878
879 if (ret_val)
880 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
881
882 out:
883 return ret_val;
884 }
885
886 /**
887 * igb_release_nvm_82575 - Release exclusive access to EEPROM
888 * @hw: pointer to the HW structure
889 *
890 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
891 * then release the semaphores acquired.
892 **/
893 static void igb_release_nvm_82575(struct e1000_hw *hw)
894 {
895 igb_release_nvm(hw);
896 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
897 }
898
899 /**
900 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
901 * @hw: pointer to the HW structure
902 * @mask: specifies which semaphore to acquire
903 *
904 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
905 * will also specify which port we're acquiring the lock for.
906 **/
907 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
908 {
909 u32 swfw_sync;
910 u32 swmask = mask;
911 u32 fwmask = mask << 16;
912 s32 ret_val = 0;
913 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
914
915 while (i < timeout) {
916 if (igb_get_hw_semaphore(hw)) {
917 ret_val = -E1000_ERR_SWFW_SYNC;
918 goto out;
919 }
920
921 swfw_sync = rd32(E1000_SW_FW_SYNC);
922 if (!(swfw_sync & (fwmask | swmask)))
923 break;
924
925 /*
926 * Firmware currently using resource (fwmask)
927 * or other software thread using resource (swmask)
928 */
929 igb_put_hw_semaphore(hw);
930 mdelay(5);
931 i++;
932 }
933
934 if (i == timeout) {
935 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
936 ret_val = -E1000_ERR_SWFW_SYNC;
937 goto out;
938 }
939
940 swfw_sync |= swmask;
941 wr32(E1000_SW_FW_SYNC, swfw_sync);
942
943 igb_put_hw_semaphore(hw);
944
945 out:
946 return ret_val;
947 }
948
949 /**
950 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
951 * @hw: pointer to the HW structure
952 * @mask: specifies which semaphore to acquire
953 *
954 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
955 * will also specify which port we're releasing the lock for.
956 **/
957 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
958 {
959 u32 swfw_sync;
960
961 while (igb_get_hw_semaphore(hw) != 0);
962 /* Empty */
963
964 swfw_sync = rd32(E1000_SW_FW_SYNC);
965 swfw_sync &= ~mask;
966 wr32(E1000_SW_FW_SYNC, swfw_sync);
967
968 igb_put_hw_semaphore(hw);
969 }
970
971 /**
972 * igb_get_cfg_done_82575 - Read config done bit
973 * @hw: pointer to the HW structure
974 *
975 * Read the management control register for the config done bit for
976 * completion status. NOTE: silicon which is EEPROM-less will fail trying
977 * to read the config done bit, so an error is *ONLY* logged and returns
978 * 0. If we were to return with error, EEPROM-less silicon
979 * would not be able to be reset or change link.
980 **/
981 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
982 {
983 s32 timeout = PHY_CFG_TIMEOUT;
984 s32 ret_val = 0;
985 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
986
987 if (hw->bus.func == 1)
988 mask = E1000_NVM_CFG_DONE_PORT_1;
989 else if (hw->bus.func == E1000_FUNC_2)
990 mask = E1000_NVM_CFG_DONE_PORT_2;
991 else if (hw->bus.func == E1000_FUNC_3)
992 mask = E1000_NVM_CFG_DONE_PORT_3;
993
994 while (timeout) {
995 if (rd32(E1000_EEMNGCTL) & mask)
996 break;
997 msleep(1);
998 timeout--;
999 }
1000 if (!timeout)
1001 hw_dbg("MNG configuration cycle has not completed.\n");
1002
1003 /* If EEPROM is not marked present, init the PHY manually */
1004 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1005 (hw->phy.type == e1000_phy_igp_3))
1006 igb_phy_init_script_igp3(hw);
1007
1008 return ret_val;
1009 }
1010
1011 /**
1012 * igb_check_for_link_82575 - Check for link
1013 * @hw: pointer to the HW structure
1014 *
1015 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1016 * use the generic interface for determining link.
1017 **/
1018 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1019 {
1020 s32 ret_val;
1021 u16 speed, duplex;
1022
1023 if (hw->phy.media_type != e1000_media_type_copper) {
1024 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1025 &duplex);
1026 /*
1027 * Use this flag to determine if link needs to be checked or
1028 * not. If we have link clear the flag so that we do not
1029 * continue to check for link.
1030 */
1031 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1032 } else {
1033 ret_val = igb_check_for_copper_link(hw);
1034 }
1035
1036 return ret_val;
1037 }
1038
1039 /**
1040 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1041 * @hw: pointer to the HW structure
1042 **/
1043 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1044 {
1045 u32 reg;
1046
1047
1048 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1049 !igb_sgmii_active_82575(hw))
1050 return;
1051
1052 /* Enable PCS to turn on link */
1053 reg = rd32(E1000_PCS_CFG0);
1054 reg |= E1000_PCS_CFG_PCS_EN;
1055 wr32(E1000_PCS_CFG0, reg);
1056
1057 /* Power up the laser */
1058 reg = rd32(E1000_CTRL_EXT);
1059 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1060 wr32(E1000_CTRL_EXT, reg);
1061
1062 /* flush the write to verify completion */
1063 wrfl();
1064 msleep(1);
1065 }
1066
1067 /**
1068 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1069 * @hw: pointer to the HW structure
1070 * @speed: stores the current speed
1071 * @duplex: stores the current duplex
1072 *
1073 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1074 * duplex, then store the values in the pointers provided.
1075 **/
1076 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1077 u16 *duplex)
1078 {
1079 struct e1000_mac_info *mac = &hw->mac;
1080 u32 pcs;
1081
1082 /* Set up defaults for the return values of this function */
1083 mac->serdes_has_link = false;
1084 *speed = 0;
1085 *duplex = 0;
1086
1087 /*
1088 * Read the PCS Status register for link state. For non-copper mode,
1089 * the status register is not accurate. The PCS status register is
1090 * used instead.
1091 */
1092 pcs = rd32(E1000_PCS_LSTAT);
1093
1094 /*
1095 * The link up bit determines when link is up on autoneg. The sync ok
1096 * gets set once both sides sync up and agree upon link. Stable link
1097 * can be determined by checking for both link up and link sync ok
1098 */
1099 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1100 mac->serdes_has_link = true;
1101
1102 /* Detect and store PCS speed */
1103 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1104 *speed = SPEED_1000;
1105 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1106 *speed = SPEED_100;
1107 } else {
1108 *speed = SPEED_10;
1109 }
1110
1111 /* Detect and store PCS duplex */
1112 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1113 *duplex = FULL_DUPLEX;
1114 } else {
1115 *duplex = HALF_DUPLEX;
1116 }
1117 }
1118
1119 return 0;
1120 }
1121
1122 /**
1123 * igb_shutdown_serdes_link_82575 - Remove link during power down
1124 * @hw: pointer to the HW structure
1125 *
1126 * In the case of fiber serdes, shut down optics and PCS on driver unload
1127 * when management pass thru is not enabled.
1128 **/
1129 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1130 {
1131 u32 reg;
1132
1133 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1134 igb_sgmii_active_82575(hw))
1135 return;
1136
1137 if (!igb_enable_mng_pass_thru(hw)) {
1138 /* Disable PCS to turn off link */
1139 reg = rd32(E1000_PCS_CFG0);
1140 reg &= ~E1000_PCS_CFG_PCS_EN;
1141 wr32(E1000_PCS_CFG0, reg);
1142
1143 /* shutdown the laser */
1144 reg = rd32(E1000_CTRL_EXT);
1145 reg |= E1000_CTRL_EXT_SDP3_DATA;
1146 wr32(E1000_CTRL_EXT, reg);
1147
1148 /* flush the write to verify completion */
1149 wrfl();
1150 msleep(1);
1151 }
1152 }
1153
1154 /**
1155 * igb_reset_hw_82575 - Reset hardware
1156 * @hw: pointer to the HW structure
1157 *
1158 * This resets the hardware into a known state. This is a
1159 * function pointer entry point called by the api module.
1160 **/
1161 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1162 {
1163 u32 ctrl, icr;
1164 s32 ret_val;
1165
1166 /*
1167 * Prevent the PCI-E bus from sticking if there is no TLP connection
1168 * on the last TLP read/write transaction when MAC is reset.
1169 */
1170 ret_val = igb_disable_pcie_master(hw);
1171 if (ret_val)
1172 hw_dbg("PCI-E Master disable polling has failed.\n");
1173
1174 /* set the completion timeout for interface */
1175 ret_val = igb_set_pcie_completion_timeout(hw);
1176 if (ret_val) {
1177 hw_dbg("PCI-E Set completion timeout has failed.\n");
1178 }
1179
1180 hw_dbg("Masking off all interrupts\n");
1181 wr32(E1000_IMC, 0xffffffff);
1182
1183 wr32(E1000_RCTL, 0);
1184 wr32(E1000_TCTL, E1000_TCTL_PSP);
1185 wrfl();
1186
1187 msleep(10);
1188
1189 ctrl = rd32(E1000_CTRL);
1190
1191 hw_dbg("Issuing a global reset to MAC\n");
1192 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1193
1194 ret_val = igb_get_auto_rd_done(hw);
1195 if (ret_val) {
1196 /*
1197 * When auto config read does not complete, do not
1198 * return with an error. This can happen in situations
1199 * where there is no eeprom and prevents getting link.
1200 */
1201 hw_dbg("Auto Read Done did not complete\n");
1202 }
1203
1204 /* If EEPROM is not present, run manual init scripts */
1205 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1206 igb_reset_init_script_82575(hw);
1207
1208 /* Clear any pending interrupt events. */
1209 wr32(E1000_IMC, 0xffffffff);
1210 icr = rd32(E1000_ICR);
1211
1212 /* Install any alternate MAC address into RAR0 */
1213 ret_val = igb_check_alt_mac_addr(hw);
1214
1215 return ret_val;
1216 }
1217
1218 /**
1219 * igb_init_hw_82575 - Initialize hardware
1220 * @hw: pointer to the HW structure
1221 *
1222 * This inits the hardware readying it for operation.
1223 **/
1224 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1225 {
1226 struct e1000_mac_info *mac = &hw->mac;
1227 s32 ret_val;
1228 u16 i, rar_count = mac->rar_entry_count;
1229
1230 /* Initialize identification LED */
1231 ret_val = igb_id_led_init(hw);
1232 if (ret_val) {
1233 hw_dbg("Error initializing identification LED\n");
1234 /* This is not fatal and we should not stop init due to this */
1235 }
1236
1237 /* Disabling VLAN filtering */
1238 hw_dbg("Initializing the IEEE VLAN\n");
1239 if (hw->mac.type == e1000_i350)
1240 igb_clear_vfta_i350(hw);
1241 else
1242 igb_clear_vfta(hw);
1243
1244 /* Setup the receive address */
1245 igb_init_rx_addrs(hw, rar_count);
1246
1247 /* Zero out the Multicast HASH table */
1248 hw_dbg("Zeroing the MTA\n");
1249 for (i = 0; i < mac->mta_reg_count; i++)
1250 array_wr32(E1000_MTA, i, 0);
1251
1252 /* Zero out the Unicast HASH table */
1253 hw_dbg("Zeroing the UTA\n");
1254 for (i = 0; i < mac->uta_reg_count; i++)
1255 array_wr32(E1000_UTA, i, 0);
1256
1257 /* Setup link and flow control */
1258 ret_val = igb_setup_link(hw);
1259
1260 /*
1261 * Clear all of the statistics registers (clear on read). It is
1262 * important that we do this after we have tried to establish link
1263 * because the symbol error count will increment wildly if there
1264 * is no link.
1265 */
1266 igb_clear_hw_cntrs_82575(hw);
1267 return ret_val;
1268 }
1269
1270 /**
1271 * igb_setup_copper_link_82575 - Configure copper link settings
1272 * @hw: pointer to the HW structure
1273 *
1274 * Configures the link for auto-neg or forced speed and duplex. Then we check
1275 * for link, once link is established calls to configure collision distance
1276 * and flow control are called.
1277 **/
1278 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1279 {
1280 u32 ctrl;
1281 s32 ret_val;
1282
1283 ctrl = rd32(E1000_CTRL);
1284 ctrl |= E1000_CTRL_SLU;
1285 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1286 wr32(E1000_CTRL, ctrl);
1287
1288 ret_val = igb_setup_serdes_link_82575(hw);
1289 if (ret_val)
1290 goto out;
1291
1292 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1293 /* allow time for SFP cage time to power up phy */
1294 msleep(300);
1295
1296 ret_val = hw->phy.ops.reset(hw);
1297 if (ret_val) {
1298 hw_dbg("Error resetting the PHY.\n");
1299 goto out;
1300 }
1301 }
1302 switch (hw->phy.type) {
1303 case e1000_phy_i210:
1304 case e1000_phy_m88:
1305 if (hw->phy.id == I347AT4_E_PHY_ID ||
1306 hw->phy.id == M88E1112_E_PHY_ID)
1307 ret_val = igb_copper_link_setup_m88_gen2(hw);
1308 else
1309 ret_val = igb_copper_link_setup_m88(hw);
1310 break;
1311 case e1000_phy_igp_3:
1312 ret_val = igb_copper_link_setup_igp(hw);
1313 break;
1314 case e1000_phy_82580:
1315 ret_val = igb_copper_link_setup_82580(hw);
1316 break;
1317 default:
1318 ret_val = -E1000_ERR_PHY;
1319 break;
1320 }
1321
1322 if (ret_val)
1323 goto out;
1324
1325 ret_val = igb_setup_copper_link(hw);
1326 out:
1327 return ret_val;
1328 }
1329
1330 /**
1331 * igb_setup_serdes_link_82575 - Setup link for serdes
1332 * @hw: pointer to the HW structure
1333 *
1334 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1335 * used on copper connections where the serialized gigabit media independent
1336 * interface (sgmii), or serdes fiber is being used. Configures the link
1337 * for auto-negotiation or forces speed/duplex.
1338 **/
1339 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1340 {
1341 u32 ctrl_ext, ctrl_reg, reg;
1342 bool pcs_autoneg;
1343 s32 ret_val = E1000_SUCCESS;
1344 u16 data;
1345
1346 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1347 !igb_sgmii_active_82575(hw))
1348 return ret_val;
1349
1350
1351 /*
1352 * On the 82575, SerDes loopback mode persists until it is
1353 * explicitly turned off or a power cycle is performed. A read to
1354 * the register does not indicate its status. Therefore, we ensure
1355 * loopback mode is disabled during initialization.
1356 */
1357 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1358
1359 /* power on the sfp cage if present */
1360 ctrl_ext = rd32(E1000_CTRL_EXT);
1361 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1362 wr32(E1000_CTRL_EXT, ctrl_ext);
1363
1364 ctrl_reg = rd32(E1000_CTRL);
1365 ctrl_reg |= E1000_CTRL_SLU;
1366
1367 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1368 /* set both sw defined pins */
1369 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1370
1371 /* Set switch control to serdes energy detect */
1372 reg = rd32(E1000_CONNSW);
1373 reg |= E1000_CONNSW_ENRGSRC;
1374 wr32(E1000_CONNSW, reg);
1375 }
1376
1377 reg = rd32(E1000_PCS_LCTL);
1378
1379 /* default pcs_autoneg to the same setting as mac autoneg */
1380 pcs_autoneg = hw->mac.autoneg;
1381
1382 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1383 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1384 /* sgmii mode lets the phy handle forcing speed/duplex */
1385 pcs_autoneg = true;
1386 /* autoneg time out should be disabled for SGMII mode */
1387 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1388 break;
1389 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1390 /* disable PCS autoneg and support parallel detect only */
1391 pcs_autoneg = false;
1392 default:
1393 if (hw->mac.type == e1000_82575 ||
1394 hw->mac.type == e1000_82576) {
1395 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1396 if (ret_val) {
1397 printk(KERN_DEBUG "NVM Read Error\n\n");
1398 return ret_val;
1399 }
1400
1401 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1402 pcs_autoneg = false;
1403 }
1404
1405 /*
1406 * non-SGMII modes only supports a speed of 1000/Full for the
1407 * link so it is best to just force the MAC and let the pcs
1408 * link either autoneg or be forced to 1000/Full
1409 */
1410 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1411 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1412
1413 /* set speed of 1000/Full if speed/duplex is forced */
1414 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1415 break;
1416 }
1417
1418 wr32(E1000_CTRL, ctrl_reg);
1419
1420 /*
1421 * New SerDes mode allows for forcing speed or autonegotiating speed
1422 * at 1gb. Autoneg should be default set by most drivers. This is the
1423 * mode that will be compatible with older link partners and switches.
1424 * However, both are supported by the hardware and some drivers/tools.
1425 */
1426 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1427 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1428
1429 /*
1430 * We force flow control to prevent the CTRL register values from being
1431 * overwritten by the autonegotiated flow control values
1432 */
1433 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1434
1435 if (pcs_autoneg) {
1436 /* Set PCS register for autoneg */
1437 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1438 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1439 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1440 } else {
1441 /* Set PCS register for forced link */
1442 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1443
1444 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1445 }
1446
1447 wr32(E1000_PCS_LCTL, reg);
1448
1449 if (!igb_sgmii_active_82575(hw))
1450 igb_force_mac_fc(hw);
1451
1452 return ret_val;
1453 }
1454
1455 /**
1456 * igb_sgmii_active_82575 - Return sgmii state
1457 * @hw: pointer to the HW structure
1458 *
1459 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1460 * which can be enabled for use in the embedded applications. Simply
1461 * return the current state of the sgmii interface.
1462 **/
1463 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1464 {
1465 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1466 return dev_spec->sgmii_active;
1467 }
1468
1469 /**
1470 * igb_reset_init_script_82575 - Inits HW defaults after reset
1471 * @hw: pointer to the HW structure
1472 *
1473 * Inits recommended HW defaults after a reset when there is no EEPROM
1474 * detected. This is only for the 82575.
1475 **/
1476 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1477 {
1478 if (hw->mac.type == e1000_82575) {
1479 hw_dbg("Running reset init script for 82575\n");
1480 /* SerDes configuration via SERDESCTRL */
1481 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1482 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1483 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1484 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1485
1486 /* CCM configuration via CCMCTL register */
1487 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1488 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1489
1490 /* PCIe lanes configuration */
1491 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1492 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1493 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1494 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1495
1496 /* PCIe PLL Configuration */
1497 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1498 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1499 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1500 }
1501
1502 return 0;
1503 }
1504
1505 /**
1506 * igb_read_mac_addr_82575 - Read device MAC address
1507 * @hw: pointer to the HW structure
1508 **/
1509 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1510 {
1511 s32 ret_val = 0;
1512
1513 /*
1514 * If there's an alternate MAC address place it in RAR0
1515 * so that it will override the Si installed default perm
1516 * address.
1517 */
1518 ret_val = igb_check_alt_mac_addr(hw);
1519 if (ret_val)
1520 goto out;
1521
1522 ret_val = igb_read_mac_addr(hw);
1523
1524 out:
1525 return ret_val;
1526 }
1527
1528 /**
1529 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1530 * @hw: pointer to the HW structure
1531 *
1532 * In the case of a PHY power down to save power, or to turn off link during a
1533 * driver unload, or wake on lan is not enabled, remove the link.
1534 **/
1535 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1536 {
1537 /* If the management interface is not enabled, then power down */
1538 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1539 igb_power_down_phy_copper(hw);
1540 }
1541
1542 /**
1543 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1544 * @hw: pointer to the HW structure
1545 *
1546 * Clears the hardware counters by reading the counter registers.
1547 **/
1548 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1549 {
1550 igb_clear_hw_cntrs_base(hw);
1551
1552 rd32(E1000_PRC64);
1553 rd32(E1000_PRC127);
1554 rd32(E1000_PRC255);
1555 rd32(E1000_PRC511);
1556 rd32(E1000_PRC1023);
1557 rd32(E1000_PRC1522);
1558 rd32(E1000_PTC64);
1559 rd32(E1000_PTC127);
1560 rd32(E1000_PTC255);
1561 rd32(E1000_PTC511);
1562 rd32(E1000_PTC1023);
1563 rd32(E1000_PTC1522);
1564
1565 rd32(E1000_ALGNERRC);
1566 rd32(E1000_RXERRC);
1567 rd32(E1000_TNCRS);
1568 rd32(E1000_CEXTERR);
1569 rd32(E1000_TSCTC);
1570 rd32(E1000_TSCTFC);
1571
1572 rd32(E1000_MGTPRC);
1573 rd32(E1000_MGTPDC);
1574 rd32(E1000_MGTPTC);
1575
1576 rd32(E1000_IAC);
1577 rd32(E1000_ICRXOC);
1578
1579 rd32(E1000_ICRXPTC);
1580 rd32(E1000_ICRXATC);
1581 rd32(E1000_ICTXPTC);
1582 rd32(E1000_ICTXATC);
1583 rd32(E1000_ICTXQEC);
1584 rd32(E1000_ICTXQMTC);
1585 rd32(E1000_ICRXDMTC);
1586
1587 rd32(E1000_CBTMPC);
1588 rd32(E1000_HTDPMC);
1589 rd32(E1000_CBRMPC);
1590 rd32(E1000_RPTHC);
1591 rd32(E1000_HGPTC);
1592 rd32(E1000_HTCBDPC);
1593 rd32(E1000_HGORCL);
1594 rd32(E1000_HGORCH);
1595 rd32(E1000_HGOTCL);
1596 rd32(E1000_HGOTCH);
1597 rd32(E1000_LENERRS);
1598
1599 /* This register should not be read in copper configurations */
1600 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1601 igb_sgmii_active_82575(hw))
1602 rd32(E1000_SCVPC);
1603 }
1604
1605 /**
1606 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1607 * @hw: pointer to the HW structure
1608 *
1609 * After rx enable if managability is enabled then there is likely some
1610 * bad data at the start of the fifo and possibly in the DMA fifo. This
1611 * function clears the fifos and flushes any packets that came in as rx was
1612 * being enabled.
1613 **/
1614 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1615 {
1616 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1617 int i, ms_wait;
1618
1619 if (hw->mac.type != e1000_82575 ||
1620 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1621 return;
1622
1623 /* Disable all RX queues */
1624 for (i = 0; i < 4; i++) {
1625 rxdctl[i] = rd32(E1000_RXDCTL(i));
1626 wr32(E1000_RXDCTL(i),
1627 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1628 }
1629 /* Poll all queues to verify they have shut down */
1630 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1631 msleep(1);
1632 rx_enabled = 0;
1633 for (i = 0; i < 4; i++)
1634 rx_enabled |= rd32(E1000_RXDCTL(i));
1635 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1636 break;
1637 }
1638
1639 if (ms_wait == 10)
1640 hw_dbg("Queue disable timed out after 10ms\n");
1641
1642 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1643 * incoming packets are rejected. Set enable and wait 2ms so that
1644 * any packet that was coming in as RCTL.EN was set is flushed
1645 */
1646 rfctl = rd32(E1000_RFCTL);
1647 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1648
1649 rlpml = rd32(E1000_RLPML);
1650 wr32(E1000_RLPML, 0);
1651
1652 rctl = rd32(E1000_RCTL);
1653 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1654 temp_rctl |= E1000_RCTL_LPE;
1655
1656 wr32(E1000_RCTL, temp_rctl);
1657 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1658 wrfl();
1659 msleep(2);
1660
1661 /* Enable RX queues that were previously enabled and restore our
1662 * previous state
1663 */
1664 for (i = 0; i < 4; i++)
1665 wr32(E1000_RXDCTL(i), rxdctl[i]);
1666 wr32(E1000_RCTL, rctl);
1667 wrfl();
1668
1669 wr32(E1000_RLPML, rlpml);
1670 wr32(E1000_RFCTL, rfctl);
1671
1672 /* Flush receive errors generated by workaround */
1673 rd32(E1000_ROC);
1674 rd32(E1000_RNBC);
1675 rd32(E1000_MPC);
1676 }
1677
1678 /**
1679 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1680 * @hw: pointer to the HW structure
1681 *
1682 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1683 * however the hardware default for these parts is 500us to 1ms which is less
1684 * than the 10ms recommended by the pci-e spec. To address this we need to
1685 * increase the value to either 10ms to 200ms for capability version 1 config,
1686 * or 16ms to 55ms for version 2.
1687 **/
1688 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1689 {
1690 u32 gcr = rd32(E1000_GCR);
1691 s32 ret_val = 0;
1692 u16 pcie_devctl2;
1693
1694 /* only take action if timeout value is defaulted to 0 */
1695 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1696 goto out;
1697
1698 /*
1699 * if capababilities version is type 1 we can write the
1700 * timeout of 10ms to 200ms through the GCR register
1701 */
1702 if (!(gcr & E1000_GCR_CAP_VER2)) {
1703 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1704 goto out;
1705 }
1706
1707 /*
1708 * for version 2 capabilities we need to write the config space
1709 * directly in order to set the completion timeout value for
1710 * 16ms to 55ms
1711 */
1712 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1713 &pcie_devctl2);
1714 if (ret_val)
1715 goto out;
1716
1717 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1718
1719 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1720 &pcie_devctl2);
1721 out:
1722 /* disable completion timeout resend */
1723 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1724
1725 wr32(E1000_GCR, gcr);
1726 return ret_val;
1727 }
1728
1729 /**
1730 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1731 * @hw: pointer to the hardware struct
1732 * @enable: state to enter, either enabled or disabled
1733 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1734 *
1735 * enables/disables L2 switch anti-spoofing functionality.
1736 **/
1737 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1738 {
1739 u32 dtxswc;
1740
1741 switch (hw->mac.type) {
1742 case e1000_82576:
1743 case e1000_i350:
1744 dtxswc = rd32(E1000_DTXSWC);
1745 if (enable) {
1746 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1747 E1000_DTXSWC_VLAN_SPOOF_MASK);
1748 /* The PF can spoof - it has to in order to
1749 * support emulation mode NICs */
1750 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1751 } else {
1752 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1753 E1000_DTXSWC_VLAN_SPOOF_MASK);
1754 }
1755 wr32(E1000_DTXSWC, dtxswc);
1756 break;
1757 default:
1758 break;
1759 }
1760 }
1761
1762 /**
1763 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1764 * @hw: pointer to the hardware struct
1765 * @enable: state to enter, either enabled or disabled
1766 *
1767 * enables/disables L2 switch loopback functionality.
1768 **/
1769 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1770 {
1771 u32 dtxswc;
1772
1773 switch (hw->mac.type) {
1774 case e1000_82576:
1775 dtxswc = rd32(E1000_DTXSWC);
1776 if (enable)
1777 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1778 else
1779 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1780 wr32(E1000_DTXSWC, dtxswc);
1781 break;
1782 case e1000_i350:
1783 dtxswc = rd32(E1000_TXSWC);
1784 if (enable)
1785 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1786 else
1787 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1788 wr32(E1000_TXSWC, dtxswc);
1789 break;
1790 default:
1791 /* Currently no other hardware supports loopback */
1792 break;
1793 }
1794
1795
1796 }
1797
1798 /**
1799 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1800 * @hw: pointer to the hardware struct
1801 * @enable: state to enter, either enabled or disabled
1802 *
1803 * enables/disables replication of packets across multiple pools.
1804 **/
1805 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1806 {
1807 u32 vt_ctl = rd32(E1000_VT_CTL);
1808
1809 if (enable)
1810 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1811 else
1812 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1813
1814 wr32(E1000_VT_CTL, vt_ctl);
1815 }
1816
1817 /**
1818 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1819 * @hw: pointer to the HW structure
1820 * @offset: register offset to be read
1821 * @data: pointer to the read data
1822 *
1823 * Reads the MDI control register in the PHY at offset and stores the
1824 * information read to data.
1825 **/
1826 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1827 {
1828 s32 ret_val;
1829
1830
1831 ret_val = hw->phy.ops.acquire(hw);
1832 if (ret_val)
1833 goto out;
1834
1835 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1836
1837 hw->phy.ops.release(hw);
1838
1839 out:
1840 return ret_val;
1841 }
1842
1843 /**
1844 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1845 * @hw: pointer to the HW structure
1846 * @offset: register offset to write to
1847 * @data: data to write to register at offset
1848 *
1849 * Writes data to MDI control register in the PHY at offset.
1850 **/
1851 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1852 {
1853 s32 ret_val;
1854
1855
1856 ret_val = hw->phy.ops.acquire(hw);
1857 if (ret_val)
1858 goto out;
1859
1860 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1861
1862 hw->phy.ops.release(hw);
1863
1864 out:
1865 return ret_val;
1866 }
1867
1868 /**
1869 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1870 * @hw: pointer to the HW structure
1871 *
1872 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1873 * the values found in the EEPROM. This addresses an issue in which these
1874 * bits are not restored from EEPROM after reset.
1875 **/
1876 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1877 {
1878 s32 ret_val = 0;
1879 u32 mdicnfg;
1880 u16 nvm_data = 0;
1881
1882 if (hw->mac.type != e1000_82580)
1883 goto out;
1884 if (!igb_sgmii_active_82575(hw))
1885 goto out;
1886
1887 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1888 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1889 &nvm_data);
1890 if (ret_val) {
1891 hw_dbg("NVM Read Error\n");
1892 goto out;
1893 }
1894
1895 mdicnfg = rd32(E1000_MDICNFG);
1896 if (nvm_data & NVM_WORD24_EXT_MDIO)
1897 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1898 if (nvm_data & NVM_WORD24_COM_MDIO)
1899 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1900 wr32(E1000_MDICNFG, mdicnfg);
1901 out:
1902 return ret_val;
1903 }
1904
1905 /**
1906 * igb_reset_hw_82580 - Reset hardware
1907 * @hw: pointer to the HW structure
1908 *
1909 * This resets function or entire device (all ports, etc.)
1910 * to a known state.
1911 **/
1912 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1913 {
1914 s32 ret_val = 0;
1915 /* BH SW mailbox bit in SW_FW_SYNC */
1916 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1917 u32 ctrl, icr;
1918 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1919
1920
1921 hw->dev_spec._82575.global_device_reset = false;
1922
1923 /* Get current control state. */
1924 ctrl = rd32(E1000_CTRL);
1925
1926 /*
1927 * Prevent the PCI-E bus from sticking if there is no TLP connection
1928 * on the last TLP read/write transaction when MAC is reset.
1929 */
1930 ret_val = igb_disable_pcie_master(hw);
1931 if (ret_val)
1932 hw_dbg("PCI-E Master disable polling has failed.\n");
1933
1934 hw_dbg("Masking off all interrupts\n");
1935 wr32(E1000_IMC, 0xffffffff);
1936 wr32(E1000_RCTL, 0);
1937 wr32(E1000_TCTL, E1000_TCTL_PSP);
1938 wrfl();
1939
1940 msleep(10);
1941
1942 /* Determine whether or not a global dev reset is requested */
1943 if (global_device_reset &&
1944 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
1945 global_device_reset = false;
1946
1947 if (global_device_reset &&
1948 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1949 ctrl |= E1000_CTRL_DEV_RST;
1950 else
1951 ctrl |= E1000_CTRL_RST;
1952
1953 wr32(E1000_CTRL, ctrl);
1954 wrfl();
1955
1956 /* Add delay to insure DEV_RST has time to complete */
1957 if (global_device_reset)
1958 msleep(5);
1959
1960 ret_val = igb_get_auto_rd_done(hw);
1961 if (ret_val) {
1962 /*
1963 * When auto config read does not complete, do not
1964 * return with an error. This can happen in situations
1965 * where there is no eeprom and prevents getting link.
1966 */
1967 hw_dbg("Auto Read Done did not complete\n");
1968 }
1969
1970 /* If EEPROM is not present, run manual init scripts */
1971 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1972 igb_reset_init_script_82575(hw);
1973
1974 /* clear global device reset status bit */
1975 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1976
1977 /* Clear any pending interrupt events. */
1978 wr32(E1000_IMC, 0xffffffff);
1979 icr = rd32(E1000_ICR);
1980
1981 ret_val = igb_reset_mdicnfg_82580(hw);
1982 if (ret_val)
1983 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
1984
1985 /* Install any alternate MAC address into RAR0 */
1986 ret_val = igb_check_alt_mac_addr(hw);
1987
1988 /* Release semaphore */
1989 if (global_device_reset)
1990 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
1991
1992 return ret_val;
1993 }
1994
1995 /**
1996 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1997 * @data: data received by reading RXPBS register
1998 *
1999 * The 82580 uses a table based approach for packet buffer allocation sizes.
2000 * This function converts the retrieved value into the correct table value
2001 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2002 * 0x0 36 72 144 1 2 4 8 16
2003 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2004 */
2005 u16 igb_rxpbs_adjust_82580(u32 data)
2006 {
2007 u16 ret_val = 0;
2008
2009 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2010 ret_val = e1000_82580_rxpbs_table[data];
2011
2012 return ret_val;
2013 }
2014
2015 /**
2016 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2017 * checksum
2018 * @hw: pointer to the HW structure
2019 * @offset: offset in words of the checksum protected region
2020 *
2021 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2022 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2023 **/
2024 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2025 u16 offset)
2026 {
2027 s32 ret_val = 0;
2028 u16 checksum = 0;
2029 u16 i, nvm_data;
2030
2031 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2032 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2033 if (ret_val) {
2034 hw_dbg("NVM Read Error\n");
2035 goto out;
2036 }
2037 checksum += nvm_data;
2038 }
2039
2040 if (checksum != (u16) NVM_SUM) {
2041 hw_dbg("NVM Checksum Invalid\n");
2042 ret_val = -E1000_ERR_NVM;
2043 goto out;
2044 }
2045
2046 out:
2047 return ret_val;
2048 }
2049
2050 /**
2051 * igb_update_nvm_checksum_with_offset - Update EEPROM
2052 * checksum
2053 * @hw: pointer to the HW structure
2054 * @offset: offset in words of the checksum protected region
2055 *
2056 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2057 * up to the checksum. Then calculates the EEPROM checksum and writes the
2058 * value to the EEPROM.
2059 **/
2060 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2061 {
2062 s32 ret_val;
2063 u16 checksum = 0;
2064 u16 i, nvm_data;
2065
2066 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2067 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2068 if (ret_val) {
2069 hw_dbg("NVM Read Error while updating checksum.\n");
2070 goto out;
2071 }
2072 checksum += nvm_data;
2073 }
2074 checksum = (u16) NVM_SUM - checksum;
2075 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2076 &checksum);
2077 if (ret_val)
2078 hw_dbg("NVM Write Error while updating checksum.\n");
2079
2080 out:
2081 return ret_val;
2082 }
2083
2084 /**
2085 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2086 * @hw: pointer to the HW structure
2087 *
2088 * Calculates the EEPROM section checksum by reading/adding each word of
2089 * the EEPROM and then verifies that the sum of the EEPROM is
2090 * equal to 0xBABA.
2091 **/
2092 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2093 {
2094 s32 ret_val = 0;
2095 u16 eeprom_regions_count = 1;
2096 u16 j, nvm_data;
2097 u16 nvm_offset;
2098
2099 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2100 if (ret_val) {
2101 hw_dbg("NVM Read Error\n");
2102 goto out;
2103 }
2104
2105 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2106 /* if checksums compatibility bit is set validate checksums
2107 * for all 4 ports. */
2108 eeprom_regions_count = 4;
2109 }
2110
2111 for (j = 0; j < eeprom_regions_count; j++) {
2112 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2113 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2114 nvm_offset);
2115 if (ret_val != 0)
2116 goto out;
2117 }
2118
2119 out:
2120 return ret_val;
2121 }
2122
2123 /**
2124 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2125 * @hw: pointer to the HW structure
2126 *
2127 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2128 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2129 * checksum and writes the value to the EEPROM.
2130 **/
2131 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2132 {
2133 s32 ret_val;
2134 u16 j, nvm_data;
2135 u16 nvm_offset;
2136
2137 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2138 if (ret_val) {
2139 hw_dbg("NVM Read Error while updating checksum"
2140 " compatibility bit.\n");
2141 goto out;
2142 }
2143
2144 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2145 /* set compatibility bit to validate checksums appropriately */
2146 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2147 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2148 &nvm_data);
2149 if (ret_val) {
2150 hw_dbg("NVM Write Error while updating checksum"
2151 " compatibility bit.\n");
2152 goto out;
2153 }
2154 }
2155
2156 for (j = 0; j < 4; j++) {
2157 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2158 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2159 if (ret_val)
2160 goto out;
2161 }
2162
2163 out:
2164 return ret_val;
2165 }
2166
2167 /**
2168 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2169 * @hw: pointer to the HW structure
2170 *
2171 * Calculates the EEPROM section checksum by reading/adding each word of
2172 * the EEPROM and then verifies that the sum of the EEPROM is
2173 * equal to 0xBABA.
2174 **/
2175 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2176 {
2177 s32 ret_val = 0;
2178 u16 j;
2179 u16 nvm_offset;
2180
2181 for (j = 0; j < 4; j++) {
2182 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2183 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2184 nvm_offset);
2185 if (ret_val != 0)
2186 goto out;
2187 }
2188
2189 out:
2190 return ret_val;
2191 }
2192
2193 /**
2194 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2195 * @hw: pointer to the HW structure
2196 *
2197 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2198 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2199 * checksum and writes the value to the EEPROM.
2200 **/
2201 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2202 {
2203 s32 ret_val = 0;
2204 u16 j;
2205 u16 nvm_offset;
2206
2207 for (j = 0; j < 4; j++) {
2208 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2209 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2210 if (ret_val != 0)
2211 goto out;
2212 }
2213
2214 out:
2215 return ret_val;
2216 }
2217
2218 /**
2219 * igb_set_eee_i350 - Enable/disable EEE support
2220 * @hw: pointer to the HW structure
2221 *
2222 * Enable/disable EEE based on setting in dev_spec structure.
2223 *
2224 **/
2225 s32 igb_set_eee_i350(struct e1000_hw *hw)
2226 {
2227 s32 ret_val = 0;
2228 u32 ipcnfg, eeer, ctrl_ext;
2229
2230 ctrl_ext = rd32(E1000_CTRL_EXT);
2231 if ((hw->mac.type != e1000_i350) ||
2232 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2233 goto out;
2234 ipcnfg = rd32(E1000_IPCNFG);
2235 eeer = rd32(E1000_EEER);
2236
2237 /* enable or disable per user setting */
2238 if (!(hw->dev_spec._82575.eee_disable)) {
2239 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
2240 E1000_IPCNFG_EEE_100M_AN);
2241 eeer |= (E1000_EEER_TX_LPI_EN |
2242 E1000_EEER_RX_LPI_EN |
2243 E1000_EEER_LPI_FC);
2244
2245 } else {
2246 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2247 E1000_IPCNFG_EEE_100M_AN);
2248 eeer &= ~(E1000_EEER_TX_LPI_EN |
2249 E1000_EEER_RX_LPI_EN |
2250 E1000_EEER_LPI_FC);
2251 }
2252 wr32(E1000_IPCNFG, ipcnfg);
2253 wr32(E1000_EEER, eeer);
2254 out:
2255
2256 return ret_val;
2257 }
2258
2259 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2260 .init_hw = igb_init_hw_82575,
2261 .check_for_link = igb_check_for_link_82575,
2262 .rar_set = igb_rar_set,
2263 .read_mac_addr = igb_read_mac_addr_82575,
2264 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
2265 };
2266
2267 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2268 .acquire = igb_acquire_phy_82575,
2269 .get_cfg_done = igb_get_cfg_done_82575,
2270 .release = igb_release_phy_82575,
2271 };
2272
2273 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2274 .acquire = igb_acquire_nvm_82575,
2275 .read = igb_read_nvm_eerd,
2276 .release = igb_release_nvm_82575,
2277 .write = igb_write_nvm_spi,
2278 };
2279
2280 const struct e1000_info e1000_82575_info = {
2281 .get_invariants = igb_get_invariants_82575,
2282 .mac_ops = &e1000_mac_ops_82575,
2283 .phy_ops = &e1000_phy_ops_82575,
2284 .nvm_ops = &e1000_nvm_ops_82575,
2285 };
2286
Linux kernel - Deliverables
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