1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
42 static s32
igb_get_invariants_82575(struct e1000_hw
*);
43 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
44 static void igb_release_phy_82575(struct e1000_hw
*);
45 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
46 static void igb_release_nvm_82575(struct e1000_hw
*);
47 static s32
igb_check_for_link_82575(struct e1000_hw
*);
48 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
49 static s32
igb_init_hw_82575(struct e1000_hw
*);
50 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
51 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
52 static s32
igb_read_phy_reg_82580(struct e1000_hw
*, u32
, u16
*);
53 static s32
igb_write_phy_reg_82580(struct e1000_hw
*, u32
, u16
);
54 static s32
igb_reset_hw_82575(struct e1000_hw
*);
55 static s32
igb_reset_hw_82580(struct e1000_hw
*);
56 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
57 static s32
igb_set_d0_lplu_state_82580(struct e1000_hw
*, bool);
58 static s32
igb_set_d3_lplu_state_82580(struct e1000_hw
*, bool);
59 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
60 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*);
61 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
63 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
64 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
66 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
67 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
68 static bool igb_sgmii_active_82575(struct e1000_hw
*);
69 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
70 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
71 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
);
72 static s32
igb_reset_mdicnfg_82580(struct e1000_hw
*hw
);
73 static s32
igb_validate_nvm_checksum_82580(struct e1000_hw
*hw
);
74 static s32
igb_update_nvm_checksum_82580(struct e1000_hw
*hw
);
75 static s32
igb_validate_nvm_checksum_i350(struct e1000_hw
*hw
);
76 static s32
igb_update_nvm_checksum_i350(struct e1000_hw
*hw
);
77 static const u16 e1000_82580_rxpbs_table
[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw
*hw
)
93 bool ext_mdio
= false;
95 switch (hw
->mac
.type
) {
98 reg
= rd32(E1000_MDIC
);
99 ext_mdio
= !!(reg
& E1000_MDIC_DEST
);
106 reg
= rd32(E1000_MDICNFG
);
107 ext_mdio
= !!(reg
& E1000_MDICNFG_EXT_MDIO
);
116 * igb_init_phy_params_82575 - Init PHY func ptrs.
117 * @hw: pointer to the HW structure
119 static s32
igb_init_phy_params_82575(struct e1000_hw
*hw
)
121 struct e1000_phy_info
*phy
= &hw
->phy
;
125 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
126 phy
->type
= e1000_phy_none
;
130 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
131 phy
->reset_delay_us
= 100;
133 ctrl_ext
= rd32(E1000_CTRL_EXT
);
135 if (igb_sgmii_active_82575(hw
)) {
136 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
137 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
139 phy
->ops
.reset
= igb_phy_hw_reset
;
140 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
143 wr32(E1000_CTRL_EXT
, ctrl_ext
);
144 igb_reset_mdicnfg_82580(hw
);
146 if (igb_sgmii_active_82575(hw
) && !igb_sgmii_uses_mdio_82575(hw
)) {
147 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
148 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
150 switch (hw
->mac
.type
) {
154 phy
->ops
.read_reg
= igb_read_phy_reg_82580
;
155 phy
->ops
.write_reg
= igb_write_phy_reg_82580
;
159 phy
->ops
.read_reg
= igb_read_phy_reg_gs40g
;
160 phy
->ops
.write_reg
= igb_write_phy_reg_gs40g
;
163 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
164 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
169 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
170 E1000_STATUS_FUNC_SHIFT
;
172 /* Set phy->phy_addr and phy->id. */
173 ret_val
= igb_get_phy_id_82575(hw
);
177 /* Verify phy id and set remaining function pointers */
179 case M88E1545_E_PHY_ID
:
180 case I347AT4_E_PHY_ID
:
181 case M88E1112_E_PHY_ID
:
182 case M88E1111_I_PHY_ID
:
183 phy
->type
= e1000_phy_m88
;
184 phy
->ops
.check_polarity
= igb_check_polarity_m88
;
185 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
186 if (phy
->id
!= M88E1111_I_PHY_ID
)
187 phy
->ops
.get_cable_length
=
188 igb_get_cable_length_m88_gen2
;
190 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
191 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
193 case IGP03E1000_E_PHY_ID
:
194 phy
->type
= e1000_phy_igp_3
;
195 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
196 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
197 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
198 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
199 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
201 case I82580_I_PHY_ID
:
203 phy
->type
= e1000_phy_82580
;
204 phy
->ops
.force_speed_duplex
=
205 igb_phy_force_speed_duplex_82580
;
206 phy
->ops
.get_cable_length
= igb_get_cable_length_82580
;
207 phy
->ops
.get_phy_info
= igb_get_phy_info_82580
;
208 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
209 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
212 phy
->type
= e1000_phy_i210
;
213 phy
->ops
.check_polarity
= igb_check_polarity_m88
;
214 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
215 phy
->ops
.get_cable_length
= igb_get_cable_length_m88_gen2
;
216 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82580
;
217 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state_82580
;
218 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
221 ret_val
= -E1000_ERR_PHY
;
230 * igb_init_nvm_params_82575 - Init NVM func ptrs.
231 * @hw: pointer to the HW structure
233 static s32
igb_init_nvm_params_82575(struct e1000_hw
*hw
)
235 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
236 u32 eecd
= rd32(E1000_EECD
);
239 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
240 E1000_EECD_SIZE_EX_SHIFT
);
241 /* Added to a constant, "size" becomes the left-shift value
242 * for setting word_size.
244 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
246 /* Just in case size is out of range, cap it to the largest
247 * EEPROM size supported
252 nvm
->word_size
= 1 << size
;
253 if (hw
->mac
.type
< e1000_i210
) {
254 nvm
->opcode_bits
= 8;
257 switch (nvm
->override
) {
258 case e1000_nvm_override_spi_large
:
260 nvm
->address_bits
= 16;
262 case e1000_nvm_override_spi_small
:
264 nvm
->address_bits
= 8;
267 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
268 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
?
272 if (nvm
->word_size
== (1 << 15))
273 nvm
->page_size
= 128;
275 nvm
->type
= e1000_nvm_eeprom_spi
;
277 nvm
->type
= e1000_nvm_flash_hw
;
280 /* NVM Function Pointers */
281 switch (hw
->mac
.type
) {
283 nvm
->ops
.validate
= igb_validate_nvm_checksum_82580
;
284 nvm
->ops
.update
= igb_update_nvm_checksum_82580
;
285 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
286 nvm
->ops
.release
= igb_release_nvm_82575
;
287 if (nvm
->word_size
< (1 << 15))
288 nvm
->ops
.read
= igb_read_nvm_eerd
;
290 nvm
->ops
.read
= igb_read_nvm_spi
;
291 nvm
->ops
.write
= igb_write_nvm_spi
;
295 nvm
->ops
.validate
= igb_validate_nvm_checksum_i350
;
296 nvm
->ops
.update
= igb_update_nvm_checksum_i350
;
297 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
298 nvm
->ops
.release
= igb_release_nvm_82575
;
299 if (nvm
->word_size
< (1 << 15))
300 nvm
->ops
.read
= igb_read_nvm_eerd
;
302 nvm
->ops
.read
= igb_read_nvm_spi
;
303 nvm
->ops
.write
= igb_write_nvm_spi
;
306 nvm
->ops
.validate
= igb_validate_nvm_checksum_i210
;
307 nvm
->ops
.update
= igb_update_nvm_checksum_i210
;
308 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
309 nvm
->ops
.release
= igb_release_nvm_i210
;
310 nvm
->ops
.read
= igb_read_nvm_srrd_i210
;
311 nvm
->ops
.write
= igb_write_nvm_srwr_i210
;
312 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
315 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
316 nvm
->ops
.release
= igb_release_nvm_i210
;
317 nvm
->ops
.read
= igb_read_nvm_i211
;
318 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
319 nvm
->ops
.validate
= NULL
;
320 nvm
->ops
.update
= NULL
;
321 nvm
->ops
.write
= NULL
;
324 nvm
->ops
.validate
= igb_validate_nvm_checksum
;
325 nvm
->ops
.update
= igb_update_nvm_checksum
;
326 nvm
->ops
.acquire
= igb_acquire_nvm_82575
;
327 nvm
->ops
.release
= igb_release_nvm_82575
;
328 if (nvm
->word_size
< (1 << 15))
329 nvm
->ops
.read
= igb_read_nvm_eerd
;
331 nvm
->ops
.read
= igb_read_nvm_spi
;
332 nvm
->ops
.write
= igb_write_nvm_spi
;
340 * igb_init_mac_params_82575 - Init MAC func ptrs.
341 * @hw: pointer to the HW structure
343 static s32
igb_init_mac_params_82575(struct e1000_hw
*hw
)
345 struct e1000_mac_info
*mac
= &hw
->mac
;
346 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
348 /* Set mta register count */
349 mac
->mta_reg_count
= 128;
350 /* Set rar entry count */
353 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
356 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82580
;
360 mac
->rar_entry_count
= E1000_RAR_ENTRIES_I350
;
363 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
367 if (mac
->type
>= e1000_82580
)
368 mac
->ops
.reset_hw
= igb_reset_hw_82580
;
370 mac
->ops
.reset_hw
= igb_reset_hw_82575
;
372 if (mac
->type
>= e1000_i210
) {
373 mac
->ops
.acquire_swfw_sync
= igb_acquire_swfw_sync_i210
;
374 mac
->ops
.release_swfw_sync
= igb_release_swfw_sync_i210
;
377 mac
->ops
.acquire_swfw_sync
= igb_acquire_swfw_sync_82575
;
378 mac
->ops
.release_swfw_sync
= igb_release_swfw_sync_82575
;
381 /* Set if part includes ASF firmware */
382 mac
->asf_firmware_present
= true;
383 /* Set if manageability features are enabled. */
384 mac
->arc_subsystem_valid
=
385 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
387 /* enable EEE on i350 parts and later parts */
388 if (mac
->type
>= e1000_i350
)
389 dev_spec
->eee_disable
= false;
391 dev_spec
->eee_disable
= true;
392 /* Allow a single clear of the SW semaphore on I210 and newer */
393 if (mac
->type
>= e1000_i210
)
394 dev_spec
->clear_semaphore_once
= true;
395 /* physical interface link setup */
396 mac
->ops
.setup_physical_interface
=
397 (hw
->phy
.media_type
== e1000_media_type_copper
)
398 ? igb_setup_copper_link_82575
399 : igb_setup_serdes_link_82575
;
404 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
406 struct e1000_mac_info
*mac
= &hw
->mac
;
407 struct e1000_dev_spec_82575
* dev_spec
= &hw
->dev_spec
._82575
;
411 switch (hw
->device_id
) {
412 case E1000_DEV_ID_82575EB_COPPER
:
413 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
414 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
415 mac
->type
= e1000_82575
;
417 case E1000_DEV_ID_82576
:
418 case E1000_DEV_ID_82576_NS
:
419 case E1000_DEV_ID_82576_NS_SERDES
:
420 case E1000_DEV_ID_82576_FIBER
:
421 case E1000_DEV_ID_82576_SERDES
:
422 case E1000_DEV_ID_82576_QUAD_COPPER
:
423 case E1000_DEV_ID_82576_QUAD_COPPER_ET2
:
424 case E1000_DEV_ID_82576_SERDES_QUAD
:
425 mac
->type
= e1000_82576
;
427 case E1000_DEV_ID_82580_COPPER
:
428 case E1000_DEV_ID_82580_FIBER
:
429 case E1000_DEV_ID_82580_QUAD_FIBER
:
430 case E1000_DEV_ID_82580_SERDES
:
431 case E1000_DEV_ID_82580_SGMII
:
432 case E1000_DEV_ID_82580_COPPER_DUAL
:
433 case E1000_DEV_ID_DH89XXCC_SGMII
:
434 case E1000_DEV_ID_DH89XXCC_SERDES
:
435 case E1000_DEV_ID_DH89XXCC_BACKPLANE
:
436 case E1000_DEV_ID_DH89XXCC_SFP
:
437 mac
->type
= e1000_82580
;
439 case E1000_DEV_ID_I350_COPPER
:
440 case E1000_DEV_ID_I350_FIBER
:
441 case E1000_DEV_ID_I350_SERDES
:
442 case E1000_DEV_ID_I350_SGMII
:
443 mac
->type
= e1000_i350
;
445 case E1000_DEV_ID_I210_COPPER
:
446 case E1000_DEV_ID_I210_FIBER
:
447 case E1000_DEV_ID_I210_SERDES
:
448 case E1000_DEV_ID_I210_SGMII
:
449 mac
->type
= e1000_i210
;
451 case E1000_DEV_ID_I211_COPPER
:
452 mac
->type
= e1000_i211
;
454 case E1000_DEV_ID_I354_BACKPLANE_1GBPS
:
455 case E1000_DEV_ID_I354_SGMII
:
456 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS
:
457 mac
->type
= e1000_i354
;
460 return -E1000_ERR_MAC_INIT
;
465 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
466 * based on the EEPROM. We cannot rely upon device ID. There
467 * is no distinguishable difference between fiber and internal
468 * SerDes mode on the 82575. There can be an external PHY attached
469 * on the SGMII interface. For this, we'll set sgmii_active to true.
471 hw
->phy
.media_type
= e1000_media_type_copper
;
472 dev_spec
->sgmii_active
= false;
474 ctrl_ext
= rd32(E1000_CTRL_EXT
);
475 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
476 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
477 dev_spec
->sgmii_active
= true;
479 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
480 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
:
481 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
487 /* mac initialization and operations */
488 ret_val
= igb_init_mac_params_82575(hw
);
492 /* NVM initialization */
493 ret_val
= igb_init_nvm_params_82575(hw
);
497 /* if part supports SR-IOV then initialize mailbox parameters */
501 igb_init_mbx_params_pf(hw
);
507 /* setup PHY parameters */
508 ret_val
= igb_init_phy_params_82575(hw
);
515 * igb_acquire_phy_82575 - Acquire rights to access PHY
516 * @hw: pointer to the HW structure
518 * Acquire access rights to the correct PHY. This is a
519 * function pointer entry point called by the api module.
521 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
523 u16 mask
= E1000_SWFW_PHY0_SM
;
525 if (hw
->bus
.func
== E1000_FUNC_1
)
526 mask
= E1000_SWFW_PHY1_SM
;
527 else if (hw
->bus
.func
== E1000_FUNC_2
)
528 mask
= E1000_SWFW_PHY2_SM
;
529 else if (hw
->bus
.func
== E1000_FUNC_3
)
530 mask
= E1000_SWFW_PHY3_SM
;
532 return hw
->mac
.ops
.acquire_swfw_sync(hw
, mask
);
536 * igb_release_phy_82575 - Release rights to access PHY
537 * @hw: pointer to the HW structure
539 * A wrapper to release access rights to the correct PHY. This is a
540 * function pointer entry point called by the api module.
542 static void igb_release_phy_82575(struct e1000_hw
*hw
)
544 u16 mask
= E1000_SWFW_PHY0_SM
;
546 if (hw
->bus
.func
== E1000_FUNC_1
)
547 mask
= E1000_SWFW_PHY1_SM
;
548 else if (hw
->bus
.func
== E1000_FUNC_2
)
549 mask
= E1000_SWFW_PHY2_SM
;
550 else if (hw
->bus
.func
== E1000_FUNC_3
)
551 mask
= E1000_SWFW_PHY3_SM
;
553 hw
->mac
.ops
.release_swfw_sync(hw
, mask
);
557 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
558 * @hw: pointer to the HW structure
559 * @offset: register offset to be read
560 * @data: pointer to the read data
562 * Reads the PHY register at offset using the serial gigabit media independent
563 * interface and stores the retrieved information in data.
565 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
568 s32 ret_val
= -E1000_ERR_PARAM
;
570 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
571 hw_dbg("PHY Address %u is out of range\n", offset
);
575 ret_val
= hw
->phy
.ops
.acquire(hw
);
579 ret_val
= igb_read_phy_reg_i2c(hw
, offset
, data
);
581 hw
->phy
.ops
.release(hw
);
588 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
589 * @hw: pointer to the HW structure
590 * @offset: register offset to write to
591 * @data: data to write at register offset
593 * Writes the data to PHY register at the offset using the serial gigabit
594 * media independent interface.
596 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
599 s32 ret_val
= -E1000_ERR_PARAM
;
602 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
603 hw_dbg("PHY Address %d is out of range\n", offset
);
607 ret_val
= hw
->phy
.ops
.acquire(hw
);
611 ret_val
= igb_write_phy_reg_i2c(hw
, offset
, data
);
613 hw
->phy
.ops
.release(hw
);
620 * igb_get_phy_id_82575 - Retrieve PHY addr and id
621 * @hw: pointer to the HW structure
623 * Retrieves the PHY address and ID for both PHY's which do and do not use
626 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
628 struct e1000_phy_info
*phy
= &hw
->phy
;
634 /* For SGMII PHYs, we try the list of possible addresses until
635 * we find one that works. For non-SGMII PHYs
636 * (e.g. integrated copper PHYs), an address of 1 should
637 * work. The result of this function should mean phy->phy_addr
638 * and phy->id are set correctly.
640 if (!(igb_sgmii_active_82575(hw
))) {
642 ret_val
= igb_get_phy_id(hw
);
646 if (igb_sgmii_uses_mdio_82575(hw
)) {
647 switch (hw
->mac
.type
) {
650 mdic
= rd32(E1000_MDIC
);
651 mdic
&= E1000_MDIC_PHY_MASK
;
652 phy
->addr
= mdic
>> E1000_MDIC_PHY_SHIFT
;
659 mdic
= rd32(E1000_MDICNFG
);
660 mdic
&= E1000_MDICNFG_PHY_MASK
;
661 phy
->addr
= mdic
>> E1000_MDICNFG_PHY_SHIFT
;
664 ret_val
= -E1000_ERR_PHY
;
668 ret_val
= igb_get_phy_id(hw
);
672 /* Power on sgmii phy if it is disabled */
673 ctrl_ext
= rd32(E1000_CTRL_EXT
);
674 wr32(E1000_CTRL_EXT
, ctrl_ext
& ~E1000_CTRL_EXT_SDP3_DATA
);
678 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
679 * Therefore, we need to test 1-7
681 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
682 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
684 hw_dbg("Vendor ID 0x%08X read at address %u\n",
686 /* At the time of this writing, The M88 part is
687 * the only supported SGMII PHY product.
689 if (phy_id
== M88_VENDOR
)
692 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
696 /* A valid PHY type couldn't be found. */
697 if (phy
->addr
== 8) {
699 ret_val
= -E1000_ERR_PHY
;
702 ret_val
= igb_get_phy_id(hw
);
705 /* restore previous sfp cage power state */
706 wr32(E1000_CTRL_EXT
, ctrl_ext
);
713 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
714 * @hw: pointer to the HW structure
716 * Resets the PHY using the serial gigabit media independent interface.
718 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
722 /* This isn't a true "hard" reset, but is the only reset
723 * available to us at this time.
726 hw_dbg("Soft resetting SGMII attached PHY...\n");
728 /* SFP documentation requires the following to configure the SPF module
729 * to work on SGMII. No further documentation is given.
731 ret_val
= hw
->phy
.ops
.write_reg(hw
, 0x1B, 0x8084);
735 ret_val
= igb_phy_sw_reset(hw
);
742 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
743 * @hw: pointer to the HW structure
744 * @active: true to enable LPLU, false to disable
746 * Sets the LPLU D0 state according to the active flag. When
747 * activating LPLU this function also disables smart speed
748 * and vice versa. LPLU will not be activated unless the
749 * device autonegotiation advertisement meets standards of
750 * either 10 or 10/100 or 10/100/1000 at all duplexes.
751 * This is a function pointer entry point only called by
752 * PHY setup routines.
754 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
756 struct e1000_phy_info
*phy
= &hw
->phy
;
760 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
765 data
|= IGP02E1000_PM_D0_LPLU
;
766 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
771 /* When LPLU is enabled, we should disable SmartSpeed */
772 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
774 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
775 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
780 data
&= ~IGP02E1000_PM_D0_LPLU
;
781 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
783 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
784 * during Dx states where the power conservation is most
785 * important. During driver activity we should enable
786 * SmartSpeed, so performance is maintained.
788 if (phy
->smart_speed
== e1000_smart_speed_on
) {
789 ret_val
= phy
->ops
.read_reg(hw
,
790 IGP01E1000_PHY_PORT_CONFIG
, &data
);
794 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
795 ret_val
= phy
->ops
.write_reg(hw
,
796 IGP01E1000_PHY_PORT_CONFIG
, data
);
799 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
800 ret_val
= phy
->ops
.read_reg(hw
,
801 IGP01E1000_PHY_PORT_CONFIG
, &data
);
805 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
806 ret_val
= phy
->ops
.write_reg(hw
,
807 IGP01E1000_PHY_PORT_CONFIG
, data
);
818 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
819 * @hw: pointer to the HW structure
820 * @active: true to enable LPLU, false to disable
822 * Sets the LPLU D0 state according to the active flag. When
823 * activating LPLU this function also disables smart speed
824 * and vice versa. LPLU will not be activated unless the
825 * device autonegotiation advertisement meets standards of
826 * either 10 or 10/100 or 10/100/1000 at all duplexes.
827 * This is a function pointer entry point only called by
828 * PHY setup routines.
830 static s32
igb_set_d0_lplu_state_82580(struct e1000_hw
*hw
, bool active
)
832 struct e1000_phy_info
*phy
= &hw
->phy
;
836 data
= rd32(E1000_82580_PHY_POWER_MGMT
);
839 data
|= E1000_82580_PM_D0_LPLU
;
841 /* When LPLU is enabled, we should disable SmartSpeed */
842 data
&= ~E1000_82580_PM_SPD
;
844 data
&= ~E1000_82580_PM_D0_LPLU
;
846 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
847 * during Dx states where the power conservation is most
848 * important. During driver activity we should enable
849 * SmartSpeed, so performance is maintained.
851 if (phy
->smart_speed
== e1000_smart_speed_on
)
852 data
|= E1000_82580_PM_SPD
;
853 else if (phy
->smart_speed
== e1000_smart_speed_off
)
854 data
&= ~E1000_82580_PM_SPD
; }
856 wr32(E1000_82580_PHY_POWER_MGMT
, data
);
861 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
862 * @hw: pointer to the HW structure
863 * @active: boolean used to enable/disable lplu
865 * Success returns 0, Failure returns 1
867 * The low power link up (lplu) state is set to the power management level D3
868 * and SmartSpeed is disabled when active is true, else clear lplu for D3
869 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
870 * is used during Dx states where the power conservation is most important.
871 * During driver activity, SmartSpeed should be enabled so performance is
874 static s32
igb_set_d3_lplu_state_82580(struct e1000_hw
*hw
, bool active
)
876 struct e1000_phy_info
*phy
= &hw
->phy
;
880 data
= rd32(E1000_82580_PHY_POWER_MGMT
);
883 data
&= ~E1000_82580_PM_D3_LPLU
;
884 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
885 * during Dx states where the power conservation is most
886 * important. During driver activity we should enable
887 * SmartSpeed, so performance is maintained.
889 if (phy
->smart_speed
== e1000_smart_speed_on
)
890 data
|= E1000_82580_PM_SPD
;
891 else if (phy
->smart_speed
== e1000_smart_speed_off
)
892 data
&= ~E1000_82580_PM_SPD
;
893 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
894 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
895 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
896 data
|= E1000_82580_PM_D3_LPLU
;
897 /* When LPLU is enabled, we should disable SmartSpeed */
898 data
&= ~E1000_82580_PM_SPD
;
901 wr32(E1000_82580_PHY_POWER_MGMT
, data
);
906 * igb_acquire_nvm_82575 - Request for access to EEPROM
907 * @hw: pointer to the HW structure
909 * Acquire the necessary semaphores for exclusive access to the EEPROM.
910 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
911 * Return successful if access grant bit set, else clear the request for
912 * EEPROM access and return -E1000_ERR_NVM (-1).
914 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
918 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
922 ret_val
= igb_acquire_nvm(hw
);
925 hw
->mac
.ops
.release_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
932 * igb_release_nvm_82575 - Release exclusive access to EEPROM
933 * @hw: pointer to the HW structure
935 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
936 * then release the semaphores acquired.
938 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
941 hw
->mac
.ops
.release_swfw_sync(hw
, E1000_SWFW_EEP_SM
);
945 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
946 * @hw: pointer to the HW structure
947 * @mask: specifies which semaphore to acquire
949 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
950 * will also specify which port we're acquiring the lock for.
952 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
956 u32 fwmask
= mask
<< 16;
958 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
960 while (i
< timeout
) {
961 if (igb_get_hw_semaphore(hw
)) {
962 ret_val
= -E1000_ERR_SWFW_SYNC
;
966 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
967 if (!(swfw_sync
& (fwmask
| swmask
)))
970 /* Firmware currently using resource (fwmask)
971 * or other software thread using resource (swmask)
973 igb_put_hw_semaphore(hw
);
979 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
980 ret_val
= -E1000_ERR_SWFW_SYNC
;
985 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
987 igb_put_hw_semaphore(hw
);
994 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
995 * @hw: pointer to the HW structure
996 * @mask: specifies which semaphore to acquire
998 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
999 * will also specify which port we're releasing the lock for.
1001 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
1005 while (igb_get_hw_semaphore(hw
) != 0);
1008 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
1010 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
1012 igb_put_hw_semaphore(hw
);
1016 * igb_get_cfg_done_82575 - Read config done bit
1017 * @hw: pointer to the HW structure
1019 * Read the management control register for the config done bit for
1020 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1021 * to read the config done bit, so an error is *ONLY* logged and returns
1022 * 0. If we were to return with error, EEPROM-less silicon
1023 * would not be able to be reset or change link.
1025 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
1027 s32 timeout
= PHY_CFG_TIMEOUT
;
1029 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
1031 if (hw
->bus
.func
== 1)
1032 mask
= E1000_NVM_CFG_DONE_PORT_1
;
1033 else if (hw
->bus
.func
== E1000_FUNC_2
)
1034 mask
= E1000_NVM_CFG_DONE_PORT_2
;
1035 else if (hw
->bus
.func
== E1000_FUNC_3
)
1036 mask
= E1000_NVM_CFG_DONE_PORT_3
;
1039 if (rd32(E1000_EEMNGCTL
) & mask
)
1045 hw_dbg("MNG configuration cycle has not completed.\n");
1047 /* If EEPROM is not marked present, init the PHY manually */
1048 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
1049 (hw
->phy
.type
== e1000_phy_igp_3
))
1050 igb_phy_init_script_igp3(hw
);
1056 * igb_check_for_link_82575 - Check for link
1057 * @hw: pointer to the HW structure
1059 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1060 * use the generic interface for determining link.
1062 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
1067 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
1068 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
1070 /* Use this flag to determine if link needs to be checked or
1071 * not. If we have link clear the flag so that we do not
1072 * continue to check for link.
1074 hw
->mac
.get_link_status
= !hw
->mac
.serdes_has_link
;
1076 /* Configure Flow Control now that Auto-Neg has completed.
1077 * First, we need to restore the desired flow control
1078 * settings because we may have had to re-autoneg with a
1079 * different link partner.
1081 ret_val
= igb_config_fc_after_link_up(hw
);
1083 hw_dbg("Error configuring flow control\n");
1085 ret_val
= igb_check_for_copper_link(hw
);
1092 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1093 * @hw: pointer to the HW structure
1095 void igb_power_up_serdes_link_82575(struct e1000_hw
*hw
)
1100 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1101 !igb_sgmii_active_82575(hw
))
1104 /* Enable PCS to turn on link */
1105 reg
= rd32(E1000_PCS_CFG0
);
1106 reg
|= E1000_PCS_CFG_PCS_EN
;
1107 wr32(E1000_PCS_CFG0
, reg
);
1109 /* Power up the laser */
1110 reg
= rd32(E1000_CTRL_EXT
);
1111 reg
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1112 wr32(E1000_CTRL_EXT
, reg
);
1114 /* flush the write to verify completion */
1120 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1121 * @hw: pointer to the HW structure
1122 * @speed: stores the current speed
1123 * @duplex: stores the current duplex
1125 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1126 * duplex, then store the values in the pointers provided.
1128 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
1131 struct e1000_mac_info
*mac
= &hw
->mac
;
1134 /* Set up defaults for the return values of this function */
1135 mac
->serdes_has_link
= false;
1139 /* Read the PCS Status register for link state. For non-copper mode,
1140 * the status register is not accurate. The PCS status register is
1143 pcs
= rd32(E1000_PCS_LSTAT
);
1145 /* The link up bit determines when link is up on autoneg. The sync ok
1146 * gets set once both sides sync up and agree upon link. Stable link
1147 * can be determined by checking for both link up and link sync ok
1149 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
1150 mac
->serdes_has_link
= true;
1152 /* Detect and store PCS speed */
1153 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
1154 *speed
= SPEED_1000
;
1155 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
1161 /* Detect and store PCS duplex */
1162 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
1163 *duplex
= FULL_DUPLEX
;
1165 *duplex
= HALF_DUPLEX
;
1173 * igb_shutdown_serdes_link_82575 - Remove link during power down
1174 * @hw: pointer to the HW structure
1176 * In the case of fiber serdes, shut down optics and PCS on driver unload
1177 * when management pass thru is not enabled.
1179 void igb_shutdown_serdes_link_82575(struct e1000_hw
*hw
)
1183 if (hw
->phy
.media_type
!= e1000_media_type_internal_serdes
&&
1184 igb_sgmii_active_82575(hw
))
1187 if (!igb_enable_mng_pass_thru(hw
)) {
1188 /* Disable PCS to turn off link */
1189 reg
= rd32(E1000_PCS_CFG0
);
1190 reg
&= ~E1000_PCS_CFG_PCS_EN
;
1191 wr32(E1000_PCS_CFG0
, reg
);
1193 /* shutdown the laser */
1194 reg
= rd32(E1000_CTRL_EXT
);
1195 reg
|= E1000_CTRL_EXT_SDP3_DATA
;
1196 wr32(E1000_CTRL_EXT
, reg
);
1198 /* flush the write to verify completion */
1205 * igb_reset_hw_82575 - Reset hardware
1206 * @hw: pointer to the HW structure
1208 * This resets the hardware into a known state. This is a
1209 * function pointer entry point called by the api module.
1211 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
1216 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1217 * on the last TLP read/write transaction when MAC is reset.
1219 ret_val
= igb_disable_pcie_master(hw
);
1221 hw_dbg("PCI-E Master disable polling has failed.\n");
1223 /* set the completion timeout for interface */
1224 ret_val
= igb_set_pcie_completion_timeout(hw
);
1226 hw_dbg("PCI-E Set completion timeout has failed.\n");
1229 hw_dbg("Masking off all interrupts\n");
1230 wr32(E1000_IMC
, 0xffffffff);
1232 wr32(E1000_RCTL
, 0);
1233 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
1238 ctrl
= rd32(E1000_CTRL
);
1240 hw_dbg("Issuing a global reset to MAC\n");
1241 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
1243 ret_val
= igb_get_auto_rd_done(hw
);
1245 /* When auto config read does not complete, do not
1246 * return with an error. This can happen in situations
1247 * where there is no eeprom and prevents getting link.
1249 hw_dbg("Auto Read Done did not complete\n");
1252 /* If EEPROM is not present, run manual init scripts */
1253 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
1254 igb_reset_init_script_82575(hw
);
1256 /* Clear any pending interrupt events. */
1257 wr32(E1000_IMC
, 0xffffffff);
1258 icr
= rd32(E1000_ICR
);
1260 /* Install any alternate MAC address into RAR0 */
1261 ret_val
= igb_check_alt_mac_addr(hw
);
1267 * igb_init_hw_82575 - Initialize hardware
1268 * @hw: pointer to the HW structure
1270 * This inits the hardware readying it for operation.
1272 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
1274 struct e1000_mac_info
*mac
= &hw
->mac
;
1276 u16 i
, rar_count
= mac
->rar_entry_count
;
1278 /* Initialize identification LED */
1279 ret_val
= igb_id_led_init(hw
);
1281 hw_dbg("Error initializing identification LED\n");
1282 /* This is not fatal and we should not stop init due to this */
1285 /* Disabling VLAN filtering */
1286 hw_dbg("Initializing the IEEE VLAN\n");
1287 if ((hw
->mac
.type
== e1000_i350
) || (hw
->mac
.type
== e1000_i354
))
1288 igb_clear_vfta_i350(hw
);
1292 /* Setup the receive address */
1293 igb_init_rx_addrs(hw
, rar_count
);
1295 /* Zero out the Multicast HASH table */
1296 hw_dbg("Zeroing the MTA\n");
1297 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
1298 array_wr32(E1000_MTA
, i
, 0);
1300 /* Zero out the Unicast HASH table */
1301 hw_dbg("Zeroing the UTA\n");
1302 for (i
= 0; i
< mac
->uta_reg_count
; i
++)
1303 array_wr32(E1000_UTA
, i
, 0);
1305 /* Setup link and flow control */
1306 ret_val
= igb_setup_link(hw
);
1308 /* Clear all of the statistics registers (clear on read). It is
1309 * important that we do this after we have tried to establish link
1310 * because the symbol error count will increment wildly if there
1313 igb_clear_hw_cntrs_82575(hw
);
1318 * igb_setup_copper_link_82575 - Configure copper link settings
1319 * @hw: pointer to the HW structure
1321 * Configures the link for auto-neg or forced speed and duplex. Then we check
1322 * for link, once link is established calls to configure collision distance
1323 * and flow control are called.
1325 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
1331 ctrl
= rd32(E1000_CTRL
);
1332 ctrl
|= E1000_CTRL_SLU
;
1333 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1334 wr32(E1000_CTRL
, ctrl
);
1336 /* Clear Go Link Disconnect bit */
1337 if (hw
->mac
.type
>= e1000_82580
) {
1338 phpm_reg
= rd32(E1000_82580_PHY_POWER_MGMT
);
1339 phpm_reg
&= ~E1000_82580_PM_GO_LINKD
;
1340 wr32(E1000_82580_PHY_POWER_MGMT
, phpm_reg
);
1343 ret_val
= igb_setup_serdes_link_82575(hw
);
1347 if (igb_sgmii_active_82575(hw
) && !hw
->phy
.reset_disable
) {
1348 /* allow time for SFP cage time to power up phy */
1351 ret_val
= hw
->phy
.ops
.reset(hw
);
1353 hw_dbg("Error resetting the PHY.\n");
1357 switch (hw
->phy
.type
) {
1358 case e1000_phy_i210
:
1360 switch (hw
->phy
.id
) {
1361 case I347AT4_E_PHY_ID
:
1362 case M88E1112_E_PHY_ID
:
1363 case M88E1545_E_PHY_ID
:
1365 ret_val
= igb_copper_link_setup_m88_gen2(hw
);
1368 ret_val
= igb_copper_link_setup_m88(hw
);
1372 case e1000_phy_igp_3
:
1373 ret_val
= igb_copper_link_setup_igp(hw
);
1375 case e1000_phy_82580
:
1376 ret_val
= igb_copper_link_setup_82580(hw
);
1379 ret_val
= -E1000_ERR_PHY
;
1386 ret_val
= igb_setup_copper_link(hw
);
1392 * igb_setup_serdes_link_82575 - Setup link for serdes
1393 * @hw: pointer to the HW structure
1395 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1396 * used on copper connections where the serialized gigabit media independent
1397 * interface (sgmii), or serdes fiber is being used. Configures the link
1398 * for auto-negotiation or forces speed/duplex.
1400 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*hw
)
1402 u32 ctrl_ext
, ctrl_reg
, reg
, anadv_reg
;
1404 s32 ret_val
= E1000_SUCCESS
;
1407 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1408 !igb_sgmii_active_82575(hw
))
1412 /* On the 82575, SerDes loopback mode persists until it is
1413 * explicitly turned off or a power cycle is performed. A read to
1414 * the register does not indicate its status. Therefore, we ensure
1415 * loopback mode is disabled during initialization.
1417 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1419 /* power on the sfp cage if present and turn on I2C */
1420 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1421 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1422 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
1423 wr32(E1000_CTRL_EXT
, ctrl_ext
);
1425 ctrl_reg
= rd32(E1000_CTRL
);
1426 ctrl_reg
|= E1000_CTRL_SLU
;
1428 if (hw
->mac
.type
== e1000_82575
|| hw
->mac
.type
== e1000_82576
) {
1429 /* set both sw defined pins */
1430 ctrl_reg
|= E1000_CTRL_SWDPIN0
| E1000_CTRL_SWDPIN1
;
1432 /* Set switch control to serdes energy detect */
1433 reg
= rd32(E1000_CONNSW
);
1434 reg
|= E1000_CONNSW_ENRGSRC
;
1435 wr32(E1000_CONNSW
, reg
);
1438 reg
= rd32(E1000_PCS_LCTL
);
1440 /* default pcs_autoneg to the same setting as mac autoneg */
1441 pcs_autoneg
= hw
->mac
.autoneg
;
1443 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
1444 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
1445 /* sgmii mode lets the phy handle forcing speed/duplex */
1447 /* autoneg time out should be disabled for SGMII mode */
1448 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1450 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
1451 /* disable PCS autoneg and support parallel detect only */
1452 pcs_autoneg
= false;
1454 if (hw
->mac
.type
== e1000_82575
||
1455 hw
->mac
.type
== e1000_82576
) {
1456 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPAT
, 1, &data
);
1458 printk(KERN_DEBUG
"NVM Read Error\n\n");
1462 if (data
& E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT
)
1463 pcs_autoneg
= false;
1466 /* non-SGMII modes only supports a speed of 1000/Full for the
1467 * link so it is best to just force the MAC and let the pcs
1468 * link either autoneg or be forced to 1000/Full
1470 ctrl_reg
|= E1000_CTRL_SPD_1000
| E1000_CTRL_FRCSPD
|
1471 E1000_CTRL_FD
| E1000_CTRL_FRCDPX
;
1473 /* set speed of 1000/Full if speed/duplex is forced */
1474 reg
|= E1000_PCS_LCTL_FSV_1000
| E1000_PCS_LCTL_FDV_FULL
;
1478 wr32(E1000_CTRL
, ctrl_reg
);
1480 /* New SerDes mode allows for forcing speed or autonegotiating speed
1481 * at 1gb. Autoneg should be default set by most drivers. This is the
1482 * mode that will be compatible with older link partners and switches.
1483 * However, both are supported by the hardware and some drivers/tools.
1485 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1486 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1489 /* Set PCS register for autoneg */
1490 reg
|= E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1491 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1493 /* Disable force flow control for autoneg */
1494 reg
&= ~E1000_PCS_LCTL_FORCE_FCTRL
;
1496 /* Configure flow control advertisement for autoneg */
1497 anadv_reg
= rd32(E1000_PCS_ANADV
);
1498 anadv_reg
&= ~(E1000_TXCW_ASM_DIR
| E1000_TXCW_PAUSE
);
1499 switch (hw
->fc
.requested_mode
) {
1501 case e1000_fc_rx_pause
:
1502 anadv_reg
|= E1000_TXCW_ASM_DIR
;
1503 anadv_reg
|= E1000_TXCW_PAUSE
;
1505 case e1000_fc_tx_pause
:
1506 anadv_reg
|= E1000_TXCW_ASM_DIR
;
1511 wr32(E1000_PCS_ANADV
, anadv_reg
);
1513 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg
);
1515 /* Set PCS register for forced link */
1516 reg
|= E1000_PCS_LCTL_FSD
; /* Force Speed */
1518 /* Force flow control for forced link */
1519 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1521 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg
);
1524 wr32(E1000_PCS_LCTL
, reg
);
1526 if (!pcs_autoneg
&& !igb_sgmii_active_82575(hw
))
1527 igb_force_mac_fc(hw
);
1533 * igb_sgmii_active_82575 - Return sgmii state
1534 * @hw: pointer to the HW structure
1536 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1537 * which can be enabled for use in the embedded applications. Simply
1538 * return the current state of the sgmii interface.
1540 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1542 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
1543 return dev_spec
->sgmii_active
;
1547 * igb_reset_init_script_82575 - Inits HW defaults after reset
1548 * @hw: pointer to the HW structure
1550 * Inits recommended HW defaults after a reset when there is no EEPROM
1551 * detected. This is only for the 82575.
1553 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1555 if (hw
->mac
.type
== e1000_82575
) {
1556 hw_dbg("Running reset init script for 82575\n");
1557 /* SerDes configuration via SERDESCTRL */
1558 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1559 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1560 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1561 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1563 /* CCM configuration via CCMCTL register */
1564 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1565 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1567 /* PCIe lanes configuration */
1568 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1569 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1570 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1571 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1573 /* PCIe PLL Configuration */
1574 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1575 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1576 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1583 * igb_read_mac_addr_82575 - Read device MAC address
1584 * @hw: pointer to the HW structure
1586 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1590 /* If there's an alternate MAC address place it in RAR0
1591 * so that it will override the Si installed default perm
1594 ret_val
= igb_check_alt_mac_addr(hw
);
1598 ret_val
= igb_read_mac_addr(hw
);
1605 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1606 * @hw: pointer to the HW structure
1608 * In the case of a PHY power down to save power, or to turn off link during a
1609 * driver unload, or wake on lan is not enabled, remove the link.
1611 void igb_power_down_phy_copper_82575(struct e1000_hw
*hw
)
1613 /* If the management interface is not enabled, then power down */
1614 if (!(igb_enable_mng_pass_thru(hw
) || igb_check_reset_block(hw
)))
1615 igb_power_down_phy_copper(hw
);
1619 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1620 * @hw: pointer to the HW structure
1622 * Clears the hardware counters by reading the counter registers.
1624 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1626 igb_clear_hw_cntrs_base(hw
);
1632 rd32(E1000_PRC1023
);
1633 rd32(E1000_PRC1522
);
1638 rd32(E1000_PTC1023
);
1639 rd32(E1000_PTC1522
);
1641 rd32(E1000_ALGNERRC
);
1644 rd32(E1000_CEXTERR
);
1655 rd32(E1000_ICRXPTC
);
1656 rd32(E1000_ICRXATC
);
1657 rd32(E1000_ICTXPTC
);
1658 rd32(E1000_ICTXATC
);
1659 rd32(E1000_ICTXQEC
);
1660 rd32(E1000_ICTXQMTC
);
1661 rd32(E1000_ICRXDMTC
);
1668 rd32(E1000_HTCBDPC
);
1673 rd32(E1000_LENERRS
);
1675 /* This register should not be read in copper configurations */
1676 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
||
1677 igb_sgmii_active_82575(hw
))
1682 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1683 * @hw: pointer to the HW structure
1685 * After rx enable if managability is enabled then there is likely some
1686 * bad data at the start of the fifo and possibly in the DMA fifo. This
1687 * function clears the fifos and flushes any packets that came in as rx was
1690 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1692 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1695 if (hw
->mac
.type
!= e1000_82575
||
1696 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1699 /* Disable all RX queues */
1700 for (i
= 0; i
< 4; i
++) {
1701 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1702 wr32(E1000_RXDCTL(i
),
1703 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1705 /* Poll all queues to verify they have shut down */
1706 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1709 for (i
= 0; i
< 4; i
++)
1710 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1711 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1716 hw_dbg("Queue disable timed out after 10ms\n");
1718 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1719 * incoming packets are rejected. Set enable and wait 2ms so that
1720 * any packet that was coming in as RCTL.EN was set is flushed
1722 rfctl
= rd32(E1000_RFCTL
);
1723 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1725 rlpml
= rd32(E1000_RLPML
);
1726 wr32(E1000_RLPML
, 0);
1728 rctl
= rd32(E1000_RCTL
);
1729 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1730 temp_rctl
|= E1000_RCTL_LPE
;
1732 wr32(E1000_RCTL
, temp_rctl
);
1733 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1737 /* Enable RX queues that were previously enabled and restore our
1740 for (i
= 0; i
< 4; i
++)
1741 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1742 wr32(E1000_RCTL
, rctl
);
1745 wr32(E1000_RLPML
, rlpml
);
1746 wr32(E1000_RFCTL
, rfctl
);
1748 /* Flush receive errors generated by workaround */
1755 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1756 * @hw: pointer to the HW structure
1758 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1759 * however the hardware default for these parts is 500us to 1ms which is less
1760 * than the 10ms recommended by the pci-e spec. To address this we need to
1761 * increase the value to either 10ms to 200ms for capability version 1 config,
1762 * or 16ms to 55ms for version 2.
1764 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
)
1766 u32 gcr
= rd32(E1000_GCR
);
1770 /* only take action if timeout value is defaulted to 0 */
1771 if (gcr
& E1000_GCR_CMPL_TMOUT_MASK
)
1774 /* if capabilities version is type 1 we can write the
1775 * timeout of 10ms to 200ms through the GCR register
1777 if (!(gcr
& E1000_GCR_CAP_VER2
)) {
1778 gcr
|= E1000_GCR_CMPL_TMOUT_10ms
;
1782 /* for version 2 capabilities we need to write the config space
1783 * directly in order to set the completion timeout value for
1786 ret_val
= igb_read_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1791 pcie_devctl2
|= PCIE_DEVICE_CONTROL2_16ms
;
1793 ret_val
= igb_write_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1796 /* disable completion timeout resend */
1797 gcr
&= ~E1000_GCR_CMPL_TMOUT_RESEND
;
1799 wr32(E1000_GCR
, gcr
);
1804 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1805 * @hw: pointer to the hardware struct
1806 * @enable: state to enter, either enabled or disabled
1807 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1809 * enables/disables L2 switch anti-spoofing functionality.
1811 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw
*hw
, bool enable
, int pf
)
1813 u32 reg_val
, reg_offset
;
1815 switch (hw
->mac
.type
) {
1817 reg_offset
= E1000_DTXSWC
;
1821 reg_offset
= E1000_TXSWC
;
1827 reg_val
= rd32(reg_offset
);
1829 reg_val
|= (E1000_DTXSWC_MAC_SPOOF_MASK
|
1830 E1000_DTXSWC_VLAN_SPOOF_MASK
);
1831 /* The PF can spoof - it has to in order to
1832 * support emulation mode NICs
1834 reg_val
^= (1 << pf
| 1 << (pf
+ MAX_NUM_VFS
));
1836 reg_val
&= ~(E1000_DTXSWC_MAC_SPOOF_MASK
|
1837 E1000_DTXSWC_VLAN_SPOOF_MASK
);
1839 wr32(reg_offset
, reg_val
);
1843 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1844 * @hw: pointer to the hardware struct
1845 * @enable: state to enter, either enabled or disabled
1847 * enables/disables L2 switch loopback functionality.
1849 void igb_vmdq_set_loopback_pf(struct e1000_hw
*hw
, bool enable
)
1853 switch (hw
->mac
.type
) {
1855 dtxswc
= rd32(E1000_DTXSWC
);
1857 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1859 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1860 wr32(E1000_DTXSWC
, dtxswc
);
1864 dtxswc
= rd32(E1000_TXSWC
);
1866 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1868 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1869 wr32(E1000_TXSWC
, dtxswc
);
1872 /* Currently no other hardware supports loopback */
1879 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1880 * @hw: pointer to the hardware struct
1881 * @enable: state to enter, either enabled or disabled
1883 * enables/disables replication of packets across multiple pools.
1885 void igb_vmdq_set_replication_pf(struct e1000_hw
*hw
, bool enable
)
1887 u32 vt_ctl
= rd32(E1000_VT_CTL
);
1890 vt_ctl
|= E1000_VT_CTL_VM_REPL_EN
;
1892 vt_ctl
&= ~E1000_VT_CTL_VM_REPL_EN
;
1894 wr32(E1000_VT_CTL
, vt_ctl
);
1898 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1899 * @hw: pointer to the HW structure
1900 * @offset: register offset to be read
1901 * @data: pointer to the read data
1903 * Reads the MDI control register in the PHY at offset and stores the
1904 * information read to data.
1906 static s32
igb_read_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
1910 ret_val
= hw
->phy
.ops
.acquire(hw
);
1914 ret_val
= igb_read_phy_reg_mdic(hw
, offset
, data
);
1916 hw
->phy
.ops
.release(hw
);
1923 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1924 * @hw: pointer to the HW structure
1925 * @offset: register offset to write to
1926 * @data: data to write to register at offset
1928 * Writes data to MDI control register in the PHY at offset.
1930 static s32
igb_write_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16 data
)
1935 ret_val
= hw
->phy
.ops
.acquire(hw
);
1939 ret_val
= igb_write_phy_reg_mdic(hw
, offset
, data
);
1941 hw
->phy
.ops
.release(hw
);
1948 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1949 * @hw: pointer to the HW structure
1951 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1952 * the values found in the EEPROM. This addresses an issue in which these
1953 * bits are not restored from EEPROM after reset.
1955 static s32
igb_reset_mdicnfg_82580(struct e1000_hw
*hw
)
1961 if (hw
->mac
.type
!= e1000_82580
)
1963 if (!igb_sgmii_active_82575(hw
))
1966 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_A
+
1967 NVM_82580_LAN_FUNC_OFFSET(hw
->bus
.func
), 1,
1970 hw_dbg("NVM Read Error\n");
1974 mdicnfg
= rd32(E1000_MDICNFG
);
1975 if (nvm_data
& NVM_WORD24_EXT_MDIO
)
1976 mdicnfg
|= E1000_MDICNFG_EXT_MDIO
;
1977 if (nvm_data
& NVM_WORD24_COM_MDIO
)
1978 mdicnfg
|= E1000_MDICNFG_COM_MDIO
;
1979 wr32(E1000_MDICNFG
, mdicnfg
);
1985 * igb_reset_hw_82580 - Reset hardware
1986 * @hw: pointer to the HW structure
1988 * This resets function or entire device (all ports, etc.)
1991 static s32
igb_reset_hw_82580(struct e1000_hw
*hw
)
1994 /* BH SW mailbox bit in SW_FW_SYNC */
1995 u16 swmbsw_mask
= E1000_SW_SYNCH_MB
;
1997 bool global_device_reset
= hw
->dev_spec
._82575
.global_device_reset
;
2000 hw
->dev_spec
._82575
.global_device_reset
= false;
2002 /* due to hw errata, global device reset doesn't always
2005 if (hw
->mac
.type
== e1000_82580
)
2006 global_device_reset
= false;
2008 /* Get current control state. */
2009 ctrl
= rd32(E1000_CTRL
);
2011 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2012 * on the last TLP read/write transaction when MAC is reset.
2014 ret_val
= igb_disable_pcie_master(hw
);
2016 hw_dbg("PCI-E Master disable polling has failed.\n");
2018 hw_dbg("Masking off all interrupts\n");
2019 wr32(E1000_IMC
, 0xffffffff);
2020 wr32(E1000_RCTL
, 0);
2021 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
2026 /* Determine whether or not a global dev reset is requested */
2027 if (global_device_reset
&&
2028 hw
->mac
.ops
.acquire_swfw_sync(hw
, swmbsw_mask
))
2029 global_device_reset
= false;
2031 if (global_device_reset
&&
2032 !(rd32(E1000_STATUS
) & E1000_STAT_DEV_RST_SET
))
2033 ctrl
|= E1000_CTRL_DEV_RST
;
2035 ctrl
|= E1000_CTRL_RST
;
2037 wr32(E1000_CTRL
, ctrl
);
2040 /* Add delay to insure DEV_RST has time to complete */
2041 if (global_device_reset
)
2044 ret_val
= igb_get_auto_rd_done(hw
);
2046 /* When auto config read does not complete, do not
2047 * return with an error. This can happen in situations
2048 * where there is no eeprom and prevents getting link.
2050 hw_dbg("Auto Read Done did not complete\n");
2053 /* clear global device reset status bit */
2054 wr32(E1000_STATUS
, E1000_STAT_DEV_RST_SET
);
2056 /* Clear any pending interrupt events. */
2057 wr32(E1000_IMC
, 0xffffffff);
2058 icr
= rd32(E1000_ICR
);
2060 ret_val
= igb_reset_mdicnfg_82580(hw
);
2062 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2064 /* Install any alternate MAC address into RAR0 */
2065 ret_val
= igb_check_alt_mac_addr(hw
);
2067 /* Release semaphore */
2068 if (global_device_reset
)
2069 hw
->mac
.ops
.release_swfw_sync(hw
, swmbsw_mask
);
2075 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2076 * @data: data received by reading RXPBS register
2078 * The 82580 uses a table based approach for packet buffer allocation sizes.
2079 * This function converts the retrieved value into the correct table value
2080 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2081 * 0x0 36 72 144 1 2 4 8 16
2082 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2084 u16
igb_rxpbs_adjust_82580(u32 data
)
2088 if (data
< E1000_82580_RXPBS_TABLE_SIZE
)
2089 ret_val
= e1000_82580_rxpbs_table
[data
];
2095 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2097 * @hw: pointer to the HW structure
2098 * @offset: offset in words of the checksum protected region
2100 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2101 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2103 static s32
igb_validate_nvm_checksum_with_offset(struct e1000_hw
*hw
,
2110 for (i
= offset
; i
< ((NVM_CHECKSUM_REG
+ offset
) + 1); i
++) {
2111 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
2113 hw_dbg("NVM Read Error\n");
2116 checksum
+= nvm_data
;
2119 if (checksum
!= (u16
) NVM_SUM
) {
2120 hw_dbg("NVM Checksum Invalid\n");
2121 ret_val
= -E1000_ERR_NVM
;
2130 * igb_update_nvm_checksum_with_offset - Update EEPROM
2132 * @hw: pointer to the HW structure
2133 * @offset: offset in words of the checksum protected region
2135 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2136 * up to the checksum. Then calculates the EEPROM checksum and writes the
2137 * value to the EEPROM.
2139 static s32
igb_update_nvm_checksum_with_offset(struct e1000_hw
*hw
, u16 offset
)
2145 for (i
= offset
; i
< (NVM_CHECKSUM_REG
+ offset
); i
++) {
2146 ret_val
= hw
->nvm
.ops
.read(hw
, i
, 1, &nvm_data
);
2148 hw_dbg("NVM Read Error while updating checksum.\n");
2151 checksum
+= nvm_data
;
2153 checksum
= (u16
) NVM_SUM
- checksum
;
2154 ret_val
= hw
->nvm
.ops
.write(hw
, (NVM_CHECKSUM_REG
+ offset
), 1,
2157 hw_dbg("NVM Write Error while updating checksum.\n");
2164 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2165 * @hw: pointer to the HW structure
2167 * Calculates the EEPROM section checksum by reading/adding each word of
2168 * the EEPROM and then verifies that the sum of the EEPROM is
2171 static s32
igb_validate_nvm_checksum_82580(struct e1000_hw
*hw
)
2174 u16 eeprom_regions_count
= 1;
2178 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPATIBILITY_REG_3
, 1, &nvm_data
);
2180 hw_dbg("NVM Read Error\n");
2184 if (nvm_data
& NVM_COMPATIBILITY_BIT_MASK
) {
2185 /* if checksums compatibility bit is set validate checksums
2188 eeprom_regions_count
= 4;
2191 for (j
= 0; j
< eeprom_regions_count
; j
++) {
2192 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2193 ret_val
= igb_validate_nvm_checksum_with_offset(hw
,
2204 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2205 * @hw: pointer to the HW structure
2207 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2208 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2209 * checksum and writes the value to the EEPROM.
2211 static s32
igb_update_nvm_checksum_82580(struct e1000_hw
*hw
)
2217 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_COMPATIBILITY_REG_3
, 1, &nvm_data
);
2219 hw_dbg("NVM Read Error while updating checksum"
2220 " compatibility bit.\n");
2224 if ((nvm_data
& NVM_COMPATIBILITY_BIT_MASK
) == 0) {
2225 /* set compatibility bit to validate checksums appropriately */
2226 nvm_data
= nvm_data
| NVM_COMPATIBILITY_BIT_MASK
;
2227 ret_val
= hw
->nvm
.ops
.write(hw
, NVM_COMPATIBILITY_REG_3
, 1,
2230 hw_dbg("NVM Write Error while updating checksum"
2231 " compatibility bit.\n");
2236 for (j
= 0; j
< 4; j
++) {
2237 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2238 ret_val
= igb_update_nvm_checksum_with_offset(hw
, nvm_offset
);
2248 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2249 * @hw: pointer to the HW structure
2251 * Calculates the EEPROM section checksum by reading/adding each word of
2252 * the EEPROM and then verifies that the sum of the EEPROM is
2255 static s32
igb_validate_nvm_checksum_i350(struct e1000_hw
*hw
)
2261 for (j
= 0; j
< 4; j
++) {
2262 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2263 ret_val
= igb_validate_nvm_checksum_with_offset(hw
,
2274 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2275 * @hw: pointer to the HW structure
2277 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2278 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2279 * checksum and writes the value to the EEPROM.
2281 static s32
igb_update_nvm_checksum_i350(struct e1000_hw
*hw
)
2287 for (j
= 0; j
< 4; j
++) {
2288 nvm_offset
= NVM_82580_LAN_FUNC_OFFSET(j
);
2289 ret_val
= igb_update_nvm_checksum_with_offset(hw
, nvm_offset
);
2299 * __igb_access_emi_reg - Read/write EMI register
2300 * @hw: pointer to the HW structure
2301 * @addr: EMI address to program
2302 * @data: pointer to value to read/write from/to the EMI address
2303 * @read: boolean flag to indicate read or write
2305 static s32
__igb_access_emi_reg(struct e1000_hw
*hw
, u16 address
,
2306 u16
*data
, bool read
)
2308 s32 ret_val
= E1000_SUCCESS
;
2310 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_EMIADD
, address
);
2315 ret_val
= hw
->phy
.ops
.read_reg(hw
, E1000_EMIDATA
, data
);
2317 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_EMIDATA
, *data
);
2323 * igb_read_emi_reg - Read Extended Management Interface register
2324 * @hw: pointer to the HW structure
2325 * @addr: EMI address to program
2326 * @data: value to be read from the EMI address
2328 s32
igb_read_emi_reg(struct e1000_hw
*hw
, u16 addr
, u16
*data
)
2330 return __igb_access_emi_reg(hw
, addr
, data
, true);
2334 * igb_set_eee_i350 - Enable/disable EEE support
2335 * @hw: pointer to the HW structure
2337 * Enable/disable EEE based on setting in dev_spec structure.
2340 s32
igb_set_eee_i350(struct e1000_hw
*hw
)
2345 if ((hw
->mac
.type
< e1000_i350
) ||
2346 (hw
->phy
.media_type
!= e1000_media_type_copper
))
2348 ipcnfg
= rd32(E1000_IPCNFG
);
2349 eeer
= rd32(E1000_EEER
);
2351 /* enable or disable per user setting */
2352 if (!(hw
->dev_spec
._82575
.eee_disable
)) {
2353 u32 eee_su
= rd32(E1000_EEE_SU
);
2355 ipcnfg
|= (E1000_IPCNFG_EEE_1G_AN
| E1000_IPCNFG_EEE_100M_AN
);
2356 eeer
|= (E1000_EEER_TX_LPI_EN
| E1000_EEER_RX_LPI_EN
|
2359 /* This bit should not be set in normal operation. */
2360 if (eee_su
& E1000_EEE_SU_LPI_CLK_STP
)
2361 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2364 ipcnfg
&= ~(E1000_IPCNFG_EEE_1G_AN
|
2365 E1000_IPCNFG_EEE_100M_AN
);
2366 eeer
&= ~(E1000_EEER_TX_LPI_EN
|
2367 E1000_EEER_RX_LPI_EN
|
2370 wr32(E1000_IPCNFG
, ipcnfg
);
2371 wr32(E1000_EEER
, eeer
);
2380 * igb_set_eee_i354 - Enable/disable EEE support
2381 * @hw: pointer to the HW structure
2383 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2386 s32
igb_set_eee_i354(struct e1000_hw
*hw
)
2388 struct e1000_phy_info
*phy
= &hw
->phy
;
2392 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
2393 (phy
->id
!= M88E1545_E_PHY_ID
))
2396 if (!hw
->dev_spec
._82575
.eee_disable
) {
2397 /* Switch to PHY page 18. */
2398 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_PAGE_ADDR
, 18);
2402 ret_val
= phy
->ops
.read_reg(hw
, E1000_M88E1545_EEE_CTRL_1
,
2407 phy_data
|= E1000_M88E1545_EEE_CTRL_1_MS
;
2408 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_EEE_CTRL_1
,
2413 /* Return the PHY to page 0. */
2414 ret_val
= phy
->ops
.write_reg(hw
, E1000_M88E1545_PAGE_ADDR
, 0);
2418 /* Turn on EEE advertisement. */
2419 ret_val
= igb_read_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2420 E1000_EEE_ADV_DEV_I354
,
2425 phy_data
|= E1000_EEE_ADV_100_SUPPORTED
|
2426 E1000_EEE_ADV_1000_SUPPORTED
;
2427 ret_val
= igb_write_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2428 E1000_EEE_ADV_DEV_I354
,
2431 /* Turn off EEE advertisement. */
2432 ret_val
= igb_read_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2433 E1000_EEE_ADV_DEV_I354
,
2438 phy_data
&= ~(E1000_EEE_ADV_100_SUPPORTED
|
2439 E1000_EEE_ADV_1000_SUPPORTED
);
2440 ret_val
= igb_write_xmdio_reg(hw
, E1000_EEE_ADV_ADDR_I354
,
2441 E1000_EEE_ADV_DEV_I354
,
2450 * igb_get_eee_status_i354 - Get EEE status
2451 * @hw: pointer to the HW structure
2452 * @status: EEE status
2454 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2457 s32
igb_get_eee_status_i354(struct e1000_hw
*hw
, bool *status
)
2459 struct e1000_phy_info
*phy
= &hw
->phy
;
2463 /* Check if EEE is supported on this device. */
2464 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
2465 (phy
->id
!= M88E1545_E_PHY_ID
))
2468 ret_val
= igb_read_xmdio_reg(hw
, E1000_PCS_STATUS_ADDR_I354
,
2469 E1000_PCS_STATUS_DEV_I354
,
2474 *status
= phy_data
& (E1000_PCS_STATUS_TX_LPI_RCVD
|
2475 E1000_PCS_STATUS_RX_LPI_RCVD
) ? true : false;
2481 static const u8 e1000_emc_temp_data
[4] = {
2482 E1000_EMC_INTERNAL_DATA
,
2483 E1000_EMC_DIODE1_DATA
,
2484 E1000_EMC_DIODE2_DATA
,
2485 E1000_EMC_DIODE3_DATA
2487 static const u8 e1000_emc_therm_limit
[4] = {
2488 E1000_EMC_INTERNAL_THERM_LIMIT
,
2489 E1000_EMC_DIODE1_THERM_LIMIT
,
2490 E1000_EMC_DIODE2_THERM_LIMIT
,
2491 E1000_EMC_DIODE3_THERM_LIMIT
2495 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2496 * @hw: pointer to hardware structure
2498 * Updates the temperatures in mac.thermal_sensor_data
2500 s32
igb_get_thermal_sensor_data_generic(struct e1000_hw
*hw
)
2502 s32 status
= E1000_SUCCESS
;
2510 struct e1000_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
2512 if ((hw
->mac
.type
!= e1000_i350
) || (hw
->bus
.func
!= 0))
2513 return E1000_NOT_IMPLEMENTED
;
2515 data
->sensor
[0].temp
= (rd32(E1000_THMJT
) & 0xFF);
2517 /* Return the internal sensor only if ETS is unsupported */
2518 hw
->nvm
.ops
.read(hw
, NVM_ETS_CFG
, 1, &ets_offset
);
2519 if ((ets_offset
== 0x0000) || (ets_offset
== 0xFFFF))
2522 hw
->nvm
.ops
.read(hw
, ets_offset
, 1, &ets_cfg
);
2523 if (((ets_cfg
& NVM_ETS_TYPE_MASK
) >> NVM_ETS_TYPE_SHIFT
)
2524 != NVM_ETS_TYPE_EMC
)
2525 return E1000_NOT_IMPLEMENTED
;
2527 num_sensors
= (ets_cfg
& NVM_ETS_NUM_SENSORS_MASK
);
2528 if (num_sensors
> E1000_MAX_SENSORS
)
2529 num_sensors
= E1000_MAX_SENSORS
;
2531 for (i
= 1; i
< num_sensors
; i
++) {
2532 hw
->nvm
.ops
.read(hw
, (ets_offset
+ i
), 1, &ets_sensor
);
2533 sensor_index
= ((ets_sensor
& NVM_ETS_DATA_INDEX_MASK
) >>
2534 NVM_ETS_DATA_INDEX_SHIFT
);
2535 sensor_location
= ((ets_sensor
& NVM_ETS_DATA_LOC_MASK
) >>
2536 NVM_ETS_DATA_LOC_SHIFT
);
2538 if (sensor_location
!= 0)
2539 hw
->phy
.ops
.read_i2c_byte(hw
,
2540 e1000_emc_temp_data
[sensor_index
],
2541 E1000_I2C_THERMAL_SENSOR_ADDR
,
2542 &data
->sensor
[i
].temp
);
2548 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2549 * @hw: pointer to hardware structure
2551 * Sets the thermal sensor thresholds according to the NVM map
2552 * and save off the threshold and location values into mac.thermal_sensor_data
2554 s32
igb_init_thermal_sensor_thresh_generic(struct e1000_hw
*hw
)
2556 s32 status
= E1000_SUCCESS
;
2560 u8 low_thresh_delta
;
2566 struct e1000_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
2568 if ((hw
->mac
.type
!= e1000_i350
) || (hw
->bus
.func
!= 0))
2569 return E1000_NOT_IMPLEMENTED
;
2571 memset(data
, 0, sizeof(struct e1000_thermal_sensor_data
));
2573 data
->sensor
[0].location
= 0x1;
2574 data
->sensor
[0].caution_thresh
=
2575 (rd32(E1000_THHIGHTC
) & 0xFF);
2576 data
->sensor
[0].max_op_thresh
=
2577 (rd32(E1000_THLOWTC
) & 0xFF);
2579 /* Return the internal sensor only if ETS is unsupported */
2580 hw
->nvm
.ops
.read(hw
, NVM_ETS_CFG
, 1, &ets_offset
);
2581 if ((ets_offset
== 0x0000) || (ets_offset
== 0xFFFF))
2584 hw
->nvm
.ops
.read(hw
, ets_offset
, 1, &ets_cfg
);
2585 if (((ets_cfg
& NVM_ETS_TYPE_MASK
) >> NVM_ETS_TYPE_SHIFT
)
2586 != NVM_ETS_TYPE_EMC
)
2587 return E1000_NOT_IMPLEMENTED
;
2589 low_thresh_delta
= ((ets_cfg
& NVM_ETS_LTHRES_DELTA_MASK
) >>
2590 NVM_ETS_LTHRES_DELTA_SHIFT
);
2591 num_sensors
= (ets_cfg
& NVM_ETS_NUM_SENSORS_MASK
);
2593 for (i
= 1; i
<= num_sensors
; i
++) {
2594 hw
->nvm
.ops
.read(hw
, (ets_offset
+ i
), 1, &ets_sensor
);
2595 sensor_index
= ((ets_sensor
& NVM_ETS_DATA_INDEX_MASK
) >>
2596 NVM_ETS_DATA_INDEX_SHIFT
);
2597 sensor_location
= ((ets_sensor
& NVM_ETS_DATA_LOC_MASK
) >>
2598 NVM_ETS_DATA_LOC_SHIFT
);
2599 therm_limit
= ets_sensor
& NVM_ETS_DATA_HTHRESH_MASK
;
2601 hw
->phy
.ops
.write_i2c_byte(hw
,
2602 e1000_emc_therm_limit
[sensor_index
],
2603 E1000_I2C_THERMAL_SENSOR_ADDR
,
2606 if ((i
< E1000_MAX_SENSORS
) && (sensor_location
!= 0)) {
2607 data
->sensor
[i
].location
= sensor_location
;
2608 data
->sensor
[i
].caution_thresh
= therm_limit
;
2609 data
->sensor
[i
].max_op_thresh
= therm_limit
-
2616 static struct e1000_mac_operations e1000_mac_ops_82575
= {
2617 .init_hw
= igb_init_hw_82575
,
2618 .check_for_link
= igb_check_for_link_82575
,
2619 .rar_set
= igb_rar_set
,
2620 .read_mac_addr
= igb_read_mac_addr_82575
,
2621 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
2622 #ifdef CONFIG_IGB_HWMON
2623 .get_thermal_sensor_data
= igb_get_thermal_sensor_data_generic
,
2624 .init_thermal_sensor_thresh
= igb_init_thermal_sensor_thresh_generic
,
2628 static struct e1000_phy_operations e1000_phy_ops_82575
= {
2629 .acquire
= igb_acquire_phy_82575
,
2630 .get_cfg_done
= igb_get_cfg_done_82575
,
2631 .release
= igb_release_phy_82575
,
2632 .write_i2c_byte
= igb_write_i2c_byte
,
2633 .read_i2c_byte
= igb_read_i2c_byte
,
2636 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
2637 .acquire
= igb_acquire_nvm_82575
,
2638 .read
= igb_read_nvm_eerd
,
2639 .release
= igb_release_nvm_82575
,
2640 .write
= igb_write_nvm_spi
,
2643 const struct e1000_info e1000_82575_info
= {
2644 .get_invariants
= igb_get_invariants_82575
,
2645 .mac_ops
= &e1000_mac_ops_82575
,
2646 .phy_ops
= &e1000_phy_ops_82575
,
2647 .nvm_ops
= &e1000_nvm_ops_82575
,