1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 ******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/if_ether.h>
36 #include "e1000_i210.h"
39 * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
40 * @hw: pointer to the HW structure
42 * Acquire the HW semaphore to access the PHY or NVM
44 static s32
igb_get_hw_semaphore_i210(struct e1000_hw
*hw
)
47 s32 timeout
= hw
->nvm
.word_size
+ 1;
50 /* Get the SW semaphore */
52 swsm
= rd32(E1000_SWSM
);
53 if (!(swsm
& E1000_SWSM_SMBI
))
61 /* In rare circumstances, the SW semaphore may already be held
62 * unintentionally. Clear the semaphore once before giving up.
64 if (hw
->dev_spec
._82575
.clear_semaphore_once
) {
65 hw
->dev_spec
._82575
.clear_semaphore_once
= false;
66 igb_put_hw_semaphore(hw
);
67 for (i
= 0; i
< timeout
; i
++) {
68 swsm
= rd32(E1000_SWSM
);
69 if (!(swsm
& E1000_SWSM_SMBI
))
76 /* If we do not have the semaphore here, we have to give up. */
78 hw_dbg("Driver can't access device - SMBI bit is set.\n");
79 return -E1000_ERR_NVM
;
83 /* Get the FW semaphore. */
84 for (i
= 0; i
< timeout
; i
++) {
85 swsm
= rd32(E1000_SWSM
);
86 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
88 /* Semaphore acquired if bit latched */
89 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
96 /* Release semaphores */
97 igb_put_hw_semaphore(hw
);
98 hw_dbg("Driver can't access the NVM\n");
99 return -E1000_ERR_NVM
;
102 return E1000_SUCCESS
;
106 * igb_acquire_nvm_i210 - Request for access to EEPROM
107 * @hw: pointer to the HW structure
109 * Acquire the necessary semaphores for exclusive access to the EEPROM.
110 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
111 * Return successful if access grant bit set, else clear the request for
112 * EEPROM access and return -E1000_ERR_NVM (-1).
114 s32
igb_acquire_nvm_i210(struct e1000_hw
*hw
)
116 return igb_acquire_swfw_sync_i210(hw
, E1000_SWFW_EEP_SM
);
120 * igb_release_nvm_i210 - Release exclusive access to EEPROM
121 * @hw: pointer to the HW structure
123 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
124 * then release the semaphores acquired.
126 void igb_release_nvm_i210(struct e1000_hw
*hw
)
128 igb_release_swfw_sync_i210(hw
, E1000_SWFW_EEP_SM
);
132 * igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
133 * @hw: pointer to the HW structure
134 * @mask: specifies which semaphore to acquire
136 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
137 * will also specify which port we're acquiring the lock for.
139 s32
igb_acquire_swfw_sync_i210(struct e1000_hw
*hw
, u16 mask
)
143 u32 fwmask
= mask
<< 16;
144 s32 ret_val
= E1000_SUCCESS
;
145 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
147 while (i
< timeout
) {
148 if (igb_get_hw_semaphore_i210(hw
)) {
149 ret_val
= -E1000_ERR_SWFW_SYNC
;
153 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
154 if (!(swfw_sync
& (fwmask
| swmask
)))
157 /* Firmware currently using resource (fwmask) */
158 igb_put_hw_semaphore(hw
);
164 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
165 ret_val
= -E1000_ERR_SWFW_SYNC
;
170 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
172 igb_put_hw_semaphore(hw
);
178 * igb_release_swfw_sync_i210 - Release SW/FW semaphore
179 * @hw: pointer to the HW structure
180 * @mask: specifies which semaphore to acquire
182 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
183 * will also specify which port we're releasing the lock for.
185 void igb_release_swfw_sync_i210(struct e1000_hw
*hw
, u16 mask
)
189 while (igb_get_hw_semaphore_i210(hw
) != E1000_SUCCESS
)
192 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
194 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
196 igb_put_hw_semaphore(hw
);
200 * igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
201 * @hw: pointer to the HW structure
202 * @offset: offset of word in the Shadow Ram to read
203 * @words: number of words to read
204 * @data: word read from the Shadow Ram
206 * Reads a 16 bit word from the Shadow Ram using the EERD register.
207 * Uses necessary synchronization semaphores.
209 s32
igb_read_nvm_srrd_i210(struct e1000_hw
*hw
, u16 offset
, u16 words
,
212 s32 status
= E1000_SUCCESS
;
215 /* We cannot hold synchronization semaphores for too long,
216 * because of forceful takeover procedure. However it is more efficient
217 * to read in bursts than synchronizing access for each word.
219 for (i
= 0; i
< words
; i
+= E1000_EERD_EEWR_MAX_COUNT
) {
220 count
= (words
- i
) / E1000_EERD_EEWR_MAX_COUNT
> 0 ?
221 E1000_EERD_EEWR_MAX_COUNT
: (words
- i
);
222 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
223 status
= igb_read_nvm_eerd(hw
, offset
, count
,
225 hw
->nvm
.ops
.release(hw
);
227 status
= E1000_ERR_SWFW_SYNC
;
230 if (status
!= E1000_SUCCESS
)
238 * igb_write_nvm_srwr - Write to Shadow Ram using EEWR
239 * @hw: pointer to the HW structure
240 * @offset: offset within the Shadow Ram to be written to
241 * @words: number of words to write
242 * @data: 16 bit word(s) to be written to the Shadow Ram
244 * Writes data to Shadow Ram at offset using EEWR register.
246 * If igb_update_nvm_checksum is not called after this function , the
247 * Shadow Ram will most likely contain an invalid checksum.
249 static s32
igb_write_nvm_srwr(struct e1000_hw
*hw
, u16 offset
, u16 words
,
252 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
254 u32 attempts
= 100000;
255 s32 ret_val
= E1000_SUCCESS
;
257 /* A check for invalid values: offset too large, too many words,
258 * too many words for the offset, and not enough words.
260 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
262 hw_dbg("nvm parameter(s) out of bounds\n");
263 ret_val
= -E1000_ERR_NVM
;
267 for (i
= 0; i
< words
; i
++) {
268 eewr
= ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) |
269 (data
[i
] << E1000_NVM_RW_REG_DATA
) |
270 E1000_NVM_RW_REG_START
;
272 wr32(E1000_SRWR
, eewr
);
274 for (k
= 0; k
< attempts
; k
++) {
275 if (E1000_NVM_RW_REG_DONE
&
277 ret_val
= E1000_SUCCESS
;
283 if (ret_val
!= E1000_SUCCESS
) {
284 hw_dbg("Shadow RAM write EEWR timed out\n");
294 * igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
295 * @hw: pointer to the HW structure
296 * @offset: offset within the Shadow RAM to be written to
297 * @words: number of words to write
298 * @data: 16 bit word(s) to be written to the Shadow RAM
300 * Writes data to Shadow RAM at offset using EEWR register.
302 * If e1000_update_nvm_checksum is not called after this function , the
303 * data will not be committed to FLASH and also Shadow RAM will most likely
304 * contain an invalid checksum.
306 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
309 s32
igb_write_nvm_srwr_i210(struct e1000_hw
*hw
, u16 offset
, u16 words
,
312 s32 status
= E1000_SUCCESS
;
315 /* We cannot hold synchronization semaphores for too long,
316 * because of forceful takeover procedure. However it is more efficient
317 * to write in bursts than synchronizing access for each word.
319 for (i
= 0; i
< words
; i
+= E1000_EERD_EEWR_MAX_COUNT
) {
320 count
= (words
- i
) / E1000_EERD_EEWR_MAX_COUNT
> 0 ?
321 E1000_EERD_EEWR_MAX_COUNT
: (words
- i
);
322 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
323 status
= igb_write_nvm_srwr(hw
, offset
, count
,
325 hw
->nvm
.ops
.release(hw
);
327 status
= E1000_ERR_SWFW_SYNC
;
330 if (status
!= E1000_SUCCESS
)
338 * igb_read_nvm_i211 - Read NVM wrapper function for I211
339 * @hw: pointer to the HW structure
340 * @words: number of words to read
341 * @data: pointer to the data read
343 * Wrapper function to return data formerly found in the NVM.
345 s32
igb_read_nvm_i211(struct e1000_hw
*hw
, u16 offset
, u16 words
,
348 s32 ret_val
= E1000_SUCCESS
;
350 /* Only the MAC addr is required to be present in the iNVM */
353 ret_val
= igb_read_invm_i211(hw
, offset
, &data
[0]);
354 ret_val
|= igb_read_invm_i211(hw
, offset
+1, &data
[1]);
355 ret_val
|= igb_read_invm_i211(hw
, offset
+2, &data
[2]);
356 if (ret_val
!= E1000_SUCCESS
)
357 hw_dbg("MAC Addr not found in iNVM\n");
359 case NVM_INIT_CTRL_2
:
360 ret_val
= igb_read_invm_i211(hw
, (u8
)offset
, data
);
361 if (ret_val
!= E1000_SUCCESS
) {
362 *data
= NVM_INIT_CTRL_2_DEFAULT_I211
;
363 ret_val
= E1000_SUCCESS
;
366 case NVM_INIT_CTRL_4
:
367 ret_val
= igb_read_invm_i211(hw
, (u8
)offset
, data
);
368 if (ret_val
!= E1000_SUCCESS
) {
369 *data
= NVM_INIT_CTRL_4_DEFAULT_I211
;
370 ret_val
= E1000_SUCCESS
;
374 ret_val
= igb_read_invm_i211(hw
, (u8
)offset
, data
);
375 if (ret_val
!= E1000_SUCCESS
) {
376 *data
= NVM_LED_1_CFG_DEFAULT_I211
;
377 ret_val
= E1000_SUCCESS
;
380 case NVM_LED_0_2_CFG
:
381 igb_read_invm_i211(hw
, offset
, data
);
382 if (ret_val
!= E1000_SUCCESS
) {
383 *data
= NVM_LED_0_2_CFG_DEFAULT_I211
;
384 ret_val
= E1000_SUCCESS
;
387 case NVM_ID_LED_SETTINGS
:
388 ret_val
= igb_read_invm_i211(hw
, (u8
)offset
, data
);
389 if (ret_val
!= E1000_SUCCESS
) {
390 *data
= ID_LED_RESERVED_FFFF
;
391 ret_val
= E1000_SUCCESS
;
394 *data
= hw
->subsystem_device_id
;
397 *data
= hw
->subsystem_vendor_id
;
400 *data
= hw
->device_id
;
403 *data
= hw
->vendor_id
;
406 hw_dbg("NVM word 0x%02x is not mapped.\n", offset
);
407 *data
= NVM_RESERVED_WORD
;
414 * igb_read_invm_i211 - Reads OTP
415 * @hw: pointer to the HW structure
416 * @address: the word address (aka eeprom offset) to read
417 * @data: pointer to the data read
419 * Reads 16-bit words from the OTP. Return error when the word is not
422 s32
igb_read_invm_i211(struct e1000_hw
*hw
, u16 address
, u16
*data
)
424 s32 status
= -E1000_ERR_INVM_VALUE_NOT_FOUND
;
427 u8 record_type
, word_address
;
429 for (i
= 0; i
< E1000_INVM_SIZE
; i
++) {
430 invm_dword
= rd32(E1000_INVM_DATA_REG(i
));
431 /* Get record type */
432 record_type
= INVM_DWORD_TO_RECORD_TYPE(invm_dword
);
433 if (record_type
== E1000_INVM_UNINITIALIZED_STRUCTURE
)
435 if (record_type
== E1000_INVM_CSR_AUTOLOAD_STRUCTURE
)
436 i
+= E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS
;
437 if (record_type
== E1000_INVM_RSA_KEY_SHA256_STRUCTURE
)
438 i
+= E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS
;
439 if (record_type
== E1000_INVM_WORD_AUTOLOAD_STRUCTURE
) {
440 word_address
= INVM_DWORD_TO_WORD_ADDRESS(invm_dword
);
441 if (word_address
== (u8
)address
) {
442 *data
= INVM_DWORD_TO_WORD_DATA(invm_dword
);
443 hw_dbg("Read INVM Word 0x%02x = %x",
445 status
= E1000_SUCCESS
;
450 if (status
!= E1000_SUCCESS
)
451 hw_dbg("Requested word 0x%02x not found in OTP\n", address
);
456 * igb_read_invm_version - Reads iNVM version and image type
457 * @hw: pointer to the HW structure
458 * @invm_ver: version structure for the version read
460 * Reads iNVM version and image type.
462 s32
igb_read_invm_version(struct e1000_hw
*hw
,
463 struct e1000_fw_version
*invm_ver
) {
465 u32
*next_record
= NULL
;
468 u32 invm_blocks
= E1000_INVM_SIZE
- (E1000_INVM_ULT_BYTES_SIZE
/
469 E1000_INVM_RECORD_SIZE_IN_BYTES
);
470 u32 buffer
[E1000_INVM_SIZE
];
471 s32 status
= -E1000_ERR_INVM_VALUE_NOT_FOUND
;
474 /* Read iNVM memory */
475 for (i
= 0; i
< E1000_INVM_SIZE
; i
++) {
476 invm_dword
= rd32(E1000_INVM_DATA_REG(i
));
477 buffer
[i
] = invm_dword
;
480 /* Read version number */
481 for (i
= 1; i
< invm_blocks
; i
++) {
482 record
= &buffer
[invm_blocks
- i
];
483 next_record
= &buffer
[invm_blocks
- i
+ 1];
485 /* Check if we have first version location used */
486 if ((i
== 1) && ((*record
& E1000_INVM_VER_FIELD_ONE
) == 0)) {
488 status
= E1000_SUCCESS
;
491 /* Check if we have second version location used */
493 ((*record
& E1000_INVM_VER_FIELD_TWO
) == 0)) {
494 version
= (*record
& E1000_INVM_VER_FIELD_ONE
) >> 3;
495 status
= E1000_SUCCESS
;
498 /* Check if we have odd version location
499 * used and it is the last one used
501 else if ((((*record
& E1000_INVM_VER_FIELD_ONE
) == 0) &&
502 ((*record
& 0x3) == 0)) || (((*record
& 0x3) != 0) &&
504 version
= (*next_record
& E1000_INVM_VER_FIELD_TWO
)
506 status
= E1000_SUCCESS
;
509 /* Check if we have even version location
510 * used and it is the last one used
512 else if (((*record
& E1000_INVM_VER_FIELD_TWO
) == 0) &&
513 ((*record
& 0x3) == 0)) {
514 version
= (*record
& E1000_INVM_VER_FIELD_ONE
) >> 3;
515 status
= E1000_SUCCESS
;
520 if (status
== E1000_SUCCESS
) {
521 invm_ver
->invm_major
= (version
& E1000_INVM_MAJOR_MASK
)
522 >> E1000_INVM_MAJOR_SHIFT
;
523 invm_ver
->invm_minor
= version
& E1000_INVM_MINOR_MASK
;
525 /* Read Image Type */
526 for (i
= 1; i
< invm_blocks
; i
++) {
527 record
= &buffer
[invm_blocks
- i
];
528 next_record
= &buffer
[invm_blocks
- i
+ 1];
530 /* Check if we have image type in first location used */
531 if ((i
== 1) && ((*record
& E1000_INVM_IMGTYPE_FIELD
) == 0)) {
532 invm_ver
->invm_img_type
= 0;
533 status
= E1000_SUCCESS
;
536 /* Check if we have image type in first location used */
537 else if ((((*record
& 0x3) == 0) &&
538 ((*record
& E1000_INVM_IMGTYPE_FIELD
) == 0)) ||
539 ((((*record
& 0x3) != 0) && (i
!= 1)))) {
540 invm_ver
->invm_img_type
=
541 (*next_record
& E1000_INVM_IMGTYPE_FIELD
) >> 23;
542 status
= E1000_SUCCESS
;
550 * igb_validate_nvm_checksum_i210 - Validate EEPROM checksum
551 * @hw: pointer to the HW structure
553 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
554 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
556 s32
igb_validate_nvm_checksum_i210(struct e1000_hw
*hw
)
558 s32 status
= E1000_SUCCESS
;
559 s32 (*read_op_ptr
)(struct e1000_hw
*, u16
, u16
, u16
*);
561 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
563 /* Replace the read function with semaphore grabbing with
564 * the one that skips this for a while.
565 * We have semaphore taken already here.
567 read_op_ptr
= hw
->nvm
.ops
.read
;
568 hw
->nvm
.ops
.read
= igb_read_nvm_eerd
;
570 status
= igb_validate_nvm_checksum(hw
);
572 /* Revert original read operation. */
573 hw
->nvm
.ops
.read
= read_op_ptr
;
575 hw
->nvm
.ops
.release(hw
);
577 status
= E1000_ERR_SWFW_SYNC
;
584 * igb_update_nvm_checksum_i210 - Update EEPROM checksum
585 * @hw: pointer to the HW structure
587 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
588 * up to the checksum. Then calculates the EEPROM checksum and writes the
589 * value to the EEPROM. Next commit EEPROM data onto the Flash.
591 s32
igb_update_nvm_checksum_i210(struct e1000_hw
*hw
)
593 s32 ret_val
= E1000_SUCCESS
;
597 /* Read the first word from the EEPROM. If this times out or fails, do
598 * not continue or we could be in for a very long wait while every
601 ret_val
= igb_read_nvm_eerd(hw
, 0, 1, &nvm_data
);
602 if (ret_val
!= E1000_SUCCESS
) {
603 hw_dbg("EEPROM read failed\n");
607 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
608 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
609 * because we do not want to take the synchronization
610 * semaphores twice here.
613 for (i
= 0; i
< NVM_CHECKSUM_REG
; i
++) {
614 ret_val
= igb_read_nvm_eerd(hw
, i
, 1, &nvm_data
);
616 hw
->nvm
.ops
.release(hw
);
617 hw_dbg("NVM Read Error while updating checksum.\n");
620 checksum
+= nvm_data
;
622 checksum
= (u16
) NVM_SUM
- checksum
;
623 ret_val
= igb_write_nvm_srwr(hw
, NVM_CHECKSUM_REG
, 1,
625 if (ret_val
!= E1000_SUCCESS
) {
626 hw
->nvm
.ops
.release(hw
);
627 hw_dbg("NVM Write Error while updating checksum.\n");
631 hw
->nvm
.ops
.release(hw
);
633 ret_val
= igb_update_flash_i210(hw
);
635 ret_val
= -E1000_ERR_SWFW_SYNC
;
642 * igb_pool_flash_update_done_i210 - Pool FLUDONE status.
643 * @hw: pointer to the HW structure
646 static s32
igb_pool_flash_update_done_i210(struct e1000_hw
*hw
)
648 s32 ret_val
= -E1000_ERR_NVM
;
651 for (i
= 0; i
< E1000_FLUDONE_ATTEMPTS
; i
++) {
652 reg
= rd32(E1000_EECD
);
653 if (reg
& E1000_EECD_FLUDONE_I210
) {
654 ret_val
= E1000_SUCCESS
;
664 * igb_get_flash_presence_i210 - Check if flash device is detected.
665 * @hw: pointer to the HW structure
668 bool igb_get_flash_presence_i210(struct e1000_hw
*hw
)
671 bool ret_val
= false;
673 eec
= rd32(E1000_EECD
);
674 if (eec
& E1000_EECD_FLASH_DETECTED_I210
)
681 * igb_update_flash_i210 - Commit EEPROM to the flash
682 * @hw: pointer to the HW structure
685 s32
igb_update_flash_i210(struct e1000_hw
*hw
)
687 s32 ret_val
= E1000_SUCCESS
;
690 ret_val
= igb_pool_flash_update_done_i210(hw
);
691 if (ret_val
== -E1000_ERR_NVM
) {
692 hw_dbg("Flash update time out\n");
696 flup
= rd32(E1000_EECD
) | E1000_EECD_FLUPD_I210
;
697 wr32(E1000_EECD
, flup
);
699 ret_val
= igb_pool_flash_update_done_i210(hw
);
700 if (ret_val
== E1000_SUCCESS
)
701 hw_dbg("Flash update complete\n");
703 hw_dbg("Flash update time out\n");
710 * igb_valid_led_default_i210 - Verify a valid default LED config
711 * @hw: pointer to the HW structure
712 * @data: pointer to the NVM (EEPROM)
714 * Read the EEPROM for the current default LED configuration. If the
715 * LED configuration is not valid, set to a valid LED configuration.
717 s32
igb_valid_led_default_i210(struct e1000_hw
*hw
, u16
*data
)
721 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
723 hw_dbg("NVM Read Error\n");
727 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
) {
728 switch (hw
->phy
.media_type
) {
729 case e1000_media_type_internal_serdes
:
730 *data
= ID_LED_DEFAULT_I210_SERDES
;
732 case e1000_media_type_copper
:
734 *data
= ID_LED_DEFAULT_I210
;
743 * __igb_access_xmdio_reg - Read/write XMDIO register
744 * @hw: pointer to the HW structure
745 * @address: XMDIO address to program
746 * @dev_addr: device address to program
747 * @data: pointer to value to read/write from/to the XMDIO address
748 * @read: boolean flag to indicate read or write
750 static s32
__igb_access_xmdio_reg(struct e1000_hw
*hw
, u16 address
,
751 u8 dev_addr
, u16
*data
, bool read
)
753 s32 ret_val
= E1000_SUCCESS
;
755 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, dev_addr
);
759 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAAD
, address
);
763 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, E1000_MMDAC_FUNC_DATA
|
769 ret_val
= hw
->phy
.ops
.read_reg(hw
, E1000_MMDAAD
, data
);
771 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAAD
, *data
);
775 /* Recalibrate the device back to 0 */
776 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, 0);
784 * igb_read_xmdio_reg - Read XMDIO register
785 * @hw: pointer to the HW structure
786 * @addr: XMDIO address to program
787 * @dev_addr: device address to program
788 * @data: value to be read from the EMI address
790 s32
igb_read_xmdio_reg(struct e1000_hw
*hw
, u16 addr
, u8 dev_addr
, u16
*data
)
792 return __igb_access_xmdio_reg(hw
, addr
, dev_addr
, data
, true);
796 * igb_write_xmdio_reg - Write XMDIO register
797 * @hw: pointer to the HW structure
798 * @addr: XMDIO address to program
799 * @dev_addr: device address to program
800 * @data: value to be written to the XMDIO address
802 s32
igb_write_xmdio_reg(struct e1000_hw
*hw
, u16 addr
, u8 dev_addr
, u16 data
)
804 return __igb_access_xmdio_reg(hw
, addr
, dev_addr
, &data
, false);
808 * igb_init_nvm_params_i210 - Init NVM func ptrs.
809 * @hw: pointer to the HW structure
811 s32
igb_init_nvm_params_i210(struct e1000_hw
*hw
)
814 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
816 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
817 nvm
->ops
.release
= igb_release_nvm_i210
;
818 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
820 /* NVM Function Pointers */
821 if (igb_get_flash_presence_i210(hw
)) {
822 hw
->nvm
.type
= e1000_nvm_flash_hw
;
823 nvm
->ops
.read
= igb_read_nvm_srrd_i210
;
824 nvm
->ops
.write
= igb_write_nvm_srwr_i210
;
825 nvm
->ops
.validate
= igb_validate_nvm_checksum_i210
;
826 nvm
->ops
.update
= igb_update_nvm_checksum_i210
;
828 hw
->nvm
.type
= e1000_nvm_invm
;
829 nvm
->ops
.read
= igb_read_nvm_i211
;
830 nvm
->ops
.write
= NULL
;
831 nvm
->ops
.validate
= NULL
;
832 nvm
->ops
.update
= NULL
;