1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 #include <linux/types.h>
29 #include <linux/if_ether.h>
32 #include "e1000_i210.h"
34 static s32
igb_update_flash_i210(struct e1000_hw
*hw
);
37 * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
38 * @hw: pointer to the HW structure
40 * Acquire the HW semaphore to access the PHY or NVM
42 static s32
igb_get_hw_semaphore_i210(struct e1000_hw
*hw
)
45 s32 timeout
= hw
->nvm
.word_size
+ 1;
48 /* Get the SW semaphore */
50 swsm
= rd32(E1000_SWSM
);
51 if (!(swsm
& E1000_SWSM_SMBI
))
59 /* In rare circumstances, the SW semaphore may already be held
60 * unintentionally. Clear the semaphore once before giving up.
62 if (hw
->dev_spec
._82575
.clear_semaphore_once
) {
63 hw
->dev_spec
._82575
.clear_semaphore_once
= false;
64 igb_put_hw_semaphore(hw
);
65 for (i
= 0; i
< timeout
; i
++) {
66 swsm
= rd32(E1000_SWSM
);
67 if (!(swsm
& E1000_SWSM_SMBI
))
74 /* If we do not have the semaphore here, we have to give up. */
76 hw_dbg("Driver can't access device - SMBI bit is set.\n");
77 return -E1000_ERR_NVM
;
81 /* Get the FW semaphore. */
82 for (i
= 0; i
< timeout
; i
++) {
83 swsm
= rd32(E1000_SWSM
);
84 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
86 /* Semaphore acquired if bit latched */
87 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
94 /* Release semaphores */
95 igb_put_hw_semaphore(hw
);
96 hw_dbg("Driver can't access the NVM\n");
97 return -E1000_ERR_NVM
;
100 return E1000_SUCCESS
;
104 * igb_acquire_nvm_i210 - Request for access to EEPROM
105 * @hw: pointer to the HW structure
107 * Acquire the necessary semaphores for exclusive access to the EEPROM.
108 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
109 * Return successful if access grant bit set, else clear the request for
110 * EEPROM access and return -E1000_ERR_NVM (-1).
112 static s32
igb_acquire_nvm_i210(struct e1000_hw
*hw
)
114 return igb_acquire_swfw_sync_i210(hw
, E1000_SWFW_EEP_SM
);
118 * igb_release_nvm_i210 - Release exclusive access to EEPROM
119 * @hw: pointer to the HW structure
121 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
122 * then release the semaphores acquired.
124 static void igb_release_nvm_i210(struct e1000_hw
*hw
)
126 igb_release_swfw_sync_i210(hw
, E1000_SWFW_EEP_SM
);
130 * igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
131 * @hw: pointer to the HW structure
132 * @mask: specifies which semaphore to acquire
134 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
135 * will also specify which port we're acquiring the lock for.
137 s32
igb_acquire_swfw_sync_i210(struct e1000_hw
*hw
, u16 mask
)
141 u32 fwmask
= mask
<< 16;
142 s32 ret_val
= E1000_SUCCESS
;
143 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
145 while (i
< timeout
) {
146 if (igb_get_hw_semaphore_i210(hw
)) {
147 ret_val
= -E1000_ERR_SWFW_SYNC
;
151 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
152 if (!(swfw_sync
& (fwmask
| swmask
)))
155 /* Firmware currently using resource (fwmask) */
156 igb_put_hw_semaphore(hw
);
162 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
163 ret_val
= -E1000_ERR_SWFW_SYNC
;
168 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
170 igb_put_hw_semaphore(hw
);
176 * igb_release_swfw_sync_i210 - Release SW/FW semaphore
177 * @hw: pointer to the HW structure
178 * @mask: specifies which semaphore to acquire
180 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
181 * will also specify which port we're releasing the lock for.
183 void igb_release_swfw_sync_i210(struct e1000_hw
*hw
, u16 mask
)
187 while (igb_get_hw_semaphore_i210(hw
) != E1000_SUCCESS
)
190 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
192 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
194 igb_put_hw_semaphore(hw
);
198 * igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
199 * @hw: pointer to the HW structure
200 * @offset: offset of word in the Shadow Ram to read
201 * @words: number of words to read
202 * @data: word read from the Shadow Ram
204 * Reads a 16 bit word from the Shadow Ram using the EERD register.
205 * Uses necessary synchronization semaphores.
207 static s32
igb_read_nvm_srrd_i210(struct e1000_hw
*hw
, u16 offset
, u16 words
,
210 s32 status
= E1000_SUCCESS
;
213 /* We cannot hold synchronization semaphores for too long,
214 * because of forceful takeover procedure. However it is more efficient
215 * to read in bursts than synchronizing access for each word.
217 for (i
= 0; i
< words
; i
+= E1000_EERD_EEWR_MAX_COUNT
) {
218 count
= (words
- i
) / E1000_EERD_EEWR_MAX_COUNT
> 0 ?
219 E1000_EERD_EEWR_MAX_COUNT
: (words
- i
);
220 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
221 status
= igb_read_nvm_eerd(hw
, offset
, count
,
223 hw
->nvm
.ops
.release(hw
);
225 status
= E1000_ERR_SWFW_SYNC
;
228 if (status
!= E1000_SUCCESS
)
236 * igb_write_nvm_srwr - Write to Shadow Ram using EEWR
237 * @hw: pointer to the HW structure
238 * @offset: offset within the Shadow Ram to be written to
239 * @words: number of words to write
240 * @data: 16 bit word(s) to be written to the Shadow Ram
242 * Writes data to Shadow Ram at offset using EEWR register.
244 * If igb_update_nvm_checksum is not called after this function , the
245 * Shadow Ram will most likely contain an invalid checksum.
247 static s32
igb_write_nvm_srwr(struct e1000_hw
*hw
, u16 offset
, u16 words
,
250 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
252 u32 attempts
= 100000;
253 s32 ret_val
= E1000_SUCCESS
;
255 /* A check for invalid values: offset too large, too many words,
256 * too many words for the offset, and not enough words.
258 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
260 hw_dbg("nvm parameter(s) out of bounds\n");
261 ret_val
= -E1000_ERR_NVM
;
265 for (i
= 0; i
< words
; i
++) {
266 eewr
= ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) |
267 (data
[i
] << E1000_NVM_RW_REG_DATA
) |
268 E1000_NVM_RW_REG_START
;
270 wr32(E1000_SRWR
, eewr
);
272 for (k
= 0; k
< attempts
; k
++) {
273 if (E1000_NVM_RW_REG_DONE
&
275 ret_val
= E1000_SUCCESS
;
281 if (ret_val
!= E1000_SUCCESS
) {
282 hw_dbg("Shadow RAM write EEWR timed out\n");
292 * igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
293 * @hw: pointer to the HW structure
294 * @offset: offset within the Shadow RAM to be written to
295 * @words: number of words to write
296 * @data: 16 bit word(s) to be written to the Shadow RAM
298 * Writes data to Shadow RAM at offset using EEWR register.
300 * If e1000_update_nvm_checksum is not called after this function , the
301 * data will not be committed to FLASH and also Shadow RAM will most likely
302 * contain an invalid checksum.
304 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
307 static s32
igb_write_nvm_srwr_i210(struct e1000_hw
*hw
, u16 offset
, u16 words
,
310 s32 status
= E1000_SUCCESS
;
313 /* We cannot hold synchronization semaphores for too long,
314 * because of forceful takeover procedure. However it is more efficient
315 * to write in bursts than synchronizing access for each word.
317 for (i
= 0; i
< words
; i
+= E1000_EERD_EEWR_MAX_COUNT
) {
318 count
= (words
- i
) / E1000_EERD_EEWR_MAX_COUNT
> 0 ?
319 E1000_EERD_EEWR_MAX_COUNT
: (words
- i
);
320 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
321 status
= igb_write_nvm_srwr(hw
, offset
, count
,
323 hw
->nvm
.ops
.release(hw
);
325 status
= E1000_ERR_SWFW_SYNC
;
328 if (status
!= E1000_SUCCESS
)
336 * igb_read_invm_word_i210 - Reads OTP
337 * @hw: pointer to the HW structure
338 * @address: the word address (aka eeprom offset) to read
339 * @data: pointer to the data read
341 * Reads 16-bit words from the OTP. Return error when the word is not
344 static s32
igb_read_invm_word_i210(struct e1000_hw
*hw
, u8 address
, u16
*data
)
346 s32 status
= -E1000_ERR_INVM_VALUE_NOT_FOUND
;
349 u8 record_type
, word_address
;
351 for (i
= 0; i
< E1000_INVM_SIZE
; i
++) {
352 invm_dword
= rd32(E1000_INVM_DATA_REG(i
));
353 /* Get record type */
354 record_type
= INVM_DWORD_TO_RECORD_TYPE(invm_dword
);
355 if (record_type
== E1000_INVM_UNINITIALIZED_STRUCTURE
)
357 if (record_type
== E1000_INVM_CSR_AUTOLOAD_STRUCTURE
)
358 i
+= E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS
;
359 if (record_type
== E1000_INVM_RSA_KEY_SHA256_STRUCTURE
)
360 i
+= E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS
;
361 if (record_type
== E1000_INVM_WORD_AUTOLOAD_STRUCTURE
) {
362 word_address
= INVM_DWORD_TO_WORD_ADDRESS(invm_dword
);
363 if (word_address
== address
) {
364 *data
= INVM_DWORD_TO_WORD_DATA(invm_dword
);
365 hw_dbg("Read INVM Word 0x%02x = %x\n",
367 status
= E1000_SUCCESS
;
372 if (status
!= E1000_SUCCESS
)
373 hw_dbg("Requested word 0x%02x not found in OTP\n", address
);
378 * igb_read_invm_i210 - Read invm wrapper function for I210/I211
379 * @hw: pointer to the HW structure
380 * @words: number of words to read
381 * @data: pointer to the data read
383 * Wrapper function to return data formerly found in the NVM.
385 static s32
igb_read_invm_i210(struct e1000_hw
*hw
, u16 offset
,
386 u16 words __always_unused
, u16
*data
)
388 s32 ret_val
= E1000_SUCCESS
;
390 /* Only the MAC addr is required to be present in the iNVM */
393 ret_val
= igb_read_invm_word_i210(hw
, (u8
)offset
, &data
[0]);
394 ret_val
|= igb_read_invm_word_i210(hw
, (u8
)offset
+1,
396 ret_val
|= igb_read_invm_word_i210(hw
, (u8
)offset
+2,
398 if (ret_val
!= E1000_SUCCESS
)
399 hw_dbg("MAC Addr not found in iNVM\n");
401 case NVM_INIT_CTRL_2
:
402 ret_val
= igb_read_invm_word_i210(hw
, (u8
)offset
, data
);
403 if (ret_val
!= E1000_SUCCESS
) {
404 *data
= NVM_INIT_CTRL_2_DEFAULT_I211
;
405 ret_val
= E1000_SUCCESS
;
408 case NVM_INIT_CTRL_4
:
409 ret_val
= igb_read_invm_word_i210(hw
, (u8
)offset
, data
);
410 if (ret_val
!= E1000_SUCCESS
) {
411 *data
= NVM_INIT_CTRL_4_DEFAULT_I211
;
412 ret_val
= E1000_SUCCESS
;
416 ret_val
= igb_read_invm_word_i210(hw
, (u8
)offset
, data
);
417 if (ret_val
!= E1000_SUCCESS
) {
418 *data
= NVM_LED_1_CFG_DEFAULT_I211
;
419 ret_val
= E1000_SUCCESS
;
422 case NVM_LED_0_2_CFG
:
423 ret_val
= igb_read_invm_word_i210(hw
, (u8
)offset
, data
);
424 if (ret_val
!= E1000_SUCCESS
) {
425 *data
= NVM_LED_0_2_CFG_DEFAULT_I211
;
426 ret_val
= E1000_SUCCESS
;
429 case NVM_ID_LED_SETTINGS
:
430 ret_val
= igb_read_invm_word_i210(hw
, (u8
)offset
, data
);
431 if (ret_val
!= E1000_SUCCESS
) {
432 *data
= ID_LED_RESERVED_FFFF
;
433 ret_val
= E1000_SUCCESS
;
436 *data
= hw
->subsystem_device_id
;
439 *data
= hw
->subsystem_vendor_id
;
442 *data
= hw
->device_id
;
445 *data
= hw
->vendor_id
;
448 hw_dbg("NVM word 0x%02x is not mapped.\n", offset
);
449 *data
= NVM_RESERVED_WORD
;
456 * igb_read_invm_version - Reads iNVM version and image type
457 * @hw: pointer to the HW structure
458 * @invm_ver: version structure for the version read
460 * Reads iNVM version and image type.
462 s32
igb_read_invm_version(struct e1000_hw
*hw
,
463 struct e1000_fw_version
*invm_ver
) {
465 u32
*next_record
= NULL
;
468 u32 invm_blocks
= E1000_INVM_SIZE
- (E1000_INVM_ULT_BYTES_SIZE
/
469 E1000_INVM_RECORD_SIZE_IN_BYTES
);
470 u32 buffer
[E1000_INVM_SIZE
];
471 s32 status
= -E1000_ERR_INVM_VALUE_NOT_FOUND
;
474 /* Read iNVM memory */
475 for (i
= 0; i
< E1000_INVM_SIZE
; i
++) {
476 invm_dword
= rd32(E1000_INVM_DATA_REG(i
));
477 buffer
[i
] = invm_dword
;
480 /* Read version number */
481 for (i
= 1; i
< invm_blocks
; i
++) {
482 record
= &buffer
[invm_blocks
- i
];
483 next_record
= &buffer
[invm_blocks
- i
+ 1];
485 /* Check if we have first version location used */
486 if ((i
== 1) && ((*record
& E1000_INVM_VER_FIELD_ONE
) == 0)) {
488 status
= E1000_SUCCESS
;
491 /* Check if we have second version location used */
493 ((*record
& E1000_INVM_VER_FIELD_TWO
) == 0)) {
494 version
= (*record
& E1000_INVM_VER_FIELD_ONE
) >> 3;
495 status
= E1000_SUCCESS
;
498 /* Check if we have odd version location
499 * used and it is the last one used
501 else if ((((*record
& E1000_INVM_VER_FIELD_ONE
) == 0) &&
502 ((*record
& 0x3) == 0)) || (((*record
& 0x3) != 0) &&
504 version
= (*next_record
& E1000_INVM_VER_FIELD_TWO
)
506 status
= E1000_SUCCESS
;
509 /* Check if we have even version location
510 * used and it is the last one used
512 else if (((*record
& E1000_INVM_VER_FIELD_TWO
) == 0) &&
513 ((*record
& 0x3) == 0)) {
514 version
= (*record
& E1000_INVM_VER_FIELD_ONE
) >> 3;
515 status
= E1000_SUCCESS
;
520 if (status
== E1000_SUCCESS
) {
521 invm_ver
->invm_major
= (version
& E1000_INVM_MAJOR_MASK
)
522 >> E1000_INVM_MAJOR_SHIFT
;
523 invm_ver
->invm_minor
= version
& E1000_INVM_MINOR_MASK
;
525 /* Read Image Type */
526 for (i
= 1; i
< invm_blocks
; i
++) {
527 record
= &buffer
[invm_blocks
- i
];
528 next_record
= &buffer
[invm_blocks
- i
+ 1];
530 /* Check if we have image type in first location used */
531 if ((i
== 1) && ((*record
& E1000_INVM_IMGTYPE_FIELD
) == 0)) {
532 invm_ver
->invm_img_type
= 0;
533 status
= E1000_SUCCESS
;
536 /* Check if we have image type in first location used */
537 else if ((((*record
& 0x3) == 0) &&
538 ((*record
& E1000_INVM_IMGTYPE_FIELD
) == 0)) ||
539 ((((*record
& 0x3) != 0) && (i
!= 1)))) {
540 invm_ver
->invm_img_type
=
541 (*next_record
& E1000_INVM_IMGTYPE_FIELD
) >> 23;
542 status
= E1000_SUCCESS
;
550 * igb_validate_nvm_checksum_i210 - Validate EEPROM checksum
551 * @hw: pointer to the HW structure
553 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
554 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
556 static s32
igb_validate_nvm_checksum_i210(struct e1000_hw
*hw
)
558 s32 status
= E1000_SUCCESS
;
559 s32 (*read_op_ptr
)(struct e1000_hw
*, u16
, u16
, u16
*);
561 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
563 /* Replace the read function with semaphore grabbing with
564 * the one that skips this for a while.
565 * We have semaphore taken already here.
567 read_op_ptr
= hw
->nvm
.ops
.read
;
568 hw
->nvm
.ops
.read
= igb_read_nvm_eerd
;
570 status
= igb_validate_nvm_checksum(hw
);
572 /* Revert original read operation. */
573 hw
->nvm
.ops
.read
= read_op_ptr
;
575 hw
->nvm
.ops
.release(hw
);
577 status
= E1000_ERR_SWFW_SYNC
;
584 * igb_update_nvm_checksum_i210 - Update EEPROM checksum
585 * @hw: pointer to the HW structure
587 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
588 * up to the checksum. Then calculates the EEPROM checksum and writes the
589 * value to the EEPROM. Next commit EEPROM data onto the Flash.
591 static s32
igb_update_nvm_checksum_i210(struct e1000_hw
*hw
)
593 s32 ret_val
= E1000_SUCCESS
;
597 /* Read the first word from the EEPROM. If this times out or fails, do
598 * not continue or we could be in for a very long wait while every
601 ret_val
= igb_read_nvm_eerd(hw
, 0, 1, &nvm_data
);
602 if (ret_val
!= E1000_SUCCESS
) {
603 hw_dbg("EEPROM read failed\n");
607 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
608 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
609 * because we do not want to take the synchronization
610 * semaphores twice here.
613 for (i
= 0; i
< NVM_CHECKSUM_REG
; i
++) {
614 ret_val
= igb_read_nvm_eerd(hw
, i
, 1, &nvm_data
);
616 hw
->nvm
.ops
.release(hw
);
617 hw_dbg("NVM Read Error while updating checksum.\n");
620 checksum
+= nvm_data
;
622 checksum
= (u16
) NVM_SUM
- checksum
;
623 ret_val
= igb_write_nvm_srwr(hw
, NVM_CHECKSUM_REG
, 1,
625 if (ret_val
!= E1000_SUCCESS
) {
626 hw
->nvm
.ops
.release(hw
);
627 hw_dbg("NVM Write Error while updating checksum.\n");
631 hw
->nvm
.ops
.release(hw
);
633 ret_val
= igb_update_flash_i210(hw
);
635 ret_val
= -E1000_ERR_SWFW_SYNC
;
642 * igb_pool_flash_update_done_i210 - Pool FLUDONE status.
643 * @hw: pointer to the HW structure
646 static s32
igb_pool_flash_update_done_i210(struct e1000_hw
*hw
)
648 s32 ret_val
= -E1000_ERR_NVM
;
651 for (i
= 0; i
< E1000_FLUDONE_ATTEMPTS
; i
++) {
652 reg
= rd32(E1000_EECD
);
653 if (reg
& E1000_EECD_FLUDONE_I210
) {
654 ret_val
= E1000_SUCCESS
;
664 * igb_get_flash_presence_i210 - Check if flash device is detected.
665 * @hw: pointer to the HW structure
668 bool igb_get_flash_presence_i210(struct e1000_hw
*hw
)
671 bool ret_val
= false;
673 eec
= rd32(E1000_EECD
);
674 if (eec
& E1000_EECD_FLASH_DETECTED_I210
)
681 * igb_update_flash_i210 - Commit EEPROM to the flash
682 * @hw: pointer to the HW structure
685 static s32
igb_update_flash_i210(struct e1000_hw
*hw
)
687 s32 ret_val
= E1000_SUCCESS
;
690 ret_val
= igb_pool_flash_update_done_i210(hw
);
691 if (ret_val
== -E1000_ERR_NVM
) {
692 hw_dbg("Flash update time out\n");
696 flup
= rd32(E1000_EECD
) | E1000_EECD_FLUPD_I210
;
697 wr32(E1000_EECD
, flup
);
699 ret_val
= igb_pool_flash_update_done_i210(hw
);
700 if (ret_val
== E1000_SUCCESS
)
701 hw_dbg("Flash update complete\n");
703 hw_dbg("Flash update time out\n");
710 * igb_valid_led_default_i210 - Verify a valid default LED config
711 * @hw: pointer to the HW structure
712 * @data: pointer to the NVM (EEPROM)
714 * Read the EEPROM for the current default LED configuration. If the
715 * LED configuration is not valid, set to a valid LED configuration.
717 s32
igb_valid_led_default_i210(struct e1000_hw
*hw
, u16
*data
)
721 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
723 hw_dbg("NVM Read Error\n");
727 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
) {
728 switch (hw
->phy
.media_type
) {
729 case e1000_media_type_internal_serdes
:
730 *data
= ID_LED_DEFAULT_I210_SERDES
;
732 case e1000_media_type_copper
:
734 *data
= ID_LED_DEFAULT_I210
;
743 * __igb_access_xmdio_reg - Read/write XMDIO register
744 * @hw: pointer to the HW structure
745 * @address: XMDIO address to program
746 * @dev_addr: device address to program
747 * @data: pointer to value to read/write from/to the XMDIO address
748 * @read: boolean flag to indicate read or write
750 static s32
__igb_access_xmdio_reg(struct e1000_hw
*hw
, u16 address
,
751 u8 dev_addr
, u16
*data
, bool read
)
753 s32 ret_val
= E1000_SUCCESS
;
755 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, dev_addr
);
759 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAAD
, address
);
763 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, E1000_MMDAC_FUNC_DATA
|
769 ret_val
= hw
->phy
.ops
.read_reg(hw
, E1000_MMDAAD
, data
);
771 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAAD
, *data
);
775 /* Recalibrate the device back to 0 */
776 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, 0);
784 * igb_read_xmdio_reg - Read XMDIO register
785 * @hw: pointer to the HW structure
786 * @addr: XMDIO address to program
787 * @dev_addr: device address to program
788 * @data: value to be read from the EMI address
790 s32
igb_read_xmdio_reg(struct e1000_hw
*hw
, u16 addr
, u8 dev_addr
, u16
*data
)
792 return __igb_access_xmdio_reg(hw
, addr
, dev_addr
, data
, true);
796 * igb_write_xmdio_reg - Write XMDIO register
797 * @hw: pointer to the HW structure
798 * @addr: XMDIO address to program
799 * @dev_addr: device address to program
800 * @data: value to be written to the XMDIO address
802 s32
igb_write_xmdio_reg(struct e1000_hw
*hw
, u16 addr
, u8 dev_addr
, u16 data
)
804 return __igb_access_xmdio_reg(hw
, addr
, dev_addr
, &data
, false);
808 * igb_init_nvm_params_i210 - Init NVM func ptrs.
809 * @hw: pointer to the HW structure
811 s32
igb_init_nvm_params_i210(struct e1000_hw
*hw
)
814 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
816 nvm
->ops
.acquire
= igb_acquire_nvm_i210
;
817 nvm
->ops
.release
= igb_release_nvm_i210
;
818 nvm
->ops
.valid_led_default
= igb_valid_led_default_i210
;
820 /* NVM Function Pointers */
821 if (igb_get_flash_presence_i210(hw
)) {
822 hw
->nvm
.type
= e1000_nvm_flash_hw
;
823 nvm
->ops
.read
= igb_read_nvm_srrd_i210
;
824 nvm
->ops
.write
= igb_write_nvm_srwr_i210
;
825 nvm
->ops
.validate
= igb_validate_nvm_checksum_i210
;
826 nvm
->ops
.update
= igb_update_nvm_checksum_i210
;
828 hw
->nvm
.type
= e1000_nvm_invm
;
829 nvm
->ops
.read
= igb_read_invm_i210
;
830 nvm
->ops
.write
= NULL
;
831 nvm
->ops
.validate
= NULL
;
832 nvm
->ops
.update
= NULL
;