1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
34 #include "e1000_mac.h"
38 static s32
igb_set_default_fc(struct e1000_hw
*hw
);
39 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
);
42 * igb_get_bus_info_pcie - Get PCIe bus information
43 * @hw: pointer to the HW structure
45 * Determines and stores the system bus information for a particular
46 * network interface. The following bus information is determined and stored:
47 * bus speed, bus width, type (PCIe), and PCIe function.
49 s32
igb_get_bus_info_pcie(struct e1000_hw
*hw
)
51 struct e1000_bus_info
*bus
= &hw
->bus
;
56 bus
->type
= e1000_bus_type_pci_express
;
58 ret_val
= igb_read_pcie_cap_reg(hw
,
62 bus
->width
= e1000_bus_width_unknown
;
63 bus
->speed
= e1000_bus_speed_unknown
;
65 switch (pcie_link_status
& PCI_EXP_LNKSTA_CLS
) {
66 case PCI_EXP_LNKSTA_CLS_2_5GB
:
67 bus
->speed
= e1000_bus_speed_2500
;
69 case PCI_EXP_LNKSTA_CLS_5_0GB
:
70 bus
->speed
= e1000_bus_speed_5000
;
73 bus
->speed
= e1000_bus_speed_unknown
;
77 bus
->width
= (enum e1000_bus_width
)((pcie_link_status
&
78 PCI_EXP_LNKSTA_NLW
) >>
79 PCI_EXP_LNKSTA_NLW_SHIFT
);
82 reg
= rd32(E1000_STATUS
);
83 bus
->func
= (reg
& E1000_STATUS_FUNC_MASK
) >> E1000_STATUS_FUNC_SHIFT
;
89 * igb_clear_vfta - Clear VLAN filter table
90 * @hw: pointer to the HW structure
92 * Clears the register array which contains the VLAN filter table by
93 * setting all the values to 0.
95 void igb_clear_vfta(struct e1000_hw
*hw
)
99 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
100 array_wr32(E1000_VFTA
, offset
, 0);
106 * igb_write_vfta - Write value to VLAN filter table
107 * @hw: pointer to the HW structure
108 * @offset: register offset in VLAN filter table
109 * @value: register value written to VLAN filter table
111 * Writes value at the given offset in the register array which stores
112 * the VLAN filter table.
114 static void igb_write_vfta(struct e1000_hw
*hw
, u32 offset
, u32 value
)
116 array_wr32(E1000_VFTA
, offset
, value
);
120 /* Due to a hw errata, if the host tries to configure the VFTA register
121 * while performing queries from the BMC or DMA, then the VFTA in some
122 * cases won't be written.
126 * igb_clear_vfta_i350 - Clear VLAN filter table
127 * @hw: pointer to the HW structure
129 * Clears the register array which contains the VLAN filter table by
130 * setting all the values to 0.
132 void igb_clear_vfta_i350(struct e1000_hw
*hw
)
137 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
138 for (i
= 0; i
< 10; i
++)
139 array_wr32(E1000_VFTA
, offset
, 0);
146 * igb_write_vfta_i350 - Write value to VLAN filter table
147 * @hw: pointer to the HW structure
148 * @offset: register offset in VLAN filter table
149 * @value: register value written to VLAN filter table
151 * Writes value at the given offset in the register array which stores
152 * the VLAN filter table.
154 static void igb_write_vfta_i350(struct e1000_hw
*hw
, u32 offset
, u32 value
)
158 for (i
= 0; i
< 10; i
++)
159 array_wr32(E1000_VFTA
, offset
, value
);
165 * igb_init_rx_addrs - Initialize receive address's
166 * @hw: pointer to the HW structure
167 * @rar_count: receive address registers
169 * Setups the receive address registers by setting the base receive address
170 * register to the devices MAC address and clearing all the other receive
171 * address registers to 0.
173 void igb_init_rx_addrs(struct e1000_hw
*hw
, u16 rar_count
)
176 u8 mac_addr
[ETH_ALEN
] = {0};
178 /* Setup the receive address */
179 hw_dbg("Programming MAC Address into RAR[0]\n");
181 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.addr
, 0);
183 /* Zero out the other (rar_entry_count - 1) receive addresses */
184 hw_dbg("Clearing RAR[1-%u]\n", rar_count
-1);
185 for (i
= 1; i
< rar_count
; i
++)
186 hw
->mac
.ops
.rar_set(hw
, mac_addr
, i
);
190 * igb_vfta_set - enable or disable vlan in VLAN filter table
191 * @hw: pointer to the HW structure
192 * @vid: VLAN id to add or remove
193 * @add: if true add filter, if false remove
195 * Sets or clears a bit in the VLAN filter table array based on VLAN id
196 * and if we are adding or removing the filter
198 s32
igb_vfta_set(struct e1000_hw
*hw
, u32 vid
, bool add
)
200 u32 index
= (vid
>> E1000_VFTA_ENTRY_SHIFT
) & E1000_VFTA_ENTRY_MASK
;
201 u32 mask
= 1 << (vid
& E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
203 struct igb_adapter
*adapter
= hw
->back
;
206 vfta
= adapter
->shadow_vfta
[index
];
208 /* bit was set/cleared before we started */
209 if ((!!(vfta
& mask
)) == add
) {
210 ret_val
= -E1000_ERR_CONFIG
;
217 if ((hw
->mac
.type
== e1000_i350
) || (hw
->mac
.type
== e1000_i354
))
218 igb_write_vfta_i350(hw
, index
, vfta
);
220 igb_write_vfta(hw
, index
, vfta
);
221 adapter
->shadow_vfta
[index
] = vfta
;
227 * igb_check_alt_mac_addr - Check for alternate MAC addr
228 * @hw: pointer to the HW structure
230 * Checks the nvm for an alternate MAC address. An alternate MAC address
231 * can be setup by pre-boot software and must be treated like a permanent
232 * address and must override the actual permanent MAC address. If an
233 * alternate MAC address is found it is saved in the hw struct and
234 * programmed into RAR0 and the function returns success, otherwise the
235 * function returns an error.
237 s32
igb_check_alt_mac_addr(struct e1000_hw
*hw
)
241 u16 offset
, nvm_alt_mac_addr_offset
, nvm_data
;
242 u8 alt_mac_addr
[ETH_ALEN
];
244 /* Alternate MAC address is handled by the option ROM for 82580
245 * and newer. SW support not required.
247 if (hw
->mac
.type
>= e1000_82580
)
250 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ALT_MAC_ADDR_PTR
, 1,
251 &nvm_alt_mac_addr_offset
);
253 hw_dbg("NVM Read Error\n");
257 if ((nvm_alt_mac_addr_offset
== 0xFFFF) ||
258 (nvm_alt_mac_addr_offset
== 0x0000))
259 /* There is no Alternate MAC Address */
262 if (hw
->bus
.func
== E1000_FUNC_1
)
263 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN1
;
264 if (hw
->bus
.func
== E1000_FUNC_2
)
265 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN2
;
267 if (hw
->bus
.func
== E1000_FUNC_3
)
268 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN3
;
269 for (i
= 0; i
< ETH_ALEN
; i
+= 2) {
270 offset
= nvm_alt_mac_addr_offset
+ (i
>> 1);
271 ret_val
= hw
->nvm
.ops
.read(hw
, offset
, 1, &nvm_data
);
273 hw_dbg("NVM Read Error\n");
277 alt_mac_addr
[i
] = (u8
)(nvm_data
& 0xFF);
278 alt_mac_addr
[i
+ 1] = (u8
)(nvm_data
>> 8);
281 /* if multicast bit is set, the alternate address will not be used */
282 if (is_multicast_ether_addr(alt_mac_addr
)) {
283 hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
287 /* We have a valid alternate MAC address, and we want to treat it the
288 * same as the normal permanent MAC address stored by the HW into the
289 * RAR. Do this by mapping this address into RAR0.
291 hw
->mac
.ops
.rar_set(hw
, alt_mac_addr
, 0);
298 * igb_rar_set - Set receive address register
299 * @hw: pointer to the HW structure
300 * @addr: pointer to the receive address
301 * @index: receive address array register
303 * Sets the receive address array register at index to the address passed
306 void igb_rar_set(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
308 u32 rar_low
, rar_high
;
310 /* HW expects these in little endian so we reverse the byte order
311 * from network order (big endian) to little endian
313 rar_low
= ((u32
) addr
[0] |
314 ((u32
) addr
[1] << 8) |
315 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
317 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
319 /* If MAC address zero, no need to set the AV bit */
320 if (rar_low
|| rar_high
)
321 rar_high
|= E1000_RAH_AV
;
323 /* Some bridges will combine consecutive 32-bit writes into
324 * a single burst write, which will malfunction on some parts.
325 * The flushes avoid this.
327 wr32(E1000_RAL(index
), rar_low
);
329 wr32(E1000_RAH(index
), rar_high
);
334 * igb_mta_set - Set multicast filter table address
335 * @hw: pointer to the HW structure
336 * @hash_value: determines the MTA register and bit to set
338 * The multicast table address is a register array of 32-bit registers.
339 * The hash_value is used to determine what register the bit is in, the
340 * current value is read, the new bit is OR'd in and the new value is
341 * written back into the register.
343 void igb_mta_set(struct e1000_hw
*hw
, u32 hash_value
)
345 u32 hash_bit
, hash_reg
, mta
;
347 /* The MTA is a register array of 32-bit registers. It is
348 * treated like an array of (32*mta_reg_count) bits. We want to
349 * set bit BitArray[hash_value]. So we figure out what register
350 * the bit is in, read it, OR in the new bit, then write
351 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
352 * mask to bits 31:5 of the hash value which gives us the
353 * register we're modifying. The hash bit within that register
354 * is determined by the lower 5 bits of the hash value.
356 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
357 hash_bit
= hash_value
& 0x1F;
359 mta
= array_rd32(E1000_MTA
, hash_reg
);
361 mta
|= (1 << hash_bit
);
363 array_wr32(E1000_MTA
, hash_reg
, mta
);
368 * igb_hash_mc_addr - Generate a multicast hash value
369 * @hw: pointer to the HW structure
370 * @mc_addr: pointer to a multicast address
372 * Generates a multicast address hash value which is used to determine
373 * the multicast filter table array address and new table value. See
376 static u32
igb_hash_mc_addr(struct e1000_hw
*hw
, u8
*mc_addr
)
378 u32 hash_value
, hash_mask
;
381 /* Register count multiplied by bits per register */
382 hash_mask
= (hw
->mac
.mta_reg_count
* 32) - 1;
384 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
385 * where 0xFF would still fall within the hash mask.
387 while (hash_mask
>> bit_shift
!= 0xFF)
390 /* The portion of the address that is used for the hash table
391 * is determined by the mc_filter_type setting.
392 * The algorithm is such that there is a total of 8 bits of shifting.
393 * The bit_shift for a mc_filter_type of 0 represents the number of
394 * left-shifts where the MSB of mc_addr[5] would still fall within
395 * the hash_mask. Case 0 does this exactly. Since there are a total
396 * of 8 bits of shifting, then mc_addr[4] will shift right the
397 * remaining number of bits. Thus 8 - bit_shift. The rest of the
398 * cases are a variation of this algorithm...essentially raising the
399 * number of bits to shift mc_addr[5] left, while still keeping the
400 * 8-bit shifting total.
402 * For example, given the following Destination MAC Address and an
403 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
404 * we can see that the bit_shift for case 0 is 4. These are the hash
405 * values resulting from each mc_filter_type...
406 * [0] [1] [2] [3] [4] [5]
410 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
411 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
412 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
413 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
415 switch (hw
->mac
.mc_filter_type
) {
430 hash_value
= hash_mask
& (((mc_addr
[4] >> (8 - bit_shift
)) |
431 (((u16
) mc_addr
[5]) << bit_shift
)));
437 * igb_update_mc_addr_list - Update Multicast addresses
438 * @hw: pointer to the HW structure
439 * @mc_addr_list: array of multicast addresses to program
440 * @mc_addr_count: number of multicast addresses to program
442 * Updates entire Multicast Table Array.
443 * The caller must have a packed mc_addr_list of multicast addresses.
445 void igb_update_mc_addr_list(struct e1000_hw
*hw
,
446 u8
*mc_addr_list
, u32 mc_addr_count
)
448 u32 hash_value
, hash_bit
, hash_reg
;
451 /* clear mta_shadow */
452 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
454 /* update mta_shadow from mc_addr_list */
455 for (i
= 0; (u32
) i
< mc_addr_count
; i
++) {
456 hash_value
= igb_hash_mc_addr(hw
, mc_addr_list
);
458 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
459 hash_bit
= hash_value
& 0x1F;
461 hw
->mac
.mta_shadow
[hash_reg
] |= (1 << hash_bit
);
462 mc_addr_list
+= (ETH_ALEN
);
465 /* replace the entire MTA table */
466 for (i
= hw
->mac
.mta_reg_count
- 1; i
>= 0; i
--)
467 array_wr32(E1000_MTA
, i
, hw
->mac
.mta_shadow
[i
]);
472 * igb_clear_hw_cntrs_base - Clear base hardware counters
473 * @hw: pointer to the HW structure
475 * Clears the base hardware counters by reading the counter registers.
477 void igb_clear_hw_cntrs_base(struct e1000_hw
*hw
)
519 * igb_check_for_copper_link - Check for link (Copper)
520 * @hw: pointer to the HW structure
522 * Checks to see of the link status of the hardware has changed. If a
523 * change in link status has been detected, then we read the PHY registers
524 * to get the current speed/duplex if link exists.
526 s32
igb_check_for_copper_link(struct e1000_hw
*hw
)
528 struct e1000_mac_info
*mac
= &hw
->mac
;
532 /* We only want to go out to the PHY registers to see if Auto-Neg
533 * has completed and/or if our link status has changed. The
534 * get_link_status flag is set upon receiving a Link Status
535 * Change or Rx Sequence Error interrupt.
537 if (!mac
->get_link_status
) {
542 /* First we want to see if the MII Status Register reports
543 * link. If so, then we want to get the current speed/duplex
546 ret_val
= igb_phy_has_link(hw
, 1, 0, &link
);
551 goto out
; /* No link detected */
553 mac
->get_link_status
= false;
555 /* Check if there was DownShift, must be checked
556 * immediately after link-up
558 igb_check_downshift(hw
);
560 /* If we are forcing speed/duplex, then we simply return since
561 * we have already determined whether we have link or not.
564 ret_val
= -E1000_ERR_CONFIG
;
568 /* Auto-Neg is enabled. Auto Speed Detection takes care
569 * of MAC speed/duplex configuration. So we only need to
570 * configure Collision Distance in the MAC.
572 igb_config_collision_dist(hw
);
574 /* Configure Flow Control now that Auto-Neg has completed.
575 * First, we need to restore the desired flow control
576 * settings because we may have had to re-autoneg with a
577 * different link partner.
579 ret_val
= igb_config_fc_after_link_up(hw
);
581 hw_dbg("Error configuring flow control\n");
588 * igb_setup_link - Setup flow control and link settings
589 * @hw: pointer to the HW structure
591 * Determines which flow control settings to use, then configures flow
592 * control. Calls the appropriate media-specific link configuration
593 * function. Assuming the adapter has a valid link partner, a valid link
594 * should be established. Assumes the hardware has previously been reset
595 * and the transmitter and receiver are not enabled.
597 s32
igb_setup_link(struct e1000_hw
*hw
)
601 /* In the case of the phy reset being blocked, we already have a link.
602 * We do not need to set it up again.
604 if (igb_check_reset_block(hw
))
607 /* If requested flow control is set to default, set flow control
608 * based on the EEPROM flow control settings.
610 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
611 ret_val
= igb_set_default_fc(hw
);
616 /* We want to save off the original Flow Control configuration just
617 * in case we get disconnected and then reconnected into a different
618 * hub or switch with different Flow Control capabilities.
620 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
622 hw_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.current_mode
);
624 /* Call the necessary media_type subroutine to configure the link. */
625 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
629 /* Initialize the flow control address, type, and PAUSE timer
630 * registers to their default values. This is done even if flow
631 * control is disabled, because it does not hurt anything to
632 * initialize these registers.
634 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
635 wr32(E1000_FCT
, FLOW_CONTROL_TYPE
);
636 wr32(E1000_FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
637 wr32(E1000_FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
639 wr32(E1000_FCTTV
, hw
->fc
.pause_time
);
641 ret_val
= igb_set_fc_watermarks(hw
);
649 * igb_config_collision_dist - Configure collision distance
650 * @hw: pointer to the HW structure
652 * Configures the collision distance to the default value and is used
653 * during link setup. Currently no func pointer exists and all
654 * implementations are handled in the generic version of this function.
656 void igb_config_collision_dist(struct e1000_hw
*hw
)
660 tctl
= rd32(E1000_TCTL
);
662 tctl
&= ~E1000_TCTL_COLD
;
663 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
665 wr32(E1000_TCTL
, tctl
);
670 * igb_set_fc_watermarks - Set flow control high/low watermarks
671 * @hw: pointer to the HW structure
673 * Sets the flow control high/low threshold (watermark) registers. If
674 * flow control XON frame transmission is enabled, then set XON frame
675 * tansmission as well.
677 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
)
680 u32 fcrtl
= 0, fcrth
= 0;
682 /* Set the flow control receive threshold registers. Normally,
683 * these registers will be set to a default threshold that may be
684 * adjusted later by the driver's runtime code. However, if the
685 * ability to transmit pause frames is not enabled, then these
686 * registers will be set to 0.
688 if (hw
->fc
.current_mode
& e1000_fc_tx_pause
) {
689 /* We need to set up the Receive Threshold high and low water
690 * marks as well as (optionally) enabling the transmission of
693 fcrtl
= hw
->fc
.low_water
;
695 fcrtl
|= E1000_FCRTL_XONE
;
697 fcrth
= hw
->fc
.high_water
;
699 wr32(E1000_FCRTL
, fcrtl
);
700 wr32(E1000_FCRTH
, fcrth
);
706 * igb_set_default_fc - Set flow control default values
707 * @hw: pointer to the HW structure
709 * Read the EEPROM for the default values for flow control and store the
712 static s32
igb_set_default_fc(struct e1000_hw
*hw
)
717 /* Read and store word 0x0F of the EEPROM. This word contains bits
718 * that determine the hardware's default PAUSE (flow control) mode,
719 * a bit that determines whether the HW defaults to enabling or
720 * disabling auto-negotiation, and the direction of the
721 * SW defined pins. If there is no SW over-ride of the flow
722 * control setting, then the variable hw->fc will
723 * be initialized based on a value in the EEPROM.
725 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL2_REG
, 1, &nvm_data
);
728 hw_dbg("NVM Read Error\n");
732 if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == 0)
733 hw
->fc
.requested_mode
= e1000_fc_none
;
734 else if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) ==
736 hw
->fc
.requested_mode
= e1000_fc_tx_pause
;
738 hw
->fc
.requested_mode
= e1000_fc_full
;
745 * igb_force_mac_fc - Force the MAC's flow control settings
746 * @hw: pointer to the HW structure
748 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
749 * device control register to reflect the adapter settings. TFCE and RFCE
750 * need to be explicitly set by software when a copper PHY is used because
751 * autonegotiation is managed by the PHY rather than the MAC. Software must
752 * also configure these bits when link is forced on a fiber connection.
754 s32
igb_force_mac_fc(struct e1000_hw
*hw
)
759 ctrl
= rd32(E1000_CTRL
);
761 /* Because we didn't get link via the internal auto-negotiation
762 * mechanism (we either forced link or we got link via PHY
763 * auto-neg), we have to manually enable/disable transmit an
764 * receive flow control.
766 * The "Case" statement below enables/disable flow control
767 * according to the "hw->fc.current_mode" parameter.
769 * The possible values of the "fc" parameter are:
770 * 0: Flow control is completely disabled
771 * 1: Rx flow control is enabled (we can receive pause
772 * frames but not send pause frames).
773 * 2: Tx flow control is enabled (we can send pause frames
774 * frames but we do not receive pause frames).
775 * 3: Both Rx and TX flow control (symmetric) is enabled.
776 * other: No other values should be possible at this point.
778 hw_dbg("hw->fc.current_mode = %u\n", hw
->fc
.current_mode
);
780 switch (hw
->fc
.current_mode
) {
782 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
784 case e1000_fc_rx_pause
:
785 ctrl
&= (~E1000_CTRL_TFCE
);
786 ctrl
|= E1000_CTRL_RFCE
;
788 case e1000_fc_tx_pause
:
789 ctrl
&= (~E1000_CTRL_RFCE
);
790 ctrl
|= E1000_CTRL_TFCE
;
793 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
796 hw_dbg("Flow control param set incorrectly\n");
797 ret_val
= -E1000_ERR_CONFIG
;
801 wr32(E1000_CTRL
, ctrl
);
808 * igb_config_fc_after_link_up - Configures flow control after link
809 * @hw: pointer to the HW structure
811 * Checks the status of auto-negotiation after link up to ensure that the
812 * speed and duplex were not forced. If the link needed to be forced, then
813 * flow control needs to be forced also. If auto-negotiation is enabled
814 * and did not fail, then we configure flow control based on our link
817 s32
igb_config_fc_after_link_up(struct e1000_hw
*hw
)
819 struct e1000_mac_info
*mac
= &hw
->mac
;
821 u32 pcs_status_reg
, pcs_adv_reg
, pcs_lp_ability_reg
, pcs_ctrl_reg
;
822 u16 mii_status_reg
, mii_nway_adv_reg
, mii_nway_lp_ability_reg
;
825 /* Check for the case where we have fiber media and auto-neg failed
826 * so we had to force link. In this case, we need to force the
827 * configuration of the MAC to match the "fc" parameter.
829 if (mac
->autoneg_failed
) {
830 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
831 ret_val
= igb_force_mac_fc(hw
);
833 if (hw
->phy
.media_type
== e1000_media_type_copper
)
834 ret_val
= igb_force_mac_fc(hw
);
838 hw_dbg("Error forcing flow control settings\n");
842 /* Check for the case where we have copper media and auto-neg is
843 * enabled. In this case, we need to check and see if Auto-Neg
844 * has completed, and if so, how the PHY and link partner has
845 * flow control configured.
847 if ((hw
->phy
.media_type
== e1000_media_type_copper
) && mac
->autoneg
) {
848 /* Read the MII Status Register and check to see if AutoNeg
849 * has completed. We read this twice because this reg has
850 * some "sticky" (latched) bits.
852 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
856 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
861 if (!(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
)) {
862 hw_dbg("Copper PHY and Auto Neg "
863 "has not completed.\n");
867 /* The AutoNeg process has completed, so we now need to
868 * read both the Auto Negotiation Advertisement
869 * Register (Address 4) and the Auto_Negotiation Base
870 * Page Ability Register (Address 5) to determine how
871 * flow control was negotiated.
873 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_AUTONEG_ADV
,
877 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_LP_ABILITY
,
878 &mii_nway_lp_ability_reg
);
882 /* Two bits in the Auto Negotiation Advertisement Register
883 * (Address 4) and two bits in the Auto Negotiation Base
884 * Page Ability Register (Address 5) determine flow control
885 * for both the PHY and the link partner. The following
886 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
887 * 1999, describes these PAUSE resolution bits and how flow
888 * control is determined based upon these settings.
889 * NOTE: DC = Don't Care
891 * LOCAL DEVICE | LINK PARTNER
892 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
893 *-------|---------|-------|---------|--------------------
894 * 0 | 0 | DC | DC | e1000_fc_none
895 * 0 | 1 | 0 | DC | e1000_fc_none
896 * 0 | 1 | 1 | 0 | e1000_fc_none
897 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
898 * 1 | 0 | 0 | DC | e1000_fc_none
899 * 1 | DC | 1 | DC | e1000_fc_full
900 * 1 | 1 | 0 | 0 | e1000_fc_none
901 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
903 * Are both PAUSE bits set to 1? If so, this implies
904 * Symmetric Flow Control is enabled at both ends. The
905 * ASM_DIR bits are irrelevant per the spec.
907 * For Symmetric Flow Control:
909 * LOCAL DEVICE | LINK PARTNER
910 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
911 *-------|---------|-------|---------|--------------------
912 * 1 | DC | 1 | DC | E1000_fc_full
915 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
916 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
917 /* Now we need to check if the user selected RX ONLY
918 * of pause frames. In this case, we had to advertise
919 * FULL flow control because we could not advertise RX
920 * ONLY. Hence, we must now check to see if we need to
921 * turn OFF the TRANSMISSION of PAUSE frames.
923 if (hw
->fc
.requested_mode
== e1000_fc_full
) {
924 hw
->fc
.current_mode
= e1000_fc_full
;
925 hw_dbg("Flow Control = FULL.\r\n");
927 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
928 hw_dbg("Flow Control = "
929 "RX PAUSE frames only.\r\n");
932 /* For receiving PAUSE frames ONLY.
934 * LOCAL DEVICE | LINK PARTNER
935 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
936 *-------|---------|-------|---------|--------------------
937 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
939 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
940 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
941 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
942 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
943 hw
->fc
.current_mode
= e1000_fc_tx_pause
;
944 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
946 /* For transmitting PAUSE frames ONLY.
948 * LOCAL DEVICE | LINK PARTNER
949 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
950 *-------|---------|-------|---------|--------------------
951 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
953 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
954 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
955 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
956 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
957 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
958 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
960 /* Per the IEEE spec, at this point flow control should be
961 * disabled. However, we want to consider that we could
962 * be connected to a legacy switch that doesn't advertise
963 * desired flow control, but can be forced on the link
964 * partner. So if we advertised no flow control, that is
965 * what we will resolve to. If we advertised some kind of
966 * receive capability (Rx Pause Only or Full Flow Control)
967 * and the link partner advertised none, we will configure
968 * ourselves to enable Rx Flow Control only. We can do
969 * this safely for two reasons: If the link partner really
970 * didn't want flow control enabled, and we enable Rx, no
971 * harm done since we won't be receiving any PAUSE frames
972 * anyway. If the intent on the link partner was to have
973 * flow control enabled, then by us enabling RX only, we
974 * can at least receive pause frames and process them.
975 * This is a good idea because in most cases, since we are
976 * predominantly a server NIC, more times than not we will
977 * be asked to delay transmission of packets than asking
978 * our link partner to pause transmission of frames.
980 else if ((hw
->fc
.requested_mode
== e1000_fc_none
) ||
981 (hw
->fc
.requested_mode
== e1000_fc_tx_pause
) ||
982 (hw
->fc
.strict_ieee
)) {
983 hw
->fc
.current_mode
= e1000_fc_none
;
984 hw_dbg("Flow Control = NONE.\r\n");
986 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
987 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
990 /* Now we need to do one last check... If we auto-
991 * negotiated to HALF DUPLEX, flow control should not be
992 * enabled per IEEE 802.3 spec.
994 ret_val
= hw
->mac
.ops
.get_speed_and_duplex(hw
, &speed
, &duplex
);
996 hw_dbg("Error getting link speed and duplex\n");
1000 if (duplex
== HALF_DUPLEX
)
1001 hw
->fc
.current_mode
= e1000_fc_none
;
1003 /* Now we call a subroutine to actually force the MAC
1004 * controller to use the correct flow control settings.
1006 ret_val
= igb_force_mac_fc(hw
);
1008 hw_dbg("Error forcing flow control settings\n");
1012 /* Check for the case where we have SerDes media and auto-neg is
1013 * enabled. In this case, we need to check and see if Auto-Neg
1014 * has completed, and if so, how the PHY and link partner has
1015 * flow control configured.
1017 if ((hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
1019 /* Read the PCS_LSTS and check to see if AutoNeg
1022 pcs_status_reg
= rd32(E1000_PCS_LSTAT
);
1024 if (!(pcs_status_reg
& E1000_PCS_LSTS_AN_COMPLETE
)) {
1025 hw_dbg("PCS Auto Neg has not completed.\n");
1029 /* The AutoNeg process has completed, so we now need to
1030 * read both the Auto Negotiation Advertisement
1031 * Register (PCS_ANADV) and the Auto_Negotiation Base
1032 * Page Ability Register (PCS_LPAB) to determine how
1033 * flow control was negotiated.
1035 pcs_adv_reg
= rd32(E1000_PCS_ANADV
);
1036 pcs_lp_ability_reg
= rd32(E1000_PCS_LPAB
);
1038 /* Two bits in the Auto Negotiation Advertisement Register
1039 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1040 * Page Ability Register (PCS_LPAB) determine flow control
1041 * for both the PHY and the link partner. The following
1042 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1043 * 1999, describes these PAUSE resolution bits and how flow
1044 * control is determined based upon these settings.
1045 * NOTE: DC = Don't Care
1047 * LOCAL DEVICE | LINK PARTNER
1048 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1049 *-------|---------|-------|---------|--------------------
1050 * 0 | 0 | DC | DC | e1000_fc_none
1051 * 0 | 1 | 0 | DC | e1000_fc_none
1052 * 0 | 1 | 1 | 0 | e1000_fc_none
1053 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1054 * 1 | 0 | 0 | DC | e1000_fc_none
1055 * 1 | DC | 1 | DC | e1000_fc_full
1056 * 1 | 1 | 0 | 0 | e1000_fc_none
1057 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1059 * Are both PAUSE bits set to 1? If so, this implies
1060 * Symmetric Flow Control is enabled at both ends. The
1061 * ASM_DIR bits are irrelevant per the spec.
1063 * For Symmetric Flow Control:
1065 * LOCAL DEVICE | LINK PARTNER
1066 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1067 *-------|---------|-------|---------|--------------------
1068 * 1 | DC | 1 | DC | e1000_fc_full
1071 if ((pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1072 (pcs_lp_ability_reg
& E1000_TXCW_PAUSE
)) {
1073 /* Now we need to check if the user selected Rx ONLY
1074 * of pause frames. In this case, we had to advertise
1075 * FULL flow control because we could not advertise Rx
1076 * ONLY. Hence, we must now check to see if we need to
1077 * turn OFF the TRANSMISSION of PAUSE frames.
1079 if (hw
->fc
.requested_mode
== e1000_fc_full
) {
1080 hw
->fc
.current_mode
= e1000_fc_full
;
1081 hw_dbg("Flow Control = FULL.\n");
1083 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1084 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1087 /* For receiving PAUSE frames ONLY.
1089 * LOCAL DEVICE | LINK PARTNER
1090 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1091 *-------|---------|-------|---------|--------------------
1092 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1094 else if (!(pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1095 (pcs_adv_reg
& E1000_TXCW_ASM_DIR
) &&
1096 (pcs_lp_ability_reg
& E1000_TXCW_PAUSE
) &&
1097 (pcs_lp_ability_reg
& E1000_TXCW_ASM_DIR
)) {
1098 hw
->fc
.current_mode
= e1000_fc_tx_pause
;
1099 hw_dbg("Flow Control = Tx PAUSE frames only.\n");
1101 /* For transmitting PAUSE frames ONLY.
1103 * LOCAL DEVICE | LINK PARTNER
1104 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1105 *-------|---------|-------|---------|--------------------
1106 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1108 else if ((pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1109 (pcs_adv_reg
& E1000_TXCW_ASM_DIR
) &&
1110 !(pcs_lp_ability_reg
& E1000_TXCW_PAUSE
) &&
1111 (pcs_lp_ability_reg
& E1000_TXCW_ASM_DIR
)) {
1112 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1113 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1115 /* Per the IEEE spec, at this point flow control
1116 * should be disabled.
1118 hw
->fc
.current_mode
= e1000_fc_none
;
1119 hw_dbg("Flow Control = NONE.\n");
1122 /* Now we call a subroutine to actually force the MAC
1123 * controller to use the correct flow control settings.
1125 pcs_ctrl_reg
= rd32(E1000_PCS_LCTL
);
1126 pcs_ctrl_reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1127 wr32(E1000_PCS_LCTL
, pcs_ctrl_reg
);
1129 ret_val
= igb_force_mac_fc(hw
);
1131 hw_dbg("Error forcing flow control settings\n");
1141 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1142 * @hw: pointer to the HW structure
1143 * @speed: stores the current speed
1144 * @duplex: stores the current duplex
1146 * Read the status register for the current speed/duplex and store the current
1147 * speed and duplex for copper connections.
1149 s32
igb_get_speed_and_duplex_copper(struct e1000_hw
*hw
, u16
*speed
,
1154 status
= rd32(E1000_STATUS
);
1155 if (status
& E1000_STATUS_SPEED_1000
) {
1156 *speed
= SPEED_1000
;
1157 hw_dbg("1000 Mbs, ");
1158 } else if (status
& E1000_STATUS_SPEED_100
) {
1160 hw_dbg("100 Mbs, ");
1166 if (status
& E1000_STATUS_FD
) {
1167 *duplex
= FULL_DUPLEX
;
1168 hw_dbg("Full Duplex\n");
1170 *duplex
= HALF_DUPLEX
;
1171 hw_dbg("Half Duplex\n");
1174 /* Check if it is an I354 2.5Gb backplane connection. */
1175 if (hw
->mac
.type
== e1000_i354
) {
1176 if ((status
& E1000_STATUS_2P5_SKU
) &&
1177 !(status
& E1000_STATUS_2P5_SKU_OVER
)) {
1178 *speed
= SPEED_2500
;
1179 *duplex
= FULL_DUPLEX
;
1180 hw_dbg("2500 Mbs, ");
1181 hw_dbg("Full Duplex\n");
1189 * igb_get_hw_semaphore - Acquire hardware semaphore
1190 * @hw: pointer to the HW structure
1192 * Acquire the HW semaphore to access the PHY or NVM
1194 s32
igb_get_hw_semaphore(struct e1000_hw
*hw
)
1198 s32 timeout
= hw
->nvm
.word_size
+ 1;
1201 /* Get the SW semaphore */
1202 while (i
< timeout
) {
1203 swsm
= rd32(E1000_SWSM
);
1204 if (!(swsm
& E1000_SWSM_SMBI
))
1212 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1213 ret_val
= -E1000_ERR_NVM
;
1217 /* Get the FW semaphore. */
1218 for (i
= 0; i
< timeout
; i
++) {
1219 swsm
= rd32(E1000_SWSM
);
1220 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
1222 /* Semaphore acquired if bit latched */
1223 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
1230 /* Release semaphores */
1231 igb_put_hw_semaphore(hw
);
1232 hw_dbg("Driver can't access the NVM\n");
1233 ret_val
= -E1000_ERR_NVM
;
1242 * igb_put_hw_semaphore - Release hardware semaphore
1243 * @hw: pointer to the HW structure
1245 * Release hardware semaphore used to access the PHY or NVM
1247 void igb_put_hw_semaphore(struct e1000_hw
*hw
)
1251 swsm
= rd32(E1000_SWSM
);
1253 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
1255 wr32(E1000_SWSM
, swsm
);
1259 * igb_get_auto_rd_done - Check for auto read completion
1260 * @hw: pointer to the HW structure
1262 * Check EEPROM for Auto Read done bit.
1264 s32
igb_get_auto_rd_done(struct e1000_hw
*hw
)
1270 while (i
< AUTO_READ_DONE_TIMEOUT
) {
1271 if (rd32(E1000_EECD
) & E1000_EECD_AUTO_RD
)
1277 if (i
== AUTO_READ_DONE_TIMEOUT
) {
1278 hw_dbg("Auto read by HW from NVM has not completed.\n");
1279 ret_val
= -E1000_ERR_RESET
;
1288 * igb_valid_led_default - Verify a valid default LED config
1289 * @hw: pointer to the HW structure
1290 * @data: pointer to the NVM (EEPROM)
1292 * Read the EEPROM for the current default LED configuration. If the
1293 * LED configuration is not valid, set to a valid LED configuration.
1295 static s32
igb_valid_led_default(struct e1000_hw
*hw
, u16
*data
)
1299 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1301 hw_dbg("NVM Read Error\n");
1305 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
) {
1306 switch(hw
->phy
.media_type
) {
1307 case e1000_media_type_internal_serdes
:
1308 *data
= ID_LED_DEFAULT_82575_SERDES
;
1310 case e1000_media_type_copper
:
1312 *data
= ID_LED_DEFAULT
;
1322 * @hw: pointer to the HW structure
1325 s32
igb_id_led_init(struct e1000_hw
*hw
)
1327 struct e1000_mac_info
*mac
= &hw
->mac
;
1329 const u32 ledctl_mask
= 0x000000FF;
1330 const u32 ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
1331 const u32 ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
1333 const u16 led_mask
= 0x0F;
1335 /* i210 and i211 devices have different LED mechanism */
1336 if ((hw
->mac
.type
== e1000_i210
) ||
1337 (hw
->mac
.type
== e1000_i211
))
1338 ret_val
= igb_valid_led_default_i210(hw
, &data
);
1340 ret_val
= igb_valid_led_default(hw
, &data
);
1345 mac
->ledctl_default
= rd32(E1000_LEDCTL
);
1346 mac
->ledctl_mode1
= mac
->ledctl_default
;
1347 mac
->ledctl_mode2
= mac
->ledctl_default
;
1349 for (i
= 0; i
< 4; i
++) {
1350 temp
= (data
>> (i
<< 2)) & led_mask
;
1352 case ID_LED_ON1_DEF2
:
1353 case ID_LED_ON1_ON2
:
1354 case ID_LED_ON1_OFF2
:
1355 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1356 mac
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
1358 case ID_LED_OFF1_DEF2
:
1359 case ID_LED_OFF1_ON2
:
1360 case ID_LED_OFF1_OFF2
:
1361 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1362 mac
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
1369 case ID_LED_DEF1_ON2
:
1370 case ID_LED_ON1_ON2
:
1371 case ID_LED_OFF1_ON2
:
1372 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1373 mac
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
1375 case ID_LED_DEF1_OFF2
:
1376 case ID_LED_ON1_OFF2
:
1377 case ID_LED_OFF1_OFF2
:
1378 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1379 mac
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
1392 * igb_cleanup_led - Set LED config to default operation
1393 * @hw: pointer to the HW structure
1395 * Remove the current LED configuration and set the LED configuration
1396 * to the default value, saved from the EEPROM.
1398 s32
igb_cleanup_led(struct e1000_hw
*hw
)
1400 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_default
);
1405 * igb_blink_led - Blink LED
1406 * @hw: pointer to the HW structure
1408 * Blink the led's which are set to be on.
1410 s32
igb_blink_led(struct e1000_hw
*hw
)
1412 u32 ledctl_blink
= 0;
1415 if (hw
->phy
.media_type
== e1000_media_type_fiber
) {
1416 /* always blink LED0 for PCI-E fiber */
1417 ledctl_blink
= E1000_LEDCTL_LED0_BLINK
|
1418 (E1000_LEDCTL_MODE_LED_ON
<< E1000_LEDCTL_LED0_MODE_SHIFT
);
1420 /* Set the blink bit for each LED that's "on" (0x0E)
1421 * (or "off" if inverted) in ledctl_mode2. The blink
1422 * logic in hardware only works when mode is set to "on"
1423 * so it must be changed accordingly when the mode is
1424 * "off" and inverted.
1426 ledctl_blink
= hw
->mac
.ledctl_mode2
;
1427 for (i
= 0; i
< 32; i
+= 8) {
1428 u32 mode
= (hw
->mac
.ledctl_mode2
>> i
) &
1429 E1000_LEDCTL_LED0_MODE_MASK
;
1430 u32 led_default
= hw
->mac
.ledctl_default
>> i
;
1432 if ((!(led_default
& E1000_LEDCTL_LED0_IVRT
) &&
1433 (mode
== E1000_LEDCTL_MODE_LED_ON
)) ||
1434 ((led_default
& E1000_LEDCTL_LED0_IVRT
) &&
1435 (mode
== E1000_LEDCTL_MODE_LED_OFF
))) {
1437 ~(E1000_LEDCTL_LED0_MODE_MASK
<< i
);
1438 ledctl_blink
|= (E1000_LEDCTL_LED0_BLINK
|
1439 E1000_LEDCTL_MODE_LED_ON
) << i
;
1444 wr32(E1000_LEDCTL
, ledctl_blink
);
1450 * igb_led_off - Turn LED off
1451 * @hw: pointer to the HW structure
1455 s32
igb_led_off(struct e1000_hw
*hw
)
1457 switch (hw
->phy
.media_type
) {
1458 case e1000_media_type_copper
:
1459 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_mode1
);
1469 * igb_disable_pcie_master - Disables PCI-express master access
1470 * @hw: pointer to the HW structure
1472 * Returns 0 (0) if successful, else returns -10
1473 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1474 * the master requests to be disabled.
1476 * Disables PCI-Express master access and verifies there are no pending
1479 s32
igb_disable_pcie_master(struct e1000_hw
*hw
)
1482 s32 timeout
= MASTER_DISABLE_TIMEOUT
;
1485 if (hw
->bus
.type
!= e1000_bus_type_pci_express
)
1488 ctrl
= rd32(E1000_CTRL
);
1489 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
1490 wr32(E1000_CTRL
, ctrl
);
1493 if (!(rd32(E1000_STATUS
) &
1494 E1000_STATUS_GIO_MASTER_ENABLE
))
1501 hw_dbg("Master requests are pending.\n");
1502 ret_val
= -E1000_ERR_MASTER_REQUESTS_PENDING
;
1511 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1512 * @hw: pointer to the HW structure
1514 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1515 * set, which is forced to MDI mode only.
1517 s32
igb_validate_mdi_setting(struct e1000_hw
*hw
)
1521 /* All MDI settings are supported on 82580 and newer. */
1522 if (hw
->mac
.type
>= e1000_82580
)
1525 if (!hw
->mac
.autoneg
&& (hw
->phy
.mdix
== 0 || hw
->phy
.mdix
== 3)) {
1526 hw_dbg("Invalid MDI setting detected\n");
1528 ret_val
= -E1000_ERR_CONFIG
;
1537 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1538 * @hw: pointer to the HW structure
1539 * @reg: 32bit register offset such as E1000_SCTL
1540 * @offset: register offset to write to
1541 * @data: data to write at register offset
1543 * Writes an address/data control type register. There are several of these
1544 * and they all have the format address << 8 | data and bit 31 is polled for
1547 s32
igb_write_8bit_ctrl_reg(struct e1000_hw
*hw
, u32 reg
,
1548 u32 offset
, u8 data
)
1550 u32 i
, regvalue
= 0;
1553 /* Set up the address and data */
1554 regvalue
= ((u32
)data
) | (offset
<< E1000_GEN_CTL_ADDRESS_SHIFT
);
1555 wr32(reg
, regvalue
);
1557 /* Poll the ready bit to see if the MDI read completed */
1558 for (i
= 0; i
< E1000_GEN_POLL_TIMEOUT
; i
++) {
1560 regvalue
= rd32(reg
);
1561 if (regvalue
& E1000_GEN_CTL_READY
)
1564 if (!(regvalue
& E1000_GEN_CTL_READY
)) {
1565 hw_dbg("Reg %08x did not indicate ready\n", reg
);
1566 ret_val
= -E1000_ERR_PHY
;
1575 * igb_enable_mng_pass_thru - Enable processing of ARP's
1576 * @hw: pointer to the HW structure
1578 * Verifies the hardware needs to leave interface enabled so that frames can
1579 * be directed to and from the management interface.
1581 bool igb_enable_mng_pass_thru(struct e1000_hw
*hw
)
1585 bool ret_val
= false;
1587 if (!hw
->mac
.asf_firmware_present
)
1590 manc
= rd32(E1000_MANC
);
1592 if (!(manc
& E1000_MANC_RCV_TCO_EN
))
1595 if (hw
->mac
.arc_subsystem_valid
) {
1596 fwsm
= rd32(E1000_FWSM
);
1597 factps
= rd32(E1000_FACTPS
);
1599 if (!(factps
& E1000_FACTPS_MNGCG
) &&
1600 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1601 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
))) {
1606 if ((manc
& E1000_MANC_SMBUS_EN
) &&
1607 !(manc
& E1000_MANC_ASF_EN
)) {