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igb: Cleanups to fix incorrect indentation
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_nvm.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25 *******************************************************************************/
26
27 #include <linux/if_ether.h>
28 #include <linux/delay.h>
29
30 #include "e1000_mac.h"
31 #include "e1000_nvm.h"
32
33 /**
34 * igb_raise_eec_clk - Raise EEPROM clock
35 * @hw: pointer to the HW structure
36 * @eecd: pointer to the EEPROM
37 *
38 * Enable/Raise the EEPROM clock bit.
39 **/
40 static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
41 {
42 *eecd = *eecd | E1000_EECD_SK;
43 wr32(E1000_EECD, *eecd);
44 wrfl();
45 udelay(hw->nvm.delay_usec);
46 }
47
48 /**
49 * igb_lower_eec_clk - Lower EEPROM clock
50 * @hw: pointer to the HW structure
51 * @eecd: pointer to the EEPROM
52 *
53 * Clear/Lower the EEPROM clock bit.
54 **/
55 static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
56 {
57 *eecd = *eecd & ~E1000_EECD_SK;
58 wr32(E1000_EECD, *eecd);
59 wrfl();
60 udelay(hw->nvm.delay_usec);
61 }
62
63 /**
64 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM
65 * @hw: pointer to the HW structure
66 * @data: data to send to the EEPROM
67 * @count: number of bits to shift out
68 *
69 * We need to shift 'count' bits out to the EEPROM. So, the value in the
70 * "data" parameter will be shifted out to the EEPROM one bit at a time.
71 * In order to do this, "data" must be broken down into bits.
72 **/
73 static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
74 {
75 struct e1000_nvm_info *nvm = &hw->nvm;
76 u32 eecd = rd32(E1000_EECD);
77 u32 mask;
78
79 mask = 0x01 << (count - 1);
80 if (nvm->type == e1000_nvm_eeprom_spi)
81 eecd |= E1000_EECD_DO;
82
83 do {
84 eecd &= ~E1000_EECD_DI;
85
86 if (data & mask)
87 eecd |= E1000_EECD_DI;
88
89 wr32(E1000_EECD, eecd);
90 wrfl();
91
92 udelay(nvm->delay_usec);
93
94 igb_raise_eec_clk(hw, &eecd);
95 igb_lower_eec_clk(hw, &eecd);
96
97 mask >>= 1;
98 } while (mask);
99
100 eecd &= ~E1000_EECD_DI;
101 wr32(E1000_EECD, eecd);
102 }
103
104 /**
105 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM
106 * @hw: pointer to the HW structure
107 * @count: number of bits to shift in
108 *
109 * In order to read a register from the EEPROM, we need to shift 'count' bits
110 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
111 * the EEPROM (setting the SK bit), and then reading the value of the data out
112 * "DO" bit. During this "shifting in" process the data in "DI" bit should
113 * always be clear.
114 **/
115 static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
116 {
117 u32 eecd;
118 u32 i;
119 u16 data;
120
121 eecd = rd32(E1000_EECD);
122
123 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
124 data = 0;
125
126 for (i = 0; i < count; i++) {
127 data <<= 1;
128 igb_raise_eec_clk(hw, &eecd);
129
130 eecd = rd32(E1000_EECD);
131
132 eecd &= ~E1000_EECD_DI;
133 if (eecd & E1000_EECD_DO)
134 data |= 1;
135
136 igb_lower_eec_clk(hw, &eecd);
137 }
138
139 return data;
140 }
141
142 /**
143 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
144 * @hw: pointer to the HW structure
145 * @ee_reg: EEPROM flag for polling
146 *
147 * Polls the EEPROM status bit for either read or write completion based
148 * upon the value of 'ee_reg'.
149 **/
150 static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
151 {
152 u32 attempts = 100000;
153 u32 i, reg = 0;
154 s32 ret_val = -E1000_ERR_NVM;
155
156 for (i = 0; i < attempts; i++) {
157 if (ee_reg == E1000_NVM_POLL_READ)
158 reg = rd32(E1000_EERD);
159 else
160 reg = rd32(E1000_EEWR);
161
162 if (reg & E1000_NVM_RW_REG_DONE) {
163 ret_val = 0;
164 break;
165 }
166
167 udelay(5);
168 }
169
170 return ret_val;
171 }
172
173 /**
174 * igb_acquire_nvm - Generic request for access to EEPROM
175 * @hw: pointer to the HW structure
176 *
177 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
178 * Return successful if access grant bit set, else clear the request for
179 * EEPROM access and return -E1000_ERR_NVM (-1).
180 **/
181 s32 igb_acquire_nvm(struct e1000_hw *hw)
182 {
183 u32 eecd = rd32(E1000_EECD);
184 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
185 s32 ret_val = 0;
186
187
188 wr32(E1000_EECD, eecd | E1000_EECD_REQ);
189 eecd = rd32(E1000_EECD);
190
191 while (timeout) {
192 if (eecd & E1000_EECD_GNT)
193 break;
194 udelay(5);
195 eecd = rd32(E1000_EECD);
196 timeout--;
197 }
198
199 if (!timeout) {
200 eecd &= ~E1000_EECD_REQ;
201 wr32(E1000_EECD, eecd);
202 hw_dbg("Could not acquire NVM grant\n");
203 ret_val = -E1000_ERR_NVM;
204 }
205
206 return ret_val;
207 }
208
209 /**
210 * igb_standby_nvm - Return EEPROM to standby state
211 * @hw: pointer to the HW structure
212 *
213 * Return the EEPROM to a standby state.
214 **/
215 static void igb_standby_nvm(struct e1000_hw *hw)
216 {
217 struct e1000_nvm_info *nvm = &hw->nvm;
218 u32 eecd = rd32(E1000_EECD);
219
220 if (nvm->type == e1000_nvm_eeprom_spi) {
221 /* Toggle CS to flush commands */
222 eecd |= E1000_EECD_CS;
223 wr32(E1000_EECD, eecd);
224 wrfl();
225 udelay(nvm->delay_usec);
226 eecd &= ~E1000_EECD_CS;
227 wr32(E1000_EECD, eecd);
228 wrfl();
229 udelay(nvm->delay_usec);
230 }
231 }
232
233 /**
234 * e1000_stop_nvm - Terminate EEPROM command
235 * @hw: pointer to the HW structure
236 *
237 * Terminates the current command by inverting the EEPROM's chip select pin.
238 **/
239 static void e1000_stop_nvm(struct e1000_hw *hw)
240 {
241 u32 eecd;
242
243 eecd = rd32(E1000_EECD);
244 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
245 /* Pull CS high */
246 eecd |= E1000_EECD_CS;
247 igb_lower_eec_clk(hw, &eecd);
248 }
249 }
250
251 /**
252 * igb_release_nvm - Release exclusive access to EEPROM
253 * @hw: pointer to the HW structure
254 *
255 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
256 **/
257 void igb_release_nvm(struct e1000_hw *hw)
258 {
259 u32 eecd;
260
261 e1000_stop_nvm(hw);
262
263 eecd = rd32(E1000_EECD);
264 eecd &= ~E1000_EECD_REQ;
265 wr32(E1000_EECD, eecd);
266 }
267
268 /**
269 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write
270 * @hw: pointer to the HW structure
271 *
272 * Setups the EEPROM for reading and writing.
273 **/
274 static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
275 {
276 struct e1000_nvm_info *nvm = &hw->nvm;
277 u32 eecd = rd32(E1000_EECD);
278 s32 ret_val = 0;
279 u16 timeout = 0;
280 u8 spi_stat_reg;
281
282
283 if (nvm->type == e1000_nvm_eeprom_spi) {
284 /* Clear SK and CS */
285 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
286 wr32(E1000_EECD, eecd);
287 wrfl();
288 udelay(1);
289 timeout = NVM_MAX_RETRY_SPI;
290
291 /* Read "Status Register" repeatedly until the LSB is cleared.
292 * The EEPROM will signal that the command has been completed
293 * by clearing bit 0 of the internal status register. If it's
294 * not cleared within 'timeout', then error out.
295 */
296 while (timeout) {
297 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
298 hw->nvm.opcode_bits);
299 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
300 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
301 break;
302
303 udelay(5);
304 igb_standby_nvm(hw);
305 timeout--;
306 }
307
308 if (!timeout) {
309 hw_dbg("SPI NVM Status error\n");
310 ret_val = -E1000_ERR_NVM;
311 goto out;
312 }
313 }
314
315 out:
316 return ret_val;
317 }
318
319 /**
320 * igb_read_nvm_spi - Read EEPROM's using SPI
321 * @hw: pointer to the HW structure
322 * @offset: offset of word in the EEPROM to read
323 * @words: number of words to read
324 * @data: word read from the EEPROM
325 *
326 * Reads a 16 bit word from the EEPROM.
327 **/
328 s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
329 {
330 struct e1000_nvm_info *nvm = &hw->nvm;
331 u32 i = 0;
332 s32 ret_val;
333 u16 word_in;
334 u8 read_opcode = NVM_READ_OPCODE_SPI;
335
336 /* A check for invalid values: offset too large, too many words,
337 * and not enough words.
338 */
339 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
340 (words == 0)) {
341 hw_dbg("nvm parameter(s) out of bounds\n");
342 ret_val = -E1000_ERR_NVM;
343 goto out;
344 }
345
346 ret_val = nvm->ops.acquire(hw);
347 if (ret_val)
348 goto out;
349
350 ret_val = igb_ready_nvm_eeprom(hw);
351 if (ret_val)
352 goto release;
353
354 igb_standby_nvm(hw);
355
356 if ((nvm->address_bits == 8) && (offset >= 128))
357 read_opcode |= NVM_A8_OPCODE_SPI;
358
359 /* Send the READ command (opcode + addr) */
360 igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
361 igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
362
363 /* Read the data. SPI NVMs increment the address with each byte
364 * read and will roll over if reading beyond the end. This allows
365 * us to read the whole NVM from any offset
366 */
367 for (i = 0; i < words; i++) {
368 word_in = igb_shift_in_eec_bits(hw, 16);
369 data[i] = (word_in >> 8) | (word_in << 8);
370 }
371
372 release:
373 nvm->ops.release(hw);
374
375 out:
376 return ret_val;
377 }
378
379 /**
380 * igb_read_nvm_eerd - Reads EEPROM using EERD register
381 * @hw: pointer to the HW structure
382 * @offset: offset of word in the EEPROM to read
383 * @words: number of words to read
384 * @data: word read from the EEPROM
385 *
386 * Reads a 16 bit word from the EEPROM using the EERD register.
387 **/
388 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
389 {
390 struct e1000_nvm_info *nvm = &hw->nvm;
391 u32 i, eerd = 0;
392 s32 ret_val = 0;
393
394 /* A check for invalid values: offset too large, too many words,
395 * and not enough words.
396 */
397 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
398 (words == 0)) {
399 hw_dbg("nvm parameter(s) out of bounds\n");
400 ret_val = -E1000_ERR_NVM;
401 goto out;
402 }
403
404 for (i = 0; i < words; i++) {
405 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
406 E1000_NVM_RW_REG_START;
407
408 wr32(E1000_EERD, eerd);
409 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
410 if (ret_val)
411 break;
412
413 data[i] = (rd32(E1000_EERD) >>
414 E1000_NVM_RW_REG_DATA);
415 }
416
417 out:
418 return ret_val;
419 }
420
421 /**
422 * igb_write_nvm_spi - Write to EEPROM using SPI
423 * @hw: pointer to the HW structure
424 * @offset: offset within the EEPROM to be written to
425 * @words: number of words to write
426 * @data: 16 bit word(s) to be written to the EEPROM
427 *
428 * Writes data to EEPROM at offset using SPI interface.
429 *
430 * If e1000_update_nvm_checksum is not called after this function , the
431 * EEPROM will most likley contain an invalid checksum.
432 **/
433 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
434 {
435 struct e1000_nvm_info *nvm = &hw->nvm;
436 s32 ret_val = -E1000_ERR_NVM;
437 u16 widx = 0;
438
439 /* A check for invalid values: offset too large, too many words,
440 * and not enough words.
441 */
442 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
443 (words == 0)) {
444 hw_dbg("nvm parameter(s) out of bounds\n");
445 return ret_val;
446 }
447
448 while (widx < words) {
449 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
450
451 ret_val = nvm->ops.acquire(hw);
452 if (ret_val)
453 return ret_val;
454
455 ret_val = igb_ready_nvm_eeprom(hw);
456 if (ret_val) {
457 nvm->ops.release(hw);
458 return ret_val;
459 }
460
461 igb_standby_nvm(hw);
462
463 /* Send the WRITE ENABLE command (8 bit opcode) */
464 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
465 nvm->opcode_bits);
466
467 igb_standby_nvm(hw);
468
469 /* Some SPI eeproms use the 8th address bit embedded in the
470 * opcode
471 */
472 if ((nvm->address_bits == 8) && (offset >= 128))
473 write_opcode |= NVM_A8_OPCODE_SPI;
474
475 /* Send the Write command (8-bit opcode + addr) */
476 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
477 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
478 nvm->address_bits);
479
480 /* Loop to allow for up to whole page write of eeprom */
481 while (widx < words) {
482 u16 word_out = data[widx];
483
484 word_out = (word_out >> 8) | (word_out << 8);
485 igb_shift_out_eec_bits(hw, word_out, 16);
486 widx++;
487
488 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
489 igb_standby_nvm(hw);
490 break;
491 }
492 }
493 usleep_range(1000, 2000);
494 nvm->ops.release(hw);
495 }
496
497 return ret_val;
498 }
499
500 /**
501 * igb_read_part_string - Read device part number
502 * @hw: pointer to the HW structure
503 * @part_num: pointer to device part number
504 * @part_num_size: size of part number buffer
505 *
506 * Reads the product board assembly (PBA) number from the EEPROM and stores
507 * the value in part_num.
508 **/
509 s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
510 {
511 s32 ret_val;
512 u16 nvm_data;
513 u16 pointer;
514 u16 offset;
515 u16 length;
516
517 if (part_num == NULL) {
518 hw_dbg("PBA string buffer was null\n");
519 ret_val = E1000_ERR_INVALID_ARGUMENT;
520 goto out;
521 }
522
523 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
524 if (ret_val) {
525 hw_dbg("NVM Read Error\n");
526 goto out;
527 }
528
529 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
530 if (ret_val) {
531 hw_dbg("NVM Read Error\n");
532 goto out;
533 }
534
535 /* if nvm_data is not ptr guard the PBA must be in legacy format which
536 * means pointer is actually our second data word for the PBA number
537 * and we can decode it into an ascii string
538 */
539 if (nvm_data != NVM_PBA_PTR_GUARD) {
540 hw_dbg("NVM PBA number is not stored as string\n");
541
542 /* we will need 11 characters to store the PBA */
543 if (part_num_size < 11) {
544 hw_dbg("PBA string buffer too small\n");
545 return E1000_ERR_NO_SPACE;
546 }
547
548 /* extract hex string from data and pointer */
549 part_num[0] = (nvm_data >> 12) & 0xF;
550 part_num[1] = (nvm_data >> 8) & 0xF;
551 part_num[2] = (nvm_data >> 4) & 0xF;
552 part_num[3] = nvm_data & 0xF;
553 part_num[4] = (pointer >> 12) & 0xF;
554 part_num[5] = (pointer >> 8) & 0xF;
555 part_num[6] = '-';
556 part_num[7] = 0;
557 part_num[8] = (pointer >> 4) & 0xF;
558 part_num[9] = pointer & 0xF;
559
560 /* put a null character on the end of our string */
561 part_num[10] = '\0';
562
563 /* switch all the data but the '-' to hex char */
564 for (offset = 0; offset < 10; offset++) {
565 if (part_num[offset] < 0xA)
566 part_num[offset] += '0';
567 else if (part_num[offset] < 0x10)
568 part_num[offset] += 'A' - 0xA;
569 }
570
571 goto out;
572 }
573
574 ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
575 if (ret_val) {
576 hw_dbg("NVM Read Error\n");
577 goto out;
578 }
579
580 if (length == 0xFFFF || length == 0) {
581 hw_dbg("NVM PBA number section invalid length\n");
582 ret_val = E1000_ERR_NVM_PBA_SECTION;
583 goto out;
584 }
585 /* check if part_num buffer is big enough */
586 if (part_num_size < (((u32)length * 2) - 1)) {
587 hw_dbg("PBA string buffer too small\n");
588 ret_val = E1000_ERR_NO_SPACE;
589 goto out;
590 }
591
592 /* trim pba length from start of string */
593 pointer++;
594 length--;
595
596 for (offset = 0; offset < length; offset++) {
597 ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
598 if (ret_val) {
599 hw_dbg("NVM Read Error\n");
600 goto out;
601 }
602 part_num[offset * 2] = (u8)(nvm_data >> 8);
603 part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
604 }
605 part_num[offset * 2] = '\0';
606
607 out:
608 return ret_val;
609 }
610
611 /**
612 * igb_read_mac_addr - Read device MAC address
613 * @hw: pointer to the HW structure
614 *
615 * Reads the device MAC address from the EEPROM and stores the value.
616 * Since devices with two ports use the same EEPROM, we increment the
617 * last bit in the MAC address for the second port.
618 **/
619 s32 igb_read_mac_addr(struct e1000_hw *hw)
620 {
621 u32 rar_high;
622 u32 rar_low;
623 u16 i;
624
625 rar_high = rd32(E1000_RAH(0));
626 rar_low = rd32(E1000_RAL(0));
627
628 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
629 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
630
631 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
632 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
633
634 for (i = 0; i < ETH_ALEN; i++)
635 hw->mac.addr[i] = hw->mac.perm_addr[i];
636
637 return 0;
638 }
639
640 /**
641 * igb_validate_nvm_checksum - Validate EEPROM checksum
642 * @hw: pointer to the HW structure
643 *
644 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
645 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
646 **/
647 s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
648 {
649 s32 ret_val = 0;
650 u16 checksum = 0;
651 u16 i, nvm_data;
652
653 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
654 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
655 if (ret_val) {
656 hw_dbg("NVM Read Error\n");
657 goto out;
658 }
659 checksum += nvm_data;
660 }
661
662 if (checksum != (u16) NVM_SUM) {
663 hw_dbg("NVM Checksum Invalid\n");
664 ret_val = -E1000_ERR_NVM;
665 goto out;
666 }
667
668 out:
669 return ret_val;
670 }
671
672 /**
673 * igb_update_nvm_checksum - Update EEPROM checksum
674 * @hw: pointer to the HW structure
675 *
676 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
677 * up to the checksum. Then calculates the EEPROM checksum and writes the
678 * value to the EEPROM.
679 **/
680 s32 igb_update_nvm_checksum(struct e1000_hw *hw)
681 {
682 s32 ret_val;
683 u16 checksum = 0;
684 u16 i, nvm_data;
685
686 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
687 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
688 if (ret_val) {
689 hw_dbg("NVM Read Error while updating checksum.\n");
690 goto out;
691 }
692 checksum += nvm_data;
693 }
694 checksum = (u16) NVM_SUM - checksum;
695 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
696 if (ret_val)
697 hw_dbg("NVM Write Error while updating checksum.\n");
698
699 out:
700 return ret_val;
701 }
702
703 /**
704 * igb_get_fw_version - Get firmware version information
705 * @hw: pointer to the HW structure
706 * @fw_vers: pointer to output structure
707 *
708 * unsupported MAC types will return all 0 version structure
709 **/
710 void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
711 {
712 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
713 u8 q, hval, rem, result;
714 u16 comb_verh, comb_verl, comb_offset;
715
716 memset(fw_vers, 0, sizeof(struct e1000_fw_version));
717
718 /* basic eeprom version numbers and bits used vary by part and by tool
719 * used to create the nvm images. Check which data format we have.
720 */
721 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
722 switch (hw->mac.type) {
723 case e1000_i211:
724 igb_read_invm_version(hw, fw_vers);
725 return;
726 case e1000_82575:
727 case e1000_82576:
728 case e1000_82580:
729 /* Use this format, unless EETRACK ID exists,
730 * then use alternate format
731 */
732 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
733 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
734 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
735 >> NVM_MAJOR_SHIFT;
736 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
737 >> NVM_MINOR_SHIFT;
738 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
739 goto etrack_id;
740 }
741 break;
742 case e1000_i210:
743 if (!(igb_get_flash_presence_i210(hw))) {
744 igb_read_invm_version(hw, fw_vers);
745 return;
746 }
747 /* fall through */
748 case e1000_i350:
749 /* find combo image version */
750 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
751 if ((comb_offset != 0x0) &&
752 (comb_offset != NVM_VER_INVALID)) {
753
754 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
755 + 1), 1, &comb_verh);
756 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
757 1, &comb_verl);
758
759 /* get Option Rom version if it exists and is valid */
760 if ((comb_verh && comb_verl) &&
761 ((comb_verh != NVM_VER_INVALID) &&
762 (comb_verl != NVM_VER_INVALID))) {
763
764 fw_vers->or_valid = true;
765 fw_vers->or_major =
766 comb_verl >> NVM_COMB_VER_SHFT;
767 fw_vers->or_build =
768 (comb_verl << NVM_COMB_VER_SHFT)
769 | (comb_verh >> NVM_COMB_VER_SHFT);
770 fw_vers->or_patch =
771 comb_verh & NVM_COMB_VER_MASK;
772 }
773 }
774 break;
775 default:
776 return;
777 }
778 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
779 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
780 >> NVM_MAJOR_SHIFT;
781
782 /* check for old style version format in newer images*/
783 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
784 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
785 } else {
786 eeprom_verl = (fw_version & NVM_MINOR_MASK)
787 >> NVM_MINOR_SHIFT;
788 }
789 /* Convert minor value to hex before assigning to output struct
790 * Val to be converted will not be higher than 99, per tool output
791 */
792 q = eeprom_verl / NVM_HEX_CONV;
793 hval = q * NVM_HEX_TENS;
794 rem = eeprom_verl % NVM_HEX_CONV;
795 result = hval + rem;
796 fw_vers->eep_minor = result;
797
798 etrack_id:
799 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
800 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
801 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
802 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
803 | eeprom_verl;
804 }
805 return;
806 }
Linux kernel - Deliverables
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