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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_phy.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #include <linux/if_ether.h>
25 #include <linux/delay.h>
26
27 #include "e1000_mac.h"
28 #include "e1000_phy.h"
29
30 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
31 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
32 u16 *phy_ctrl);
33 static s32 igb_wait_autoneg(struct e1000_hw *hw);
34 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
35
36 /* Cable length tables */
37 static const u16 e1000_m88_cable_length_table[] = {
38 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
39
40 static const u16 e1000_igp_2_cable_length_table[] = {
41 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
42 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
43 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
44 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
45 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
46 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
47 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
48 104, 109, 114, 118, 121, 124};
49
50 /**
51 * igb_check_reset_block - Check if PHY reset is blocked
52 * @hw: pointer to the HW structure
53 *
54 * Read the PHY management control register and check whether a PHY reset
55 * is blocked. If a reset is not blocked return 0, otherwise
56 * return E1000_BLK_PHY_RESET (12).
57 **/
58 s32 igb_check_reset_block(struct e1000_hw *hw)
59 {
60 u32 manc;
61
62 manc = rd32(E1000_MANC);
63
64 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
65 }
66
67 /**
68 * igb_get_phy_id - Retrieve the PHY ID and revision
69 * @hw: pointer to the HW structure
70 *
71 * Reads the PHY registers and stores the PHY ID and possibly the PHY
72 * revision in the hardware structure.
73 **/
74 s32 igb_get_phy_id(struct e1000_hw *hw)
75 {
76 struct e1000_phy_info *phy = &hw->phy;
77 s32 ret_val = 0;
78 u16 phy_id;
79
80 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
81 if (ret_val)
82 goto out;
83
84 phy->id = (u32)(phy_id << 16);
85 udelay(20);
86 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
87 if (ret_val)
88 goto out;
89
90 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
91 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
92
93 out:
94 return ret_val;
95 }
96
97 /**
98 * igb_phy_reset_dsp - Reset PHY DSP
99 * @hw: pointer to the HW structure
100 *
101 * Reset the digital signal processor.
102 **/
103 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
104 {
105 s32 ret_val = 0;
106
107 if (!(hw->phy.ops.write_reg))
108 goto out;
109
110 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
111 if (ret_val)
112 goto out;
113
114 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
115
116 out:
117 return ret_val;
118 }
119
120 /**
121 * igb_read_phy_reg_mdic - Read MDI control register
122 * @hw: pointer to the HW structure
123 * @offset: register offset to be read
124 * @data: pointer to the read data
125 *
126 * Reads the MDI control regsiter in the PHY at offset and stores the
127 * information read to data.
128 **/
129 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
130 {
131 struct e1000_phy_info *phy = &hw->phy;
132 u32 i, mdic = 0;
133 s32 ret_val = 0;
134
135 if (offset > MAX_PHY_REG_ADDRESS) {
136 hw_dbg("PHY Address %d is out of range\n", offset);
137 ret_val = -E1000_ERR_PARAM;
138 goto out;
139 }
140
141 /* Set up Op-code, Phy Address, and register offset in the MDI
142 * Control register. The MAC will take care of interfacing with the
143 * PHY to retrieve the desired data.
144 */
145 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
146 (phy->addr << E1000_MDIC_PHY_SHIFT) |
147 (E1000_MDIC_OP_READ));
148
149 wr32(E1000_MDIC, mdic);
150
151 /* Poll the ready bit to see if the MDI read completed
152 * Increasing the time out as testing showed failures with
153 * the lower time out
154 */
155 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
156 udelay(50);
157 mdic = rd32(E1000_MDIC);
158 if (mdic & E1000_MDIC_READY)
159 break;
160 }
161 if (!(mdic & E1000_MDIC_READY)) {
162 hw_dbg("MDI Read did not complete\n");
163 ret_val = -E1000_ERR_PHY;
164 goto out;
165 }
166 if (mdic & E1000_MDIC_ERROR) {
167 hw_dbg("MDI Error\n");
168 ret_val = -E1000_ERR_PHY;
169 goto out;
170 }
171 *data = (u16) mdic;
172
173 out:
174 return ret_val;
175 }
176
177 /**
178 * igb_write_phy_reg_mdic - Write MDI control register
179 * @hw: pointer to the HW structure
180 * @offset: register offset to write to
181 * @data: data to write to register at offset
182 *
183 * Writes data to MDI control register in the PHY at offset.
184 **/
185 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
186 {
187 struct e1000_phy_info *phy = &hw->phy;
188 u32 i, mdic = 0;
189 s32 ret_val = 0;
190
191 if (offset > MAX_PHY_REG_ADDRESS) {
192 hw_dbg("PHY Address %d is out of range\n", offset);
193 ret_val = -E1000_ERR_PARAM;
194 goto out;
195 }
196
197 /* Set up Op-code, Phy Address, and register offset in the MDI
198 * Control register. The MAC will take care of interfacing with the
199 * PHY to retrieve the desired data.
200 */
201 mdic = (((u32)data) |
202 (offset << E1000_MDIC_REG_SHIFT) |
203 (phy->addr << E1000_MDIC_PHY_SHIFT) |
204 (E1000_MDIC_OP_WRITE));
205
206 wr32(E1000_MDIC, mdic);
207
208 /* Poll the ready bit to see if the MDI read completed
209 * Increasing the time out as testing showed failures with
210 * the lower time out
211 */
212 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
213 udelay(50);
214 mdic = rd32(E1000_MDIC);
215 if (mdic & E1000_MDIC_READY)
216 break;
217 }
218 if (!(mdic & E1000_MDIC_READY)) {
219 hw_dbg("MDI Write did not complete\n");
220 ret_val = -E1000_ERR_PHY;
221 goto out;
222 }
223 if (mdic & E1000_MDIC_ERROR) {
224 hw_dbg("MDI Error\n");
225 ret_val = -E1000_ERR_PHY;
226 goto out;
227 }
228
229 out:
230 return ret_val;
231 }
232
233 /**
234 * igb_read_phy_reg_i2c - Read PHY register using i2c
235 * @hw: pointer to the HW structure
236 * @offset: register offset to be read
237 * @data: pointer to the read data
238 *
239 * Reads the PHY register at offset using the i2c interface and stores the
240 * retrieved information in data.
241 **/
242 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
243 {
244 struct e1000_phy_info *phy = &hw->phy;
245 u32 i, i2ccmd = 0;
246
247 /* Set up Op-code, Phy Address, and register address in the I2CCMD
248 * register. The MAC will take care of interfacing with the
249 * PHY to retrieve the desired data.
250 */
251 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
252 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
253 (E1000_I2CCMD_OPCODE_READ));
254
255 wr32(E1000_I2CCMD, i2ccmd);
256
257 /* Poll the ready bit to see if the I2C read completed */
258 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
259 udelay(50);
260 i2ccmd = rd32(E1000_I2CCMD);
261 if (i2ccmd & E1000_I2CCMD_READY)
262 break;
263 }
264 if (!(i2ccmd & E1000_I2CCMD_READY)) {
265 hw_dbg("I2CCMD Read did not complete\n");
266 return -E1000_ERR_PHY;
267 }
268 if (i2ccmd & E1000_I2CCMD_ERROR) {
269 hw_dbg("I2CCMD Error bit set\n");
270 return -E1000_ERR_PHY;
271 }
272
273 /* Need to byte-swap the 16-bit value. */
274 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
275
276 return 0;
277 }
278
279 /**
280 * igb_write_phy_reg_i2c - Write PHY register using i2c
281 * @hw: pointer to the HW structure
282 * @offset: register offset to write to
283 * @data: data to write at register offset
284 *
285 * Writes the data to PHY register at the offset using the i2c interface.
286 **/
287 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
288 {
289 struct e1000_phy_info *phy = &hw->phy;
290 u32 i, i2ccmd = 0;
291 u16 phy_data_swapped;
292
293 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
294 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
295 hw_dbg("PHY I2C Address %d is out of range.\n",
296 hw->phy.addr);
297 return -E1000_ERR_CONFIG;
298 }
299
300 /* Swap the data bytes for the I2C interface */
301 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
302
303 /* Set up Op-code, Phy Address, and register address in the I2CCMD
304 * register. The MAC will take care of interfacing with the
305 * PHY to retrieve the desired data.
306 */
307 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
308 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
309 E1000_I2CCMD_OPCODE_WRITE |
310 phy_data_swapped);
311
312 wr32(E1000_I2CCMD, i2ccmd);
313
314 /* Poll the ready bit to see if the I2C read completed */
315 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
316 udelay(50);
317 i2ccmd = rd32(E1000_I2CCMD);
318 if (i2ccmd & E1000_I2CCMD_READY)
319 break;
320 }
321 if (!(i2ccmd & E1000_I2CCMD_READY)) {
322 hw_dbg("I2CCMD Write did not complete\n");
323 return -E1000_ERR_PHY;
324 }
325 if (i2ccmd & E1000_I2CCMD_ERROR) {
326 hw_dbg("I2CCMD Error bit set\n");
327 return -E1000_ERR_PHY;
328 }
329
330 return 0;
331 }
332
333 /**
334 * igb_read_sfp_data_byte - Reads SFP module data.
335 * @hw: pointer to the HW structure
336 * @offset: byte location offset to be read
337 * @data: read data buffer pointer
338 *
339 * Reads one byte from SFP module data stored
340 * in SFP resided EEPROM memory or SFP diagnostic area.
341 * Function should be called with
342 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
343 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
344 * access
345 **/
346 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
347 {
348 u32 i = 0;
349 u32 i2ccmd = 0;
350 u32 data_local = 0;
351
352 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
353 hw_dbg("I2CCMD command address exceeds upper limit\n");
354 return -E1000_ERR_PHY;
355 }
356
357 /* Set up Op-code, EEPROM Address,in the I2CCMD
358 * register. The MAC will take care of interfacing with the
359 * EEPROM to retrieve the desired data.
360 */
361 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
362 E1000_I2CCMD_OPCODE_READ);
363
364 wr32(E1000_I2CCMD, i2ccmd);
365
366 /* Poll the ready bit to see if the I2C read completed */
367 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
368 udelay(50);
369 data_local = rd32(E1000_I2CCMD);
370 if (data_local & E1000_I2CCMD_READY)
371 break;
372 }
373 if (!(data_local & E1000_I2CCMD_READY)) {
374 hw_dbg("I2CCMD Read did not complete\n");
375 return -E1000_ERR_PHY;
376 }
377 if (data_local & E1000_I2CCMD_ERROR) {
378 hw_dbg("I2CCMD Error bit set\n");
379 return -E1000_ERR_PHY;
380 }
381 *data = (u8) data_local & 0xFF;
382
383 return 0;
384 }
385
386 /**
387 * igb_read_phy_reg_igp - Read igp PHY register
388 * @hw: pointer to the HW structure
389 * @offset: register offset to be read
390 * @data: pointer to the read data
391 *
392 * Acquires semaphore, if necessary, then reads the PHY register at offset
393 * and storing the retrieved information in data. Release any acquired
394 * semaphores before exiting.
395 **/
396 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
397 {
398 s32 ret_val = 0;
399
400 if (!(hw->phy.ops.acquire))
401 goto out;
402
403 ret_val = hw->phy.ops.acquire(hw);
404 if (ret_val)
405 goto out;
406
407 if (offset > MAX_PHY_MULTI_PAGE_REG) {
408 ret_val = igb_write_phy_reg_mdic(hw,
409 IGP01E1000_PHY_PAGE_SELECT,
410 (u16)offset);
411 if (ret_val) {
412 hw->phy.ops.release(hw);
413 goto out;
414 }
415 }
416
417 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
418 data);
419
420 hw->phy.ops.release(hw);
421
422 out:
423 return ret_val;
424 }
425
426 /**
427 * igb_write_phy_reg_igp - Write igp PHY register
428 * @hw: pointer to the HW structure
429 * @offset: register offset to write to
430 * @data: data to write at register offset
431 *
432 * Acquires semaphore, if necessary, then writes the data to PHY register
433 * at the offset. Release any acquired semaphores before exiting.
434 **/
435 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
436 {
437 s32 ret_val = 0;
438
439 if (!(hw->phy.ops.acquire))
440 goto out;
441
442 ret_val = hw->phy.ops.acquire(hw);
443 if (ret_val)
444 goto out;
445
446 if (offset > MAX_PHY_MULTI_PAGE_REG) {
447 ret_val = igb_write_phy_reg_mdic(hw,
448 IGP01E1000_PHY_PAGE_SELECT,
449 (u16)offset);
450 if (ret_val) {
451 hw->phy.ops.release(hw);
452 goto out;
453 }
454 }
455
456 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
457 data);
458
459 hw->phy.ops.release(hw);
460
461 out:
462 return ret_val;
463 }
464
465 /**
466 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
467 * @hw: pointer to the HW structure
468 *
469 * Sets up Carrier-sense on Transmit and downshift values.
470 **/
471 s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
472 {
473 struct e1000_phy_info *phy = &hw->phy;
474 s32 ret_val;
475 u16 phy_data;
476
477 if (phy->reset_disable) {
478 ret_val = 0;
479 goto out;
480 }
481
482 if (phy->type == e1000_phy_82580) {
483 ret_val = hw->phy.ops.reset(hw);
484 if (ret_val) {
485 hw_dbg("Error resetting the PHY.\n");
486 goto out;
487 }
488 }
489
490 /* Enable CRS on TX. This must be set for half-duplex operation. */
491 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
492 if (ret_val)
493 goto out;
494
495 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
496
497 /* Enable downshift */
498 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
499
500 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
501 if (ret_val)
502 goto out;
503
504 /* Set MDI/MDIX mode */
505 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
506 if (ret_val)
507 goto out;
508 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
509 /* Options:
510 * 0 - Auto (default)
511 * 1 - MDI mode
512 * 2 - MDI-X mode
513 */
514 switch (hw->phy.mdix) {
515 case 1:
516 break;
517 case 2:
518 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
519 break;
520 case 0:
521 default:
522 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
523 break;
524 }
525 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
526
527 out:
528 return ret_val;
529 }
530
531 /**
532 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
533 * @hw: pointer to the HW structure
534 *
535 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
536 * and downshift values are set also.
537 **/
538 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
539 {
540 struct e1000_phy_info *phy = &hw->phy;
541 s32 ret_val;
542 u16 phy_data;
543
544 if (phy->reset_disable) {
545 ret_val = 0;
546 goto out;
547 }
548
549 /* Enable CRS on TX. This must be set for half-duplex operation. */
550 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
551 if (ret_val)
552 goto out;
553
554 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
555
556 /* Options:
557 * MDI/MDI-X = 0 (default)
558 * 0 - Auto for all speeds
559 * 1 - MDI mode
560 * 2 - MDI-X mode
561 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
562 */
563 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
564
565 switch (phy->mdix) {
566 case 1:
567 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
568 break;
569 case 2:
570 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
571 break;
572 case 3:
573 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
574 break;
575 case 0:
576 default:
577 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
578 break;
579 }
580
581 /* Options:
582 * disable_polarity_correction = 0 (default)
583 * Automatic Correction for Reversed Cable Polarity
584 * 0 - Disabled
585 * 1 - Enabled
586 */
587 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
588 if (phy->disable_polarity_correction == 1)
589 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
590
591 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
592 if (ret_val)
593 goto out;
594
595 if (phy->revision < E1000_REVISION_4) {
596 /* Force TX_CLK in the Extended PHY Specific Control Register
597 * to 25MHz clock.
598 */
599 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
600 &phy_data);
601 if (ret_val)
602 goto out;
603
604 phy_data |= M88E1000_EPSCR_TX_CLK_25;
605
606 if ((phy->revision == E1000_REVISION_2) &&
607 (phy->id == M88E1111_I_PHY_ID)) {
608 /* 82573L PHY - set the downshift counter to 5x. */
609 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
610 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
611 } else {
612 /* Configure Master and Slave downshift values */
613 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
614 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
615 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
616 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
617 }
618 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
619 phy_data);
620 if (ret_val)
621 goto out;
622 }
623
624 /* Commit the changes. */
625 ret_val = igb_phy_sw_reset(hw);
626 if (ret_val) {
627 hw_dbg("Error committing the PHY changes\n");
628 goto out;
629 }
630
631 out:
632 return ret_val;
633 }
634
635 /**
636 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
637 * @hw: pointer to the HW structure
638 *
639 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
640 * Also enables and sets the downshift parameters.
641 **/
642 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
643 {
644 struct e1000_phy_info *phy = &hw->phy;
645 s32 ret_val;
646 u16 phy_data;
647
648 if (phy->reset_disable)
649 return 0;
650
651 /* Enable CRS on Tx. This must be set for half-duplex operation. */
652 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
653 if (ret_val)
654 return ret_val;
655
656 /* Options:
657 * MDI/MDI-X = 0 (default)
658 * 0 - Auto for all speeds
659 * 1 - MDI mode
660 * 2 - MDI-X mode
661 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
662 */
663 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
664
665 switch (phy->mdix) {
666 case 1:
667 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
668 break;
669 case 2:
670 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
671 break;
672 case 3:
673 /* M88E1112 does not support this mode) */
674 if (phy->id != M88E1112_E_PHY_ID) {
675 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
676 break;
677 }
678 case 0:
679 default:
680 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
681 break;
682 }
683
684 /* Options:
685 * disable_polarity_correction = 0 (default)
686 * Automatic Correction for Reversed Cable Polarity
687 * 0 - Disabled
688 * 1 - Enabled
689 */
690 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
691 if (phy->disable_polarity_correction == 1)
692 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
693
694 /* Enable downshift and setting it to X6 */
695 if (phy->id == M88E1543_E_PHY_ID) {
696 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
697 ret_val =
698 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
699 if (ret_val)
700 return ret_val;
701
702 ret_val = igb_phy_sw_reset(hw);
703 if (ret_val) {
704 hw_dbg("Error committing the PHY changes\n");
705 return ret_val;
706 }
707 }
708
709 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
710 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
711 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
712
713 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
714 if (ret_val)
715 return ret_val;
716
717 /* Commit the changes. */
718 ret_val = igb_phy_sw_reset(hw);
719 if (ret_val) {
720 hw_dbg("Error committing the PHY changes\n");
721 return ret_val;
722 }
723 ret_val = igb_set_master_slave_mode(hw);
724 if (ret_val)
725 return ret_val;
726
727 return 0;
728 }
729
730 /**
731 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
732 * @hw: pointer to the HW structure
733 *
734 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
735 * igp PHY's.
736 **/
737 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
738 {
739 struct e1000_phy_info *phy = &hw->phy;
740 s32 ret_val;
741 u16 data;
742
743 if (phy->reset_disable) {
744 ret_val = 0;
745 goto out;
746 }
747
748 ret_val = phy->ops.reset(hw);
749 if (ret_val) {
750 hw_dbg("Error resetting the PHY.\n");
751 goto out;
752 }
753
754 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
755 * timeout issues when LFS is enabled.
756 */
757 msleep(100);
758
759 /* The NVM settings will configure LPLU in D3 for
760 * non-IGP1 PHYs.
761 */
762 if (phy->type == e1000_phy_igp) {
763 /* disable lplu d3 during driver init */
764 if (phy->ops.set_d3_lplu_state)
765 ret_val = phy->ops.set_d3_lplu_state(hw, false);
766 if (ret_val) {
767 hw_dbg("Error Disabling LPLU D3\n");
768 goto out;
769 }
770 }
771
772 /* disable lplu d0 during driver init */
773 ret_val = phy->ops.set_d0_lplu_state(hw, false);
774 if (ret_val) {
775 hw_dbg("Error Disabling LPLU D0\n");
776 goto out;
777 }
778 /* Configure mdi-mdix settings */
779 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
780 if (ret_val)
781 goto out;
782
783 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
784
785 switch (phy->mdix) {
786 case 1:
787 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
788 break;
789 case 2:
790 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
791 break;
792 case 0:
793 default:
794 data |= IGP01E1000_PSCR_AUTO_MDIX;
795 break;
796 }
797 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
798 if (ret_val)
799 goto out;
800
801 /* set auto-master slave resolution settings */
802 if (hw->mac.autoneg) {
803 /* when autonegotiation advertisement is only 1000Mbps then we
804 * should disable SmartSpeed and enable Auto MasterSlave
805 * resolution as hardware default.
806 */
807 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
808 /* Disable SmartSpeed */
809 ret_val = phy->ops.read_reg(hw,
810 IGP01E1000_PHY_PORT_CONFIG,
811 &data);
812 if (ret_val)
813 goto out;
814
815 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
816 ret_val = phy->ops.write_reg(hw,
817 IGP01E1000_PHY_PORT_CONFIG,
818 data);
819 if (ret_val)
820 goto out;
821
822 /* Set auto Master/Slave resolution process */
823 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
824 if (ret_val)
825 goto out;
826
827 data &= ~CR_1000T_MS_ENABLE;
828 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
829 if (ret_val)
830 goto out;
831 }
832
833 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
834 if (ret_val)
835 goto out;
836
837 /* load defaults for future use */
838 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
839 ((data & CR_1000T_MS_VALUE) ?
840 e1000_ms_force_master :
841 e1000_ms_force_slave) :
842 e1000_ms_auto;
843
844 switch (phy->ms_type) {
845 case e1000_ms_force_master:
846 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
847 break;
848 case e1000_ms_force_slave:
849 data |= CR_1000T_MS_ENABLE;
850 data &= ~(CR_1000T_MS_VALUE);
851 break;
852 case e1000_ms_auto:
853 data &= ~CR_1000T_MS_ENABLE;
854 default:
855 break;
856 }
857 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
858 if (ret_val)
859 goto out;
860 }
861
862 out:
863 return ret_val;
864 }
865
866 /**
867 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
868 * @hw: pointer to the HW structure
869 *
870 * Performs initial bounds checking on autoneg advertisement parameter, then
871 * configure to advertise the full capability. Setup the PHY to autoneg
872 * and restart the negotiation process between the link partner. If
873 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
874 **/
875 static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
876 {
877 struct e1000_phy_info *phy = &hw->phy;
878 s32 ret_val;
879 u16 phy_ctrl;
880
881 /* Perform some bounds checking on the autoneg advertisement
882 * parameter.
883 */
884 phy->autoneg_advertised &= phy->autoneg_mask;
885
886 /* If autoneg_advertised is zero, we assume it was not defaulted
887 * by the calling code so we set to advertise full capability.
888 */
889 if (phy->autoneg_advertised == 0)
890 phy->autoneg_advertised = phy->autoneg_mask;
891
892 hw_dbg("Reconfiguring auto-neg advertisement params\n");
893 ret_val = igb_phy_setup_autoneg(hw);
894 if (ret_val) {
895 hw_dbg("Error Setting up Auto-Negotiation\n");
896 goto out;
897 }
898 hw_dbg("Restarting Auto-Neg\n");
899
900 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
901 * the Auto Neg Restart bit in the PHY control register.
902 */
903 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
904 if (ret_val)
905 goto out;
906
907 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
908 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
909 if (ret_val)
910 goto out;
911
912 /* Does the user want to wait for Auto-Neg to complete here, or
913 * check at a later time (for example, callback routine).
914 */
915 if (phy->autoneg_wait_to_complete) {
916 ret_val = igb_wait_autoneg(hw);
917 if (ret_val) {
918 hw_dbg("Error while waiting for autoneg to complete\n");
919 goto out;
920 }
921 }
922
923 hw->mac.get_link_status = true;
924
925 out:
926 return ret_val;
927 }
928
929 /**
930 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
931 * @hw: pointer to the HW structure
932 *
933 * Reads the MII auto-neg advertisement register and/or the 1000T control
934 * register and if the PHY is already setup for auto-negotiation, then
935 * return successful. Otherwise, setup advertisement and flow control to
936 * the appropriate values for the wanted auto-negotiation.
937 **/
938 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
939 {
940 struct e1000_phy_info *phy = &hw->phy;
941 s32 ret_val;
942 u16 mii_autoneg_adv_reg;
943 u16 mii_1000t_ctrl_reg = 0;
944
945 phy->autoneg_advertised &= phy->autoneg_mask;
946
947 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
948 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
949 if (ret_val)
950 goto out;
951
952 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
953 /* Read the MII 1000Base-T Control Register (Address 9). */
954 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
955 &mii_1000t_ctrl_reg);
956 if (ret_val)
957 goto out;
958 }
959
960 /* Need to parse both autoneg_advertised and fc and set up
961 * the appropriate PHY registers. First we will parse for
962 * autoneg_advertised software override. Since we can advertise
963 * a plethora of combinations, we need to check each bit
964 * individually.
965 */
966
967 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
968 * Advertisement Register (Address 4) and the 1000 mb speed bits in
969 * the 1000Base-T Control Register (Address 9).
970 */
971 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
972 NWAY_AR_100TX_HD_CAPS |
973 NWAY_AR_10T_FD_CAPS |
974 NWAY_AR_10T_HD_CAPS);
975 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
976
977 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
978
979 /* Do we want to advertise 10 Mb Half Duplex? */
980 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
981 hw_dbg("Advertise 10mb Half duplex\n");
982 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
983 }
984
985 /* Do we want to advertise 10 Mb Full Duplex? */
986 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
987 hw_dbg("Advertise 10mb Full duplex\n");
988 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
989 }
990
991 /* Do we want to advertise 100 Mb Half Duplex? */
992 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
993 hw_dbg("Advertise 100mb Half duplex\n");
994 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
995 }
996
997 /* Do we want to advertise 100 Mb Full Duplex? */
998 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
999 hw_dbg("Advertise 100mb Full duplex\n");
1000 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1001 }
1002
1003 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1004 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1005 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1006
1007 /* Do we want to advertise 1000 Mb Full Duplex? */
1008 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1009 hw_dbg("Advertise 1000mb Full duplex\n");
1010 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1011 }
1012
1013 /* Check for a software override of the flow control settings, and
1014 * setup the PHY advertisement registers accordingly. If
1015 * auto-negotiation is enabled, then software will have to set the
1016 * "PAUSE" bits to the correct value in the Auto-Negotiation
1017 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1018 * negotiation.
1019 *
1020 * The possible values of the "fc" parameter are:
1021 * 0: Flow control is completely disabled
1022 * 1: Rx flow control is enabled (we can receive pause frames
1023 * but not send pause frames).
1024 * 2: Tx flow control is enabled (we can send pause frames
1025 * but we do not support receiving pause frames).
1026 * 3: Both Rx and TX flow control (symmetric) are enabled.
1027 * other: No software override. The flow control configuration
1028 * in the EEPROM is used.
1029 */
1030 switch (hw->fc.current_mode) {
1031 case e1000_fc_none:
1032 /* Flow control (RX & TX) is completely disabled by a
1033 * software over-ride.
1034 */
1035 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1036 break;
1037 case e1000_fc_rx_pause:
1038 /* RX Flow control is enabled, and TX Flow control is
1039 * disabled, by a software over-ride.
1040 *
1041 * Since there really isn't a way to advertise that we are
1042 * capable of RX Pause ONLY, we will advertise that we
1043 * support both symmetric and asymmetric RX PAUSE. Later
1044 * (in e1000_config_fc_after_link_up) we will disable the
1045 * hw's ability to send PAUSE frames.
1046 */
1047 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1048 break;
1049 case e1000_fc_tx_pause:
1050 /* TX Flow control is enabled, and RX Flow control is
1051 * disabled, by a software over-ride.
1052 */
1053 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1054 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1055 break;
1056 case e1000_fc_full:
1057 /* Flow control (both RX and TX) is enabled by a software
1058 * over-ride.
1059 */
1060 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1061 break;
1062 default:
1063 hw_dbg("Flow control param set incorrectly\n");
1064 ret_val = -E1000_ERR_CONFIG;
1065 goto out;
1066 }
1067
1068 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1069 if (ret_val)
1070 goto out;
1071
1072 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1073
1074 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1075 ret_val = phy->ops.write_reg(hw,
1076 PHY_1000T_CTRL,
1077 mii_1000t_ctrl_reg);
1078 if (ret_val)
1079 goto out;
1080 }
1081
1082 out:
1083 return ret_val;
1084 }
1085
1086 /**
1087 * igb_setup_copper_link - Configure copper link settings
1088 * @hw: pointer to the HW structure
1089 *
1090 * Calls the appropriate function to configure the link for auto-neg or forced
1091 * speed and duplex. Then we check for link, once link is established calls
1092 * to configure collision distance and flow control are called. If link is
1093 * not established, we return -E1000_ERR_PHY (-2).
1094 **/
1095 s32 igb_setup_copper_link(struct e1000_hw *hw)
1096 {
1097 s32 ret_val;
1098 bool link;
1099
1100 if (hw->mac.autoneg) {
1101 /* Setup autoneg and flow control advertisement and perform
1102 * autonegotiation.
1103 */
1104 ret_val = igb_copper_link_autoneg(hw);
1105 if (ret_val)
1106 goto out;
1107 } else {
1108 /* PHY will be set to 10H, 10F, 100H or 100F
1109 * depending on user settings.
1110 */
1111 hw_dbg("Forcing Speed and Duplex\n");
1112 ret_val = hw->phy.ops.force_speed_duplex(hw);
1113 if (ret_val) {
1114 hw_dbg("Error Forcing Speed and Duplex\n");
1115 goto out;
1116 }
1117 }
1118
1119 /* Check link status. Wait up to 100 microseconds for link to become
1120 * valid.
1121 */
1122 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1123 if (ret_val)
1124 goto out;
1125
1126 if (link) {
1127 hw_dbg("Valid link established!!!\n");
1128 igb_config_collision_dist(hw);
1129 ret_val = igb_config_fc_after_link_up(hw);
1130 } else {
1131 hw_dbg("Unable to establish link!!!\n");
1132 }
1133
1134 out:
1135 return ret_val;
1136 }
1137
1138 /**
1139 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1140 * @hw: pointer to the HW structure
1141 *
1142 * Calls the PHY setup function to force speed and duplex. Clears the
1143 * auto-crossover to force MDI manually. Waits for link and returns
1144 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1145 **/
1146 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1147 {
1148 struct e1000_phy_info *phy = &hw->phy;
1149 s32 ret_val;
1150 u16 phy_data;
1151 bool link;
1152
1153 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1154 if (ret_val)
1155 goto out;
1156
1157 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1158
1159 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1160 if (ret_val)
1161 goto out;
1162
1163 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1164 * forced whenever speed and duplex are forced.
1165 */
1166 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1167 if (ret_val)
1168 goto out;
1169
1170 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1171 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1172
1173 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1174 if (ret_val)
1175 goto out;
1176
1177 hw_dbg("IGP PSCR: %X\n", phy_data);
1178
1179 udelay(1);
1180
1181 if (phy->autoneg_wait_to_complete) {
1182 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1183
1184 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1185 if (ret_val)
1186 goto out;
1187
1188 if (!link)
1189 hw_dbg("Link taking longer than expected.\n");
1190
1191 /* Try once more */
1192 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1193 if (ret_val)
1194 goto out;
1195 }
1196
1197 out:
1198 return ret_val;
1199 }
1200
1201 /**
1202 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1203 * @hw: pointer to the HW structure
1204 *
1205 * Calls the PHY setup function to force speed and duplex. Clears the
1206 * auto-crossover to force MDI manually. Resets the PHY to commit the
1207 * changes. If time expires while waiting for link up, we reset the DSP.
1208 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1209 * successful completion, else return corresponding error code.
1210 **/
1211 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1212 {
1213 struct e1000_phy_info *phy = &hw->phy;
1214 s32 ret_val;
1215 u16 phy_data;
1216 bool link;
1217
1218 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1219 if (phy->type != e1000_phy_i210) {
1220 /* Clear Auto-Crossover to force MDI manually. M88E1000
1221 * requires MDI forced whenever speed and duplex are forced.
1222 */
1223 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1224 &phy_data);
1225 if (ret_val)
1226 goto out;
1227
1228 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1229 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1230 phy_data);
1231 if (ret_val)
1232 goto out;
1233
1234 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1235 }
1236
1237 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1238 if (ret_val)
1239 goto out;
1240
1241 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1242
1243 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1244 if (ret_val)
1245 goto out;
1246
1247 /* Reset the phy to commit changes. */
1248 ret_val = igb_phy_sw_reset(hw);
1249 if (ret_val)
1250 goto out;
1251
1252 if (phy->autoneg_wait_to_complete) {
1253 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1254
1255 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1256 if (ret_val)
1257 goto out;
1258
1259 if (!link) {
1260 bool reset_dsp = true;
1261
1262 switch (hw->phy.id) {
1263 case I347AT4_E_PHY_ID:
1264 case M88E1112_E_PHY_ID:
1265 case M88E1543_E_PHY_ID:
1266 case M88E1512_E_PHY_ID:
1267 case I210_I_PHY_ID:
1268 reset_dsp = false;
1269 break;
1270 default:
1271 if (hw->phy.type != e1000_phy_m88)
1272 reset_dsp = false;
1273 break;
1274 }
1275 if (!reset_dsp) {
1276 hw_dbg("Link taking longer than expected.\n");
1277 } else {
1278 /* We didn't get link.
1279 * Reset the DSP and cross our fingers.
1280 */
1281 ret_val = phy->ops.write_reg(hw,
1282 M88E1000_PHY_PAGE_SELECT,
1283 0x001d);
1284 if (ret_val)
1285 goto out;
1286 ret_val = igb_phy_reset_dsp(hw);
1287 if (ret_val)
1288 goto out;
1289 }
1290 }
1291
1292 /* Try once more */
1293 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1294 100000, &link);
1295 if (ret_val)
1296 goto out;
1297 }
1298
1299 if (hw->phy.type != e1000_phy_m88 ||
1300 hw->phy.id == I347AT4_E_PHY_ID ||
1301 hw->phy.id == M88E1112_E_PHY_ID ||
1302 hw->phy.id == M88E1543_E_PHY_ID ||
1303 hw->phy.id == M88E1512_E_PHY_ID ||
1304 hw->phy.id == I210_I_PHY_ID)
1305 goto out;
1306
1307 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1308 if (ret_val)
1309 goto out;
1310
1311 /* Resetting the phy means we need to re-force TX_CLK in the
1312 * Extended PHY Specific Control Register to 25MHz clock from
1313 * the reset value of 2.5MHz.
1314 */
1315 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1316 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1317 if (ret_val)
1318 goto out;
1319
1320 /* In addition, we must re-enable CRS on Tx for both half and full
1321 * duplex.
1322 */
1323 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1324 if (ret_val)
1325 goto out;
1326
1327 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1328 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1329
1330 out:
1331 return ret_val;
1332 }
1333
1334 /**
1335 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1336 * @hw: pointer to the HW structure
1337 * @phy_ctrl: pointer to current value of PHY_CONTROL
1338 *
1339 * Forces speed and duplex on the PHY by doing the following: disable flow
1340 * control, force speed/duplex on the MAC, disable auto speed detection,
1341 * disable auto-negotiation, configure duplex, configure speed, configure
1342 * the collision distance, write configuration to CTRL register. The
1343 * caller must write to the PHY_CONTROL register for these settings to
1344 * take affect.
1345 **/
1346 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1347 u16 *phy_ctrl)
1348 {
1349 struct e1000_mac_info *mac = &hw->mac;
1350 u32 ctrl;
1351
1352 /* Turn off flow control when forcing speed/duplex */
1353 hw->fc.current_mode = e1000_fc_none;
1354
1355 /* Force speed/duplex on the mac */
1356 ctrl = rd32(E1000_CTRL);
1357 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1358 ctrl &= ~E1000_CTRL_SPD_SEL;
1359
1360 /* Disable Auto Speed Detection */
1361 ctrl &= ~E1000_CTRL_ASDE;
1362
1363 /* Disable autoneg on the phy */
1364 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1365
1366 /* Forcing Full or Half Duplex? */
1367 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1368 ctrl &= ~E1000_CTRL_FD;
1369 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1370 hw_dbg("Half Duplex\n");
1371 } else {
1372 ctrl |= E1000_CTRL_FD;
1373 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1374 hw_dbg("Full Duplex\n");
1375 }
1376
1377 /* Forcing 10mb or 100mb? */
1378 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1379 ctrl |= E1000_CTRL_SPD_100;
1380 *phy_ctrl |= MII_CR_SPEED_100;
1381 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1382 hw_dbg("Forcing 100mb\n");
1383 } else {
1384 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1385 *phy_ctrl |= MII_CR_SPEED_10;
1386 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1387 hw_dbg("Forcing 10mb\n");
1388 }
1389
1390 igb_config_collision_dist(hw);
1391
1392 wr32(E1000_CTRL, ctrl);
1393 }
1394
1395 /**
1396 * igb_set_d3_lplu_state - Sets low power link up state for D3
1397 * @hw: pointer to the HW structure
1398 * @active: boolean used to enable/disable lplu
1399 *
1400 * Success returns 0, Failure returns 1
1401 *
1402 * The low power link up (lplu) state is set to the power management level D3
1403 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1404 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1405 * is used during Dx states where the power conservation is most important.
1406 * During driver activity, SmartSpeed should be enabled so performance is
1407 * maintained.
1408 **/
1409 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1410 {
1411 struct e1000_phy_info *phy = &hw->phy;
1412 s32 ret_val = 0;
1413 u16 data;
1414
1415 if (!(hw->phy.ops.read_reg))
1416 goto out;
1417
1418 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1419 if (ret_val)
1420 goto out;
1421
1422 if (!active) {
1423 data &= ~IGP02E1000_PM_D3_LPLU;
1424 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1425 data);
1426 if (ret_val)
1427 goto out;
1428 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1429 * during Dx states where the power conservation is most
1430 * important. During driver activity we should enable
1431 * SmartSpeed, so performance is maintained.
1432 */
1433 if (phy->smart_speed == e1000_smart_speed_on) {
1434 ret_val = phy->ops.read_reg(hw,
1435 IGP01E1000_PHY_PORT_CONFIG,
1436 &data);
1437 if (ret_val)
1438 goto out;
1439
1440 data |= IGP01E1000_PSCFR_SMART_SPEED;
1441 ret_val = phy->ops.write_reg(hw,
1442 IGP01E1000_PHY_PORT_CONFIG,
1443 data);
1444 if (ret_val)
1445 goto out;
1446 } else if (phy->smart_speed == e1000_smart_speed_off) {
1447 ret_val = phy->ops.read_reg(hw,
1448 IGP01E1000_PHY_PORT_CONFIG,
1449 &data);
1450 if (ret_val)
1451 goto out;
1452
1453 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1454 ret_val = phy->ops.write_reg(hw,
1455 IGP01E1000_PHY_PORT_CONFIG,
1456 data);
1457 if (ret_val)
1458 goto out;
1459 }
1460 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1461 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1462 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1463 data |= IGP02E1000_PM_D3_LPLU;
1464 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1465 data);
1466 if (ret_val)
1467 goto out;
1468
1469 /* When LPLU is enabled, we should disable SmartSpeed */
1470 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1471 &data);
1472 if (ret_val)
1473 goto out;
1474
1475 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1476 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1477 data);
1478 }
1479
1480 out:
1481 return ret_val;
1482 }
1483
1484 /**
1485 * igb_check_downshift - Checks whether a downshift in speed occurred
1486 * @hw: pointer to the HW structure
1487 *
1488 * Success returns 0, Failure returns 1
1489 *
1490 * A downshift is detected by querying the PHY link health.
1491 **/
1492 s32 igb_check_downshift(struct e1000_hw *hw)
1493 {
1494 struct e1000_phy_info *phy = &hw->phy;
1495 s32 ret_val;
1496 u16 phy_data, offset, mask;
1497
1498 switch (phy->type) {
1499 case e1000_phy_i210:
1500 case e1000_phy_m88:
1501 case e1000_phy_gg82563:
1502 offset = M88E1000_PHY_SPEC_STATUS;
1503 mask = M88E1000_PSSR_DOWNSHIFT;
1504 break;
1505 case e1000_phy_igp_2:
1506 case e1000_phy_igp:
1507 case e1000_phy_igp_3:
1508 offset = IGP01E1000_PHY_LINK_HEALTH;
1509 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1510 break;
1511 default:
1512 /* speed downshift not supported */
1513 phy->speed_downgraded = false;
1514 ret_val = 0;
1515 goto out;
1516 }
1517
1518 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1519
1520 if (!ret_val)
1521 phy->speed_downgraded = (phy_data & mask) ? true : false;
1522
1523 out:
1524 return ret_val;
1525 }
1526
1527 /**
1528 * igb_check_polarity_m88 - Checks the polarity.
1529 * @hw: pointer to the HW structure
1530 *
1531 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1532 *
1533 * Polarity is determined based on the PHY specific status register.
1534 **/
1535 s32 igb_check_polarity_m88(struct e1000_hw *hw)
1536 {
1537 struct e1000_phy_info *phy = &hw->phy;
1538 s32 ret_val;
1539 u16 data;
1540
1541 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1542
1543 if (!ret_val)
1544 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1545 ? e1000_rev_polarity_reversed
1546 : e1000_rev_polarity_normal;
1547
1548 return ret_val;
1549 }
1550
1551 /**
1552 * igb_check_polarity_igp - Checks the polarity.
1553 * @hw: pointer to the HW structure
1554 *
1555 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1556 *
1557 * Polarity is determined based on the PHY port status register, and the
1558 * current speed (since there is no polarity at 100Mbps).
1559 **/
1560 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1561 {
1562 struct e1000_phy_info *phy = &hw->phy;
1563 s32 ret_val;
1564 u16 data, offset, mask;
1565
1566 /* Polarity is determined based on the speed of
1567 * our connection.
1568 */
1569 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1570 if (ret_val)
1571 goto out;
1572
1573 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1574 IGP01E1000_PSSR_SPEED_1000MBPS) {
1575 offset = IGP01E1000_PHY_PCS_INIT_REG;
1576 mask = IGP01E1000_PHY_POLARITY_MASK;
1577 } else {
1578 /* This really only applies to 10Mbps since
1579 * there is no polarity for 100Mbps (always 0).
1580 */
1581 offset = IGP01E1000_PHY_PORT_STATUS;
1582 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1583 }
1584
1585 ret_val = phy->ops.read_reg(hw, offset, &data);
1586
1587 if (!ret_val)
1588 phy->cable_polarity = (data & mask)
1589 ? e1000_rev_polarity_reversed
1590 : e1000_rev_polarity_normal;
1591
1592 out:
1593 return ret_val;
1594 }
1595
1596 /**
1597 * igb_wait_autoneg - Wait for auto-neg completion
1598 * @hw: pointer to the HW structure
1599 *
1600 * Waits for auto-negotiation to complete or for the auto-negotiation time
1601 * limit to expire, which ever happens first.
1602 **/
1603 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1604 {
1605 s32 ret_val = 0;
1606 u16 i, phy_status;
1607
1608 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1609 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1610 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1611 if (ret_val)
1612 break;
1613 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1614 if (ret_val)
1615 break;
1616 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1617 break;
1618 msleep(100);
1619 }
1620
1621 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1622 * has completed.
1623 */
1624 return ret_val;
1625 }
1626
1627 /**
1628 * igb_phy_has_link - Polls PHY for link
1629 * @hw: pointer to the HW structure
1630 * @iterations: number of times to poll for link
1631 * @usec_interval: delay between polling attempts
1632 * @success: pointer to whether polling was successful or not
1633 *
1634 * Polls the PHY status register for link, 'iterations' number of times.
1635 **/
1636 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1637 u32 usec_interval, bool *success)
1638 {
1639 s32 ret_val = 0;
1640 u16 i, phy_status;
1641
1642 for (i = 0; i < iterations; i++) {
1643 /* Some PHYs require the PHY_STATUS register to be read
1644 * twice due to the link bit being sticky. No harm doing
1645 * it across the board.
1646 */
1647 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1648 if (ret_val && usec_interval > 0) {
1649 /* If the first read fails, another entity may have
1650 * ownership of the resources, wait and try again to
1651 * see if they have relinquished the resources yet.
1652 */
1653 if (usec_interval >= 1000)
1654 mdelay(usec_interval/1000);
1655 else
1656 udelay(usec_interval);
1657 }
1658 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1659 if (ret_val)
1660 break;
1661 if (phy_status & MII_SR_LINK_STATUS)
1662 break;
1663 if (usec_interval >= 1000)
1664 mdelay(usec_interval/1000);
1665 else
1666 udelay(usec_interval);
1667 }
1668
1669 *success = (i < iterations) ? true : false;
1670
1671 return ret_val;
1672 }
1673
1674 /**
1675 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1676 * @hw: pointer to the HW structure
1677 *
1678 * Reads the PHY specific status register to retrieve the cable length
1679 * information. The cable length is determined by averaging the minimum and
1680 * maximum values to get the "average" cable length. The m88 PHY has four
1681 * possible cable length values, which are:
1682 * Register Value Cable Length
1683 * 0 < 50 meters
1684 * 1 50 - 80 meters
1685 * 2 80 - 110 meters
1686 * 3 110 - 140 meters
1687 * 4 > 140 meters
1688 **/
1689 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1690 {
1691 struct e1000_phy_info *phy = &hw->phy;
1692 s32 ret_val;
1693 u16 phy_data, index;
1694
1695 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1696 if (ret_val)
1697 goto out;
1698
1699 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1700 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1701 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1702 ret_val = -E1000_ERR_PHY;
1703 goto out;
1704 }
1705
1706 phy->min_cable_length = e1000_m88_cable_length_table[index];
1707 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1708
1709 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1710
1711 out:
1712 return ret_val;
1713 }
1714
1715 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1716 {
1717 struct e1000_phy_info *phy = &hw->phy;
1718 s32 ret_val;
1719 u16 phy_data, phy_data2, index, default_page, is_cm;
1720
1721 switch (hw->phy.id) {
1722 case I210_I_PHY_ID:
1723 /* Get cable length from PHY Cable Diagnostics Control Reg */
1724 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1725 (I347AT4_PCDL + phy->addr),
1726 &phy_data);
1727 if (ret_val)
1728 return ret_val;
1729
1730 /* Check if the unit of cable length is meters or cm */
1731 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1732 I347AT4_PCDC, &phy_data2);
1733 if (ret_val)
1734 return ret_val;
1735
1736 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1737
1738 /* Populate the phy structure with cable length in meters */
1739 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1740 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1741 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1742 break;
1743 case M88E1543_E_PHY_ID:
1744 case M88E1512_E_PHY_ID:
1745 case I347AT4_E_PHY_ID:
1746 /* Remember the original page select and set it to 7 */
1747 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1748 &default_page);
1749 if (ret_val)
1750 goto out;
1751
1752 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1753 if (ret_val)
1754 goto out;
1755
1756 /* Get cable length from PHY Cable Diagnostics Control Reg */
1757 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1758 &phy_data);
1759 if (ret_val)
1760 goto out;
1761
1762 /* Check if the unit of cable length is meters or cm */
1763 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1764 if (ret_val)
1765 goto out;
1766
1767 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1768
1769 /* Populate the phy structure with cable length in meters */
1770 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1771 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1772 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1773
1774 /* Reset the page selec to its original value */
1775 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1776 default_page);
1777 if (ret_val)
1778 goto out;
1779 break;
1780 case M88E1112_E_PHY_ID:
1781 /* Remember the original page select and set it to 5 */
1782 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1783 &default_page);
1784 if (ret_val)
1785 goto out;
1786
1787 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1788 if (ret_val)
1789 goto out;
1790
1791 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1792 &phy_data);
1793 if (ret_val)
1794 goto out;
1795
1796 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1797 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1798 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1799 ret_val = -E1000_ERR_PHY;
1800 goto out;
1801 }
1802
1803 phy->min_cable_length = e1000_m88_cable_length_table[index];
1804 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1805
1806 phy->cable_length = (phy->min_cable_length +
1807 phy->max_cable_length) / 2;
1808
1809 /* Reset the page select to its original value */
1810 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1811 default_page);
1812 if (ret_val)
1813 goto out;
1814
1815 break;
1816 default:
1817 ret_val = -E1000_ERR_PHY;
1818 goto out;
1819 }
1820
1821 out:
1822 return ret_val;
1823 }
1824
1825 /**
1826 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1827 * @hw: pointer to the HW structure
1828 *
1829 * The automatic gain control (agc) normalizes the amplitude of the
1830 * received signal, adjusting for the attenuation produced by the
1831 * cable. By reading the AGC registers, which represent the
1832 * combination of coarse and fine gain value, the value can be put
1833 * into a lookup table to obtain the approximate cable length
1834 * for each channel.
1835 **/
1836 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1837 {
1838 struct e1000_phy_info *phy = &hw->phy;
1839 s32 ret_val = 0;
1840 u16 phy_data, i, agc_value = 0;
1841 u16 cur_agc_index, max_agc_index = 0;
1842 u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1;
1843 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1844 IGP02E1000_PHY_AGC_A,
1845 IGP02E1000_PHY_AGC_B,
1846 IGP02E1000_PHY_AGC_C,
1847 IGP02E1000_PHY_AGC_D
1848 };
1849
1850 /* Read the AGC registers for all channels */
1851 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1852 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1853 if (ret_val)
1854 goto out;
1855
1856 /* Getting bits 15:9, which represent the combination of
1857 * coarse and fine gain values. The result is a number
1858 * that can be put into the lookup table to obtain the
1859 * approximate cable length.
1860 */
1861 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1862 IGP02E1000_AGC_LENGTH_MASK;
1863
1864 /* Array index bound check. */
1865 if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) ||
1866 (cur_agc_index == 0)) {
1867 ret_val = -E1000_ERR_PHY;
1868 goto out;
1869 }
1870
1871 /* Remove min & max AGC values from calculation. */
1872 if (e1000_igp_2_cable_length_table[min_agc_index] >
1873 e1000_igp_2_cable_length_table[cur_agc_index])
1874 min_agc_index = cur_agc_index;
1875 if (e1000_igp_2_cable_length_table[max_agc_index] <
1876 e1000_igp_2_cable_length_table[cur_agc_index])
1877 max_agc_index = cur_agc_index;
1878
1879 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1880 }
1881
1882 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1883 e1000_igp_2_cable_length_table[max_agc_index]);
1884 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1885
1886 /* Calculate cable length with the error range of +/- 10 meters. */
1887 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1888 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1889 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1890
1891 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1892
1893 out:
1894 return ret_val;
1895 }
1896
1897 /**
1898 * igb_get_phy_info_m88 - Retrieve PHY information
1899 * @hw: pointer to the HW structure
1900 *
1901 * Valid for only copper links. Read the PHY status register (sticky read)
1902 * to verify that link is up. Read the PHY special control register to
1903 * determine the polarity and 10base-T extended distance. Read the PHY
1904 * special status register to determine MDI/MDIx and current speed. If
1905 * speed is 1000, then determine cable length, local and remote receiver.
1906 **/
1907 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1908 {
1909 struct e1000_phy_info *phy = &hw->phy;
1910 s32 ret_val;
1911 u16 phy_data;
1912 bool link;
1913
1914 if (phy->media_type != e1000_media_type_copper) {
1915 hw_dbg("Phy info is only valid for copper media\n");
1916 ret_val = -E1000_ERR_CONFIG;
1917 goto out;
1918 }
1919
1920 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1921 if (ret_val)
1922 goto out;
1923
1924 if (!link) {
1925 hw_dbg("Phy info is only valid if link is up\n");
1926 ret_val = -E1000_ERR_CONFIG;
1927 goto out;
1928 }
1929
1930 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1931 if (ret_val)
1932 goto out;
1933
1934 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1935 ? true : false;
1936
1937 ret_val = igb_check_polarity_m88(hw);
1938 if (ret_val)
1939 goto out;
1940
1941 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1942 if (ret_val)
1943 goto out;
1944
1945 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1946
1947 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1948 ret_val = phy->ops.get_cable_length(hw);
1949 if (ret_val)
1950 goto out;
1951
1952 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1953 if (ret_val)
1954 goto out;
1955
1956 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1957 ? e1000_1000t_rx_status_ok
1958 : e1000_1000t_rx_status_not_ok;
1959
1960 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1961 ? e1000_1000t_rx_status_ok
1962 : e1000_1000t_rx_status_not_ok;
1963 } else {
1964 /* Set values to "undefined" */
1965 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1966 phy->local_rx = e1000_1000t_rx_status_undefined;
1967 phy->remote_rx = e1000_1000t_rx_status_undefined;
1968 }
1969
1970 out:
1971 return ret_val;
1972 }
1973
1974 /**
1975 * igb_get_phy_info_igp - Retrieve igp PHY information
1976 * @hw: pointer to the HW structure
1977 *
1978 * Read PHY status to determine if link is up. If link is up, then
1979 * set/determine 10base-T extended distance and polarity correction. Read
1980 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1981 * determine on the cable length, local and remote receiver.
1982 **/
1983 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1984 {
1985 struct e1000_phy_info *phy = &hw->phy;
1986 s32 ret_val;
1987 u16 data;
1988 bool link;
1989
1990 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1991 if (ret_val)
1992 goto out;
1993
1994 if (!link) {
1995 hw_dbg("Phy info is only valid if link is up\n");
1996 ret_val = -E1000_ERR_CONFIG;
1997 goto out;
1998 }
1999
2000 phy->polarity_correction = true;
2001
2002 ret_val = igb_check_polarity_igp(hw);
2003 if (ret_val)
2004 goto out;
2005
2006 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2007 if (ret_val)
2008 goto out;
2009
2010 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2011
2012 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2013 IGP01E1000_PSSR_SPEED_1000MBPS) {
2014 ret_val = phy->ops.get_cable_length(hw);
2015 if (ret_val)
2016 goto out;
2017
2018 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2019 if (ret_val)
2020 goto out;
2021
2022 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2023 ? e1000_1000t_rx_status_ok
2024 : e1000_1000t_rx_status_not_ok;
2025
2026 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2027 ? e1000_1000t_rx_status_ok
2028 : e1000_1000t_rx_status_not_ok;
2029 } else {
2030 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2031 phy->local_rx = e1000_1000t_rx_status_undefined;
2032 phy->remote_rx = e1000_1000t_rx_status_undefined;
2033 }
2034
2035 out:
2036 return ret_val;
2037 }
2038
2039 /**
2040 * igb_phy_sw_reset - PHY software reset
2041 * @hw: pointer to the HW structure
2042 *
2043 * Does a software reset of the PHY by reading the PHY control register and
2044 * setting/write the control register reset bit to the PHY.
2045 **/
2046 s32 igb_phy_sw_reset(struct e1000_hw *hw)
2047 {
2048 s32 ret_val = 0;
2049 u16 phy_ctrl;
2050
2051 if (!(hw->phy.ops.read_reg))
2052 goto out;
2053
2054 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2055 if (ret_val)
2056 goto out;
2057
2058 phy_ctrl |= MII_CR_RESET;
2059 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2060 if (ret_val)
2061 goto out;
2062
2063 udelay(1);
2064
2065 out:
2066 return ret_val;
2067 }
2068
2069 /**
2070 * igb_phy_hw_reset - PHY hardware reset
2071 * @hw: pointer to the HW structure
2072 *
2073 * Verify the reset block is not blocking us from resetting. Acquire
2074 * semaphore (if necessary) and read/set/write the device control reset
2075 * bit in the PHY. Wait the appropriate delay time for the device to
2076 * reset and release the semaphore (if necessary).
2077 **/
2078 s32 igb_phy_hw_reset(struct e1000_hw *hw)
2079 {
2080 struct e1000_phy_info *phy = &hw->phy;
2081 s32 ret_val;
2082 u32 ctrl;
2083
2084 ret_val = igb_check_reset_block(hw);
2085 if (ret_val) {
2086 ret_val = 0;
2087 goto out;
2088 }
2089
2090 ret_val = phy->ops.acquire(hw);
2091 if (ret_val)
2092 goto out;
2093
2094 ctrl = rd32(E1000_CTRL);
2095 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2096 wrfl();
2097
2098 udelay(phy->reset_delay_us);
2099
2100 wr32(E1000_CTRL, ctrl);
2101 wrfl();
2102
2103 udelay(150);
2104
2105 phy->ops.release(hw);
2106
2107 ret_val = phy->ops.get_cfg_done(hw);
2108
2109 out:
2110 return ret_val;
2111 }
2112
2113 /**
2114 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2115 * @hw: pointer to the HW structure
2116 *
2117 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2118 **/
2119 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2120 {
2121 hw_dbg("Running IGP 3 PHY init script\n");
2122
2123 /* PHY init IGP 3 */
2124 /* Enable rise/fall, 10-mode work in class-A */
2125 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2126 /* Remove all caps from Replica path filter */
2127 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2128 /* Bias trimming for ADC, AFE and Driver (Default) */
2129 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2130 /* Increase Hybrid poly bias */
2131 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2132 /* Add 4% to TX amplitude in Giga mode */
2133 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2134 /* Disable trimming (TTT) */
2135 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2136 /* Poly DC correction to 94.6% + 2% for all channels */
2137 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2138 /* ABS DC correction to 95.9% */
2139 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2140 /* BG temp curve trim */
2141 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2142 /* Increasing ADC OPAMP stage 1 currents to max */
2143 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2144 /* Force 1000 ( required for enabling PHY regs configuration) */
2145 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2146 /* Set upd_freq to 6 */
2147 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2148 /* Disable NPDFE */
2149 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2150 /* Disable adaptive fixed FFE (Default) */
2151 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2152 /* Enable FFE hysteresis */
2153 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2154 /* Fixed FFE for short cable lengths */
2155 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2156 /* Fixed FFE for medium cable lengths */
2157 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2158 /* Fixed FFE for long cable lengths */
2159 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2160 /* Enable Adaptive Clip Threshold */
2161 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2162 /* AHT reset limit to 1 */
2163 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2164 /* Set AHT master delay to 127 msec */
2165 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2166 /* Set scan bits for AHT */
2167 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2168 /* Set AHT Preset bits */
2169 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2170 /* Change integ_factor of channel A to 3 */
2171 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2172 /* Change prop_factor of channels BCD to 8 */
2173 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2174 /* Change cg_icount + enable integbp for channels BCD */
2175 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2176 /* Change cg_icount + enable integbp + change prop_factor_master
2177 * to 8 for channel A
2178 */
2179 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2180 /* Disable AHT in Slave mode on channel A */
2181 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2182 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2183 * Enable SPD+B2B
2184 */
2185 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2186 /* Enable restart AN on an1000_dis change */
2187 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2188 /* Enable wh_fifo read clock in 10/100 modes */
2189 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2190 /* Restart AN, Speed selection is 1000 */
2191 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2192
2193 return 0;
2194 }
2195
2196 /**
2197 * igb_initialize_M88E1512_phy - Initialize M88E1512 PHY
2198 * @hw: pointer to the HW structure
2199 *
2200 * Initialize Marvel 1512 to work correctly with Avoton.
2201 **/
2202 s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)
2203 {
2204 struct e1000_phy_info *phy = &hw->phy;
2205 s32 ret_val = 0;
2206
2207 /* Switch to PHY page 0xFF. */
2208 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2209 if (ret_val)
2210 goto out;
2211
2212 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2213 if (ret_val)
2214 goto out;
2215
2216 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2217 if (ret_val)
2218 goto out;
2219
2220 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2221 if (ret_val)
2222 goto out;
2223
2224 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2225 if (ret_val)
2226 goto out;
2227
2228 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2229 if (ret_val)
2230 goto out;
2231
2232 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2233 if (ret_val)
2234 goto out;
2235
2236 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2237 if (ret_val)
2238 goto out;
2239
2240 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2241 if (ret_val)
2242 goto out;
2243
2244 /* Switch to PHY page 0xFB. */
2245 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2246 if (ret_val)
2247 goto out;
2248
2249 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2250 if (ret_val)
2251 goto out;
2252
2253 /* Switch to PHY page 0x12. */
2254 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2255 if (ret_val)
2256 goto out;
2257
2258 /* Change mode to SGMII-to-Copper */
2259 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2260 if (ret_val)
2261 goto out;
2262
2263 /* Return the PHY to page 0. */
2264 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2265 if (ret_val)
2266 goto out;
2267
2268 ret_val = igb_phy_sw_reset(hw);
2269 if (ret_val) {
2270 hw_dbg("Error committing the PHY changes\n");
2271 return ret_val;
2272 }
2273
2274 /* msec_delay(1000); */
2275 usleep_range(1000, 2000);
2276 out:
2277 return ret_val;
2278 }
2279
2280 /**
2281 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2282 * @hw: pointer to the HW structure
2283 *
2284 * In the case of a PHY power down to save power, or to turn off link during a
2285 * driver unload, restore the link to previous settings.
2286 **/
2287 void igb_power_up_phy_copper(struct e1000_hw *hw)
2288 {
2289 u16 mii_reg = 0;
2290
2291 /* The PHY will retain its settings across a power down/up cycle */
2292 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2293 mii_reg &= ~MII_CR_POWER_DOWN;
2294 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2295 }
2296
2297 /**
2298 * igb_power_down_phy_copper - Power down copper PHY
2299 * @hw: pointer to the HW structure
2300 *
2301 * Power down PHY to save power when interface is down and wake on lan
2302 * is not enabled.
2303 **/
2304 void igb_power_down_phy_copper(struct e1000_hw *hw)
2305 {
2306 u16 mii_reg = 0;
2307
2308 /* The PHY will retain its settings across a power down/up cycle */
2309 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2310 mii_reg |= MII_CR_POWER_DOWN;
2311 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2312 usleep_range(1000, 2000);
2313 }
2314
2315 /**
2316 * igb_check_polarity_82580 - Checks the polarity.
2317 * @hw: pointer to the HW structure
2318 *
2319 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2320 *
2321 * Polarity is determined based on the PHY specific status register.
2322 **/
2323 static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2324 {
2325 struct e1000_phy_info *phy = &hw->phy;
2326 s32 ret_val;
2327 u16 data;
2328
2329
2330 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2331
2332 if (!ret_val)
2333 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2334 ? e1000_rev_polarity_reversed
2335 : e1000_rev_polarity_normal;
2336
2337 return ret_val;
2338 }
2339
2340 /**
2341 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2342 * @hw: pointer to the HW structure
2343 *
2344 * Calls the PHY setup function to force speed and duplex. Clears the
2345 * auto-crossover to force MDI manually. Waits for link and returns
2346 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2347 **/
2348 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2349 {
2350 struct e1000_phy_info *phy = &hw->phy;
2351 s32 ret_val;
2352 u16 phy_data;
2353 bool link;
2354
2355 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2356 if (ret_val)
2357 goto out;
2358
2359 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2360
2361 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2362 if (ret_val)
2363 goto out;
2364
2365 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2366 * forced whenever speed and duplex are forced.
2367 */
2368 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2369 if (ret_val)
2370 goto out;
2371
2372 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2373
2374 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2375 if (ret_val)
2376 goto out;
2377
2378 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2379
2380 udelay(1);
2381
2382 if (phy->autoneg_wait_to_complete) {
2383 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2384
2385 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2386 if (ret_val)
2387 goto out;
2388
2389 if (!link)
2390 hw_dbg("Link taking longer than expected.\n");
2391
2392 /* Try once more */
2393 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2394 if (ret_val)
2395 goto out;
2396 }
2397
2398 out:
2399 return ret_val;
2400 }
2401
2402 /**
2403 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2404 * @hw: pointer to the HW structure
2405 *
2406 * Read PHY status to determine if link is up. If link is up, then
2407 * set/determine 10base-T extended distance and polarity correction. Read
2408 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2409 * determine on the cable length, local and remote receiver.
2410 **/
2411 s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2412 {
2413 struct e1000_phy_info *phy = &hw->phy;
2414 s32 ret_val;
2415 u16 data;
2416 bool link;
2417
2418 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2419 if (ret_val)
2420 goto out;
2421
2422 if (!link) {
2423 hw_dbg("Phy info is only valid if link is up\n");
2424 ret_val = -E1000_ERR_CONFIG;
2425 goto out;
2426 }
2427
2428 phy->polarity_correction = true;
2429
2430 ret_val = igb_check_polarity_82580(hw);
2431 if (ret_val)
2432 goto out;
2433
2434 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2435 if (ret_val)
2436 goto out;
2437
2438 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2439
2440 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2441 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2442 ret_val = hw->phy.ops.get_cable_length(hw);
2443 if (ret_val)
2444 goto out;
2445
2446 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2447 if (ret_val)
2448 goto out;
2449
2450 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2451 ? e1000_1000t_rx_status_ok
2452 : e1000_1000t_rx_status_not_ok;
2453
2454 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2455 ? e1000_1000t_rx_status_ok
2456 : e1000_1000t_rx_status_not_ok;
2457 } else {
2458 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2459 phy->local_rx = e1000_1000t_rx_status_undefined;
2460 phy->remote_rx = e1000_1000t_rx_status_undefined;
2461 }
2462
2463 out:
2464 return ret_val;
2465 }
2466
2467 /**
2468 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2469 * @hw: pointer to the HW structure
2470 *
2471 * Reads the diagnostic status register and verifies result is valid before
2472 * placing it in the phy_cable_length field.
2473 **/
2474 s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2475 {
2476 struct e1000_phy_info *phy = &hw->phy;
2477 s32 ret_val;
2478 u16 phy_data, length;
2479
2480 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2481 if (ret_val)
2482 goto out;
2483
2484 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2485 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2486
2487 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2488 ret_val = -E1000_ERR_PHY;
2489
2490 phy->cable_length = length;
2491
2492 out:
2493 return ret_val;
2494 }
2495
2496 /**
2497 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2498 * @hw: pointer to the HW structure
2499 * @offset: lower half is register offset to write to
2500 * upper half is page to use.
2501 * @data: data to write at register offset
2502 *
2503 * Acquires semaphore, if necessary, then writes the data to PHY register
2504 * at the offset. Release any acquired semaphores before exiting.
2505 **/
2506 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2507 {
2508 s32 ret_val;
2509 u16 page = offset >> GS40G_PAGE_SHIFT;
2510
2511 offset = offset & GS40G_OFFSET_MASK;
2512 ret_val = hw->phy.ops.acquire(hw);
2513 if (ret_val)
2514 return ret_val;
2515
2516 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2517 if (ret_val)
2518 goto release;
2519 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2520
2521 release:
2522 hw->phy.ops.release(hw);
2523 return ret_val;
2524 }
2525
2526 /**
2527 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2528 * @hw: pointer to the HW structure
2529 * @offset: lower half is register offset to read to
2530 * upper half is page to use.
2531 * @data: data to read at register offset
2532 *
2533 * Acquires semaphore, if necessary, then reads the data in the PHY register
2534 * at the offset. Release any acquired semaphores before exiting.
2535 **/
2536 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2537 {
2538 s32 ret_val;
2539 u16 page = offset >> GS40G_PAGE_SHIFT;
2540
2541 offset = offset & GS40G_OFFSET_MASK;
2542 ret_val = hw->phy.ops.acquire(hw);
2543 if (ret_val)
2544 return ret_val;
2545
2546 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2547 if (ret_val)
2548 goto release;
2549 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2550
2551 release:
2552 hw->phy.ops.release(hw);
2553 return ret_val;
2554 }
2555
2556 /**
2557 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2558 * @hw: pointer to the HW structure
2559 *
2560 * Sets up Master/slave mode
2561 **/
2562 static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2563 {
2564 s32 ret_val;
2565 u16 phy_data;
2566
2567 /* Resolve Master/Slave mode */
2568 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2569 if (ret_val)
2570 return ret_val;
2571
2572 /* load defaults for future use */
2573 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2574 ((phy_data & CR_1000T_MS_VALUE) ?
2575 e1000_ms_force_master :
2576 e1000_ms_force_slave) : e1000_ms_auto;
2577
2578 switch (hw->phy.ms_type) {
2579 case e1000_ms_force_master:
2580 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2581 break;
2582 case e1000_ms_force_slave:
2583 phy_data |= CR_1000T_MS_ENABLE;
2584 phy_data &= ~(CR_1000T_MS_VALUE);
2585 break;
2586 case e1000_ms_auto:
2587 phy_data &= ~CR_1000T_MS_ENABLE;
2588 /* fall-through */
2589 default:
2590 break;
2591 }
2592
2593 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2594 }
Linux kernel - Deliverables
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