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[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_phy.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
30
31 #include "e1000_mac.h"
32 #include "e1000_phy.h"
33
34 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
35 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
36 u16 *phy_ctrl);
37 static s32 igb_wait_autoneg(struct e1000_hw *hw);
38 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
39
40 /* Cable length tables */
41 static const u16 e1000_m88_cable_length_table[] = {
42 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
44 (sizeof(e1000_m88_cable_length_table) / \
45 sizeof(e1000_m88_cable_length_table[0]))
46
47 static const u16 e1000_igp_2_cable_length_table[] = {
48 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
55 104, 109, 114, 118, 121, 124};
56 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
57 (sizeof(e1000_igp_2_cable_length_table) / \
58 sizeof(e1000_igp_2_cable_length_table[0]))
59
60 /**
61 * igb_check_reset_block - Check if PHY reset is blocked
62 * @hw: pointer to the HW structure
63 *
64 * Read the PHY management control register and check whether a PHY reset
65 * is blocked. If a reset is not blocked return 0, otherwise
66 * return E1000_BLK_PHY_RESET (12).
67 **/
68 s32 igb_check_reset_block(struct e1000_hw *hw)
69 {
70 u32 manc;
71
72 manc = rd32(E1000_MANC);
73
74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
75 }
76
77 /**
78 * igb_get_phy_id - Retrieve the PHY ID and revision
79 * @hw: pointer to the HW structure
80 *
81 * Reads the PHY registers and stores the PHY ID and possibly the PHY
82 * revision in the hardware structure.
83 **/
84 s32 igb_get_phy_id(struct e1000_hw *hw)
85 {
86 struct e1000_phy_info *phy = &hw->phy;
87 s32 ret_val = 0;
88 u16 phy_id;
89
90 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
91 if (ret_val)
92 goto out;
93
94 phy->id = (u32)(phy_id << 16);
95 udelay(20);
96 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
97 if (ret_val)
98 goto out;
99
100 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
101 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
102
103 out:
104 return ret_val;
105 }
106
107 /**
108 * igb_phy_reset_dsp - Reset PHY DSP
109 * @hw: pointer to the HW structure
110 *
111 * Reset the digital signal processor.
112 **/
113 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
114 {
115 s32 ret_val = 0;
116
117 if (!(hw->phy.ops.write_reg))
118 goto out;
119
120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
121 if (ret_val)
122 goto out;
123
124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
125
126 out:
127 return ret_val;
128 }
129
130 /**
131 * igb_read_phy_reg_mdic - Read MDI control register
132 * @hw: pointer to the HW structure
133 * @offset: register offset to be read
134 * @data: pointer to the read data
135 *
136 * Reads the MDI control regsiter in the PHY at offset and stores the
137 * information read to data.
138 **/
139 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
140 {
141 struct e1000_phy_info *phy = &hw->phy;
142 u32 i, mdic = 0;
143 s32 ret_val = 0;
144
145 if (offset > MAX_PHY_REG_ADDRESS) {
146 hw_dbg("PHY Address %d is out of range\n", offset);
147 ret_val = -E1000_ERR_PARAM;
148 goto out;
149 }
150
151 /* Set up Op-code, Phy Address, and register offset in the MDI
152 * Control register. The MAC will take care of interfacing with the
153 * PHY to retrieve the desired data.
154 */
155 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
156 (phy->addr << E1000_MDIC_PHY_SHIFT) |
157 (E1000_MDIC_OP_READ));
158
159 wr32(E1000_MDIC, mdic);
160
161 /* Poll the ready bit to see if the MDI read completed
162 * Increasing the time out as testing showed failures with
163 * the lower time out
164 */
165 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
166 udelay(50);
167 mdic = rd32(E1000_MDIC);
168 if (mdic & E1000_MDIC_READY)
169 break;
170 }
171 if (!(mdic & E1000_MDIC_READY)) {
172 hw_dbg("MDI Read did not complete\n");
173 ret_val = -E1000_ERR_PHY;
174 goto out;
175 }
176 if (mdic & E1000_MDIC_ERROR) {
177 hw_dbg("MDI Error\n");
178 ret_val = -E1000_ERR_PHY;
179 goto out;
180 }
181 *data = (u16) mdic;
182
183 out:
184 return ret_val;
185 }
186
187 /**
188 * igb_write_phy_reg_mdic - Write MDI control register
189 * @hw: pointer to the HW structure
190 * @offset: register offset to write to
191 * @data: data to write to register at offset
192 *
193 * Writes data to MDI control register in the PHY at offset.
194 **/
195 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
196 {
197 struct e1000_phy_info *phy = &hw->phy;
198 u32 i, mdic = 0;
199 s32 ret_val = 0;
200
201 if (offset > MAX_PHY_REG_ADDRESS) {
202 hw_dbg("PHY Address %d is out of range\n", offset);
203 ret_val = -E1000_ERR_PARAM;
204 goto out;
205 }
206
207 /* Set up Op-code, Phy Address, and register offset in the MDI
208 * Control register. The MAC will take care of interfacing with the
209 * PHY to retrieve the desired data.
210 */
211 mdic = (((u32)data) |
212 (offset << E1000_MDIC_REG_SHIFT) |
213 (phy->addr << E1000_MDIC_PHY_SHIFT) |
214 (E1000_MDIC_OP_WRITE));
215
216 wr32(E1000_MDIC, mdic);
217
218 /* Poll the ready bit to see if the MDI read completed
219 * Increasing the time out as testing showed failures with
220 * the lower time out
221 */
222 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
223 udelay(50);
224 mdic = rd32(E1000_MDIC);
225 if (mdic & E1000_MDIC_READY)
226 break;
227 }
228 if (!(mdic & E1000_MDIC_READY)) {
229 hw_dbg("MDI Write did not complete\n");
230 ret_val = -E1000_ERR_PHY;
231 goto out;
232 }
233 if (mdic & E1000_MDIC_ERROR) {
234 hw_dbg("MDI Error\n");
235 ret_val = -E1000_ERR_PHY;
236 goto out;
237 }
238
239 out:
240 return ret_val;
241 }
242
243 /**
244 * igb_read_phy_reg_i2c - Read PHY register using i2c
245 * @hw: pointer to the HW structure
246 * @offset: register offset to be read
247 * @data: pointer to the read data
248 *
249 * Reads the PHY register at offset using the i2c interface and stores the
250 * retrieved information in data.
251 **/
252 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
253 {
254 struct e1000_phy_info *phy = &hw->phy;
255 u32 i, i2ccmd = 0;
256
257 /* Set up Op-code, Phy Address, and register address in the I2CCMD
258 * register. The MAC will take care of interfacing with the
259 * PHY to retrieve the desired data.
260 */
261 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
262 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
263 (E1000_I2CCMD_OPCODE_READ));
264
265 wr32(E1000_I2CCMD, i2ccmd);
266
267 /* Poll the ready bit to see if the I2C read completed */
268 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
269 udelay(50);
270 i2ccmd = rd32(E1000_I2CCMD);
271 if (i2ccmd & E1000_I2CCMD_READY)
272 break;
273 }
274 if (!(i2ccmd & E1000_I2CCMD_READY)) {
275 hw_dbg("I2CCMD Read did not complete\n");
276 return -E1000_ERR_PHY;
277 }
278 if (i2ccmd & E1000_I2CCMD_ERROR) {
279 hw_dbg("I2CCMD Error bit set\n");
280 return -E1000_ERR_PHY;
281 }
282
283 /* Need to byte-swap the 16-bit value. */
284 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
285
286 return 0;
287 }
288
289 /**
290 * igb_write_phy_reg_i2c - Write PHY register using i2c
291 * @hw: pointer to the HW structure
292 * @offset: register offset to write to
293 * @data: data to write at register offset
294 *
295 * Writes the data to PHY register at the offset using the i2c interface.
296 **/
297 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
298 {
299 struct e1000_phy_info *phy = &hw->phy;
300 u32 i, i2ccmd = 0;
301 u16 phy_data_swapped;
302
303 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
304 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
305 hw_dbg("PHY I2C Address %d is out of range.\n",
306 hw->phy.addr);
307 return -E1000_ERR_CONFIG;
308 }
309
310 /* Swap the data bytes for the I2C interface */
311 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
312
313 /* Set up Op-code, Phy Address, and register address in the I2CCMD
314 * register. The MAC will take care of interfacing with the
315 * PHY to retrieve the desired data.
316 */
317 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
318 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
319 E1000_I2CCMD_OPCODE_WRITE |
320 phy_data_swapped);
321
322 wr32(E1000_I2CCMD, i2ccmd);
323
324 /* Poll the ready bit to see if the I2C read completed */
325 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
326 udelay(50);
327 i2ccmd = rd32(E1000_I2CCMD);
328 if (i2ccmd & E1000_I2CCMD_READY)
329 break;
330 }
331 if (!(i2ccmd & E1000_I2CCMD_READY)) {
332 hw_dbg("I2CCMD Write did not complete\n");
333 return -E1000_ERR_PHY;
334 }
335 if (i2ccmd & E1000_I2CCMD_ERROR) {
336 hw_dbg("I2CCMD Error bit set\n");
337 return -E1000_ERR_PHY;
338 }
339
340 return 0;
341 }
342
343 /**
344 * igb_read_sfp_data_byte - Reads SFP module data.
345 * @hw: pointer to the HW structure
346 * @offset: byte location offset to be read
347 * @data: read data buffer pointer
348 *
349 * Reads one byte from SFP module data stored
350 * in SFP resided EEPROM memory or SFP diagnostic area.
351 * Function should be called with
352 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
353 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
354 * access
355 **/
356 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
357 {
358 u32 i = 0;
359 u32 i2ccmd = 0;
360 u32 data_local = 0;
361
362 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
363 hw_dbg("I2CCMD command address exceeds upper limit\n");
364 return -E1000_ERR_PHY;
365 }
366
367 /* Set up Op-code, EEPROM Address,in the I2CCMD
368 * register. The MAC will take care of interfacing with the
369 * EEPROM to retrieve the desired data.
370 */
371 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
372 E1000_I2CCMD_OPCODE_READ);
373
374 wr32(E1000_I2CCMD, i2ccmd);
375
376 /* Poll the ready bit to see if the I2C read completed */
377 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
378 udelay(50);
379 data_local = rd32(E1000_I2CCMD);
380 if (data_local & E1000_I2CCMD_READY)
381 break;
382 }
383 if (!(data_local & E1000_I2CCMD_READY)) {
384 hw_dbg("I2CCMD Read did not complete\n");
385 return -E1000_ERR_PHY;
386 }
387 if (data_local & E1000_I2CCMD_ERROR) {
388 hw_dbg("I2CCMD Error bit set\n");
389 return -E1000_ERR_PHY;
390 }
391 *data = (u8) data_local & 0xFF;
392
393 return 0;
394 }
395
396 /**
397 * e1000_write_sfp_data_byte - Writes SFP module data.
398 * @hw: pointer to the HW structure
399 * @offset: byte location offset to write to
400 * @data: data to write
401 *
402 * Writes one byte to SFP module data stored
403 * in SFP resided EEPROM memory or SFP diagnostic area.
404 * Function should be called with
405 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
406 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
407 * access
408 **/
409 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
410 {
411 u32 i = 0;
412 u32 i2ccmd = 0;
413 u32 data_local = 0;
414
415 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
416 hw_dbg("I2CCMD command address exceeds upper limit\n");
417 return -E1000_ERR_PHY;
418 }
419 /* The programming interface is 16 bits wide
420 * so we need to read the whole word first
421 * then update appropriate byte lane and write
422 * the updated word back.
423 */
424 /* Set up Op-code, EEPROM Address,in the I2CCMD
425 * register. The MAC will take care of interfacing
426 * with an EEPROM to write the data given.
427 */
428 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
429 E1000_I2CCMD_OPCODE_READ);
430 /* Set a command to read single word */
431 wr32(E1000_I2CCMD, i2ccmd);
432 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
433 udelay(50);
434 /* Poll the ready bit to see if lastly
435 * launched I2C operation completed
436 */
437 i2ccmd = rd32(E1000_I2CCMD);
438 if (i2ccmd & E1000_I2CCMD_READY) {
439 /* Check if this is READ or WRITE phase */
440 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
441 E1000_I2CCMD_OPCODE_READ) {
442 /* Write the selected byte
443 * lane and update whole word
444 */
445 data_local = i2ccmd & 0xFF00;
446 data_local |= data;
447 i2ccmd = ((offset <<
448 E1000_I2CCMD_REG_ADDR_SHIFT) |
449 E1000_I2CCMD_OPCODE_WRITE | data_local);
450 wr32(E1000_I2CCMD, i2ccmd);
451 } else {
452 break;
453 }
454 }
455 }
456 if (!(i2ccmd & E1000_I2CCMD_READY)) {
457 hw_dbg("I2CCMD Write did not complete\n");
458 return -E1000_ERR_PHY;
459 }
460 if (i2ccmd & E1000_I2CCMD_ERROR) {
461 hw_dbg("I2CCMD Error bit set\n");
462 return -E1000_ERR_PHY;
463 }
464 return 0;
465 }
466
467 /**
468 * igb_read_phy_reg_igp - Read igp PHY register
469 * @hw: pointer to the HW structure
470 * @offset: register offset to be read
471 * @data: pointer to the read data
472 *
473 * Acquires semaphore, if necessary, then reads the PHY register at offset
474 * and storing the retrieved information in data. Release any acquired
475 * semaphores before exiting.
476 **/
477 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
478 {
479 s32 ret_val = 0;
480
481 if (!(hw->phy.ops.acquire))
482 goto out;
483
484 ret_val = hw->phy.ops.acquire(hw);
485 if (ret_val)
486 goto out;
487
488 if (offset > MAX_PHY_MULTI_PAGE_REG) {
489 ret_val = igb_write_phy_reg_mdic(hw,
490 IGP01E1000_PHY_PAGE_SELECT,
491 (u16)offset);
492 if (ret_val) {
493 hw->phy.ops.release(hw);
494 goto out;
495 }
496 }
497
498 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
499 data);
500
501 hw->phy.ops.release(hw);
502
503 out:
504 return ret_val;
505 }
506
507 /**
508 * igb_write_phy_reg_igp - Write igp PHY register
509 * @hw: pointer to the HW structure
510 * @offset: register offset to write to
511 * @data: data to write at register offset
512 *
513 * Acquires semaphore, if necessary, then writes the data to PHY register
514 * at the offset. Release any acquired semaphores before exiting.
515 **/
516 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
517 {
518 s32 ret_val = 0;
519
520 if (!(hw->phy.ops.acquire))
521 goto out;
522
523 ret_val = hw->phy.ops.acquire(hw);
524 if (ret_val)
525 goto out;
526
527 if (offset > MAX_PHY_MULTI_PAGE_REG) {
528 ret_val = igb_write_phy_reg_mdic(hw,
529 IGP01E1000_PHY_PAGE_SELECT,
530 (u16)offset);
531 if (ret_val) {
532 hw->phy.ops.release(hw);
533 goto out;
534 }
535 }
536
537 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
538 data);
539
540 hw->phy.ops.release(hw);
541
542 out:
543 return ret_val;
544 }
545
546 /**
547 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
548 * @hw: pointer to the HW structure
549 *
550 * Sets up Carrier-sense on Transmit and downshift values.
551 **/
552 s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
553 {
554 struct e1000_phy_info *phy = &hw->phy;
555 s32 ret_val;
556 u16 phy_data;
557
558 if (phy->reset_disable) {
559 ret_val = 0;
560 goto out;
561 }
562
563 if (phy->type == e1000_phy_82580) {
564 ret_val = hw->phy.ops.reset(hw);
565 if (ret_val) {
566 hw_dbg("Error resetting the PHY.\n");
567 goto out;
568 }
569 }
570
571 /* Enable CRS on TX. This must be set for half-duplex operation. */
572 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
573 if (ret_val)
574 goto out;
575
576 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
577
578 /* Enable downshift */
579 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
580
581 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
582 if (ret_val)
583 goto out;
584
585 /* Set MDI/MDIX mode */
586 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
587 if (ret_val)
588 goto out;
589 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
590 /* Options:
591 * 0 - Auto (default)
592 * 1 - MDI mode
593 * 2 - MDI-X mode
594 */
595 switch (hw->phy.mdix) {
596 case 1:
597 break;
598 case 2:
599 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
600 break;
601 case 0:
602 default:
603 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
604 break;
605 }
606 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
607
608 out:
609 return ret_val;
610 }
611
612 /**
613 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
614 * @hw: pointer to the HW structure
615 *
616 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
617 * and downshift values are set also.
618 **/
619 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
620 {
621 struct e1000_phy_info *phy = &hw->phy;
622 s32 ret_val;
623 u16 phy_data;
624
625 if (phy->reset_disable) {
626 ret_val = 0;
627 goto out;
628 }
629
630 /* Enable CRS on TX. This must be set for half-duplex operation. */
631 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
632 if (ret_val)
633 goto out;
634
635 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
636
637 /* Options:
638 * MDI/MDI-X = 0 (default)
639 * 0 - Auto for all speeds
640 * 1 - MDI mode
641 * 2 - MDI-X mode
642 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
643 */
644 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
645
646 switch (phy->mdix) {
647 case 1:
648 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
649 break;
650 case 2:
651 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
652 break;
653 case 3:
654 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
655 break;
656 case 0:
657 default:
658 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
659 break;
660 }
661
662 /* Options:
663 * disable_polarity_correction = 0 (default)
664 * Automatic Correction for Reversed Cable Polarity
665 * 0 - Disabled
666 * 1 - Enabled
667 */
668 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
669 if (phy->disable_polarity_correction == 1)
670 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
671
672 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
673 if (ret_val)
674 goto out;
675
676 if (phy->revision < E1000_REVISION_4) {
677 /* Force TX_CLK in the Extended PHY Specific Control Register
678 * to 25MHz clock.
679 */
680 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
681 &phy_data);
682 if (ret_val)
683 goto out;
684
685 phy_data |= M88E1000_EPSCR_TX_CLK_25;
686
687 if ((phy->revision == E1000_REVISION_2) &&
688 (phy->id == M88E1111_I_PHY_ID)) {
689 /* 82573L PHY - set the downshift counter to 5x. */
690 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
691 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
692 } else {
693 /* Configure Master and Slave downshift values */
694 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
695 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
696 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
697 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
698 }
699 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
700 phy_data);
701 if (ret_val)
702 goto out;
703 }
704
705 /* Commit the changes. */
706 ret_val = igb_phy_sw_reset(hw);
707 if (ret_val) {
708 hw_dbg("Error committing the PHY changes\n");
709 goto out;
710 }
711
712 out:
713 return ret_val;
714 }
715
716 /**
717 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
718 * @hw: pointer to the HW structure
719 *
720 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
721 * Also enables and sets the downshift parameters.
722 **/
723 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
724 {
725 struct e1000_phy_info *phy = &hw->phy;
726 s32 ret_val;
727 u16 phy_data;
728
729 if (phy->reset_disable)
730 return 0;
731
732 /* Enable CRS on Tx. This must be set for half-duplex operation. */
733 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
734 if (ret_val)
735 return ret_val;
736
737 /* Options:
738 * MDI/MDI-X = 0 (default)
739 * 0 - Auto for all speeds
740 * 1 - MDI mode
741 * 2 - MDI-X mode
742 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
743 */
744 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
745
746 switch (phy->mdix) {
747 case 1:
748 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
749 break;
750 case 2:
751 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
752 break;
753 case 3:
754 /* M88E1112 does not support this mode) */
755 if (phy->id != M88E1112_E_PHY_ID) {
756 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
757 break;
758 }
759 case 0:
760 default:
761 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
762 break;
763 }
764
765 /* Options:
766 * disable_polarity_correction = 0 (default)
767 * Automatic Correction for Reversed Cable Polarity
768 * 0 - Disabled
769 * 1 - Enabled
770 */
771 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
772 if (phy->disable_polarity_correction == 1)
773 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
774
775 /* Enable downshift and setting it to X6 */
776 if (phy->id == M88E1543_E_PHY_ID) {
777 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
778 ret_val =
779 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
780 if (ret_val)
781 return ret_val;
782
783 ret_val = igb_phy_sw_reset(hw);
784 if (ret_val) {
785 hw_dbg("Error committing the PHY changes\n");
786 return ret_val;
787 }
788 }
789
790 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
791 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
792 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
793
794 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
795 if (ret_val)
796 return ret_val;
797
798 /* Commit the changes. */
799 ret_val = igb_phy_sw_reset(hw);
800 if (ret_val) {
801 hw_dbg("Error committing the PHY changes\n");
802 return ret_val;
803 }
804 ret_val = igb_set_master_slave_mode(hw);
805 if (ret_val)
806 return ret_val;
807
808 return 0;
809 }
810
811 /**
812 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
813 * @hw: pointer to the HW structure
814 *
815 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
816 * igp PHY's.
817 **/
818 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
819 {
820 struct e1000_phy_info *phy = &hw->phy;
821 s32 ret_val;
822 u16 data;
823
824 if (phy->reset_disable) {
825 ret_val = 0;
826 goto out;
827 }
828
829 ret_val = phy->ops.reset(hw);
830 if (ret_val) {
831 hw_dbg("Error resetting the PHY.\n");
832 goto out;
833 }
834
835 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
836 * timeout issues when LFS is enabled.
837 */
838 msleep(100);
839
840 /* The NVM settings will configure LPLU in D3 for
841 * non-IGP1 PHYs.
842 */
843 if (phy->type == e1000_phy_igp) {
844 /* disable lplu d3 during driver init */
845 if (phy->ops.set_d3_lplu_state)
846 ret_val = phy->ops.set_d3_lplu_state(hw, false);
847 if (ret_val) {
848 hw_dbg("Error Disabling LPLU D3\n");
849 goto out;
850 }
851 }
852
853 /* disable lplu d0 during driver init */
854 ret_val = phy->ops.set_d0_lplu_state(hw, false);
855 if (ret_val) {
856 hw_dbg("Error Disabling LPLU D0\n");
857 goto out;
858 }
859 /* Configure mdi-mdix settings */
860 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
861 if (ret_val)
862 goto out;
863
864 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
865
866 switch (phy->mdix) {
867 case 1:
868 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
869 break;
870 case 2:
871 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
872 break;
873 case 0:
874 default:
875 data |= IGP01E1000_PSCR_AUTO_MDIX;
876 break;
877 }
878 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
879 if (ret_val)
880 goto out;
881
882 /* set auto-master slave resolution settings */
883 if (hw->mac.autoneg) {
884 /* when autonegotiation advertisement is only 1000Mbps then we
885 * should disable SmartSpeed and enable Auto MasterSlave
886 * resolution as hardware default.
887 */
888 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
889 /* Disable SmartSpeed */
890 ret_val = phy->ops.read_reg(hw,
891 IGP01E1000_PHY_PORT_CONFIG,
892 &data);
893 if (ret_val)
894 goto out;
895
896 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
897 ret_val = phy->ops.write_reg(hw,
898 IGP01E1000_PHY_PORT_CONFIG,
899 data);
900 if (ret_val)
901 goto out;
902
903 /* Set auto Master/Slave resolution process */
904 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
905 if (ret_val)
906 goto out;
907
908 data &= ~CR_1000T_MS_ENABLE;
909 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
910 if (ret_val)
911 goto out;
912 }
913
914 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
915 if (ret_val)
916 goto out;
917
918 /* load defaults for future use */
919 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
920 ((data & CR_1000T_MS_VALUE) ?
921 e1000_ms_force_master :
922 e1000_ms_force_slave) :
923 e1000_ms_auto;
924
925 switch (phy->ms_type) {
926 case e1000_ms_force_master:
927 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
928 break;
929 case e1000_ms_force_slave:
930 data |= CR_1000T_MS_ENABLE;
931 data &= ~(CR_1000T_MS_VALUE);
932 break;
933 case e1000_ms_auto:
934 data &= ~CR_1000T_MS_ENABLE;
935 default:
936 break;
937 }
938 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
939 if (ret_val)
940 goto out;
941 }
942
943 out:
944 return ret_val;
945 }
946
947 /**
948 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
949 * @hw: pointer to the HW structure
950 *
951 * Performs initial bounds checking on autoneg advertisement parameter, then
952 * configure to advertise the full capability. Setup the PHY to autoneg
953 * and restart the negotiation process between the link partner. If
954 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
955 **/
956 static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
957 {
958 struct e1000_phy_info *phy = &hw->phy;
959 s32 ret_val;
960 u16 phy_ctrl;
961
962 /* Perform some bounds checking on the autoneg advertisement
963 * parameter.
964 */
965 phy->autoneg_advertised &= phy->autoneg_mask;
966
967 /* If autoneg_advertised is zero, we assume it was not defaulted
968 * by the calling code so we set to advertise full capability.
969 */
970 if (phy->autoneg_advertised == 0)
971 phy->autoneg_advertised = phy->autoneg_mask;
972
973 hw_dbg("Reconfiguring auto-neg advertisement params\n");
974 ret_val = igb_phy_setup_autoneg(hw);
975 if (ret_val) {
976 hw_dbg("Error Setting up Auto-Negotiation\n");
977 goto out;
978 }
979 hw_dbg("Restarting Auto-Neg\n");
980
981 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
982 * the Auto Neg Restart bit in the PHY control register.
983 */
984 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
985 if (ret_val)
986 goto out;
987
988 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
989 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
990 if (ret_val)
991 goto out;
992
993 /* Does the user want to wait for Auto-Neg to complete here, or
994 * check at a later time (for example, callback routine).
995 */
996 if (phy->autoneg_wait_to_complete) {
997 ret_val = igb_wait_autoneg(hw);
998 if (ret_val) {
999 hw_dbg("Error while waiting for "
1000 "autoneg to complete\n");
1001 goto out;
1002 }
1003 }
1004
1005 hw->mac.get_link_status = true;
1006
1007 out:
1008 return ret_val;
1009 }
1010
1011 /**
1012 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
1013 * @hw: pointer to the HW structure
1014 *
1015 * Reads the MII auto-neg advertisement register and/or the 1000T control
1016 * register and if the PHY is already setup for auto-negotiation, then
1017 * return successful. Otherwise, setup advertisement and flow control to
1018 * the appropriate values for the wanted auto-negotiation.
1019 **/
1020 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
1021 {
1022 struct e1000_phy_info *phy = &hw->phy;
1023 s32 ret_val;
1024 u16 mii_autoneg_adv_reg;
1025 u16 mii_1000t_ctrl_reg = 0;
1026
1027 phy->autoneg_advertised &= phy->autoneg_mask;
1028
1029 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1030 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1031 if (ret_val)
1032 goto out;
1033
1034 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1035 /* Read the MII 1000Base-T Control Register (Address 9). */
1036 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1037 &mii_1000t_ctrl_reg);
1038 if (ret_val)
1039 goto out;
1040 }
1041
1042 /* Need to parse both autoneg_advertised and fc and set up
1043 * the appropriate PHY registers. First we will parse for
1044 * autoneg_advertised software override. Since we can advertise
1045 * a plethora of combinations, we need to check each bit
1046 * individually.
1047 */
1048
1049 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1050 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1051 * the 1000Base-T Control Register (Address 9).
1052 */
1053 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1054 NWAY_AR_100TX_HD_CAPS |
1055 NWAY_AR_10T_FD_CAPS |
1056 NWAY_AR_10T_HD_CAPS);
1057 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1058
1059 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
1060
1061 /* Do we want to advertise 10 Mb Half Duplex? */
1062 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1063 hw_dbg("Advertise 10mb Half duplex\n");
1064 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1065 }
1066
1067 /* Do we want to advertise 10 Mb Full Duplex? */
1068 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1069 hw_dbg("Advertise 10mb Full duplex\n");
1070 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1071 }
1072
1073 /* Do we want to advertise 100 Mb Half Duplex? */
1074 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1075 hw_dbg("Advertise 100mb Half duplex\n");
1076 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1077 }
1078
1079 /* Do we want to advertise 100 Mb Full Duplex? */
1080 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1081 hw_dbg("Advertise 100mb Full duplex\n");
1082 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1083 }
1084
1085 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1086 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1087 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1088
1089 /* Do we want to advertise 1000 Mb Full Duplex? */
1090 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1091 hw_dbg("Advertise 1000mb Full duplex\n");
1092 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1093 }
1094
1095 /* Check for a software override of the flow control settings, and
1096 * setup the PHY advertisement registers accordingly. If
1097 * auto-negotiation is enabled, then software will have to set the
1098 * "PAUSE" bits to the correct value in the Auto-Negotiation
1099 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1100 * negotiation.
1101 *
1102 * The possible values of the "fc" parameter are:
1103 * 0: Flow control is completely disabled
1104 * 1: Rx flow control is enabled (we can receive pause frames
1105 * but not send pause frames).
1106 * 2: Tx flow control is enabled (we can send pause frames
1107 * but we do not support receiving pause frames).
1108 * 3: Both Rx and TX flow control (symmetric) are enabled.
1109 * other: No software override. The flow control configuration
1110 * in the EEPROM is used.
1111 */
1112 switch (hw->fc.current_mode) {
1113 case e1000_fc_none:
1114 /* Flow control (RX & TX) is completely disabled by a
1115 * software over-ride.
1116 */
1117 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1118 break;
1119 case e1000_fc_rx_pause:
1120 /* RX Flow control is enabled, and TX Flow control is
1121 * disabled, by a software over-ride.
1122 *
1123 * Since there really isn't a way to advertise that we are
1124 * capable of RX Pause ONLY, we will advertise that we
1125 * support both symmetric and asymmetric RX PAUSE. Later
1126 * (in e1000_config_fc_after_link_up) we will disable the
1127 * hw's ability to send PAUSE frames.
1128 */
1129 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1130 break;
1131 case e1000_fc_tx_pause:
1132 /* TX Flow control is enabled, and RX Flow control is
1133 * disabled, by a software over-ride.
1134 */
1135 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1136 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1137 break;
1138 case e1000_fc_full:
1139 /* Flow control (both RX and TX) is enabled by a software
1140 * over-ride.
1141 */
1142 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1143 break;
1144 default:
1145 hw_dbg("Flow control param set incorrectly\n");
1146 ret_val = -E1000_ERR_CONFIG;
1147 goto out;
1148 }
1149
1150 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1151 if (ret_val)
1152 goto out;
1153
1154 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1155
1156 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1157 ret_val = phy->ops.write_reg(hw,
1158 PHY_1000T_CTRL,
1159 mii_1000t_ctrl_reg);
1160 if (ret_val)
1161 goto out;
1162 }
1163
1164 out:
1165 return ret_val;
1166 }
1167
1168 /**
1169 * igb_setup_copper_link - Configure copper link settings
1170 * @hw: pointer to the HW structure
1171 *
1172 * Calls the appropriate function to configure the link for auto-neg or forced
1173 * speed and duplex. Then we check for link, once link is established calls
1174 * to configure collision distance and flow control are called. If link is
1175 * not established, we return -E1000_ERR_PHY (-2).
1176 **/
1177 s32 igb_setup_copper_link(struct e1000_hw *hw)
1178 {
1179 s32 ret_val;
1180 bool link;
1181
1182 if (hw->mac.autoneg) {
1183 /* Setup autoneg and flow control advertisement and perform
1184 * autonegotiation.
1185 */
1186 ret_val = igb_copper_link_autoneg(hw);
1187 if (ret_val)
1188 goto out;
1189 } else {
1190 /* PHY will be set to 10H, 10F, 100H or 100F
1191 * depending on user settings.
1192 */
1193 hw_dbg("Forcing Speed and Duplex\n");
1194 ret_val = hw->phy.ops.force_speed_duplex(hw);
1195 if (ret_val) {
1196 hw_dbg("Error Forcing Speed and Duplex\n");
1197 goto out;
1198 }
1199 }
1200
1201 /* Check link status. Wait up to 100 microseconds for link to become
1202 * valid.
1203 */
1204 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1205 if (ret_val)
1206 goto out;
1207
1208 if (link) {
1209 hw_dbg("Valid link established!!!\n");
1210 igb_config_collision_dist(hw);
1211 ret_val = igb_config_fc_after_link_up(hw);
1212 } else {
1213 hw_dbg("Unable to establish link!!!\n");
1214 }
1215
1216 out:
1217 return ret_val;
1218 }
1219
1220 /**
1221 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1222 * @hw: pointer to the HW structure
1223 *
1224 * Calls the PHY setup function to force speed and duplex. Clears the
1225 * auto-crossover to force MDI manually. Waits for link and returns
1226 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1227 **/
1228 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1229 {
1230 struct e1000_phy_info *phy = &hw->phy;
1231 s32 ret_val;
1232 u16 phy_data;
1233 bool link;
1234
1235 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1236 if (ret_val)
1237 goto out;
1238
1239 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1240
1241 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1242 if (ret_val)
1243 goto out;
1244
1245 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1246 * forced whenever speed and duplex are forced.
1247 */
1248 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1249 if (ret_val)
1250 goto out;
1251
1252 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1253 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1254
1255 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1256 if (ret_val)
1257 goto out;
1258
1259 hw_dbg("IGP PSCR: %X\n", phy_data);
1260
1261 udelay(1);
1262
1263 if (phy->autoneg_wait_to_complete) {
1264 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1265
1266 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1267 if (ret_val)
1268 goto out;
1269
1270 if (!link)
1271 hw_dbg("Link taking longer than expected.\n");
1272
1273 /* Try once more */
1274 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1275 if (ret_val)
1276 goto out;
1277 }
1278
1279 out:
1280 return ret_val;
1281 }
1282
1283 /**
1284 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1285 * @hw: pointer to the HW structure
1286 *
1287 * Calls the PHY setup function to force speed and duplex. Clears the
1288 * auto-crossover to force MDI manually. Resets the PHY to commit the
1289 * changes. If time expires while waiting for link up, we reset the DSP.
1290 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1291 * successful completion, else return corresponding error code.
1292 **/
1293 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1294 {
1295 struct e1000_phy_info *phy = &hw->phy;
1296 s32 ret_val;
1297 u16 phy_data;
1298 bool link;
1299
1300 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1301 if (phy->type != e1000_phy_i210) {
1302 /* Clear Auto-Crossover to force MDI manually. M88E1000
1303 * requires MDI forced whenever speed and duplex are forced.
1304 */
1305 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1306 &phy_data);
1307 if (ret_val)
1308 goto out;
1309
1310 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1311 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1312 phy_data);
1313 if (ret_val)
1314 goto out;
1315
1316 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1317 }
1318
1319 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1320 if (ret_val)
1321 goto out;
1322
1323 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1324
1325 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1326 if (ret_val)
1327 goto out;
1328
1329 /* Reset the phy to commit changes. */
1330 ret_val = igb_phy_sw_reset(hw);
1331 if (ret_val)
1332 goto out;
1333
1334 if (phy->autoneg_wait_to_complete) {
1335 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1336
1337 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1338 if (ret_val)
1339 goto out;
1340
1341 if (!link) {
1342 bool reset_dsp = true;
1343
1344 switch (hw->phy.id) {
1345 case I347AT4_E_PHY_ID:
1346 case M88E1112_E_PHY_ID:
1347 case I210_I_PHY_ID:
1348 reset_dsp = false;
1349 break;
1350 default:
1351 if (hw->phy.type != e1000_phy_m88)
1352 reset_dsp = false;
1353 break;
1354 }
1355 if (!reset_dsp)
1356 hw_dbg("Link taking longer than expected.\n");
1357 else {
1358 /* We didn't get link.
1359 * Reset the DSP and cross our fingers.
1360 */
1361 ret_val = phy->ops.write_reg(hw,
1362 M88E1000_PHY_PAGE_SELECT,
1363 0x001d);
1364 if (ret_val)
1365 goto out;
1366 ret_val = igb_phy_reset_dsp(hw);
1367 if (ret_val)
1368 goto out;
1369 }
1370 }
1371
1372 /* Try once more */
1373 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1374 100000, &link);
1375 if (ret_val)
1376 goto out;
1377 }
1378
1379 if (hw->phy.type != e1000_phy_m88 ||
1380 hw->phy.id == I347AT4_E_PHY_ID ||
1381 hw->phy.id == M88E1112_E_PHY_ID ||
1382 hw->phy.id == I210_I_PHY_ID)
1383 goto out;
1384
1385 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1386 if (ret_val)
1387 goto out;
1388
1389 /* Resetting the phy means we need to re-force TX_CLK in the
1390 * Extended PHY Specific Control Register to 25MHz clock from
1391 * the reset value of 2.5MHz.
1392 */
1393 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1394 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1395 if (ret_val)
1396 goto out;
1397
1398 /* In addition, we must re-enable CRS on Tx for both half and full
1399 * duplex.
1400 */
1401 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1402 if (ret_val)
1403 goto out;
1404
1405 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1406 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1407
1408 out:
1409 return ret_val;
1410 }
1411
1412 /**
1413 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1414 * @hw: pointer to the HW structure
1415 * @phy_ctrl: pointer to current value of PHY_CONTROL
1416 *
1417 * Forces speed and duplex on the PHY by doing the following: disable flow
1418 * control, force speed/duplex on the MAC, disable auto speed detection,
1419 * disable auto-negotiation, configure duplex, configure speed, configure
1420 * the collision distance, write configuration to CTRL register. The
1421 * caller must write to the PHY_CONTROL register for these settings to
1422 * take affect.
1423 **/
1424 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1425 u16 *phy_ctrl)
1426 {
1427 struct e1000_mac_info *mac = &hw->mac;
1428 u32 ctrl;
1429
1430 /* Turn off flow control when forcing speed/duplex */
1431 hw->fc.current_mode = e1000_fc_none;
1432
1433 /* Force speed/duplex on the mac */
1434 ctrl = rd32(E1000_CTRL);
1435 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1436 ctrl &= ~E1000_CTRL_SPD_SEL;
1437
1438 /* Disable Auto Speed Detection */
1439 ctrl &= ~E1000_CTRL_ASDE;
1440
1441 /* Disable autoneg on the phy */
1442 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1443
1444 /* Forcing Full or Half Duplex? */
1445 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1446 ctrl &= ~E1000_CTRL_FD;
1447 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1448 hw_dbg("Half Duplex\n");
1449 } else {
1450 ctrl |= E1000_CTRL_FD;
1451 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1452 hw_dbg("Full Duplex\n");
1453 }
1454
1455 /* Forcing 10mb or 100mb? */
1456 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1457 ctrl |= E1000_CTRL_SPD_100;
1458 *phy_ctrl |= MII_CR_SPEED_100;
1459 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1460 hw_dbg("Forcing 100mb\n");
1461 } else {
1462 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1463 *phy_ctrl |= MII_CR_SPEED_10;
1464 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1465 hw_dbg("Forcing 10mb\n");
1466 }
1467
1468 igb_config_collision_dist(hw);
1469
1470 wr32(E1000_CTRL, ctrl);
1471 }
1472
1473 /**
1474 * igb_set_d3_lplu_state - Sets low power link up state for D3
1475 * @hw: pointer to the HW structure
1476 * @active: boolean used to enable/disable lplu
1477 *
1478 * Success returns 0, Failure returns 1
1479 *
1480 * The low power link up (lplu) state is set to the power management level D3
1481 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1482 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1483 * is used during Dx states where the power conservation is most important.
1484 * During driver activity, SmartSpeed should be enabled so performance is
1485 * maintained.
1486 **/
1487 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1488 {
1489 struct e1000_phy_info *phy = &hw->phy;
1490 s32 ret_val = 0;
1491 u16 data;
1492
1493 if (!(hw->phy.ops.read_reg))
1494 goto out;
1495
1496 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1497 if (ret_val)
1498 goto out;
1499
1500 if (!active) {
1501 data &= ~IGP02E1000_PM_D3_LPLU;
1502 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1503 data);
1504 if (ret_val)
1505 goto out;
1506 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1507 * during Dx states where the power conservation is most
1508 * important. During driver activity we should enable
1509 * SmartSpeed, so performance is maintained.
1510 */
1511 if (phy->smart_speed == e1000_smart_speed_on) {
1512 ret_val = phy->ops.read_reg(hw,
1513 IGP01E1000_PHY_PORT_CONFIG,
1514 &data);
1515 if (ret_val)
1516 goto out;
1517
1518 data |= IGP01E1000_PSCFR_SMART_SPEED;
1519 ret_val = phy->ops.write_reg(hw,
1520 IGP01E1000_PHY_PORT_CONFIG,
1521 data);
1522 if (ret_val)
1523 goto out;
1524 } else if (phy->smart_speed == e1000_smart_speed_off) {
1525 ret_val = phy->ops.read_reg(hw,
1526 IGP01E1000_PHY_PORT_CONFIG,
1527 &data);
1528 if (ret_val)
1529 goto out;
1530
1531 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1532 ret_val = phy->ops.write_reg(hw,
1533 IGP01E1000_PHY_PORT_CONFIG,
1534 data);
1535 if (ret_val)
1536 goto out;
1537 }
1538 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1539 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1540 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1541 data |= IGP02E1000_PM_D3_LPLU;
1542 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1543 data);
1544 if (ret_val)
1545 goto out;
1546
1547 /* When LPLU is enabled, we should disable SmartSpeed */
1548 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1549 &data);
1550 if (ret_val)
1551 goto out;
1552
1553 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1554 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1555 data);
1556 }
1557
1558 out:
1559 return ret_val;
1560 }
1561
1562 /**
1563 * igb_check_downshift - Checks whether a downshift in speed occurred
1564 * @hw: pointer to the HW structure
1565 *
1566 * Success returns 0, Failure returns 1
1567 *
1568 * A downshift is detected by querying the PHY link health.
1569 **/
1570 s32 igb_check_downshift(struct e1000_hw *hw)
1571 {
1572 struct e1000_phy_info *phy = &hw->phy;
1573 s32 ret_val;
1574 u16 phy_data, offset, mask;
1575
1576 switch (phy->type) {
1577 case e1000_phy_i210:
1578 case e1000_phy_m88:
1579 case e1000_phy_gg82563:
1580 offset = M88E1000_PHY_SPEC_STATUS;
1581 mask = M88E1000_PSSR_DOWNSHIFT;
1582 break;
1583 case e1000_phy_igp_2:
1584 case e1000_phy_igp:
1585 case e1000_phy_igp_3:
1586 offset = IGP01E1000_PHY_LINK_HEALTH;
1587 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1588 break;
1589 default:
1590 /* speed downshift not supported */
1591 phy->speed_downgraded = false;
1592 ret_val = 0;
1593 goto out;
1594 }
1595
1596 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1597
1598 if (!ret_val)
1599 phy->speed_downgraded = (phy_data & mask) ? true : false;
1600
1601 out:
1602 return ret_val;
1603 }
1604
1605 /**
1606 * igb_check_polarity_m88 - Checks the polarity.
1607 * @hw: pointer to the HW structure
1608 *
1609 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1610 *
1611 * Polarity is determined based on the PHY specific status register.
1612 **/
1613 s32 igb_check_polarity_m88(struct e1000_hw *hw)
1614 {
1615 struct e1000_phy_info *phy = &hw->phy;
1616 s32 ret_val;
1617 u16 data;
1618
1619 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1620
1621 if (!ret_val)
1622 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1623 ? e1000_rev_polarity_reversed
1624 : e1000_rev_polarity_normal;
1625
1626 return ret_val;
1627 }
1628
1629 /**
1630 * igb_check_polarity_igp - Checks the polarity.
1631 * @hw: pointer to the HW structure
1632 *
1633 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1634 *
1635 * Polarity is determined based on the PHY port status register, and the
1636 * current speed (since there is no polarity at 100Mbps).
1637 **/
1638 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1639 {
1640 struct e1000_phy_info *phy = &hw->phy;
1641 s32 ret_val;
1642 u16 data, offset, mask;
1643
1644 /* Polarity is determined based on the speed of
1645 * our connection.
1646 */
1647 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1648 if (ret_val)
1649 goto out;
1650
1651 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1652 IGP01E1000_PSSR_SPEED_1000MBPS) {
1653 offset = IGP01E1000_PHY_PCS_INIT_REG;
1654 mask = IGP01E1000_PHY_POLARITY_MASK;
1655 } else {
1656 /* This really only applies to 10Mbps since
1657 * there is no polarity for 100Mbps (always 0).
1658 */
1659 offset = IGP01E1000_PHY_PORT_STATUS;
1660 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1661 }
1662
1663 ret_val = phy->ops.read_reg(hw, offset, &data);
1664
1665 if (!ret_val)
1666 phy->cable_polarity = (data & mask)
1667 ? e1000_rev_polarity_reversed
1668 : e1000_rev_polarity_normal;
1669
1670 out:
1671 return ret_val;
1672 }
1673
1674 /**
1675 * igb_wait_autoneg - Wait for auto-neg completion
1676 * @hw: pointer to the HW structure
1677 *
1678 * Waits for auto-negotiation to complete or for the auto-negotiation time
1679 * limit to expire, which ever happens first.
1680 **/
1681 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1682 {
1683 s32 ret_val = 0;
1684 u16 i, phy_status;
1685
1686 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1687 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1688 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1689 if (ret_val)
1690 break;
1691 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1692 if (ret_val)
1693 break;
1694 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1695 break;
1696 msleep(100);
1697 }
1698
1699 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1700 * has completed.
1701 */
1702 return ret_val;
1703 }
1704
1705 /**
1706 * igb_phy_has_link - Polls PHY for link
1707 * @hw: pointer to the HW structure
1708 * @iterations: number of times to poll for link
1709 * @usec_interval: delay between polling attempts
1710 * @success: pointer to whether polling was successful or not
1711 *
1712 * Polls the PHY status register for link, 'iterations' number of times.
1713 **/
1714 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1715 u32 usec_interval, bool *success)
1716 {
1717 s32 ret_val = 0;
1718 u16 i, phy_status;
1719
1720 for (i = 0; i < iterations; i++) {
1721 /* Some PHYs require the PHY_STATUS register to be read
1722 * twice due to the link bit being sticky. No harm doing
1723 * it across the board.
1724 */
1725 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1726 if (ret_val && usec_interval > 0) {
1727 /* If the first read fails, another entity may have
1728 * ownership of the resources, wait and try again to
1729 * see if they have relinquished the resources yet.
1730 */
1731 udelay(usec_interval);
1732 }
1733 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1734 if (ret_val)
1735 break;
1736 if (phy_status & MII_SR_LINK_STATUS)
1737 break;
1738 if (usec_interval >= 1000)
1739 mdelay(usec_interval/1000);
1740 else
1741 udelay(usec_interval);
1742 }
1743
1744 *success = (i < iterations) ? true : false;
1745
1746 return ret_val;
1747 }
1748
1749 /**
1750 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1751 * @hw: pointer to the HW structure
1752 *
1753 * Reads the PHY specific status register to retrieve the cable length
1754 * information. The cable length is determined by averaging the minimum and
1755 * maximum values to get the "average" cable length. The m88 PHY has four
1756 * possible cable length values, which are:
1757 * Register Value Cable Length
1758 * 0 < 50 meters
1759 * 1 50 - 80 meters
1760 * 2 80 - 110 meters
1761 * 3 110 - 140 meters
1762 * 4 > 140 meters
1763 **/
1764 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1765 {
1766 struct e1000_phy_info *phy = &hw->phy;
1767 s32 ret_val;
1768 u16 phy_data, index;
1769
1770 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1771 if (ret_val)
1772 goto out;
1773
1774 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1775 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1776 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1777 ret_val = -E1000_ERR_PHY;
1778 goto out;
1779 }
1780
1781 phy->min_cable_length = e1000_m88_cable_length_table[index];
1782 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1783
1784 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1785
1786 out:
1787 return ret_val;
1788 }
1789
1790 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1791 {
1792 struct e1000_phy_info *phy = &hw->phy;
1793 s32 ret_val;
1794 u16 phy_data, phy_data2, index, default_page, is_cm;
1795
1796 switch (hw->phy.id) {
1797 case I210_I_PHY_ID:
1798 /* Get cable length from PHY Cable Diagnostics Control Reg */
1799 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1800 (I347AT4_PCDL + phy->addr),
1801 &phy_data);
1802 if (ret_val)
1803 return ret_val;
1804
1805 /* Check if the unit of cable length is meters or cm */
1806 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1807 I347AT4_PCDC, &phy_data2);
1808 if (ret_val)
1809 return ret_val;
1810
1811 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1812
1813 /* Populate the phy structure with cable length in meters */
1814 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1815 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1816 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1817 break;
1818 case M88E1543_E_PHY_ID:
1819 case I347AT4_E_PHY_ID:
1820 /* Remember the original page select and set it to 7 */
1821 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1822 &default_page);
1823 if (ret_val)
1824 goto out;
1825
1826 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1827 if (ret_val)
1828 goto out;
1829
1830 /* Get cable length from PHY Cable Diagnostics Control Reg */
1831 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1832 &phy_data);
1833 if (ret_val)
1834 goto out;
1835
1836 /* Check if the unit of cable length is meters or cm */
1837 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1838 if (ret_val)
1839 goto out;
1840
1841 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1842
1843 /* Populate the phy structure with cable length in meters */
1844 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1845 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1846 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1847
1848 /* Reset the page selec to its original value */
1849 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1850 default_page);
1851 if (ret_val)
1852 goto out;
1853 break;
1854 case M88E1112_E_PHY_ID:
1855 /* Remember the original page select and set it to 5 */
1856 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1857 &default_page);
1858 if (ret_val)
1859 goto out;
1860
1861 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1862 if (ret_val)
1863 goto out;
1864
1865 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1866 &phy_data);
1867 if (ret_val)
1868 goto out;
1869
1870 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1871 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1872 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1873 ret_val = -E1000_ERR_PHY;
1874 goto out;
1875 }
1876
1877 phy->min_cable_length = e1000_m88_cable_length_table[index];
1878 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1879
1880 phy->cable_length = (phy->min_cable_length +
1881 phy->max_cable_length) / 2;
1882
1883 /* Reset the page select to its original value */
1884 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1885 default_page);
1886 if (ret_val)
1887 goto out;
1888
1889 break;
1890 default:
1891 ret_val = -E1000_ERR_PHY;
1892 goto out;
1893 }
1894
1895 out:
1896 return ret_val;
1897 }
1898
1899 /**
1900 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1901 * @hw: pointer to the HW structure
1902 *
1903 * The automatic gain control (agc) normalizes the amplitude of the
1904 * received signal, adjusting for the attenuation produced by the
1905 * cable. By reading the AGC registers, which represent the
1906 * combination of coarse and fine gain value, the value can be put
1907 * into a lookup table to obtain the approximate cable length
1908 * for each channel.
1909 **/
1910 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1911 {
1912 struct e1000_phy_info *phy = &hw->phy;
1913 s32 ret_val = 0;
1914 u16 phy_data, i, agc_value = 0;
1915 u16 cur_agc_index, max_agc_index = 0;
1916 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1917 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1918 IGP02E1000_PHY_AGC_A,
1919 IGP02E1000_PHY_AGC_B,
1920 IGP02E1000_PHY_AGC_C,
1921 IGP02E1000_PHY_AGC_D
1922 };
1923
1924 /* Read the AGC registers for all channels */
1925 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1926 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1927 if (ret_val)
1928 goto out;
1929
1930 /* Getting bits 15:9, which represent the combination of
1931 * coarse and fine gain values. The result is a number
1932 * that can be put into the lookup table to obtain the
1933 * approximate cable length.
1934 */
1935 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1936 IGP02E1000_AGC_LENGTH_MASK;
1937
1938 /* Array index bound check. */
1939 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1940 (cur_agc_index == 0)) {
1941 ret_val = -E1000_ERR_PHY;
1942 goto out;
1943 }
1944
1945 /* Remove min & max AGC values from calculation. */
1946 if (e1000_igp_2_cable_length_table[min_agc_index] >
1947 e1000_igp_2_cable_length_table[cur_agc_index])
1948 min_agc_index = cur_agc_index;
1949 if (e1000_igp_2_cable_length_table[max_agc_index] <
1950 e1000_igp_2_cable_length_table[cur_agc_index])
1951 max_agc_index = cur_agc_index;
1952
1953 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1954 }
1955
1956 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1957 e1000_igp_2_cable_length_table[max_agc_index]);
1958 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1959
1960 /* Calculate cable length with the error range of +/- 10 meters. */
1961 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1962 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1963 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1964
1965 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1966
1967 out:
1968 return ret_val;
1969 }
1970
1971 /**
1972 * igb_get_phy_info_m88 - Retrieve PHY information
1973 * @hw: pointer to the HW structure
1974 *
1975 * Valid for only copper links. Read the PHY status register (sticky read)
1976 * to verify that link is up. Read the PHY special control register to
1977 * determine the polarity and 10base-T extended distance. Read the PHY
1978 * special status register to determine MDI/MDIx and current speed. If
1979 * speed is 1000, then determine cable length, local and remote receiver.
1980 **/
1981 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1982 {
1983 struct e1000_phy_info *phy = &hw->phy;
1984 s32 ret_val;
1985 u16 phy_data;
1986 bool link;
1987
1988 if (phy->media_type != e1000_media_type_copper) {
1989 hw_dbg("Phy info is only valid for copper media\n");
1990 ret_val = -E1000_ERR_CONFIG;
1991 goto out;
1992 }
1993
1994 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1995 if (ret_val)
1996 goto out;
1997
1998 if (!link) {
1999 hw_dbg("Phy info is only valid if link is up\n");
2000 ret_val = -E1000_ERR_CONFIG;
2001 goto out;
2002 }
2003
2004 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2005 if (ret_val)
2006 goto out;
2007
2008 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2009 ? true : false;
2010
2011 ret_val = igb_check_polarity_m88(hw);
2012 if (ret_val)
2013 goto out;
2014
2015 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2016 if (ret_val)
2017 goto out;
2018
2019 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
2020
2021 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2022 ret_val = phy->ops.get_cable_length(hw);
2023 if (ret_val)
2024 goto out;
2025
2026 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2027 if (ret_val)
2028 goto out;
2029
2030 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2031 ? e1000_1000t_rx_status_ok
2032 : e1000_1000t_rx_status_not_ok;
2033
2034 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2035 ? e1000_1000t_rx_status_ok
2036 : e1000_1000t_rx_status_not_ok;
2037 } else {
2038 /* Set values to "undefined" */
2039 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2040 phy->local_rx = e1000_1000t_rx_status_undefined;
2041 phy->remote_rx = e1000_1000t_rx_status_undefined;
2042 }
2043
2044 out:
2045 return ret_val;
2046 }
2047
2048 /**
2049 * igb_get_phy_info_igp - Retrieve igp PHY information
2050 * @hw: pointer to the HW structure
2051 *
2052 * Read PHY status to determine if link is up. If link is up, then
2053 * set/determine 10base-T extended distance and polarity correction. Read
2054 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2055 * determine on the cable length, local and remote receiver.
2056 **/
2057 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
2058 {
2059 struct e1000_phy_info *phy = &hw->phy;
2060 s32 ret_val;
2061 u16 data;
2062 bool link;
2063
2064 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2065 if (ret_val)
2066 goto out;
2067
2068 if (!link) {
2069 hw_dbg("Phy info is only valid if link is up\n");
2070 ret_val = -E1000_ERR_CONFIG;
2071 goto out;
2072 }
2073
2074 phy->polarity_correction = true;
2075
2076 ret_val = igb_check_polarity_igp(hw);
2077 if (ret_val)
2078 goto out;
2079
2080 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2081 if (ret_val)
2082 goto out;
2083
2084 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2085
2086 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2087 IGP01E1000_PSSR_SPEED_1000MBPS) {
2088 ret_val = phy->ops.get_cable_length(hw);
2089 if (ret_val)
2090 goto out;
2091
2092 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2093 if (ret_val)
2094 goto out;
2095
2096 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2097 ? e1000_1000t_rx_status_ok
2098 : e1000_1000t_rx_status_not_ok;
2099
2100 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2101 ? e1000_1000t_rx_status_ok
2102 : e1000_1000t_rx_status_not_ok;
2103 } else {
2104 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2105 phy->local_rx = e1000_1000t_rx_status_undefined;
2106 phy->remote_rx = e1000_1000t_rx_status_undefined;
2107 }
2108
2109 out:
2110 return ret_val;
2111 }
2112
2113 /**
2114 * igb_phy_sw_reset - PHY software reset
2115 * @hw: pointer to the HW structure
2116 *
2117 * Does a software reset of the PHY by reading the PHY control register and
2118 * setting/write the control register reset bit to the PHY.
2119 **/
2120 s32 igb_phy_sw_reset(struct e1000_hw *hw)
2121 {
2122 s32 ret_val = 0;
2123 u16 phy_ctrl;
2124
2125 if (!(hw->phy.ops.read_reg))
2126 goto out;
2127
2128 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2129 if (ret_val)
2130 goto out;
2131
2132 phy_ctrl |= MII_CR_RESET;
2133 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2134 if (ret_val)
2135 goto out;
2136
2137 udelay(1);
2138
2139 out:
2140 return ret_val;
2141 }
2142
2143 /**
2144 * igb_phy_hw_reset - PHY hardware reset
2145 * @hw: pointer to the HW structure
2146 *
2147 * Verify the reset block is not blocking us from resetting. Acquire
2148 * semaphore (if necessary) and read/set/write the device control reset
2149 * bit in the PHY. Wait the appropriate delay time for the device to
2150 * reset and release the semaphore (if necessary).
2151 **/
2152 s32 igb_phy_hw_reset(struct e1000_hw *hw)
2153 {
2154 struct e1000_phy_info *phy = &hw->phy;
2155 s32 ret_val;
2156 u32 ctrl;
2157
2158 ret_val = igb_check_reset_block(hw);
2159 if (ret_val) {
2160 ret_val = 0;
2161 goto out;
2162 }
2163
2164 ret_val = phy->ops.acquire(hw);
2165 if (ret_val)
2166 goto out;
2167
2168 ctrl = rd32(E1000_CTRL);
2169 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2170 wrfl();
2171
2172 udelay(phy->reset_delay_us);
2173
2174 wr32(E1000_CTRL, ctrl);
2175 wrfl();
2176
2177 udelay(150);
2178
2179 phy->ops.release(hw);
2180
2181 ret_val = phy->ops.get_cfg_done(hw);
2182
2183 out:
2184 return ret_val;
2185 }
2186
2187 /**
2188 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2189 * @hw: pointer to the HW structure
2190 *
2191 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2192 **/
2193 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2194 {
2195 hw_dbg("Running IGP 3 PHY init script\n");
2196
2197 /* PHY init IGP 3 */
2198 /* Enable rise/fall, 10-mode work in class-A */
2199 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2200 /* Remove all caps from Replica path filter */
2201 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2202 /* Bias trimming for ADC, AFE and Driver (Default) */
2203 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2204 /* Increase Hybrid poly bias */
2205 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2206 /* Add 4% to TX amplitude in Giga mode */
2207 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2208 /* Disable trimming (TTT) */
2209 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2210 /* Poly DC correction to 94.6% + 2% for all channels */
2211 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2212 /* ABS DC correction to 95.9% */
2213 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2214 /* BG temp curve trim */
2215 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2216 /* Increasing ADC OPAMP stage 1 currents to max */
2217 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2218 /* Force 1000 ( required for enabling PHY regs configuration) */
2219 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2220 /* Set upd_freq to 6 */
2221 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2222 /* Disable NPDFE */
2223 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2224 /* Disable adaptive fixed FFE (Default) */
2225 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2226 /* Enable FFE hysteresis */
2227 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2228 /* Fixed FFE for short cable lengths */
2229 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2230 /* Fixed FFE for medium cable lengths */
2231 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2232 /* Fixed FFE for long cable lengths */
2233 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2234 /* Enable Adaptive Clip Threshold */
2235 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2236 /* AHT reset limit to 1 */
2237 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2238 /* Set AHT master delay to 127 msec */
2239 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2240 /* Set scan bits for AHT */
2241 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2242 /* Set AHT Preset bits */
2243 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2244 /* Change integ_factor of channel A to 3 */
2245 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2246 /* Change prop_factor of channels BCD to 8 */
2247 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2248 /* Change cg_icount + enable integbp for channels BCD */
2249 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2250 /* Change cg_icount + enable integbp + change prop_factor_master
2251 * to 8 for channel A
2252 */
2253 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2254 /* Disable AHT in Slave mode on channel A */
2255 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2256 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2257 * Enable SPD+B2B
2258 */
2259 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2260 /* Enable restart AN on an1000_dis change */
2261 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2262 /* Enable wh_fifo read clock in 10/100 modes */
2263 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2264 /* Restart AN, Speed selection is 1000 */
2265 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2266
2267 return 0;
2268 }
2269
2270 /**
2271 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2272 * @hw: pointer to the HW structure
2273 *
2274 * In the case of a PHY power down to save power, or to turn off link during a
2275 * driver unload, restore the link to previous settings.
2276 **/
2277 void igb_power_up_phy_copper(struct e1000_hw *hw)
2278 {
2279 u16 mii_reg = 0;
2280 u16 power_reg = 0;
2281
2282 /* The PHY will retain its settings across a power down/up cycle */
2283 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2284 mii_reg &= ~MII_CR_POWER_DOWN;
2285 if (hw->phy.type == e1000_phy_i210) {
2286 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2287 power_reg &= ~GS40G_CS_POWER_DOWN;
2288 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2289 }
2290 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2291 }
2292
2293 /**
2294 * igb_power_down_phy_copper - Power down copper PHY
2295 * @hw: pointer to the HW structure
2296 *
2297 * Power down PHY to save power when interface is down and wake on lan
2298 * is not enabled.
2299 **/
2300 void igb_power_down_phy_copper(struct e1000_hw *hw)
2301 {
2302 u16 mii_reg = 0;
2303 u16 power_reg = 0;
2304
2305 /* The PHY will retain its settings across a power down/up cycle */
2306 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2307 mii_reg |= MII_CR_POWER_DOWN;
2308
2309 /* i210 Phy requires an additional bit for power up/down */
2310 if (hw->phy.type == e1000_phy_i210) {
2311 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2312 power_reg |= GS40G_CS_POWER_DOWN;
2313 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2314 }
2315 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2316 msleep(1);
2317 }
2318
2319 /**
2320 * igb_check_polarity_82580 - Checks the polarity.
2321 * @hw: pointer to the HW structure
2322 *
2323 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2324 *
2325 * Polarity is determined based on the PHY specific status register.
2326 **/
2327 static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2328 {
2329 struct e1000_phy_info *phy = &hw->phy;
2330 s32 ret_val;
2331 u16 data;
2332
2333
2334 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2335
2336 if (!ret_val)
2337 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2338 ? e1000_rev_polarity_reversed
2339 : e1000_rev_polarity_normal;
2340
2341 return ret_val;
2342 }
2343
2344 /**
2345 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2346 * @hw: pointer to the HW structure
2347 *
2348 * Calls the PHY setup function to force speed and duplex. Clears the
2349 * auto-crossover to force MDI manually. Waits for link and returns
2350 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2351 **/
2352 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2353 {
2354 struct e1000_phy_info *phy = &hw->phy;
2355 s32 ret_val;
2356 u16 phy_data;
2357 bool link;
2358
2359 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2360 if (ret_val)
2361 goto out;
2362
2363 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2364
2365 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2366 if (ret_val)
2367 goto out;
2368
2369 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2370 * forced whenever speed and duplex are forced.
2371 */
2372 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2373 if (ret_val)
2374 goto out;
2375
2376 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2377
2378 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2379 if (ret_val)
2380 goto out;
2381
2382 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2383
2384 udelay(1);
2385
2386 if (phy->autoneg_wait_to_complete) {
2387 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2388
2389 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2390 if (ret_val)
2391 goto out;
2392
2393 if (!link)
2394 hw_dbg("Link taking longer than expected.\n");
2395
2396 /* Try once more */
2397 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2398 if (ret_val)
2399 goto out;
2400 }
2401
2402 out:
2403 return ret_val;
2404 }
2405
2406 /**
2407 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2408 * @hw: pointer to the HW structure
2409 *
2410 * Read PHY status to determine if link is up. If link is up, then
2411 * set/determine 10base-T extended distance and polarity correction. Read
2412 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2413 * determine on the cable length, local and remote receiver.
2414 **/
2415 s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2416 {
2417 struct e1000_phy_info *phy = &hw->phy;
2418 s32 ret_val;
2419 u16 data;
2420 bool link;
2421
2422 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2423 if (ret_val)
2424 goto out;
2425
2426 if (!link) {
2427 hw_dbg("Phy info is only valid if link is up\n");
2428 ret_val = -E1000_ERR_CONFIG;
2429 goto out;
2430 }
2431
2432 phy->polarity_correction = true;
2433
2434 ret_val = igb_check_polarity_82580(hw);
2435 if (ret_val)
2436 goto out;
2437
2438 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2439 if (ret_val)
2440 goto out;
2441
2442 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2443
2444 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2445 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2446 ret_val = hw->phy.ops.get_cable_length(hw);
2447 if (ret_val)
2448 goto out;
2449
2450 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2451 if (ret_val)
2452 goto out;
2453
2454 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2455 ? e1000_1000t_rx_status_ok
2456 : e1000_1000t_rx_status_not_ok;
2457
2458 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2459 ? e1000_1000t_rx_status_ok
2460 : e1000_1000t_rx_status_not_ok;
2461 } else {
2462 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2463 phy->local_rx = e1000_1000t_rx_status_undefined;
2464 phy->remote_rx = e1000_1000t_rx_status_undefined;
2465 }
2466
2467 out:
2468 return ret_val;
2469 }
2470
2471 /**
2472 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2473 * @hw: pointer to the HW structure
2474 *
2475 * Reads the diagnostic status register and verifies result is valid before
2476 * placing it in the phy_cable_length field.
2477 **/
2478 s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2479 {
2480 struct e1000_phy_info *phy = &hw->phy;
2481 s32 ret_val;
2482 u16 phy_data, length;
2483
2484 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2485 if (ret_val)
2486 goto out;
2487
2488 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2489 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2490
2491 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2492 ret_val = -E1000_ERR_PHY;
2493
2494 phy->cable_length = length;
2495
2496 out:
2497 return ret_val;
2498 }
2499
2500 /**
2501 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2502 * @hw: pointer to the HW structure
2503 * @offset: lower half is register offset to write to
2504 * upper half is page to use.
2505 * @data: data to write at register offset
2506 *
2507 * Acquires semaphore, if necessary, then writes the data to PHY register
2508 * at the offset. Release any acquired semaphores before exiting.
2509 **/
2510 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2511 {
2512 s32 ret_val;
2513 u16 page = offset >> GS40G_PAGE_SHIFT;
2514
2515 offset = offset & GS40G_OFFSET_MASK;
2516 ret_val = hw->phy.ops.acquire(hw);
2517 if (ret_val)
2518 return ret_val;
2519
2520 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2521 if (ret_val)
2522 goto release;
2523 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2524
2525 release:
2526 hw->phy.ops.release(hw);
2527 return ret_val;
2528 }
2529
2530 /**
2531 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2532 * @hw: pointer to the HW structure
2533 * @offset: lower half is register offset to read to
2534 * upper half is page to use.
2535 * @data: data to read at register offset
2536 *
2537 * Acquires semaphore, if necessary, then reads the data in the PHY register
2538 * at the offset. Release any acquired semaphores before exiting.
2539 **/
2540 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2541 {
2542 s32 ret_val;
2543 u16 page = offset >> GS40G_PAGE_SHIFT;
2544
2545 offset = offset & GS40G_OFFSET_MASK;
2546 ret_val = hw->phy.ops.acquire(hw);
2547 if (ret_val)
2548 return ret_val;
2549
2550 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2551 if (ret_val)
2552 goto release;
2553 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2554
2555 release:
2556 hw->phy.ops.release(hw);
2557 return ret_val;
2558 }
2559
2560 /**
2561 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2562 * @hw: pointer to the HW structure
2563 *
2564 * Sets up Master/slave mode
2565 **/
2566 static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2567 {
2568 s32 ret_val;
2569 u16 phy_data;
2570
2571 /* Resolve Master/Slave mode */
2572 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2573 if (ret_val)
2574 return ret_val;
2575
2576 /* load defaults for future use */
2577 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2578 ((phy_data & CR_1000T_MS_VALUE) ?
2579 e1000_ms_force_master :
2580 e1000_ms_force_slave) : e1000_ms_auto;
2581
2582 switch (hw->phy.ms_type) {
2583 case e1000_ms_force_master:
2584 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2585 break;
2586 case e1000_ms_force_slave:
2587 phy_data |= CR_1000T_MS_ENABLE;
2588 phy_data &= ~(CR_1000T_MS_VALUE);
2589 break;
2590 case e1000_ms_auto:
2591 phy_data &= ~CR_1000T_MS_ENABLE;
2592 /* fall-through */
2593 default:
2594 break;
2595 }
2596
2597 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2598 }
Linux kernel - Deliverables
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