drivers/net/ethernet/intel/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #ifdef CONFIG_IGB_PTP
  38 #include <linux/clocksource.h>
  39 #include <linux/net_tstamp.h>
  40 #include <linux/ptp_clock_kernel.h>
  41 #endif /* CONFIG_IGB_PTP */
  42 #include <linux/bitops.h>
  43 #include <linux/if_vlan.h>
  44
  45 struct igb_adapter;
  46
  47 /* Interrupt defines */
  48 #define IGB_START_ITR                    648 /* ~6000 ints/sec */
  49 #define IGB_4K_ITR                       980
  50 #define IGB_20K_ITR                      196
  51 #define IGB_70K_ITR                       56
  52
  53 /* TX/RX descriptor defines */
  54 #define IGB_DEFAULT_TXD                  256
  55 #define IGB_DEFAULT_TX_WORK              128
  56 #define IGB_MIN_TXD                       80
  57 #define IGB_MAX_TXD                     4096
  58
  59 #define IGB_DEFAULT_RXD                  256
  60 #define IGB_MIN_RXD                       80
  61 #define IGB_MAX_RXD                     4096
  62
  63 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  64 #define IGB_MAX_ITR_USECS              10000
  65 #define IGB_MIN_ITR_USECS                 10
  66 #define NON_Q_VECTORS                      1
  67 #define MAX_Q_VECTORS                      8
  68
  69 /* Transmit and receive queues */
  70 #define IGB_MAX_RX_QUEUES                  8
  71 #define IGB_MAX_RX_QUEUES_82575            4
  72 #define IGB_MAX_RX_QUEUES_I211             2
  73 #define IGB_MAX_TX_QUEUES                  8
  74 #define IGB_MAX_VF_MC_ENTRIES              30
  75 #define IGB_MAX_VF_FUNCTIONS               8
  76 #define IGB_MAX_VFTA_ENTRIES               128
  77 #define IGB_82576_VF_DEV_ID                0x10CA
  78 #define IGB_I350_VF_DEV_ID                 0x1520
  79
  80 /* NVM version defines */
  81 #define IGB_MAJOR_MASK                  0xF000
  82 #define IGB_MINOR_MASK                  0x0FF0
  83 #define IGB_BUILD_MASK                  0x000F
  84 #define IGB_COMB_VER_MASK               0x00FF
  85 #define IGB_MAJOR_SHIFT                 12
  86 #define IGB_MINOR_SHIFT                 4
  87 #define IGB_COMB_VER_SHFT               8
  88 #define IGB_NVM_VER_INVALID             0xFFFF
  89 #define IGB_ETRACK_SHIFT                16
  90 #define NVM_ETRACK_WORD                 0x0042
  91 #define NVM_COMB_VER_OFF                0x0083
  92 #define NVM_COMB_VER_PTR                0x003d
  93
  94 struct vf_data_storage {
  95         unsigned char vf_mac_addresses[ETH_ALEN];
  96         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  97         u16 num_vf_mc_hashes;
  98         u16 vlans_enabled;
  99         u32 flags;
 100         unsigned long last_nack;
 101         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 102         u16 pf_qos;
 103         u16 tx_rate;
 104         struct pci_dev *vfdev;
 105 };
 106
 107 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
 108 #define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
 109 #define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
 110 #define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
 111
 112 /* RX descriptor control thresholds.
 113  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 114  *           descriptors available in its onboard memory.
 115  *           Setting this to 0 disables RX descriptor prefetch.
 116  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 117  *           available in host memory.
 118  *           If PTHRESH is 0, this should also be 0.
 119  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 120  *           descriptors until either it has this many to write back, or the
 121  *           ITR timer expires.
 122  */
 123 #define IGB_RX_PTHRESH                     8
 124 #define IGB_RX_HTHRESH                     8
 125 #define IGB_TX_PTHRESH                     8
 126 #define IGB_TX_HTHRESH                     1
 127 #define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
 128                                              adapter->msix_entries) ? 1 : 4)
 129 #define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
 130                                              adapter->msix_entries) ? 1 : 16)
 131
 132 /* this is the size past which hardware will drop packets when setting LPE=0 */
 133 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 134
 135 /* Supported Rx Buffer Sizes */
 136 #define IGB_RXBUFFER_256   256
 137 #define IGB_RXBUFFER_16384 16384
 138 #define IGB_RX_HDR_LEN     IGB_RXBUFFER_256
 139
 140 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 141 #define IGB_TX_QUEUE_WAKE       16
 142 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 143 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 144
 145 #define AUTO_ALL_MODES            0
 146 #define IGB_EEPROM_APME         0x0400
 147
 148 #ifndef IGB_MASTER_SLAVE
 149 /* Switch to override PHY master/slave setting */
 150 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 151 #endif
 152
 153 #define IGB_MNG_VLAN_NONE -1
 154
 155 #define IGB_TX_FLAGS_CSUM               0x00000001
 156 #define IGB_TX_FLAGS_VLAN               0x00000002
 157 #define IGB_TX_FLAGS_TSO                0x00000004
 158 #define IGB_TX_FLAGS_IPV4               0x00000008
 159 #define IGB_TX_FLAGS_TSTAMP             0x00000010
 160 #define IGB_TX_FLAGS_VLAN_MASK          0xffff0000
 161 #define IGB_TX_FLAGS_VLAN_SHIFT 16
 162
 163 /* wrapper around a pointer to a socket buffer,
 164  * so a DMA handle can be stored along with the buffer */
 165 struct igb_tx_buffer {
 166         union e1000_adv_tx_desc *next_to_watch;
 167         unsigned long time_stamp;
 168         struct sk_buff *skb;
 169         unsigned int bytecount;
 170         u16 gso_segs;
 171         __be16 protocol;
 172         dma_addr_t dma;
 173         u32 length;
 174         u32 tx_flags;
 175 };
 176
 177 struct igb_rx_buffer {
 178         struct sk_buff *skb;
 179         dma_addr_t dma;
 180         struct page *page;
 181         dma_addr_t page_dma;
 182         u32 page_offset;
 183 };
 184
 185 struct igb_tx_queue_stats {
 186         u64 packets;
 187         u64 bytes;
 188         u64 restart_queue;
 189         u64 restart_queue2;
 190 };
 191
 192 struct igb_rx_queue_stats {
 193         u64 packets;
 194         u64 bytes;
 195         u64 drops;
 196         u64 csum_err;
 197         u64 alloc_failed;
 198 };
 199
 200 struct igb_ring_container {
 201         struct igb_ring *ring;          /* pointer to linked list of rings */
 202         unsigned int total_bytes;       /* total bytes processed this int */
 203         unsigned int total_packets;     /* total packets processed this int */
 204         u16 work_limit;                 /* total work allowed per interrupt */
 205         u8 count;                       /* total number of rings in vector */
 206         u8 itr;                         /* current ITR setting for ring */
 207 };
 208
 209 struct igb_q_vector {
 210         struct igb_adapter *adapter;    /* backlink */
 211         int cpu;                        /* CPU for DCA */
 212         u32 eims_value;                 /* EIMS mask value */
 213
 214         struct igb_ring_container rx, tx;
 215
 216         struct napi_struct napi;
 217         int numa_node;
 218
 219         u16 itr_val;
 220         u8 set_itr;
 221         void __iomem *itr_register;
 222
 223         char name[IFNAMSIZ + 9];
 224 };
 225
 226 struct igb_ring {
 227         struct igb_q_vector *q_vector;  /* backlink to q_vector */
 228         struct net_device *netdev;      /* back pointer to net_device */
 229         struct device *dev;             /* device pointer for dma mapping */
 230         union {                         /* array of buffer info structs */
 231                 struct igb_tx_buffer *tx_buffer_info;
 232                 struct igb_rx_buffer *rx_buffer_info;
 233         };
 234         void *desc;                     /* descriptor ring memory */
 235         unsigned long flags;            /* ring specific flags */
 236         void __iomem *tail;             /* pointer to ring tail register */
 237
 238         u16 count;                      /* number of desc. in the ring */
 239         u8 queue_index;                 /* logical index of the ring*/
 240         u8 reg_idx;                     /* physical index of the ring */
 241         u32 size;                       /* length of desc. ring in bytes */
 242
 243         /* everything past this point are written often */
 244         u16 next_to_clean ____cacheline_aligned_in_smp;
 245         u16 next_to_use;
 246
 247         union {
 248                 /* TX */
 249                 struct {
 250                         struct igb_tx_queue_stats tx_stats;
 251                         struct u64_stats_sync tx_syncp;
 252                         struct u64_stats_sync tx_syncp2;
 253                 };
 254                 /* RX */
 255                 struct {
 256                         struct igb_rx_queue_stats rx_stats;
 257                         struct u64_stats_sync rx_syncp;
 258                 };
 259         };
 260         /* Items past this point are only used during ring alloc / free */
 261         dma_addr_t dma;                /* phys address of the ring */
 262         int numa_node;                  /* node to alloc ring memory on */
 263 };
 264
 265 enum e1000_ring_flags_t {
 266         IGB_RING_FLAG_RX_SCTP_CSUM,
 267         IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
 268         IGB_RING_FLAG_TX_CTX_IDX,
 269         IGB_RING_FLAG_TX_DETECT_HANG
 270 };
 271
 272 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
 273
 274 #define IGB_RX_DESC(R, i)           \
 275         (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
 276 #define IGB_TX_DESC(R, i)           \
 277         (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
 278 #define IGB_TX_CTXTDESC(R, i)       \
 279         (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
 280
 281 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
 282 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
 283                                       const u32 stat_err_bits)
 284 {
 285         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 286 }
 287
 288 /* igb_desc_unused - calculate if we have unused descriptors */
 289 static inline int igb_desc_unused(struct igb_ring *ring)
 290 {
 291         if (ring->next_to_clean > ring->next_to_use)
 292                 return ring->next_to_clean - ring->next_to_use - 1;
 293
 294         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 295 }
 296
 297 /* board specific private data structure */
 298 struct igb_adapter {
 299         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 300
 301         struct net_device *netdev;
 302
 303         unsigned long state;
 304         unsigned int flags;
 305
 306         unsigned int num_q_vectors;
 307         struct msix_entry *msix_entries;
 308
 309         /* Interrupt Throttle Rate */
 310         u32 rx_itr_setting;
 311         u32 tx_itr_setting;
 312         u16 tx_itr;
 313         u16 rx_itr;
 314
 315         /* TX */
 316         u16 tx_work_limit;
 317         u32 tx_timeout_count;
 318         int num_tx_queues;
 319         struct igb_ring *tx_ring[16];
 320
 321         /* RX */
 322         int num_rx_queues;
 323         struct igb_ring *rx_ring[16];
 324
 325         u32 max_frame_size;
 326         u32 min_frame_size;
 327
 328         struct timer_list watchdog_timer;
 329         struct timer_list phy_info_timer;
 330
 331         u16 mng_vlan_id;
 332         u32 bd_number;
 333         u32 wol;
 334         u32 en_mng_pt;
 335         u16 link_speed;
 336         u16 link_duplex;
 337
 338         struct work_struct reset_task;
 339         struct work_struct watchdog_task;
 340         bool fc_autoneg;
 341         u8  tx_timeout_factor;
 342         struct timer_list blink_timer;
 343         unsigned long led_status;
 344
 345         /* OS defined structs */
 346         struct pci_dev *pdev;
 347
 348         spinlock_t stats64_lock;
 349         struct rtnl_link_stats64 stats64;
 350
 351         /* structs defined in e1000_hw.h */
 352         struct e1000_hw hw;
 353         struct e1000_hw_stats stats;
 354         struct e1000_phy_info phy_info;
 355         struct e1000_phy_stats phy_stats;
 356
 357         u32 test_icr;
 358         struct igb_ring test_tx_ring;
 359         struct igb_ring test_rx_ring;
 360
 361         int msg_enable;
 362
 363         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 364         u32 eims_enable_mask;
 365         u32 eims_other;
 366
 367         /* to not mess up cache alignment, always add to the bottom */
 368         u32 eeprom_wol;
 369
 370         u16 tx_ring_count;
 371         u16 rx_ring_count;
 372         unsigned int vfs_allocated_count;
 373         struct vf_data_storage *vf_data;
 374         int vf_rate_link_speed;
 375         u32 rss_queues;
 376         u32 wvbr;
 377         int node;
 378         u32 *shadow_vfta;
 379
 380 #ifdef CONFIG_IGB_PTP
 381         struct ptp_clock *ptp_clock;
 382         struct ptp_clock_info ptp_caps;
 383         struct delayed_work ptp_overflow_work;
 384         struct work_struct ptp_tx_work;
 385         struct sk_buff *ptp_tx_skb;
 386         spinlock_t tmreg_lock;
 387         struct cyclecounter cc;
 388         struct timecounter tc;
 389 #endif /* CONFIG_IGB_PTP */
 390
 391         char fw_version[32];
 392 };
 393
 394 #define IGB_FLAG_HAS_MSI           (1 << 0)
 395 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 396 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 397 #define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
 398 #define IGB_FLAG_DMAC              (1 << 4)
 399 #define IGB_FLAG_PTP               (1 << 5)
 400
 401 /* DMA Coalescing defines */
 402 #define IGB_MIN_TXPBSIZE           20408
 403 #define IGB_TX_BUF_4096            4096
 404 #define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */
 405
 406 #define IGB_82576_TSYNC_SHIFT 19
 407 #define IGB_TS_HDR_LEN        16
 408 enum e1000_state_t {
 409         __IGB_TESTING,
 410         __IGB_RESETTING,
 411         __IGB_DOWN
 412 };
 413
 414 enum igb_boards {
 415         board_82575,
 416 };
 417
 418 extern char igb_driver_name[];
 419 extern char igb_driver_version[];
 420
 421 extern int igb_up(struct igb_adapter *);
 422 extern void igb_down(struct igb_adapter *);
 423 extern void igb_reinit_locked(struct igb_adapter *);
 424 extern void igb_reset(struct igb_adapter *);
 425 extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
 426 extern int igb_setup_tx_resources(struct igb_ring *);
 427 extern int igb_setup_rx_resources(struct igb_ring *);
 428 extern void igb_free_tx_resources(struct igb_ring *);
 429 extern void igb_free_rx_resources(struct igb_ring *);
 430 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 431 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 432 extern void igb_setup_tctl(struct igb_adapter *);
 433 extern void igb_setup_rctl(struct igb_adapter *);
 434 extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
 435 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
 436                                            struct igb_tx_buffer *);
 437 extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
 438 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
 439 extern bool igb_has_link(struct igb_adapter *adapter);
 440 extern void igb_set_ethtool_ops(struct net_device *);
 441 extern void igb_power_up_link(struct igb_adapter *);
 442 extern void igb_set_fw_version(struct igb_adapter *);
 443 #ifdef CONFIG_IGB_PTP
 444 extern void igb_ptp_init(struct igb_adapter *adapter);
 445 extern void igb_ptp_stop(struct igb_adapter *adapter);
 446 extern void igb_ptp_reset(struct igb_adapter *adapter);
 447 extern void igb_ptp_tx_work(struct work_struct *work);
 448 extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
 449 extern void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector,
 450                                 union e1000_adv_rx_desc *rx_desc,
 451                                 struct sk_buff *skb);
 452 extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
 453                                   struct ifreq *ifr, int cmd);
 454 #endif /* CONFIG_IGB_PTP */
 455
 456 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 457 {
 458         if (hw->phy.ops.reset)
 459                 return hw->phy.ops.reset(hw);
 460
 461         return 0;
 462 }
 463
 464 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 465 {
 466         if (hw->phy.ops.read_reg)
 467                 return hw->phy.ops.read_reg(hw, offset, data);
 468
 469         return 0;
 470 }
 471
 472 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 473 {
 474         if (hw->phy.ops.write_reg)
 475                 return hw->phy.ops.write_reg(hw, offset, data);
 476
 477         return 0;
 478 }
 479
 480 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 481 {
 482         if (hw->phy.ops.get_phy_info)
 483                 return hw->phy.ops.get_phy_info(hw);
 484
 485         return 0;
 486 }
 487
 488 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
 489 {
 490         return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
 491 }
 492
 493 #endif /* _IGB_H_ */