drivers/net/ethernet/intel/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #include <linux/clocksource.h>
  38 #include <linux/timecompare.h>
  39 #include <linux/net_tstamp.h>
  40 #include <linux/bitops.h>
  41 #include <linux/if_vlan.h>
  42
  43 struct igb_adapter;
  44
  45 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  46 #define IGB_START_ITR 648
  47
  48 /* TX/RX descriptor defines */
  49 #define IGB_DEFAULT_TXD                  256
  50 #define IGB_DEFAULT_TX_WORK              128
  51 #define IGB_MIN_TXD                       80
  52 #define IGB_MAX_TXD                     4096
  53
  54 #define IGB_DEFAULT_RXD                  256
  55 #define IGB_MIN_RXD                       80
  56 #define IGB_MAX_RXD                     4096
  57
  58 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  59 #define IGB_MAX_ITR_USECS              10000
  60 #define IGB_MIN_ITR_USECS                 10
  61 #define NON_Q_VECTORS                      1
  62 #define MAX_Q_VECTORS                      8
  63
  64 /* Transmit and receive queues */
  65 #define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
  66                                            (hw->mac.type > e1000_82575 ? 8 : 4))
  67 #define IGB_MAX_TX_QUEUES                  16
  68
  69 #define IGB_MAX_VF_MC_ENTRIES              30
  70 #define IGB_MAX_VF_FUNCTIONS               8
  71 #define IGB_MAX_VFTA_ENTRIES               128
  72
  73 struct vf_data_storage {
  74         unsigned char vf_mac_addresses[ETH_ALEN];
  75         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  76         u16 num_vf_mc_hashes;
  77         u16 vlans_enabled;
  78         u32 flags;
  79         unsigned long last_nack;
  80         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
  81         u16 pf_qos;
  82         u16 tx_rate;
  83 };
  84
  85 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
  86 #define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
  87 #define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
  88 #define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
  89
  90 /* RX descriptor control thresholds.
  91  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  92  *           descriptors available in its onboard memory.
  93  *           Setting this to 0 disables RX descriptor prefetch.
  94  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  95  *           available in host memory.
  96  *           If PTHRESH is 0, this should also be 0.
  97  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  98  *           descriptors until either it has this many to write back, or the
  99  *           ITR timer expires.
 100  */
 101 #define IGB_RX_PTHRESH                     8
 102 #define IGB_RX_HTHRESH                     8
 103 #define IGB_TX_PTHRESH                     8
 104 #define IGB_TX_HTHRESH                     1
 105 #define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
 106                                              adapter->msix_entries) ? 1 : 4)
 107 #define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
 108                                              adapter->msix_entries) ? 1 : 16)
 109
 110 /* this is the size past which hardware will drop packets when setting LPE=0 */
 111 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 112
 113 /* Supported Rx Buffer Sizes */
 114 #define IGB_RXBUFFER_512   512
 115 #define IGB_RXBUFFER_16384 16384
 116 #define IGB_RX_HDR_LEN     IGB_RXBUFFER_512
 117
 118 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 119 #define IGB_TX_QUEUE_WAKE       16
 120 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 121 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 122
 123 #define AUTO_ALL_MODES            0
 124 #define IGB_EEPROM_APME         0x0400
 125
 126 #ifndef IGB_MASTER_SLAVE
 127 /* Switch to override PHY master/slave setting */
 128 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 129 #endif
 130
 131 #define IGB_MNG_VLAN_NONE -1
 132
 133 #define IGB_TX_FLAGS_CSUM               0x00000001
 134 #define IGB_TX_FLAGS_VLAN               0x00000002
 135 #define IGB_TX_FLAGS_TSO                0x00000004
 136 #define IGB_TX_FLAGS_IPV4               0x00000008
 137 #define IGB_TX_FLAGS_TSTAMP             0x00000010
 138 #define IGB_TX_FLAGS_MAPPED_AS_PAGE     0x00000020
 139 #define IGB_TX_FLAGS_VLAN_MASK          0xffff0000
 140 #define IGB_TX_FLAGS_VLAN_SHIFT 16
 141
 142 /* wrapper around a pointer to a socket buffer,
 143  * so a DMA handle can be stored along with the buffer */
 144 struct igb_tx_buffer {
 145         union e1000_adv_tx_desc *next_to_watch;
 146         unsigned long time_stamp;
 147         dma_addr_t dma;
 148         u32 length;
 149         u32 tx_flags;
 150         struct sk_buff *skb;
 151         unsigned int bytecount;
 152         u16 gso_segs;
 153         u8 mapped_as_page;
 154 };
 155
 156 struct igb_rx_buffer {
 157         struct sk_buff *skb;
 158         dma_addr_t dma;
 159         struct page *page;
 160         dma_addr_t page_dma;
 161         u32 page_offset;
 162 };
 163
 164 struct igb_tx_queue_stats {
 165         u64 packets;
 166         u64 bytes;
 167         u64 restart_queue;
 168         u64 restart_queue2;
 169 };
 170
 171 struct igb_rx_queue_stats {
 172         u64 packets;
 173         u64 bytes;
 174         u64 drops;
 175         u64 csum_err;
 176         u64 alloc_failed;
 177 };
 178
 179 struct igb_q_vector {
 180         struct igb_adapter *adapter; /* backlink */
 181         struct igb_ring *rx_ring;
 182         struct igb_ring *tx_ring;
 183         struct napi_struct napi;
 184
 185         u32 eims_value;
 186         u16 cpu;
 187         u16 tx_work_limit;
 188
 189         u16 itr_val;
 190         u8 set_itr;
 191         void __iomem *itr_register;
 192
 193         char name[IFNAMSIZ + 9];
 194 };
 195
 196 struct igb_ring {
 197         struct igb_q_vector *q_vector;  /* backlink to q_vector */
 198         struct net_device *netdev;      /* back pointer to net_device */
 199         struct device *dev;             /* device pointer for dma mapping */
 200         union {                         /* array of buffer info structs */
 201                 struct igb_tx_buffer *tx_buffer_info;
 202                 struct igb_rx_buffer *rx_buffer_info;
 203         };
 204         void *desc;                     /* descriptor ring memory */
 205         unsigned long flags;            /* ring specific flags */
 206         void __iomem *tail;             /* pointer to ring tail register */
 207
 208         u16 count;                      /* number of desc. in the ring */
 209         u8 queue_index;                 /* logical index of the ring*/
 210         u8 reg_idx;                     /* physical index of the ring */
 211         u32 size;                       /* length of desc. ring in bytes */
 212
 213         /* everything past this point are written often */
 214         u16 next_to_clean ____cacheline_aligned_in_smp;
 215         u16 next_to_use;
 216
 217         unsigned int total_bytes;
 218         unsigned int total_packets;
 219
 220         union {
 221                 /* TX */
 222                 struct {
 223                         struct igb_tx_queue_stats tx_stats;
 224                         struct u64_stats_sync tx_syncp;
 225                         struct u64_stats_sync tx_syncp2;
 226                         bool detect_tx_hung;
 227                 };
 228                 /* RX */
 229                 struct {
 230                         struct igb_rx_queue_stats rx_stats;
 231                         struct u64_stats_sync rx_syncp;
 232                 };
 233         };
 234         /* Items past this point are only used during ring alloc / free */
 235         dma_addr_t dma;                /* phys address of the ring */
 236 };
 237
 238 #define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
 239 #define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */
 240
 241 #define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */
 242
 243 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
 244
 245 #define IGB_RX_DESC(R, i)           \
 246         (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
 247 #define IGB_TX_DESC(R, i)           \
 248         (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
 249 #define IGB_TX_CTXTDESC(R, i)       \
 250         (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
 251
 252 /* igb_desc_unused - calculate if we have unused descriptors */
 253 static inline int igb_desc_unused(struct igb_ring *ring)
 254 {
 255         if (ring->next_to_clean > ring->next_to_use)
 256                 return ring->next_to_clean - ring->next_to_use - 1;
 257
 258         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 259 }
 260
 261 /* board specific private data structure */
 262 struct igb_adapter {
 263         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 264
 265         struct net_device *netdev;
 266
 267         unsigned long state;
 268         unsigned int flags;
 269
 270         unsigned int num_q_vectors;
 271         struct msix_entry *msix_entries;
 272
 273         /* Interrupt Throttle Rate */
 274         u32 rx_itr_setting;
 275         u32 tx_itr_setting;
 276         u16 tx_itr;
 277         u16 rx_itr;
 278
 279         /* TX */
 280         u16 tx_work_limit;
 281         u32 tx_timeout_count;
 282         int num_tx_queues;
 283         struct igb_ring *tx_ring[16];
 284
 285         /* RX */
 286         int num_rx_queues;
 287         struct igb_ring *rx_ring[16];
 288
 289         u32 max_frame_size;
 290         u32 min_frame_size;
 291
 292         struct timer_list watchdog_timer;
 293         struct timer_list phy_info_timer;
 294
 295         u16 mng_vlan_id;
 296         u32 bd_number;
 297         u32 wol;
 298         u32 en_mng_pt;
 299         u16 link_speed;
 300         u16 link_duplex;
 301
 302         struct work_struct reset_task;
 303         struct work_struct watchdog_task;
 304         bool fc_autoneg;
 305         u8  tx_timeout_factor;
 306         struct timer_list blink_timer;
 307         unsigned long led_status;
 308
 309         /* OS defined structs */
 310         struct pci_dev *pdev;
 311         struct cyclecounter cycles;
 312         struct timecounter clock;
 313         struct timecompare compare;
 314         struct hwtstamp_config hwtstamp_config;
 315
 316         spinlock_t stats64_lock;
 317         struct rtnl_link_stats64 stats64;
 318
 319         /* structs defined in e1000_hw.h */
 320         struct e1000_hw hw;
 321         struct e1000_hw_stats stats;
 322         struct e1000_phy_info phy_info;
 323         struct e1000_phy_stats phy_stats;
 324
 325         u32 test_icr;
 326         struct igb_ring test_tx_ring;
 327         struct igb_ring test_rx_ring;
 328
 329         int msg_enable;
 330
 331         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 332         u32 eims_enable_mask;
 333         u32 eims_other;
 334
 335         /* to not mess up cache alignment, always add to the bottom */
 336         u32 eeprom_wol;
 337
 338         u16 tx_ring_count;
 339         u16 rx_ring_count;
 340         unsigned int vfs_allocated_count;
 341         struct vf_data_storage *vf_data;
 342         int vf_rate_link_speed;
 343         u32 rss_queues;
 344         u32 wvbr;
 345 };
 346
 347 #define IGB_FLAG_HAS_MSI           (1 << 0)
 348 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 349 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 350 #define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
 351 #define IGB_FLAG_DMAC              (1 << 4)
 352
 353 /* DMA Coalescing defines */
 354 #define IGB_MIN_TXPBSIZE           20408
 355 #define IGB_TX_BUF_4096            4096
 356 #define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */
 357
 358 #define IGB_82576_TSYNC_SHIFT 19
 359 #define IGB_82580_TSYNC_SHIFT 24
 360 #define IGB_TS_HDR_LEN        16
 361 enum e1000_state_t {
 362         __IGB_TESTING,
 363         __IGB_RESETTING,
 364         __IGB_DOWN
 365 };
 366
 367 enum igb_boards {
 368         board_82575,
 369 };
 370
 371 extern char igb_driver_name[];
 372 extern char igb_driver_version[];
 373
 374 extern int igb_up(struct igb_adapter *);
 375 extern void igb_down(struct igb_adapter *);
 376 extern void igb_reinit_locked(struct igb_adapter *);
 377 extern void igb_reset(struct igb_adapter *);
 378 extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
 379 extern int igb_setup_tx_resources(struct igb_ring *);
 380 extern int igb_setup_rx_resources(struct igb_ring *);
 381 extern void igb_free_tx_resources(struct igb_ring *);
 382 extern void igb_free_rx_resources(struct igb_ring *);
 383 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 384 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 385 extern void igb_setup_tctl(struct igb_adapter *);
 386 extern void igb_setup_rctl(struct igb_adapter *);
 387 extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
 388 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
 389                                            struct igb_tx_buffer *);
 390 extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
 391 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
 392 extern bool igb_has_link(struct igb_adapter *adapter);
 393 extern void igb_set_ethtool_ops(struct net_device *);
 394 extern void igb_power_up_link(struct igb_adapter *);
 395
 396 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 397 {
 398         if (hw->phy.ops.reset)
 399                 return hw->phy.ops.reset(hw);
 400
 401         return 0;
 402 }
 403
 404 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 405 {
 406         if (hw->phy.ops.read_reg)
 407                 return hw->phy.ops.read_reg(hw, offset, data);
 408
 409         return 0;
 410 }
 411
 412 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 413 {
 414         if (hw->phy.ops.write_reg)
 415                 return hw->phy.ops.write_reg(hw, offset, data);
 416
 417         return 0;
 418 }
 419
 420 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 421 {
 422         if (hw->phy.ops.get_phy_info)
 423                 return hw->phy.ops.get_phy_info(hw);
 424
 425         return 0;
 426 }
 427
 428 #endif /* _IGB_H_ */