drivers/net/ethernet/intel/igb/igb.h

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 /* Linux PRO/1000 Ethernet Driver main header file */
  25
  26 #ifndef _IGB_H_
  27 #define _IGB_H_
  28
  29 #include "e1000_mac.h"
  30 #include "e1000_82575.h"
  31
  32 #include <linux/timecounter.h>
  33 #include <linux/net_tstamp.h>
  34 #include <linux/ptp_clock_kernel.h>
  35 #include <linux/bitops.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/pci.h>
  40 #include <linux/mdio.h>
  41
  42 struct igb_adapter;
  43
  44 #define E1000_PCS_CFG_IGN_SD    1
  45
  46 /* Interrupt defines */
  47 #define IGB_START_ITR           648 /* ~6000 ints/sec */
  48 #define IGB_4K_ITR              980
  49 #define IGB_20K_ITR             196
  50 #define IGB_70K_ITR             56
  51
  52 /* TX/RX descriptor defines */
  53 #define IGB_DEFAULT_TXD         256
  54 #define IGB_DEFAULT_TX_WORK     128
  55 #define IGB_MIN_TXD             80
  56 #define IGB_MAX_TXD             4096
  57
  58 #define IGB_DEFAULT_RXD         256
  59 #define IGB_MIN_RXD             80
  60 #define IGB_MAX_RXD             4096
  61
  62 #define IGB_DEFAULT_ITR         3 /* dynamic */
  63 #define IGB_MAX_ITR_USECS       10000
  64 #define IGB_MIN_ITR_USECS       10
  65 #define NON_Q_VECTORS           1
  66 #define MAX_Q_VECTORS           8
  67 #define MAX_MSIX_ENTRIES        10
  68
  69 /* Transmit and receive queues */
  70 #define IGB_MAX_RX_QUEUES       8
  71 #define IGB_MAX_RX_QUEUES_82575 4
  72 #define IGB_MAX_RX_QUEUES_I211  2
  73 #define IGB_MAX_TX_QUEUES       8
  74 #define IGB_MAX_VF_MC_ENTRIES   30
  75 #define IGB_MAX_VF_FUNCTIONS    8
  76 #define IGB_MAX_VFTA_ENTRIES    128
  77 #define IGB_82576_VF_DEV_ID     0x10CA
  78 #define IGB_I350_VF_DEV_ID      0x1520
  79
  80 /* NVM version defines */
  81 #define IGB_MAJOR_MASK          0xF000
  82 #define IGB_MINOR_MASK          0x0FF0
  83 #define IGB_BUILD_MASK          0x000F
  84 #define IGB_COMB_VER_MASK       0x00FF
  85 #define IGB_MAJOR_SHIFT         12
  86 #define IGB_MINOR_SHIFT         4
  87 #define IGB_COMB_VER_SHFT       8
  88 #define IGB_NVM_VER_INVALID     0xFFFF
  89 #define IGB_ETRACK_SHIFT        16
  90 #define NVM_ETRACK_WORD         0x0042
  91 #define NVM_COMB_VER_OFF        0x0083
  92 #define NVM_COMB_VER_PTR        0x003d
  93
  94 struct vf_data_storage {
  95         unsigned char vf_mac_addresses[ETH_ALEN];
  96         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  97         u16 num_vf_mc_hashes;
  98         u16 vlans_enabled;
  99         u32 flags;
 100         unsigned long last_nack;
 101         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 102         u16 pf_qos;
 103         u16 tx_rate;
 104         bool spoofchk_enabled;
 105 };
 106
 107 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
 108 #define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
 109 #define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
 110 #define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
 111
 112 /* RX descriptor control thresholds.
 113  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 114  *           descriptors available in its onboard memory.
 115  *           Setting this to 0 disables RX descriptor prefetch.
 116  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 117  *           available in host memory.
 118  *           If PTHRESH is 0, this should also be 0.
 119  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 120  *           descriptors until either it has this many to write back, or the
 121  *           ITR timer expires.
 122  */
 123 #define IGB_RX_PTHRESH  ((hw->mac.type == e1000_i354) ? 12 : 8)
 124 #define IGB_RX_HTHRESH  8
 125 #define IGB_TX_PTHRESH  ((hw->mac.type == e1000_i354) ? 20 : 8)
 126 #define IGB_TX_HTHRESH  1
 127 #define IGB_RX_WTHRESH  ((hw->mac.type == e1000_82576 && \
 128                           (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
 129 #define IGB_TX_WTHRESH  ((hw->mac.type == e1000_82576 && \
 130                           (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
 131
 132 /* this is the size past which hardware will drop packets when setting LPE=0 */
 133 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 134
 135 /* Supported Rx Buffer Sizes */
 136 #define IGB_RXBUFFER_256        256
 137 #define IGB_RXBUFFER_2048       2048
 138 #define IGB_RX_HDR_LEN          IGB_RXBUFFER_256
 139 #define IGB_RX_BUFSZ            IGB_RXBUFFER_2048
 140
 141 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 142 #define IGB_RX_BUFFER_WRITE     16 /* Must be power of 2 */
 143
 144 #define AUTO_ALL_MODES          0
 145 #define IGB_EEPROM_APME         0x0400
 146
 147 #ifndef IGB_MASTER_SLAVE
 148 /* Switch to override PHY master/slave setting */
 149 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 150 #endif
 151
 152 #define IGB_MNG_VLAN_NONE       -1
 153
 154 enum igb_tx_flags {
 155         /* cmd_type flags */
 156         IGB_TX_FLAGS_VLAN       = 0x01,
 157         IGB_TX_FLAGS_TSO        = 0x02,
 158         IGB_TX_FLAGS_TSTAMP     = 0x04,
 159
 160         /* olinfo flags */
 161         IGB_TX_FLAGS_IPV4       = 0x10,
 162         IGB_TX_FLAGS_CSUM       = 0x20,
 163 };
 164
 165 /* VLAN info */
 166 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
 167 #define IGB_TX_FLAGS_VLAN_SHIFT 16
 168
 169 /* The largest size we can write to the descriptor is 65535.  In order to
 170  * maintain a power of two alignment we have to limit ourselves to 32K.
 171  */
 172 #define IGB_MAX_TXD_PWR 15
 173 #define IGB_MAX_DATA_PER_TXD    (1 << IGB_MAX_TXD_PWR)
 174
 175 /* Tx Descriptors needed, worst case */
 176 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
 177 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
 178
 179 /* EEPROM byte offsets */
 180 #define IGB_SFF_8472_SWAP               0x5C
 181 #define IGB_SFF_8472_COMP               0x5E
 182
 183 /* Bitmasks */
 184 #define IGB_SFF_ADDRESSING_MODE         0x4
 185 #define IGB_SFF_8472_UNSUP              0x00
 186
 187 /* wrapper around a pointer to a socket buffer,
 188  * so a DMA handle can be stored along with the buffer
 189  */
 190 struct igb_tx_buffer {
 191         union e1000_adv_tx_desc *next_to_watch;
 192         unsigned long time_stamp;
 193         struct sk_buff *skb;
 194         unsigned int bytecount;
 195         u16 gso_segs;
 196         __be16 protocol;
 197
 198         DEFINE_DMA_UNMAP_ADDR(dma);
 199         DEFINE_DMA_UNMAP_LEN(len);
 200         u32 tx_flags;
 201 };
 202
 203 struct igb_rx_buffer {
 204         dma_addr_t dma;
 205         struct page *page;
 206         unsigned int page_offset;
 207 };
 208
 209 struct igb_tx_queue_stats {
 210         u64 packets;
 211         u64 bytes;
 212         u64 restart_queue;
 213         u64 restart_queue2;
 214 };
 215
 216 struct igb_rx_queue_stats {
 217         u64 packets;
 218         u64 bytes;
 219         u64 drops;
 220         u64 csum_err;
 221         u64 alloc_failed;
 222 };
 223
 224 struct igb_ring_container {
 225         struct igb_ring *ring;          /* pointer to linked list of rings */
 226         unsigned int total_bytes;       /* total bytes processed this int */
 227         unsigned int total_packets;     /* total packets processed this int */
 228         u16 work_limit;                 /* total work allowed per interrupt */
 229         u8 count;                       /* total number of rings in vector */
 230         u8 itr;                         /* current ITR setting for ring */
 231 };
 232
 233 struct igb_ring {
 234         struct igb_q_vector *q_vector;  /* backlink to q_vector */
 235         struct net_device *netdev;      /* back pointer to net_device */
 236         struct device *dev;             /* device pointer for dma mapping */
 237         union {                         /* array of buffer info structs */
 238                 struct igb_tx_buffer *tx_buffer_info;
 239                 struct igb_rx_buffer *rx_buffer_info;
 240         };
 241         void *desc;                     /* descriptor ring memory */
 242         unsigned long flags;            /* ring specific flags */
 243         void __iomem *tail;             /* pointer to ring tail register */
 244         dma_addr_t dma;                 /* phys address of the ring */
 245         unsigned int  size;             /* length of desc. ring in bytes */
 246
 247         u16 count;                      /* number of desc. in the ring */
 248         u8 queue_index;                 /* logical index of the ring*/
 249         u8 reg_idx;                     /* physical index of the ring */
 250
 251         /* everything past this point are written often */
 252         u16 next_to_clean;
 253         u16 next_to_use;
 254         u16 next_to_alloc;
 255
 256         union {
 257                 /* TX */
 258                 struct {
 259                         struct igb_tx_queue_stats tx_stats;
 260                         struct u64_stats_sync tx_syncp;
 261                         struct u64_stats_sync tx_syncp2;
 262                 };
 263                 /* RX */
 264                 struct {
 265                         struct sk_buff *skb;
 266                         struct igb_rx_queue_stats rx_stats;
 267                         struct u64_stats_sync rx_syncp;
 268                 };
 269         };
 270 } ____cacheline_internodealigned_in_smp;
 271
 272 struct igb_q_vector {
 273         struct igb_adapter *adapter;    /* backlink */
 274         int cpu;                        /* CPU for DCA */
 275         u32 eims_value;                 /* EIMS mask value */
 276
 277         u16 itr_val;
 278         u8 set_itr;
 279         void __iomem *itr_register;
 280
 281         struct igb_ring_container rx, tx;
 282
 283         struct napi_struct napi;
 284         struct rcu_head rcu;    /* to avoid race with update stats on free */
 285         char name[IFNAMSIZ + 9];
 286
 287         /* for dynamic allocation of rings associated with this q_vector */
 288         struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
 289 };
 290
 291 enum e1000_ring_flags_t {
 292         IGB_RING_FLAG_RX_SCTP_CSUM,
 293         IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
 294         IGB_RING_FLAG_TX_CTX_IDX,
 295         IGB_RING_FLAG_TX_DETECT_HANG
 296 };
 297
 298 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
 299
 300 #define IGB_RX_DESC(R, i)       \
 301         (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
 302 #define IGB_TX_DESC(R, i)       \
 303         (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
 304 #define IGB_TX_CTXTDESC(R, i)   \
 305         (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
 306
 307 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
 308 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
 309                                       const u32 stat_err_bits)
 310 {
 311         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 312 }
 313
 314 /* igb_desc_unused - calculate if we have unused descriptors */
 315 static inline int igb_desc_unused(struct igb_ring *ring)
 316 {
 317         if (ring->next_to_clean > ring->next_to_use)
 318                 return ring->next_to_clean - ring->next_to_use - 1;
 319
 320         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 321 }
 322
 323 #ifdef CONFIG_IGB_HWMON
 324
 325 #define IGB_HWMON_TYPE_LOC      0
 326 #define IGB_HWMON_TYPE_TEMP     1
 327 #define IGB_HWMON_TYPE_CAUTION  2
 328 #define IGB_HWMON_TYPE_MAX      3
 329
 330 struct hwmon_attr {
 331         struct device_attribute dev_attr;
 332         struct e1000_hw *hw;
 333         struct e1000_thermal_diode_data *sensor;
 334         char name[12];
 335         };
 336
 337 struct hwmon_buff {
 338         struct attribute_group group;
 339         const struct attribute_group *groups[2];
 340         struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
 341         struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
 342         unsigned int n_hwmon;
 343         };
 344 #endif
 345
 346 #define IGB_N_EXTTS     2
 347 #define IGB_N_PEROUT    2
 348 #define IGB_N_SDP       4
 349 #define IGB_RETA_SIZE   128
 350
 351 /* board specific private data structure */
 352 struct igb_adapter {
 353         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 354
 355         struct net_device *netdev;
 356
 357         unsigned long state;
 358         unsigned int flags;
 359
 360         unsigned int num_q_vectors;
 361         struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
 362
 363         /* Interrupt Throttle Rate */
 364         u32 rx_itr_setting;
 365         u32 tx_itr_setting;
 366         u16 tx_itr;
 367         u16 rx_itr;
 368
 369         /* TX */
 370         u16 tx_work_limit;
 371         u32 tx_timeout_count;
 372         int num_tx_queues;
 373         struct igb_ring *tx_ring[16];
 374
 375         /* RX */
 376         int num_rx_queues;
 377         struct igb_ring *rx_ring[16];
 378
 379         u32 max_frame_size;
 380         u32 min_frame_size;
 381
 382         struct timer_list watchdog_timer;
 383         struct timer_list phy_info_timer;
 384
 385         u16 mng_vlan_id;
 386         u32 bd_number;
 387         u32 wol;
 388         u32 en_mng_pt;
 389         u16 link_speed;
 390         u16 link_duplex;
 391
 392         u8 __iomem *io_addr; /* Mainly for iounmap use */
 393
 394         struct work_struct reset_task;
 395         struct work_struct watchdog_task;
 396         bool fc_autoneg;
 397         u8  tx_timeout_factor;
 398         struct timer_list blink_timer;
 399         unsigned long led_status;
 400
 401         /* OS defined structs */
 402         struct pci_dev *pdev;
 403
 404         spinlock_t stats64_lock;
 405         struct rtnl_link_stats64 stats64;
 406
 407         /* structs defined in e1000_hw.h */
 408         struct e1000_hw hw;
 409         struct e1000_hw_stats stats;
 410         struct e1000_phy_info phy_info;
 411
 412         u32 test_icr;
 413         struct igb_ring test_tx_ring;
 414         struct igb_ring test_rx_ring;
 415
 416         int msg_enable;
 417
 418         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 419         u32 eims_enable_mask;
 420         u32 eims_other;
 421
 422         /* to not mess up cache alignment, always add to the bottom */
 423         u16 tx_ring_count;
 424         u16 rx_ring_count;
 425         unsigned int vfs_allocated_count;
 426         struct vf_data_storage *vf_data;
 427         int vf_rate_link_speed;
 428         u32 rss_queues;
 429         u32 wvbr;
 430         u32 *shadow_vfta;
 431
 432         struct ptp_clock *ptp_clock;
 433         struct ptp_clock_info ptp_caps;
 434         struct delayed_work ptp_overflow_work;
 435         struct work_struct ptp_tx_work;
 436         struct sk_buff *ptp_tx_skb;
 437         struct hwtstamp_config tstamp_config;
 438         unsigned long ptp_tx_start;
 439         unsigned long last_rx_ptp_check;
 440         unsigned long last_rx_timestamp;
 441         spinlock_t tmreg_lock;
 442         struct cyclecounter cc;
 443         struct timecounter tc;
 444         u32 tx_hwtstamp_timeouts;
 445         u32 rx_hwtstamp_cleared;
 446
 447         struct ptp_pin_desc sdp_config[IGB_N_SDP];
 448         struct {
 449                 struct timespec64 start;
 450                 struct timespec64 period;
 451         } perout[IGB_N_PEROUT];
 452
 453         char fw_version[32];
 454 #ifdef CONFIG_IGB_HWMON
 455         struct hwmon_buff *igb_hwmon_buff;
 456         bool ets;
 457 #endif
 458         struct i2c_algo_bit_data i2c_algo;
 459         struct i2c_adapter i2c_adap;
 460         struct i2c_client *i2c_client;
 461         u32 rss_indir_tbl_init;
 462         u8 rss_indir_tbl[IGB_RETA_SIZE];
 463
 464         unsigned long link_check_timeout;
 465         int copper_tries;
 466         struct e1000_info ei;
 467         u16 eee_advert;
 468 };
 469
 470 #define IGB_FLAG_HAS_MSI                (1 << 0)
 471 #define IGB_FLAG_DCA_ENABLED            (1 << 1)
 472 #define IGB_FLAG_QUAD_PORT_A            (1 << 2)
 473 #define IGB_FLAG_QUEUE_PAIRS            (1 << 3)
 474 #define IGB_FLAG_DMAC                   (1 << 4)
 475 #define IGB_FLAG_PTP                    (1 << 5)
 476 #define IGB_FLAG_RSS_FIELD_IPV4_UDP     (1 << 6)
 477 #define IGB_FLAG_RSS_FIELD_IPV6_UDP     (1 << 7)
 478 #define IGB_FLAG_WOL_SUPPORTED          (1 << 8)
 479 #define IGB_FLAG_NEED_LINK_UPDATE       (1 << 9)
 480 #define IGB_FLAG_MEDIA_RESET            (1 << 10)
 481 #define IGB_FLAG_MAS_CAPABLE            (1 << 11)
 482 #define IGB_FLAG_MAS_ENABLE             (1 << 12)
 483 #define IGB_FLAG_HAS_MSIX               (1 << 13)
 484 #define IGB_FLAG_EEE                    (1 << 14)
 485
 486 /* Media Auto Sense */
 487 #define IGB_MAS_ENABLE_0                0X0001
 488 #define IGB_MAS_ENABLE_1                0X0002
 489 #define IGB_MAS_ENABLE_2                0X0004
 490 #define IGB_MAS_ENABLE_3                0X0008
 491
 492 /* DMA Coalescing defines */
 493 #define IGB_MIN_TXPBSIZE        20408
 494 #define IGB_TX_BUF_4096         4096
 495 #define IGB_DMCTLX_DCFLUSH_DIS  0x80000000  /* Disable DMA Coal Flush */
 496
 497 #define IGB_82576_TSYNC_SHIFT   19
 498 #define IGB_TS_HDR_LEN          16
 499 enum e1000_state_t {
 500         __IGB_TESTING,
 501         __IGB_RESETTING,
 502         __IGB_DOWN,
 503         __IGB_PTP_TX_IN_PROGRESS,
 504 };
 505
 506 enum igb_boards {
 507         board_82575,
 508 };
 509
 510 extern char igb_driver_name[];
 511 extern char igb_driver_version[];
 512
 513 int igb_up(struct igb_adapter *);
 514 void igb_down(struct igb_adapter *);
 515 void igb_reinit_locked(struct igb_adapter *);
 516 void igb_reset(struct igb_adapter *);
 517 int igb_reinit_queues(struct igb_adapter *);
 518 void igb_write_rss_indir_tbl(struct igb_adapter *);
 519 int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
 520 int igb_setup_tx_resources(struct igb_ring *);
 521 int igb_setup_rx_resources(struct igb_ring *);
 522 void igb_free_tx_resources(struct igb_ring *);
 523 void igb_free_rx_resources(struct igb_ring *);
 524 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 525 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 526 void igb_setup_tctl(struct igb_adapter *);
 527 void igb_setup_rctl(struct igb_adapter *);
 528 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
 529 void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *);
 530 void igb_alloc_rx_buffers(struct igb_ring *, u16);
 531 void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
 532 bool igb_has_link(struct igb_adapter *adapter);
 533 void igb_set_ethtool_ops(struct net_device *);
 534 void igb_power_up_link(struct igb_adapter *);
 535 void igb_set_fw_version(struct igb_adapter *);
 536 void igb_ptp_init(struct igb_adapter *adapter);
 537 void igb_ptp_stop(struct igb_adapter *adapter);
 538 void igb_ptp_reset(struct igb_adapter *adapter);
 539 void igb_ptp_rx_hang(struct igb_adapter *adapter);
 540 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
 541 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va,
 542                          struct sk_buff *skb);
 543 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
 544 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
 545 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
 546 #ifdef CONFIG_IGB_HWMON
 547 void igb_sysfs_exit(struct igb_adapter *adapter);
 548 int igb_sysfs_init(struct igb_adapter *adapter);
 549 #endif
 550 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 551 {
 552         if (hw->phy.ops.reset)
 553                 return hw->phy.ops.reset(hw);
 554
 555         return 0;
 556 }
 557
 558 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 559 {
 560         if (hw->phy.ops.read_reg)
 561                 return hw->phy.ops.read_reg(hw, offset, data);
 562
 563         return 0;
 564 }
 565
 566 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 567 {
 568         if (hw->phy.ops.write_reg)
 569                 return hw->phy.ops.write_reg(hw, offset, data);
 570
 571         return 0;
 572 }
 573
 574 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 575 {
 576         if (hw->phy.ops.get_phy_info)
 577                 return hw->phy.ops.get_phy_info(hw);
 578
 579         return 0;
 580 }
 581
 582 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
 583 {
 584         return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
 585 }
 586
 587 #endif /* _IGB_H_ */