1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 /* Linux PRO/1000 Ethernet Driver main header file */
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
37 #include <linux/clocksource.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/bitops.h>
41 #include <linux/if_vlan.h>
45 /* Interrupt defines */
46 #define IGB_START_ITR 648 /* ~6000 ints/sec */
47 #define IGB_4K_ITR 980
48 #define IGB_20K_ITR 196
49 #define IGB_70K_ITR 56
51 /* TX/RX descriptor defines */
52 #define IGB_DEFAULT_TXD 256
53 #define IGB_DEFAULT_TX_WORK 128
54 #define IGB_MIN_TXD 80
55 #define IGB_MAX_TXD 4096
57 #define IGB_DEFAULT_RXD 256
58 #define IGB_MIN_RXD 80
59 #define IGB_MAX_RXD 4096
61 #define IGB_DEFAULT_ITR 3 /* dynamic */
62 #define IGB_MAX_ITR_USECS 10000
63 #define IGB_MIN_ITR_USECS 10
64 #define NON_Q_VECTORS 1
65 #define MAX_Q_VECTORS 8
67 /* Transmit and receive queues */
68 #define IGB_MAX_RX_QUEUES ((adapter->vfs_allocated_count ? 2 : \
69 (hw->mac.type > e1000_82575 ? 8 : 4)))
70 #define IGB_MAX_RX_QUEUES_I210 4
71 #define IGB_MAX_RX_QUEUES_I211 2
72 #define IGB_MAX_TX_QUEUES 16
73 #define IGB_MAX_TX_QUEUES_I210 4
74 #define IGB_MAX_TX_QUEUES_I211 2
75 #define IGB_MAX_VF_MC_ENTRIES 30
76 #define IGB_MAX_VF_FUNCTIONS 8
77 #define IGB_MAX_VFTA_ENTRIES 128
78 #define IGB_82576_VF_DEV_ID 0x10CA
79 #define IGB_I350_VF_DEV_ID 0x1520
81 struct vf_data_storage
{
82 unsigned char vf_mac_addresses
[ETH_ALEN
];
83 u16 vf_mc_hashes
[IGB_MAX_VF_MC_ENTRIES
];
87 unsigned long last_nack
;
88 u16 pf_vlan
; /* When set, guest VLAN config not allowed. */
91 struct pci_dev
*vfdev
;
94 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
95 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
96 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
97 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
99 /* RX descriptor control thresholds.
100 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
101 * descriptors available in its onboard memory.
102 * Setting this to 0 disables RX descriptor prefetch.
103 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
104 * available in host memory.
105 * If PTHRESH is 0, this should also be 0.
106 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
107 * descriptors until either it has this many to write back, or the
110 #define IGB_RX_PTHRESH 8
111 #define IGB_RX_HTHRESH 8
112 #define IGB_TX_PTHRESH 8
113 #define IGB_TX_HTHRESH 1
114 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
115 adapter->msix_entries) ? 1 : 4)
116 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
117 adapter->msix_entries) ? 1 : 16)
119 /* this is the size past which hardware will drop packets when setting LPE=0 */
120 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
122 /* Supported Rx Buffer Sizes */
123 #define IGB_RXBUFFER_512 512
124 #define IGB_RXBUFFER_16384 16384
125 #define IGB_RX_HDR_LEN IGB_RXBUFFER_512
127 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
128 #define IGB_TX_QUEUE_WAKE 16
129 /* How many Rx Buffers do we bundle into one write to the hardware ? */
130 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
132 #define AUTO_ALL_MODES 0
133 #define IGB_EEPROM_APME 0x0400
135 #ifndef IGB_MASTER_SLAVE
136 /* Switch to override PHY master/slave setting */
137 #define IGB_MASTER_SLAVE e1000_ms_hw_default
140 #define IGB_MNG_VLAN_NONE -1
142 #define IGB_TX_FLAGS_CSUM 0x00000001
143 #define IGB_TX_FLAGS_VLAN 0x00000002
144 #define IGB_TX_FLAGS_TSO 0x00000004
145 #define IGB_TX_FLAGS_IPV4 0x00000008
146 #define IGB_TX_FLAGS_TSTAMP 0x00000010
147 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
148 #define IGB_TX_FLAGS_VLAN_SHIFT 16
150 /* wrapper around a pointer to a socket buffer,
151 * so a DMA handle can be stored along with the buffer */
152 struct igb_tx_buffer
{
153 union e1000_adv_tx_desc
*next_to_watch
;
154 unsigned long time_stamp
;
156 unsigned int bytecount
;
164 struct igb_rx_buffer
{
172 struct igb_tx_queue_stats
{
179 struct igb_rx_queue_stats
{
187 struct igb_ring_container
{
188 struct igb_ring
*ring
; /* pointer to linked list of rings */
189 unsigned int total_bytes
; /* total bytes processed this int */
190 unsigned int total_packets
; /* total packets processed this int */
191 u16 work_limit
; /* total work allowed per interrupt */
192 u8 count
; /* total number of rings in vector */
193 u8 itr
; /* current ITR setting for ring */
196 struct igb_q_vector
{
197 struct igb_adapter
*adapter
; /* backlink */
198 int cpu
; /* CPU for DCA */
199 u32 eims_value
; /* EIMS mask value */
201 struct igb_ring_container rx
, tx
;
203 struct napi_struct napi
;
208 void __iomem
*itr_register
;
210 char name
[IFNAMSIZ
+ 9];
214 struct igb_q_vector
*q_vector
; /* backlink to q_vector */
215 struct net_device
*netdev
; /* back pointer to net_device */
216 struct device
*dev
; /* device pointer for dma mapping */
217 union { /* array of buffer info structs */
218 struct igb_tx_buffer
*tx_buffer_info
;
219 struct igb_rx_buffer
*rx_buffer_info
;
221 void *desc
; /* descriptor ring memory */
222 unsigned long flags
; /* ring specific flags */
223 void __iomem
*tail
; /* pointer to ring tail register */
225 u16 count
; /* number of desc. in the ring */
226 u8 queue_index
; /* logical index of the ring*/
227 u8 reg_idx
; /* physical index of the ring */
228 u32 size
; /* length of desc. ring in bytes */
230 /* everything past this point are written often */
231 u16 next_to_clean ____cacheline_aligned_in_smp
;
237 struct igb_tx_queue_stats tx_stats
;
238 struct u64_stats_sync tx_syncp
;
239 struct u64_stats_sync tx_syncp2
;
243 struct igb_rx_queue_stats rx_stats
;
244 struct u64_stats_sync rx_syncp
;
247 /* Items past this point are only used during ring alloc / free */
248 dma_addr_t dma
; /* phys address of the ring */
249 int numa_node
; /* node to alloc ring memory on */
252 enum e1000_ring_flags_t
{
253 IGB_RING_FLAG_RX_SCTP_CSUM
,
254 IGB_RING_FLAG_RX_LB_VLAN_BSWAP
,
255 IGB_RING_FLAG_TX_CTX_IDX
,
256 IGB_RING_FLAG_TX_DETECT_HANG
259 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
261 #define IGB_RX_DESC(R, i) \
262 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
263 #define IGB_TX_DESC(R, i) \
264 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
265 #define IGB_TX_CTXTDESC(R, i) \
266 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
268 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
269 static inline __le32
igb_test_staterr(union e1000_adv_rx_desc
*rx_desc
,
270 const u32 stat_err_bits
)
272 return rx_desc
->wb
.upper
.status_error
& cpu_to_le32(stat_err_bits
);
275 /* igb_desc_unused - calculate if we have unused descriptors */
276 static inline int igb_desc_unused(struct igb_ring
*ring
)
278 if (ring
->next_to_clean
> ring
->next_to_use
)
279 return ring
->next_to_clean
- ring
->next_to_use
- 1;
281 return ring
->count
+ ring
->next_to_clean
- ring
->next_to_use
- 1;
284 /* board specific private data structure */
286 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
288 struct net_device
*netdev
;
293 unsigned int num_q_vectors
;
294 struct msix_entry
*msix_entries
;
296 /* Interrupt Throttle Rate */
304 u32 tx_timeout_count
;
306 struct igb_ring
*tx_ring
[16];
310 struct igb_ring
*rx_ring
[16];
315 struct timer_list watchdog_timer
;
316 struct timer_list phy_info_timer
;
325 struct work_struct reset_task
;
326 struct work_struct watchdog_task
;
328 u8 tx_timeout_factor
;
329 struct timer_list blink_timer
;
330 unsigned long led_status
;
332 /* OS defined structs */
333 struct pci_dev
*pdev
;
334 struct hwtstamp_config hwtstamp_config
;
336 spinlock_t stats64_lock
;
337 struct rtnl_link_stats64 stats64
;
339 /* structs defined in e1000_hw.h */
341 struct e1000_hw_stats stats
;
342 struct e1000_phy_info phy_info
;
343 struct e1000_phy_stats phy_stats
;
346 struct igb_ring test_tx_ring
;
347 struct igb_ring test_rx_ring
;
351 struct igb_q_vector
*q_vector
[MAX_Q_VECTORS
];
352 u32 eims_enable_mask
;
355 /* to not mess up cache alignment, always add to the bottom */
360 unsigned int vfs_allocated_count
;
361 struct vf_data_storage
*vf_data
;
362 int vf_rate_link_speed
;
368 struct ptp_clock
*ptp_clock
;
369 struct ptp_clock_info caps
;
370 struct delayed_work overflow_work
;
371 spinlock_t tmreg_lock
;
372 struct cyclecounter cc
;
373 struct timecounter tc
;
376 #define IGB_FLAG_HAS_MSI (1 << 0)
377 #define IGB_FLAG_DCA_ENABLED (1 << 1)
378 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
379 #define IGB_FLAG_QUEUE_PAIRS (1 << 3)
380 #define IGB_FLAG_DMAC (1 << 4)
382 /* DMA Coalescing defines */
383 #define IGB_MIN_TXPBSIZE 20408
384 #define IGB_TX_BUF_4096 4096
385 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
387 #define IGB_82576_TSYNC_SHIFT 19
388 #define IGB_TS_HDR_LEN 16
399 extern char igb_driver_name
[];
400 extern char igb_driver_version
[];
402 extern int igb_up(struct igb_adapter
*);
403 extern void igb_down(struct igb_adapter
*);
404 extern void igb_reinit_locked(struct igb_adapter
*);
405 extern void igb_reset(struct igb_adapter
*);
406 extern int igb_set_spd_dplx(struct igb_adapter
*, u32
, u8
);
407 extern int igb_setup_tx_resources(struct igb_ring
*);
408 extern int igb_setup_rx_resources(struct igb_ring
*);
409 extern void igb_free_tx_resources(struct igb_ring
*);
410 extern void igb_free_rx_resources(struct igb_ring
*);
411 extern void igb_configure_tx_ring(struct igb_adapter
*, struct igb_ring
*);
412 extern void igb_configure_rx_ring(struct igb_adapter
*, struct igb_ring
*);
413 extern void igb_setup_tctl(struct igb_adapter
*);
414 extern void igb_setup_rctl(struct igb_adapter
*);
415 extern netdev_tx_t
igb_xmit_frame_ring(struct sk_buff
*, struct igb_ring
*);
416 extern void igb_unmap_and_free_tx_resource(struct igb_ring
*,
417 struct igb_tx_buffer
*);
418 extern void igb_alloc_rx_buffers(struct igb_ring
*, u16
);
419 extern void igb_update_stats(struct igb_adapter
*, struct rtnl_link_stats64
*);
420 extern bool igb_has_link(struct igb_adapter
*adapter
);
421 extern void igb_set_ethtool_ops(struct net_device
*);
422 extern void igb_power_up_link(struct igb_adapter
*);
423 #ifdef CONFIG_IGB_PTP
424 extern void igb_ptp_init(struct igb_adapter
*adapter
);
425 extern void igb_ptp_remove(struct igb_adapter
*adapter
);
427 extern void igb_systim_to_hwtstamp(struct igb_adapter
*adapter
,
428 struct skb_shared_hwtstamps
*hwtstamps
,
432 static inline s32
igb_reset_phy(struct e1000_hw
*hw
)
434 if (hw
->phy
.ops
.reset
)
435 return hw
->phy
.ops
.reset(hw
);
440 static inline s32
igb_read_phy_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
442 if (hw
->phy
.ops
.read_reg
)
443 return hw
->phy
.ops
.read_reg(hw
, offset
, data
);
448 static inline s32
igb_write_phy_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
450 if (hw
->phy
.ops
.write_reg
)
451 return hw
->phy
.ops
.write_reg(hw
, offset
, data
);
456 static inline s32
igb_get_phy_info(struct e1000_hw
*hw
)
458 if (hw
->phy
.ops
.get_phy_info
)
459 return hw
->phy
.ops
.get_phy_info(hw
);
464 static inline struct netdev_queue
*txring_txq(const struct igb_ring
*tx_ring
)
466 return netdev_get_tx_queue(tx_ring
->netdev
, tx_ring
->queue_index
);