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igb: add flags to set eee advertisement mode
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 /* ethtool support for igb */
25
26 #include <linux/vmalloc.h>
27 #include <linux/netdevice.h>
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/if_ether.h>
32 #include <linux/ethtool.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/highmem.h>
37 #include <linux/mdio.h>
38
39 #include "igb.h"
40
41 struct igb_stats {
42 char stat_string[ETH_GSTRING_LEN];
43 int sizeof_stat;
44 int stat_offset;
45 };
46
47 #define IGB_STAT(_name, _stat) { \
48 .stat_string = _name, \
49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
50 .stat_offset = offsetof(struct igb_adapter, _stat) \
51 }
52 static const struct igb_stats igb_gstrings_stats[] = {
53 IGB_STAT("rx_packets", stats.gprc),
54 IGB_STAT("tx_packets", stats.gptc),
55 IGB_STAT("rx_bytes", stats.gorc),
56 IGB_STAT("tx_bytes", stats.gotc),
57 IGB_STAT("rx_broadcast", stats.bprc),
58 IGB_STAT("tx_broadcast", stats.bptc),
59 IGB_STAT("rx_multicast", stats.mprc),
60 IGB_STAT("tx_multicast", stats.mptc),
61 IGB_STAT("multicast", stats.mprc),
62 IGB_STAT("collisions", stats.colc),
63 IGB_STAT("rx_crc_errors", stats.crcerrs),
64 IGB_STAT("rx_no_buffer_count", stats.rnbc),
65 IGB_STAT("rx_missed_errors", stats.mpc),
66 IGB_STAT("tx_aborted_errors", stats.ecol),
67 IGB_STAT("tx_carrier_errors", stats.tncrs),
68 IGB_STAT("tx_window_errors", stats.latecol),
69 IGB_STAT("tx_abort_late_coll", stats.latecol),
70 IGB_STAT("tx_deferred_ok", stats.dc),
71 IGB_STAT("tx_single_coll_ok", stats.scc),
72 IGB_STAT("tx_multi_coll_ok", stats.mcc),
73 IGB_STAT("tx_timeout_count", tx_timeout_count),
74 IGB_STAT("rx_long_length_errors", stats.roc),
75 IGB_STAT("rx_short_length_errors", stats.ruc),
76 IGB_STAT("rx_align_errors", stats.algnerrc),
77 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
79 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
81 IGB_STAT("tx_flow_control_xon", stats.xontxc),
82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
83 IGB_STAT("rx_long_byte_count", stats.gorc),
84 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
85 IGB_STAT("tx_smbus", stats.mgptc),
86 IGB_STAT("rx_smbus", stats.mgprc),
87 IGB_STAT("dropped_smbus", stats.mgpdc),
88 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
89 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
90 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
91 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
92 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
93 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
94 };
95
96 #define IGB_NETDEV_STAT(_net_stat) { \
97 .stat_string = __stringify(_net_stat), \
98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
100 }
101 static const struct igb_stats igb_gstrings_net_stats[] = {
102 IGB_NETDEV_STAT(rx_errors),
103 IGB_NETDEV_STAT(tx_errors),
104 IGB_NETDEV_STAT(tx_dropped),
105 IGB_NETDEV_STAT(rx_length_errors),
106 IGB_NETDEV_STAT(rx_over_errors),
107 IGB_NETDEV_STAT(rx_frame_errors),
108 IGB_NETDEV_STAT(rx_fifo_errors),
109 IGB_NETDEV_STAT(tx_fifo_errors),
110 IGB_NETDEV_STAT(tx_heartbeat_errors)
111 };
112
113 #define IGB_GLOBAL_STATS_LEN \
114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
115 #define IGB_NETDEV_STATS_LEN \
116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
117 #define IGB_RX_QUEUE_STATS_LEN \
118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
119
120 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
121
122 #define IGB_QUEUE_STATS_LEN \
123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
124 IGB_RX_QUEUE_STATS_LEN) + \
125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
126 IGB_TX_QUEUE_STATS_LEN))
127 #define IGB_STATS_LEN \
128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
129
130 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
131 "Register test (offline)", "Eeprom test (offline)",
132 "Interrupt test (offline)", "Loopback test (offline)",
133 "Link test (on/offline)"
134 };
135 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
136
137 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
138 {
139 struct igb_adapter *adapter = netdev_priv(netdev);
140 struct e1000_hw *hw = &adapter->hw;
141 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
142 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
143 u32 status;
144 u32 speed;
145
146 status = rd32(E1000_STATUS);
147 if (hw->phy.media_type == e1000_media_type_copper) {
148
149 ecmd->supported = (SUPPORTED_10baseT_Half |
150 SUPPORTED_10baseT_Full |
151 SUPPORTED_100baseT_Half |
152 SUPPORTED_100baseT_Full |
153 SUPPORTED_1000baseT_Full|
154 SUPPORTED_Autoneg |
155 SUPPORTED_TP |
156 SUPPORTED_Pause);
157 ecmd->advertising = ADVERTISED_TP;
158
159 if (hw->mac.autoneg == 1) {
160 ecmd->advertising |= ADVERTISED_Autoneg;
161 /* the e1000 autoneg seems to match ethtool nicely */
162 ecmd->advertising |= hw->phy.autoneg_advertised;
163 }
164
165 ecmd->port = PORT_TP;
166 ecmd->phy_address = hw->phy.addr;
167 ecmd->transceiver = XCVR_INTERNAL;
168 } else {
169 ecmd->supported = (SUPPORTED_FIBRE |
170 SUPPORTED_1000baseKX_Full |
171 SUPPORTED_Autoneg |
172 SUPPORTED_Pause);
173 ecmd->advertising = (ADVERTISED_FIBRE |
174 ADVERTISED_1000baseKX_Full);
175 if (hw->mac.type == e1000_i354) {
176 if ((hw->device_id ==
177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
178 !(status & E1000_STATUS_2P5_SKU_OVER)) {
179 ecmd->supported |= SUPPORTED_2500baseX_Full;
180 ecmd->supported &=
181 ~SUPPORTED_1000baseKX_Full;
182 ecmd->advertising |= ADVERTISED_2500baseX_Full;
183 ecmd->advertising &=
184 ~ADVERTISED_1000baseKX_Full;
185 }
186 }
187 if (eth_flags->e100_base_fx) {
188 ecmd->supported |= SUPPORTED_100baseT_Full;
189 ecmd->advertising |= ADVERTISED_100baseT_Full;
190 }
191 if (hw->mac.autoneg == 1)
192 ecmd->advertising |= ADVERTISED_Autoneg;
193
194 ecmd->port = PORT_FIBRE;
195 ecmd->transceiver = XCVR_EXTERNAL;
196 }
197 if (hw->mac.autoneg != 1)
198 ecmd->advertising &= ~(ADVERTISED_Pause |
199 ADVERTISED_Asym_Pause);
200
201 switch (hw->fc.requested_mode) {
202 case e1000_fc_full:
203 ecmd->advertising |= ADVERTISED_Pause;
204 break;
205 case e1000_fc_rx_pause:
206 ecmd->advertising |= (ADVERTISED_Pause |
207 ADVERTISED_Asym_Pause);
208 break;
209 case e1000_fc_tx_pause:
210 ecmd->advertising |= ADVERTISED_Asym_Pause;
211 break;
212 default:
213 ecmd->advertising &= ~(ADVERTISED_Pause |
214 ADVERTISED_Asym_Pause);
215 }
216 if (status & E1000_STATUS_LU) {
217 if ((status & E1000_STATUS_2P5_SKU) &&
218 !(status & E1000_STATUS_2P5_SKU_OVER)) {
219 speed = SPEED_2500;
220 } else if (status & E1000_STATUS_SPEED_1000) {
221 speed = SPEED_1000;
222 } else if (status & E1000_STATUS_SPEED_100) {
223 speed = SPEED_100;
224 } else {
225 speed = SPEED_10;
226 }
227 if ((status & E1000_STATUS_FD) ||
228 hw->phy.media_type != e1000_media_type_copper)
229 ecmd->duplex = DUPLEX_FULL;
230 else
231 ecmd->duplex = DUPLEX_HALF;
232 } else {
233 speed = SPEED_UNKNOWN;
234 ecmd->duplex = DUPLEX_UNKNOWN;
235 }
236 ethtool_cmd_speed_set(ecmd, speed);
237 if ((hw->phy.media_type == e1000_media_type_fiber) ||
238 hw->mac.autoneg)
239 ecmd->autoneg = AUTONEG_ENABLE;
240 else
241 ecmd->autoneg = AUTONEG_DISABLE;
242
243 /* MDI-X => 2; MDI =>1; Invalid =>0 */
244 if (hw->phy.media_type == e1000_media_type_copper)
245 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
246 ETH_TP_MDI;
247 else
248 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
249
250 if (hw->phy.mdix == AUTO_ALL_MODES)
251 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
252 else
253 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
254
255 return 0;
256 }
257
258 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
259 {
260 struct igb_adapter *adapter = netdev_priv(netdev);
261 struct e1000_hw *hw = &adapter->hw;
262
263 /* When SoL/IDER sessions are active, autoneg/speed/duplex
264 * cannot be changed
265 */
266 if (igb_check_reset_block(hw)) {
267 dev_err(&adapter->pdev->dev,
268 "Cannot change link characteristics when SoL/IDER is active.\n");
269 return -EINVAL;
270 }
271
272 /* MDI setting is only allowed when autoneg enabled because
273 * some hardware doesn't allow MDI setting when speed or
274 * duplex is forced.
275 */
276 if (ecmd->eth_tp_mdix_ctrl) {
277 if (hw->phy.media_type != e1000_media_type_copper)
278 return -EOPNOTSUPP;
279
280 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
281 (ecmd->autoneg != AUTONEG_ENABLE)) {
282 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
283 return -EINVAL;
284 }
285 }
286
287 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
288 usleep_range(1000, 2000);
289
290 if (ecmd->autoneg == AUTONEG_ENABLE) {
291 hw->mac.autoneg = 1;
292 if (hw->phy.media_type == e1000_media_type_fiber) {
293 hw->phy.autoneg_advertised = ecmd->advertising |
294 ADVERTISED_FIBRE |
295 ADVERTISED_Autoneg;
296 switch (adapter->link_speed) {
297 case SPEED_2500:
298 hw->phy.autoneg_advertised =
299 ADVERTISED_2500baseX_Full;
300 break;
301 case SPEED_1000:
302 hw->phy.autoneg_advertised =
303 ADVERTISED_1000baseT_Full;
304 break;
305 case SPEED_100:
306 hw->phy.autoneg_advertised =
307 ADVERTISED_100baseT_Full;
308 break;
309 default:
310 break;
311 }
312 } else {
313 hw->phy.autoneg_advertised = ecmd->advertising |
314 ADVERTISED_TP |
315 ADVERTISED_Autoneg;
316 }
317 ecmd->advertising = hw->phy.autoneg_advertised;
318 if (adapter->fc_autoneg)
319 hw->fc.requested_mode = e1000_fc_default;
320 } else {
321 u32 speed = ethtool_cmd_speed(ecmd);
322 /* calling this overrides forced MDI setting */
323 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
324 clear_bit(__IGB_RESETTING, &adapter->state);
325 return -EINVAL;
326 }
327 }
328
329 /* MDI-X => 2; MDI => 1; Auto => 3 */
330 if (ecmd->eth_tp_mdix_ctrl) {
331 /* fix up the value for auto (3 => 0) as zero is mapped
332 * internally to auto
333 */
334 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
335 hw->phy.mdix = AUTO_ALL_MODES;
336 else
337 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
338 }
339
340 /* reset the link */
341 if (netif_running(adapter->netdev)) {
342 igb_down(adapter);
343 igb_up(adapter);
344 } else
345 igb_reset(adapter);
346
347 clear_bit(__IGB_RESETTING, &adapter->state);
348 return 0;
349 }
350
351 static u32 igb_get_link(struct net_device *netdev)
352 {
353 struct igb_adapter *adapter = netdev_priv(netdev);
354 struct e1000_mac_info *mac = &adapter->hw.mac;
355
356 /* If the link is not reported up to netdev, interrupts are disabled,
357 * and so the physical link state may have changed since we last
358 * looked. Set get_link_status to make sure that the true link
359 * state is interrogated, rather than pulling a cached and possibly
360 * stale link state from the driver.
361 */
362 if (!netif_carrier_ok(netdev))
363 mac->get_link_status = 1;
364
365 return igb_has_link(adapter);
366 }
367
368 static void igb_get_pauseparam(struct net_device *netdev,
369 struct ethtool_pauseparam *pause)
370 {
371 struct igb_adapter *adapter = netdev_priv(netdev);
372 struct e1000_hw *hw = &adapter->hw;
373
374 pause->autoneg =
375 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
376
377 if (hw->fc.current_mode == e1000_fc_rx_pause)
378 pause->rx_pause = 1;
379 else if (hw->fc.current_mode == e1000_fc_tx_pause)
380 pause->tx_pause = 1;
381 else if (hw->fc.current_mode == e1000_fc_full) {
382 pause->rx_pause = 1;
383 pause->tx_pause = 1;
384 }
385 }
386
387 static int igb_set_pauseparam(struct net_device *netdev,
388 struct ethtool_pauseparam *pause)
389 {
390 struct igb_adapter *adapter = netdev_priv(netdev);
391 struct e1000_hw *hw = &adapter->hw;
392 int retval = 0;
393
394 /* 100basefx does not support setting link flow control */
395 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
396 return -EINVAL;
397
398 adapter->fc_autoneg = pause->autoneg;
399
400 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
401 usleep_range(1000, 2000);
402
403 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
404 hw->fc.requested_mode = e1000_fc_default;
405 if (netif_running(adapter->netdev)) {
406 igb_down(adapter);
407 igb_up(adapter);
408 } else {
409 igb_reset(adapter);
410 }
411 } else {
412 if (pause->rx_pause && pause->tx_pause)
413 hw->fc.requested_mode = e1000_fc_full;
414 else if (pause->rx_pause && !pause->tx_pause)
415 hw->fc.requested_mode = e1000_fc_rx_pause;
416 else if (!pause->rx_pause && pause->tx_pause)
417 hw->fc.requested_mode = e1000_fc_tx_pause;
418 else if (!pause->rx_pause && !pause->tx_pause)
419 hw->fc.requested_mode = e1000_fc_none;
420
421 hw->fc.current_mode = hw->fc.requested_mode;
422
423 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
424 igb_force_mac_fc(hw) : igb_setup_link(hw));
425 }
426
427 clear_bit(__IGB_RESETTING, &adapter->state);
428 return retval;
429 }
430
431 static u32 igb_get_msglevel(struct net_device *netdev)
432 {
433 struct igb_adapter *adapter = netdev_priv(netdev);
434 return adapter->msg_enable;
435 }
436
437 static void igb_set_msglevel(struct net_device *netdev, u32 data)
438 {
439 struct igb_adapter *adapter = netdev_priv(netdev);
440 adapter->msg_enable = data;
441 }
442
443 static int igb_get_regs_len(struct net_device *netdev)
444 {
445 #define IGB_REGS_LEN 739
446 return IGB_REGS_LEN * sizeof(u32);
447 }
448
449 static void igb_get_regs(struct net_device *netdev,
450 struct ethtool_regs *regs, void *p)
451 {
452 struct igb_adapter *adapter = netdev_priv(netdev);
453 struct e1000_hw *hw = &adapter->hw;
454 u32 *regs_buff = p;
455 u8 i;
456
457 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
458
459 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
460
461 /* General Registers */
462 regs_buff[0] = rd32(E1000_CTRL);
463 regs_buff[1] = rd32(E1000_STATUS);
464 regs_buff[2] = rd32(E1000_CTRL_EXT);
465 regs_buff[3] = rd32(E1000_MDIC);
466 regs_buff[4] = rd32(E1000_SCTL);
467 regs_buff[5] = rd32(E1000_CONNSW);
468 regs_buff[6] = rd32(E1000_VET);
469 regs_buff[7] = rd32(E1000_LEDCTL);
470 regs_buff[8] = rd32(E1000_PBA);
471 regs_buff[9] = rd32(E1000_PBS);
472 regs_buff[10] = rd32(E1000_FRTIMER);
473 regs_buff[11] = rd32(E1000_TCPTIMER);
474
475 /* NVM Register */
476 regs_buff[12] = rd32(E1000_EECD);
477
478 /* Interrupt */
479 /* Reading EICS for EICR because they read the
480 * same but EICS does not clear on read
481 */
482 regs_buff[13] = rd32(E1000_EICS);
483 regs_buff[14] = rd32(E1000_EICS);
484 regs_buff[15] = rd32(E1000_EIMS);
485 regs_buff[16] = rd32(E1000_EIMC);
486 regs_buff[17] = rd32(E1000_EIAC);
487 regs_buff[18] = rd32(E1000_EIAM);
488 /* Reading ICS for ICR because they read the
489 * same but ICS does not clear on read
490 */
491 regs_buff[19] = rd32(E1000_ICS);
492 regs_buff[20] = rd32(E1000_ICS);
493 regs_buff[21] = rd32(E1000_IMS);
494 regs_buff[22] = rd32(E1000_IMC);
495 regs_buff[23] = rd32(E1000_IAC);
496 regs_buff[24] = rd32(E1000_IAM);
497 regs_buff[25] = rd32(E1000_IMIRVP);
498
499 /* Flow Control */
500 regs_buff[26] = rd32(E1000_FCAL);
501 regs_buff[27] = rd32(E1000_FCAH);
502 regs_buff[28] = rd32(E1000_FCTTV);
503 regs_buff[29] = rd32(E1000_FCRTL);
504 regs_buff[30] = rd32(E1000_FCRTH);
505 regs_buff[31] = rd32(E1000_FCRTV);
506
507 /* Receive */
508 regs_buff[32] = rd32(E1000_RCTL);
509 regs_buff[33] = rd32(E1000_RXCSUM);
510 regs_buff[34] = rd32(E1000_RLPML);
511 regs_buff[35] = rd32(E1000_RFCTL);
512 regs_buff[36] = rd32(E1000_MRQC);
513 regs_buff[37] = rd32(E1000_VT_CTL);
514
515 /* Transmit */
516 regs_buff[38] = rd32(E1000_TCTL);
517 regs_buff[39] = rd32(E1000_TCTL_EXT);
518 regs_buff[40] = rd32(E1000_TIPG);
519 regs_buff[41] = rd32(E1000_DTXCTL);
520
521 /* Wake Up */
522 regs_buff[42] = rd32(E1000_WUC);
523 regs_buff[43] = rd32(E1000_WUFC);
524 regs_buff[44] = rd32(E1000_WUS);
525 regs_buff[45] = rd32(E1000_IPAV);
526 regs_buff[46] = rd32(E1000_WUPL);
527
528 /* MAC */
529 regs_buff[47] = rd32(E1000_PCS_CFG0);
530 regs_buff[48] = rd32(E1000_PCS_LCTL);
531 regs_buff[49] = rd32(E1000_PCS_LSTAT);
532 regs_buff[50] = rd32(E1000_PCS_ANADV);
533 regs_buff[51] = rd32(E1000_PCS_LPAB);
534 regs_buff[52] = rd32(E1000_PCS_NPTX);
535 regs_buff[53] = rd32(E1000_PCS_LPABNP);
536
537 /* Statistics */
538 regs_buff[54] = adapter->stats.crcerrs;
539 regs_buff[55] = adapter->stats.algnerrc;
540 regs_buff[56] = adapter->stats.symerrs;
541 regs_buff[57] = adapter->stats.rxerrc;
542 regs_buff[58] = adapter->stats.mpc;
543 regs_buff[59] = adapter->stats.scc;
544 regs_buff[60] = adapter->stats.ecol;
545 regs_buff[61] = adapter->stats.mcc;
546 regs_buff[62] = adapter->stats.latecol;
547 regs_buff[63] = adapter->stats.colc;
548 regs_buff[64] = adapter->stats.dc;
549 regs_buff[65] = adapter->stats.tncrs;
550 regs_buff[66] = adapter->stats.sec;
551 regs_buff[67] = adapter->stats.htdpmc;
552 regs_buff[68] = adapter->stats.rlec;
553 regs_buff[69] = adapter->stats.xonrxc;
554 regs_buff[70] = adapter->stats.xontxc;
555 regs_buff[71] = adapter->stats.xoffrxc;
556 regs_buff[72] = adapter->stats.xofftxc;
557 regs_buff[73] = adapter->stats.fcruc;
558 regs_buff[74] = adapter->stats.prc64;
559 regs_buff[75] = adapter->stats.prc127;
560 regs_buff[76] = adapter->stats.prc255;
561 regs_buff[77] = adapter->stats.prc511;
562 regs_buff[78] = adapter->stats.prc1023;
563 regs_buff[79] = adapter->stats.prc1522;
564 regs_buff[80] = adapter->stats.gprc;
565 regs_buff[81] = adapter->stats.bprc;
566 regs_buff[82] = adapter->stats.mprc;
567 regs_buff[83] = adapter->stats.gptc;
568 regs_buff[84] = adapter->stats.gorc;
569 regs_buff[86] = adapter->stats.gotc;
570 regs_buff[88] = adapter->stats.rnbc;
571 regs_buff[89] = adapter->stats.ruc;
572 regs_buff[90] = adapter->stats.rfc;
573 regs_buff[91] = adapter->stats.roc;
574 regs_buff[92] = adapter->stats.rjc;
575 regs_buff[93] = adapter->stats.mgprc;
576 regs_buff[94] = adapter->stats.mgpdc;
577 regs_buff[95] = adapter->stats.mgptc;
578 regs_buff[96] = adapter->stats.tor;
579 regs_buff[98] = adapter->stats.tot;
580 regs_buff[100] = adapter->stats.tpr;
581 regs_buff[101] = adapter->stats.tpt;
582 regs_buff[102] = adapter->stats.ptc64;
583 regs_buff[103] = adapter->stats.ptc127;
584 regs_buff[104] = adapter->stats.ptc255;
585 regs_buff[105] = adapter->stats.ptc511;
586 regs_buff[106] = adapter->stats.ptc1023;
587 regs_buff[107] = adapter->stats.ptc1522;
588 regs_buff[108] = adapter->stats.mptc;
589 regs_buff[109] = adapter->stats.bptc;
590 regs_buff[110] = adapter->stats.tsctc;
591 regs_buff[111] = adapter->stats.iac;
592 regs_buff[112] = adapter->stats.rpthc;
593 regs_buff[113] = adapter->stats.hgptc;
594 regs_buff[114] = adapter->stats.hgorc;
595 regs_buff[116] = adapter->stats.hgotc;
596 regs_buff[118] = adapter->stats.lenerrs;
597 regs_buff[119] = adapter->stats.scvpc;
598 regs_buff[120] = adapter->stats.hrmpc;
599
600 for (i = 0; i < 4; i++)
601 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
602 for (i = 0; i < 4; i++)
603 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
604 for (i = 0; i < 4; i++)
605 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
606 for (i = 0; i < 4; i++)
607 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
608 for (i = 0; i < 4; i++)
609 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
610 for (i = 0; i < 4; i++)
611 regs_buff[141 + i] = rd32(E1000_RDH(i));
612 for (i = 0; i < 4; i++)
613 regs_buff[145 + i] = rd32(E1000_RDT(i));
614 for (i = 0; i < 4; i++)
615 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
616
617 for (i = 0; i < 10; i++)
618 regs_buff[153 + i] = rd32(E1000_EITR(i));
619 for (i = 0; i < 8; i++)
620 regs_buff[163 + i] = rd32(E1000_IMIR(i));
621 for (i = 0; i < 8; i++)
622 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
623 for (i = 0; i < 16; i++)
624 regs_buff[179 + i] = rd32(E1000_RAL(i));
625 for (i = 0; i < 16; i++)
626 regs_buff[195 + i] = rd32(E1000_RAH(i));
627
628 for (i = 0; i < 4; i++)
629 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
630 for (i = 0; i < 4; i++)
631 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
632 for (i = 0; i < 4; i++)
633 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
634 for (i = 0; i < 4; i++)
635 regs_buff[223 + i] = rd32(E1000_TDH(i));
636 for (i = 0; i < 4; i++)
637 regs_buff[227 + i] = rd32(E1000_TDT(i));
638 for (i = 0; i < 4; i++)
639 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
640 for (i = 0; i < 4; i++)
641 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
642 for (i = 0; i < 4; i++)
643 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
644 for (i = 0; i < 4; i++)
645 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
646
647 for (i = 0; i < 4; i++)
648 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
649 for (i = 0; i < 4; i++)
650 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
651 for (i = 0; i < 32; i++)
652 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
653 for (i = 0; i < 128; i++)
654 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
655 for (i = 0; i < 128; i++)
656 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
657 for (i = 0; i < 4; i++)
658 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
659
660 regs_buff[547] = rd32(E1000_TDFH);
661 regs_buff[548] = rd32(E1000_TDFT);
662 regs_buff[549] = rd32(E1000_TDFHS);
663 regs_buff[550] = rd32(E1000_TDFPC);
664
665 if (hw->mac.type > e1000_82580) {
666 regs_buff[551] = adapter->stats.o2bgptc;
667 regs_buff[552] = adapter->stats.b2ospc;
668 regs_buff[553] = adapter->stats.o2bspc;
669 regs_buff[554] = adapter->stats.b2ogprc;
670 }
671
672 if (hw->mac.type != e1000_82576)
673 return;
674 for (i = 0; i < 12; i++)
675 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
676 for (i = 0; i < 4; i++)
677 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
678 for (i = 0; i < 12; i++)
679 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
680 for (i = 0; i < 12; i++)
681 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
682 for (i = 0; i < 12; i++)
683 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
684 for (i = 0; i < 12; i++)
685 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
686 for (i = 0; i < 12; i++)
687 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
688 for (i = 0; i < 12; i++)
689 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
690
691 for (i = 0; i < 12; i++)
692 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
693 for (i = 0; i < 12; i++)
694 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
695 for (i = 0; i < 12; i++)
696 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
697 for (i = 0; i < 12; i++)
698 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
699 for (i = 0; i < 12; i++)
700 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
701 for (i = 0; i < 12; i++)
702 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
703 for (i = 0; i < 12; i++)
704 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
705 for (i = 0; i < 12; i++)
706 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
707 }
708
709 static int igb_get_eeprom_len(struct net_device *netdev)
710 {
711 struct igb_adapter *adapter = netdev_priv(netdev);
712 return adapter->hw.nvm.word_size * 2;
713 }
714
715 static int igb_get_eeprom(struct net_device *netdev,
716 struct ethtool_eeprom *eeprom, u8 *bytes)
717 {
718 struct igb_adapter *adapter = netdev_priv(netdev);
719 struct e1000_hw *hw = &adapter->hw;
720 u16 *eeprom_buff;
721 int first_word, last_word;
722 int ret_val = 0;
723 u16 i;
724
725 if (eeprom->len == 0)
726 return -EINVAL;
727
728 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
729
730 first_word = eeprom->offset >> 1;
731 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
732
733 eeprom_buff = kmalloc(sizeof(u16) *
734 (last_word - first_word + 1), GFP_KERNEL);
735 if (!eeprom_buff)
736 return -ENOMEM;
737
738 if (hw->nvm.type == e1000_nvm_eeprom_spi)
739 ret_val = hw->nvm.ops.read(hw, first_word,
740 last_word - first_word + 1,
741 eeprom_buff);
742 else {
743 for (i = 0; i < last_word - first_word + 1; i++) {
744 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
745 &eeprom_buff[i]);
746 if (ret_val)
747 break;
748 }
749 }
750
751 /* Device's eeprom is always little-endian, word addressable */
752 for (i = 0; i < last_word - first_word + 1; i++)
753 le16_to_cpus(&eeprom_buff[i]);
754
755 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
756 eeprom->len);
757 kfree(eeprom_buff);
758
759 return ret_val;
760 }
761
762 static int igb_set_eeprom(struct net_device *netdev,
763 struct ethtool_eeprom *eeprom, u8 *bytes)
764 {
765 struct igb_adapter *adapter = netdev_priv(netdev);
766 struct e1000_hw *hw = &adapter->hw;
767 u16 *eeprom_buff;
768 void *ptr;
769 int max_len, first_word, last_word, ret_val = 0;
770 u16 i;
771
772 if (eeprom->len == 0)
773 return -EOPNOTSUPP;
774
775 if ((hw->mac.type >= e1000_i210) &&
776 !igb_get_flash_presence_i210(hw)) {
777 return -EOPNOTSUPP;
778 }
779
780 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
781 return -EFAULT;
782
783 max_len = hw->nvm.word_size * 2;
784
785 first_word = eeprom->offset >> 1;
786 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
787 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
788 if (!eeprom_buff)
789 return -ENOMEM;
790
791 ptr = (void *)eeprom_buff;
792
793 if (eeprom->offset & 1) {
794 /* need read/modify/write of first changed EEPROM word
795 * only the second byte of the word is being modified
796 */
797 ret_val = hw->nvm.ops.read(hw, first_word, 1,
798 &eeprom_buff[0]);
799 ptr++;
800 }
801 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
802 /* need read/modify/write of last changed EEPROM word
803 * only the first byte of the word is being modified
804 */
805 ret_val = hw->nvm.ops.read(hw, last_word, 1,
806 &eeprom_buff[last_word - first_word]);
807 }
808
809 /* Device's eeprom is always little-endian, word addressable */
810 for (i = 0; i < last_word - first_word + 1; i++)
811 le16_to_cpus(&eeprom_buff[i]);
812
813 memcpy(ptr, bytes, eeprom->len);
814
815 for (i = 0; i < last_word - first_word + 1; i++)
816 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
817
818 ret_val = hw->nvm.ops.write(hw, first_word,
819 last_word - first_word + 1, eeprom_buff);
820
821 /* Update the checksum if nvm write succeeded */
822 if (ret_val == 0)
823 hw->nvm.ops.update(hw);
824
825 igb_set_fw_version(adapter);
826 kfree(eeprom_buff);
827 return ret_val;
828 }
829
830 static void igb_get_drvinfo(struct net_device *netdev,
831 struct ethtool_drvinfo *drvinfo)
832 {
833 struct igb_adapter *adapter = netdev_priv(netdev);
834
835 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
836 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
837
838 /* EEPROM image version # is reported as firmware version # for
839 * 82575 controllers
840 */
841 strlcpy(drvinfo->fw_version, adapter->fw_version,
842 sizeof(drvinfo->fw_version));
843 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
844 sizeof(drvinfo->bus_info));
845 drvinfo->n_stats = IGB_STATS_LEN;
846 drvinfo->testinfo_len = IGB_TEST_LEN;
847 drvinfo->regdump_len = igb_get_regs_len(netdev);
848 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
849 }
850
851 static void igb_get_ringparam(struct net_device *netdev,
852 struct ethtool_ringparam *ring)
853 {
854 struct igb_adapter *adapter = netdev_priv(netdev);
855
856 ring->rx_max_pending = IGB_MAX_RXD;
857 ring->tx_max_pending = IGB_MAX_TXD;
858 ring->rx_pending = adapter->rx_ring_count;
859 ring->tx_pending = adapter->tx_ring_count;
860 }
861
862 static int igb_set_ringparam(struct net_device *netdev,
863 struct ethtool_ringparam *ring)
864 {
865 struct igb_adapter *adapter = netdev_priv(netdev);
866 struct igb_ring *temp_ring;
867 int i, err = 0;
868 u16 new_rx_count, new_tx_count;
869
870 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
871 return -EINVAL;
872
873 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
874 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
875 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
876
877 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
878 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
879 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
880
881 if ((new_tx_count == adapter->tx_ring_count) &&
882 (new_rx_count == adapter->rx_ring_count)) {
883 /* nothing to do */
884 return 0;
885 }
886
887 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
888 usleep_range(1000, 2000);
889
890 if (!netif_running(adapter->netdev)) {
891 for (i = 0; i < adapter->num_tx_queues; i++)
892 adapter->tx_ring[i]->count = new_tx_count;
893 for (i = 0; i < adapter->num_rx_queues; i++)
894 adapter->rx_ring[i]->count = new_rx_count;
895 adapter->tx_ring_count = new_tx_count;
896 adapter->rx_ring_count = new_rx_count;
897 goto clear_reset;
898 }
899
900 if (adapter->num_tx_queues > adapter->num_rx_queues)
901 temp_ring = vmalloc(adapter->num_tx_queues *
902 sizeof(struct igb_ring));
903 else
904 temp_ring = vmalloc(adapter->num_rx_queues *
905 sizeof(struct igb_ring));
906
907 if (!temp_ring) {
908 err = -ENOMEM;
909 goto clear_reset;
910 }
911
912 igb_down(adapter);
913
914 /* We can't just free everything and then setup again,
915 * because the ISRs in MSI-X mode get passed pointers
916 * to the Tx and Rx ring structs.
917 */
918 if (new_tx_count != adapter->tx_ring_count) {
919 for (i = 0; i < adapter->num_tx_queues; i++) {
920 memcpy(&temp_ring[i], adapter->tx_ring[i],
921 sizeof(struct igb_ring));
922
923 temp_ring[i].count = new_tx_count;
924 err = igb_setup_tx_resources(&temp_ring[i]);
925 if (err) {
926 while (i) {
927 i--;
928 igb_free_tx_resources(&temp_ring[i]);
929 }
930 goto err_setup;
931 }
932 }
933
934 for (i = 0; i < adapter->num_tx_queues; i++) {
935 igb_free_tx_resources(adapter->tx_ring[i]);
936
937 memcpy(adapter->tx_ring[i], &temp_ring[i],
938 sizeof(struct igb_ring));
939 }
940
941 adapter->tx_ring_count = new_tx_count;
942 }
943
944 if (new_rx_count != adapter->rx_ring_count) {
945 for (i = 0; i < adapter->num_rx_queues; i++) {
946 memcpy(&temp_ring[i], adapter->rx_ring[i],
947 sizeof(struct igb_ring));
948
949 temp_ring[i].count = new_rx_count;
950 err = igb_setup_rx_resources(&temp_ring[i]);
951 if (err) {
952 while (i) {
953 i--;
954 igb_free_rx_resources(&temp_ring[i]);
955 }
956 goto err_setup;
957 }
958
959 }
960
961 for (i = 0; i < adapter->num_rx_queues; i++) {
962 igb_free_rx_resources(adapter->rx_ring[i]);
963
964 memcpy(adapter->rx_ring[i], &temp_ring[i],
965 sizeof(struct igb_ring));
966 }
967
968 adapter->rx_ring_count = new_rx_count;
969 }
970 err_setup:
971 igb_up(adapter);
972 vfree(temp_ring);
973 clear_reset:
974 clear_bit(__IGB_RESETTING, &adapter->state);
975 return err;
976 }
977
978 /* ethtool register test data */
979 struct igb_reg_test {
980 u16 reg;
981 u16 reg_offset;
982 u16 array_len;
983 u16 test_type;
984 u32 mask;
985 u32 write;
986 };
987
988 /* In the hardware, registers are laid out either singly, in arrays
989 * spaced 0x100 bytes apart, or in contiguous tables. We assume
990 * most tests take place on arrays or single registers (handled
991 * as a single-element array) and special-case the tables.
992 * Table tests are always pattern tests.
993 *
994 * We also make provision for some required setup steps by specifying
995 * registers to be written without any read-back testing.
996 */
997
998 #define PATTERN_TEST 1
999 #define SET_READ_TEST 2
1000 #define WRITE_NO_TEST 3
1001 #define TABLE32_TEST 4
1002 #define TABLE64_TEST_LO 5
1003 #define TABLE64_TEST_HI 6
1004
1005 /* i210 reg test */
1006 static struct igb_reg_test reg_test_i210[] = {
1007 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1008 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1009 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1010 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1011 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1012 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1013 /* RDH is read-only for i210, only test RDT. */
1014 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1015 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1016 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1017 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1018 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1019 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1020 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1021 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1022 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1023 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1024 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1025 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1026 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1027 0xFFFFFFFF, 0xFFFFFFFF },
1028 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1029 0x900FFFFF, 0xFFFFFFFF },
1030 { E1000_MTA, 0, 128, TABLE32_TEST,
1031 0xFFFFFFFF, 0xFFFFFFFF },
1032 { 0, 0, 0, 0, 0 }
1033 };
1034
1035 /* i350 reg test */
1036 static struct igb_reg_test reg_test_i350[] = {
1037 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1038 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1039 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1040 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1041 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1042 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1043 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1044 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1045 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1046 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1047 /* RDH is read-only for i350, only test RDT. */
1048 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1049 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1050 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1051 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1052 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1053 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1054 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1055 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1056 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1057 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1058 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1059 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1060 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1061 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1062 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1063 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1064 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1065 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1066 0xFFFFFFFF, 0xFFFFFFFF },
1067 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1068 0xC3FFFFFF, 0xFFFFFFFF },
1069 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1070 0xFFFFFFFF, 0xFFFFFFFF },
1071 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1072 0xC3FFFFFF, 0xFFFFFFFF },
1073 { E1000_MTA, 0, 128, TABLE32_TEST,
1074 0xFFFFFFFF, 0xFFFFFFFF },
1075 { 0, 0, 0, 0 }
1076 };
1077
1078 /* 82580 reg test */
1079 static struct igb_reg_test reg_test_82580[] = {
1080 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1081 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1082 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1083 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1084 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1085 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1086 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1087 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1088 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1089 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1090 /* RDH is read-only for 82580, only test RDT. */
1091 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1092 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1093 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1094 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1095 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1096 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1097 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1098 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1099 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1100 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1101 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1102 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1103 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1104 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1105 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1106 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1107 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1108 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1109 0xFFFFFFFF, 0xFFFFFFFF },
1110 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1111 0x83FFFFFF, 0xFFFFFFFF },
1112 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1113 0xFFFFFFFF, 0xFFFFFFFF },
1114 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1115 0x83FFFFFF, 0xFFFFFFFF },
1116 { E1000_MTA, 0, 128, TABLE32_TEST,
1117 0xFFFFFFFF, 0xFFFFFFFF },
1118 { 0, 0, 0, 0 }
1119 };
1120
1121 /* 82576 reg test */
1122 static struct igb_reg_test reg_test_82576[] = {
1123 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1124 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1125 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1126 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1127 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1128 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1129 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1130 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1131 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1132 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1133 /* Enable all RX queues before testing. */
1134 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1135 E1000_RXDCTL_QUEUE_ENABLE },
1136 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1137 E1000_RXDCTL_QUEUE_ENABLE },
1138 /* RDH is read-only for 82576, only test RDT. */
1139 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1140 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1141 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1142 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1143 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1144 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1145 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1146 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1147 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1148 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1149 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1150 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1152 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1153 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1154 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1155 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1156 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1157 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1158 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1159 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1160 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1161 { 0, 0, 0, 0 }
1162 };
1163
1164 /* 82575 register test */
1165 static struct igb_reg_test reg_test_82575[] = {
1166 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1167 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1168 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1169 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1171 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1172 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1173 /* Enable all four RX queues before testing. */
1174 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1175 E1000_RXDCTL_QUEUE_ENABLE },
1176 /* RDH is read-only for 82575, only test RDT. */
1177 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1178 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1179 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1180 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1181 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1182 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1183 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1184 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1185 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1186 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1187 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1188 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1189 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1190 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1191 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1192 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1193 { 0, 0, 0, 0 }
1194 };
1195
1196 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1197 int reg, u32 mask, u32 write)
1198 {
1199 struct e1000_hw *hw = &adapter->hw;
1200 u32 pat, val;
1201 static const u32 _test[] = {
1202 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1203 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1204 wr32(reg, (_test[pat] & write));
1205 val = rd32(reg) & mask;
1206 if (val != (_test[pat] & write & mask)) {
1207 dev_err(&adapter->pdev->dev,
1208 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1209 reg, val, (_test[pat] & write & mask));
1210 *data = reg;
1211 return true;
1212 }
1213 }
1214
1215 return false;
1216 }
1217
1218 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1219 int reg, u32 mask, u32 write)
1220 {
1221 struct e1000_hw *hw = &adapter->hw;
1222 u32 val;
1223
1224 wr32(reg, write & mask);
1225 val = rd32(reg);
1226 if ((write & mask) != (val & mask)) {
1227 dev_err(&adapter->pdev->dev,
1228 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1229 reg, (val & mask), (write & mask));
1230 *data = reg;
1231 return true;
1232 }
1233
1234 return false;
1235 }
1236
1237 #define REG_PATTERN_TEST(reg, mask, write) \
1238 do { \
1239 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1240 return 1; \
1241 } while (0)
1242
1243 #define REG_SET_AND_CHECK(reg, mask, write) \
1244 do { \
1245 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1246 return 1; \
1247 } while (0)
1248
1249 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1250 {
1251 struct e1000_hw *hw = &adapter->hw;
1252 struct igb_reg_test *test;
1253 u32 value, before, after;
1254 u32 i, toggle;
1255
1256 switch (adapter->hw.mac.type) {
1257 case e1000_i350:
1258 case e1000_i354:
1259 test = reg_test_i350;
1260 toggle = 0x7FEFF3FF;
1261 break;
1262 case e1000_i210:
1263 case e1000_i211:
1264 test = reg_test_i210;
1265 toggle = 0x7FEFF3FF;
1266 break;
1267 case e1000_82580:
1268 test = reg_test_82580;
1269 toggle = 0x7FEFF3FF;
1270 break;
1271 case e1000_82576:
1272 test = reg_test_82576;
1273 toggle = 0x7FFFF3FF;
1274 break;
1275 default:
1276 test = reg_test_82575;
1277 toggle = 0x7FFFF3FF;
1278 break;
1279 }
1280
1281 /* Because the status register is such a special case,
1282 * we handle it separately from the rest of the register
1283 * tests. Some bits are read-only, some toggle, and some
1284 * are writable on newer MACs.
1285 */
1286 before = rd32(E1000_STATUS);
1287 value = (rd32(E1000_STATUS) & toggle);
1288 wr32(E1000_STATUS, toggle);
1289 after = rd32(E1000_STATUS) & toggle;
1290 if (value != after) {
1291 dev_err(&adapter->pdev->dev,
1292 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1293 after, value);
1294 *data = 1;
1295 return 1;
1296 }
1297 /* restore previous status */
1298 wr32(E1000_STATUS, before);
1299
1300 /* Perform the remainder of the register test, looping through
1301 * the test table until we either fail or reach the null entry.
1302 */
1303 while (test->reg) {
1304 for (i = 0; i < test->array_len; i++) {
1305 switch (test->test_type) {
1306 case PATTERN_TEST:
1307 REG_PATTERN_TEST(test->reg +
1308 (i * test->reg_offset),
1309 test->mask,
1310 test->write);
1311 break;
1312 case SET_READ_TEST:
1313 REG_SET_AND_CHECK(test->reg +
1314 (i * test->reg_offset),
1315 test->mask,
1316 test->write);
1317 break;
1318 case WRITE_NO_TEST:
1319 writel(test->write,
1320 (adapter->hw.hw_addr + test->reg)
1321 + (i * test->reg_offset));
1322 break;
1323 case TABLE32_TEST:
1324 REG_PATTERN_TEST(test->reg + (i * 4),
1325 test->mask,
1326 test->write);
1327 break;
1328 case TABLE64_TEST_LO:
1329 REG_PATTERN_TEST(test->reg + (i * 8),
1330 test->mask,
1331 test->write);
1332 break;
1333 case TABLE64_TEST_HI:
1334 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1335 test->mask,
1336 test->write);
1337 break;
1338 }
1339 }
1340 test++;
1341 }
1342
1343 *data = 0;
1344 return 0;
1345 }
1346
1347 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1348 {
1349 struct e1000_hw *hw = &adapter->hw;
1350
1351 *data = 0;
1352
1353 /* Validate eeprom on all parts but flashless */
1354 switch (hw->mac.type) {
1355 case e1000_i210:
1356 case e1000_i211:
1357 if (igb_get_flash_presence_i210(hw)) {
1358 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1359 *data = 2;
1360 }
1361 break;
1362 default:
1363 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1364 *data = 2;
1365 break;
1366 }
1367
1368 return *data;
1369 }
1370
1371 static irqreturn_t igb_test_intr(int irq, void *data)
1372 {
1373 struct igb_adapter *adapter = (struct igb_adapter *) data;
1374 struct e1000_hw *hw = &adapter->hw;
1375
1376 adapter->test_icr |= rd32(E1000_ICR);
1377
1378 return IRQ_HANDLED;
1379 }
1380
1381 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1382 {
1383 struct e1000_hw *hw = &adapter->hw;
1384 struct net_device *netdev = adapter->netdev;
1385 u32 mask, ics_mask, i = 0, shared_int = true;
1386 u32 irq = adapter->pdev->irq;
1387
1388 *data = 0;
1389
1390 /* Hook up test interrupt handler just for this test */
1391 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1392 if (request_irq(adapter->msix_entries[0].vector,
1393 igb_test_intr, 0, netdev->name, adapter)) {
1394 *data = 1;
1395 return -1;
1396 }
1397 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1398 shared_int = false;
1399 if (request_irq(irq,
1400 igb_test_intr, 0, netdev->name, adapter)) {
1401 *data = 1;
1402 return -1;
1403 }
1404 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1405 netdev->name, adapter)) {
1406 shared_int = false;
1407 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1408 netdev->name, adapter)) {
1409 *data = 1;
1410 return -1;
1411 }
1412 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1413 (shared_int ? "shared" : "unshared"));
1414
1415 /* Disable all the interrupts */
1416 wr32(E1000_IMC, ~0);
1417 wrfl();
1418 usleep_range(10000, 11000);
1419
1420 /* Define all writable bits for ICS */
1421 switch (hw->mac.type) {
1422 case e1000_82575:
1423 ics_mask = 0x37F47EDD;
1424 break;
1425 case e1000_82576:
1426 ics_mask = 0x77D4FBFD;
1427 break;
1428 case e1000_82580:
1429 ics_mask = 0x77DCFED5;
1430 break;
1431 case e1000_i350:
1432 case e1000_i354:
1433 case e1000_i210:
1434 case e1000_i211:
1435 ics_mask = 0x77DCFED5;
1436 break;
1437 default:
1438 ics_mask = 0x7FFFFFFF;
1439 break;
1440 }
1441
1442 /* Test each interrupt */
1443 for (; i < 31; i++) {
1444 /* Interrupt to test */
1445 mask = 1 << i;
1446
1447 if (!(mask & ics_mask))
1448 continue;
1449
1450 if (!shared_int) {
1451 /* Disable the interrupt to be reported in
1452 * the cause register and then force the same
1453 * interrupt and see if one gets posted. If
1454 * an interrupt was posted to the bus, the
1455 * test failed.
1456 */
1457 adapter->test_icr = 0;
1458
1459 /* Flush any pending interrupts */
1460 wr32(E1000_ICR, ~0);
1461
1462 wr32(E1000_IMC, mask);
1463 wr32(E1000_ICS, mask);
1464 wrfl();
1465 usleep_range(10000, 11000);
1466
1467 if (adapter->test_icr & mask) {
1468 *data = 3;
1469 break;
1470 }
1471 }
1472
1473 /* Enable the interrupt to be reported in
1474 * the cause register and then force the same
1475 * interrupt and see if one gets posted. If
1476 * an interrupt was not posted to the bus, the
1477 * test failed.
1478 */
1479 adapter->test_icr = 0;
1480
1481 /* Flush any pending interrupts */
1482 wr32(E1000_ICR, ~0);
1483
1484 wr32(E1000_IMS, mask);
1485 wr32(E1000_ICS, mask);
1486 wrfl();
1487 usleep_range(10000, 11000);
1488
1489 if (!(adapter->test_icr & mask)) {
1490 *data = 4;
1491 break;
1492 }
1493
1494 if (!shared_int) {
1495 /* Disable the other interrupts to be reported in
1496 * the cause register and then force the other
1497 * interrupts and see if any get posted. If
1498 * an interrupt was posted to the bus, the
1499 * test failed.
1500 */
1501 adapter->test_icr = 0;
1502
1503 /* Flush any pending interrupts */
1504 wr32(E1000_ICR, ~0);
1505
1506 wr32(E1000_IMC, ~mask);
1507 wr32(E1000_ICS, ~mask);
1508 wrfl();
1509 usleep_range(10000, 11000);
1510
1511 if (adapter->test_icr & mask) {
1512 *data = 5;
1513 break;
1514 }
1515 }
1516 }
1517
1518 /* Disable all the interrupts */
1519 wr32(E1000_IMC, ~0);
1520 wrfl();
1521 usleep_range(10000, 11000);
1522
1523 /* Unhook test interrupt handler */
1524 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1525 free_irq(adapter->msix_entries[0].vector, adapter);
1526 else
1527 free_irq(irq, adapter);
1528
1529 return *data;
1530 }
1531
1532 static void igb_free_desc_rings(struct igb_adapter *adapter)
1533 {
1534 igb_free_tx_resources(&adapter->test_tx_ring);
1535 igb_free_rx_resources(&adapter->test_rx_ring);
1536 }
1537
1538 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1539 {
1540 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1541 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1542 struct e1000_hw *hw = &adapter->hw;
1543 int ret_val;
1544
1545 /* Setup Tx descriptor ring and Tx buffers */
1546 tx_ring->count = IGB_DEFAULT_TXD;
1547 tx_ring->dev = &adapter->pdev->dev;
1548 tx_ring->netdev = adapter->netdev;
1549 tx_ring->reg_idx = adapter->vfs_allocated_count;
1550
1551 if (igb_setup_tx_resources(tx_ring)) {
1552 ret_val = 1;
1553 goto err_nomem;
1554 }
1555
1556 igb_setup_tctl(adapter);
1557 igb_configure_tx_ring(adapter, tx_ring);
1558
1559 /* Setup Rx descriptor ring and Rx buffers */
1560 rx_ring->count = IGB_DEFAULT_RXD;
1561 rx_ring->dev = &adapter->pdev->dev;
1562 rx_ring->netdev = adapter->netdev;
1563 rx_ring->reg_idx = adapter->vfs_allocated_count;
1564
1565 if (igb_setup_rx_resources(rx_ring)) {
1566 ret_val = 3;
1567 goto err_nomem;
1568 }
1569
1570 /* set the default queue to queue 0 of PF */
1571 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1572
1573 /* enable receive ring */
1574 igb_setup_rctl(adapter);
1575 igb_configure_rx_ring(adapter, rx_ring);
1576
1577 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1578
1579 return 0;
1580
1581 err_nomem:
1582 igb_free_desc_rings(adapter);
1583 return ret_val;
1584 }
1585
1586 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1587 {
1588 struct e1000_hw *hw = &adapter->hw;
1589
1590 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1591 igb_write_phy_reg(hw, 29, 0x001F);
1592 igb_write_phy_reg(hw, 30, 0x8FFC);
1593 igb_write_phy_reg(hw, 29, 0x001A);
1594 igb_write_phy_reg(hw, 30, 0x8FF0);
1595 }
1596
1597 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1598 {
1599 struct e1000_hw *hw = &adapter->hw;
1600 u32 ctrl_reg = 0;
1601
1602 hw->mac.autoneg = false;
1603
1604 if (hw->phy.type == e1000_phy_m88) {
1605 if (hw->phy.id != I210_I_PHY_ID) {
1606 /* Auto-MDI/MDIX Off */
1607 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1608 /* reset to update Auto-MDI/MDIX */
1609 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1610 /* autoneg off */
1611 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1612 } else {
1613 /* force 1000, set loopback */
1614 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1615 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1616 }
1617 } else if (hw->phy.type == e1000_phy_82580) {
1618 /* enable MII loopback */
1619 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1620 }
1621
1622 /* add small delay to avoid loopback test failure */
1623 msleep(50);
1624
1625 /* force 1000, set loopback */
1626 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1627
1628 /* Now set up the MAC to the same speed/duplex as the PHY. */
1629 ctrl_reg = rd32(E1000_CTRL);
1630 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1631 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1632 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1633 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1634 E1000_CTRL_FD | /* Force Duplex to FULL */
1635 E1000_CTRL_SLU); /* Set link up enable bit */
1636
1637 if (hw->phy.type == e1000_phy_m88)
1638 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1639
1640 wr32(E1000_CTRL, ctrl_reg);
1641
1642 /* Disable the receiver on the PHY so when a cable is plugged in, the
1643 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1644 */
1645 if (hw->phy.type == e1000_phy_m88)
1646 igb_phy_disable_receiver(adapter);
1647
1648 mdelay(500);
1649 return 0;
1650 }
1651
1652 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1653 {
1654 return igb_integrated_phy_loopback(adapter);
1655 }
1656
1657 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1658 {
1659 struct e1000_hw *hw = &adapter->hw;
1660 u32 reg;
1661
1662 reg = rd32(E1000_CTRL_EXT);
1663
1664 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1665 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1666 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1667 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1668 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1669 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1670 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1671 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
1672 /* Enable DH89xxCC MPHY for near end loopback */
1673 reg = rd32(E1000_MPHY_ADDR_CTL);
1674 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1675 E1000_MPHY_PCS_CLK_REG_OFFSET;
1676 wr32(E1000_MPHY_ADDR_CTL, reg);
1677
1678 reg = rd32(E1000_MPHY_DATA);
1679 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1680 wr32(E1000_MPHY_DATA, reg);
1681 }
1682
1683 reg = rd32(E1000_RCTL);
1684 reg |= E1000_RCTL_LBM_TCVR;
1685 wr32(E1000_RCTL, reg);
1686
1687 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1688
1689 reg = rd32(E1000_CTRL);
1690 reg &= ~(E1000_CTRL_RFCE |
1691 E1000_CTRL_TFCE |
1692 E1000_CTRL_LRST);
1693 reg |= E1000_CTRL_SLU |
1694 E1000_CTRL_FD;
1695 wr32(E1000_CTRL, reg);
1696
1697 /* Unset switch control to serdes energy detect */
1698 reg = rd32(E1000_CONNSW);
1699 reg &= ~E1000_CONNSW_ENRGSRC;
1700 wr32(E1000_CONNSW, reg);
1701
1702 /* Unset sigdetect for SERDES loopback on
1703 * 82580 and newer devices.
1704 */
1705 if (hw->mac.type >= e1000_82580) {
1706 reg = rd32(E1000_PCS_CFG0);
1707 reg |= E1000_PCS_CFG_IGN_SD;
1708 wr32(E1000_PCS_CFG0, reg);
1709 }
1710
1711 /* Set PCS register for forced speed */
1712 reg = rd32(E1000_PCS_LCTL);
1713 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1714 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1715 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1716 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1717 E1000_PCS_LCTL_FSD | /* Force Speed */
1718 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1719 wr32(E1000_PCS_LCTL, reg);
1720
1721 return 0;
1722 }
1723
1724 return igb_set_phy_loopback(adapter);
1725 }
1726
1727 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1728 {
1729 struct e1000_hw *hw = &adapter->hw;
1730 u32 rctl;
1731 u16 phy_reg;
1732
1733 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1734 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1735 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1736 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1737 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1738 u32 reg;
1739
1740 /* Disable near end loopback on DH89xxCC */
1741 reg = rd32(E1000_MPHY_ADDR_CTL);
1742 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1743 E1000_MPHY_PCS_CLK_REG_OFFSET;
1744 wr32(E1000_MPHY_ADDR_CTL, reg);
1745
1746 reg = rd32(E1000_MPHY_DATA);
1747 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1748 wr32(E1000_MPHY_DATA, reg);
1749 }
1750
1751 rctl = rd32(E1000_RCTL);
1752 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1753 wr32(E1000_RCTL, rctl);
1754
1755 hw->mac.autoneg = true;
1756 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1757 if (phy_reg & MII_CR_LOOPBACK) {
1758 phy_reg &= ~MII_CR_LOOPBACK;
1759 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1760 igb_phy_sw_reset(hw);
1761 }
1762 }
1763
1764 static void igb_create_lbtest_frame(struct sk_buff *skb,
1765 unsigned int frame_size)
1766 {
1767 memset(skb->data, 0xFF, frame_size);
1768 frame_size /= 2;
1769 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1770 memset(&skb->data[frame_size + 10], 0xBE, 1);
1771 memset(&skb->data[frame_size + 12], 0xAF, 1);
1772 }
1773
1774 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1775 unsigned int frame_size)
1776 {
1777 unsigned char *data;
1778 bool match = true;
1779
1780 frame_size >>= 1;
1781
1782 data = kmap(rx_buffer->page);
1783
1784 if (data[3] != 0xFF ||
1785 data[frame_size + 10] != 0xBE ||
1786 data[frame_size + 12] != 0xAF)
1787 match = false;
1788
1789 kunmap(rx_buffer->page);
1790
1791 return match;
1792 }
1793
1794 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1795 struct igb_ring *tx_ring,
1796 unsigned int size)
1797 {
1798 union e1000_adv_rx_desc *rx_desc;
1799 struct igb_rx_buffer *rx_buffer_info;
1800 struct igb_tx_buffer *tx_buffer_info;
1801 u16 rx_ntc, tx_ntc, count = 0;
1802
1803 /* initialize next to clean and descriptor values */
1804 rx_ntc = rx_ring->next_to_clean;
1805 tx_ntc = tx_ring->next_to_clean;
1806 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1807
1808 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
1809 /* check Rx buffer */
1810 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1811
1812 /* sync Rx buffer for CPU read */
1813 dma_sync_single_for_cpu(rx_ring->dev,
1814 rx_buffer_info->dma,
1815 IGB_RX_BUFSZ,
1816 DMA_FROM_DEVICE);
1817
1818 /* verify contents of skb */
1819 if (igb_check_lbtest_frame(rx_buffer_info, size))
1820 count++;
1821
1822 /* sync Rx buffer for device write */
1823 dma_sync_single_for_device(rx_ring->dev,
1824 rx_buffer_info->dma,
1825 IGB_RX_BUFSZ,
1826 DMA_FROM_DEVICE);
1827
1828 /* unmap buffer on Tx side */
1829 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1830 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1831
1832 /* increment Rx/Tx next to clean counters */
1833 rx_ntc++;
1834 if (rx_ntc == rx_ring->count)
1835 rx_ntc = 0;
1836 tx_ntc++;
1837 if (tx_ntc == tx_ring->count)
1838 tx_ntc = 0;
1839
1840 /* fetch next descriptor */
1841 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1842 }
1843
1844 netdev_tx_reset_queue(txring_txq(tx_ring));
1845
1846 /* re-map buffers to ring, store next to clean values */
1847 igb_alloc_rx_buffers(rx_ring, count);
1848 rx_ring->next_to_clean = rx_ntc;
1849 tx_ring->next_to_clean = tx_ntc;
1850
1851 return count;
1852 }
1853
1854 static int igb_run_loopback_test(struct igb_adapter *adapter)
1855 {
1856 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1857 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1858 u16 i, j, lc, good_cnt;
1859 int ret_val = 0;
1860 unsigned int size = IGB_RX_HDR_LEN;
1861 netdev_tx_t tx_ret_val;
1862 struct sk_buff *skb;
1863
1864 /* allocate test skb */
1865 skb = alloc_skb(size, GFP_KERNEL);
1866 if (!skb)
1867 return 11;
1868
1869 /* place data into test skb */
1870 igb_create_lbtest_frame(skb, size);
1871 skb_put(skb, size);
1872
1873 /* Calculate the loop count based on the largest descriptor ring
1874 * The idea is to wrap the largest ring a number of times using 64
1875 * send/receive pairs during each loop
1876 */
1877
1878 if (rx_ring->count <= tx_ring->count)
1879 lc = ((tx_ring->count / 64) * 2) + 1;
1880 else
1881 lc = ((rx_ring->count / 64) * 2) + 1;
1882
1883 for (j = 0; j <= lc; j++) { /* loop count loop */
1884 /* reset count of good packets */
1885 good_cnt = 0;
1886
1887 /* place 64 packets on the transmit queue*/
1888 for (i = 0; i < 64; i++) {
1889 skb_get(skb);
1890 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1891 if (tx_ret_val == NETDEV_TX_OK)
1892 good_cnt++;
1893 }
1894
1895 if (good_cnt != 64) {
1896 ret_val = 12;
1897 break;
1898 }
1899
1900 /* allow 200 milliseconds for packets to go from Tx to Rx */
1901 msleep(200);
1902
1903 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1904 if (good_cnt != 64) {
1905 ret_val = 13;
1906 break;
1907 }
1908 } /* end loop count loop */
1909
1910 /* free the original skb */
1911 kfree_skb(skb);
1912
1913 return ret_val;
1914 }
1915
1916 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1917 {
1918 /* PHY loopback cannot be performed if SoL/IDER
1919 * sessions are active
1920 */
1921 if (igb_check_reset_block(&adapter->hw)) {
1922 dev_err(&adapter->pdev->dev,
1923 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1924 *data = 0;
1925 goto out;
1926 }
1927
1928 if (adapter->hw.mac.type == e1000_i354) {
1929 dev_info(&adapter->pdev->dev,
1930 "Loopback test not supported on i354.\n");
1931 *data = 0;
1932 goto out;
1933 }
1934 *data = igb_setup_desc_rings(adapter);
1935 if (*data)
1936 goto out;
1937 *data = igb_setup_loopback_test(adapter);
1938 if (*data)
1939 goto err_loopback;
1940 *data = igb_run_loopback_test(adapter);
1941 igb_loopback_cleanup(adapter);
1942
1943 err_loopback:
1944 igb_free_desc_rings(adapter);
1945 out:
1946 return *data;
1947 }
1948
1949 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1950 {
1951 struct e1000_hw *hw = &adapter->hw;
1952 *data = 0;
1953 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1954 int i = 0;
1955
1956 hw->mac.serdes_has_link = false;
1957
1958 /* On some blade server designs, link establishment
1959 * could take as long as 2-3 minutes
1960 */
1961 do {
1962 hw->mac.ops.check_for_link(&adapter->hw);
1963 if (hw->mac.serdes_has_link)
1964 return *data;
1965 msleep(20);
1966 } while (i++ < 3750);
1967
1968 *data = 1;
1969 } else {
1970 hw->mac.ops.check_for_link(&adapter->hw);
1971 if (hw->mac.autoneg)
1972 msleep(5000);
1973
1974 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1975 *data = 1;
1976 }
1977 return *data;
1978 }
1979
1980 static void igb_diag_test(struct net_device *netdev,
1981 struct ethtool_test *eth_test, u64 *data)
1982 {
1983 struct igb_adapter *adapter = netdev_priv(netdev);
1984 u16 autoneg_advertised;
1985 u8 forced_speed_duplex, autoneg;
1986 bool if_running = netif_running(netdev);
1987
1988 set_bit(__IGB_TESTING, &adapter->state);
1989
1990 /* can't do offline tests on media switching devices */
1991 if (adapter->hw.dev_spec._82575.mas_capable)
1992 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
1993 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1994 /* Offline tests */
1995
1996 /* save speed, duplex, autoneg settings */
1997 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1998 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1999 autoneg = adapter->hw.mac.autoneg;
2000
2001 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2002
2003 /* power up link for link test */
2004 igb_power_up_link(adapter);
2005
2006 /* Link test performed before hardware reset so autoneg doesn't
2007 * interfere with test result
2008 */
2009 if (igb_link_test(adapter, &data[4]))
2010 eth_test->flags |= ETH_TEST_FL_FAILED;
2011
2012 if (if_running)
2013 /* indicate we're in test mode */
2014 dev_close(netdev);
2015 else
2016 igb_reset(adapter);
2017
2018 if (igb_reg_test(adapter, &data[0]))
2019 eth_test->flags |= ETH_TEST_FL_FAILED;
2020
2021 igb_reset(adapter);
2022 if (igb_eeprom_test(adapter, &data[1]))
2023 eth_test->flags |= ETH_TEST_FL_FAILED;
2024
2025 igb_reset(adapter);
2026 if (igb_intr_test(adapter, &data[2]))
2027 eth_test->flags |= ETH_TEST_FL_FAILED;
2028
2029 igb_reset(adapter);
2030 /* power up link for loopback test */
2031 igb_power_up_link(adapter);
2032 if (igb_loopback_test(adapter, &data[3]))
2033 eth_test->flags |= ETH_TEST_FL_FAILED;
2034
2035 /* restore speed, duplex, autoneg settings */
2036 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2037 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2038 adapter->hw.mac.autoneg = autoneg;
2039
2040 /* force this routine to wait until autoneg complete/timeout */
2041 adapter->hw.phy.autoneg_wait_to_complete = true;
2042 igb_reset(adapter);
2043 adapter->hw.phy.autoneg_wait_to_complete = false;
2044
2045 clear_bit(__IGB_TESTING, &adapter->state);
2046 if (if_running)
2047 dev_open(netdev);
2048 } else {
2049 dev_info(&adapter->pdev->dev, "online testing starting\n");
2050
2051 /* PHY is powered down when interface is down */
2052 if (if_running && igb_link_test(adapter, &data[4]))
2053 eth_test->flags |= ETH_TEST_FL_FAILED;
2054 else
2055 data[4] = 0;
2056
2057 /* Online tests aren't run; pass by default */
2058 data[0] = 0;
2059 data[1] = 0;
2060 data[2] = 0;
2061 data[3] = 0;
2062
2063 clear_bit(__IGB_TESTING, &adapter->state);
2064 }
2065 msleep_interruptible(4 * 1000);
2066 }
2067
2068 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2069 {
2070 struct igb_adapter *adapter = netdev_priv(netdev);
2071
2072 wol->wolopts = 0;
2073
2074 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2075 return;
2076
2077 wol->supported = WAKE_UCAST | WAKE_MCAST |
2078 WAKE_BCAST | WAKE_MAGIC |
2079 WAKE_PHY;
2080
2081 /* apply any specific unsupported masks here */
2082 switch (adapter->hw.device_id) {
2083 default:
2084 break;
2085 }
2086
2087 if (adapter->wol & E1000_WUFC_EX)
2088 wol->wolopts |= WAKE_UCAST;
2089 if (adapter->wol & E1000_WUFC_MC)
2090 wol->wolopts |= WAKE_MCAST;
2091 if (adapter->wol & E1000_WUFC_BC)
2092 wol->wolopts |= WAKE_BCAST;
2093 if (adapter->wol & E1000_WUFC_MAG)
2094 wol->wolopts |= WAKE_MAGIC;
2095 if (adapter->wol & E1000_WUFC_LNKC)
2096 wol->wolopts |= WAKE_PHY;
2097 }
2098
2099 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2100 {
2101 struct igb_adapter *adapter = netdev_priv(netdev);
2102
2103 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2104 return -EOPNOTSUPP;
2105
2106 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2107 return wol->wolopts ? -EOPNOTSUPP : 0;
2108
2109 /* these settings will always override what we currently have */
2110 adapter->wol = 0;
2111
2112 if (wol->wolopts & WAKE_UCAST)
2113 adapter->wol |= E1000_WUFC_EX;
2114 if (wol->wolopts & WAKE_MCAST)
2115 adapter->wol |= E1000_WUFC_MC;
2116 if (wol->wolopts & WAKE_BCAST)
2117 adapter->wol |= E1000_WUFC_BC;
2118 if (wol->wolopts & WAKE_MAGIC)
2119 adapter->wol |= E1000_WUFC_MAG;
2120 if (wol->wolopts & WAKE_PHY)
2121 adapter->wol |= E1000_WUFC_LNKC;
2122 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2123
2124 return 0;
2125 }
2126
2127 /* bit defines for adapter->led_status */
2128 #define IGB_LED_ON 0
2129
2130 static int igb_set_phys_id(struct net_device *netdev,
2131 enum ethtool_phys_id_state state)
2132 {
2133 struct igb_adapter *adapter = netdev_priv(netdev);
2134 struct e1000_hw *hw = &adapter->hw;
2135
2136 switch (state) {
2137 case ETHTOOL_ID_ACTIVE:
2138 igb_blink_led(hw);
2139 return 2;
2140 case ETHTOOL_ID_ON:
2141 igb_blink_led(hw);
2142 break;
2143 case ETHTOOL_ID_OFF:
2144 igb_led_off(hw);
2145 break;
2146 case ETHTOOL_ID_INACTIVE:
2147 igb_led_off(hw);
2148 clear_bit(IGB_LED_ON, &adapter->led_status);
2149 igb_cleanup_led(hw);
2150 break;
2151 }
2152
2153 return 0;
2154 }
2155
2156 static int igb_set_coalesce(struct net_device *netdev,
2157 struct ethtool_coalesce *ec)
2158 {
2159 struct igb_adapter *adapter = netdev_priv(netdev);
2160 int i;
2161
2162 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2163 ((ec->rx_coalesce_usecs > 3) &&
2164 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2165 (ec->rx_coalesce_usecs == 2))
2166 return -EINVAL;
2167
2168 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2169 ((ec->tx_coalesce_usecs > 3) &&
2170 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2171 (ec->tx_coalesce_usecs == 2))
2172 return -EINVAL;
2173
2174 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2175 return -EINVAL;
2176
2177 /* If ITR is disabled, disable DMAC */
2178 if (ec->rx_coalesce_usecs == 0) {
2179 if (adapter->flags & IGB_FLAG_DMAC)
2180 adapter->flags &= ~IGB_FLAG_DMAC;
2181 }
2182
2183 /* convert to rate of irq's per second */
2184 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2185 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2186 else
2187 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2188
2189 /* convert to rate of irq's per second */
2190 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2191 adapter->tx_itr_setting = adapter->rx_itr_setting;
2192 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2193 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2194 else
2195 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2196
2197 for (i = 0; i < adapter->num_q_vectors; i++) {
2198 struct igb_q_vector *q_vector = adapter->q_vector[i];
2199 q_vector->tx.work_limit = adapter->tx_work_limit;
2200 if (q_vector->rx.ring)
2201 q_vector->itr_val = adapter->rx_itr_setting;
2202 else
2203 q_vector->itr_val = adapter->tx_itr_setting;
2204 if (q_vector->itr_val && q_vector->itr_val <= 3)
2205 q_vector->itr_val = IGB_START_ITR;
2206 q_vector->set_itr = 1;
2207 }
2208
2209 return 0;
2210 }
2211
2212 static int igb_get_coalesce(struct net_device *netdev,
2213 struct ethtool_coalesce *ec)
2214 {
2215 struct igb_adapter *adapter = netdev_priv(netdev);
2216
2217 if (adapter->rx_itr_setting <= 3)
2218 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2219 else
2220 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2221
2222 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2223 if (adapter->tx_itr_setting <= 3)
2224 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2225 else
2226 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2227 }
2228
2229 return 0;
2230 }
2231
2232 static int igb_nway_reset(struct net_device *netdev)
2233 {
2234 struct igb_adapter *adapter = netdev_priv(netdev);
2235 if (netif_running(netdev))
2236 igb_reinit_locked(adapter);
2237 return 0;
2238 }
2239
2240 static int igb_get_sset_count(struct net_device *netdev, int sset)
2241 {
2242 switch (sset) {
2243 case ETH_SS_STATS:
2244 return IGB_STATS_LEN;
2245 case ETH_SS_TEST:
2246 return IGB_TEST_LEN;
2247 default:
2248 return -ENOTSUPP;
2249 }
2250 }
2251
2252 static void igb_get_ethtool_stats(struct net_device *netdev,
2253 struct ethtool_stats *stats, u64 *data)
2254 {
2255 struct igb_adapter *adapter = netdev_priv(netdev);
2256 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2257 unsigned int start;
2258 struct igb_ring *ring;
2259 int i, j;
2260 char *p;
2261
2262 spin_lock(&adapter->stats64_lock);
2263 igb_update_stats(adapter, net_stats);
2264
2265 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2266 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2267 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2268 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2269 }
2270 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2271 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2272 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2273 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2274 }
2275 for (j = 0; j < adapter->num_tx_queues; j++) {
2276 u64 restart2;
2277
2278 ring = adapter->tx_ring[j];
2279 do {
2280 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
2281 data[i] = ring->tx_stats.packets;
2282 data[i+1] = ring->tx_stats.bytes;
2283 data[i+2] = ring->tx_stats.restart_queue;
2284 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
2285 do {
2286 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
2287 restart2 = ring->tx_stats.restart_queue2;
2288 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
2289 data[i+2] += restart2;
2290
2291 i += IGB_TX_QUEUE_STATS_LEN;
2292 }
2293 for (j = 0; j < adapter->num_rx_queues; j++) {
2294 ring = adapter->rx_ring[j];
2295 do {
2296 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
2297 data[i] = ring->rx_stats.packets;
2298 data[i+1] = ring->rx_stats.bytes;
2299 data[i+2] = ring->rx_stats.drops;
2300 data[i+3] = ring->rx_stats.csum_err;
2301 data[i+4] = ring->rx_stats.alloc_failed;
2302 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
2303 i += IGB_RX_QUEUE_STATS_LEN;
2304 }
2305 spin_unlock(&adapter->stats64_lock);
2306 }
2307
2308 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2309 {
2310 struct igb_adapter *adapter = netdev_priv(netdev);
2311 u8 *p = data;
2312 int i;
2313
2314 switch (stringset) {
2315 case ETH_SS_TEST:
2316 memcpy(data, *igb_gstrings_test,
2317 IGB_TEST_LEN*ETH_GSTRING_LEN);
2318 break;
2319 case ETH_SS_STATS:
2320 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2321 memcpy(p, igb_gstrings_stats[i].stat_string,
2322 ETH_GSTRING_LEN);
2323 p += ETH_GSTRING_LEN;
2324 }
2325 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2326 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2327 ETH_GSTRING_LEN);
2328 p += ETH_GSTRING_LEN;
2329 }
2330 for (i = 0; i < adapter->num_tx_queues; i++) {
2331 sprintf(p, "tx_queue_%u_packets", i);
2332 p += ETH_GSTRING_LEN;
2333 sprintf(p, "tx_queue_%u_bytes", i);
2334 p += ETH_GSTRING_LEN;
2335 sprintf(p, "tx_queue_%u_restart", i);
2336 p += ETH_GSTRING_LEN;
2337 }
2338 for (i = 0; i < adapter->num_rx_queues; i++) {
2339 sprintf(p, "rx_queue_%u_packets", i);
2340 p += ETH_GSTRING_LEN;
2341 sprintf(p, "rx_queue_%u_bytes", i);
2342 p += ETH_GSTRING_LEN;
2343 sprintf(p, "rx_queue_%u_drops", i);
2344 p += ETH_GSTRING_LEN;
2345 sprintf(p, "rx_queue_%u_csum_err", i);
2346 p += ETH_GSTRING_LEN;
2347 sprintf(p, "rx_queue_%u_alloc_failed", i);
2348 p += ETH_GSTRING_LEN;
2349 }
2350 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2351 break;
2352 }
2353 }
2354
2355 static int igb_get_ts_info(struct net_device *dev,
2356 struct ethtool_ts_info *info)
2357 {
2358 struct igb_adapter *adapter = netdev_priv(dev);
2359
2360 if (adapter->ptp_clock)
2361 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2362 else
2363 info->phc_index = -1;
2364
2365 switch (adapter->hw.mac.type) {
2366 case e1000_82575:
2367 info->so_timestamping =
2368 SOF_TIMESTAMPING_TX_SOFTWARE |
2369 SOF_TIMESTAMPING_RX_SOFTWARE |
2370 SOF_TIMESTAMPING_SOFTWARE;
2371 return 0;
2372 case e1000_82576:
2373 case e1000_82580:
2374 case e1000_i350:
2375 case e1000_i354:
2376 case e1000_i210:
2377 case e1000_i211:
2378 info->so_timestamping =
2379 SOF_TIMESTAMPING_TX_SOFTWARE |
2380 SOF_TIMESTAMPING_RX_SOFTWARE |
2381 SOF_TIMESTAMPING_SOFTWARE |
2382 SOF_TIMESTAMPING_TX_HARDWARE |
2383 SOF_TIMESTAMPING_RX_HARDWARE |
2384 SOF_TIMESTAMPING_RAW_HARDWARE;
2385
2386 info->tx_types =
2387 (1 << HWTSTAMP_TX_OFF) |
2388 (1 << HWTSTAMP_TX_ON);
2389
2390 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
2391
2392 /* 82576 does not support timestamping all packets. */
2393 if (adapter->hw.mac.type >= e1000_82580)
2394 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2395 else
2396 info->rx_filters |=
2397 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2398 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2399 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2400 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2401 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2402 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2403 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2404
2405 return 0;
2406 default:
2407 return -EOPNOTSUPP;
2408 }
2409 }
2410
2411 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2412 struct ethtool_rxnfc *cmd)
2413 {
2414 cmd->data = 0;
2415
2416 /* Report default options for RSS on igb */
2417 switch (cmd->flow_type) {
2418 case TCP_V4_FLOW:
2419 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2420 /* Fall through */
2421 case UDP_V4_FLOW:
2422 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2423 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2424 /* Fall through */
2425 case SCTP_V4_FLOW:
2426 case AH_ESP_V4_FLOW:
2427 case AH_V4_FLOW:
2428 case ESP_V4_FLOW:
2429 case IPV4_FLOW:
2430 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2431 break;
2432 case TCP_V6_FLOW:
2433 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2434 /* Fall through */
2435 case UDP_V6_FLOW:
2436 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2437 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2438 /* Fall through */
2439 case SCTP_V6_FLOW:
2440 case AH_ESP_V6_FLOW:
2441 case AH_V6_FLOW:
2442 case ESP_V6_FLOW:
2443 case IPV6_FLOW:
2444 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2445 break;
2446 default:
2447 return -EINVAL;
2448 }
2449
2450 return 0;
2451 }
2452
2453 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2454 u32 *rule_locs)
2455 {
2456 struct igb_adapter *adapter = netdev_priv(dev);
2457 int ret = -EOPNOTSUPP;
2458
2459 switch (cmd->cmd) {
2460 case ETHTOOL_GRXRINGS:
2461 cmd->data = adapter->num_rx_queues;
2462 ret = 0;
2463 break;
2464 case ETHTOOL_GRXFH:
2465 ret = igb_get_rss_hash_opts(adapter, cmd);
2466 break;
2467 default:
2468 break;
2469 }
2470
2471 return ret;
2472 }
2473
2474 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2475 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2476 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2477 struct ethtool_rxnfc *nfc)
2478 {
2479 u32 flags = adapter->flags;
2480
2481 /* RSS does not support anything other than hashing
2482 * to queues on src and dst IPs and ports
2483 */
2484 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2485 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2486 return -EINVAL;
2487
2488 switch (nfc->flow_type) {
2489 case TCP_V4_FLOW:
2490 case TCP_V6_FLOW:
2491 if (!(nfc->data & RXH_IP_SRC) ||
2492 !(nfc->data & RXH_IP_DST) ||
2493 !(nfc->data & RXH_L4_B_0_1) ||
2494 !(nfc->data & RXH_L4_B_2_3))
2495 return -EINVAL;
2496 break;
2497 case UDP_V4_FLOW:
2498 if (!(nfc->data & RXH_IP_SRC) ||
2499 !(nfc->data & RXH_IP_DST))
2500 return -EINVAL;
2501 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2502 case 0:
2503 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2504 break;
2505 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2506 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2507 break;
2508 default:
2509 return -EINVAL;
2510 }
2511 break;
2512 case UDP_V6_FLOW:
2513 if (!(nfc->data & RXH_IP_SRC) ||
2514 !(nfc->data & RXH_IP_DST))
2515 return -EINVAL;
2516 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2517 case 0:
2518 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2519 break;
2520 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2521 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2522 break;
2523 default:
2524 return -EINVAL;
2525 }
2526 break;
2527 case AH_ESP_V4_FLOW:
2528 case AH_V4_FLOW:
2529 case ESP_V4_FLOW:
2530 case SCTP_V4_FLOW:
2531 case AH_ESP_V6_FLOW:
2532 case AH_V6_FLOW:
2533 case ESP_V6_FLOW:
2534 case SCTP_V6_FLOW:
2535 if (!(nfc->data & RXH_IP_SRC) ||
2536 !(nfc->data & RXH_IP_DST) ||
2537 (nfc->data & RXH_L4_B_0_1) ||
2538 (nfc->data & RXH_L4_B_2_3))
2539 return -EINVAL;
2540 break;
2541 default:
2542 return -EINVAL;
2543 }
2544
2545 /* if we changed something we need to update flags */
2546 if (flags != adapter->flags) {
2547 struct e1000_hw *hw = &adapter->hw;
2548 u32 mrqc = rd32(E1000_MRQC);
2549
2550 if ((flags & UDP_RSS_FLAGS) &&
2551 !(adapter->flags & UDP_RSS_FLAGS))
2552 dev_err(&adapter->pdev->dev,
2553 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2554
2555 adapter->flags = flags;
2556
2557 /* Perform hash on these packet types */
2558 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2559 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2560 E1000_MRQC_RSS_FIELD_IPV6 |
2561 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2562
2563 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2564 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2565
2566 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2567 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2568
2569 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2570 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2571
2572 wr32(E1000_MRQC, mrqc);
2573 }
2574
2575 return 0;
2576 }
2577
2578 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2579 {
2580 struct igb_adapter *adapter = netdev_priv(dev);
2581 int ret = -EOPNOTSUPP;
2582
2583 switch (cmd->cmd) {
2584 case ETHTOOL_SRXFH:
2585 ret = igb_set_rss_hash_opt(adapter, cmd);
2586 break;
2587 default:
2588 break;
2589 }
2590
2591 return ret;
2592 }
2593
2594 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2595 {
2596 struct igb_adapter *adapter = netdev_priv(netdev);
2597 struct e1000_hw *hw = &adapter->hw;
2598 u32 ret_val;
2599 u16 phy_data;
2600
2601 if ((hw->mac.type < e1000_i350) ||
2602 (hw->phy.media_type != e1000_media_type_copper))
2603 return -EOPNOTSUPP;
2604
2605 edata->supported = (SUPPORTED_1000baseT_Full |
2606 SUPPORTED_100baseT_Full);
2607 if (!hw->dev_spec._82575.eee_disable)
2608 edata->advertised =
2609 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
2610
2611 /* The IPCNFG and EEER registers are not supported on I354. */
2612 if (hw->mac.type == e1000_i354) {
2613 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
2614 } else {
2615 u32 eeer;
2616
2617 eeer = rd32(E1000_EEER);
2618
2619 /* EEE status on negotiated link */
2620 if (eeer & E1000_EEER_EEE_NEG)
2621 edata->eee_active = true;
2622
2623 if (eeer & E1000_EEER_TX_LPI_EN)
2624 edata->tx_lpi_enabled = true;
2625 }
2626
2627 /* EEE Link Partner Advertised */
2628 switch (hw->mac.type) {
2629 case e1000_i350:
2630 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
2631 &phy_data);
2632 if (ret_val)
2633 return -ENODATA;
2634
2635 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2636 break;
2637 case e1000_i354:
2638 case e1000_i210:
2639 case e1000_i211:
2640 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
2641 E1000_EEE_LP_ADV_DEV_I210,
2642 &phy_data);
2643 if (ret_val)
2644 return -ENODATA;
2645
2646 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2647
2648 break;
2649 default:
2650 break;
2651 }
2652
2653 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2654
2655 if ((hw->mac.type == e1000_i354) &&
2656 (edata->eee_enabled))
2657 edata->tx_lpi_enabled = true;
2658
2659 /* Report correct negotiated EEE status for devices that
2660 * wrongly report EEE at half-duplex
2661 */
2662 if (adapter->link_duplex == HALF_DUPLEX) {
2663 edata->eee_enabled = false;
2664 edata->eee_active = false;
2665 edata->tx_lpi_enabled = false;
2666 edata->advertised &= ~edata->advertised;
2667 }
2668
2669 return 0;
2670 }
2671
2672 static int igb_set_eee(struct net_device *netdev,
2673 struct ethtool_eee *edata)
2674 {
2675 struct igb_adapter *adapter = netdev_priv(netdev);
2676 struct e1000_hw *hw = &adapter->hw;
2677 struct ethtool_eee eee_curr;
2678 bool adv1g_eee = true, adv100m_eee = true;
2679 s32 ret_val;
2680
2681 if ((hw->mac.type < e1000_i350) ||
2682 (hw->phy.media_type != e1000_media_type_copper))
2683 return -EOPNOTSUPP;
2684
2685 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
2686
2687 ret_val = igb_get_eee(netdev, &eee_curr);
2688 if (ret_val)
2689 return ret_val;
2690
2691 if (eee_curr.eee_enabled) {
2692 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2693 dev_err(&adapter->pdev->dev,
2694 "Setting EEE tx-lpi is not supported\n");
2695 return -EINVAL;
2696 }
2697
2698 /* Tx LPI timer is not implemented currently */
2699 if (edata->tx_lpi_timer) {
2700 dev_err(&adapter->pdev->dev,
2701 "Setting EEE Tx LPI timer is not supported\n");
2702 return -EINVAL;
2703 }
2704
2705 if (!edata->advertised || (edata->advertised &
2706 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
2707 dev_err(&adapter->pdev->dev,
2708 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
2709 return -EINVAL;
2710 }
2711 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
2712 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
2713
2714 } else if (!edata->eee_enabled) {
2715 dev_err(&adapter->pdev->dev,
2716 "Setting EEE options are not supported with EEE disabled\n");
2717 return -EINVAL;
2718 }
2719
2720 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
2721 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2722 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2723 adapter->flags |= IGB_FLAG_EEE;
2724
2725 /* reset link */
2726 if (netif_running(netdev))
2727 igb_reinit_locked(adapter);
2728 else
2729 igb_reset(adapter);
2730 }
2731
2732 if (hw->mac.type == e1000_i354)
2733 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
2734 else
2735 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
2736
2737 if (ret_val) {
2738 dev_err(&adapter->pdev->dev,
2739 "Problem setting EEE advertisement options\n");
2740 return -EINVAL;
2741 }
2742
2743 return 0;
2744 }
2745
2746 static int igb_get_module_info(struct net_device *netdev,
2747 struct ethtool_modinfo *modinfo)
2748 {
2749 struct igb_adapter *adapter = netdev_priv(netdev);
2750 struct e1000_hw *hw = &adapter->hw;
2751 u32 status = 0;
2752 u16 sff8472_rev, addr_mode;
2753 bool page_swap = false;
2754
2755 if ((hw->phy.media_type == e1000_media_type_copper) ||
2756 (hw->phy.media_type == e1000_media_type_unknown))
2757 return -EOPNOTSUPP;
2758
2759 /* Check whether we support SFF-8472 or not */
2760 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
2761 if (status)
2762 return -EIO;
2763
2764 /* addressing mode is not supported */
2765 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
2766 if (status)
2767 return -EIO;
2768
2769 /* addressing mode is not supported */
2770 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
2771 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2772 page_swap = true;
2773 }
2774
2775 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
2776 /* We have an SFP, but it does not support SFF-8472 */
2777 modinfo->type = ETH_MODULE_SFF_8079;
2778 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2779 } else {
2780 /* We have an SFP which supports a revision of SFF-8472 */
2781 modinfo->type = ETH_MODULE_SFF_8472;
2782 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2783 }
2784
2785 return 0;
2786 }
2787
2788 static int igb_get_module_eeprom(struct net_device *netdev,
2789 struct ethtool_eeprom *ee, u8 *data)
2790 {
2791 struct igb_adapter *adapter = netdev_priv(netdev);
2792 struct e1000_hw *hw = &adapter->hw;
2793 u32 status = 0;
2794 u16 *dataword;
2795 u16 first_word, last_word;
2796 int i = 0;
2797
2798 if (ee->len == 0)
2799 return -EINVAL;
2800
2801 first_word = ee->offset >> 1;
2802 last_word = (ee->offset + ee->len - 1) >> 1;
2803
2804 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
2805 GFP_KERNEL);
2806 if (!dataword)
2807 return -ENOMEM;
2808
2809 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
2810 for (i = 0; i < last_word - first_word + 1; i++) {
2811 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
2812 if (status) {
2813 /* Error occurred while reading module */
2814 kfree(dataword);
2815 return -EIO;
2816 }
2817
2818 be16_to_cpus(&dataword[i]);
2819 }
2820
2821 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
2822 kfree(dataword);
2823
2824 return 0;
2825 }
2826
2827 static int igb_ethtool_begin(struct net_device *netdev)
2828 {
2829 struct igb_adapter *adapter = netdev_priv(netdev);
2830 pm_runtime_get_sync(&adapter->pdev->dev);
2831 return 0;
2832 }
2833
2834 static void igb_ethtool_complete(struct net_device *netdev)
2835 {
2836 struct igb_adapter *adapter = netdev_priv(netdev);
2837 pm_runtime_put(&adapter->pdev->dev);
2838 }
2839
2840 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
2841 {
2842 return IGB_RETA_SIZE;
2843 }
2844
2845 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key)
2846 {
2847 struct igb_adapter *adapter = netdev_priv(netdev);
2848 int i;
2849
2850 for (i = 0; i < IGB_RETA_SIZE; i++)
2851 indir[i] = adapter->rss_indir_tbl[i];
2852
2853 return 0;
2854 }
2855
2856 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
2857 {
2858 struct e1000_hw *hw = &adapter->hw;
2859 u32 reg = E1000_RETA(0);
2860 u32 shift = 0;
2861 int i = 0;
2862
2863 switch (hw->mac.type) {
2864 case e1000_82575:
2865 shift = 6;
2866 break;
2867 case e1000_82576:
2868 /* 82576 supports 2 RSS queues for SR-IOV */
2869 if (adapter->vfs_allocated_count)
2870 shift = 3;
2871 break;
2872 default:
2873 break;
2874 }
2875
2876 while (i < IGB_RETA_SIZE) {
2877 u32 val = 0;
2878 int j;
2879
2880 for (j = 3; j >= 0; j--) {
2881 val <<= 8;
2882 val |= adapter->rss_indir_tbl[i + j];
2883 }
2884
2885 wr32(reg, val << shift);
2886 reg += 4;
2887 i += 4;
2888 }
2889 }
2890
2891 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
2892 const u8 *key)
2893 {
2894 struct igb_adapter *adapter = netdev_priv(netdev);
2895 struct e1000_hw *hw = &adapter->hw;
2896 int i;
2897 u32 num_queues;
2898
2899 num_queues = adapter->rss_queues;
2900
2901 switch (hw->mac.type) {
2902 case e1000_82576:
2903 /* 82576 supports 2 RSS queues for SR-IOV */
2904 if (adapter->vfs_allocated_count)
2905 num_queues = 2;
2906 break;
2907 default:
2908 break;
2909 }
2910
2911 /* Verify user input. */
2912 for (i = 0; i < IGB_RETA_SIZE; i++)
2913 if (indir[i] >= num_queues)
2914 return -EINVAL;
2915
2916
2917 for (i = 0; i < IGB_RETA_SIZE; i++)
2918 adapter->rss_indir_tbl[i] = indir[i];
2919
2920 igb_write_rss_indir_tbl(adapter);
2921
2922 return 0;
2923 }
2924
2925 static unsigned int igb_max_channels(struct igb_adapter *adapter)
2926 {
2927 struct e1000_hw *hw = &adapter->hw;
2928 unsigned int max_combined = 0;
2929
2930 switch (hw->mac.type) {
2931 case e1000_i211:
2932 max_combined = IGB_MAX_RX_QUEUES_I211;
2933 break;
2934 case e1000_82575:
2935 case e1000_i210:
2936 max_combined = IGB_MAX_RX_QUEUES_82575;
2937 break;
2938 case e1000_i350:
2939 if (!!adapter->vfs_allocated_count) {
2940 max_combined = 1;
2941 break;
2942 }
2943 /* fall through */
2944 case e1000_82576:
2945 if (!!adapter->vfs_allocated_count) {
2946 max_combined = 2;
2947 break;
2948 }
2949 /* fall through */
2950 case e1000_82580:
2951 case e1000_i354:
2952 default:
2953 max_combined = IGB_MAX_RX_QUEUES;
2954 break;
2955 }
2956
2957 return max_combined;
2958 }
2959
2960 static void igb_get_channels(struct net_device *netdev,
2961 struct ethtool_channels *ch)
2962 {
2963 struct igb_adapter *adapter = netdev_priv(netdev);
2964
2965 /* Report maximum channels */
2966 ch->max_combined = igb_max_channels(adapter);
2967
2968 /* Report info for other vector */
2969 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2970 ch->max_other = NON_Q_VECTORS;
2971 ch->other_count = NON_Q_VECTORS;
2972 }
2973
2974 ch->combined_count = adapter->rss_queues;
2975 }
2976
2977 static int igb_set_channels(struct net_device *netdev,
2978 struct ethtool_channels *ch)
2979 {
2980 struct igb_adapter *adapter = netdev_priv(netdev);
2981 unsigned int count = ch->combined_count;
2982
2983 /* Verify they are not requesting separate vectors */
2984 if (!count || ch->rx_count || ch->tx_count)
2985 return -EINVAL;
2986
2987 /* Verify other_count is valid and has not been changed */
2988 if (ch->other_count != NON_Q_VECTORS)
2989 return -EINVAL;
2990
2991 /* Verify the number of channels doesn't exceed hw limits */
2992 if (count > igb_max_channels(adapter))
2993 return -EINVAL;
2994
2995 if (count != adapter->rss_queues) {
2996 adapter->rss_queues = count;
2997
2998 /* Hardware has to reinitialize queues and interrupts to
2999 * match the new configuration.
3000 */
3001 return igb_reinit_queues(adapter);
3002 }
3003
3004 return 0;
3005 }
3006
3007 static const struct ethtool_ops igb_ethtool_ops = {
3008 .get_settings = igb_get_settings,
3009 .set_settings = igb_set_settings,
3010 .get_drvinfo = igb_get_drvinfo,
3011 .get_regs_len = igb_get_regs_len,
3012 .get_regs = igb_get_regs,
3013 .get_wol = igb_get_wol,
3014 .set_wol = igb_set_wol,
3015 .get_msglevel = igb_get_msglevel,
3016 .set_msglevel = igb_set_msglevel,
3017 .nway_reset = igb_nway_reset,
3018 .get_link = igb_get_link,
3019 .get_eeprom_len = igb_get_eeprom_len,
3020 .get_eeprom = igb_get_eeprom,
3021 .set_eeprom = igb_set_eeprom,
3022 .get_ringparam = igb_get_ringparam,
3023 .set_ringparam = igb_set_ringparam,
3024 .get_pauseparam = igb_get_pauseparam,
3025 .set_pauseparam = igb_set_pauseparam,
3026 .self_test = igb_diag_test,
3027 .get_strings = igb_get_strings,
3028 .set_phys_id = igb_set_phys_id,
3029 .get_sset_count = igb_get_sset_count,
3030 .get_ethtool_stats = igb_get_ethtool_stats,
3031 .get_coalesce = igb_get_coalesce,
3032 .set_coalesce = igb_set_coalesce,
3033 .get_ts_info = igb_get_ts_info,
3034 .get_rxnfc = igb_get_rxnfc,
3035 .set_rxnfc = igb_set_rxnfc,
3036 .get_eee = igb_get_eee,
3037 .set_eee = igb_set_eee,
3038 .get_module_info = igb_get_module_info,
3039 .get_module_eeprom = igb_get_module_eeprom,
3040 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
3041 .get_rxfh = igb_get_rxfh,
3042 .set_rxfh = igb_set_rxfh,
3043 .get_channels = igb_get_channels,
3044 .set_channels = igb_set_channels,
3045 .begin = igb_ethtool_begin,
3046 .complete = igb_ethtool_complete,
3047 };
3048
3049 void igb_set_ethtool_ops(struct net_device *netdev)
3050 {
3051 netdev->ethtool_ops = &igb_ethtool_ops;
3052 }
Linux kernel - Deliverables
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