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igb: Update license text to remove FSF address and update copyright.
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25 *******************************************************************************/
26
27 /* ethtool support for igb */
28
29 #include <linux/vmalloc.h>
30 #include <linux/netdevice.h>
31 #include <linux/pci.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/if_ether.h>
35 #include <linux/ethtool.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/highmem.h>
40 #include <linux/mdio.h>
41
42 #include "igb.h"
43
44 struct igb_stats {
45 char stat_string[ETH_GSTRING_LEN];
46 int sizeof_stat;
47 int stat_offset;
48 };
49
50 #define IGB_STAT(_name, _stat) { \
51 .stat_string = _name, \
52 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
53 .stat_offset = offsetof(struct igb_adapter, _stat) \
54 }
55 static const struct igb_stats igb_gstrings_stats[] = {
56 IGB_STAT("rx_packets", stats.gprc),
57 IGB_STAT("tx_packets", stats.gptc),
58 IGB_STAT("rx_bytes", stats.gorc),
59 IGB_STAT("tx_bytes", stats.gotc),
60 IGB_STAT("rx_broadcast", stats.bprc),
61 IGB_STAT("tx_broadcast", stats.bptc),
62 IGB_STAT("rx_multicast", stats.mprc),
63 IGB_STAT("tx_multicast", stats.mptc),
64 IGB_STAT("multicast", stats.mprc),
65 IGB_STAT("collisions", stats.colc),
66 IGB_STAT("rx_crc_errors", stats.crcerrs),
67 IGB_STAT("rx_no_buffer_count", stats.rnbc),
68 IGB_STAT("rx_missed_errors", stats.mpc),
69 IGB_STAT("tx_aborted_errors", stats.ecol),
70 IGB_STAT("tx_carrier_errors", stats.tncrs),
71 IGB_STAT("tx_window_errors", stats.latecol),
72 IGB_STAT("tx_abort_late_coll", stats.latecol),
73 IGB_STAT("tx_deferred_ok", stats.dc),
74 IGB_STAT("tx_single_coll_ok", stats.scc),
75 IGB_STAT("tx_multi_coll_ok", stats.mcc),
76 IGB_STAT("tx_timeout_count", tx_timeout_count),
77 IGB_STAT("rx_long_length_errors", stats.roc),
78 IGB_STAT("rx_short_length_errors", stats.ruc),
79 IGB_STAT("rx_align_errors", stats.algnerrc),
80 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
81 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
82 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
83 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
84 IGB_STAT("tx_flow_control_xon", stats.xontxc),
85 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
86 IGB_STAT("rx_long_byte_count", stats.gorc),
87 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
88 IGB_STAT("tx_smbus", stats.mgptc),
89 IGB_STAT("rx_smbus", stats.mgprc),
90 IGB_STAT("dropped_smbus", stats.mgpdc),
91 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
92 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
93 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
94 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
95 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
96 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
97 };
98
99 #define IGB_NETDEV_STAT(_net_stat) { \
100 .stat_string = __stringify(_net_stat), \
101 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
102 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
103 }
104 static const struct igb_stats igb_gstrings_net_stats[] = {
105 IGB_NETDEV_STAT(rx_errors),
106 IGB_NETDEV_STAT(tx_errors),
107 IGB_NETDEV_STAT(tx_dropped),
108 IGB_NETDEV_STAT(rx_length_errors),
109 IGB_NETDEV_STAT(rx_over_errors),
110 IGB_NETDEV_STAT(rx_frame_errors),
111 IGB_NETDEV_STAT(rx_fifo_errors),
112 IGB_NETDEV_STAT(tx_fifo_errors),
113 IGB_NETDEV_STAT(tx_heartbeat_errors)
114 };
115
116 #define IGB_GLOBAL_STATS_LEN \
117 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
118 #define IGB_NETDEV_STATS_LEN \
119 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
120 #define IGB_RX_QUEUE_STATS_LEN \
121 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
122
123 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
124
125 #define IGB_QUEUE_STATS_LEN \
126 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
127 IGB_RX_QUEUE_STATS_LEN) + \
128 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
129 IGB_TX_QUEUE_STATS_LEN))
130 #define IGB_STATS_LEN \
131 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
132
133 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
134 "Register test (offline)", "Eeprom test (offline)",
135 "Interrupt test (offline)", "Loopback test (offline)",
136 "Link test (on/offline)"
137 };
138 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
139
140 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
141 {
142 struct igb_adapter *adapter = netdev_priv(netdev);
143 struct e1000_hw *hw = &adapter->hw;
144 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
145 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
146 u32 status;
147
148 status = rd32(E1000_STATUS);
149 if (hw->phy.media_type == e1000_media_type_copper) {
150
151 ecmd->supported = (SUPPORTED_10baseT_Half |
152 SUPPORTED_10baseT_Full |
153 SUPPORTED_100baseT_Half |
154 SUPPORTED_100baseT_Full |
155 SUPPORTED_1000baseT_Full|
156 SUPPORTED_Autoneg |
157 SUPPORTED_TP |
158 SUPPORTED_Pause);
159 ecmd->advertising = ADVERTISED_TP;
160
161 if (hw->mac.autoneg == 1) {
162 ecmd->advertising |= ADVERTISED_Autoneg;
163 /* the e1000 autoneg seems to match ethtool nicely */
164 ecmd->advertising |= hw->phy.autoneg_advertised;
165 }
166
167 ecmd->port = PORT_TP;
168 ecmd->phy_address = hw->phy.addr;
169 ecmd->transceiver = XCVR_INTERNAL;
170 } else {
171 ecmd->supported = (SUPPORTED_FIBRE |
172 SUPPORTED_1000baseKX_Full |
173 SUPPORTED_Autoneg |
174 SUPPORTED_Pause);
175 ecmd->advertising = (ADVERTISED_FIBRE |
176 ADVERTISED_1000baseKX_Full);
177 if (hw->mac.type == e1000_i354) {
178 if ((hw->device_id ==
179 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
180 !(status & E1000_STATUS_2P5_SKU_OVER)) {
181 ecmd->supported |= SUPPORTED_2500baseX_Full;
182 ecmd->supported &=
183 ~SUPPORTED_1000baseKX_Full;
184 ecmd->advertising |= ADVERTISED_2500baseX_Full;
185 ecmd->advertising &=
186 ~ADVERTISED_1000baseKX_Full;
187 }
188 }
189 if (eth_flags->e100_base_fx) {
190 ecmd->supported |= SUPPORTED_100baseT_Full;
191 ecmd->advertising |= ADVERTISED_100baseT_Full;
192 }
193 if (hw->mac.autoneg == 1)
194 ecmd->advertising |= ADVERTISED_Autoneg;
195
196 ecmd->port = PORT_FIBRE;
197 ecmd->transceiver = XCVR_EXTERNAL;
198 }
199 if (hw->mac.autoneg != 1)
200 ecmd->advertising &= ~(ADVERTISED_Pause |
201 ADVERTISED_Asym_Pause);
202
203 switch (hw->fc.requested_mode) {
204 case e1000_fc_full:
205 ecmd->advertising |= ADVERTISED_Pause;
206 break;
207 case e1000_fc_rx_pause:
208 ecmd->advertising |= (ADVERTISED_Pause |
209 ADVERTISED_Asym_Pause);
210 break;
211 case e1000_fc_tx_pause:
212 ecmd->advertising |= ADVERTISED_Asym_Pause;
213 break;
214 default:
215 ecmd->advertising &= ~(ADVERTISED_Pause |
216 ADVERTISED_Asym_Pause);
217 }
218 if (status & E1000_STATUS_LU) {
219 if ((status & E1000_STATUS_2P5_SKU) &&
220 !(status & E1000_STATUS_2P5_SKU_OVER)) {
221 ecmd->speed = SPEED_2500;
222 } else if (status & E1000_STATUS_SPEED_1000) {
223 ecmd->speed = SPEED_1000;
224 } else if (status & E1000_STATUS_SPEED_100) {
225 ecmd->speed = SPEED_100;
226 } else {
227 ecmd->speed = SPEED_10;
228 }
229 if ((status & E1000_STATUS_FD) ||
230 hw->phy.media_type != e1000_media_type_copper)
231 ecmd->duplex = DUPLEX_FULL;
232 else
233 ecmd->duplex = DUPLEX_HALF;
234 } else {
235 ecmd->speed = -1;
236 ecmd->duplex = -1;
237 }
238 if ((hw->phy.media_type == e1000_media_type_fiber) ||
239 hw->mac.autoneg)
240 ecmd->autoneg = AUTONEG_ENABLE;
241 else
242 ecmd->autoneg = AUTONEG_DISABLE;
243
244 /* MDI-X => 2; MDI =>1; Invalid =>0 */
245 if (hw->phy.media_type == e1000_media_type_copper)
246 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
247 ETH_TP_MDI;
248 else
249 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
250
251 if (hw->phy.mdix == AUTO_ALL_MODES)
252 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
253 else
254 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
255
256 return 0;
257 }
258
259 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
260 {
261 struct igb_adapter *adapter = netdev_priv(netdev);
262 struct e1000_hw *hw = &adapter->hw;
263
264 /* When SoL/IDER sessions are active, autoneg/speed/duplex
265 * cannot be changed
266 */
267 if (igb_check_reset_block(hw)) {
268 dev_err(&adapter->pdev->dev,
269 "Cannot change link characteristics when SoL/IDER is active.\n");
270 return -EINVAL;
271 }
272
273 /* MDI setting is only allowed when autoneg enabled because
274 * some hardware doesn't allow MDI setting when speed or
275 * duplex is forced.
276 */
277 if (ecmd->eth_tp_mdix_ctrl) {
278 if (hw->phy.media_type != e1000_media_type_copper)
279 return -EOPNOTSUPP;
280
281 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
282 (ecmd->autoneg != AUTONEG_ENABLE)) {
283 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
284 return -EINVAL;
285 }
286 }
287
288 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
289 msleep(1);
290
291 if (ecmd->autoneg == AUTONEG_ENABLE) {
292 hw->mac.autoneg = 1;
293 if (hw->phy.media_type == e1000_media_type_fiber) {
294 hw->phy.autoneg_advertised = ecmd->advertising |
295 ADVERTISED_FIBRE |
296 ADVERTISED_Autoneg;
297 switch (adapter->link_speed) {
298 case SPEED_2500:
299 hw->phy.autoneg_advertised =
300 ADVERTISED_2500baseX_Full;
301 break;
302 case SPEED_1000:
303 hw->phy.autoneg_advertised =
304 ADVERTISED_1000baseT_Full;
305 break;
306 case SPEED_100:
307 hw->phy.autoneg_advertised =
308 ADVERTISED_100baseT_Full;
309 break;
310 default:
311 break;
312 }
313 } else {
314 hw->phy.autoneg_advertised = ecmd->advertising |
315 ADVERTISED_TP |
316 ADVERTISED_Autoneg;
317 }
318 ecmd->advertising = hw->phy.autoneg_advertised;
319 if (adapter->fc_autoneg)
320 hw->fc.requested_mode = e1000_fc_default;
321 } else {
322 u32 speed = ethtool_cmd_speed(ecmd);
323 /* calling this overrides forced MDI setting */
324 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
325 clear_bit(__IGB_RESETTING, &adapter->state);
326 return -EINVAL;
327 }
328 }
329
330 /* MDI-X => 2; MDI => 1; Auto => 3 */
331 if (ecmd->eth_tp_mdix_ctrl) {
332 /* fix up the value for auto (3 => 0) as zero is mapped
333 * internally to auto
334 */
335 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
336 hw->phy.mdix = AUTO_ALL_MODES;
337 else
338 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
339 }
340
341 /* reset the link */
342 if (netif_running(adapter->netdev)) {
343 igb_down(adapter);
344 igb_up(adapter);
345 } else
346 igb_reset(adapter);
347
348 clear_bit(__IGB_RESETTING, &adapter->state);
349 return 0;
350 }
351
352 static u32 igb_get_link(struct net_device *netdev)
353 {
354 struct igb_adapter *adapter = netdev_priv(netdev);
355 struct e1000_mac_info *mac = &adapter->hw.mac;
356
357 /* If the link is not reported up to netdev, interrupts are disabled,
358 * and so the physical link state may have changed since we last
359 * looked. Set get_link_status to make sure that the true link
360 * state is interrogated, rather than pulling a cached and possibly
361 * stale link state from the driver.
362 */
363 if (!netif_carrier_ok(netdev))
364 mac->get_link_status = 1;
365
366 return igb_has_link(adapter);
367 }
368
369 static void igb_get_pauseparam(struct net_device *netdev,
370 struct ethtool_pauseparam *pause)
371 {
372 struct igb_adapter *adapter = netdev_priv(netdev);
373 struct e1000_hw *hw = &adapter->hw;
374
375 pause->autoneg =
376 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
377
378 if (hw->fc.current_mode == e1000_fc_rx_pause)
379 pause->rx_pause = 1;
380 else if (hw->fc.current_mode == e1000_fc_tx_pause)
381 pause->tx_pause = 1;
382 else if (hw->fc.current_mode == e1000_fc_full) {
383 pause->rx_pause = 1;
384 pause->tx_pause = 1;
385 }
386 }
387
388 static int igb_set_pauseparam(struct net_device *netdev,
389 struct ethtool_pauseparam *pause)
390 {
391 struct igb_adapter *adapter = netdev_priv(netdev);
392 struct e1000_hw *hw = &adapter->hw;
393 int retval = 0;
394
395 /* 100basefx does not support setting link flow control */
396 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
397 return -EINVAL;
398
399 adapter->fc_autoneg = pause->autoneg;
400
401 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
402 msleep(1);
403
404 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
405 hw->fc.requested_mode = e1000_fc_default;
406 if (netif_running(adapter->netdev)) {
407 igb_down(adapter);
408 igb_up(adapter);
409 } else {
410 igb_reset(adapter);
411 }
412 } else {
413 if (pause->rx_pause && pause->tx_pause)
414 hw->fc.requested_mode = e1000_fc_full;
415 else if (pause->rx_pause && !pause->tx_pause)
416 hw->fc.requested_mode = e1000_fc_rx_pause;
417 else if (!pause->rx_pause && pause->tx_pause)
418 hw->fc.requested_mode = e1000_fc_tx_pause;
419 else if (!pause->rx_pause && !pause->tx_pause)
420 hw->fc.requested_mode = e1000_fc_none;
421
422 hw->fc.current_mode = hw->fc.requested_mode;
423
424 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
425 igb_force_mac_fc(hw) : igb_setup_link(hw));
426 }
427
428 clear_bit(__IGB_RESETTING, &adapter->state);
429 return retval;
430 }
431
432 static u32 igb_get_msglevel(struct net_device *netdev)
433 {
434 struct igb_adapter *adapter = netdev_priv(netdev);
435 return adapter->msg_enable;
436 }
437
438 static void igb_set_msglevel(struct net_device *netdev, u32 data)
439 {
440 struct igb_adapter *adapter = netdev_priv(netdev);
441 adapter->msg_enable = data;
442 }
443
444 static int igb_get_regs_len(struct net_device *netdev)
445 {
446 #define IGB_REGS_LEN 739
447 return IGB_REGS_LEN * sizeof(u32);
448 }
449
450 static void igb_get_regs(struct net_device *netdev,
451 struct ethtool_regs *regs, void *p)
452 {
453 struct igb_adapter *adapter = netdev_priv(netdev);
454 struct e1000_hw *hw = &adapter->hw;
455 u32 *regs_buff = p;
456 u8 i;
457
458 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
459
460 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
461
462 /* General Registers */
463 regs_buff[0] = rd32(E1000_CTRL);
464 regs_buff[1] = rd32(E1000_STATUS);
465 regs_buff[2] = rd32(E1000_CTRL_EXT);
466 regs_buff[3] = rd32(E1000_MDIC);
467 regs_buff[4] = rd32(E1000_SCTL);
468 regs_buff[5] = rd32(E1000_CONNSW);
469 regs_buff[6] = rd32(E1000_VET);
470 regs_buff[7] = rd32(E1000_LEDCTL);
471 regs_buff[8] = rd32(E1000_PBA);
472 regs_buff[9] = rd32(E1000_PBS);
473 regs_buff[10] = rd32(E1000_FRTIMER);
474 regs_buff[11] = rd32(E1000_TCPTIMER);
475
476 /* NVM Register */
477 regs_buff[12] = rd32(E1000_EECD);
478
479 /* Interrupt */
480 /* Reading EICS for EICR because they read the
481 * same but EICS does not clear on read
482 */
483 regs_buff[13] = rd32(E1000_EICS);
484 regs_buff[14] = rd32(E1000_EICS);
485 regs_buff[15] = rd32(E1000_EIMS);
486 regs_buff[16] = rd32(E1000_EIMC);
487 regs_buff[17] = rd32(E1000_EIAC);
488 regs_buff[18] = rd32(E1000_EIAM);
489 /* Reading ICS for ICR because they read the
490 * same but ICS does not clear on read
491 */
492 regs_buff[19] = rd32(E1000_ICS);
493 regs_buff[20] = rd32(E1000_ICS);
494 regs_buff[21] = rd32(E1000_IMS);
495 regs_buff[22] = rd32(E1000_IMC);
496 regs_buff[23] = rd32(E1000_IAC);
497 regs_buff[24] = rd32(E1000_IAM);
498 regs_buff[25] = rd32(E1000_IMIRVP);
499
500 /* Flow Control */
501 regs_buff[26] = rd32(E1000_FCAL);
502 regs_buff[27] = rd32(E1000_FCAH);
503 regs_buff[28] = rd32(E1000_FCTTV);
504 regs_buff[29] = rd32(E1000_FCRTL);
505 regs_buff[30] = rd32(E1000_FCRTH);
506 regs_buff[31] = rd32(E1000_FCRTV);
507
508 /* Receive */
509 regs_buff[32] = rd32(E1000_RCTL);
510 regs_buff[33] = rd32(E1000_RXCSUM);
511 regs_buff[34] = rd32(E1000_RLPML);
512 regs_buff[35] = rd32(E1000_RFCTL);
513 regs_buff[36] = rd32(E1000_MRQC);
514 regs_buff[37] = rd32(E1000_VT_CTL);
515
516 /* Transmit */
517 regs_buff[38] = rd32(E1000_TCTL);
518 regs_buff[39] = rd32(E1000_TCTL_EXT);
519 regs_buff[40] = rd32(E1000_TIPG);
520 regs_buff[41] = rd32(E1000_DTXCTL);
521
522 /* Wake Up */
523 regs_buff[42] = rd32(E1000_WUC);
524 regs_buff[43] = rd32(E1000_WUFC);
525 regs_buff[44] = rd32(E1000_WUS);
526 regs_buff[45] = rd32(E1000_IPAV);
527 regs_buff[46] = rd32(E1000_WUPL);
528
529 /* MAC */
530 regs_buff[47] = rd32(E1000_PCS_CFG0);
531 regs_buff[48] = rd32(E1000_PCS_LCTL);
532 regs_buff[49] = rd32(E1000_PCS_LSTAT);
533 regs_buff[50] = rd32(E1000_PCS_ANADV);
534 regs_buff[51] = rd32(E1000_PCS_LPAB);
535 regs_buff[52] = rd32(E1000_PCS_NPTX);
536 regs_buff[53] = rd32(E1000_PCS_LPABNP);
537
538 /* Statistics */
539 regs_buff[54] = adapter->stats.crcerrs;
540 regs_buff[55] = adapter->stats.algnerrc;
541 regs_buff[56] = adapter->stats.symerrs;
542 regs_buff[57] = adapter->stats.rxerrc;
543 regs_buff[58] = adapter->stats.mpc;
544 regs_buff[59] = adapter->stats.scc;
545 regs_buff[60] = adapter->stats.ecol;
546 regs_buff[61] = adapter->stats.mcc;
547 regs_buff[62] = adapter->stats.latecol;
548 regs_buff[63] = adapter->stats.colc;
549 regs_buff[64] = adapter->stats.dc;
550 regs_buff[65] = adapter->stats.tncrs;
551 regs_buff[66] = adapter->stats.sec;
552 regs_buff[67] = adapter->stats.htdpmc;
553 regs_buff[68] = adapter->stats.rlec;
554 regs_buff[69] = adapter->stats.xonrxc;
555 regs_buff[70] = adapter->stats.xontxc;
556 regs_buff[71] = adapter->stats.xoffrxc;
557 regs_buff[72] = adapter->stats.xofftxc;
558 regs_buff[73] = adapter->stats.fcruc;
559 regs_buff[74] = adapter->stats.prc64;
560 regs_buff[75] = adapter->stats.prc127;
561 regs_buff[76] = adapter->stats.prc255;
562 regs_buff[77] = adapter->stats.prc511;
563 regs_buff[78] = adapter->stats.prc1023;
564 regs_buff[79] = adapter->stats.prc1522;
565 regs_buff[80] = adapter->stats.gprc;
566 regs_buff[81] = adapter->stats.bprc;
567 regs_buff[82] = adapter->stats.mprc;
568 regs_buff[83] = adapter->stats.gptc;
569 regs_buff[84] = adapter->stats.gorc;
570 regs_buff[86] = adapter->stats.gotc;
571 regs_buff[88] = adapter->stats.rnbc;
572 regs_buff[89] = adapter->stats.ruc;
573 regs_buff[90] = adapter->stats.rfc;
574 regs_buff[91] = adapter->stats.roc;
575 regs_buff[92] = adapter->stats.rjc;
576 regs_buff[93] = adapter->stats.mgprc;
577 regs_buff[94] = adapter->stats.mgpdc;
578 regs_buff[95] = adapter->stats.mgptc;
579 regs_buff[96] = adapter->stats.tor;
580 regs_buff[98] = adapter->stats.tot;
581 regs_buff[100] = adapter->stats.tpr;
582 regs_buff[101] = adapter->stats.tpt;
583 regs_buff[102] = adapter->stats.ptc64;
584 regs_buff[103] = adapter->stats.ptc127;
585 regs_buff[104] = adapter->stats.ptc255;
586 regs_buff[105] = adapter->stats.ptc511;
587 regs_buff[106] = adapter->stats.ptc1023;
588 regs_buff[107] = adapter->stats.ptc1522;
589 regs_buff[108] = adapter->stats.mptc;
590 regs_buff[109] = adapter->stats.bptc;
591 regs_buff[110] = adapter->stats.tsctc;
592 regs_buff[111] = adapter->stats.iac;
593 regs_buff[112] = adapter->stats.rpthc;
594 regs_buff[113] = adapter->stats.hgptc;
595 regs_buff[114] = adapter->stats.hgorc;
596 regs_buff[116] = adapter->stats.hgotc;
597 regs_buff[118] = adapter->stats.lenerrs;
598 regs_buff[119] = adapter->stats.scvpc;
599 regs_buff[120] = adapter->stats.hrmpc;
600
601 for (i = 0; i < 4; i++)
602 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
603 for (i = 0; i < 4; i++)
604 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
605 for (i = 0; i < 4; i++)
606 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
607 for (i = 0; i < 4; i++)
608 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
609 for (i = 0; i < 4; i++)
610 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
611 for (i = 0; i < 4; i++)
612 regs_buff[141 + i] = rd32(E1000_RDH(i));
613 for (i = 0; i < 4; i++)
614 regs_buff[145 + i] = rd32(E1000_RDT(i));
615 for (i = 0; i < 4; i++)
616 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
617
618 for (i = 0; i < 10; i++)
619 regs_buff[153 + i] = rd32(E1000_EITR(i));
620 for (i = 0; i < 8; i++)
621 regs_buff[163 + i] = rd32(E1000_IMIR(i));
622 for (i = 0; i < 8; i++)
623 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
624 for (i = 0; i < 16; i++)
625 regs_buff[179 + i] = rd32(E1000_RAL(i));
626 for (i = 0; i < 16; i++)
627 regs_buff[195 + i] = rd32(E1000_RAH(i));
628
629 for (i = 0; i < 4; i++)
630 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
631 for (i = 0; i < 4; i++)
632 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
633 for (i = 0; i < 4; i++)
634 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
635 for (i = 0; i < 4; i++)
636 regs_buff[223 + i] = rd32(E1000_TDH(i));
637 for (i = 0; i < 4; i++)
638 regs_buff[227 + i] = rd32(E1000_TDT(i));
639 for (i = 0; i < 4; i++)
640 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
641 for (i = 0; i < 4; i++)
642 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
643 for (i = 0; i < 4; i++)
644 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
645 for (i = 0; i < 4; i++)
646 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
647
648 for (i = 0; i < 4; i++)
649 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
650 for (i = 0; i < 4; i++)
651 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
652 for (i = 0; i < 32; i++)
653 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
654 for (i = 0; i < 128; i++)
655 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
656 for (i = 0; i < 128; i++)
657 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
658 for (i = 0; i < 4; i++)
659 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
660
661 regs_buff[547] = rd32(E1000_TDFH);
662 regs_buff[548] = rd32(E1000_TDFT);
663 regs_buff[549] = rd32(E1000_TDFHS);
664 regs_buff[550] = rd32(E1000_TDFPC);
665
666 if (hw->mac.type > e1000_82580) {
667 regs_buff[551] = adapter->stats.o2bgptc;
668 regs_buff[552] = adapter->stats.b2ospc;
669 regs_buff[553] = adapter->stats.o2bspc;
670 regs_buff[554] = adapter->stats.b2ogprc;
671 }
672
673 if (hw->mac.type != e1000_82576)
674 return;
675 for (i = 0; i < 12; i++)
676 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
677 for (i = 0; i < 4; i++)
678 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
679 for (i = 0; i < 12; i++)
680 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
681 for (i = 0; i < 12; i++)
682 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
683 for (i = 0; i < 12; i++)
684 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
685 for (i = 0; i < 12; i++)
686 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
687 for (i = 0; i < 12; i++)
688 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
689 for (i = 0; i < 12; i++)
690 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
691
692 for (i = 0; i < 12; i++)
693 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
694 for (i = 0; i < 12; i++)
695 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
696 for (i = 0; i < 12; i++)
697 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
698 for (i = 0; i < 12; i++)
699 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
700 for (i = 0; i < 12; i++)
701 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
702 for (i = 0; i < 12; i++)
703 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
704 for (i = 0; i < 12; i++)
705 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
706 for (i = 0; i < 12; i++)
707 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
708 }
709
710 static int igb_get_eeprom_len(struct net_device *netdev)
711 {
712 struct igb_adapter *adapter = netdev_priv(netdev);
713 return adapter->hw.nvm.word_size * 2;
714 }
715
716 static int igb_get_eeprom(struct net_device *netdev,
717 struct ethtool_eeprom *eeprom, u8 *bytes)
718 {
719 struct igb_adapter *adapter = netdev_priv(netdev);
720 struct e1000_hw *hw = &adapter->hw;
721 u16 *eeprom_buff;
722 int first_word, last_word;
723 int ret_val = 0;
724 u16 i;
725
726 if (eeprom->len == 0)
727 return -EINVAL;
728
729 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
730
731 first_word = eeprom->offset >> 1;
732 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
733
734 eeprom_buff = kmalloc(sizeof(u16) *
735 (last_word - first_word + 1), GFP_KERNEL);
736 if (!eeprom_buff)
737 return -ENOMEM;
738
739 if (hw->nvm.type == e1000_nvm_eeprom_spi)
740 ret_val = hw->nvm.ops.read(hw, first_word,
741 last_word - first_word + 1,
742 eeprom_buff);
743 else {
744 for (i = 0; i < last_word - first_word + 1; i++) {
745 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
746 &eeprom_buff[i]);
747 if (ret_val)
748 break;
749 }
750 }
751
752 /* Device's eeprom is always little-endian, word addressable */
753 for (i = 0; i < last_word - first_word + 1; i++)
754 le16_to_cpus(&eeprom_buff[i]);
755
756 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
757 eeprom->len);
758 kfree(eeprom_buff);
759
760 return ret_val;
761 }
762
763 static int igb_set_eeprom(struct net_device *netdev,
764 struct ethtool_eeprom *eeprom, u8 *bytes)
765 {
766 struct igb_adapter *adapter = netdev_priv(netdev);
767 struct e1000_hw *hw = &adapter->hw;
768 u16 *eeprom_buff;
769 void *ptr;
770 int max_len, first_word, last_word, ret_val = 0;
771 u16 i;
772
773 if (eeprom->len == 0)
774 return -EOPNOTSUPP;
775
776 if ((hw->mac.type >= e1000_i210) &&
777 !igb_get_flash_presence_i210(hw)) {
778 return -EOPNOTSUPP;
779 }
780
781 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
782 return -EFAULT;
783
784 max_len = hw->nvm.word_size * 2;
785
786 first_word = eeprom->offset >> 1;
787 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
788 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
789 if (!eeprom_buff)
790 return -ENOMEM;
791
792 ptr = (void *)eeprom_buff;
793
794 if (eeprom->offset & 1) {
795 /* need read/modify/write of first changed EEPROM word
796 * only the second byte of the word is being modified
797 */
798 ret_val = hw->nvm.ops.read(hw, first_word, 1,
799 &eeprom_buff[0]);
800 ptr++;
801 }
802 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
803 /* need read/modify/write of last changed EEPROM word
804 * only the first byte of the word is being modified
805 */
806 ret_val = hw->nvm.ops.read(hw, last_word, 1,
807 &eeprom_buff[last_word - first_word]);
808 }
809
810 /* Device's eeprom is always little-endian, word addressable */
811 for (i = 0; i < last_word - first_word + 1; i++)
812 le16_to_cpus(&eeprom_buff[i]);
813
814 memcpy(ptr, bytes, eeprom->len);
815
816 for (i = 0; i < last_word - first_word + 1; i++)
817 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
818
819 ret_val = hw->nvm.ops.write(hw, first_word,
820 last_word - first_word + 1, eeprom_buff);
821
822 /* Update the checksum if nvm write succeeded */
823 if (ret_val == 0)
824 hw->nvm.ops.update(hw);
825
826 igb_set_fw_version(adapter);
827 kfree(eeprom_buff);
828 return ret_val;
829 }
830
831 static void igb_get_drvinfo(struct net_device *netdev,
832 struct ethtool_drvinfo *drvinfo)
833 {
834 struct igb_adapter *adapter = netdev_priv(netdev);
835
836 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
837 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
838
839 /* EEPROM image version # is reported as firmware version # for
840 * 82575 controllers
841 */
842 strlcpy(drvinfo->fw_version, adapter->fw_version,
843 sizeof(drvinfo->fw_version));
844 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
845 sizeof(drvinfo->bus_info));
846 drvinfo->n_stats = IGB_STATS_LEN;
847 drvinfo->testinfo_len = IGB_TEST_LEN;
848 drvinfo->regdump_len = igb_get_regs_len(netdev);
849 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
850 }
851
852 static void igb_get_ringparam(struct net_device *netdev,
853 struct ethtool_ringparam *ring)
854 {
855 struct igb_adapter *adapter = netdev_priv(netdev);
856
857 ring->rx_max_pending = IGB_MAX_RXD;
858 ring->tx_max_pending = IGB_MAX_TXD;
859 ring->rx_pending = adapter->rx_ring_count;
860 ring->tx_pending = adapter->tx_ring_count;
861 }
862
863 static int igb_set_ringparam(struct net_device *netdev,
864 struct ethtool_ringparam *ring)
865 {
866 struct igb_adapter *adapter = netdev_priv(netdev);
867 struct igb_ring *temp_ring;
868 int i, err = 0;
869 u16 new_rx_count, new_tx_count;
870
871 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
872 return -EINVAL;
873
874 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
875 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
876 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
877
878 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
879 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
880 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
881
882 if ((new_tx_count == adapter->tx_ring_count) &&
883 (new_rx_count == adapter->rx_ring_count)) {
884 /* nothing to do */
885 return 0;
886 }
887
888 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
889 msleep(1);
890
891 if (!netif_running(adapter->netdev)) {
892 for (i = 0; i < adapter->num_tx_queues; i++)
893 adapter->tx_ring[i]->count = new_tx_count;
894 for (i = 0; i < adapter->num_rx_queues; i++)
895 adapter->rx_ring[i]->count = new_rx_count;
896 adapter->tx_ring_count = new_tx_count;
897 adapter->rx_ring_count = new_rx_count;
898 goto clear_reset;
899 }
900
901 if (adapter->num_tx_queues > adapter->num_rx_queues)
902 temp_ring = vmalloc(adapter->num_tx_queues *
903 sizeof(struct igb_ring));
904 else
905 temp_ring = vmalloc(adapter->num_rx_queues *
906 sizeof(struct igb_ring));
907
908 if (!temp_ring) {
909 err = -ENOMEM;
910 goto clear_reset;
911 }
912
913 igb_down(adapter);
914
915 /* We can't just free everything and then setup again,
916 * because the ISRs in MSI-X mode get passed pointers
917 * to the Tx and Rx ring structs.
918 */
919 if (new_tx_count != adapter->tx_ring_count) {
920 for (i = 0; i < adapter->num_tx_queues; i++) {
921 memcpy(&temp_ring[i], adapter->tx_ring[i],
922 sizeof(struct igb_ring));
923
924 temp_ring[i].count = new_tx_count;
925 err = igb_setup_tx_resources(&temp_ring[i]);
926 if (err) {
927 while (i) {
928 i--;
929 igb_free_tx_resources(&temp_ring[i]);
930 }
931 goto err_setup;
932 }
933 }
934
935 for (i = 0; i < adapter->num_tx_queues; i++) {
936 igb_free_tx_resources(adapter->tx_ring[i]);
937
938 memcpy(adapter->tx_ring[i], &temp_ring[i],
939 sizeof(struct igb_ring));
940 }
941
942 adapter->tx_ring_count = new_tx_count;
943 }
944
945 if (new_rx_count != adapter->rx_ring_count) {
946 for (i = 0; i < adapter->num_rx_queues; i++) {
947 memcpy(&temp_ring[i], adapter->rx_ring[i],
948 sizeof(struct igb_ring));
949
950 temp_ring[i].count = new_rx_count;
951 err = igb_setup_rx_resources(&temp_ring[i]);
952 if (err) {
953 while (i) {
954 i--;
955 igb_free_rx_resources(&temp_ring[i]);
956 }
957 goto err_setup;
958 }
959
960 }
961
962 for (i = 0; i < adapter->num_rx_queues; i++) {
963 igb_free_rx_resources(adapter->rx_ring[i]);
964
965 memcpy(adapter->rx_ring[i], &temp_ring[i],
966 sizeof(struct igb_ring));
967 }
968
969 adapter->rx_ring_count = new_rx_count;
970 }
971 err_setup:
972 igb_up(adapter);
973 vfree(temp_ring);
974 clear_reset:
975 clear_bit(__IGB_RESETTING, &adapter->state);
976 return err;
977 }
978
979 /* ethtool register test data */
980 struct igb_reg_test {
981 u16 reg;
982 u16 reg_offset;
983 u16 array_len;
984 u16 test_type;
985 u32 mask;
986 u32 write;
987 };
988
989 /* In the hardware, registers are laid out either singly, in arrays
990 * spaced 0x100 bytes apart, or in contiguous tables. We assume
991 * most tests take place on arrays or single registers (handled
992 * as a single-element array) and special-case the tables.
993 * Table tests are always pattern tests.
994 *
995 * We also make provision for some required setup steps by specifying
996 * registers to be written without any read-back testing.
997 */
998
999 #define PATTERN_TEST 1
1000 #define SET_READ_TEST 2
1001 #define WRITE_NO_TEST 3
1002 #define TABLE32_TEST 4
1003 #define TABLE64_TEST_LO 5
1004 #define TABLE64_TEST_HI 6
1005
1006 /* i210 reg test */
1007 static struct igb_reg_test reg_test_i210[] = {
1008 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1009 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1010 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1011 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1012 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1013 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1014 /* RDH is read-only for i210, only test RDT. */
1015 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1016 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1017 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1018 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1019 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1020 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1021 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1022 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1023 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1024 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1025 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1026 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1027 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1028 0xFFFFFFFF, 0xFFFFFFFF },
1029 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1030 0x900FFFFF, 0xFFFFFFFF },
1031 { E1000_MTA, 0, 128, TABLE32_TEST,
1032 0xFFFFFFFF, 0xFFFFFFFF },
1033 { 0, 0, 0, 0, 0 }
1034 };
1035
1036 /* i350 reg test */
1037 static struct igb_reg_test reg_test_i350[] = {
1038 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1039 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1040 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1041 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1042 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1043 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1044 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1045 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1046 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1047 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1048 /* RDH is read-only for i350, only test RDT. */
1049 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1050 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1051 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1052 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1053 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1054 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1055 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1056 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1057 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1058 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1059 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1060 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1061 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1062 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1063 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1064 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1065 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1066 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1067 0xFFFFFFFF, 0xFFFFFFFF },
1068 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1069 0xC3FFFFFF, 0xFFFFFFFF },
1070 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1071 0xFFFFFFFF, 0xFFFFFFFF },
1072 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1073 0xC3FFFFFF, 0xFFFFFFFF },
1074 { E1000_MTA, 0, 128, TABLE32_TEST,
1075 0xFFFFFFFF, 0xFFFFFFFF },
1076 { 0, 0, 0, 0 }
1077 };
1078
1079 /* 82580 reg test */
1080 static struct igb_reg_test reg_test_82580[] = {
1081 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1082 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1083 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1084 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1085 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1086 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1087 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1088 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1089 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1090 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1091 /* RDH is read-only for 82580, only test RDT. */
1092 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1093 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1094 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1095 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1096 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1097 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1098 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1099 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1100 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1101 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1102 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1103 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1104 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1105 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1106 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1107 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1108 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1109 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1110 0xFFFFFFFF, 0xFFFFFFFF },
1111 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1112 0x83FFFFFF, 0xFFFFFFFF },
1113 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1114 0xFFFFFFFF, 0xFFFFFFFF },
1115 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1116 0x83FFFFFF, 0xFFFFFFFF },
1117 { E1000_MTA, 0, 128, TABLE32_TEST,
1118 0xFFFFFFFF, 0xFFFFFFFF },
1119 { 0, 0, 0, 0 }
1120 };
1121
1122 /* 82576 reg test */
1123 static struct igb_reg_test reg_test_82576[] = {
1124 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1125 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1126 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1127 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1128 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1129 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1130 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1131 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1132 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1133 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1134 /* Enable all RX queues before testing. */
1135 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1136 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1137 /* RDH is read-only for 82576, only test RDT. */
1138 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1139 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1140 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1141 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1142 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1143 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1144 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1145 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1146 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1147 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1148 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1149 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1150 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1151 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1152 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1153 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1154 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1155 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1156 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1157 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1158 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1159 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1160 { 0, 0, 0, 0 }
1161 };
1162
1163 /* 82575 register test */
1164 static struct igb_reg_test reg_test_82575[] = {
1165 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1166 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1167 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1168 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1169 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1170 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1171 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1172 /* Enable all four RX queues before testing. */
1173 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1174 /* RDH is read-only for 82575, only test RDT. */
1175 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1176 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1177 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1178 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1179 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1180 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1181 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1182 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1183 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1184 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1185 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1186 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1187 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1188 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1189 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1190 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1191 { 0, 0, 0, 0 }
1192 };
1193
1194 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1195 int reg, u32 mask, u32 write)
1196 {
1197 struct e1000_hw *hw = &adapter->hw;
1198 u32 pat, val;
1199 static const u32 _test[] =
1200 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1201 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1202 wr32(reg, (_test[pat] & write));
1203 val = rd32(reg) & mask;
1204 if (val != (_test[pat] & write & mask)) {
1205 dev_err(&adapter->pdev->dev,
1206 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1207 reg, val, (_test[pat] & write & mask));
1208 *data = reg;
1209 return 1;
1210 }
1211 }
1212
1213 return 0;
1214 }
1215
1216 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1217 int reg, u32 mask, u32 write)
1218 {
1219 struct e1000_hw *hw = &adapter->hw;
1220 u32 val;
1221 wr32(reg, write & mask);
1222 val = rd32(reg);
1223 if ((write & mask) != (val & mask)) {
1224 dev_err(&adapter->pdev->dev,
1225 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg,
1226 (val & mask), (write & mask));
1227 *data = reg;
1228 return 1;
1229 }
1230
1231 return 0;
1232 }
1233
1234 #define REG_PATTERN_TEST(reg, mask, write) \
1235 do { \
1236 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1237 return 1; \
1238 } while (0)
1239
1240 #define REG_SET_AND_CHECK(reg, mask, write) \
1241 do { \
1242 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1243 return 1; \
1244 } while (0)
1245
1246 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1247 {
1248 struct e1000_hw *hw = &adapter->hw;
1249 struct igb_reg_test *test;
1250 u32 value, before, after;
1251 u32 i, toggle;
1252
1253 switch (adapter->hw.mac.type) {
1254 case e1000_i350:
1255 case e1000_i354:
1256 test = reg_test_i350;
1257 toggle = 0x7FEFF3FF;
1258 break;
1259 case e1000_i210:
1260 case e1000_i211:
1261 test = reg_test_i210;
1262 toggle = 0x7FEFF3FF;
1263 break;
1264 case e1000_82580:
1265 test = reg_test_82580;
1266 toggle = 0x7FEFF3FF;
1267 break;
1268 case e1000_82576:
1269 test = reg_test_82576;
1270 toggle = 0x7FFFF3FF;
1271 break;
1272 default:
1273 test = reg_test_82575;
1274 toggle = 0x7FFFF3FF;
1275 break;
1276 }
1277
1278 /* Because the status register is such a special case,
1279 * we handle it separately from the rest of the register
1280 * tests. Some bits are read-only, some toggle, and some
1281 * are writable on newer MACs.
1282 */
1283 before = rd32(E1000_STATUS);
1284 value = (rd32(E1000_STATUS) & toggle);
1285 wr32(E1000_STATUS, toggle);
1286 after = rd32(E1000_STATUS) & toggle;
1287 if (value != after) {
1288 dev_err(&adapter->pdev->dev,
1289 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1290 after, value);
1291 *data = 1;
1292 return 1;
1293 }
1294 /* restore previous status */
1295 wr32(E1000_STATUS, before);
1296
1297 /* Perform the remainder of the register test, looping through
1298 * the test table until we either fail or reach the null entry.
1299 */
1300 while (test->reg) {
1301 for (i = 0; i < test->array_len; i++) {
1302 switch (test->test_type) {
1303 case PATTERN_TEST:
1304 REG_PATTERN_TEST(test->reg +
1305 (i * test->reg_offset),
1306 test->mask,
1307 test->write);
1308 break;
1309 case SET_READ_TEST:
1310 REG_SET_AND_CHECK(test->reg +
1311 (i * test->reg_offset),
1312 test->mask,
1313 test->write);
1314 break;
1315 case WRITE_NO_TEST:
1316 writel(test->write,
1317 (adapter->hw.hw_addr + test->reg)
1318 + (i * test->reg_offset));
1319 break;
1320 case TABLE32_TEST:
1321 REG_PATTERN_TEST(test->reg + (i * 4),
1322 test->mask,
1323 test->write);
1324 break;
1325 case TABLE64_TEST_LO:
1326 REG_PATTERN_TEST(test->reg + (i * 8),
1327 test->mask,
1328 test->write);
1329 break;
1330 case TABLE64_TEST_HI:
1331 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1332 test->mask,
1333 test->write);
1334 break;
1335 }
1336 }
1337 test++;
1338 }
1339
1340 *data = 0;
1341 return 0;
1342 }
1343
1344 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1345 {
1346 struct e1000_hw *hw = &adapter->hw;
1347
1348 *data = 0;
1349
1350 /* Validate eeprom on all parts but flashless */
1351 switch (hw->mac.type) {
1352 case e1000_i210:
1353 case e1000_i211:
1354 if (igb_get_flash_presence_i210(hw)) {
1355 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1356 *data = 2;
1357 }
1358 break;
1359 default:
1360 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1361 *data = 2;
1362 break;
1363 }
1364
1365 return *data;
1366 }
1367
1368 static irqreturn_t igb_test_intr(int irq, void *data)
1369 {
1370 struct igb_adapter *adapter = (struct igb_adapter *) data;
1371 struct e1000_hw *hw = &adapter->hw;
1372
1373 adapter->test_icr |= rd32(E1000_ICR);
1374
1375 return IRQ_HANDLED;
1376 }
1377
1378 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1379 {
1380 struct e1000_hw *hw = &adapter->hw;
1381 struct net_device *netdev = adapter->netdev;
1382 u32 mask, ics_mask, i = 0, shared_int = true;
1383 u32 irq = adapter->pdev->irq;
1384
1385 *data = 0;
1386
1387 /* Hook up test interrupt handler just for this test */
1388 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1389 if (request_irq(adapter->msix_entries[0].vector,
1390 igb_test_intr, 0, netdev->name, adapter)) {
1391 *data = 1;
1392 return -1;
1393 }
1394 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1395 shared_int = false;
1396 if (request_irq(irq,
1397 igb_test_intr, 0, netdev->name, adapter)) {
1398 *data = 1;
1399 return -1;
1400 }
1401 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1402 netdev->name, adapter)) {
1403 shared_int = false;
1404 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1405 netdev->name, adapter)) {
1406 *data = 1;
1407 return -1;
1408 }
1409 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1410 (shared_int ? "shared" : "unshared"));
1411
1412 /* Disable all the interrupts */
1413 wr32(E1000_IMC, ~0);
1414 wrfl();
1415 msleep(10);
1416
1417 /* Define all writable bits for ICS */
1418 switch (hw->mac.type) {
1419 case e1000_82575:
1420 ics_mask = 0x37F47EDD;
1421 break;
1422 case e1000_82576:
1423 ics_mask = 0x77D4FBFD;
1424 break;
1425 case e1000_82580:
1426 ics_mask = 0x77DCFED5;
1427 break;
1428 case e1000_i350:
1429 case e1000_i354:
1430 case e1000_i210:
1431 case e1000_i211:
1432 ics_mask = 0x77DCFED5;
1433 break;
1434 default:
1435 ics_mask = 0x7FFFFFFF;
1436 break;
1437 }
1438
1439 /* Test each interrupt */
1440 for (; i < 31; i++) {
1441 /* Interrupt to test */
1442 mask = 1 << i;
1443
1444 if (!(mask & ics_mask))
1445 continue;
1446
1447 if (!shared_int) {
1448 /* Disable the interrupt to be reported in
1449 * the cause register and then force the same
1450 * interrupt and see if one gets posted. If
1451 * an interrupt was posted to the bus, the
1452 * test failed.
1453 */
1454 adapter->test_icr = 0;
1455
1456 /* Flush any pending interrupts */
1457 wr32(E1000_ICR, ~0);
1458
1459 wr32(E1000_IMC, mask);
1460 wr32(E1000_ICS, mask);
1461 wrfl();
1462 msleep(10);
1463
1464 if (adapter->test_icr & mask) {
1465 *data = 3;
1466 break;
1467 }
1468 }
1469
1470 /* Enable the interrupt to be reported in
1471 * the cause register and then force the same
1472 * interrupt and see if one gets posted. If
1473 * an interrupt was not posted to the bus, the
1474 * test failed.
1475 */
1476 adapter->test_icr = 0;
1477
1478 /* Flush any pending interrupts */
1479 wr32(E1000_ICR, ~0);
1480
1481 wr32(E1000_IMS, mask);
1482 wr32(E1000_ICS, mask);
1483 wrfl();
1484 msleep(10);
1485
1486 if (!(adapter->test_icr & mask)) {
1487 *data = 4;
1488 break;
1489 }
1490
1491 if (!shared_int) {
1492 /* Disable the other interrupts to be reported in
1493 * the cause register and then force the other
1494 * interrupts and see if any get posted. If
1495 * an interrupt was posted to the bus, the
1496 * test failed.
1497 */
1498 adapter->test_icr = 0;
1499
1500 /* Flush any pending interrupts */
1501 wr32(E1000_ICR, ~0);
1502
1503 wr32(E1000_IMC, ~mask);
1504 wr32(E1000_ICS, ~mask);
1505 wrfl();
1506 msleep(10);
1507
1508 if (adapter->test_icr & mask) {
1509 *data = 5;
1510 break;
1511 }
1512 }
1513 }
1514
1515 /* Disable all the interrupts */
1516 wr32(E1000_IMC, ~0);
1517 wrfl();
1518 msleep(10);
1519
1520 /* Unhook test interrupt handler */
1521 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1522 free_irq(adapter->msix_entries[0].vector, adapter);
1523 else
1524 free_irq(irq, adapter);
1525
1526 return *data;
1527 }
1528
1529 static void igb_free_desc_rings(struct igb_adapter *adapter)
1530 {
1531 igb_free_tx_resources(&adapter->test_tx_ring);
1532 igb_free_rx_resources(&adapter->test_rx_ring);
1533 }
1534
1535 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1536 {
1537 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1538 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1539 struct e1000_hw *hw = &adapter->hw;
1540 int ret_val;
1541
1542 /* Setup Tx descriptor ring and Tx buffers */
1543 tx_ring->count = IGB_DEFAULT_TXD;
1544 tx_ring->dev = &adapter->pdev->dev;
1545 tx_ring->netdev = adapter->netdev;
1546 tx_ring->reg_idx = adapter->vfs_allocated_count;
1547
1548 if (igb_setup_tx_resources(tx_ring)) {
1549 ret_val = 1;
1550 goto err_nomem;
1551 }
1552
1553 igb_setup_tctl(adapter);
1554 igb_configure_tx_ring(adapter, tx_ring);
1555
1556 /* Setup Rx descriptor ring and Rx buffers */
1557 rx_ring->count = IGB_DEFAULT_RXD;
1558 rx_ring->dev = &adapter->pdev->dev;
1559 rx_ring->netdev = adapter->netdev;
1560 rx_ring->reg_idx = adapter->vfs_allocated_count;
1561
1562 if (igb_setup_rx_resources(rx_ring)) {
1563 ret_val = 3;
1564 goto err_nomem;
1565 }
1566
1567 /* set the default queue to queue 0 of PF */
1568 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1569
1570 /* enable receive ring */
1571 igb_setup_rctl(adapter);
1572 igb_configure_rx_ring(adapter, rx_ring);
1573
1574 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1575
1576 return 0;
1577
1578 err_nomem:
1579 igb_free_desc_rings(adapter);
1580 return ret_val;
1581 }
1582
1583 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1584 {
1585 struct e1000_hw *hw = &adapter->hw;
1586
1587 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1588 igb_write_phy_reg(hw, 29, 0x001F);
1589 igb_write_phy_reg(hw, 30, 0x8FFC);
1590 igb_write_phy_reg(hw, 29, 0x001A);
1591 igb_write_phy_reg(hw, 30, 0x8FF0);
1592 }
1593
1594 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1595 {
1596 struct e1000_hw *hw = &adapter->hw;
1597 u32 ctrl_reg = 0;
1598
1599 hw->mac.autoneg = false;
1600
1601 if (hw->phy.type == e1000_phy_m88) {
1602 if (hw->phy.id != I210_I_PHY_ID) {
1603 /* Auto-MDI/MDIX Off */
1604 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1605 /* reset to update Auto-MDI/MDIX */
1606 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1607 /* autoneg off */
1608 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1609 } else {
1610 /* force 1000, set loopback */
1611 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1612 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1613 }
1614 } else if (hw->phy.type == e1000_phy_82580) {
1615 /* enable MII loopback */
1616 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1617 }
1618
1619 /* add small delay to avoid loopback test failure */
1620 msleep(50);
1621
1622 /* force 1000, set loopback */
1623 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1624
1625 /* Now set up the MAC to the same speed/duplex as the PHY. */
1626 ctrl_reg = rd32(E1000_CTRL);
1627 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1628 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1629 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1630 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1631 E1000_CTRL_FD | /* Force Duplex to FULL */
1632 E1000_CTRL_SLU); /* Set link up enable bit */
1633
1634 if (hw->phy.type == e1000_phy_m88)
1635 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1636
1637 wr32(E1000_CTRL, ctrl_reg);
1638
1639 /* Disable the receiver on the PHY so when a cable is plugged in, the
1640 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1641 */
1642 if (hw->phy.type == e1000_phy_m88)
1643 igb_phy_disable_receiver(adapter);
1644
1645 mdelay(500);
1646 return 0;
1647 }
1648
1649 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1650 {
1651 return igb_integrated_phy_loopback(adapter);
1652 }
1653
1654 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1655 {
1656 struct e1000_hw *hw = &adapter->hw;
1657 u32 reg;
1658
1659 reg = rd32(E1000_CTRL_EXT);
1660
1661 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1662 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1663 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1664 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1665 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1666 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1667 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1668
1669 /* Enable DH89xxCC MPHY for near end loopback */
1670 reg = rd32(E1000_MPHY_ADDR_CTL);
1671 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1672 E1000_MPHY_PCS_CLK_REG_OFFSET;
1673 wr32(E1000_MPHY_ADDR_CTL, reg);
1674
1675 reg = rd32(E1000_MPHY_DATA);
1676 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1677 wr32(E1000_MPHY_DATA, reg);
1678 }
1679
1680 reg = rd32(E1000_RCTL);
1681 reg |= E1000_RCTL_LBM_TCVR;
1682 wr32(E1000_RCTL, reg);
1683
1684 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1685
1686 reg = rd32(E1000_CTRL);
1687 reg &= ~(E1000_CTRL_RFCE |
1688 E1000_CTRL_TFCE |
1689 E1000_CTRL_LRST);
1690 reg |= E1000_CTRL_SLU |
1691 E1000_CTRL_FD;
1692 wr32(E1000_CTRL, reg);
1693
1694 /* Unset switch control to serdes energy detect */
1695 reg = rd32(E1000_CONNSW);
1696 reg &= ~E1000_CONNSW_ENRGSRC;
1697 wr32(E1000_CONNSW, reg);
1698
1699 /* Unset sigdetect for SERDES loopback on
1700 * 82580 and newer devices.
1701 */
1702 if (hw->mac.type >= e1000_82580) {
1703 reg = rd32(E1000_PCS_CFG0);
1704 reg |= E1000_PCS_CFG_IGN_SD;
1705 wr32(E1000_PCS_CFG0, reg);
1706 }
1707
1708 /* Set PCS register for forced speed */
1709 reg = rd32(E1000_PCS_LCTL);
1710 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1711 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1712 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1713 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1714 E1000_PCS_LCTL_FSD | /* Force Speed */
1715 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1716 wr32(E1000_PCS_LCTL, reg);
1717
1718 return 0;
1719 }
1720
1721 return igb_set_phy_loopback(adapter);
1722 }
1723
1724 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1725 {
1726 struct e1000_hw *hw = &adapter->hw;
1727 u32 rctl;
1728 u16 phy_reg;
1729
1730 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1731 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1732 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1733 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1734 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1735 u32 reg;
1736
1737 /* Disable near end loopback on DH89xxCC */
1738 reg = rd32(E1000_MPHY_ADDR_CTL);
1739 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1740 E1000_MPHY_PCS_CLK_REG_OFFSET;
1741 wr32(E1000_MPHY_ADDR_CTL, reg);
1742
1743 reg = rd32(E1000_MPHY_DATA);
1744 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1745 wr32(E1000_MPHY_DATA, reg);
1746 }
1747
1748 rctl = rd32(E1000_RCTL);
1749 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1750 wr32(E1000_RCTL, rctl);
1751
1752 hw->mac.autoneg = true;
1753 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1754 if (phy_reg & MII_CR_LOOPBACK) {
1755 phy_reg &= ~MII_CR_LOOPBACK;
1756 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1757 igb_phy_sw_reset(hw);
1758 }
1759 }
1760
1761 static void igb_create_lbtest_frame(struct sk_buff *skb,
1762 unsigned int frame_size)
1763 {
1764 memset(skb->data, 0xFF, frame_size);
1765 frame_size /= 2;
1766 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1767 memset(&skb->data[frame_size + 10], 0xBE, 1);
1768 memset(&skb->data[frame_size + 12], 0xAF, 1);
1769 }
1770
1771 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1772 unsigned int frame_size)
1773 {
1774 unsigned char *data;
1775 bool match = true;
1776
1777 frame_size >>= 1;
1778
1779 data = kmap(rx_buffer->page);
1780
1781 if (data[3] != 0xFF ||
1782 data[frame_size + 10] != 0xBE ||
1783 data[frame_size + 12] != 0xAF)
1784 match = false;
1785
1786 kunmap(rx_buffer->page);
1787
1788 return match;
1789 }
1790
1791 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1792 struct igb_ring *tx_ring,
1793 unsigned int size)
1794 {
1795 union e1000_adv_rx_desc *rx_desc;
1796 struct igb_rx_buffer *rx_buffer_info;
1797 struct igb_tx_buffer *tx_buffer_info;
1798 u16 rx_ntc, tx_ntc, count = 0;
1799
1800 /* initialize next to clean and descriptor values */
1801 rx_ntc = rx_ring->next_to_clean;
1802 tx_ntc = tx_ring->next_to_clean;
1803 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1804
1805 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
1806 /* check Rx buffer */
1807 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1808
1809 /* sync Rx buffer for CPU read */
1810 dma_sync_single_for_cpu(rx_ring->dev,
1811 rx_buffer_info->dma,
1812 IGB_RX_BUFSZ,
1813 DMA_FROM_DEVICE);
1814
1815 /* verify contents of skb */
1816 if (igb_check_lbtest_frame(rx_buffer_info, size))
1817 count++;
1818
1819 /* sync Rx buffer for device write */
1820 dma_sync_single_for_device(rx_ring->dev,
1821 rx_buffer_info->dma,
1822 IGB_RX_BUFSZ,
1823 DMA_FROM_DEVICE);
1824
1825 /* unmap buffer on Tx side */
1826 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1827 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1828
1829 /* increment Rx/Tx next to clean counters */
1830 rx_ntc++;
1831 if (rx_ntc == rx_ring->count)
1832 rx_ntc = 0;
1833 tx_ntc++;
1834 if (tx_ntc == tx_ring->count)
1835 tx_ntc = 0;
1836
1837 /* fetch next descriptor */
1838 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1839 }
1840
1841 netdev_tx_reset_queue(txring_txq(tx_ring));
1842
1843 /* re-map buffers to ring, store next to clean values */
1844 igb_alloc_rx_buffers(rx_ring, count);
1845 rx_ring->next_to_clean = rx_ntc;
1846 tx_ring->next_to_clean = tx_ntc;
1847
1848 return count;
1849 }
1850
1851 static int igb_run_loopback_test(struct igb_adapter *adapter)
1852 {
1853 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1854 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1855 u16 i, j, lc, good_cnt;
1856 int ret_val = 0;
1857 unsigned int size = IGB_RX_HDR_LEN;
1858 netdev_tx_t tx_ret_val;
1859 struct sk_buff *skb;
1860
1861 /* allocate test skb */
1862 skb = alloc_skb(size, GFP_KERNEL);
1863 if (!skb)
1864 return 11;
1865
1866 /* place data into test skb */
1867 igb_create_lbtest_frame(skb, size);
1868 skb_put(skb, size);
1869
1870 /* Calculate the loop count based on the largest descriptor ring
1871 * The idea is to wrap the largest ring a number of times using 64
1872 * send/receive pairs during each loop
1873 */
1874
1875 if (rx_ring->count <= tx_ring->count)
1876 lc = ((tx_ring->count / 64) * 2) + 1;
1877 else
1878 lc = ((rx_ring->count / 64) * 2) + 1;
1879
1880 for (j = 0; j <= lc; j++) { /* loop count loop */
1881 /* reset count of good packets */
1882 good_cnt = 0;
1883
1884 /* place 64 packets on the transmit queue*/
1885 for (i = 0; i < 64; i++) {
1886 skb_get(skb);
1887 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1888 if (tx_ret_val == NETDEV_TX_OK)
1889 good_cnt++;
1890 }
1891
1892 if (good_cnt != 64) {
1893 ret_val = 12;
1894 break;
1895 }
1896
1897 /* allow 200 milliseconds for packets to go from Tx to Rx */
1898 msleep(200);
1899
1900 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1901 if (good_cnt != 64) {
1902 ret_val = 13;
1903 break;
1904 }
1905 } /* end loop count loop */
1906
1907 /* free the original skb */
1908 kfree_skb(skb);
1909
1910 return ret_val;
1911 }
1912
1913 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1914 {
1915 /* PHY loopback cannot be performed if SoL/IDER
1916 * sessions are active
1917 */
1918 if (igb_check_reset_block(&adapter->hw)) {
1919 dev_err(&adapter->pdev->dev,
1920 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1921 *data = 0;
1922 goto out;
1923 }
1924
1925 if (adapter->hw.mac.type == e1000_i354) {
1926 dev_info(&adapter->pdev->dev,
1927 "Loopback test not supported on i354.\n");
1928 *data = 0;
1929 goto out;
1930 }
1931 *data = igb_setup_desc_rings(adapter);
1932 if (*data)
1933 goto out;
1934 *data = igb_setup_loopback_test(adapter);
1935 if (*data)
1936 goto err_loopback;
1937 *data = igb_run_loopback_test(adapter);
1938 igb_loopback_cleanup(adapter);
1939
1940 err_loopback:
1941 igb_free_desc_rings(adapter);
1942 out:
1943 return *data;
1944 }
1945
1946 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1947 {
1948 struct e1000_hw *hw = &adapter->hw;
1949 *data = 0;
1950 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1951 int i = 0;
1952 hw->mac.serdes_has_link = false;
1953
1954 /* On some blade server designs, link establishment
1955 * could take as long as 2-3 minutes
1956 */
1957 do {
1958 hw->mac.ops.check_for_link(&adapter->hw);
1959 if (hw->mac.serdes_has_link)
1960 return *data;
1961 msleep(20);
1962 } while (i++ < 3750);
1963
1964 *data = 1;
1965 } else {
1966 hw->mac.ops.check_for_link(&adapter->hw);
1967 if (hw->mac.autoneg)
1968 msleep(5000);
1969
1970 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1971 *data = 1;
1972 }
1973 return *data;
1974 }
1975
1976 static void igb_diag_test(struct net_device *netdev,
1977 struct ethtool_test *eth_test, u64 *data)
1978 {
1979 struct igb_adapter *adapter = netdev_priv(netdev);
1980 u16 autoneg_advertised;
1981 u8 forced_speed_duplex, autoneg;
1982 bool if_running = netif_running(netdev);
1983
1984 set_bit(__IGB_TESTING, &adapter->state);
1985
1986 /* can't do offline tests on media switching devices */
1987 if (adapter->hw.dev_spec._82575.mas_capable)
1988 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
1989 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1990 /* Offline tests */
1991
1992 /* save speed, duplex, autoneg settings */
1993 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1994 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1995 autoneg = adapter->hw.mac.autoneg;
1996
1997 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1998
1999 /* power up link for link test */
2000 igb_power_up_link(adapter);
2001
2002 /* Link test performed before hardware reset so autoneg doesn't
2003 * interfere with test result
2004 */
2005 if (igb_link_test(adapter, &data[4]))
2006 eth_test->flags |= ETH_TEST_FL_FAILED;
2007
2008 if (if_running)
2009 /* indicate we're in test mode */
2010 dev_close(netdev);
2011 else
2012 igb_reset(adapter);
2013
2014 if (igb_reg_test(adapter, &data[0]))
2015 eth_test->flags |= ETH_TEST_FL_FAILED;
2016
2017 igb_reset(adapter);
2018 if (igb_eeprom_test(adapter, &data[1]))
2019 eth_test->flags |= ETH_TEST_FL_FAILED;
2020
2021 igb_reset(adapter);
2022 if (igb_intr_test(adapter, &data[2]))
2023 eth_test->flags |= ETH_TEST_FL_FAILED;
2024
2025 igb_reset(adapter);
2026 /* power up link for loopback test */
2027 igb_power_up_link(adapter);
2028 if (igb_loopback_test(adapter, &data[3]))
2029 eth_test->flags |= ETH_TEST_FL_FAILED;
2030
2031 /* restore speed, duplex, autoneg settings */
2032 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2033 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2034 adapter->hw.mac.autoneg = autoneg;
2035
2036 /* force this routine to wait until autoneg complete/timeout */
2037 adapter->hw.phy.autoneg_wait_to_complete = true;
2038 igb_reset(adapter);
2039 adapter->hw.phy.autoneg_wait_to_complete = false;
2040
2041 clear_bit(__IGB_TESTING, &adapter->state);
2042 if (if_running)
2043 dev_open(netdev);
2044 } else {
2045 dev_info(&adapter->pdev->dev, "online testing starting\n");
2046
2047 /* PHY is powered down when interface is down */
2048 if (if_running && igb_link_test(adapter, &data[4]))
2049 eth_test->flags |= ETH_TEST_FL_FAILED;
2050 else
2051 data[4] = 0;
2052
2053 /* Online tests aren't run; pass by default */
2054 data[0] = 0;
2055 data[1] = 0;
2056 data[2] = 0;
2057 data[3] = 0;
2058
2059 clear_bit(__IGB_TESTING, &adapter->state);
2060 }
2061 msleep_interruptible(4 * 1000);
2062 }
2063
2064 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2065 {
2066 struct igb_adapter *adapter = netdev_priv(netdev);
2067
2068 wol->wolopts = 0;
2069
2070 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2071 return;
2072
2073 wol->supported = WAKE_UCAST | WAKE_MCAST |
2074 WAKE_BCAST | WAKE_MAGIC |
2075 WAKE_PHY;
2076
2077 /* apply any specific unsupported masks here */
2078 switch (adapter->hw.device_id) {
2079 default:
2080 break;
2081 }
2082
2083 if (adapter->wol & E1000_WUFC_EX)
2084 wol->wolopts |= WAKE_UCAST;
2085 if (adapter->wol & E1000_WUFC_MC)
2086 wol->wolopts |= WAKE_MCAST;
2087 if (adapter->wol & E1000_WUFC_BC)
2088 wol->wolopts |= WAKE_BCAST;
2089 if (adapter->wol & E1000_WUFC_MAG)
2090 wol->wolopts |= WAKE_MAGIC;
2091 if (adapter->wol & E1000_WUFC_LNKC)
2092 wol->wolopts |= WAKE_PHY;
2093 }
2094
2095 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2096 {
2097 struct igb_adapter *adapter = netdev_priv(netdev);
2098
2099 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2100 return -EOPNOTSUPP;
2101
2102 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2103 return wol->wolopts ? -EOPNOTSUPP : 0;
2104
2105 /* these settings will always override what we currently have */
2106 adapter->wol = 0;
2107
2108 if (wol->wolopts & WAKE_UCAST)
2109 adapter->wol |= E1000_WUFC_EX;
2110 if (wol->wolopts & WAKE_MCAST)
2111 adapter->wol |= E1000_WUFC_MC;
2112 if (wol->wolopts & WAKE_BCAST)
2113 adapter->wol |= E1000_WUFC_BC;
2114 if (wol->wolopts & WAKE_MAGIC)
2115 adapter->wol |= E1000_WUFC_MAG;
2116 if (wol->wolopts & WAKE_PHY)
2117 adapter->wol |= E1000_WUFC_LNKC;
2118 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2119
2120 return 0;
2121 }
2122
2123 /* bit defines for adapter->led_status */
2124 #define IGB_LED_ON 0
2125
2126 static int igb_set_phys_id(struct net_device *netdev,
2127 enum ethtool_phys_id_state state)
2128 {
2129 struct igb_adapter *adapter = netdev_priv(netdev);
2130 struct e1000_hw *hw = &adapter->hw;
2131
2132 switch (state) {
2133 case ETHTOOL_ID_ACTIVE:
2134 igb_blink_led(hw);
2135 return 2;
2136 case ETHTOOL_ID_ON:
2137 igb_blink_led(hw);
2138 break;
2139 case ETHTOOL_ID_OFF:
2140 igb_led_off(hw);
2141 break;
2142 case ETHTOOL_ID_INACTIVE:
2143 igb_led_off(hw);
2144 clear_bit(IGB_LED_ON, &adapter->led_status);
2145 igb_cleanup_led(hw);
2146 break;
2147 }
2148
2149 return 0;
2150 }
2151
2152 static int igb_set_coalesce(struct net_device *netdev,
2153 struct ethtool_coalesce *ec)
2154 {
2155 struct igb_adapter *adapter = netdev_priv(netdev);
2156 int i;
2157
2158 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2159 ((ec->rx_coalesce_usecs > 3) &&
2160 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2161 (ec->rx_coalesce_usecs == 2))
2162 return -EINVAL;
2163
2164 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2165 ((ec->tx_coalesce_usecs > 3) &&
2166 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2167 (ec->tx_coalesce_usecs == 2))
2168 return -EINVAL;
2169
2170 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2171 return -EINVAL;
2172
2173 /* If ITR is disabled, disable DMAC */
2174 if (ec->rx_coalesce_usecs == 0) {
2175 if (adapter->flags & IGB_FLAG_DMAC)
2176 adapter->flags &= ~IGB_FLAG_DMAC;
2177 }
2178
2179 /* convert to rate of irq's per second */
2180 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2181 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2182 else
2183 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2184
2185 /* convert to rate of irq's per second */
2186 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2187 adapter->tx_itr_setting = adapter->rx_itr_setting;
2188 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2189 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2190 else
2191 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2192
2193 for (i = 0; i < adapter->num_q_vectors; i++) {
2194 struct igb_q_vector *q_vector = adapter->q_vector[i];
2195 q_vector->tx.work_limit = adapter->tx_work_limit;
2196 if (q_vector->rx.ring)
2197 q_vector->itr_val = adapter->rx_itr_setting;
2198 else
2199 q_vector->itr_val = adapter->tx_itr_setting;
2200 if (q_vector->itr_val && q_vector->itr_val <= 3)
2201 q_vector->itr_val = IGB_START_ITR;
2202 q_vector->set_itr = 1;
2203 }
2204
2205 return 0;
2206 }
2207
2208 static int igb_get_coalesce(struct net_device *netdev,
2209 struct ethtool_coalesce *ec)
2210 {
2211 struct igb_adapter *adapter = netdev_priv(netdev);
2212
2213 if (adapter->rx_itr_setting <= 3)
2214 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2215 else
2216 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2217
2218 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2219 if (adapter->tx_itr_setting <= 3)
2220 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2221 else
2222 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2223 }
2224
2225 return 0;
2226 }
2227
2228 static int igb_nway_reset(struct net_device *netdev)
2229 {
2230 struct igb_adapter *adapter = netdev_priv(netdev);
2231 if (netif_running(netdev))
2232 igb_reinit_locked(adapter);
2233 return 0;
2234 }
2235
2236 static int igb_get_sset_count(struct net_device *netdev, int sset)
2237 {
2238 switch (sset) {
2239 case ETH_SS_STATS:
2240 return IGB_STATS_LEN;
2241 case ETH_SS_TEST:
2242 return IGB_TEST_LEN;
2243 default:
2244 return -ENOTSUPP;
2245 }
2246 }
2247
2248 static void igb_get_ethtool_stats(struct net_device *netdev,
2249 struct ethtool_stats *stats, u64 *data)
2250 {
2251 struct igb_adapter *adapter = netdev_priv(netdev);
2252 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2253 unsigned int start;
2254 struct igb_ring *ring;
2255 int i, j;
2256 char *p;
2257
2258 spin_lock(&adapter->stats64_lock);
2259 igb_update_stats(adapter, net_stats);
2260
2261 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2262 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2263 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2264 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2265 }
2266 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2267 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2268 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2269 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2270 }
2271 for (j = 0; j < adapter->num_tx_queues; j++) {
2272 u64 restart2;
2273
2274 ring = adapter->tx_ring[j];
2275 do {
2276 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2277 data[i] = ring->tx_stats.packets;
2278 data[i+1] = ring->tx_stats.bytes;
2279 data[i+2] = ring->tx_stats.restart_queue;
2280 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2281 do {
2282 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2283 restart2 = ring->tx_stats.restart_queue2;
2284 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2285 data[i+2] += restart2;
2286
2287 i += IGB_TX_QUEUE_STATS_LEN;
2288 }
2289 for (j = 0; j < adapter->num_rx_queues; j++) {
2290 ring = adapter->rx_ring[j];
2291 do {
2292 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2293 data[i] = ring->rx_stats.packets;
2294 data[i+1] = ring->rx_stats.bytes;
2295 data[i+2] = ring->rx_stats.drops;
2296 data[i+3] = ring->rx_stats.csum_err;
2297 data[i+4] = ring->rx_stats.alloc_failed;
2298 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2299 i += IGB_RX_QUEUE_STATS_LEN;
2300 }
2301 spin_unlock(&adapter->stats64_lock);
2302 }
2303
2304 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2305 {
2306 struct igb_adapter *adapter = netdev_priv(netdev);
2307 u8 *p = data;
2308 int i;
2309
2310 switch (stringset) {
2311 case ETH_SS_TEST:
2312 memcpy(data, *igb_gstrings_test,
2313 IGB_TEST_LEN*ETH_GSTRING_LEN);
2314 break;
2315 case ETH_SS_STATS:
2316 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2317 memcpy(p, igb_gstrings_stats[i].stat_string,
2318 ETH_GSTRING_LEN);
2319 p += ETH_GSTRING_LEN;
2320 }
2321 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2322 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2323 ETH_GSTRING_LEN);
2324 p += ETH_GSTRING_LEN;
2325 }
2326 for (i = 0; i < adapter->num_tx_queues; i++) {
2327 sprintf(p, "tx_queue_%u_packets", i);
2328 p += ETH_GSTRING_LEN;
2329 sprintf(p, "tx_queue_%u_bytes", i);
2330 p += ETH_GSTRING_LEN;
2331 sprintf(p, "tx_queue_%u_restart", i);
2332 p += ETH_GSTRING_LEN;
2333 }
2334 for (i = 0; i < adapter->num_rx_queues; i++) {
2335 sprintf(p, "rx_queue_%u_packets", i);
2336 p += ETH_GSTRING_LEN;
2337 sprintf(p, "rx_queue_%u_bytes", i);
2338 p += ETH_GSTRING_LEN;
2339 sprintf(p, "rx_queue_%u_drops", i);
2340 p += ETH_GSTRING_LEN;
2341 sprintf(p, "rx_queue_%u_csum_err", i);
2342 p += ETH_GSTRING_LEN;
2343 sprintf(p, "rx_queue_%u_alloc_failed", i);
2344 p += ETH_GSTRING_LEN;
2345 }
2346 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2347 break;
2348 }
2349 }
2350
2351 static int igb_get_ts_info(struct net_device *dev,
2352 struct ethtool_ts_info *info)
2353 {
2354 struct igb_adapter *adapter = netdev_priv(dev);
2355
2356 switch (adapter->hw.mac.type) {
2357 case e1000_82575:
2358 info->so_timestamping =
2359 SOF_TIMESTAMPING_TX_SOFTWARE |
2360 SOF_TIMESTAMPING_RX_SOFTWARE |
2361 SOF_TIMESTAMPING_SOFTWARE;
2362 return 0;
2363 case e1000_82576:
2364 case e1000_82580:
2365 case e1000_i350:
2366 case e1000_i354:
2367 case e1000_i210:
2368 case e1000_i211:
2369 info->so_timestamping =
2370 SOF_TIMESTAMPING_TX_SOFTWARE |
2371 SOF_TIMESTAMPING_RX_SOFTWARE |
2372 SOF_TIMESTAMPING_SOFTWARE |
2373 SOF_TIMESTAMPING_TX_HARDWARE |
2374 SOF_TIMESTAMPING_RX_HARDWARE |
2375 SOF_TIMESTAMPING_RAW_HARDWARE;
2376
2377 if (adapter->ptp_clock)
2378 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2379 else
2380 info->phc_index = -1;
2381
2382 info->tx_types =
2383 (1 << HWTSTAMP_TX_OFF) |
2384 (1 << HWTSTAMP_TX_ON);
2385
2386 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
2387
2388 /* 82576 does not support timestamping all packets. */
2389 if (adapter->hw.mac.type >= e1000_82580)
2390 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2391 else
2392 info->rx_filters |=
2393 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2394 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2395 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2396 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2397 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2398 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2399 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2400
2401 return 0;
2402 default:
2403 return -EOPNOTSUPP;
2404 }
2405 }
2406
2407 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2408 struct ethtool_rxnfc *cmd)
2409 {
2410 cmd->data = 0;
2411
2412 /* Report default options for RSS on igb */
2413 switch (cmd->flow_type) {
2414 case TCP_V4_FLOW:
2415 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2416 case UDP_V4_FLOW:
2417 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2418 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2419 case SCTP_V4_FLOW:
2420 case AH_ESP_V4_FLOW:
2421 case AH_V4_FLOW:
2422 case ESP_V4_FLOW:
2423 case IPV4_FLOW:
2424 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2425 break;
2426 case TCP_V6_FLOW:
2427 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2428 case UDP_V6_FLOW:
2429 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2430 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2431 case SCTP_V6_FLOW:
2432 case AH_ESP_V6_FLOW:
2433 case AH_V6_FLOW:
2434 case ESP_V6_FLOW:
2435 case IPV6_FLOW:
2436 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2437 break;
2438 default:
2439 return -EINVAL;
2440 }
2441
2442 return 0;
2443 }
2444
2445 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2446 u32 *rule_locs)
2447 {
2448 struct igb_adapter *adapter = netdev_priv(dev);
2449 int ret = -EOPNOTSUPP;
2450
2451 switch (cmd->cmd) {
2452 case ETHTOOL_GRXRINGS:
2453 cmd->data = adapter->num_rx_queues;
2454 ret = 0;
2455 break;
2456 case ETHTOOL_GRXFH:
2457 ret = igb_get_rss_hash_opts(adapter, cmd);
2458 break;
2459 default:
2460 break;
2461 }
2462
2463 return ret;
2464 }
2465
2466 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2467 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2468 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2469 struct ethtool_rxnfc *nfc)
2470 {
2471 u32 flags = adapter->flags;
2472
2473 /* RSS does not support anything other than hashing
2474 * to queues on src and dst IPs and ports
2475 */
2476 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2477 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2478 return -EINVAL;
2479
2480 switch (nfc->flow_type) {
2481 case TCP_V4_FLOW:
2482 case TCP_V6_FLOW:
2483 if (!(nfc->data & RXH_IP_SRC) ||
2484 !(nfc->data & RXH_IP_DST) ||
2485 !(nfc->data & RXH_L4_B_0_1) ||
2486 !(nfc->data & RXH_L4_B_2_3))
2487 return -EINVAL;
2488 break;
2489 case UDP_V4_FLOW:
2490 if (!(nfc->data & RXH_IP_SRC) ||
2491 !(nfc->data & RXH_IP_DST))
2492 return -EINVAL;
2493 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2494 case 0:
2495 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2496 break;
2497 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2498 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2499 break;
2500 default:
2501 return -EINVAL;
2502 }
2503 break;
2504 case UDP_V6_FLOW:
2505 if (!(nfc->data & RXH_IP_SRC) ||
2506 !(nfc->data & RXH_IP_DST))
2507 return -EINVAL;
2508 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2509 case 0:
2510 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2511 break;
2512 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2513 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2514 break;
2515 default:
2516 return -EINVAL;
2517 }
2518 break;
2519 case AH_ESP_V4_FLOW:
2520 case AH_V4_FLOW:
2521 case ESP_V4_FLOW:
2522 case SCTP_V4_FLOW:
2523 case AH_ESP_V6_FLOW:
2524 case AH_V6_FLOW:
2525 case ESP_V6_FLOW:
2526 case SCTP_V6_FLOW:
2527 if (!(nfc->data & RXH_IP_SRC) ||
2528 !(nfc->data & RXH_IP_DST) ||
2529 (nfc->data & RXH_L4_B_0_1) ||
2530 (nfc->data & RXH_L4_B_2_3))
2531 return -EINVAL;
2532 break;
2533 default:
2534 return -EINVAL;
2535 }
2536
2537 /* if we changed something we need to update flags */
2538 if (flags != adapter->flags) {
2539 struct e1000_hw *hw = &adapter->hw;
2540 u32 mrqc = rd32(E1000_MRQC);
2541
2542 if ((flags & UDP_RSS_FLAGS) &&
2543 !(adapter->flags & UDP_RSS_FLAGS))
2544 dev_err(&adapter->pdev->dev,
2545 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2546
2547 adapter->flags = flags;
2548
2549 /* Perform hash on these packet types */
2550 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2551 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2552 E1000_MRQC_RSS_FIELD_IPV6 |
2553 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2554
2555 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2556 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2557
2558 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2559 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2560
2561 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2562 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2563
2564 wr32(E1000_MRQC, mrqc);
2565 }
2566
2567 return 0;
2568 }
2569
2570 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2571 {
2572 struct igb_adapter *adapter = netdev_priv(dev);
2573 int ret = -EOPNOTSUPP;
2574
2575 switch (cmd->cmd) {
2576 case ETHTOOL_SRXFH:
2577 ret = igb_set_rss_hash_opt(adapter, cmd);
2578 break;
2579 default:
2580 break;
2581 }
2582
2583 return ret;
2584 }
2585
2586 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2587 {
2588 struct igb_adapter *adapter = netdev_priv(netdev);
2589 struct e1000_hw *hw = &adapter->hw;
2590 u32 ipcnfg, eeer, ret_val;
2591 u16 phy_data;
2592
2593 if ((hw->mac.type < e1000_i350) ||
2594 (hw->phy.media_type != e1000_media_type_copper))
2595 return -EOPNOTSUPP;
2596
2597 edata->supported = (SUPPORTED_1000baseT_Full |
2598 SUPPORTED_100baseT_Full);
2599
2600 ipcnfg = rd32(E1000_IPCNFG);
2601 eeer = rd32(E1000_EEER);
2602
2603 /* EEE status on negotiated link */
2604 if (ipcnfg & E1000_IPCNFG_EEE_1G_AN)
2605 edata->advertised = ADVERTISED_1000baseT_Full;
2606
2607 if (ipcnfg & E1000_IPCNFG_EEE_100M_AN)
2608 edata->advertised |= ADVERTISED_100baseT_Full;
2609
2610 /* EEE Link Partner Advertised */
2611 switch (hw->mac.type) {
2612 case e1000_i350:
2613 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
2614 &phy_data);
2615 if (ret_val)
2616 return -ENODATA;
2617
2618 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2619
2620 break;
2621 case e1000_i210:
2622 case e1000_i211:
2623 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
2624 E1000_EEE_LP_ADV_DEV_I210,
2625 &phy_data);
2626 if (ret_val)
2627 return -ENODATA;
2628
2629 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2630
2631 break;
2632 default:
2633 break;
2634 }
2635
2636 if (eeer & E1000_EEER_EEE_NEG)
2637 edata->eee_active = true;
2638
2639 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2640
2641 if (eeer & E1000_EEER_TX_LPI_EN)
2642 edata->tx_lpi_enabled = true;
2643
2644 /* Report correct negotiated EEE status for devices that
2645 * wrongly report EEE at half-duplex
2646 */
2647 if (adapter->link_duplex == HALF_DUPLEX) {
2648 edata->eee_enabled = false;
2649 edata->eee_active = false;
2650 edata->tx_lpi_enabled = false;
2651 edata->advertised &= ~edata->advertised;
2652 }
2653
2654 return 0;
2655 }
2656
2657 static int igb_set_eee(struct net_device *netdev,
2658 struct ethtool_eee *edata)
2659 {
2660 struct igb_adapter *adapter = netdev_priv(netdev);
2661 struct e1000_hw *hw = &adapter->hw;
2662 struct ethtool_eee eee_curr;
2663 s32 ret_val;
2664
2665 if ((hw->mac.type < e1000_i350) ||
2666 (hw->phy.media_type != e1000_media_type_copper))
2667 return -EOPNOTSUPP;
2668
2669 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
2670
2671 ret_val = igb_get_eee(netdev, &eee_curr);
2672 if (ret_val)
2673 return ret_val;
2674
2675 if (eee_curr.eee_enabled) {
2676 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2677 dev_err(&adapter->pdev->dev,
2678 "Setting EEE tx-lpi is not supported\n");
2679 return -EINVAL;
2680 }
2681
2682 /* Tx LPI timer is not implemented currently */
2683 if (edata->tx_lpi_timer) {
2684 dev_err(&adapter->pdev->dev,
2685 "Setting EEE Tx LPI timer is not supported\n");
2686 return -EINVAL;
2687 }
2688
2689 if (eee_curr.advertised != edata->advertised) {
2690 dev_err(&adapter->pdev->dev,
2691 "Setting EEE Advertisement is not supported\n");
2692 return -EINVAL;
2693 }
2694
2695 } else if (!edata->eee_enabled) {
2696 dev_err(&adapter->pdev->dev,
2697 "Setting EEE options are not supported with EEE disabled\n");
2698 return -EINVAL;
2699 }
2700
2701 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2702 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2703 igb_set_eee_i350(hw);
2704
2705 /* reset link */
2706 if (netif_running(netdev))
2707 igb_reinit_locked(adapter);
2708 else
2709 igb_reset(adapter);
2710 }
2711
2712 return 0;
2713 }
2714
2715 static int igb_get_module_info(struct net_device *netdev,
2716 struct ethtool_modinfo *modinfo)
2717 {
2718 struct igb_adapter *adapter = netdev_priv(netdev);
2719 struct e1000_hw *hw = &adapter->hw;
2720 u32 status = E1000_SUCCESS;
2721 u16 sff8472_rev, addr_mode;
2722 bool page_swap = false;
2723
2724 if ((hw->phy.media_type == e1000_media_type_copper) ||
2725 (hw->phy.media_type == e1000_media_type_unknown))
2726 return -EOPNOTSUPP;
2727
2728 /* Check whether we support SFF-8472 or not */
2729 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
2730 if (status != E1000_SUCCESS)
2731 return -EIO;
2732
2733 /* addressing mode is not supported */
2734 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
2735 if (status != E1000_SUCCESS)
2736 return -EIO;
2737
2738 /* addressing mode is not supported */
2739 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
2740 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2741 page_swap = true;
2742 }
2743
2744 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
2745 /* We have an SFP, but it does not support SFF-8472 */
2746 modinfo->type = ETH_MODULE_SFF_8079;
2747 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2748 } else {
2749 /* We have an SFP which supports a revision of SFF-8472 */
2750 modinfo->type = ETH_MODULE_SFF_8472;
2751 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2752 }
2753
2754 return 0;
2755 }
2756
2757 static int igb_get_module_eeprom(struct net_device *netdev,
2758 struct ethtool_eeprom *ee, u8 *data)
2759 {
2760 struct igb_adapter *adapter = netdev_priv(netdev);
2761 struct e1000_hw *hw = &adapter->hw;
2762 u32 status = E1000_SUCCESS;
2763 u16 *dataword;
2764 u16 first_word, last_word;
2765 int i = 0;
2766
2767 if (ee->len == 0)
2768 return -EINVAL;
2769
2770 first_word = ee->offset >> 1;
2771 last_word = (ee->offset + ee->len - 1) >> 1;
2772
2773 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
2774 GFP_KERNEL);
2775 if (!dataword)
2776 return -ENOMEM;
2777
2778 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
2779 for (i = 0; i < last_word - first_word + 1; i++) {
2780 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
2781 if (status != E1000_SUCCESS)
2782 /* Error occurred while reading module */
2783 return -EIO;
2784
2785 be16_to_cpus(&dataword[i]);
2786 }
2787
2788 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
2789 kfree(dataword);
2790
2791 return 0;
2792 }
2793
2794 static int igb_ethtool_begin(struct net_device *netdev)
2795 {
2796 struct igb_adapter *adapter = netdev_priv(netdev);
2797 pm_runtime_get_sync(&adapter->pdev->dev);
2798 return 0;
2799 }
2800
2801 static void igb_ethtool_complete(struct net_device *netdev)
2802 {
2803 struct igb_adapter *adapter = netdev_priv(netdev);
2804 pm_runtime_put(&adapter->pdev->dev);
2805 }
2806
2807 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
2808 {
2809 return IGB_RETA_SIZE;
2810 }
2811
2812 static int igb_get_rxfh_indir(struct net_device *netdev, u32 *indir)
2813 {
2814 struct igb_adapter *adapter = netdev_priv(netdev);
2815 int i;
2816
2817 for (i = 0; i < IGB_RETA_SIZE; i++)
2818 indir[i] = adapter->rss_indir_tbl[i];
2819
2820 return 0;
2821 }
2822
2823 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
2824 {
2825 struct e1000_hw *hw = &adapter->hw;
2826 u32 reg = E1000_RETA(0);
2827 u32 shift = 0;
2828 int i = 0;
2829
2830 switch (hw->mac.type) {
2831 case e1000_82575:
2832 shift = 6;
2833 break;
2834 case e1000_82576:
2835 /* 82576 supports 2 RSS queues for SR-IOV */
2836 if (adapter->vfs_allocated_count)
2837 shift = 3;
2838 break;
2839 default:
2840 break;
2841 }
2842
2843 while (i < IGB_RETA_SIZE) {
2844 u32 val = 0;
2845 int j;
2846
2847 for (j = 3; j >= 0; j--) {
2848 val <<= 8;
2849 val |= adapter->rss_indir_tbl[i + j];
2850 }
2851
2852 wr32(reg, val << shift);
2853 reg += 4;
2854 i += 4;
2855 }
2856 }
2857
2858 static int igb_set_rxfh_indir(struct net_device *netdev, const u32 *indir)
2859 {
2860 struct igb_adapter *adapter = netdev_priv(netdev);
2861 struct e1000_hw *hw = &adapter->hw;
2862 int i;
2863 u32 num_queues;
2864
2865 num_queues = adapter->rss_queues;
2866
2867 switch (hw->mac.type) {
2868 case e1000_82576:
2869 /* 82576 supports 2 RSS queues for SR-IOV */
2870 if (adapter->vfs_allocated_count)
2871 num_queues = 2;
2872 break;
2873 default:
2874 break;
2875 }
2876
2877 /* Verify user input. */
2878 for (i = 0; i < IGB_RETA_SIZE; i++)
2879 if (indir[i] >= num_queues)
2880 return -EINVAL;
2881
2882
2883 for (i = 0; i < IGB_RETA_SIZE; i++)
2884 adapter->rss_indir_tbl[i] = indir[i];
2885
2886 igb_write_rss_indir_tbl(adapter);
2887
2888 return 0;
2889 }
2890
2891 static unsigned int igb_max_channels(struct igb_adapter *adapter)
2892 {
2893 struct e1000_hw *hw = &adapter->hw;
2894 unsigned int max_combined = 0;
2895
2896 switch (hw->mac.type) {
2897 case e1000_i211:
2898 max_combined = IGB_MAX_RX_QUEUES_I211;
2899 break;
2900 case e1000_82575:
2901 case e1000_i210:
2902 max_combined = IGB_MAX_RX_QUEUES_82575;
2903 break;
2904 case e1000_i350:
2905 if (!!adapter->vfs_allocated_count) {
2906 max_combined = 1;
2907 break;
2908 }
2909 /* fall through */
2910 case e1000_82576:
2911 if (!!adapter->vfs_allocated_count) {
2912 max_combined = 2;
2913 break;
2914 }
2915 /* fall through */
2916 case e1000_82580:
2917 case e1000_i354:
2918 default:
2919 max_combined = IGB_MAX_RX_QUEUES;
2920 break;
2921 }
2922
2923 return max_combined;
2924 }
2925
2926 static void igb_get_channels(struct net_device *netdev,
2927 struct ethtool_channels *ch)
2928 {
2929 struct igb_adapter *adapter = netdev_priv(netdev);
2930
2931 /* Report maximum channels */
2932 ch->max_combined = igb_max_channels(adapter);
2933
2934 /* Report info for other vector */
2935 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2936 ch->max_other = NON_Q_VECTORS;
2937 ch->other_count = NON_Q_VECTORS;
2938 }
2939
2940 ch->combined_count = adapter->rss_queues;
2941 }
2942
2943 static int igb_set_channels(struct net_device *netdev,
2944 struct ethtool_channels *ch)
2945 {
2946 struct igb_adapter *adapter = netdev_priv(netdev);
2947 unsigned int count = ch->combined_count;
2948
2949 /* Verify they are not requesting separate vectors */
2950 if (!count || ch->rx_count || ch->tx_count)
2951 return -EINVAL;
2952
2953 /* Verify other_count is valid and has not been changed */
2954 if (ch->other_count != NON_Q_VECTORS)
2955 return -EINVAL;
2956
2957 /* Verify the number of channels doesn't exceed hw limits */
2958 if (count > igb_max_channels(adapter))
2959 return -EINVAL;
2960
2961 if (count != adapter->rss_queues) {
2962 adapter->rss_queues = count;
2963
2964 /* Hardware has to reinitialize queues and interrupts to
2965 * match the new configuration.
2966 */
2967 return igb_reinit_queues(adapter);
2968 }
2969
2970 return 0;
2971 }
2972
2973 static const struct ethtool_ops igb_ethtool_ops = {
2974 .get_settings = igb_get_settings,
2975 .set_settings = igb_set_settings,
2976 .get_drvinfo = igb_get_drvinfo,
2977 .get_regs_len = igb_get_regs_len,
2978 .get_regs = igb_get_regs,
2979 .get_wol = igb_get_wol,
2980 .set_wol = igb_set_wol,
2981 .get_msglevel = igb_get_msglevel,
2982 .set_msglevel = igb_set_msglevel,
2983 .nway_reset = igb_nway_reset,
2984 .get_link = igb_get_link,
2985 .get_eeprom_len = igb_get_eeprom_len,
2986 .get_eeprom = igb_get_eeprom,
2987 .set_eeprom = igb_set_eeprom,
2988 .get_ringparam = igb_get_ringparam,
2989 .set_ringparam = igb_set_ringparam,
2990 .get_pauseparam = igb_get_pauseparam,
2991 .set_pauseparam = igb_set_pauseparam,
2992 .self_test = igb_diag_test,
2993 .get_strings = igb_get_strings,
2994 .set_phys_id = igb_set_phys_id,
2995 .get_sset_count = igb_get_sset_count,
2996 .get_ethtool_stats = igb_get_ethtool_stats,
2997 .get_coalesce = igb_get_coalesce,
2998 .set_coalesce = igb_set_coalesce,
2999 .get_ts_info = igb_get_ts_info,
3000 .get_rxnfc = igb_get_rxnfc,
3001 .set_rxnfc = igb_set_rxnfc,
3002 .get_eee = igb_get_eee,
3003 .set_eee = igb_set_eee,
3004 .get_module_info = igb_get_module_info,
3005 .get_module_eeprom = igb_get_module_eeprom,
3006 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
3007 .get_rxfh_indir = igb_get_rxfh_indir,
3008 .set_rxfh_indir = igb_set_rxfh_indir,
3009 .get_channels = igb_get_channels,
3010 .set_channels = igb_set_channels,
3011 .begin = igb_ethtool_begin,
3012 .complete = igb_ethtool_complete,
3013 };
3014
3015 void igb_set_ethtool_ops(struct net_device *netdev)
3016 {
3017 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
3018 }
Linux kernel - Deliverables
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