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e1000e / igb / PM: Eliminate CONFIG_PM_RUNTIME
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
57 #include "igb.h"
58
59 #define MAJ 5
60 #define MIN 2
61 #define BUILD 15
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71 static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73 };
74
75 static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 #endif
183
184 #ifdef CONFIG_PM
185 #ifdef CONFIG_PM_SLEEP
186 static int igb_suspend(struct device *);
187 #endif
188 static int igb_resume(struct device *);
189 static int igb_runtime_suspend(struct device *dev);
190 static int igb_runtime_resume(struct device *dev);
191 static int igb_runtime_idle(struct device *dev);
192 static const struct dev_pm_ops igb_pm_ops = {
193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
195 igb_runtime_idle)
196 };
197 #endif
198 static void igb_shutdown(struct pci_dev *);
199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
200 #ifdef CONFIG_IGB_DCA
201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202 static struct notifier_block dca_notifier = {
203 .notifier_call = igb_notify_dca,
204 .next = NULL,
205 .priority = 0
206 };
207 #endif
208 #ifdef CONFIG_NET_POLL_CONTROLLER
209 /* for netdump / net console */
210 static void igb_netpoll(struct net_device *);
211 #endif
212 #ifdef CONFIG_PCI_IOV
213 static unsigned int max_vfs;
214 module_param(max_vfs, uint, 0);
215 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
216 #endif /* CONFIG_PCI_IOV */
217
218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221 static void igb_io_resume(struct pci_dev *);
222
223 static const struct pci_error_handlers igb_err_handler = {
224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227 };
228
229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
230
231 static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
235 .remove = igb_remove,
236 #ifdef CONFIG_PM
237 .driver.pm = &igb_pm_ops,
238 #endif
239 .shutdown = igb_shutdown,
240 .sriov_configure = igb_pci_sriov_configure,
241 .err_handler = &igb_err_handler
242 };
243
244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246 MODULE_LICENSE("GPL");
247 MODULE_VERSION(DRV_VERSION);
248
249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250 static int debug = -1;
251 module_param(debug, int, 0);
252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
254 struct igb_reg_info {
255 u32 ofs;
256 char *name;
257 };
258
259 static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293 };
294
295 /* igb_regdump - register printout routine */
296 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297 {
298 int n = 0;
299 char rname[16];
300 u32 regs[8];
301
302 switch (reginfo->ofs) {
303 case E1000_RDLEN(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_RDLEN(n));
306 break;
307 case E1000_RDH(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDH(n));
310 break;
311 case E1000_RDT(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDT(n));
314 break;
315 case E1000_RXDCTL(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RXDCTL(n));
318 break;
319 case E1000_RDBAL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RDBAL(n));
322 break;
323 case E1000_RDBAH(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAH(n));
326 break;
327 case E1000_TDBAL(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAL(n));
330 break;
331 case E1000_TDBAH(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_TDBAH(n));
334 break;
335 case E1000_TDLEN(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDLEN(n));
338 break;
339 case E1000_TDH(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDH(n));
342 break;
343 case E1000_TDT(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDT(n));
346 break;
347 case E1000_TXDCTL(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TXDCTL(n));
350 break;
351 default:
352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
353 return;
354 }
355
356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 regs[2], regs[3]);
359 }
360
361 /* igb_dump - Print registers, Tx-rings and Rx-rings */
362 static void igb_dump(struct igb_adapter *adapter)
363 {
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
373 u16 i, n;
374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
381 pr_info("Device Name state trans_start last_rx\n");
382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
388 pr_info(" Register Name Value\n");
389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
400 for (n = 0; n < adapter->num_tx_queues; n++) {
401 struct igb_tx_buffer *buffer_info;
402 tx_ring = adapter->tx_ring[n];
403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
435
436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
437 const char *next_desc;
438 struct igb_tx_buffer *buffer_info;
439 tx_desc = IGB_TX_DESC(tx_ring, i);
440 buffer_info = &tx_ring->tx_buffer_info[i];
441 u0 = (struct my_u0 *)tx_desc;
442 if (i == tx_ring->next_to_use &&
443 i == tx_ring->next_to_clean)
444 next_desc = " NTC/U";
445 else if (i == tx_ring->next_to_use)
446 next_desc = " NTU";
447 else if (i == tx_ring->next_to_clean)
448 next_desc = " NTC";
449 else
450 next_desc = "";
451
452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
453 i, le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(buffer_info, dma),
456 dma_unmap_len(buffer_info, len),
457 buffer_info->next_to_watch,
458 (u64)buffer_info->time_stamp,
459 buffer_info->skb, next_desc);
460
461 if (netif_msg_pktdata(adapter) && buffer_info->skb)
462 print_hex_dump(KERN_INFO, "",
463 DUMP_PREFIX_ADDRESS,
464 16, 1, buffer_info->skb->data,
465 dma_unmap_len(buffer_info, len),
466 true);
467 }
468 }
469
470 /* Print RX Rings Summary */
471 rx_ring_summary:
472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
473 pr_info("Queue [NTU] [NTC]\n");
474 for (n = 0; n < adapter->num_rx_queues; n++) {
475 rx_ring = adapter->rx_ring[n];
476 pr_info(" %5d %5X %5X\n",
477 n, rx_ring->next_to_use, rx_ring->next_to_clean);
478 }
479
480 /* Print RX Rings */
481 if (!netif_msg_rx_status(adapter))
482 goto exit;
483
484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
485
486 /* Advanced Receive Descriptor (Read) Format
487 * 63 1 0
488 * +-----------------------------------------------------+
489 * 0 | Packet Buffer Address [63:1] |A0/NSE|
490 * +----------------------------------------------+------+
491 * 8 | Header Buffer Address [63:1] | DD |
492 * +-----------------------------------------------------+
493 *
494 *
495 * Advanced Receive Descriptor (Write-Back) Format
496 *
497 * 63 48 47 32 31 30 21 20 17 16 4 3 0
498 * +------------------------------------------------------+
499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
500 * | Checksum Ident | | | | Type | Type |
501 * +------------------------------------------------------+
502 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 * +------------------------------------------------------+
504 * 63 48 47 32 31 20 19 0
505 */
506
507 for (n = 0; n < adapter->num_rx_queues; n++) {
508 rx_ring = adapter->rx_ring[n];
509 pr_info("------------------------------------\n");
510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
511 pr_info("------------------------------------\n");
512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
514
515 for (i = 0; i < rx_ring->count; i++) {
516 const char *next_desc;
517 struct igb_rx_buffer *buffer_info;
518 buffer_info = &rx_ring->rx_buffer_info[i];
519 rx_desc = IGB_RX_DESC(rx_ring, i);
520 u0 = (struct my_u0 *)rx_desc;
521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
522
523 if (i == rx_ring->next_to_use)
524 next_desc = " NTU";
525 else if (i == rx_ring->next_to_clean)
526 next_desc = " NTC";
527 else
528 next_desc = "";
529
530 if (staterr & E1000_RXD_STAT_DD) {
531 /* Descriptor Done */
532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
533 "RWB", i,
534 le64_to_cpu(u0->a),
535 le64_to_cpu(u0->b),
536 next_desc);
537 } else {
538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
539 "R ", i,
540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
542 (u64)buffer_info->dma,
543 next_desc);
544
545 if (netif_msg_pktdata(adapter) &&
546 buffer_info->dma && buffer_info->page) {
547 print_hex_dump(KERN_INFO, "",
548 DUMP_PREFIX_ADDRESS,
549 16, 1,
550 page_address(buffer_info->page) +
551 buffer_info->page_offset,
552 IGB_RX_BUFSZ, true);
553 }
554 }
555 }
556 }
557
558 exit:
559 return;
560 }
561
562 /**
563 * igb_get_i2c_data - Reads the I2C SDA data bit
564 * @hw: pointer to hardware structure
565 * @i2cctl: Current value of I2CCTL register
566 *
567 * Returns the I2C data bit value
568 **/
569 static int igb_get_i2c_data(void *data)
570 {
571 struct igb_adapter *adapter = (struct igb_adapter *)data;
572 struct e1000_hw *hw = &adapter->hw;
573 s32 i2cctl = rd32(E1000_I2CPARAMS);
574
575 return !!(i2cctl & E1000_I2C_DATA_IN);
576 }
577
578 /**
579 * igb_set_i2c_data - Sets the I2C data bit
580 * @data: pointer to hardware structure
581 * @state: I2C data value (0 or 1) to set
582 *
583 * Sets the I2C data bit
584 **/
585 static void igb_set_i2c_data(void *data, int state)
586 {
587 struct igb_adapter *adapter = (struct igb_adapter *)data;
588 struct e1000_hw *hw = &adapter->hw;
589 s32 i2cctl = rd32(E1000_I2CPARAMS);
590
591 if (state)
592 i2cctl |= E1000_I2C_DATA_OUT;
593 else
594 i2cctl &= ~E1000_I2C_DATA_OUT;
595
596 i2cctl &= ~E1000_I2C_DATA_OE_N;
597 i2cctl |= E1000_I2C_CLK_OE_N;
598 wr32(E1000_I2CPARAMS, i2cctl);
599 wrfl();
600
601 }
602
603 /**
604 * igb_set_i2c_clk - Sets the I2C SCL clock
605 * @data: pointer to hardware structure
606 * @state: state to set clock
607 *
608 * Sets the I2C clock line to state
609 **/
610 static void igb_set_i2c_clk(void *data, int state)
611 {
612 struct igb_adapter *adapter = (struct igb_adapter *)data;
613 struct e1000_hw *hw = &adapter->hw;
614 s32 i2cctl = rd32(E1000_I2CPARAMS);
615
616 if (state) {
617 i2cctl |= E1000_I2C_CLK_OUT;
618 i2cctl &= ~E1000_I2C_CLK_OE_N;
619 } else {
620 i2cctl &= ~E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 }
623 wr32(E1000_I2CPARAMS, i2cctl);
624 wrfl();
625 }
626
627 /**
628 * igb_get_i2c_clk - Gets the I2C SCL clock state
629 * @data: pointer to hardware structure
630 *
631 * Gets the I2C clock state
632 **/
633 static int igb_get_i2c_clk(void *data)
634 {
635 struct igb_adapter *adapter = (struct igb_adapter *)data;
636 struct e1000_hw *hw = &adapter->hw;
637 s32 i2cctl = rd32(E1000_I2CPARAMS);
638
639 return !!(i2cctl & E1000_I2C_CLK_IN);
640 }
641
642 static const struct i2c_algo_bit_data igb_i2c_algo = {
643 .setsda = igb_set_i2c_data,
644 .setscl = igb_set_i2c_clk,
645 .getsda = igb_get_i2c_data,
646 .getscl = igb_get_i2c_clk,
647 .udelay = 5,
648 .timeout = 20,
649 };
650
651 /**
652 * igb_get_hw_dev - return device
653 * @hw: pointer to hardware structure
654 *
655 * used by hardware layer to print debugging information
656 **/
657 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
658 {
659 struct igb_adapter *adapter = hw->back;
660 return adapter->netdev;
661 }
662
663 /**
664 * igb_init_module - Driver Registration Routine
665 *
666 * igb_init_module is the first routine called when the driver is
667 * loaded. All it does is register with the PCI subsystem.
668 **/
669 static int __init igb_init_module(void)
670 {
671 int ret;
672
673 pr_info("%s - version %s\n",
674 igb_driver_string, igb_driver_version);
675 pr_info("%s\n", igb_copyright);
676
677 #ifdef CONFIG_IGB_DCA
678 dca_register_notify(&dca_notifier);
679 #endif
680 ret = pci_register_driver(&igb_driver);
681 return ret;
682 }
683
684 module_init(igb_init_module);
685
686 /**
687 * igb_exit_module - Driver Exit Cleanup Routine
688 *
689 * igb_exit_module is called just before the driver is removed
690 * from memory.
691 **/
692 static void __exit igb_exit_module(void)
693 {
694 #ifdef CONFIG_IGB_DCA
695 dca_unregister_notify(&dca_notifier);
696 #endif
697 pci_unregister_driver(&igb_driver);
698 }
699
700 module_exit(igb_exit_module);
701
702 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703 /**
704 * igb_cache_ring_register - Descriptor ring to register mapping
705 * @adapter: board private structure to initialize
706 *
707 * Once we know the feature-set enabled for the device, we'll cache
708 * the register offset the descriptor ring is assigned to.
709 **/
710 static void igb_cache_ring_register(struct igb_adapter *adapter)
711 {
712 int i = 0, j = 0;
713 u32 rbase_offset = adapter->vfs_allocated_count;
714
715 switch (adapter->hw.mac.type) {
716 case e1000_82576:
717 /* The queues are allocated for virtualization such that VF 0
718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 * In order to avoid collision we start at the first free queue
720 * and continue consuming queues in the same sequence
721 */
722 if (adapter->vfs_allocated_count) {
723 for (; i < adapter->rss_queues; i++)
724 adapter->rx_ring[i]->reg_idx = rbase_offset +
725 Q_IDX_82576(i);
726 }
727 /* Fall through */
728 case e1000_82575:
729 case e1000_82580:
730 case e1000_i350:
731 case e1000_i354:
732 case e1000_i210:
733 case e1000_i211:
734 /* Fall through */
735 default:
736 for (; i < adapter->num_rx_queues; i++)
737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
738 for (; j < adapter->num_tx_queues; j++)
739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
740 break;
741 }
742 }
743
744 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
745 {
746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
748 u32 value = 0;
749
750 if (E1000_REMOVED(hw_addr))
751 return ~value;
752
753 value = readl(&hw_addr[reg]);
754
755 /* reads should not return all F's */
756 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
757 struct net_device *netdev = igb->netdev;
758 hw->hw_addr = NULL;
759 netif_device_detach(netdev);
760 netdev_err(netdev, "PCIe link lost, device now detached\n");
761 }
762
763 return value;
764 }
765
766 /**
767 * igb_write_ivar - configure ivar for given MSI-X vector
768 * @hw: pointer to the HW structure
769 * @msix_vector: vector number we are allocating to a given ring
770 * @index: row index of IVAR register to write within IVAR table
771 * @offset: column offset of in IVAR, should be multiple of 8
772 *
773 * This function is intended to handle the writing of the IVAR register
774 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
775 * each containing an cause allocation for an Rx and Tx ring, and a
776 * variable number of rows depending on the number of queues supported.
777 **/
778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
779 int index, int offset)
780 {
781 u32 ivar = array_rd32(E1000_IVAR0, index);
782
783 /* clear any bits that are currently set */
784 ivar &= ~((u32)0xFF << offset);
785
786 /* write vector and valid bit */
787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
788
789 array_wr32(E1000_IVAR0, index, ivar);
790 }
791
792 #define IGB_N0_QUEUE -1
793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
794 {
795 struct igb_adapter *adapter = q_vector->adapter;
796 struct e1000_hw *hw = &adapter->hw;
797 int rx_queue = IGB_N0_QUEUE;
798 int tx_queue = IGB_N0_QUEUE;
799 u32 msixbm = 0;
800
801 if (q_vector->rx.ring)
802 rx_queue = q_vector->rx.ring->reg_idx;
803 if (q_vector->tx.ring)
804 tx_queue = q_vector->tx.ring->reg_idx;
805
806 switch (hw->mac.type) {
807 case e1000_82575:
808 /* The 82575 assigns vectors using a bitmask, which matches the
809 * bitmask for the EICR/EIMS/EIMC registers. To assign one
810 * or more queues to a vector, we write the appropriate bits
811 * into the MSIXBM register for that vector.
812 */
813 if (rx_queue > IGB_N0_QUEUE)
814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
815 if (tx_queue > IGB_N0_QUEUE)
816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
818 msixbm |= E1000_EIMS_OTHER;
819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
820 q_vector->eims_value = msixbm;
821 break;
822 case e1000_82576:
823 /* 82576 uses a table that essentially consists of 2 columns
824 * with 8 rows. The ordering is column-major so we use the
825 * lower 3 bits as the row index, and the 4th bit as the
826 * column offset.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue & 0x7,
831 (rx_queue & 0x8) << 1);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue & 0x7,
835 ((tx_queue & 0x8) << 1) + 8);
836 q_vector->eims_value = 1 << msix_vector;
837 break;
838 case e1000_82580:
839 case e1000_i350:
840 case e1000_i354:
841 case e1000_i210:
842 case e1000_i211:
843 /* On 82580 and newer adapters the scheme is similar to 82576
844 * however instead of ordering column-major we have things
845 * ordered row-major. So we traverse the table by using
846 * bit 0 as the column offset, and the remaining bits as the
847 * row index.
848 */
849 if (rx_queue > IGB_N0_QUEUE)
850 igb_write_ivar(hw, msix_vector,
851 rx_queue >> 1,
852 (rx_queue & 0x1) << 4);
853 if (tx_queue > IGB_N0_QUEUE)
854 igb_write_ivar(hw, msix_vector,
855 tx_queue >> 1,
856 ((tx_queue & 0x1) << 4) + 8);
857 q_vector->eims_value = 1 << msix_vector;
858 break;
859 default:
860 BUG();
861 break;
862 }
863
864 /* add q_vector eims value to global eims_enable_mask */
865 adapter->eims_enable_mask |= q_vector->eims_value;
866
867 /* configure q_vector to set itr on first interrupt */
868 q_vector->set_itr = 1;
869 }
870
871 /**
872 * igb_configure_msix - Configure MSI-X hardware
873 * @adapter: board private structure to initialize
874 *
875 * igb_configure_msix sets up the hardware to properly
876 * generate MSI-X interrupts.
877 **/
878 static void igb_configure_msix(struct igb_adapter *adapter)
879 {
880 u32 tmp;
881 int i, vector = 0;
882 struct e1000_hw *hw = &adapter->hw;
883
884 adapter->eims_enable_mask = 0;
885
886 /* set vector for other causes, i.e. link changes */
887 switch (hw->mac.type) {
888 case e1000_82575:
889 tmp = rd32(E1000_CTRL_EXT);
890 /* enable MSI-X PBA support*/
891 tmp |= E1000_CTRL_EXT_PBA_CLR;
892
893 /* Auto-Mask interrupts upon ICR read. */
894 tmp |= E1000_CTRL_EXT_EIAME;
895 tmp |= E1000_CTRL_EXT_IRCA;
896
897 wr32(E1000_CTRL_EXT, tmp);
898
899 /* enable msix_other interrupt */
900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
901 adapter->eims_other = E1000_EIMS_OTHER;
902
903 break;
904
905 case e1000_82576:
906 case e1000_82580:
907 case e1000_i350:
908 case e1000_i354:
909 case e1000_i210:
910 case e1000_i211:
911 /* Turn on MSI-X capability first, or our settings
912 * won't stick. And it will take days to debug.
913 */
914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
915 E1000_GPIE_PBA | E1000_GPIE_EIAME |
916 E1000_GPIE_NSICR);
917
918 /* enable msix_other interrupt */
919 adapter->eims_other = 1 << vector;
920 tmp = (vector++ | E1000_IVAR_VALID) << 8;
921
922 wr32(E1000_IVAR_MISC, tmp);
923 break;
924 default:
925 /* do nothing, since nothing else supports MSI-X */
926 break;
927 } /* switch (hw->mac.type) */
928
929 adapter->eims_enable_mask |= adapter->eims_other;
930
931 for (i = 0; i < adapter->num_q_vectors; i++)
932 igb_assign_vector(adapter->q_vector[i], vector++);
933
934 wrfl();
935 }
936
937 /**
938 * igb_request_msix - Initialize MSI-X interrupts
939 * @adapter: board private structure to initialize
940 *
941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
942 * kernel.
943 **/
944 static int igb_request_msix(struct igb_adapter *adapter)
945 {
946 struct net_device *netdev = adapter->netdev;
947 struct e1000_hw *hw = &adapter->hw;
948 int i, err = 0, vector = 0, free_vector = 0;
949
950 err = request_irq(adapter->msix_entries[vector].vector,
951 igb_msix_other, 0, netdev->name, adapter);
952 if (err)
953 goto err_out;
954
955 for (i = 0; i < adapter->num_q_vectors; i++) {
956 struct igb_q_vector *q_vector = adapter->q_vector[i];
957
958 vector++;
959
960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
961
962 if (q_vector->rx.ring && q_vector->tx.ring)
963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
964 q_vector->rx.ring->queue_index);
965 else if (q_vector->tx.ring)
966 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
967 q_vector->tx.ring->queue_index);
968 else if (q_vector->rx.ring)
969 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
970 q_vector->rx.ring->queue_index);
971 else
972 sprintf(q_vector->name, "%s-unused", netdev->name);
973
974 err = request_irq(adapter->msix_entries[vector].vector,
975 igb_msix_ring, 0, q_vector->name,
976 q_vector);
977 if (err)
978 goto err_free;
979 }
980
981 igb_configure_msix(adapter);
982 return 0;
983
984 err_free:
985 /* free already assigned IRQs */
986 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
987
988 vector--;
989 for (i = 0; i < vector; i++) {
990 free_irq(adapter->msix_entries[free_vector++].vector,
991 adapter->q_vector[i]);
992 }
993 err_out:
994 return err;
995 }
996
997 /**
998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
1001 *
1002 * This function frees the memory allocated to the q_vector.
1003 **/
1004 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005 {
1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007
1008 adapter->q_vector[v_idx] = NULL;
1009
1010 /* igb_get_stats64() might access the rings on this vector,
1011 * we must wait a grace period before freeing it.
1012 */
1013 kfree_rcu(q_vector, rcu);
1014 }
1015
1016 /**
1017 * igb_reset_q_vector - Reset config for interrupt vector
1018 * @adapter: board private structure to initialize
1019 * @v_idx: Index of vector to be reset
1020 *
1021 * If NAPI is enabled it will delete any references to the
1022 * NAPI struct. This is preparation for igb_free_q_vector.
1023 **/
1024 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1025 {
1026 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1027
1028 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1029 * allocated. So, q_vector is NULL so we should stop here.
1030 */
1031 if (!q_vector)
1032 return;
1033
1034 if (q_vector->tx.ring)
1035 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1036
1037 if (q_vector->rx.ring)
1038 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1039
1040 netif_napi_del(&q_vector->napi);
1041
1042 }
1043
1044 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1045 {
1046 int v_idx = adapter->num_q_vectors;
1047
1048 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1049 pci_disable_msix(adapter->pdev);
1050 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1051 pci_disable_msi(adapter->pdev);
1052
1053 while (v_idx--)
1054 igb_reset_q_vector(adapter, v_idx);
1055 }
1056
1057 /**
1058 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1059 * @adapter: board private structure to initialize
1060 *
1061 * This function frees the memory allocated to the q_vectors. In addition if
1062 * NAPI is enabled it will delete any references to the NAPI struct prior
1063 * to freeing the q_vector.
1064 **/
1065 static void igb_free_q_vectors(struct igb_adapter *adapter)
1066 {
1067 int v_idx = adapter->num_q_vectors;
1068
1069 adapter->num_tx_queues = 0;
1070 adapter->num_rx_queues = 0;
1071 adapter->num_q_vectors = 0;
1072
1073 while (v_idx--) {
1074 igb_reset_q_vector(adapter, v_idx);
1075 igb_free_q_vector(adapter, v_idx);
1076 }
1077 }
1078
1079 /**
1080 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1081 * @adapter: board private structure to initialize
1082 *
1083 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1084 * MSI-X interrupts allocated.
1085 */
1086 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1087 {
1088 igb_free_q_vectors(adapter);
1089 igb_reset_interrupt_capability(adapter);
1090 }
1091
1092 /**
1093 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1094 * @adapter: board private structure to initialize
1095 * @msix: boolean value of MSIX capability
1096 *
1097 * Attempt to configure interrupts using the best available
1098 * capabilities of the hardware and kernel.
1099 **/
1100 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1101 {
1102 int err;
1103 int numvecs, i;
1104
1105 if (!msix)
1106 goto msi_only;
1107 adapter->flags |= IGB_FLAG_HAS_MSIX;
1108
1109 /* Number of supported queues. */
1110 adapter->num_rx_queues = adapter->rss_queues;
1111 if (adapter->vfs_allocated_count)
1112 adapter->num_tx_queues = 1;
1113 else
1114 adapter->num_tx_queues = adapter->rss_queues;
1115
1116 /* start with one vector for every Rx queue */
1117 numvecs = adapter->num_rx_queues;
1118
1119 /* if Tx handler is separate add 1 for every Tx queue */
1120 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1121 numvecs += adapter->num_tx_queues;
1122
1123 /* store the number of vectors reserved for queues */
1124 adapter->num_q_vectors = numvecs;
1125
1126 /* add 1 vector for link status interrupts */
1127 numvecs++;
1128 for (i = 0; i < numvecs; i++)
1129 adapter->msix_entries[i].entry = i;
1130
1131 err = pci_enable_msix_range(adapter->pdev,
1132 adapter->msix_entries,
1133 numvecs,
1134 numvecs);
1135 if (err > 0)
1136 return;
1137
1138 igb_reset_interrupt_capability(adapter);
1139
1140 /* If we can't do MSI-X, try MSI */
1141 msi_only:
1142 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1143 #ifdef CONFIG_PCI_IOV
1144 /* disable SR-IOV for non MSI-X configurations */
1145 if (adapter->vf_data) {
1146 struct e1000_hw *hw = &adapter->hw;
1147 /* disable iov and allow time for transactions to clear */
1148 pci_disable_sriov(adapter->pdev);
1149 msleep(500);
1150
1151 kfree(adapter->vf_data);
1152 adapter->vf_data = NULL;
1153 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1154 wrfl();
1155 msleep(100);
1156 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1157 }
1158 #endif
1159 adapter->vfs_allocated_count = 0;
1160 adapter->rss_queues = 1;
1161 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1162 adapter->num_rx_queues = 1;
1163 adapter->num_tx_queues = 1;
1164 adapter->num_q_vectors = 1;
1165 if (!pci_enable_msi(adapter->pdev))
1166 adapter->flags |= IGB_FLAG_HAS_MSI;
1167 }
1168
1169 static void igb_add_ring(struct igb_ring *ring,
1170 struct igb_ring_container *head)
1171 {
1172 head->ring = ring;
1173 head->count++;
1174 }
1175
1176 /**
1177 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1178 * @adapter: board private structure to initialize
1179 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1180 * @v_idx: index of vector in adapter struct
1181 * @txr_count: total number of Tx rings to allocate
1182 * @txr_idx: index of first Tx ring to allocate
1183 * @rxr_count: total number of Rx rings to allocate
1184 * @rxr_idx: index of first Rx ring to allocate
1185 *
1186 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1187 **/
1188 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1189 int v_count, int v_idx,
1190 int txr_count, int txr_idx,
1191 int rxr_count, int rxr_idx)
1192 {
1193 struct igb_q_vector *q_vector;
1194 struct igb_ring *ring;
1195 int ring_count, size;
1196
1197 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1198 if (txr_count > 1 || rxr_count > 1)
1199 return -ENOMEM;
1200
1201 ring_count = txr_count + rxr_count;
1202 size = sizeof(struct igb_q_vector) +
1203 (sizeof(struct igb_ring) * ring_count);
1204
1205 /* allocate q_vector and rings */
1206 q_vector = adapter->q_vector[v_idx];
1207 if (!q_vector)
1208 q_vector = kzalloc(size, GFP_KERNEL);
1209 if (!q_vector)
1210 return -ENOMEM;
1211
1212 /* initialize NAPI */
1213 netif_napi_add(adapter->netdev, &q_vector->napi,
1214 igb_poll, 64);
1215
1216 /* tie q_vector and adapter together */
1217 adapter->q_vector[v_idx] = q_vector;
1218 q_vector->adapter = adapter;
1219
1220 /* initialize work limits */
1221 q_vector->tx.work_limit = adapter->tx_work_limit;
1222
1223 /* initialize ITR configuration */
1224 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1225 q_vector->itr_val = IGB_START_ITR;
1226
1227 /* initialize pointer to rings */
1228 ring = q_vector->ring;
1229
1230 /* intialize ITR */
1231 if (rxr_count) {
1232 /* rx or rx/tx vector */
1233 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1234 q_vector->itr_val = adapter->rx_itr_setting;
1235 } else {
1236 /* tx only vector */
1237 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1238 q_vector->itr_val = adapter->tx_itr_setting;
1239 }
1240
1241 if (txr_count) {
1242 /* assign generic ring traits */
1243 ring->dev = &adapter->pdev->dev;
1244 ring->netdev = adapter->netdev;
1245
1246 /* configure backlink on ring */
1247 ring->q_vector = q_vector;
1248
1249 /* update q_vector Tx values */
1250 igb_add_ring(ring, &q_vector->tx);
1251
1252 /* For 82575, context index must be unique per ring. */
1253 if (adapter->hw.mac.type == e1000_82575)
1254 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1255
1256 /* apply Tx specific ring traits */
1257 ring->count = adapter->tx_ring_count;
1258 ring->queue_index = txr_idx;
1259
1260 u64_stats_init(&ring->tx_syncp);
1261 u64_stats_init(&ring->tx_syncp2);
1262
1263 /* assign ring to adapter */
1264 adapter->tx_ring[txr_idx] = ring;
1265
1266 /* push pointer to next ring */
1267 ring++;
1268 }
1269
1270 if (rxr_count) {
1271 /* assign generic ring traits */
1272 ring->dev = &adapter->pdev->dev;
1273 ring->netdev = adapter->netdev;
1274
1275 /* configure backlink on ring */
1276 ring->q_vector = q_vector;
1277
1278 /* update q_vector Rx values */
1279 igb_add_ring(ring, &q_vector->rx);
1280
1281 /* set flag indicating ring supports SCTP checksum offload */
1282 if (adapter->hw.mac.type >= e1000_82576)
1283 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1284
1285 /* On i350, i354, i210, and i211, loopback VLAN packets
1286 * have the tag byte-swapped.
1287 */
1288 if (adapter->hw.mac.type >= e1000_i350)
1289 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1290
1291 /* apply Rx specific ring traits */
1292 ring->count = adapter->rx_ring_count;
1293 ring->queue_index = rxr_idx;
1294
1295 u64_stats_init(&ring->rx_syncp);
1296
1297 /* assign ring to adapter */
1298 adapter->rx_ring[rxr_idx] = ring;
1299 }
1300
1301 return 0;
1302 }
1303
1304
1305 /**
1306 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1307 * @adapter: board private structure to initialize
1308 *
1309 * We allocate one q_vector per queue interrupt. If allocation fails we
1310 * return -ENOMEM.
1311 **/
1312 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1313 {
1314 int q_vectors = adapter->num_q_vectors;
1315 int rxr_remaining = adapter->num_rx_queues;
1316 int txr_remaining = adapter->num_tx_queues;
1317 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1318 int err;
1319
1320 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1321 for (; rxr_remaining; v_idx++) {
1322 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1323 0, 0, 1, rxr_idx);
1324
1325 if (err)
1326 goto err_out;
1327
1328 /* update counts and index */
1329 rxr_remaining--;
1330 rxr_idx++;
1331 }
1332 }
1333
1334 for (; v_idx < q_vectors; v_idx++) {
1335 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1336 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1337
1338 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1339 tqpv, txr_idx, rqpv, rxr_idx);
1340
1341 if (err)
1342 goto err_out;
1343
1344 /* update counts and index */
1345 rxr_remaining -= rqpv;
1346 txr_remaining -= tqpv;
1347 rxr_idx++;
1348 txr_idx++;
1349 }
1350
1351 return 0;
1352
1353 err_out:
1354 adapter->num_tx_queues = 0;
1355 adapter->num_rx_queues = 0;
1356 adapter->num_q_vectors = 0;
1357
1358 while (v_idx--)
1359 igb_free_q_vector(adapter, v_idx);
1360
1361 return -ENOMEM;
1362 }
1363
1364 /**
1365 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1366 * @adapter: board private structure to initialize
1367 * @msix: boolean value of MSIX capability
1368 *
1369 * This function initializes the interrupts and allocates all of the queues.
1370 **/
1371 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1372 {
1373 struct pci_dev *pdev = adapter->pdev;
1374 int err;
1375
1376 igb_set_interrupt_capability(adapter, msix);
1377
1378 err = igb_alloc_q_vectors(adapter);
1379 if (err) {
1380 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1381 goto err_alloc_q_vectors;
1382 }
1383
1384 igb_cache_ring_register(adapter);
1385
1386 return 0;
1387
1388 err_alloc_q_vectors:
1389 igb_reset_interrupt_capability(adapter);
1390 return err;
1391 }
1392
1393 /**
1394 * igb_request_irq - initialize interrupts
1395 * @adapter: board private structure to initialize
1396 *
1397 * Attempts to configure interrupts using the best available
1398 * capabilities of the hardware and kernel.
1399 **/
1400 static int igb_request_irq(struct igb_adapter *adapter)
1401 {
1402 struct net_device *netdev = adapter->netdev;
1403 struct pci_dev *pdev = adapter->pdev;
1404 int err = 0;
1405
1406 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1407 err = igb_request_msix(adapter);
1408 if (!err)
1409 goto request_done;
1410 /* fall back to MSI */
1411 igb_free_all_tx_resources(adapter);
1412 igb_free_all_rx_resources(adapter);
1413
1414 igb_clear_interrupt_scheme(adapter);
1415 err = igb_init_interrupt_scheme(adapter, false);
1416 if (err)
1417 goto request_done;
1418
1419 igb_setup_all_tx_resources(adapter);
1420 igb_setup_all_rx_resources(adapter);
1421 igb_configure(adapter);
1422 }
1423
1424 igb_assign_vector(adapter->q_vector[0], 0);
1425
1426 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1427 err = request_irq(pdev->irq, igb_intr_msi, 0,
1428 netdev->name, adapter);
1429 if (!err)
1430 goto request_done;
1431
1432 /* fall back to legacy interrupts */
1433 igb_reset_interrupt_capability(adapter);
1434 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1435 }
1436
1437 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1438 netdev->name, adapter);
1439
1440 if (err)
1441 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1442 err);
1443
1444 request_done:
1445 return err;
1446 }
1447
1448 static void igb_free_irq(struct igb_adapter *adapter)
1449 {
1450 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1451 int vector = 0, i;
1452
1453 free_irq(adapter->msix_entries[vector++].vector, adapter);
1454
1455 for (i = 0; i < adapter->num_q_vectors; i++)
1456 free_irq(adapter->msix_entries[vector++].vector,
1457 adapter->q_vector[i]);
1458 } else {
1459 free_irq(adapter->pdev->irq, adapter);
1460 }
1461 }
1462
1463 /**
1464 * igb_irq_disable - Mask off interrupt generation on the NIC
1465 * @adapter: board private structure
1466 **/
1467 static void igb_irq_disable(struct igb_adapter *adapter)
1468 {
1469 struct e1000_hw *hw = &adapter->hw;
1470
1471 /* we need to be careful when disabling interrupts. The VFs are also
1472 * mapped into these registers and so clearing the bits can cause
1473 * issues on the VF drivers so we only need to clear what we set
1474 */
1475 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1476 u32 regval = rd32(E1000_EIAM);
1477
1478 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1479 wr32(E1000_EIMC, adapter->eims_enable_mask);
1480 regval = rd32(E1000_EIAC);
1481 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1482 }
1483
1484 wr32(E1000_IAM, 0);
1485 wr32(E1000_IMC, ~0);
1486 wrfl();
1487 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1488 int i;
1489
1490 for (i = 0; i < adapter->num_q_vectors; i++)
1491 synchronize_irq(adapter->msix_entries[i].vector);
1492 } else {
1493 synchronize_irq(adapter->pdev->irq);
1494 }
1495 }
1496
1497 /**
1498 * igb_irq_enable - Enable default interrupt generation settings
1499 * @adapter: board private structure
1500 **/
1501 static void igb_irq_enable(struct igb_adapter *adapter)
1502 {
1503 struct e1000_hw *hw = &adapter->hw;
1504
1505 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1506 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1507 u32 regval = rd32(E1000_EIAC);
1508
1509 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1510 regval = rd32(E1000_EIAM);
1511 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1512 wr32(E1000_EIMS, adapter->eims_enable_mask);
1513 if (adapter->vfs_allocated_count) {
1514 wr32(E1000_MBVFIMR, 0xFF);
1515 ims |= E1000_IMS_VMMB;
1516 }
1517 wr32(E1000_IMS, ims);
1518 } else {
1519 wr32(E1000_IMS, IMS_ENABLE_MASK |
1520 E1000_IMS_DRSTA);
1521 wr32(E1000_IAM, IMS_ENABLE_MASK |
1522 E1000_IMS_DRSTA);
1523 }
1524 }
1525
1526 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1527 {
1528 struct e1000_hw *hw = &adapter->hw;
1529 u16 vid = adapter->hw.mng_cookie.vlan_id;
1530 u16 old_vid = adapter->mng_vlan_id;
1531
1532 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1533 /* add VID to filter table */
1534 igb_vfta_set(hw, vid, true);
1535 adapter->mng_vlan_id = vid;
1536 } else {
1537 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1538 }
1539
1540 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1541 (vid != old_vid) &&
1542 !test_bit(old_vid, adapter->active_vlans)) {
1543 /* remove VID from filter table */
1544 igb_vfta_set(hw, old_vid, false);
1545 }
1546 }
1547
1548 /**
1549 * igb_release_hw_control - release control of the h/w to f/w
1550 * @adapter: address of board private structure
1551 *
1552 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1553 * For ASF and Pass Through versions of f/w this means that the
1554 * driver is no longer loaded.
1555 **/
1556 static void igb_release_hw_control(struct igb_adapter *adapter)
1557 {
1558 struct e1000_hw *hw = &adapter->hw;
1559 u32 ctrl_ext;
1560
1561 /* Let firmware take over control of h/w */
1562 ctrl_ext = rd32(E1000_CTRL_EXT);
1563 wr32(E1000_CTRL_EXT,
1564 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1565 }
1566
1567 /**
1568 * igb_get_hw_control - get control of the h/w from f/w
1569 * @adapter: address of board private structure
1570 *
1571 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1572 * For ASF and Pass Through versions of f/w this means that
1573 * the driver is loaded.
1574 **/
1575 static void igb_get_hw_control(struct igb_adapter *adapter)
1576 {
1577 struct e1000_hw *hw = &adapter->hw;
1578 u32 ctrl_ext;
1579
1580 /* Let firmware know the driver has taken over */
1581 ctrl_ext = rd32(E1000_CTRL_EXT);
1582 wr32(E1000_CTRL_EXT,
1583 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1584 }
1585
1586 /**
1587 * igb_configure - configure the hardware for RX and TX
1588 * @adapter: private board structure
1589 **/
1590 static void igb_configure(struct igb_adapter *adapter)
1591 {
1592 struct net_device *netdev = adapter->netdev;
1593 int i;
1594
1595 igb_get_hw_control(adapter);
1596 igb_set_rx_mode(netdev);
1597
1598 igb_restore_vlan(adapter);
1599
1600 igb_setup_tctl(adapter);
1601 igb_setup_mrqc(adapter);
1602 igb_setup_rctl(adapter);
1603
1604 igb_configure_tx(adapter);
1605 igb_configure_rx(adapter);
1606
1607 igb_rx_fifo_flush_82575(&adapter->hw);
1608
1609 /* call igb_desc_unused which always leaves
1610 * at least 1 descriptor unused to make sure
1611 * next_to_use != next_to_clean
1612 */
1613 for (i = 0; i < adapter->num_rx_queues; i++) {
1614 struct igb_ring *ring = adapter->rx_ring[i];
1615 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1616 }
1617 }
1618
1619 /**
1620 * igb_power_up_link - Power up the phy/serdes link
1621 * @adapter: address of board private structure
1622 **/
1623 void igb_power_up_link(struct igb_adapter *adapter)
1624 {
1625 igb_reset_phy(&adapter->hw);
1626
1627 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1628 igb_power_up_phy_copper(&adapter->hw);
1629 else
1630 igb_power_up_serdes_link_82575(&adapter->hw);
1631
1632 igb_setup_link(&adapter->hw);
1633 }
1634
1635 /**
1636 * igb_power_down_link - Power down the phy/serdes link
1637 * @adapter: address of board private structure
1638 */
1639 static void igb_power_down_link(struct igb_adapter *adapter)
1640 {
1641 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1642 igb_power_down_phy_copper_82575(&adapter->hw);
1643 else
1644 igb_shutdown_serdes_link_82575(&adapter->hw);
1645 }
1646
1647 /**
1648 * Detect and switch function for Media Auto Sense
1649 * @adapter: address of the board private structure
1650 **/
1651 static void igb_check_swap_media(struct igb_adapter *adapter)
1652 {
1653 struct e1000_hw *hw = &adapter->hw;
1654 u32 ctrl_ext, connsw;
1655 bool swap_now = false;
1656
1657 ctrl_ext = rd32(E1000_CTRL_EXT);
1658 connsw = rd32(E1000_CONNSW);
1659
1660 /* need to live swap if current media is copper and we have fiber/serdes
1661 * to go to.
1662 */
1663
1664 if ((hw->phy.media_type == e1000_media_type_copper) &&
1665 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1666 swap_now = true;
1667 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1668 /* copper signal takes time to appear */
1669 if (adapter->copper_tries < 4) {
1670 adapter->copper_tries++;
1671 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1672 wr32(E1000_CONNSW, connsw);
1673 return;
1674 } else {
1675 adapter->copper_tries = 0;
1676 if ((connsw & E1000_CONNSW_PHYSD) &&
1677 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1678 swap_now = true;
1679 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1680 wr32(E1000_CONNSW, connsw);
1681 }
1682 }
1683 }
1684
1685 if (!swap_now)
1686 return;
1687
1688 switch (hw->phy.media_type) {
1689 case e1000_media_type_copper:
1690 netdev_info(adapter->netdev,
1691 "MAS: changing media to fiber/serdes\n");
1692 ctrl_ext |=
1693 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1694 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1695 adapter->copper_tries = 0;
1696 break;
1697 case e1000_media_type_internal_serdes:
1698 case e1000_media_type_fiber:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to copper\n");
1701 ctrl_ext &=
1702 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 break;
1705 default:
1706 /* shouldn't get here during regular operation */
1707 netdev_err(adapter->netdev,
1708 "AMS: Invalid media type found, returning\n");
1709 break;
1710 }
1711 wr32(E1000_CTRL_EXT, ctrl_ext);
1712 }
1713
1714 /**
1715 * igb_up - Open the interface and prepare it to handle traffic
1716 * @adapter: board private structure
1717 **/
1718 int igb_up(struct igb_adapter *adapter)
1719 {
1720 struct e1000_hw *hw = &adapter->hw;
1721 int i;
1722
1723 /* hardware has been reset, we need to reload some things */
1724 igb_configure(adapter);
1725
1726 clear_bit(__IGB_DOWN, &adapter->state);
1727
1728 for (i = 0; i < adapter->num_q_vectors; i++)
1729 napi_enable(&(adapter->q_vector[i]->napi));
1730
1731 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1732 igb_configure_msix(adapter);
1733 else
1734 igb_assign_vector(adapter->q_vector[0], 0);
1735
1736 /* Clear any pending interrupts. */
1737 rd32(E1000_ICR);
1738 igb_irq_enable(adapter);
1739
1740 /* notify VFs that reset has been completed */
1741 if (adapter->vfs_allocated_count) {
1742 u32 reg_data = rd32(E1000_CTRL_EXT);
1743
1744 reg_data |= E1000_CTRL_EXT_PFRSTD;
1745 wr32(E1000_CTRL_EXT, reg_data);
1746 }
1747
1748 netif_tx_start_all_queues(adapter->netdev);
1749
1750 /* start the watchdog. */
1751 hw->mac.get_link_status = 1;
1752 schedule_work(&adapter->watchdog_task);
1753
1754 if ((adapter->flags & IGB_FLAG_EEE) &&
1755 (!hw->dev_spec._82575.eee_disable))
1756 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1757
1758 return 0;
1759 }
1760
1761 void igb_down(struct igb_adapter *adapter)
1762 {
1763 struct net_device *netdev = adapter->netdev;
1764 struct e1000_hw *hw = &adapter->hw;
1765 u32 tctl, rctl;
1766 int i;
1767
1768 /* signal that we're down so the interrupt handler does not
1769 * reschedule our watchdog timer
1770 */
1771 set_bit(__IGB_DOWN, &adapter->state);
1772
1773 /* disable receives in the hardware */
1774 rctl = rd32(E1000_RCTL);
1775 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1776 /* flush and sleep below */
1777
1778 netif_tx_stop_all_queues(netdev);
1779
1780 /* disable transmits in the hardware */
1781 tctl = rd32(E1000_TCTL);
1782 tctl &= ~E1000_TCTL_EN;
1783 wr32(E1000_TCTL, tctl);
1784 /* flush both disables and wait for them to finish */
1785 wrfl();
1786 usleep_range(10000, 11000);
1787
1788 igb_irq_disable(adapter);
1789
1790 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1791
1792 for (i = 0; i < adapter->num_q_vectors; i++) {
1793 napi_synchronize(&(adapter->q_vector[i]->napi));
1794 napi_disable(&(adapter->q_vector[i]->napi));
1795 }
1796
1797
1798 del_timer_sync(&adapter->watchdog_timer);
1799 del_timer_sync(&adapter->phy_info_timer);
1800
1801 netif_carrier_off(netdev);
1802
1803 /* record the stats before reset*/
1804 spin_lock(&adapter->stats64_lock);
1805 igb_update_stats(adapter, &adapter->stats64);
1806 spin_unlock(&adapter->stats64_lock);
1807
1808 adapter->link_speed = 0;
1809 adapter->link_duplex = 0;
1810
1811 if (!pci_channel_offline(adapter->pdev))
1812 igb_reset(adapter);
1813 igb_clean_all_tx_rings(adapter);
1814 igb_clean_all_rx_rings(adapter);
1815 #ifdef CONFIG_IGB_DCA
1816
1817 /* since we reset the hardware DCA settings were cleared */
1818 igb_setup_dca(adapter);
1819 #endif
1820 }
1821
1822 void igb_reinit_locked(struct igb_adapter *adapter)
1823 {
1824 WARN_ON(in_interrupt());
1825 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1826 usleep_range(1000, 2000);
1827 igb_down(adapter);
1828 igb_up(adapter);
1829 clear_bit(__IGB_RESETTING, &adapter->state);
1830 }
1831
1832 /** igb_enable_mas - Media Autosense re-enable after swap
1833 *
1834 * @adapter: adapter struct
1835 **/
1836 static s32 igb_enable_mas(struct igb_adapter *adapter)
1837 {
1838 struct e1000_hw *hw = &adapter->hw;
1839 u32 connsw;
1840 s32 ret_val = 0;
1841
1842 connsw = rd32(E1000_CONNSW);
1843 if (!(hw->phy.media_type == e1000_media_type_copper))
1844 return ret_val;
1845
1846 /* configure for SerDes media detect */
1847 if (!(connsw & E1000_CONNSW_SERDESD)) {
1848 connsw |= E1000_CONNSW_ENRGSRC;
1849 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1850 wr32(E1000_CONNSW, connsw);
1851 wrfl();
1852 } else if (connsw & E1000_CONNSW_SERDESD) {
1853 /* already SerDes, no need to enable anything */
1854 return ret_val;
1855 } else {
1856 netdev_info(adapter->netdev,
1857 "MAS: Unable to configure feature, disabling..\n");
1858 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1859 }
1860 return ret_val;
1861 }
1862
1863 void igb_reset(struct igb_adapter *adapter)
1864 {
1865 struct pci_dev *pdev = adapter->pdev;
1866 struct e1000_hw *hw = &adapter->hw;
1867 struct e1000_mac_info *mac = &hw->mac;
1868 struct e1000_fc_info *fc = &hw->fc;
1869 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1870
1871 /* Repartition Pba for greater than 9k mtu
1872 * To take effect CTRL.RST is required.
1873 */
1874 switch (mac->type) {
1875 case e1000_i350:
1876 case e1000_i354:
1877 case e1000_82580:
1878 pba = rd32(E1000_RXPBS);
1879 pba = igb_rxpbs_adjust_82580(pba);
1880 break;
1881 case e1000_82576:
1882 pba = rd32(E1000_RXPBS);
1883 pba &= E1000_RXPBS_SIZE_MASK_82576;
1884 break;
1885 case e1000_82575:
1886 case e1000_i210:
1887 case e1000_i211:
1888 default:
1889 pba = E1000_PBA_34K;
1890 break;
1891 }
1892
1893 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1894 (mac->type < e1000_82576)) {
1895 /* adjust PBA for jumbo frames */
1896 wr32(E1000_PBA, pba);
1897
1898 /* To maintain wire speed transmits, the Tx FIFO should be
1899 * large enough to accommodate two full transmit packets,
1900 * rounded up to the next 1KB and expressed in KB. Likewise,
1901 * the Rx FIFO should be large enough to accommodate at least
1902 * one full receive packet and is similarly rounded up and
1903 * expressed in KB.
1904 */
1905 pba = rd32(E1000_PBA);
1906 /* upper 16 bits has Tx packet buffer allocation size in KB */
1907 tx_space = pba >> 16;
1908 /* lower 16 bits has Rx packet buffer allocation size in KB */
1909 pba &= 0xffff;
1910 /* the Tx fifo also stores 16 bytes of information about the Tx
1911 * but don't include ethernet FCS because hardware appends it
1912 */
1913 min_tx_space = (adapter->max_frame_size +
1914 sizeof(union e1000_adv_tx_desc) -
1915 ETH_FCS_LEN) * 2;
1916 min_tx_space = ALIGN(min_tx_space, 1024);
1917 min_tx_space >>= 10;
1918 /* software strips receive CRC, so leave room for it */
1919 min_rx_space = adapter->max_frame_size;
1920 min_rx_space = ALIGN(min_rx_space, 1024);
1921 min_rx_space >>= 10;
1922
1923 /* If current Tx allocation is less than the min Tx FIFO size,
1924 * and the min Tx FIFO size is less than the current Rx FIFO
1925 * allocation, take space away from current Rx allocation
1926 */
1927 if (tx_space < min_tx_space &&
1928 ((min_tx_space - tx_space) < pba)) {
1929 pba = pba - (min_tx_space - tx_space);
1930
1931 /* if short on Rx space, Rx wins and must trump Tx
1932 * adjustment
1933 */
1934 if (pba < min_rx_space)
1935 pba = min_rx_space;
1936 }
1937 wr32(E1000_PBA, pba);
1938 }
1939
1940 /* flow control settings */
1941 /* The high water mark must be low enough to fit one full frame
1942 * (or the size used for early receive) above it in the Rx FIFO.
1943 * Set it to the lower of:
1944 * - 90% of the Rx FIFO size, or
1945 * - the full Rx FIFO size minus one full frame
1946 */
1947 hwm = min(((pba << 10) * 9 / 10),
1948 ((pba << 10) - 2 * adapter->max_frame_size));
1949
1950 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1951 fc->low_water = fc->high_water - 16;
1952 fc->pause_time = 0xFFFF;
1953 fc->send_xon = 1;
1954 fc->current_mode = fc->requested_mode;
1955
1956 /* disable receive for all VFs and wait one second */
1957 if (adapter->vfs_allocated_count) {
1958 int i;
1959
1960 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1961 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1962
1963 /* ping all the active vfs to let them know we are going down */
1964 igb_ping_all_vfs(adapter);
1965
1966 /* disable transmits and receives */
1967 wr32(E1000_VFRE, 0);
1968 wr32(E1000_VFTE, 0);
1969 }
1970
1971 /* Allow time for pending master requests to run */
1972 hw->mac.ops.reset_hw(hw);
1973 wr32(E1000_WUC, 0);
1974
1975 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1976 /* need to resetup here after media swap */
1977 adapter->ei.get_invariants(hw);
1978 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1979 }
1980 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1981 if (igb_enable_mas(adapter))
1982 dev_err(&pdev->dev,
1983 "Error enabling Media Auto Sense\n");
1984 }
1985 if (hw->mac.ops.init_hw(hw))
1986 dev_err(&pdev->dev, "Hardware Error\n");
1987
1988 /* Flow control settings reset on hardware reset, so guarantee flow
1989 * control is off when forcing speed.
1990 */
1991 if (!hw->mac.autoneg)
1992 igb_force_mac_fc(hw);
1993
1994 igb_init_dmac(adapter, pba);
1995 #ifdef CONFIG_IGB_HWMON
1996 /* Re-initialize the thermal sensor on i350 devices. */
1997 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1998 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1999 /* If present, re-initialize the external thermal sensor
2000 * interface.
2001 */
2002 if (adapter->ets)
2003 mac->ops.init_thermal_sensor_thresh(hw);
2004 }
2005 }
2006 #endif
2007 /* Re-establish EEE setting */
2008 if (hw->phy.media_type == e1000_media_type_copper) {
2009 switch (mac->type) {
2010 case e1000_i350:
2011 case e1000_i210:
2012 case e1000_i211:
2013 igb_set_eee_i350(hw, true, true);
2014 break;
2015 case e1000_i354:
2016 igb_set_eee_i354(hw, true, true);
2017 break;
2018 default:
2019 break;
2020 }
2021 }
2022 if (!netif_running(adapter->netdev))
2023 igb_power_down_link(adapter);
2024
2025 igb_update_mng_vlan(adapter);
2026
2027 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2028 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2029
2030 /* Re-enable PTP, where applicable. */
2031 igb_ptp_reset(adapter);
2032
2033 igb_get_phy_info(hw);
2034 }
2035
2036 static netdev_features_t igb_fix_features(struct net_device *netdev,
2037 netdev_features_t features)
2038 {
2039 /* Since there is no support for separate Rx/Tx vlan accel
2040 * enable/disable make sure Tx flag is always in same state as Rx.
2041 */
2042 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2043 features |= NETIF_F_HW_VLAN_CTAG_TX;
2044 else
2045 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2046
2047 return features;
2048 }
2049
2050 static int igb_set_features(struct net_device *netdev,
2051 netdev_features_t features)
2052 {
2053 netdev_features_t changed = netdev->features ^ features;
2054 struct igb_adapter *adapter = netdev_priv(netdev);
2055
2056 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2057 igb_vlan_mode(netdev, features);
2058
2059 if (!(changed & NETIF_F_RXALL))
2060 return 0;
2061
2062 netdev->features = features;
2063
2064 if (netif_running(netdev))
2065 igb_reinit_locked(adapter);
2066 else
2067 igb_reset(adapter);
2068
2069 return 0;
2070 }
2071
2072 static const struct net_device_ops igb_netdev_ops = {
2073 .ndo_open = igb_open,
2074 .ndo_stop = igb_close,
2075 .ndo_start_xmit = igb_xmit_frame,
2076 .ndo_get_stats64 = igb_get_stats64,
2077 .ndo_set_rx_mode = igb_set_rx_mode,
2078 .ndo_set_mac_address = igb_set_mac,
2079 .ndo_change_mtu = igb_change_mtu,
2080 .ndo_do_ioctl = igb_ioctl,
2081 .ndo_tx_timeout = igb_tx_timeout,
2082 .ndo_validate_addr = eth_validate_addr,
2083 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2084 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2085 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2086 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2087 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2088 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2089 .ndo_get_vf_config = igb_ndo_get_vf_config,
2090 #ifdef CONFIG_NET_POLL_CONTROLLER
2091 .ndo_poll_controller = igb_netpoll,
2092 #endif
2093 .ndo_fix_features = igb_fix_features,
2094 .ndo_set_features = igb_set_features,
2095 };
2096
2097 /**
2098 * igb_set_fw_version - Configure version string for ethtool
2099 * @adapter: adapter struct
2100 **/
2101 void igb_set_fw_version(struct igb_adapter *adapter)
2102 {
2103 struct e1000_hw *hw = &adapter->hw;
2104 struct e1000_fw_version fw;
2105
2106 igb_get_fw_version(hw, &fw);
2107
2108 switch (hw->mac.type) {
2109 case e1000_i210:
2110 case e1000_i211:
2111 if (!(igb_get_flash_presence_i210(hw))) {
2112 snprintf(adapter->fw_version,
2113 sizeof(adapter->fw_version),
2114 "%2d.%2d-%d",
2115 fw.invm_major, fw.invm_minor,
2116 fw.invm_img_type);
2117 break;
2118 }
2119 /* fall through */
2120 default:
2121 /* if option is rom valid, display its version too */
2122 if (fw.or_valid) {
2123 snprintf(adapter->fw_version,
2124 sizeof(adapter->fw_version),
2125 "%d.%d, 0x%08x, %d.%d.%d",
2126 fw.eep_major, fw.eep_minor, fw.etrack_id,
2127 fw.or_major, fw.or_build, fw.or_patch);
2128 /* no option rom */
2129 } else if (fw.etrack_id != 0X0000) {
2130 snprintf(adapter->fw_version,
2131 sizeof(adapter->fw_version),
2132 "%d.%d, 0x%08x",
2133 fw.eep_major, fw.eep_minor, fw.etrack_id);
2134 } else {
2135 snprintf(adapter->fw_version,
2136 sizeof(adapter->fw_version),
2137 "%d.%d.%d",
2138 fw.eep_major, fw.eep_minor, fw.eep_build);
2139 }
2140 break;
2141 }
2142 }
2143
2144 /**
2145 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2146 *
2147 * @adapter: adapter struct
2148 **/
2149 static void igb_init_mas(struct igb_adapter *adapter)
2150 {
2151 struct e1000_hw *hw = &adapter->hw;
2152 u16 eeprom_data;
2153
2154 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2155 switch (hw->bus.func) {
2156 case E1000_FUNC_0:
2157 if (eeprom_data & IGB_MAS_ENABLE_0) {
2158 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2159 netdev_info(adapter->netdev,
2160 "MAS: Enabling Media Autosense for port %d\n",
2161 hw->bus.func);
2162 }
2163 break;
2164 case E1000_FUNC_1:
2165 if (eeprom_data & IGB_MAS_ENABLE_1) {
2166 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2167 netdev_info(adapter->netdev,
2168 "MAS: Enabling Media Autosense for port %d\n",
2169 hw->bus.func);
2170 }
2171 break;
2172 case E1000_FUNC_2:
2173 if (eeprom_data & IGB_MAS_ENABLE_2) {
2174 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2175 netdev_info(adapter->netdev,
2176 "MAS: Enabling Media Autosense for port %d\n",
2177 hw->bus.func);
2178 }
2179 break;
2180 case E1000_FUNC_3:
2181 if (eeprom_data & IGB_MAS_ENABLE_3) {
2182 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2183 netdev_info(adapter->netdev,
2184 "MAS: Enabling Media Autosense for port %d\n",
2185 hw->bus.func);
2186 }
2187 break;
2188 default:
2189 /* Shouldn't get here */
2190 netdev_err(adapter->netdev,
2191 "MAS: Invalid port configuration, returning\n");
2192 break;
2193 }
2194 }
2195
2196 /**
2197 * igb_init_i2c - Init I2C interface
2198 * @adapter: pointer to adapter structure
2199 **/
2200 static s32 igb_init_i2c(struct igb_adapter *adapter)
2201 {
2202 s32 status = 0;
2203
2204 /* I2C interface supported on i350 devices */
2205 if (adapter->hw.mac.type != e1000_i350)
2206 return 0;
2207
2208 /* Initialize the i2c bus which is controlled by the registers.
2209 * This bus will use the i2c_algo_bit structue that implements
2210 * the protocol through toggling of the 4 bits in the register.
2211 */
2212 adapter->i2c_adap.owner = THIS_MODULE;
2213 adapter->i2c_algo = igb_i2c_algo;
2214 adapter->i2c_algo.data = adapter;
2215 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2216 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2217 strlcpy(adapter->i2c_adap.name, "igb BB",
2218 sizeof(adapter->i2c_adap.name));
2219 status = i2c_bit_add_bus(&adapter->i2c_adap);
2220 return status;
2221 }
2222
2223 /**
2224 * igb_probe - Device Initialization Routine
2225 * @pdev: PCI device information struct
2226 * @ent: entry in igb_pci_tbl
2227 *
2228 * Returns 0 on success, negative on failure
2229 *
2230 * igb_probe initializes an adapter identified by a pci_dev structure.
2231 * The OS initialization, configuring of the adapter private structure,
2232 * and a hardware reset occur.
2233 **/
2234 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2235 {
2236 struct net_device *netdev;
2237 struct igb_adapter *adapter;
2238 struct e1000_hw *hw;
2239 u16 eeprom_data = 0;
2240 s32 ret_val;
2241 static int global_quad_port_a; /* global quad port a indication */
2242 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2243 int err, pci_using_dac;
2244 u8 part_str[E1000_PBANUM_LENGTH];
2245
2246 /* Catch broken hardware that put the wrong VF device ID in
2247 * the PCIe SR-IOV capability.
2248 */
2249 if (pdev->is_virtfn) {
2250 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2251 pci_name(pdev), pdev->vendor, pdev->device);
2252 return -EINVAL;
2253 }
2254
2255 err = pci_enable_device_mem(pdev);
2256 if (err)
2257 return err;
2258
2259 pci_using_dac = 0;
2260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2261 if (!err) {
2262 pci_using_dac = 1;
2263 } else {
2264 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2265 if (err) {
2266 dev_err(&pdev->dev,
2267 "No usable DMA configuration, aborting\n");
2268 goto err_dma;
2269 }
2270 }
2271
2272 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2273 IORESOURCE_MEM),
2274 igb_driver_name);
2275 if (err)
2276 goto err_pci_reg;
2277
2278 pci_enable_pcie_error_reporting(pdev);
2279
2280 pci_set_master(pdev);
2281 pci_save_state(pdev);
2282
2283 err = -ENOMEM;
2284 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2285 IGB_MAX_TX_QUEUES);
2286 if (!netdev)
2287 goto err_alloc_etherdev;
2288
2289 SET_NETDEV_DEV(netdev, &pdev->dev);
2290
2291 pci_set_drvdata(pdev, netdev);
2292 adapter = netdev_priv(netdev);
2293 adapter->netdev = netdev;
2294 adapter->pdev = pdev;
2295 hw = &adapter->hw;
2296 hw->back = adapter;
2297 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2298
2299 err = -EIO;
2300 hw->hw_addr = pci_iomap(pdev, 0, 0);
2301 if (!hw->hw_addr)
2302 goto err_ioremap;
2303
2304 netdev->netdev_ops = &igb_netdev_ops;
2305 igb_set_ethtool_ops(netdev);
2306 netdev->watchdog_timeo = 5 * HZ;
2307
2308 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2309
2310 netdev->mem_start = pci_resource_start(pdev, 0);
2311 netdev->mem_end = pci_resource_end(pdev, 0);
2312
2313 /* PCI config space info */
2314 hw->vendor_id = pdev->vendor;
2315 hw->device_id = pdev->device;
2316 hw->revision_id = pdev->revision;
2317 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2318 hw->subsystem_device_id = pdev->subsystem_device;
2319
2320 /* Copy the default MAC, PHY and NVM function pointers */
2321 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2322 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2323 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2324 /* Initialize skew-specific constants */
2325 err = ei->get_invariants(hw);
2326 if (err)
2327 goto err_sw_init;
2328
2329 /* setup the private structure */
2330 err = igb_sw_init(adapter);
2331 if (err)
2332 goto err_sw_init;
2333
2334 igb_get_bus_info_pcie(hw);
2335
2336 hw->phy.autoneg_wait_to_complete = false;
2337
2338 /* Copper options */
2339 if (hw->phy.media_type == e1000_media_type_copper) {
2340 hw->phy.mdix = AUTO_ALL_MODES;
2341 hw->phy.disable_polarity_correction = false;
2342 hw->phy.ms_type = e1000_ms_hw_default;
2343 }
2344
2345 if (igb_check_reset_block(hw))
2346 dev_info(&pdev->dev,
2347 "PHY reset is blocked due to SOL/IDER session.\n");
2348
2349 /* features is initialized to 0 in allocation, it might have bits
2350 * set by igb_sw_init so we should use an or instead of an
2351 * assignment.
2352 */
2353 netdev->features |= NETIF_F_SG |
2354 NETIF_F_IP_CSUM |
2355 NETIF_F_IPV6_CSUM |
2356 NETIF_F_TSO |
2357 NETIF_F_TSO6 |
2358 NETIF_F_RXHASH |
2359 NETIF_F_RXCSUM |
2360 NETIF_F_HW_VLAN_CTAG_RX |
2361 NETIF_F_HW_VLAN_CTAG_TX;
2362
2363 /* copy netdev features into list of user selectable features */
2364 netdev->hw_features |= netdev->features;
2365 netdev->hw_features |= NETIF_F_RXALL;
2366
2367 /* set this bit last since it cannot be part of hw_features */
2368 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2369
2370 netdev->vlan_features |= NETIF_F_TSO |
2371 NETIF_F_TSO6 |
2372 NETIF_F_IP_CSUM |
2373 NETIF_F_IPV6_CSUM |
2374 NETIF_F_SG;
2375
2376 netdev->priv_flags |= IFF_SUPP_NOFCS;
2377
2378 if (pci_using_dac) {
2379 netdev->features |= NETIF_F_HIGHDMA;
2380 netdev->vlan_features |= NETIF_F_HIGHDMA;
2381 }
2382
2383 if (hw->mac.type >= e1000_82576) {
2384 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2385 netdev->features |= NETIF_F_SCTP_CSUM;
2386 }
2387
2388 netdev->priv_flags |= IFF_UNICAST_FLT;
2389
2390 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2391
2392 /* before reading the NVM, reset the controller to put the device in a
2393 * known good starting state
2394 */
2395 hw->mac.ops.reset_hw(hw);
2396
2397 /* make sure the NVM is good , i211/i210 parts can have special NVM
2398 * that doesn't contain a checksum
2399 */
2400 switch (hw->mac.type) {
2401 case e1000_i210:
2402 case e1000_i211:
2403 if (igb_get_flash_presence_i210(hw)) {
2404 if (hw->nvm.ops.validate(hw) < 0) {
2405 dev_err(&pdev->dev,
2406 "The NVM Checksum Is Not Valid\n");
2407 err = -EIO;
2408 goto err_eeprom;
2409 }
2410 }
2411 break;
2412 default:
2413 if (hw->nvm.ops.validate(hw) < 0) {
2414 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2415 err = -EIO;
2416 goto err_eeprom;
2417 }
2418 break;
2419 }
2420
2421 /* copy the MAC address out of the NVM */
2422 if (hw->mac.ops.read_mac_addr(hw))
2423 dev_err(&pdev->dev, "NVM Read Error\n");
2424
2425 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2426
2427 if (!is_valid_ether_addr(netdev->dev_addr)) {
2428 dev_err(&pdev->dev, "Invalid MAC Address\n");
2429 err = -EIO;
2430 goto err_eeprom;
2431 }
2432
2433 /* get firmware version for ethtool -i */
2434 igb_set_fw_version(adapter);
2435
2436 /* configure RXPBSIZE and TXPBSIZE */
2437 if (hw->mac.type == e1000_i210) {
2438 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2439 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2440 }
2441
2442 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2443 (unsigned long) adapter);
2444 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2445 (unsigned long) adapter);
2446
2447 INIT_WORK(&adapter->reset_task, igb_reset_task);
2448 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2449
2450 /* Initialize link properties that are user-changeable */
2451 adapter->fc_autoneg = true;
2452 hw->mac.autoneg = true;
2453 hw->phy.autoneg_advertised = 0x2f;
2454
2455 hw->fc.requested_mode = e1000_fc_default;
2456 hw->fc.current_mode = e1000_fc_default;
2457
2458 igb_validate_mdi_setting(hw);
2459
2460 /* By default, support wake on port A */
2461 if (hw->bus.func == 0)
2462 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2463
2464 /* Check the NVM for wake support on non-port A ports */
2465 if (hw->mac.type >= e1000_82580)
2466 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2467 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2468 &eeprom_data);
2469 else if (hw->bus.func == 1)
2470 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2471
2472 if (eeprom_data & IGB_EEPROM_APME)
2473 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2474
2475 /* now that we have the eeprom settings, apply the special cases where
2476 * the eeprom may be wrong or the board simply won't support wake on
2477 * lan on a particular port
2478 */
2479 switch (pdev->device) {
2480 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2481 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2482 break;
2483 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2484 case E1000_DEV_ID_82576_FIBER:
2485 case E1000_DEV_ID_82576_SERDES:
2486 /* Wake events only supported on port A for dual fiber
2487 * regardless of eeprom setting
2488 */
2489 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2490 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2491 break;
2492 case E1000_DEV_ID_82576_QUAD_COPPER:
2493 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2494 /* if quad port adapter, disable WoL on all but port A */
2495 if (global_quad_port_a != 0)
2496 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2497 else
2498 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2499 /* Reset for multiple quad port adapters */
2500 if (++global_quad_port_a == 4)
2501 global_quad_port_a = 0;
2502 break;
2503 default:
2504 /* If the device can't wake, don't set software support */
2505 if (!device_can_wakeup(&adapter->pdev->dev))
2506 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2507 }
2508
2509 /* initialize the wol settings based on the eeprom settings */
2510 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2511 adapter->wol |= E1000_WUFC_MAG;
2512
2513 /* Some vendors want WoL disabled by default, but still supported */
2514 if ((hw->mac.type == e1000_i350) &&
2515 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2516 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2517 adapter->wol = 0;
2518 }
2519
2520 device_set_wakeup_enable(&adapter->pdev->dev,
2521 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2522
2523 /* reset the hardware with the new settings */
2524 igb_reset(adapter);
2525
2526 /* Init the I2C interface */
2527 err = igb_init_i2c(adapter);
2528 if (err) {
2529 dev_err(&pdev->dev, "failed to init i2c interface\n");
2530 goto err_eeprom;
2531 }
2532
2533 /* let the f/w know that the h/w is now under the control of the
2534 * driver.
2535 */
2536 igb_get_hw_control(adapter);
2537
2538 strcpy(netdev->name, "eth%d");
2539 err = register_netdev(netdev);
2540 if (err)
2541 goto err_register;
2542
2543 /* carrier off reporting is important to ethtool even BEFORE open */
2544 netif_carrier_off(netdev);
2545
2546 #ifdef CONFIG_IGB_DCA
2547 if (dca_add_requester(&pdev->dev) == 0) {
2548 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2549 dev_info(&pdev->dev, "DCA enabled\n");
2550 igb_setup_dca(adapter);
2551 }
2552
2553 #endif
2554 #ifdef CONFIG_IGB_HWMON
2555 /* Initialize the thermal sensor on i350 devices. */
2556 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2557 u16 ets_word;
2558
2559 /* Read the NVM to determine if this i350 device supports an
2560 * external thermal sensor.
2561 */
2562 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2563 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2564 adapter->ets = true;
2565 else
2566 adapter->ets = false;
2567 if (igb_sysfs_init(adapter))
2568 dev_err(&pdev->dev,
2569 "failed to allocate sysfs resources\n");
2570 } else {
2571 adapter->ets = false;
2572 }
2573 #endif
2574 /* Check if Media Autosense is enabled */
2575 adapter->ei = *ei;
2576 if (hw->dev_spec._82575.mas_capable)
2577 igb_init_mas(adapter);
2578
2579 /* do hw tstamp init after resetting */
2580 igb_ptp_init(adapter);
2581
2582 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2583 /* print bus type/speed/width info, not applicable to i354 */
2584 if (hw->mac.type != e1000_i354) {
2585 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2586 netdev->name,
2587 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2588 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2589 "unknown"),
2590 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2591 "Width x4" :
2592 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2593 "Width x2" :
2594 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2595 "Width x1" : "unknown"), netdev->dev_addr);
2596 }
2597
2598 if ((hw->mac.type >= e1000_i210 ||
2599 igb_get_flash_presence_i210(hw))) {
2600 ret_val = igb_read_part_string(hw, part_str,
2601 E1000_PBANUM_LENGTH);
2602 } else {
2603 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2604 }
2605
2606 if (ret_val)
2607 strcpy(part_str, "Unknown");
2608 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2609 dev_info(&pdev->dev,
2610 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2611 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2612 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2613 adapter->num_rx_queues, adapter->num_tx_queues);
2614 if (hw->phy.media_type == e1000_media_type_copper) {
2615 switch (hw->mac.type) {
2616 case e1000_i350:
2617 case e1000_i210:
2618 case e1000_i211:
2619 /* Enable EEE for internal copper PHY devices */
2620 err = igb_set_eee_i350(hw, true, true);
2621 if ((!err) &&
2622 (!hw->dev_spec._82575.eee_disable)) {
2623 adapter->eee_advert =
2624 MDIO_EEE_100TX | MDIO_EEE_1000T;
2625 adapter->flags |= IGB_FLAG_EEE;
2626 }
2627 break;
2628 case e1000_i354:
2629 if ((rd32(E1000_CTRL_EXT) &
2630 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2631 err = igb_set_eee_i354(hw, true, true);
2632 if ((!err) &&
2633 (!hw->dev_spec._82575.eee_disable)) {
2634 adapter->eee_advert =
2635 MDIO_EEE_100TX | MDIO_EEE_1000T;
2636 adapter->flags |= IGB_FLAG_EEE;
2637 }
2638 }
2639 break;
2640 default:
2641 break;
2642 }
2643 }
2644 pm_runtime_put_noidle(&pdev->dev);
2645 return 0;
2646
2647 err_register:
2648 igb_release_hw_control(adapter);
2649 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2650 err_eeprom:
2651 if (!igb_check_reset_block(hw))
2652 igb_reset_phy(hw);
2653
2654 if (hw->flash_address)
2655 iounmap(hw->flash_address);
2656 err_sw_init:
2657 igb_clear_interrupt_scheme(adapter);
2658 pci_iounmap(pdev, hw->hw_addr);
2659 err_ioremap:
2660 free_netdev(netdev);
2661 err_alloc_etherdev:
2662 pci_release_selected_regions(pdev,
2663 pci_select_bars(pdev, IORESOURCE_MEM));
2664 err_pci_reg:
2665 err_dma:
2666 pci_disable_device(pdev);
2667 return err;
2668 }
2669
2670 #ifdef CONFIG_PCI_IOV
2671 static int igb_disable_sriov(struct pci_dev *pdev)
2672 {
2673 struct net_device *netdev = pci_get_drvdata(pdev);
2674 struct igb_adapter *adapter = netdev_priv(netdev);
2675 struct e1000_hw *hw = &adapter->hw;
2676
2677 /* reclaim resources allocated to VFs */
2678 if (adapter->vf_data) {
2679 /* disable iov and allow time for transactions to clear */
2680 if (pci_vfs_assigned(pdev)) {
2681 dev_warn(&pdev->dev,
2682 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2683 return -EPERM;
2684 } else {
2685 pci_disable_sriov(pdev);
2686 msleep(500);
2687 }
2688
2689 kfree(adapter->vf_data);
2690 adapter->vf_data = NULL;
2691 adapter->vfs_allocated_count = 0;
2692 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2693 wrfl();
2694 msleep(100);
2695 dev_info(&pdev->dev, "IOV Disabled\n");
2696
2697 /* Re-enable DMA Coalescing flag since IOV is turned off */
2698 adapter->flags |= IGB_FLAG_DMAC;
2699 }
2700
2701 return 0;
2702 }
2703
2704 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2705 {
2706 struct net_device *netdev = pci_get_drvdata(pdev);
2707 struct igb_adapter *adapter = netdev_priv(netdev);
2708 int old_vfs = pci_num_vf(pdev);
2709 int err = 0;
2710 int i;
2711
2712 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2713 err = -EPERM;
2714 goto out;
2715 }
2716 if (!num_vfs)
2717 goto out;
2718
2719 if (old_vfs) {
2720 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2721 old_vfs, max_vfs);
2722 adapter->vfs_allocated_count = old_vfs;
2723 } else
2724 adapter->vfs_allocated_count = num_vfs;
2725
2726 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2727 sizeof(struct vf_data_storage), GFP_KERNEL);
2728
2729 /* if allocation failed then we do not support SR-IOV */
2730 if (!adapter->vf_data) {
2731 adapter->vfs_allocated_count = 0;
2732 dev_err(&pdev->dev,
2733 "Unable to allocate memory for VF Data Storage\n");
2734 err = -ENOMEM;
2735 goto out;
2736 }
2737
2738 /* only call pci_enable_sriov() if no VFs are allocated already */
2739 if (!old_vfs) {
2740 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2741 if (err)
2742 goto err_out;
2743 }
2744 dev_info(&pdev->dev, "%d VFs allocated\n",
2745 adapter->vfs_allocated_count);
2746 for (i = 0; i < adapter->vfs_allocated_count; i++)
2747 igb_vf_configure(adapter, i);
2748
2749 /* DMA Coalescing is not supported in IOV mode. */
2750 adapter->flags &= ~IGB_FLAG_DMAC;
2751 goto out;
2752
2753 err_out:
2754 kfree(adapter->vf_data);
2755 adapter->vf_data = NULL;
2756 adapter->vfs_allocated_count = 0;
2757 out:
2758 return err;
2759 }
2760
2761 #endif
2762 /**
2763 * igb_remove_i2c - Cleanup I2C interface
2764 * @adapter: pointer to adapter structure
2765 **/
2766 static void igb_remove_i2c(struct igb_adapter *adapter)
2767 {
2768 /* free the adapter bus structure */
2769 i2c_del_adapter(&adapter->i2c_adap);
2770 }
2771
2772 /**
2773 * igb_remove - Device Removal Routine
2774 * @pdev: PCI device information struct
2775 *
2776 * igb_remove is called by the PCI subsystem to alert the driver
2777 * that it should release a PCI device. The could be caused by a
2778 * Hot-Plug event, or because the driver is going to be removed from
2779 * memory.
2780 **/
2781 static void igb_remove(struct pci_dev *pdev)
2782 {
2783 struct net_device *netdev = pci_get_drvdata(pdev);
2784 struct igb_adapter *adapter = netdev_priv(netdev);
2785 struct e1000_hw *hw = &adapter->hw;
2786
2787 pm_runtime_get_noresume(&pdev->dev);
2788 #ifdef CONFIG_IGB_HWMON
2789 igb_sysfs_exit(adapter);
2790 #endif
2791 igb_remove_i2c(adapter);
2792 igb_ptp_stop(adapter);
2793 /* The watchdog timer may be rescheduled, so explicitly
2794 * disable watchdog from being rescheduled.
2795 */
2796 set_bit(__IGB_DOWN, &adapter->state);
2797 del_timer_sync(&adapter->watchdog_timer);
2798 del_timer_sync(&adapter->phy_info_timer);
2799
2800 cancel_work_sync(&adapter->reset_task);
2801 cancel_work_sync(&adapter->watchdog_task);
2802
2803 #ifdef CONFIG_IGB_DCA
2804 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2805 dev_info(&pdev->dev, "DCA disabled\n");
2806 dca_remove_requester(&pdev->dev);
2807 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2808 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2809 }
2810 #endif
2811
2812 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2813 * would have already happened in close and is redundant.
2814 */
2815 igb_release_hw_control(adapter);
2816
2817 unregister_netdev(netdev);
2818
2819 igb_clear_interrupt_scheme(adapter);
2820
2821 #ifdef CONFIG_PCI_IOV
2822 igb_disable_sriov(pdev);
2823 #endif
2824
2825 pci_iounmap(pdev, hw->hw_addr);
2826 if (hw->flash_address)
2827 iounmap(hw->flash_address);
2828 pci_release_selected_regions(pdev,
2829 pci_select_bars(pdev, IORESOURCE_MEM));
2830
2831 kfree(adapter->shadow_vfta);
2832 free_netdev(netdev);
2833
2834 pci_disable_pcie_error_reporting(pdev);
2835
2836 pci_disable_device(pdev);
2837 }
2838
2839 /**
2840 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2841 * @adapter: board private structure to initialize
2842 *
2843 * This function initializes the vf specific data storage and then attempts to
2844 * allocate the VFs. The reason for ordering it this way is because it is much
2845 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2846 * the memory for the VFs.
2847 **/
2848 static void igb_probe_vfs(struct igb_adapter *adapter)
2849 {
2850 #ifdef CONFIG_PCI_IOV
2851 struct pci_dev *pdev = adapter->pdev;
2852 struct e1000_hw *hw = &adapter->hw;
2853
2854 /* Virtualization features not supported on i210 family. */
2855 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2856 return;
2857
2858 pci_sriov_set_totalvfs(pdev, 7);
2859 igb_pci_enable_sriov(pdev, max_vfs);
2860
2861 #endif /* CONFIG_PCI_IOV */
2862 }
2863
2864 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2865 {
2866 struct e1000_hw *hw = &adapter->hw;
2867 u32 max_rss_queues;
2868
2869 /* Determine the maximum number of RSS queues supported. */
2870 switch (hw->mac.type) {
2871 case e1000_i211:
2872 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2873 break;
2874 case e1000_82575:
2875 case e1000_i210:
2876 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2877 break;
2878 case e1000_i350:
2879 /* I350 cannot do RSS and SR-IOV at the same time */
2880 if (!!adapter->vfs_allocated_count) {
2881 max_rss_queues = 1;
2882 break;
2883 }
2884 /* fall through */
2885 case e1000_82576:
2886 if (!!adapter->vfs_allocated_count) {
2887 max_rss_queues = 2;
2888 break;
2889 }
2890 /* fall through */
2891 case e1000_82580:
2892 case e1000_i354:
2893 default:
2894 max_rss_queues = IGB_MAX_RX_QUEUES;
2895 break;
2896 }
2897
2898 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2899
2900 /* Determine if we need to pair queues. */
2901 switch (hw->mac.type) {
2902 case e1000_82575:
2903 case e1000_i211:
2904 /* Device supports enough interrupts without queue pairing. */
2905 break;
2906 case e1000_82576:
2907 /* If VFs are going to be allocated with RSS queues then we
2908 * should pair the queues in order to conserve interrupts due
2909 * to limited supply.
2910 */
2911 if ((adapter->rss_queues > 1) &&
2912 (adapter->vfs_allocated_count > 6))
2913 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2914 /* fall through */
2915 case e1000_82580:
2916 case e1000_i350:
2917 case e1000_i354:
2918 case e1000_i210:
2919 default:
2920 /* If rss_queues > half of max_rss_queues, pair the queues in
2921 * order to conserve interrupts due to limited supply.
2922 */
2923 if (adapter->rss_queues > (max_rss_queues / 2))
2924 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2925 break;
2926 }
2927 }
2928
2929 /**
2930 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2931 * @adapter: board private structure to initialize
2932 *
2933 * igb_sw_init initializes the Adapter private data structure.
2934 * Fields are initialized based on PCI device information and
2935 * OS network device settings (MTU size).
2936 **/
2937 static int igb_sw_init(struct igb_adapter *adapter)
2938 {
2939 struct e1000_hw *hw = &adapter->hw;
2940 struct net_device *netdev = adapter->netdev;
2941 struct pci_dev *pdev = adapter->pdev;
2942
2943 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2944
2945 /* set default ring sizes */
2946 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2947 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2948
2949 /* set default ITR values */
2950 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2951 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2952
2953 /* set default work limits */
2954 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2955
2956 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2957 VLAN_HLEN;
2958 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2959
2960 spin_lock_init(&adapter->stats64_lock);
2961 #ifdef CONFIG_PCI_IOV
2962 switch (hw->mac.type) {
2963 case e1000_82576:
2964 case e1000_i350:
2965 if (max_vfs > 7) {
2966 dev_warn(&pdev->dev,
2967 "Maximum of 7 VFs per PF, using max\n");
2968 max_vfs = adapter->vfs_allocated_count = 7;
2969 } else
2970 adapter->vfs_allocated_count = max_vfs;
2971 if (adapter->vfs_allocated_count)
2972 dev_warn(&pdev->dev,
2973 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2974 break;
2975 default:
2976 break;
2977 }
2978 #endif /* CONFIG_PCI_IOV */
2979
2980 igb_init_queue_configuration(adapter);
2981
2982 /* Setup and initialize a copy of the hw vlan table array */
2983 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2984 GFP_ATOMIC);
2985
2986 /* This call may decrease the number of queues */
2987 if (igb_init_interrupt_scheme(adapter, true)) {
2988 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2989 return -ENOMEM;
2990 }
2991
2992 igb_probe_vfs(adapter);
2993
2994 /* Explicitly disable IRQ since the NIC can be in any state. */
2995 igb_irq_disable(adapter);
2996
2997 if (hw->mac.type >= e1000_i350)
2998 adapter->flags &= ~IGB_FLAG_DMAC;
2999
3000 set_bit(__IGB_DOWN, &adapter->state);
3001 return 0;
3002 }
3003
3004 /**
3005 * igb_open - Called when a network interface is made active
3006 * @netdev: network interface device structure
3007 *
3008 * Returns 0 on success, negative value on failure
3009 *
3010 * The open entry point is called when a network interface is made
3011 * active by the system (IFF_UP). At this point all resources needed
3012 * for transmit and receive operations are allocated, the interrupt
3013 * handler is registered with the OS, the watchdog timer is started,
3014 * and the stack is notified that the interface is ready.
3015 **/
3016 static int __igb_open(struct net_device *netdev, bool resuming)
3017 {
3018 struct igb_adapter *adapter = netdev_priv(netdev);
3019 struct e1000_hw *hw = &adapter->hw;
3020 struct pci_dev *pdev = adapter->pdev;
3021 int err;
3022 int i;
3023
3024 /* disallow open during test */
3025 if (test_bit(__IGB_TESTING, &adapter->state)) {
3026 WARN_ON(resuming);
3027 return -EBUSY;
3028 }
3029
3030 if (!resuming)
3031 pm_runtime_get_sync(&pdev->dev);
3032
3033 netif_carrier_off(netdev);
3034
3035 /* allocate transmit descriptors */
3036 err = igb_setup_all_tx_resources(adapter);
3037 if (err)
3038 goto err_setup_tx;
3039
3040 /* allocate receive descriptors */
3041 err = igb_setup_all_rx_resources(adapter);
3042 if (err)
3043 goto err_setup_rx;
3044
3045 igb_power_up_link(adapter);
3046
3047 /* before we allocate an interrupt, we must be ready to handle it.
3048 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3049 * as soon as we call pci_request_irq, so we have to setup our
3050 * clean_rx handler before we do so.
3051 */
3052 igb_configure(adapter);
3053
3054 err = igb_request_irq(adapter);
3055 if (err)
3056 goto err_req_irq;
3057
3058 /* Notify the stack of the actual queue counts. */
3059 err = netif_set_real_num_tx_queues(adapter->netdev,
3060 adapter->num_tx_queues);
3061 if (err)
3062 goto err_set_queues;
3063
3064 err = netif_set_real_num_rx_queues(adapter->netdev,
3065 adapter->num_rx_queues);
3066 if (err)
3067 goto err_set_queues;
3068
3069 /* From here on the code is the same as igb_up() */
3070 clear_bit(__IGB_DOWN, &adapter->state);
3071
3072 for (i = 0; i < adapter->num_q_vectors; i++)
3073 napi_enable(&(adapter->q_vector[i]->napi));
3074
3075 /* Clear any pending interrupts. */
3076 rd32(E1000_ICR);
3077
3078 igb_irq_enable(adapter);
3079
3080 /* notify VFs that reset has been completed */
3081 if (adapter->vfs_allocated_count) {
3082 u32 reg_data = rd32(E1000_CTRL_EXT);
3083
3084 reg_data |= E1000_CTRL_EXT_PFRSTD;
3085 wr32(E1000_CTRL_EXT, reg_data);
3086 }
3087
3088 netif_tx_start_all_queues(netdev);
3089
3090 if (!resuming)
3091 pm_runtime_put(&pdev->dev);
3092
3093 /* start the watchdog. */
3094 hw->mac.get_link_status = 1;
3095 schedule_work(&adapter->watchdog_task);
3096
3097 return 0;
3098
3099 err_set_queues:
3100 igb_free_irq(adapter);
3101 err_req_irq:
3102 igb_release_hw_control(adapter);
3103 igb_power_down_link(adapter);
3104 igb_free_all_rx_resources(adapter);
3105 err_setup_rx:
3106 igb_free_all_tx_resources(adapter);
3107 err_setup_tx:
3108 igb_reset(adapter);
3109 if (!resuming)
3110 pm_runtime_put(&pdev->dev);
3111
3112 return err;
3113 }
3114
3115 static int igb_open(struct net_device *netdev)
3116 {
3117 return __igb_open(netdev, false);
3118 }
3119
3120 /**
3121 * igb_close - Disables a network interface
3122 * @netdev: network interface device structure
3123 *
3124 * Returns 0, this is not allowed to fail
3125 *
3126 * The close entry point is called when an interface is de-activated
3127 * by the OS. The hardware is still under the driver's control, but
3128 * needs to be disabled. A global MAC reset is issued to stop the
3129 * hardware, and all transmit and receive resources are freed.
3130 **/
3131 static int __igb_close(struct net_device *netdev, bool suspending)
3132 {
3133 struct igb_adapter *adapter = netdev_priv(netdev);
3134 struct pci_dev *pdev = adapter->pdev;
3135
3136 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3137
3138 if (!suspending)
3139 pm_runtime_get_sync(&pdev->dev);
3140
3141 igb_down(adapter);
3142 igb_free_irq(adapter);
3143
3144 igb_free_all_tx_resources(adapter);
3145 igb_free_all_rx_resources(adapter);
3146
3147 if (!suspending)
3148 pm_runtime_put_sync(&pdev->dev);
3149 return 0;
3150 }
3151
3152 static int igb_close(struct net_device *netdev)
3153 {
3154 return __igb_close(netdev, false);
3155 }
3156
3157 /**
3158 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3159 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3160 *
3161 * Return 0 on success, negative on failure
3162 **/
3163 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3164 {
3165 struct device *dev = tx_ring->dev;
3166 int size;
3167
3168 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3169
3170 tx_ring->tx_buffer_info = vzalloc(size);
3171 if (!tx_ring->tx_buffer_info)
3172 goto err;
3173
3174 /* round up to nearest 4K */
3175 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3176 tx_ring->size = ALIGN(tx_ring->size, 4096);
3177
3178 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3179 &tx_ring->dma, GFP_KERNEL);
3180 if (!tx_ring->desc)
3181 goto err;
3182
3183 tx_ring->next_to_use = 0;
3184 tx_ring->next_to_clean = 0;
3185
3186 return 0;
3187
3188 err:
3189 vfree(tx_ring->tx_buffer_info);
3190 tx_ring->tx_buffer_info = NULL;
3191 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3192 return -ENOMEM;
3193 }
3194
3195 /**
3196 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3197 * (Descriptors) for all queues
3198 * @adapter: board private structure
3199 *
3200 * Return 0 on success, negative on failure
3201 **/
3202 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3203 {
3204 struct pci_dev *pdev = adapter->pdev;
3205 int i, err = 0;
3206
3207 for (i = 0; i < adapter->num_tx_queues; i++) {
3208 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3209 if (err) {
3210 dev_err(&pdev->dev,
3211 "Allocation for Tx Queue %u failed\n", i);
3212 for (i--; i >= 0; i--)
3213 igb_free_tx_resources(adapter->tx_ring[i]);
3214 break;
3215 }
3216 }
3217
3218 return err;
3219 }
3220
3221 /**
3222 * igb_setup_tctl - configure the transmit control registers
3223 * @adapter: Board private structure
3224 **/
3225 void igb_setup_tctl(struct igb_adapter *adapter)
3226 {
3227 struct e1000_hw *hw = &adapter->hw;
3228 u32 tctl;
3229
3230 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3231 wr32(E1000_TXDCTL(0), 0);
3232
3233 /* Program the Transmit Control Register */
3234 tctl = rd32(E1000_TCTL);
3235 tctl &= ~E1000_TCTL_CT;
3236 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3237 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3238
3239 igb_config_collision_dist(hw);
3240
3241 /* Enable transmits */
3242 tctl |= E1000_TCTL_EN;
3243
3244 wr32(E1000_TCTL, tctl);
3245 }
3246
3247 /**
3248 * igb_configure_tx_ring - Configure transmit ring after Reset
3249 * @adapter: board private structure
3250 * @ring: tx ring to configure
3251 *
3252 * Configure a transmit ring after a reset.
3253 **/
3254 void igb_configure_tx_ring(struct igb_adapter *adapter,
3255 struct igb_ring *ring)
3256 {
3257 struct e1000_hw *hw = &adapter->hw;
3258 u32 txdctl = 0;
3259 u64 tdba = ring->dma;
3260 int reg_idx = ring->reg_idx;
3261
3262 /* disable the queue */
3263 wr32(E1000_TXDCTL(reg_idx), 0);
3264 wrfl();
3265 mdelay(10);
3266
3267 wr32(E1000_TDLEN(reg_idx),
3268 ring->count * sizeof(union e1000_adv_tx_desc));
3269 wr32(E1000_TDBAL(reg_idx),
3270 tdba & 0x00000000ffffffffULL);
3271 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3272
3273 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3274 wr32(E1000_TDH(reg_idx), 0);
3275 writel(0, ring->tail);
3276
3277 txdctl |= IGB_TX_PTHRESH;
3278 txdctl |= IGB_TX_HTHRESH << 8;
3279 txdctl |= IGB_TX_WTHRESH << 16;
3280
3281 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3282 wr32(E1000_TXDCTL(reg_idx), txdctl);
3283 }
3284
3285 /**
3286 * igb_configure_tx - Configure transmit Unit after Reset
3287 * @adapter: board private structure
3288 *
3289 * Configure the Tx unit of the MAC after a reset.
3290 **/
3291 static void igb_configure_tx(struct igb_adapter *adapter)
3292 {
3293 int i;
3294
3295 for (i = 0; i < adapter->num_tx_queues; i++)
3296 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3297 }
3298
3299 /**
3300 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3301 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3302 *
3303 * Returns 0 on success, negative on failure
3304 **/
3305 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3306 {
3307 struct device *dev = rx_ring->dev;
3308 int size;
3309
3310 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3311
3312 rx_ring->rx_buffer_info = vzalloc(size);
3313 if (!rx_ring->rx_buffer_info)
3314 goto err;
3315
3316 /* Round up to nearest 4K */
3317 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3318 rx_ring->size = ALIGN(rx_ring->size, 4096);
3319
3320 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3321 &rx_ring->dma, GFP_KERNEL);
3322 if (!rx_ring->desc)
3323 goto err;
3324
3325 rx_ring->next_to_alloc = 0;
3326 rx_ring->next_to_clean = 0;
3327 rx_ring->next_to_use = 0;
3328
3329 return 0;
3330
3331 err:
3332 vfree(rx_ring->rx_buffer_info);
3333 rx_ring->rx_buffer_info = NULL;
3334 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3335 return -ENOMEM;
3336 }
3337
3338 /**
3339 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3340 * (Descriptors) for all queues
3341 * @adapter: board private structure
3342 *
3343 * Return 0 on success, negative on failure
3344 **/
3345 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3346 {
3347 struct pci_dev *pdev = adapter->pdev;
3348 int i, err = 0;
3349
3350 for (i = 0; i < adapter->num_rx_queues; i++) {
3351 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3352 if (err) {
3353 dev_err(&pdev->dev,
3354 "Allocation for Rx Queue %u failed\n", i);
3355 for (i--; i >= 0; i--)
3356 igb_free_rx_resources(adapter->rx_ring[i]);
3357 break;
3358 }
3359 }
3360
3361 return err;
3362 }
3363
3364 /**
3365 * igb_setup_mrqc - configure the multiple receive queue control registers
3366 * @adapter: Board private structure
3367 **/
3368 static void igb_setup_mrqc(struct igb_adapter *adapter)
3369 {
3370 struct e1000_hw *hw = &adapter->hw;
3371 u32 mrqc, rxcsum;
3372 u32 j, num_rx_queues;
3373 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3374 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3375 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3376 0xFA01ACBE };
3377
3378 /* Fill out hash function seeds */
3379 for (j = 0; j < 10; j++)
3380 wr32(E1000_RSSRK(j), rsskey[j]);
3381
3382 num_rx_queues = adapter->rss_queues;
3383
3384 switch (hw->mac.type) {
3385 case e1000_82576:
3386 /* 82576 supports 2 RSS queues for SR-IOV */
3387 if (adapter->vfs_allocated_count)
3388 num_rx_queues = 2;
3389 break;
3390 default:
3391 break;
3392 }
3393
3394 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3395 for (j = 0; j < IGB_RETA_SIZE; j++)
3396 adapter->rss_indir_tbl[j] =
3397 (j * num_rx_queues) / IGB_RETA_SIZE;
3398 adapter->rss_indir_tbl_init = num_rx_queues;
3399 }
3400 igb_write_rss_indir_tbl(adapter);
3401
3402 /* Disable raw packet checksumming so that RSS hash is placed in
3403 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3404 * offloads as they are enabled by default
3405 */
3406 rxcsum = rd32(E1000_RXCSUM);
3407 rxcsum |= E1000_RXCSUM_PCSD;
3408
3409 if (adapter->hw.mac.type >= e1000_82576)
3410 /* Enable Receive Checksum Offload for SCTP */
3411 rxcsum |= E1000_RXCSUM_CRCOFL;
3412
3413 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3414 wr32(E1000_RXCSUM, rxcsum);
3415
3416 /* Generate RSS hash based on packet types, TCP/UDP
3417 * port numbers and/or IPv4/v6 src and dst addresses
3418 */
3419 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3420 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3421 E1000_MRQC_RSS_FIELD_IPV6 |
3422 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3424
3425 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3426 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3427 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3428 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3429
3430 /* If VMDq is enabled then we set the appropriate mode for that, else
3431 * we default to RSS so that an RSS hash is calculated per packet even
3432 * if we are only using one queue
3433 */
3434 if (adapter->vfs_allocated_count) {
3435 if (hw->mac.type > e1000_82575) {
3436 /* Set the default pool for the PF's first queue */
3437 u32 vtctl = rd32(E1000_VT_CTL);
3438
3439 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3440 E1000_VT_CTL_DISABLE_DEF_POOL);
3441 vtctl |= adapter->vfs_allocated_count <<
3442 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3443 wr32(E1000_VT_CTL, vtctl);
3444 }
3445 if (adapter->rss_queues > 1)
3446 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3447 else
3448 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3449 } else {
3450 if (hw->mac.type != e1000_i211)
3451 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3452 }
3453 igb_vmm_control(adapter);
3454
3455 wr32(E1000_MRQC, mrqc);
3456 }
3457
3458 /**
3459 * igb_setup_rctl - configure the receive control registers
3460 * @adapter: Board private structure
3461 **/
3462 void igb_setup_rctl(struct igb_adapter *adapter)
3463 {
3464 struct e1000_hw *hw = &adapter->hw;
3465 u32 rctl;
3466
3467 rctl = rd32(E1000_RCTL);
3468
3469 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3470 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3471
3472 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3473 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3474
3475 /* enable stripping of CRC. It's unlikely this will break BMC
3476 * redirection as it did with e1000. Newer features require
3477 * that the HW strips the CRC.
3478 */
3479 rctl |= E1000_RCTL_SECRC;
3480
3481 /* disable store bad packets and clear size bits. */
3482 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3483
3484 /* enable LPE to prevent packets larger than max_frame_size */
3485 rctl |= E1000_RCTL_LPE;
3486
3487 /* disable queue 0 to prevent tail write w/o re-config */
3488 wr32(E1000_RXDCTL(0), 0);
3489
3490 /* Attention!!! For SR-IOV PF driver operations you must enable
3491 * queue drop for all VF and PF queues to prevent head of line blocking
3492 * if an un-trusted VF does not provide descriptors to hardware.
3493 */
3494 if (adapter->vfs_allocated_count) {
3495 /* set all queue drop enable bits */
3496 wr32(E1000_QDE, ALL_QUEUES);
3497 }
3498
3499 /* This is useful for sniffing bad packets. */
3500 if (adapter->netdev->features & NETIF_F_RXALL) {
3501 /* UPE and MPE will be handled by normal PROMISC logic
3502 * in e1000e_set_rx_mode
3503 */
3504 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3505 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3506 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3507
3508 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3509 E1000_RCTL_DPF | /* Allow filtered pause */
3510 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3511 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3512 * and that breaks VLANs.
3513 */
3514 }
3515
3516 wr32(E1000_RCTL, rctl);
3517 }
3518
3519 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3520 int vfn)
3521 {
3522 struct e1000_hw *hw = &adapter->hw;
3523 u32 vmolr;
3524
3525 /* if it isn't the PF check to see if VFs are enabled and
3526 * increase the size to support vlan tags
3527 */
3528 if (vfn < adapter->vfs_allocated_count &&
3529 adapter->vf_data[vfn].vlans_enabled)
3530 size += VLAN_TAG_SIZE;
3531
3532 vmolr = rd32(E1000_VMOLR(vfn));
3533 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3534 vmolr |= size | E1000_VMOLR_LPE;
3535 wr32(E1000_VMOLR(vfn), vmolr);
3536
3537 return 0;
3538 }
3539
3540 /**
3541 * igb_rlpml_set - set maximum receive packet size
3542 * @adapter: board private structure
3543 *
3544 * Configure maximum receivable packet size.
3545 **/
3546 static void igb_rlpml_set(struct igb_adapter *adapter)
3547 {
3548 u32 max_frame_size = adapter->max_frame_size;
3549 struct e1000_hw *hw = &adapter->hw;
3550 u16 pf_id = adapter->vfs_allocated_count;
3551
3552 if (pf_id) {
3553 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3554 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3555 * to our max jumbo frame size, in case we need to enable
3556 * jumbo frames on one of the rings later.
3557 * This will not pass over-length frames into the default
3558 * queue because it's gated by the VMOLR.RLPML.
3559 */
3560 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3561 }
3562
3563 wr32(E1000_RLPML, max_frame_size);
3564 }
3565
3566 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3567 int vfn, bool aupe)
3568 {
3569 struct e1000_hw *hw = &adapter->hw;
3570 u32 vmolr;
3571
3572 /* This register exists only on 82576 and newer so if we are older then
3573 * we should exit and do nothing
3574 */
3575 if (hw->mac.type < e1000_82576)
3576 return;
3577
3578 vmolr = rd32(E1000_VMOLR(vfn));
3579 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3580 if (hw->mac.type == e1000_i350) {
3581 u32 dvmolr;
3582
3583 dvmolr = rd32(E1000_DVMOLR(vfn));
3584 dvmolr |= E1000_DVMOLR_STRVLAN;
3585 wr32(E1000_DVMOLR(vfn), dvmolr);
3586 }
3587 if (aupe)
3588 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3589 else
3590 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3591
3592 /* clear all bits that might not be set */
3593 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3594
3595 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3596 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3597 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3598 * multicast packets
3599 */
3600 if (vfn <= adapter->vfs_allocated_count)
3601 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3602
3603 wr32(E1000_VMOLR(vfn), vmolr);
3604 }
3605
3606 /**
3607 * igb_configure_rx_ring - Configure a receive ring after Reset
3608 * @adapter: board private structure
3609 * @ring: receive ring to be configured
3610 *
3611 * Configure the Rx unit of the MAC after a reset.
3612 **/
3613 void igb_configure_rx_ring(struct igb_adapter *adapter,
3614 struct igb_ring *ring)
3615 {
3616 struct e1000_hw *hw = &adapter->hw;
3617 u64 rdba = ring->dma;
3618 int reg_idx = ring->reg_idx;
3619 u32 srrctl = 0, rxdctl = 0;
3620
3621 /* disable the queue */
3622 wr32(E1000_RXDCTL(reg_idx), 0);
3623
3624 /* Set DMA base address registers */
3625 wr32(E1000_RDBAL(reg_idx),
3626 rdba & 0x00000000ffffffffULL);
3627 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3628 wr32(E1000_RDLEN(reg_idx),
3629 ring->count * sizeof(union e1000_adv_rx_desc));
3630
3631 /* initialize head and tail */
3632 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3633 wr32(E1000_RDH(reg_idx), 0);
3634 writel(0, ring->tail);
3635
3636 /* set descriptor configuration */
3637 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3638 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3639 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3640 if (hw->mac.type >= e1000_82580)
3641 srrctl |= E1000_SRRCTL_TIMESTAMP;
3642 /* Only set Drop Enable if we are supporting multiple queues */
3643 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3644 srrctl |= E1000_SRRCTL_DROP_EN;
3645
3646 wr32(E1000_SRRCTL(reg_idx), srrctl);
3647
3648 /* set filtering for VMDQ pools */
3649 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3650
3651 rxdctl |= IGB_RX_PTHRESH;
3652 rxdctl |= IGB_RX_HTHRESH << 8;
3653 rxdctl |= IGB_RX_WTHRESH << 16;
3654
3655 /* enable receive descriptor fetching */
3656 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3657 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3658 }
3659
3660 /**
3661 * igb_configure_rx - Configure receive Unit after Reset
3662 * @adapter: board private structure
3663 *
3664 * Configure the Rx unit of the MAC after a reset.
3665 **/
3666 static void igb_configure_rx(struct igb_adapter *adapter)
3667 {
3668 int i;
3669
3670 /* set UTA to appropriate mode */
3671 igb_set_uta(adapter);
3672
3673 /* set the correct pool for the PF default MAC address in entry 0 */
3674 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3675 adapter->vfs_allocated_count);
3676
3677 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3678 * the Base and Length of the Rx Descriptor Ring
3679 */
3680 for (i = 0; i < adapter->num_rx_queues; i++)
3681 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3682 }
3683
3684 /**
3685 * igb_free_tx_resources - Free Tx Resources per Queue
3686 * @tx_ring: Tx descriptor ring for a specific queue
3687 *
3688 * Free all transmit software resources
3689 **/
3690 void igb_free_tx_resources(struct igb_ring *tx_ring)
3691 {
3692 igb_clean_tx_ring(tx_ring);
3693
3694 vfree(tx_ring->tx_buffer_info);
3695 tx_ring->tx_buffer_info = NULL;
3696
3697 /* if not set, then don't free */
3698 if (!tx_ring->desc)
3699 return;
3700
3701 dma_free_coherent(tx_ring->dev, tx_ring->size,
3702 tx_ring->desc, tx_ring->dma);
3703
3704 tx_ring->desc = NULL;
3705 }
3706
3707 /**
3708 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3709 * @adapter: board private structure
3710 *
3711 * Free all transmit software resources
3712 **/
3713 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3714 {
3715 int i;
3716
3717 for (i = 0; i < adapter->num_tx_queues; i++)
3718 igb_free_tx_resources(adapter->tx_ring[i]);
3719 }
3720
3721 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3722 struct igb_tx_buffer *tx_buffer)
3723 {
3724 if (tx_buffer->skb) {
3725 dev_kfree_skb_any(tx_buffer->skb);
3726 if (dma_unmap_len(tx_buffer, len))
3727 dma_unmap_single(ring->dev,
3728 dma_unmap_addr(tx_buffer, dma),
3729 dma_unmap_len(tx_buffer, len),
3730 DMA_TO_DEVICE);
3731 } else if (dma_unmap_len(tx_buffer, len)) {
3732 dma_unmap_page(ring->dev,
3733 dma_unmap_addr(tx_buffer, dma),
3734 dma_unmap_len(tx_buffer, len),
3735 DMA_TO_DEVICE);
3736 }
3737 tx_buffer->next_to_watch = NULL;
3738 tx_buffer->skb = NULL;
3739 dma_unmap_len_set(tx_buffer, len, 0);
3740 /* buffer_info must be completely set up in the transmit path */
3741 }
3742
3743 /**
3744 * igb_clean_tx_ring - Free Tx Buffers
3745 * @tx_ring: ring to be cleaned
3746 **/
3747 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3748 {
3749 struct igb_tx_buffer *buffer_info;
3750 unsigned long size;
3751 u16 i;
3752
3753 if (!tx_ring->tx_buffer_info)
3754 return;
3755 /* Free all the Tx ring sk_buffs */
3756
3757 for (i = 0; i < tx_ring->count; i++) {
3758 buffer_info = &tx_ring->tx_buffer_info[i];
3759 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3760 }
3761
3762 netdev_tx_reset_queue(txring_txq(tx_ring));
3763
3764 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3765 memset(tx_ring->tx_buffer_info, 0, size);
3766
3767 /* Zero out the descriptor ring */
3768 memset(tx_ring->desc, 0, tx_ring->size);
3769
3770 tx_ring->next_to_use = 0;
3771 tx_ring->next_to_clean = 0;
3772 }
3773
3774 /**
3775 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3776 * @adapter: board private structure
3777 **/
3778 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3779 {
3780 int i;
3781
3782 for (i = 0; i < adapter->num_tx_queues; i++)
3783 igb_clean_tx_ring(adapter->tx_ring[i]);
3784 }
3785
3786 /**
3787 * igb_free_rx_resources - Free Rx Resources
3788 * @rx_ring: ring to clean the resources from
3789 *
3790 * Free all receive software resources
3791 **/
3792 void igb_free_rx_resources(struct igb_ring *rx_ring)
3793 {
3794 igb_clean_rx_ring(rx_ring);
3795
3796 vfree(rx_ring->rx_buffer_info);
3797 rx_ring->rx_buffer_info = NULL;
3798
3799 /* if not set, then don't free */
3800 if (!rx_ring->desc)
3801 return;
3802
3803 dma_free_coherent(rx_ring->dev, rx_ring->size,
3804 rx_ring->desc, rx_ring->dma);
3805
3806 rx_ring->desc = NULL;
3807 }
3808
3809 /**
3810 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3811 * @adapter: board private structure
3812 *
3813 * Free all receive software resources
3814 **/
3815 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3816 {
3817 int i;
3818
3819 for (i = 0; i < adapter->num_rx_queues; i++)
3820 igb_free_rx_resources(adapter->rx_ring[i]);
3821 }
3822
3823 /**
3824 * igb_clean_rx_ring - Free Rx Buffers per Queue
3825 * @rx_ring: ring to free buffers from
3826 **/
3827 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3828 {
3829 unsigned long size;
3830 u16 i;
3831
3832 if (rx_ring->skb)
3833 dev_kfree_skb(rx_ring->skb);
3834 rx_ring->skb = NULL;
3835
3836 if (!rx_ring->rx_buffer_info)
3837 return;
3838
3839 /* Free all the Rx ring sk_buffs */
3840 for (i = 0; i < rx_ring->count; i++) {
3841 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3842
3843 if (!buffer_info->page)
3844 continue;
3845
3846 dma_unmap_page(rx_ring->dev,
3847 buffer_info->dma,
3848 PAGE_SIZE,
3849 DMA_FROM_DEVICE);
3850 __free_page(buffer_info->page);
3851
3852 buffer_info->page = NULL;
3853 }
3854
3855 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3856 memset(rx_ring->rx_buffer_info, 0, size);
3857
3858 /* Zero out the descriptor ring */
3859 memset(rx_ring->desc, 0, rx_ring->size);
3860
3861 rx_ring->next_to_alloc = 0;
3862 rx_ring->next_to_clean = 0;
3863 rx_ring->next_to_use = 0;
3864 }
3865
3866 /**
3867 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3868 * @adapter: board private structure
3869 **/
3870 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3871 {
3872 int i;
3873
3874 for (i = 0; i < adapter->num_rx_queues; i++)
3875 igb_clean_rx_ring(adapter->rx_ring[i]);
3876 }
3877
3878 /**
3879 * igb_set_mac - Change the Ethernet Address of the NIC
3880 * @netdev: network interface device structure
3881 * @p: pointer to an address structure
3882 *
3883 * Returns 0 on success, negative on failure
3884 **/
3885 static int igb_set_mac(struct net_device *netdev, void *p)
3886 {
3887 struct igb_adapter *adapter = netdev_priv(netdev);
3888 struct e1000_hw *hw = &adapter->hw;
3889 struct sockaddr *addr = p;
3890
3891 if (!is_valid_ether_addr(addr->sa_data))
3892 return -EADDRNOTAVAIL;
3893
3894 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3895 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3896
3897 /* set the correct pool for the new PF MAC address in entry 0 */
3898 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3899 adapter->vfs_allocated_count);
3900
3901 return 0;
3902 }
3903
3904 /**
3905 * igb_write_mc_addr_list - write multicast addresses to MTA
3906 * @netdev: network interface device structure
3907 *
3908 * Writes multicast address list to the MTA hash table.
3909 * Returns: -ENOMEM on failure
3910 * 0 on no addresses written
3911 * X on writing X addresses to MTA
3912 **/
3913 static int igb_write_mc_addr_list(struct net_device *netdev)
3914 {
3915 struct igb_adapter *adapter = netdev_priv(netdev);
3916 struct e1000_hw *hw = &adapter->hw;
3917 struct netdev_hw_addr *ha;
3918 u8 *mta_list;
3919 int i;
3920
3921 if (netdev_mc_empty(netdev)) {
3922 /* nothing to program, so clear mc list */
3923 igb_update_mc_addr_list(hw, NULL, 0);
3924 igb_restore_vf_multicasts(adapter);
3925 return 0;
3926 }
3927
3928 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3929 if (!mta_list)
3930 return -ENOMEM;
3931
3932 /* The shared function expects a packed array of only addresses. */
3933 i = 0;
3934 netdev_for_each_mc_addr(ha, netdev)
3935 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3936
3937 igb_update_mc_addr_list(hw, mta_list, i);
3938 kfree(mta_list);
3939
3940 return netdev_mc_count(netdev);
3941 }
3942
3943 /**
3944 * igb_write_uc_addr_list - write unicast addresses to RAR table
3945 * @netdev: network interface device structure
3946 *
3947 * Writes unicast address list to the RAR table.
3948 * Returns: -ENOMEM on failure/insufficient address space
3949 * 0 on no addresses written
3950 * X on writing X addresses to the RAR table
3951 **/
3952 static int igb_write_uc_addr_list(struct net_device *netdev)
3953 {
3954 struct igb_adapter *adapter = netdev_priv(netdev);
3955 struct e1000_hw *hw = &adapter->hw;
3956 unsigned int vfn = adapter->vfs_allocated_count;
3957 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3958 int count = 0;
3959
3960 /* return ENOMEM indicating insufficient memory for addresses */
3961 if (netdev_uc_count(netdev) > rar_entries)
3962 return -ENOMEM;
3963
3964 if (!netdev_uc_empty(netdev) && rar_entries) {
3965 struct netdev_hw_addr *ha;
3966
3967 netdev_for_each_uc_addr(ha, netdev) {
3968 if (!rar_entries)
3969 break;
3970 igb_rar_set_qsel(adapter, ha->addr,
3971 rar_entries--,
3972 vfn);
3973 count++;
3974 }
3975 }
3976 /* write the addresses in reverse order to avoid write combining */
3977 for (; rar_entries > 0 ; rar_entries--) {
3978 wr32(E1000_RAH(rar_entries), 0);
3979 wr32(E1000_RAL(rar_entries), 0);
3980 }
3981 wrfl();
3982
3983 return count;
3984 }
3985
3986 /**
3987 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3988 * @netdev: network interface device structure
3989 *
3990 * The set_rx_mode entry point is called whenever the unicast or multicast
3991 * address lists or the network interface flags are updated. This routine is
3992 * responsible for configuring the hardware for proper unicast, multicast,
3993 * promiscuous mode, and all-multi behavior.
3994 **/
3995 static void igb_set_rx_mode(struct net_device *netdev)
3996 {
3997 struct igb_adapter *adapter = netdev_priv(netdev);
3998 struct e1000_hw *hw = &adapter->hw;
3999 unsigned int vfn = adapter->vfs_allocated_count;
4000 u32 rctl, vmolr = 0;
4001 int count;
4002
4003 /* Check for Promiscuous and All Multicast modes */
4004 rctl = rd32(E1000_RCTL);
4005
4006 /* clear the effected bits */
4007 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4008
4009 if (netdev->flags & IFF_PROMISC) {
4010 /* retain VLAN HW filtering if in VT mode */
4011 if (adapter->vfs_allocated_count)
4012 rctl |= E1000_RCTL_VFE;
4013 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4014 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4015 } else {
4016 if (netdev->flags & IFF_ALLMULTI) {
4017 rctl |= E1000_RCTL_MPE;
4018 vmolr |= E1000_VMOLR_MPME;
4019 } else {
4020 /* Write addresses to the MTA, if the attempt fails
4021 * then we should just turn on promiscuous mode so
4022 * that we can at least receive multicast traffic
4023 */
4024 count = igb_write_mc_addr_list(netdev);
4025 if (count < 0) {
4026 rctl |= E1000_RCTL_MPE;
4027 vmolr |= E1000_VMOLR_MPME;
4028 } else if (count) {
4029 vmolr |= E1000_VMOLR_ROMPE;
4030 }
4031 }
4032 /* Write addresses to available RAR registers, if there is not
4033 * sufficient space to store all the addresses then enable
4034 * unicast promiscuous mode
4035 */
4036 count = igb_write_uc_addr_list(netdev);
4037 if (count < 0) {
4038 rctl |= E1000_RCTL_UPE;
4039 vmolr |= E1000_VMOLR_ROPE;
4040 }
4041 rctl |= E1000_RCTL_VFE;
4042 }
4043 wr32(E1000_RCTL, rctl);
4044
4045 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4046 * the VMOLR to enable the appropriate modes. Without this workaround
4047 * we will have issues with VLAN tag stripping not being done for frames
4048 * that are only arriving because we are the default pool
4049 */
4050 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4051 return;
4052
4053 vmolr |= rd32(E1000_VMOLR(vfn)) &
4054 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4055 wr32(E1000_VMOLR(vfn), vmolr);
4056 igb_restore_vf_multicasts(adapter);
4057 }
4058
4059 static void igb_check_wvbr(struct igb_adapter *adapter)
4060 {
4061 struct e1000_hw *hw = &adapter->hw;
4062 u32 wvbr = 0;
4063
4064 switch (hw->mac.type) {
4065 case e1000_82576:
4066 case e1000_i350:
4067 wvbr = rd32(E1000_WVBR);
4068 if (!wvbr)
4069 return;
4070 break;
4071 default:
4072 break;
4073 }
4074
4075 adapter->wvbr |= wvbr;
4076 }
4077
4078 #define IGB_STAGGERED_QUEUE_OFFSET 8
4079
4080 static void igb_spoof_check(struct igb_adapter *adapter)
4081 {
4082 int j;
4083
4084 if (!adapter->wvbr)
4085 return;
4086
4087 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4088 if (adapter->wvbr & (1 << j) ||
4089 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4090 dev_warn(&adapter->pdev->dev,
4091 "Spoof event(s) detected on VF %d\n", j);
4092 adapter->wvbr &=
4093 ~((1 << j) |
4094 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4095 }
4096 }
4097 }
4098
4099 /* Need to wait a few seconds after link up to get diagnostic information from
4100 * the phy
4101 */
4102 static void igb_update_phy_info(unsigned long data)
4103 {
4104 struct igb_adapter *adapter = (struct igb_adapter *) data;
4105 igb_get_phy_info(&adapter->hw);
4106 }
4107
4108 /**
4109 * igb_has_link - check shared code for link and determine up/down
4110 * @adapter: pointer to driver private info
4111 **/
4112 bool igb_has_link(struct igb_adapter *adapter)
4113 {
4114 struct e1000_hw *hw = &adapter->hw;
4115 bool link_active = false;
4116
4117 /* get_link_status is set on LSC (link status) interrupt or
4118 * rx sequence error interrupt. get_link_status will stay
4119 * false until the e1000_check_for_link establishes link
4120 * for copper adapters ONLY
4121 */
4122 switch (hw->phy.media_type) {
4123 case e1000_media_type_copper:
4124 if (!hw->mac.get_link_status)
4125 return true;
4126 case e1000_media_type_internal_serdes:
4127 hw->mac.ops.check_for_link(hw);
4128 link_active = !hw->mac.get_link_status;
4129 break;
4130 default:
4131 case e1000_media_type_unknown:
4132 break;
4133 }
4134
4135 if (((hw->mac.type == e1000_i210) ||
4136 (hw->mac.type == e1000_i211)) &&
4137 (hw->phy.id == I210_I_PHY_ID)) {
4138 if (!netif_carrier_ok(adapter->netdev)) {
4139 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4140 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4141 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4142 adapter->link_check_timeout = jiffies;
4143 }
4144 }
4145
4146 return link_active;
4147 }
4148
4149 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4150 {
4151 bool ret = false;
4152 u32 ctrl_ext, thstat;
4153
4154 /* check for thermal sensor event on i350 copper only */
4155 if (hw->mac.type == e1000_i350) {
4156 thstat = rd32(E1000_THSTAT);
4157 ctrl_ext = rd32(E1000_CTRL_EXT);
4158
4159 if ((hw->phy.media_type == e1000_media_type_copper) &&
4160 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4161 ret = !!(thstat & event);
4162 }
4163
4164 return ret;
4165 }
4166
4167 /**
4168 * igb_check_lvmmc - check for malformed packets received
4169 * and indicated in LVMMC register
4170 * @adapter: pointer to adapter
4171 **/
4172 static void igb_check_lvmmc(struct igb_adapter *adapter)
4173 {
4174 struct e1000_hw *hw = &adapter->hw;
4175 u32 lvmmc;
4176
4177 lvmmc = rd32(E1000_LVMMC);
4178 if (lvmmc) {
4179 if (unlikely(net_ratelimit())) {
4180 netdev_warn(adapter->netdev,
4181 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4182 lvmmc);
4183 }
4184 }
4185 }
4186
4187 /**
4188 * igb_watchdog - Timer Call-back
4189 * @data: pointer to adapter cast into an unsigned long
4190 **/
4191 static void igb_watchdog(unsigned long data)
4192 {
4193 struct igb_adapter *adapter = (struct igb_adapter *)data;
4194 /* Do the rest outside of interrupt context */
4195 schedule_work(&adapter->watchdog_task);
4196 }
4197
4198 static void igb_watchdog_task(struct work_struct *work)
4199 {
4200 struct igb_adapter *adapter = container_of(work,
4201 struct igb_adapter,
4202 watchdog_task);
4203 struct e1000_hw *hw = &adapter->hw;
4204 struct e1000_phy_info *phy = &hw->phy;
4205 struct net_device *netdev = adapter->netdev;
4206 u32 link;
4207 int i;
4208 u32 connsw;
4209
4210 link = igb_has_link(adapter);
4211
4212 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4213 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4214 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4215 else
4216 link = false;
4217 }
4218
4219 /* Force link down if we have fiber to swap to */
4220 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4221 if (hw->phy.media_type == e1000_media_type_copper) {
4222 connsw = rd32(E1000_CONNSW);
4223 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4224 link = 0;
4225 }
4226 }
4227 if (link) {
4228 /* Perform a reset if the media type changed. */
4229 if (hw->dev_spec._82575.media_changed) {
4230 hw->dev_spec._82575.media_changed = false;
4231 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4232 igb_reset(adapter);
4233 }
4234 /* Cancel scheduled suspend requests. */
4235 pm_runtime_resume(netdev->dev.parent);
4236
4237 if (!netif_carrier_ok(netdev)) {
4238 u32 ctrl;
4239
4240 hw->mac.ops.get_speed_and_duplex(hw,
4241 &adapter->link_speed,
4242 &adapter->link_duplex);
4243
4244 ctrl = rd32(E1000_CTRL);
4245 /* Links status message must follow this format */
4246 netdev_info(netdev,
4247 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4248 netdev->name,
4249 adapter->link_speed,
4250 adapter->link_duplex == FULL_DUPLEX ?
4251 "Full" : "Half",
4252 (ctrl & E1000_CTRL_TFCE) &&
4253 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4254 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4255 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4256
4257 /* disable EEE if enabled */
4258 if ((adapter->flags & IGB_FLAG_EEE) &&
4259 (adapter->link_duplex == HALF_DUPLEX)) {
4260 dev_info(&adapter->pdev->dev,
4261 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4262 adapter->hw.dev_spec._82575.eee_disable = true;
4263 adapter->flags &= ~IGB_FLAG_EEE;
4264 }
4265
4266 /* check if SmartSpeed worked */
4267 igb_check_downshift(hw);
4268 if (phy->speed_downgraded)
4269 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4270
4271 /* check for thermal sensor event */
4272 if (igb_thermal_sensor_event(hw,
4273 E1000_THSTAT_LINK_THROTTLE))
4274 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4275
4276 /* adjust timeout factor according to speed/duplex */
4277 adapter->tx_timeout_factor = 1;
4278 switch (adapter->link_speed) {
4279 case SPEED_10:
4280 adapter->tx_timeout_factor = 14;
4281 break;
4282 case SPEED_100:
4283 /* maybe add some timeout factor ? */
4284 break;
4285 }
4286
4287 netif_carrier_on(netdev);
4288
4289 igb_ping_all_vfs(adapter);
4290 igb_check_vf_rate_limit(adapter);
4291
4292 /* link state has changed, schedule phy info update */
4293 if (!test_bit(__IGB_DOWN, &adapter->state))
4294 mod_timer(&adapter->phy_info_timer,
4295 round_jiffies(jiffies + 2 * HZ));
4296 }
4297 } else {
4298 if (netif_carrier_ok(netdev)) {
4299 adapter->link_speed = 0;
4300 adapter->link_duplex = 0;
4301
4302 /* check for thermal sensor event */
4303 if (igb_thermal_sensor_event(hw,
4304 E1000_THSTAT_PWR_DOWN)) {
4305 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4306 }
4307
4308 /* Links status message must follow this format */
4309 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4310 netdev->name);
4311 netif_carrier_off(netdev);
4312
4313 igb_ping_all_vfs(adapter);
4314
4315 /* link state has changed, schedule phy info update */
4316 if (!test_bit(__IGB_DOWN, &adapter->state))
4317 mod_timer(&adapter->phy_info_timer,
4318 round_jiffies(jiffies + 2 * HZ));
4319
4320 /* link is down, time to check for alternate media */
4321 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4322 igb_check_swap_media(adapter);
4323 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4324 schedule_work(&adapter->reset_task);
4325 /* return immediately */
4326 return;
4327 }
4328 }
4329 pm_schedule_suspend(netdev->dev.parent,
4330 MSEC_PER_SEC * 5);
4331
4332 /* also check for alternate media here */
4333 } else if (!netif_carrier_ok(netdev) &&
4334 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4335 igb_check_swap_media(adapter);
4336 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4337 schedule_work(&adapter->reset_task);
4338 /* return immediately */
4339 return;
4340 }
4341 }
4342 }
4343
4344 spin_lock(&adapter->stats64_lock);
4345 igb_update_stats(adapter, &adapter->stats64);
4346 spin_unlock(&adapter->stats64_lock);
4347
4348 for (i = 0; i < adapter->num_tx_queues; i++) {
4349 struct igb_ring *tx_ring = adapter->tx_ring[i];
4350 if (!netif_carrier_ok(netdev)) {
4351 /* We've lost link, so the controller stops DMA,
4352 * but we've got queued Tx work that's never going
4353 * to get done, so reset controller to flush Tx.
4354 * (Do the reset outside of interrupt context).
4355 */
4356 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4357 adapter->tx_timeout_count++;
4358 schedule_work(&adapter->reset_task);
4359 /* return immediately since reset is imminent */
4360 return;
4361 }
4362 }
4363
4364 /* Force detection of hung controller every watchdog period */
4365 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4366 }
4367
4368 /* Cause software interrupt to ensure Rx ring is cleaned */
4369 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4370 u32 eics = 0;
4371
4372 for (i = 0; i < adapter->num_q_vectors; i++)
4373 eics |= adapter->q_vector[i]->eims_value;
4374 wr32(E1000_EICS, eics);
4375 } else {
4376 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4377 }
4378
4379 igb_spoof_check(adapter);
4380 igb_ptp_rx_hang(adapter);
4381
4382 /* Check LVMMC register on i350/i354 only */
4383 if ((adapter->hw.mac.type == e1000_i350) ||
4384 (adapter->hw.mac.type == e1000_i354))
4385 igb_check_lvmmc(adapter);
4386
4387 /* Reset the timer */
4388 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4389 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4390 mod_timer(&adapter->watchdog_timer,
4391 round_jiffies(jiffies + HZ));
4392 else
4393 mod_timer(&adapter->watchdog_timer,
4394 round_jiffies(jiffies + 2 * HZ));
4395 }
4396 }
4397
4398 enum latency_range {
4399 lowest_latency = 0,
4400 low_latency = 1,
4401 bulk_latency = 2,
4402 latency_invalid = 255
4403 };
4404
4405 /**
4406 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4407 * @q_vector: pointer to q_vector
4408 *
4409 * Stores a new ITR value based on strictly on packet size. This
4410 * algorithm is less sophisticated than that used in igb_update_itr,
4411 * due to the difficulty of synchronizing statistics across multiple
4412 * receive rings. The divisors and thresholds used by this function
4413 * were determined based on theoretical maximum wire speed and testing
4414 * data, in order to minimize response time while increasing bulk
4415 * throughput.
4416 * This functionality is controlled by ethtool's coalescing settings.
4417 * NOTE: This function is called only when operating in a multiqueue
4418 * receive environment.
4419 **/
4420 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4421 {
4422 int new_val = q_vector->itr_val;
4423 int avg_wire_size = 0;
4424 struct igb_adapter *adapter = q_vector->adapter;
4425 unsigned int packets;
4426
4427 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4428 * ints/sec - ITR timer value of 120 ticks.
4429 */
4430 if (adapter->link_speed != SPEED_1000) {
4431 new_val = IGB_4K_ITR;
4432 goto set_itr_val;
4433 }
4434
4435 packets = q_vector->rx.total_packets;
4436 if (packets)
4437 avg_wire_size = q_vector->rx.total_bytes / packets;
4438
4439 packets = q_vector->tx.total_packets;
4440 if (packets)
4441 avg_wire_size = max_t(u32, avg_wire_size,
4442 q_vector->tx.total_bytes / packets);
4443
4444 /* if avg_wire_size isn't set no work was done */
4445 if (!avg_wire_size)
4446 goto clear_counts;
4447
4448 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4449 avg_wire_size += 24;
4450
4451 /* Don't starve jumbo frames */
4452 avg_wire_size = min(avg_wire_size, 3000);
4453
4454 /* Give a little boost to mid-size frames */
4455 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4456 new_val = avg_wire_size / 3;
4457 else
4458 new_val = avg_wire_size / 2;
4459
4460 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4461 if (new_val < IGB_20K_ITR &&
4462 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4463 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4464 new_val = IGB_20K_ITR;
4465
4466 set_itr_val:
4467 if (new_val != q_vector->itr_val) {
4468 q_vector->itr_val = new_val;
4469 q_vector->set_itr = 1;
4470 }
4471 clear_counts:
4472 q_vector->rx.total_bytes = 0;
4473 q_vector->rx.total_packets = 0;
4474 q_vector->tx.total_bytes = 0;
4475 q_vector->tx.total_packets = 0;
4476 }
4477
4478 /**
4479 * igb_update_itr - update the dynamic ITR value based on statistics
4480 * @q_vector: pointer to q_vector
4481 * @ring_container: ring info to update the itr for
4482 *
4483 * Stores a new ITR value based on packets and byte
4484 * counts during the last interrupt. The advantage of per interrupt
4485 * computation is faster updates and more accurate ITR for the current
4486 * traffic pattern. Constants in this function were computed
4487 * based on theoretical maximum wire speed and thresholds were set based
4488 * on testing data as well as attempting to minimize response time
4489 * while increasing bulk throughput.
4490 * This functionality is controlled by ethtool's coalescing settings.
4491 * NOTE: These calculations are only valid when operating in a single-
4492 * queue environment.
4493 **/
4494 static void igb_update_itr(struct igb_q_vector *q_vector,
4495 struct igb_ring_container *ring_container)
4496 {
4497 unsigned int packets = ring_container->total_packets;
4498 unsigned int bytes = ring_container->total_bytes;
4499 u8 itrval = ring_container->itr;
4500
4501 /* no packets, exit with status unchanged */
4502 if (packets == 0)
4503 return;
4504
4505 switch (itrval) {
4506 case lowest_latency:
4507 /* handle TSO and jumbo frames */
4508 if (bytes/packets > 8000)
4509 itrval = bulk_latency;
4510 else if ((packets < 5) && (bytes > 512))
4511 itrval = low_latency;
4512 break;
4513 case low_latency: /* 50 usec aka 20000 ints/s */
4514 if (bytes > 10000) {
4515 /* this if handles the TSO accounting */
4516 if (bytes/packets > 8000)
4517 itrval = bulk_latency;
4518 else if ((packets < 10) || ((bytes/packets) > 1200))
4519 itrval = bulk_latency;
4520 else if ((packets > 35))
4521 itrval = lowest_latency;
4522 } else if (bytes/packets > 2000) {
4523 itrval = bulk_latency;
4524 } else if (packets <= 2 && bytes < 512) {
4525 itrval = lowest_latency;
4526 }
4527 break;
4528 case bulk_latency: /* 250 usec aka 4000 ints/s */
4529 if (bytes > 25000) {
4530 if (packets > 35)
4531 itrval = low_latency;
4532 } else if (bytes < 1500) {
4533 itrval = low_latency;
4534 }
4535 break;
4536 }
4537
4538 /* clear work counters since we have the values we need */
4539 ring_container->total_bytes = 0;
4540 ring_container->total_packets = 0;
4541
4542 /* write updated itr to ring container */
4543 ring_container->itr = itrval;
4544 }
4545
4546 static void igb_set_itr(struct igb_q_vector *q_vector)
4547 {
4548 struct igb_adapter *adapter = q_vector->adapter;
4549 u32 new_itr = q_vector->itr_val;
4550 u8 current_itr = 0;
4551
4552 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4553 if (adapter->link_speed != SPEED_1000) {
4554 current_itr = 0;
4555 new_itr = IGB_4K_ITR;
4556 goto set_itr_now;
4557 }
4558
4559 igb_update_itr(q_vector, &q_vector->tx);
4560 igb_update_itr(q_vector, &q_vector->rx);
4561
4562 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4563
4564 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4565 if (current_itr == lowest_latency &&
4566 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4567 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4568 current_itr = low_latency;
4569
4570 switch (current_itr) {
4571 /* counts and packets in update_itr are dependent on these numbers */
4572 case lowest_latency:
4573 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4574 break;
4575 case low_latency:
4576 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4577 break;
4578 case bulk_latency:
4579 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4580 break;
4581 default:
4582 break;
4583 }
4584
4585 set_itr_now:
4586 if (new_itr != q_vector->itr_val) {
4587 /* this attempts to bias the interrupt rate towards Bulk
4588 * by adding intermediate steps when interrupt rate is
4589 * increasing
4590 */
4591 new_itr = new_itr > q_vector->itr_val ?
4592 max((new_itr * q_vector->itr_val) /
4593 (new_itr + (q_vector->itr_val >> 2)),
4594 new_itr) : new_itr;
4595 /* Don't write the value here; it resets the adapter's
4596 * internal timer, and causes us to delay far longer than
4597 * we should between interrupts. Instead, we write the ITR
4598 * value at the beginning of the next interrupt so the timing
4599 * ends up being correct.
4600 */
4601 q_vector->itr_val = new_itr;
4602 q_vector->set_itr = 1;
4603 }
4604 }
4605
4606 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4607 u32 type_tucmd, u32 mss_l4len_idx)
4608 {
4609 struct e1000_adv_tx_context_desc *context_desc;
4610 u16 i = tx_ring->next_to_use;
4611
4612 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4613
4614 i++;
4615 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4616
4617 /* set bits to identify this as an advanced context descriptor */
4618 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4619
4620 /* For 82575, context index must be unique per ring. */
4621 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4622 mss_l4len_idx |= tx_ring->reg_idx << 4;
4623
4624 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4625 context_desc->seqnum_seed = 0;
4626 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4627 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4628 }
4629
4630 static int igb_tso(struct igb_ring *tx_ring,
4631 struct igb_tx_buffer *first,
4632 u8 *hdr_len)
4633 {
4634 struct sk_buff *skb = first->skb;
4635 u32 vlan_macip_lens, type_tucmd;
4636 u32 mss_l4len_idx, l4len;
4637 int err;
4638
4639 if (skb->ip_summed != CHECKSUM_PARTIAL)
4640 return 0;
4641
4642 if (!skb_is_gso(skb))
4643 return 0;
4644
4645 err = skb_cow_head(skb, 0);
4646 if (err < 0)
4647 return err;
4648
4649 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4650 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4651
4652 if (first->protocol == htons(ETH_P_IP)) {
4653 struct iphdr *iph = ip_hdr(skb);
4654 iph->tot_len = 0;
4655 iph->check = 0;
4656 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4657 iph->daddr, 0,
4658 IPPROTO_TCP,
4659 0);
4660 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4661 first->tx_flags |= IGB_TX_FLAGS_TSO |
4662 IGB_TX_FLAGS_CSUM |
4663 IGB_TX_FLAGS_IPV4;
4664 } else if (skb_is_gso_v6(skb)) {
4665 ipv6_hdr(skb)->payload_len = 0;
4666 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4667 &ipv6_hdr(skb)->daddr,
4668 0, IPPROTO_TCP, 0);
4669 first->tx_flags |= IGB_TX_FLAGS_TSO |
4670 IGB_TX_FLAGS_CSUM;
4671 }
4672
4673 /* compute header lengths */
4674 l4len = tcp_hdrlen(skb);
4675 *hdr_len = skb_transport_offset(skb) + l4len;
4676
4677 /* update gso size and bytecount with header size */
4678 first->gso_segs = skb_shinfo(skb)->gso_segs;
4679 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4680
4681 /* MSS L4LEN IDX */
4682 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4683 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4684
4685 /* VLAN MACLEN IPLEN */
4686 vlan_macip_lens = skb_network_header_len(skb);
4687 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4688 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4689
4690 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4691
4692 return 1;
4693 }
4694
4695 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4696 {
4697 struct sk_buff *skb = first->skb;
4698 u32 vlan_macip_lens = 0;
4699 u32 mss_l4len_idx = 0;
4700 u32 type_tucmd = 0;
4701
4702 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4703 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4704 return;
4705 } else {
4706 u8 l4_hdr = 0;
4707
4708 switch (first->protocol) {
4709 case htons(ETH_P_IP):
4710 vlan_macip_lens |= skb_network_header_len(skb);
4711 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4712 l4_hdr = ip_hdr(skb)->protocol;
4713 break;
4714 case htons(ETH_P_IPV6):
4715 vlan_macip_lens |= skb_network_header_len(skb);
4716 l4_hdr = ipv6_hdr(skb)->nexthdr;
4717 break;
4718 default:
4719 if (unlikely(net_ratelimit())) {
4720 dev_warn(tx_ring->dev,
4721 "partial checksum but proto=%x!\n",
4722 first->protocol);
4723 }
4724 break;
4725 }
4726
4727 switch (l4_hdr) {
4728 case IPPROTO_TCP:
4729 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4730 mss_l4len_idx = tcp_hdrlen(skb) <<
4731 E1000_ADVTXD_L4LEN_SHIFT;
4732 break;
4733 case IPPROTO_SCTP:
4734 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4735 mss_l4len_idx = sizeof(struct sctphdr) <<
4736 E1000_ADVTXD_L4LEN_SHIFT;
4737 break;
4738 case IPPROTO_UDP:
4739 mss_l4len_idx = sizeof(struct udphdr) <<
4740 E1000_ADVTXD_L4LEN_SHIFT;
4741 break;
4742 default:
4743 if (unlikely(net_ratelimit())) {
4744 dev_warn(tx_ring->dev,
4745 "partial checksum but l4 proto=%x!\n",
4746 l4_hdr);
4747 }
4748 break;
4749 }
4750
4751 /* update TX checksum flag */
4752 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4753 }
4754
4755 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4756 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4757
4758 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4759 }
4760
4761 #define IGB_SET_FLAG(_input, _flag, _result) \
4762 ((_flag <= _result) ? \
4763 ((u32)(_input & _flag) * (_result / _flag)) : \
4764 ((u32)(_input & _flag) / (_flag / _result)))
4765
4766 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4767 {
4768 /* set type for advanced descriptor with frame checksum insertion */
4769 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4770 E1000_ADVTXD_DCMD_DEXT |
4771 E1000_ADVTXD_DCMD_IFCS;
4772
4773 /* set HW vlan bit if vlan is present */
4774 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4775 (E1000_ADVTXD_DCMD_VLE));
4776
4777 /* set segmentation bits for TSO */
4778 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4779 (E1000_ADVTXD_DCMD_TSE));
4780
4781 /* set timestamp bit if present */
4782 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4783 (E1000_ADVTXD_MAC_TSTAMP));
4784
4785 /* insert frame checksum */
4786 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4787
4788 return cmd_type;
4789 }
4790
4791 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4792 union e1000_adv_tx_desc *tx_desc,
4793 u32 tx_flags, unsigned int paylen)
4794 {
4795 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4796
4797 /* 82575 requires a unique index per ring */
4798 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4799 olinfo_status |= tx_ring->reg_idx << 4;
4800
4801 /* insert L4 checksum */
4802 olinfo_status |= IGB_SET_FLAG(tx_flags,
4803 IGB_TX_FLAGS_CSUM,
4804 (E1000_TXD_POPTS_TXSM << 8));
4805
4806 /* insert IPv4 checksum */
4807 olinfo_status |= IGB_SET_FLAG(tx_flags,
4808 IGB_TX_FLAGS_IPV4,
4809 (E1000_TXD_POPTS_IXSM << 8));
4810
4811 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4812 }
4813
4814 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4815 {
4816 struct net_device *netdev = tx_ring->netdev;
4817
4818 netif_stop_subqueue(netdev, tx_ring->queue_index);
4819
4820 /* Herbert's original patch had:
4821 * smp_mb__after_netif_stop_queue();
4822 * but since that doesn't exist yet, just open code it.
4823 */
4824 smp_mb();
4825
4826 /* We need to check again in a case another CPU has just
4827 * made room available.
4828 */
4829 if (igb_desc_unused(tx_ring) < size)
4830 return -EBUSY;
4831
4832 /* A reprieve! */
4833 netif_wake_subqueue(netdev, tx_ring->queue_index);
4834
4835 u64_stats_update_begin(&tx_ring->tx_syncp2);
4836 tx_ring->tx_stats.restart_queue2++;
4837 u64_stats_update_end(&tx_ring->tx_syncp2);
4838
4839 return 0;
4840 }
4841
4842 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4843 {
4844 if (igb_desc_unused(tx_ring) >= size)
4845 return 0;
4846 return __igb_maybe_stop_tx(tx_ring, size);
4847 }
4848
4849 static void igb_tx_map(struct igb_ring *tx_ring,
4850 struct igb_tx_buffer *first,
4851 const u8 hdr_len)
4852 {
4853 struct sk_buff *skb = first->skb;
4854 struct igb_tx_buffer *tx_buffer;
4855 union e1000_adv_tx_desc *tx_desc;
4856 struct skb_frag_struct *frag;
4857 dma_addr_t dma;
4858 unsigned int data_len, size;
4859 u32 tx_flags = first->tx_flags;
4860 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4861 u16 i = tx_ring->next_to_use;
4862
4863 tx_desc = IGB_TX_DESC(tx_ring, i);
4864
4865 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4866
4867 size = skb_headlen(skb);
4868 data_len = skb->data_len;
4869
4870 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4871
4872 tx_buffer = first;
4873
4874 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4875 if (dma_mapping_error(tx_ring->dev, dma))
4876 goto dma_error;
4877
4878 /* record length, and DMA address */
4879 dma_unmap_len_set(tx_buffer, len, size);
4880 dma_unmap_addr_set(tx_buffer, dma, dma);
4881
4882 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4883
4884 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4885 tx_desc->read.cmd_type_len =
4886 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4887
4888 i++;
4889 tx_desc++;
4890 if (i == tx_ring->count) {
4891 tx_desc = IGB_TX_DESC(tx_ring, 0);
4892 i = 0;
4893 }
4894 tx_desc->read.olinfo_status = 0;
4895
4896 dma += IGB_MAX_DATA_PER_TXD;
4897 size -= IGB_MAX_DATA_PER_TXD;
4898
4899 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4900 }
4901
4902 if (likely(!data_len))
4903 break;
4904
4905 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4906
4907 i++;
4908 tx_desc++;
4909 if (i == tx_ring->count) {
4910 tx_desc = IGB_TX_DESC(tx_ring, 0);
4911 i = 0;
4912 }
4913 tx_desc->read.olinfo_status = 0;
4914
4915 size = skb_frag_size(frag);
4916 data_len -= size;
4917
4918 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4919 size, DMA_TO_DEVICE);
4920
4921 tx_buffer = &tx_ring->tx_buffer_info[i];
4922 }
4923
4924 /* write last descriptor with RS and EOP bits */
4925 cmd_type |= size | IGB_TXD_DCMD;
4926 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4927
4928 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4929
4930 /* set the timestamp */
4931 first->time_stamp = jiffies;
4932
4933 /* Force memory writes to complete before letting h/w know there
4934 * are new descriptors to fetch. (Only applicable for weak-ordered
4935 * memory model archs, such as IA-64).
4936 *
4937 * We also need this memory barrier to make certain all of the
4938 * status bits have been updated before next_to_watch is written.
4939 */
4940 wmb();
4941
4942 /* set next_to_watch value indicating a packet is present */
4943 first->next_to_watch = tx_desc;
4944
4945 i++;
4946 if (i == tx_ring->count)
4947 i = 0;
4948
4949 tx_ring->next_to_use = i;
4950
4951 /* Make sure there is space in the ring for the next send. */
4952 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4953
4954 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4955 writel(i, tx_ring->tail);
4956
4957 /* we need this if more than one processor can write to our tail
4958 * at a time, it synchronizes IO on IA64/Altix systems
4959 */
4960 mmiowb();
4961 }
4962 return;
4963
4964 dma_error:
4965 dev_err(tx_ring->dev, "TX DMA map failed\n");
4966
4967 /* clear dma mappings for failed tx_buffer_info map */
4968 for (;;) {
4969 tx_buffer = &tx_ring->tx_buffer_info[i];
4970 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4971 if (tx_buffer == first)
4972 break;
4973 if (i == 0)
4974 i = tx_ring->count;
4975 i--;
4976 }
4977
4978 tx_ring->next_to_use = i;
4979 }
4980
4981 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4982 struct igb_ring *tx_ring)
4983 {
4984 struct igb_tx_buffer *first;
4985 int tso;
4986 u32 tx_flags = 0;
4987 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4988 __be16 protocol = vlan_get_protocol(skb);
4989 u8 hdr_len = 0;
4990
4991 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4992 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4993 * + 2 desc gap to keep tail from touching head,
4994 * + 1 desc for context descriptor,
4995 * otherwise try next time
4996 */
4997 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4998 unsigned short f;
4999
5000 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5001 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5002 } else {
5003 count += skb_shinfo(skb)->nr_frags;
5004 }
5005
5006 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5007 /* this is a hard error */
5008 return NETDEV_TX_BUSY;
5009 }
5010
5011 /* record the location of the first descriptor for this packet */
5012 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5013 first->skb = skb;
5014 first->bytecount = skb->len;
5015 first->gso_segs = 1;
5016
5017 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5018 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5019
5020 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5021 &adapter->state)) {
5022 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5023 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5024
5025 adapter->ptp_tx_skb = skb_get(skb);
5026 adapter->ptp_tx_start = jiffies;
5027 if (adapter->hw.mac.type == e1000_82576)
5028 schedule_work(&adapter->ptp_tx_work);
5029 }
5030 }
5031
5032 skb_tx_timestamp(skb);
5033
5034 if (vlan_tx_tag_present(skb)) {
5035 tx_flags |= IGB_TX_FLAGS_VLAN;
5036 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5037 }
5038
5039 /* record initial flags and protocol */
5040 first->tx_flags = tx_flags;
5041 first->protocol = protocol;
5042
5043 tso = igb_tso(tx_ring, first, &hdr_len);
5044 if (tso < 0)
5045 goto out_drop;
5046 else if (!tso)
5047 igb_tx_csum(tx_ring, first);
5048
5049 igb_tx_map(tx_ring, first, hdr_len);
5050
5051 return NETDEV_TX_OK;
5052
5053 out_drop:
5054 igb_unmap_and_free_tx_resource(tx_ring, first);
5055
5056 return NETDEV_TX_OK;
5057 }
5058
5059 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5060 struct sk_buff *skb)
5061 {
5062 unsigned int r_idx = skb->queue_mapping;
5063
5064 if (r_idx >= adapter->num_tx_queues)
5065 r_idx = r_idx % adapter->num_tx_queues;
5066
5067 return adapter->tx_ring[r_idx];
5068 }
5069
5070 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5071 struct net_device *netdev)
5072 {
5073 struct igb_adapter *adapter = netdev_priv(netdev);
5074
5075 if (test_bit(__IGB_DOWN, &adapter->state)) {
5076 dev_kfree_skb_any(skb);
5077 return NETDEV_TX_OK;
5078 }
5079
5080 if (skb->len <= 0) {
5081 dev_kfree_skb_any(skb);
5082 return NETDEV_TX_OK;
5083 }
5084
5085 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5086 * in order to meet this minimum size requirement.
5087 */
5088 if (unlikely(skb->len < 17)) {
5089 if (skb_pad(skb, 17 - skb->len))
5090 return NETDEV_TX_OK;
5091 skb->len = 17;
5092 skb_set_tail_pointer(skb, 17);
5093 }
5094
5095 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5096 }
5097
5098 /**
5099 * igb_tx_timeout - Respond to a Tx Hang
5100 * @netdev: network interface device structure
5101 **/
5102 static void igb_tx_timeout(struct net_device *netdev)
5103 {
5104 struct igb_adapter *adapter = netdev_priv(netdev);
5105 struct e1000_hw *hw = &adapter->hw;
5106
5107 /* Do the reset outside of interrupt context */
5108 adapter->tx_timeout_count++;
5109
5110 if (hw->mac.type >= e1000_82580)
5111 hw->dev_spec._82575.global_device_reset = true;
5112
5113 schedule_work(&adapter->reset_task);
5114 wr32(E1000_EICS,
5115 (adapter->eims_enable_mask & ~adapter->eims_other));
5116 }
5117
5118 static void igb_reset_task(struct work_struct *work)
5119 {
5120 struct igb_adapter *adapter;
5121 adapter = container_of(work, struct igb_adapter, reset_task);
5122
5123 igb_dump(adapter);
5124 netdev_err(adapter->netdev, "Reset adapter\n");
5125 igb_reinit_locked(adapter);
5126 }
5127
5128 /**
5129 * igb_get_stats64 - Get System Network Statistics
5130 * @netdev: network interface device structure
5131 * @stats: rtnl_link_stats64 pointer
5132 **/
5133 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5134 struct rtnl_link_stats64 *stats)
5135 {
5136 struct igb_adapter *adapter = netdev_priv(netdev);
5137
5138 spin_lock(&adapter->stats64_lock);
5139 igb_update_stats(adapter, &adapter->stats64);
5140 memcpy(stats, &adapter->stats64, sizeof(*stats));
5141 spin_unlock(&adapter->stats64_lock);
5142
5143 return stats;
5144 }
5145
5146 /**
5147 * igb_change_mtu - Change the Maximum Transfer Unit
5148 * @netdev: network interface device structure
5149 * @new_mtu: new value for maximum frame size
5150 *
5151 * Returns 0 on success, negative on failure
5152 **/
5153 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5154 {
5155 struct igb_adapter *adapter = netdev_priv(netdev);
5156 struct pci_dev *pdev = adapter->pdev;
5157 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5158
5159 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5160 dev_err(&pdev->dev, "Invalid MTU setting\n");
5161 return -EINVAL;
5162 }
5163
5164 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5165 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5166 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5167 return -EINVAL;
5168 }
5169
5170 /* adjust max frame to be at least the size of a standard frame */
5171 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5172 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5173
5174 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5175 usleep_range(1000, 2000);
5176
5177 /* igb_down has a dependency on max_frame_size */
5178 adapter->max_frame_size = max_frame;
5179
5180 if (netif_running(netdev))
5181 igb_down(adapter);
5182
5183 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5184 netdev->mtu, new_mtu);
5185 netdev->mtu = new_mtu;
5186
5187 if (netif_running(netdev))
5188 igb_up(adapter);
5189 else
5190 igb_reset(adapter);
5191
5192 clear_bit(__IGB_RESETTING, &adapter->state);
5193
5194 return 0;
5195 }
5196
5197 /**
5198 * igb_update_stats - Update the board statistics counters
5199 * @adapter: board private structure
5200 **/
5201 void igb_update_stats(struct igb_adapter *adapter,
5202 struct rtnl_link_stats64 *net_stats)
5203 {
5204 struct e1000_hw *hw = &adapter->hw;
5205 struct pci_dev *pdev = adapter->pdev;
5206 u32 reg, mpc;
5207 int i;
5208 u64 bytes, packets;
5209 unsigned int start;
5210 u64 _bytes, _packets;
5211
5212 /* Prevent stats update while adapter is being reset, or if the pci
5213 * connection is down.
5214 */
5215 if (adapter->link_speed == 0)
5216 return;
5217 if (pci_channel_offline(pdev))
5218 return;
5219
5220 bytes = 0;
5221 packets = 0;
5222
5223 rcu_read_lock();
5224 for (i = 0; i < adapter->num_rx_queues; i++) {
5225 struct igb_ring *ring = adapter->rx_ring[i];
5226 u32 rqdpc = rd32(E1000_RQDPC(i));
5227 if (hw->mac.type >= e1000_i210)
5228 wr32(E1000_RQDPC(i), 0);
5229
5230 if (rqdpc) {
5231 ring->rx_stats.drops += rqdpc;
5232 net_stats->rx_fifo_errors += rqdpc;
5233 }
5234
5235 do {
5236 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5237 _bytes = ring->rx_stats.bytes;
5238 _packets = ring->rx_stats.packets;
5239 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5240 bytes += _bytes;
5241 packets += _packets;
5242 }
5243
5244 net_stats->rx_bytes = bytes;
5245 net_stats->rx_packets = packets;
5246
5247 bytes = 0;
5248 packets = 0;
5249 for (i = 0; i < adapter->num_tx_queues; i++) {
5250 struct igb_ring *ring = adapter->tx_ring[i];
5251 do {
5252 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5253 _bytes = ring->tx_stats.bytes;
5254 _packets = ring->tx_stats.packets;
5255 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5256 bytes += _bytes;
5257 packets += _packets;
5258 }
5259 net_stats->tx_bytes = bytes;
5260 net_stats->tx_packets = packets;
5261 rcu_read_unlock();
5262
5263 /* read stats registers */
5264 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5265 adapter->stats.gprc += rd32(E1000_GPRC);
5266 adapter->stats.gorc += rd32(E1000_GORCL);
5267 rd32(E1000_GORCH); /* clear GORCL */
5268 adapter->stats.bprc += rd32(E1000_BPRC);
5269 adapter->stats.mprc += rd32(E1000_MPRC);
5270 adapter->stats.roc += rd32(E1000_ROC);
5271
5272 adapter->stats.prc64 += rd32(E1000_PRC64);
5273 adapter->stats.prc127 += rd32(E1000_PRC127);
5274 adapter->stats.prc255 += rd32(E1000_PRC255);
5275 adapter->stats.prc511 += rd32(E1000_PRC511);
5276 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5277 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5278 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5279 adapter->stats.sec += rd32(E1000_SEC);
5280
5281 mpc = rd32(E1000_MPC);
5282 adapter->stats.mpc += mpc;
5283 net_stats->rx_fifo_errors += mpc;
5284 adapter->stats.scc += rd32(E1000_SCC);
5285 adapter->stats.ecol += rd32(E1000_ECOL);
5286 adapter->stats.mcc += rd32(E1000_MCC);
5287 adapter->stats.latecol += rd32(E1000_LATECOL);
5288 adapter->stats.dc += rd32(E1000_DC);
5289 adapter->stats.rlec += rd32(E1000_RLEC);
5290 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5291 adapter->stats.xontxc += rd32(E1000_XONTXC);
5292 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5293 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5294 adapter->stats.fcruc += rd32(E1000_FCRUC);
5295 adapter->stats.gptc += rd32(E1000_GPTC);
5296 adapter->stats.gotc += rd32(E1000_GOTCL);
5297 rd32(E1000_GOTCH); /* clear GOTCL */
5298 adapter->stats.rnbc += rd32(E1000_RNBC);
5299 adapter->stats.ruc += rd32(E1000_RUC);
5300 adapter->stats.rfc += rd32(E1000_RFC);
5301 adapter->stats.rjc += rd32(E1000_RJC);
5302 adapter->stats.tor += rd32(E1000_TORH);
5303 adapter->stats.tot += rd32(E1000_TOTH);
5304 adapter->stats.tpr += rd32(E1000_TPR);
5305
5306 adapter->stats.ptc64 += rd32(E1000_PTC64);
5307 adapter->stats.ptc127 += rd32(E1000_PTC127);
5308 adapter->stats.ptc255 += rd32(E1000_PTC255);
5309 adapter->stats.ptc511 += rd32(E1000_PTC511);
5310 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5311 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5312
5313 adapter->stats.mptc += rd32(E1000_MPTC);
5314 adapter->stats.bptc += rd32(E1000_BPTC);
5315
5316 adapter->stats.tpt += rd32(E1000_TPT);
5317 adapter->stats.colc += rd32(E1000_COLC);
5318
5319 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5320 /* read internal phy specific stats */
5321 reg = rd32(E1000_CTRL_EXT);
5322 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5323 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5324
5325 /* this stat has invalid values on i210/i211 */
5326 if ((hw->mac.type != e1000_i210) &&
5327 (hw->mac.type != e1000_i211))
5328 adapter->stats.tncrs += rd32(E1000_TNCRS);
5329 }
5330
5331 adapter->stats.tsctc += rd32(E1000_TSCTC);
5332 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5333
5334 adapter->stats.iac += rd32(E1000_IAC);
5335 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5336 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5337 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5338 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5339 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5340 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5341 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5342 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5343
5344 /* Fill out the OS statistics structure */
5345 net_stats->multicast = adapter->stats.mprc;
5346 net_stats->collisions = adapter->stats.colc;
5347
5348 /* Rx Errors */
5349
5350 /* RLEC on some newer hardware can be incorrect so build
5351 * our own version based on RUC and ROC
5352 */
5353 net_stats->rx_errors = adapter->stats.rxerrc +
5354 adapter->stats.crcerrs + adapter->stats.algnerrc +
5355 adapter->stats.ruc + adapter->stats.roc +
5356 adapter->stats.cexterr;
5357 net_stats->rx_length_errors = adapter->stats.ruc +
5358 adapter->stats.roc;
5359 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5360 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5361 net_stats->rx_missed_errors = adapter->stats.mpc;
5362
5363 /* Tx Errors */
5364 net_stats->tx_errors = adapter->stats.ecol +
5365 adapter->stats.latecol;
5366 net_stats->tx_aborted_errors = adapter->stats.ecol;
5367 net_stats->tx_window_errors = adapter->stats.latecol;
5368 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5369
5370 /* Tx Dropped needs to be maintained elsewhere */
5371
5372 /* Management Stats */
5373 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5374 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5375 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5376
5377 /* OS2BMC Stats */
5378 reg = rd32(E1000_MANC);
5379 if (reg & E1000_MANC_EN_BMC2OS) {
5380 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5381 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5382 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5383 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5384 }
5385 }
5386
5387 static irqreturn_t igb_msix_other(int irq, void *data)
5388 {
5389 struct igb_adapter *adapter = data;
5390 struct e1000_hw *hw = &adapter->hw;
5391 u32 icr = rd32(E1000_ICR);
5392 /* reading ICR causes bit 31 of EICR to be cleared */
5393
5394 if (icr & E1000_ICR_DRSTA)
5395 schedule_work(&adapter->reset_task);
5396
5397 if (icr & E1000_ICR_DOUTSYNC) {
5398 /* HW is reporting DMA is out of sync */
5399 adapter->stats.doosync++;
5400 /* The DMA Out of Sync is also indication of a spoof event
5401 * in IOV mode. Check the Wrong VM Behavior register to
5402 * see if it is really a spoof event.
5403 */
5404 igb_check_wvbr(adapter);
5405 }
5406
5407 /* Check for a mailbox event */
5408 if (icr & E1000_ICR_VMMB)
5409 igb_msg_task(adapter);
5410
5411 if (icr & E1000_ICR_LSC) {
5412 hw->mac.get_link_status = 1;
5413 /* guard against interrupt when we're going down */
5414 if (!test_bit(__IGB_DOWN, &adapter->state))
5415 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5416 }
5417
5418 if (icr & E1000_ICR_TS) {
5419 u32 tsicr = rd32(E1000_TSICR);
5420
5421 if (tsicr & E1000_TSICR_TXTS) {
5422 /* acknowledge the interrupt */
5423 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5424 /* retrieve hardware timestamp */
5425 schedule_work(&adapter->ptp_tx_work);
5426 }
5427 }
5428
5429 wr32(E1000_EIMS, adapter->eims_other);
5430
5431 return IRQ_HANDLED;
5432 }
5433
5434 static void igb_write_itr(struct igb_q_vector *q_vector)
5435 {
5436 struct igb_adapter *adapter = q_vector->adapter;
5437 u32 itr_val = q_vector->itr_val & 0x7FFC;
5438
5439 if (!q_vector->set_itr)
5440 return;
5441
5442 if (!itr_val)
5443 itr_val = 0x4;
5444
5445 if (adapter->hw.mac.type == e1000_82575)
5446 itr_val |= itr_val << 16;
5447 else
5448 itr_val |= E1000_EITR_CNT_IGNR;
5449
5450 writel(itr_val, q_vector->itr_register);
5451 q_vector->set_itr = 0;
5452 }
5453
5454 static irqreturn_t igb_msix_ring(int irq, void *data)
5455 {
5456 struct igb_q_vector *q_vector = data;
5457
5458 /* Write the ITR value calculated from the previous interrupt. */
5459 igb_write_itr(q_vector);
5460
5461 napi_schedule(&q_vector->napi);
5462
5463 return IRQ_HANDLED;
5464 }
5465
5466 #ifdef CONFIG_IGB_DCA
5467 static void igb_update_tx_dca(struct igb_adapter *adapter,
5468 struct igb_ring *tx_ring,
5469 int cpu)
5470 {
5471 struct e1000_hw *hw = &adapter->hw;
5472 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5473
5474 if (hw->mac.type != e1000_82575)
5475 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5476
5477 /* We can enable relaxed ordering for reads, but not writes when
5478 * DCA is enabled. This is due to a known issue in some chipsets
5479 * which will cause the DCA tag to be cleared.
5480 */
5481 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5482 E1000_DCA_TXCTRL_DATA_RRO_EN |
5483 E1000_DCA_TXCTRL_DESC_DCA_EN;
5484
5485 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5486 }
5487
5488 static void igb_update_rx_dca(struct igb_adapter *adapter,
5489 struct igb_ring *rx_ring,
5490 int cpu)
5491 {
5492 struct e1000_hw *hw = &adapter->hw;
5493 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5494
5495 if (hw->mac.type != e1000_82575)
5496 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5497
5498 /* We can enable relaxed ordering for reads, but not writes when
5499 * DCA is enabled. This is due to a known issue in some chipsets
5500 * which will cause the DCA tag to be cleared.
5501 */
5502 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5503 E1000_DCA_RXCTRL_DESC_DCA_EN;
5504
5505 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5506 }
5507
5508 static void igb_update_dca(struct igb_q_vector *q_vector)
5509 {
5510 struct igb_adapter *adapter = q_vector->adapter;
5511 int cpu = get_cpu();
5512
5513 if (q_vector->cpu == cpu)
5514 goto out_no_update;
5515
5516 if (q_vector->tx.ring)
5517 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5518
5519 if (q_vector->rx.ring)
5520 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5521
5522 q_vector->cpu = cpu;
5523 out_no_update:
5524 put_cpu();
5525 }
5526
5527 static void igb_setup_dca(struct igb_adapter *adapter)
5528 {
5529 struct e1000_hw *hw = &adapter->hw;
5530 int i;
5531
5532 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5533 return;
5534
5535 /* Always use CB2 mode, difference is masked in the CB driver. */
5536 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5537
5538 for (i = 0; i < adapter->num_q_vectors; i++) {
5539 adapter->q_vector[i]->cpu = -1;
5540 igb_update_dca(adapter->q_vector[i]);
5541 }
5542 }
5543
5544 static int __igb_notify_dca(struct device *dev, void *data)
5545 {
5546 struct net_device *netdev = dev_get_drvdata(dev);
5547 struct igb_adapter *adapter = netdev_priv(netdev);
5548 struct pci_dev *pdev = adapter->pdev;
5549 struct e1000_hw *hw = &adapter->hw;
5550 unsigned long event = *(unsigned long *)data;
5551
5552 switch (event) {
5553 case DCA_PROVIDER_ADD:
5554 /* if already enabled, don't do it again */
5555 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5556 break;
5557 if (dca_add_requester(dev) == 0) {
5558 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5559 dev_info(&pdev->dev, "DCA enabled\n");
5560 igb_setup_dca(adapter);
5561 break;
5562 }
5563 /* Fall Through since DCA is disabled. */
5564 case DCA_PROVIDER_REMOVE:
5565 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5566 /* without this a class_device is left
5567 * hanging around in the sysfs model
5568 */
5569 dca_remove_requester(dev);
5570 dev_info(&pdev->dev, "DCA disabled\n");
5571 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5572 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5573 }
5574 break;
5575 }
5576
5577 return 0;
5578 }
5579
5580 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5581 void *p)
5582 {
5583 int ret_val;
5584
5585 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5586 __igb_notify_dca);
5587
5588 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5589 }
5590 #endif /* CONFIG_IGB_DCA */
5591
5592 #ifdef CONFIG_PCI_IOV
5593 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5594 {
5595 unsigned char mac_addr[ETH_ALEN];
5596
5597 eth_zero_addr(mac_addr);
5598 igb_set_vf_mac(adapter, vf, mac_addr);
5599
5600 /* By default spoof check is enabled for all VFs */
5601 adapter->vf_data[vf].spoofchk_enabled = true;
5602
5603 return 0;
5604 }
5605
5606 #endif
5607 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5608 {
5609 struct e1000_hw *hw = &adapter->hw;
5610 u32 ping;
5611 int i;
5612
5613 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5614 ping = E1000_PF_CONTROL_MSG;
5615 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5616 ping |= E1000_VT_MSGTYPE_CTS;
5617 igb_write_mbx(hw, &ping, 1, i);
5618 }
5619 }
5620
5621 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5622 {
5623 struct e1000_hw *hw = &adapter->hw;
5624 u32 vmolr = rd32(E1000_VMOLR(vf));
5625 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5626
5627 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5628 IGB_VF_FLAG_MULTI_PROMISC);
5629 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5630
5631 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5632 vmolr |= E1000_VMOLR_MPME;
5633 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5634 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5635 } else {
5636 /* if we have hashes and we are clearing a multicast promisc
5637 * flag we need to write the hashes to the MTA as this step
5638 * was previously skipped
5639 */
5640 if (vf_data->num_vf_mc_hashes > 30) {
5641 vmolr |= E1000_VMOLR_MPME;
5642 } else if (vf_data->num_vf_mc_hashes) {
5643 int j;
5644
5645 vmolr |= E1000_VMOLR_ROMPE;
5646 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5647 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5648 }
5649 }
5650
5651 wr32(E1000_VMOLR(vf), vmolr);
5652
5653 /* there are flags left unprocessed, likely not supported */
5654 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5655 return -EINVAL;
5656
5657 return 0;
5658 }
5659
5660 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5661 u32 *msgbuf, u32 vf)
5662 {
5663 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5664 u16 *hash_list = (u16 *)&msgbuf[1];
5665 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5666 int i;
5667
5668 /* salt away the number of multicast addresses assigned
5669 * to this VF for later use to restore when the PF multi cast
5670 * list changes
5671 */
5672 vf_data->num_vf_mc_hashes = n;
5673
5674 /* only up to 30 hash values supported */
5675 if (n > 30)
5676 n = 30;
5677
5678 /* store the hashes for later use */
5679 for (i = 0; i < n; i++)
5680 vf_data->vf_mc_hashes[i] = hash_list[i];
5681
5682 /* Flush and reset the mta with the new values */
5683 igb_set_rx_mode(adapter->netdev);
5684
5685 return 0;
5686 }
5687
5688 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5689 {
5690 struct e1000_hw *hw = &adapter->hw;
5691 struct vf_data_storage *vf_data;
5692 int i, j;
5693
5694 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5695 u32 vmolr = rd32(E1000_VMOLR(i));
5696
5697 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5698
5699 vf_data = &adapter->vf_data[i];
5700
5701 if ((vf_data->num_vf_mc_hashes > 30) ||
5702 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5703 vmolr |= E1000_VMOLR_MPME;
5704 } else if (vf_data->num_vf_mc_hashes) {
5705 vmolr |= E1000_VMOLR_ROMPE;
5706 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5707 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5708 }
5709 wr32(E1000_VMOLR(i), vmolr);
5710 }
5711 }
5712
5713 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5714 {
5715 struct e1000_hw *hw = &adapter->hw;
5716 u32 pool_mask, reg, vid;
5717 int i;
5718
5719 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5720
5721 /* Find the vlan filter for this id */
5722 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5723 reg = rd32(E1000_VLVF(i));
5724
5725 /* remove the vf from the pool */
5726 reg &= ~pool_mask;
5727
5728 /* if pool is empty then remove entry from vfta */
5729 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5730 (reg & E1000_VLVF_VLANID_ENABLE)) {
5731 reg = 0;
5732 vid = reg & E1000_VLVF_VLANID_MASK;
5733 igb_vfta_set(hw, vid, false);
5734 }
5735
5736 wr32(E1000_VLVF(i), reg);
5737 }
5738
5739 adapter->vf_data[vf].vlans_enabled = 0;
5740 }
5741
5742 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5743 {
5744 struct e1000_hw *hw = &adapter->hw;
5745 u32 reg, i;
5746
5747 /* The vlvf table only exists on 82576 hardware and newer */
5748 if (hw->mac.type < e1000_82576)
5749 return -1;
5750
5751 /* we only need to do this if VMDq is enabled */
5752 if (!adapter->vfs_allocated_count)
5753 return -1;
5754
5755 /* Find the vlan filter for this id */
5756 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5757 reg = rd32(E1000_VLVF(i));
5758 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5759 vid == (reg & E1000_VLVF_VLANID_MASK))
5760 break;
5761 }
5762
5763 if (add) {
5764 if (i == E1000_VLVF_ARRAY_SIZE) {
5765 /* Did not find a matching VLAN ID entry that was
5766 * enabled. Search for a free filter entry, i.e.
5767 * one without the enable bit set
5768 */
5769 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5770 reg = rd32(E1000_VLVF(i));
5771 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5772 break;
5773 }
5774 }
5775 if (i < E1000_VLVF_ARRAY_SIZE) {
5776 /* Found an enabled/available entry */
5777 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5778
5779 /* if !enabled we need to set this up in vfta */
5780 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5781 /* add VID to filter table */
5782 igb_vfta_set(hw, vid, true);
5783 reg |= E1000_VLVF_VLANID_ENABLE;
5784 }
5785 reg &= ~E1000_VLVF_VLANID_MASK;
5786 reg |= vid;
5787 wr32(E1000_VLVF(i), reg);
5788
5789 /* do not modify RLPML for PF devices */
5790 if (vf >= adapter->vfs_allocated_count)
5791 return 0;
5792
5793 if (!adapter->vf_data[vf].vlans_enabled) {
5794 u32 size;
5795
5796 reg = rd32(E1000_VMOLR(vf));
5797 size = reg & E1000_VMOLR_RLPML_MASK;
5798 size += 4;
5799 reg &= ~E1000_VMOLR_RLPML_MASK;
5800 reg |= size;
5801 wr32(E1000_VMOLR(vf), reg);
5802 }
5803
5804 adapter->vf_data[vf].vlans_enabled++;
5805 }
5806 } else {
5807 if (i < E1000_VLVF_ARRAY_SIZE) {
5808 /* remove vf from the pool */
5809 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5810 /* if pool is empty then remove entry from vfta */
5811 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5812 reg = 0;
5813 igb_vfta_set(hw, vid, false);
5814 }
5815 wr32(E1000_VLVF(i), reg);
5816
5817 /* do not modify RLPML for PF devices */
5818 if (vf >= adapter->vfs_allocated_count)
5819 return 0;
5820
5821 adapter->vf_data[vf].vlans_enabled--;
5822 if (!adapter->vf_data[vf].vlans_enabled) {
5823 u32 size;
5824
5825 reg = rd32(E1000_VMOLR(vf));
5826 size = reg & E1000_VMOLR_RLPML_MASK;
5827 size -= 4;
5828 reg &= ~E1000_VMOLR_RLPML_MASK;
5829 reg |= size;
5830 wr32(E1000_VMOLR(vf), reg);
5831 }
5832 }
5833 }
5834 return 0;
5835 }
5836
5837 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5838 {
5839 struct e1000_hw *hw = &adapter->hw;
5840
5841 if (vid)
5842 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5843 else
5844 wr32(E1000_VMVIR(vf), 0);
5845 }
5846
5847 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5848 int vf, u16 vlan, u8 qos)
5849 {
5850 int err = 0;
5851 struct igb_adapter *adapter = netdev_priv(netdev);
5852
5853 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5854 return -EINVAL;
5855 if (vlan || qos) {
5856 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5857 if (err)
5858 goto out;
5859 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5860 igb_set_vmolr(adapter, vf, !vlan);
5861 adapter->vf_data[vf].pf_vlan = vlan;
5862 adapter->vf_data[vf].pf_qos = qos;
5863 dev_info(&adapter->pdev->dev,
5864 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5865 if (test_bit(__IGB_DOWN, &adapter->state)) {
5866 dev_warn(&adapter->pdev->dev,
5867 "The VF VLAN has been set, but the PF device is not up.\n");
5868 dev_warn(&adapter->pdev->dev,
5869 "Bring the PF device up before attempting to use the VF device.\n");
5870 }
5871 } else {
5872 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5873 false, vf);
5874 igb_set_vmvir(adapter, vlan, vf);
5875 igb_set_vmolr(adapter, vf, true);
5876 adapter->vf_data[vf].pf_vlan = 0;
5877 adapter->vf_data[vf].pf_qos = 0;
5878 }
5879 out:
5880 return err;
5881 }
5882
5883 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5884 {
5885 struct e1000_hw *hw = &adapter->hw;
5886 int i;
5887 u32 reg;
5888
5889 /* Find the vlan filter for this id */
5890 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5891 reg = rd32(E1000_VLVF(i));
5892 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5893 vid == (reg & E1000_VLVF_VLANID_MASK))
5894 break;
5895 }
5896
5897 if (i >= E1000_VLVF_ARRAY_SIZE)
5898 i = -1;
5899
5900 return i;
5901 }
5902
5903 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5904 {
5905 struct e1000_hw *hw = &adapter->hw;
5906 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5907 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5908 int err = 0;
5909
5910 /* If in promiscuous mode we need to make sure the PF also has
5911 * the VLAN filter set.
5912 */
5913 if (add && (adapter->netdev->flags & IFF_PROMISC))
5914 err = igb_vlvf_set(adapter, vid, add,
5915 adapter->vfs_allocated_count);
5916 if (err)
5917 goto out;
5918
5919 err = igb_vlvf_set(adapter, vid, add, vf);
5920
5921 if (err)
5922 goto out;
5923
5924 /* Go through all the checks to see if the VLAN filter should
5925 * be wiped completely.
5926 */
5927 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5928 u32 vlvf, bits;
5929 int regndx = igb_find_vlvf_entry(adapter, vid);
5930
5931 if (regndx < 0)
5932 goto out;
5933 /* See if any other pools are set for this VLAN filter
5934 * entry other than the PF.
5935 */
5936 vlvf = bits = rd32(E1000_VLVF(regndx));
5937 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5938 adapter->vfs_allocated_count);
5939 /* If the filter was removed then ensure PF pool bit
5940 * is cleared if the PF only added itself to the pool
5941 * because the PF is in promiscuous mode.
5942 */
5943 if ((vlvf & VLAN_VID_MASK) == vid &&
5944 !test_bit(vid, adapter->active_vlans) &&
5945 !bits)
5946 igb_vlvf_set(adapter, vid, add,
5947 adapter->vfs_allocated_count);
5948 }
5949
5950 out:
5951 return err;
5952 }
5953
5954 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5955 {
5956 /* clear flags - except flag that indicates PF has set the MAC */
5957 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5958 adapter->vf_data[vf].last_nack = jiffies;
5959
5960 /* reset offloads to defaults */
5961 igb_set_vmolr(adapter, vf, true);
5962
5963 /* reset vlans for device */
5964 igb_clear_vf_vfta(adapter, vf);
5965 if (adapter->vf_data[vf].pf_vlan)
5966 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5967 adapter->vf_data[vf].pf_vlan,
5968 adapter->vf_data[vf].pf_qos);
5969 else
5970 igb_clear_vf_vfta(adapter, vf);
5971
5972 /* reset multicast table array for vf */
5973 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5974
5975 /* Flush and reset the mta with the new values */
5976 igb_set_rx_mode(adapter->netdev);
5977 }
5978
5979 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5980 {
5981 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5982
5983 /* clear mac address as we were hotplug removed/added */
5984 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5985 eth_zero_addr(vf_mac);
5986
5987 /* process remaining reset events */
5988 igb_vf_reset(adapter, vf);
5989 }
5990
5991 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5992 {
5993 struct e1000_hw *hw = &adapter->hw;
5994 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5995 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5996 u32 reg, msgbuf[3];
5997 u8 *addr = (u8 *)(&msgbuf[1]);
5998
5999 /* process all the same items cleared in a function level reset */
6000 igb_vf_reset(adapter, vf);
6001
6002 /* set vf mac address */
6003 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6004
6005 /* enable transmit and receive for vf */
6006 reg = rd32(E1000_VFTE);
6007 wr32(E1000_VFTE, reg | (1 << vf));
6008 reg = rd32(E1000_VFRE);
6009 wr32(E1000_VFRE, reg | (1 << vf));
6010
6011 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6012
6013 /* reply to reset with ack and vf mac address */
6014 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6015 memcpy(addr, vf_mac, ETH_ALEN);
6016 igb_write_mbx(hw, msgbuf, 3, vf);
6017 }
6018
6019 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6020 {
6021 /* The VF MAC Address is stored in a packed array of bytes
6022 * starting at the second 32 bit word of the msg array
6023 */
6024 unsigned char *addr = (char *)&msg[1];
6025 int err = -1;
6026
6027 if (is_valid_ether_addr(addr))
6028 err = igb_set_vf_mac(adapter, vf, addr);
6029
6030 return err;
6031 }
6032
6033 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6034 {
6035 struct e1000_hw *hw = &adapter->hw;
6036 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6037 u32 msg = E1000_VT_MSGTYPE_NACK;
6038
6039 /* if device isn't clear to send it shouldn't be reading either */
6040 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6041 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6042 igb_write_mbx(hw, &msg, 1, vf);
6043 vf_data->last_nack = jiffies;
6044 }
6045 }
6046
6047 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6048 {
6049 struct pci_dev *pdev = adapter->pdev;
6050 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6051 struct e1000_hw *hw = &adapter->hw;
6052 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6053 s32 retval;
6054
6055 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6056
6057 if (retval) {
6058 /* if receive failed revoke VF CTS stats and restart init */
6059 dev_err(&pdev->dev, "Error receiving message from VF\n");
6060 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6061 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6062 return;
6063 goto out;
6064 }
6065
6066 /* this is a message we already processed, do nothing */
6067 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6068 return;
6069
6070 /* until the vf completes a reset it should not be
6071 * allowed to start any configuration.
6072 */
6073 if (msgbuf[0] == E1000_VF_RESET) {
6074 igb_vf_reset_msg(adapter, vf);
6075 return;
6076 }
6077
6078 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6079 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6080 return;
6081 retval = -1;
6082 goto out;
6083 }
6084
6085 switch ((msgbuf[0] & 0xFFFF)) {
6086 case E1000_VF_SET_MAC_ADDR:
6087 retval = -EINVAL;
6088 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6089 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6090 else
6091 dev_warn(&pdev->dev,
6092 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6093 vf);
6094 break;
6095 case E1000_VF_SET_PROMISC:
6096 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6097 break;
6098 case E1000_VF_SET_MULTICAST:
6099 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6100 break;
6101 case E1000_VF_SET_LPE:
6102 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6103 break;
6104 case E1000_VF_SET_VLAN:
6105 retval = -1;
6106 if (vf_data->pf_vlan)
6107 dev_warn(&pdev->dev,
6108 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6109 vf);
6110 else
6111 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6112 break;
6113 default:
6114 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6115 retval = -1;
6116 break;
6117 }
6118
6119 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6120 out:
6121 /* notify the VF of the results of what it sent us */
6122 if (retval)
6123 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6124 else
6125 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6126
6127 igb_write_mbx(hw, msgbuf, 1, vf);
6128 }
6129
6130 static void igb_msg_task(struct igb_adapter *adapter)
6131 {
6132 struct e1000_hw *hw = &adapter->hw;
6133 u32 vf;
6134
6135 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6136 /* process any reset requests */
6137 if (!igb_check_for_rst(hw, vf))
6138 igb_vf_reset_event(adapter, vf);
6139
6140 /* process any messages pending */
6141 if (!igb_check_for_msg(hw, vf))
6142 igb_rcv_msg_from_vf(adapter, vf);
6143
6144 /* process any acks */
6145 if (!igb_check_for_ack(hw, vf))
6146 igb_rcv_ack_from_vf(adapter, vf);
6147 }
6148 }
6149
6150 /**
6151 * igb_set_uta - Set unicast filter table address
6152 * @adapter: board private structure
6153 *
6154 * The unicast table address is a register array of 32-bit registers.
6155 * The table is meant to be used in a way similar to how the MTA is used
6156 * however due to certain limitations in the hardware it is necessary to
6157 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6158 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6159 **/
6160 static void igb_set_uta(struct igb_adapter *adapter)
6161 {
6162 struct e1000_hw *hw = &adapter->hw;
6163 int i;
6164
6165 /* The UTA table only exists on 82576 hardware and newer */
6166 if (hw->mac.type < e1000_82576)
6167 return;
6168
6169 /* we only need to do this if VMDq is enabled */
6170 if (!adapter->vfs_allocated_count)
6171 return;
6172
6173 for (i = 0; i < hw->mac.uta_reg_count; i++)
6174 array_wr32(E1000_UTA, i, ~0);
6175 }
6176
6177 /**
6178 * igb_intr_msi - Interrupt Handler
6179 * @irq: interrupt number
6180 * @data: pointer to a network interface device structure
6181 **/
6182 static irqreturn_t igb_intr_msi(int irq, void *data)
6183 {
6184 struct igb_adapter *adapter = data;
6185 struct igb_q_vector *q_vector = adapter->q_vector[0];
6186 struct e1000_hw *hw = &adapter->hw;
6187 /* read ICR disables interrupts using IAM */
6188 u32 icr = rd32(E1000_ICR);
6189
6190 igb_write_itr(q_vector);
6191
6192 if (icr & E1000_ICR_DRSTA)
6193 schedule_work(&adapter->reset_task);
6194
6195 if (icr & E1000_ICR_DOUTSYNC) {
6196 /* HW is reporting DMA is out of sync */
6197 adapter->stats.doosync++;
6198 }
6199
6200 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6201 hw->mac.get_link_status = 1;
6202 if (!test_bit(__IGB_DOWN, &adapter->state))
6203 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6204 }
6205
6206 if (icr & E1000_ICR_TS) {
6207 u32 tsicr = rd32(E1000_TSICR);
6208
6209 if (tsicr & E1000_TSICR_TXTS) {
6210 /* acknowledge the interrupt */
6211 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6212 /* retrieve hardware timestamp */
6213 schedule_work(&adapter->ptp_tx_work);
6214 }
6215 }
6216
6217 napi_schedule(&q_vector->napi);
6218
6219 return IRQ_HANDLED;
6220 }
6221
6222 /**
6223 * igb_intr - Legacy Interrupt Handler
6224 * @irq: interrupt number
6225 * @data: pointer to a network interface device structure
6226 **/
6227 static irqreturn_t igb_intr(int irq, void *data)
6228 {
6229 struct igb_adapter *adapter = data;
6230 struct igb_q_vector *q_vector = adapter->q_vector[0];
6231 struct e1000_hw *hw = &adapter->hw;
6232 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6233 * need for the IMC write
6234 */
6235 u32 icr = rd32(E1000_ICR);
6236
6237 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6238 * not set, then the adapter didn't send an interrupt
6239 */
6240 if (!(icr & E1000_ICR_INT_ASSERTED))
6241 return IRQ_NONE;
6242
6243 igb_write_itr(q_vector);
6244
6245 if (icr & E1000_ICR_DRSTA)
6246 schedule_work(&adapter->reset_task);
6247
6248 if (icr & E1000_ICR_DOUTSYNC) {
6249 /* HW is reporting DMA is out of sync */
6250 adapter->stats.doosync++;
6251 }
6252
6253 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6254 hw->mac.get_link_status = 1;
6255 /* guard against interrupt when we're going down */
6256 if (!test_bit(__IGB_DOWN, &adapter->state))
6257 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6258 }
6259
6260 if (icr & E1000_ICR_TS) {
6261 u32 tsicr = rd32(E1000_TSICR);
6262
6263 if (tsicr & E1000_TSICR_TXTS) {
6264 /* acknowledge the interrupt */
6265 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6266 /* retrieve hardware timestamp */
6267 schedule_work(&adapter->ptp_tx_work);
6268 }
6269 }
6270
6271 napi_schedule(&q_vector->napi);
6272
6273 return IRQ_HANDLED;
6274 }
6275
6276 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6277 {
6278 struct igb_adapter *adapter = q_vector->adapter;
6279 struct e1000_hw *hw = &adapter->hw;
6280
6281 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6282 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6283 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6284 igb_set_itr(q_vector);
6285 else
6286 igb_update_ring_itr(q_vector);
6287 }
6288
6289 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6290 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6291 wr32(E1000_EIMS, q_vector->eims_value);
6292 else
6293 igb_irq_enable(adapter);
6294 }
6295 }
6296
6297 /**
6298 * igb_poll - NAPI Rx polling callback
6299 * @napi: napi polling structure
6300 * @budget: count of how many packets we should handle
6301 **/
6302 static int igb_poll(struct napi_struct *napi, int budget)
6303 {
6304 struct igb_q_vector *q_vector = container_of(napi,
6305 struct igb_q_vector,
6306 napi);
6307 bool clean_complete = true;
6308
6309 #ifdef CONFIG_IGB_DCA
6310 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6311 igb_update_dca(q_vector);
6312 #endif
6313 if (q_vector->tx.ring)
6314 clean_complete = igb_clean_tx_irq(q_vector);
6315
6316 if (q_vector->rx.ring)
6317 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6318
6319 /* If all work not completed, return budget and keep polling */
6320 if (!clean_complete)
6321 return budget;
6322
6323 /* If not enough Rx work done, exit the polling mode */
6324 napi_complete(napi);
6325 igb_ring_irq_enable(q_vector);
6326
6327 return 0;
6328 }
6329
6330 /**
6331 * igb_clean_tx_irq - Reclaim resources after transmit completes
6332 * @q_vector: pointer to q_vector containing needed info
6333 *
6334 * returns true if ring is completely cleaned
6335 **/
6336 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6337 {
6338 struct igb_adapter *adapter = q_vector->adapter;
6339 struct igb_ring *tx_ring = q_vector->tx.ring;
6340 struct igb_tx_buffer *tx_buffer;
6341 union e1000_adv_tx_desc *tx_desc;
6342 unsigned int total_bytes = 0, total_packets = 0;
6343 unsigned int budget = q_vector->tx.work_limit;
6344 unsigned int i = tx_ring->next_to_clean;
6345
6346 if (test_bit(__IGB_DOWN, &adapter->state))
6347 return true;
6348
6349 tx_buffer = &tx_ring->tx_buffer_info[i];
6350 tx_desc = IGB_TX_DESC(tx_ring, i);
6351 i -= tx_ring->count;
6352
6353 do {
6354 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6355
6356 /* if next_to_watch is not set then there is no work pending */
6357 if (!eop_desc)
6358 break;
6359
6360 /* prevent any other reads prior to eop_desc */
6361 read_barrier_depends();
6362
6363 /* if DD is not set pending work has not been completed */
6364 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6365 break;
6366
6367 /* clear next_to_watch to prevent false hangs */
6368 tx_buffer->next_to_watch = NULL;
6369
6370 /* update the statistics for this packet */
6371 total_bytes += tx_buffer->bytecount;
6372 total_packets += tx_buffer->gso_segs;
6373
6374 /* free the skb */
6375 dev_consume_skb_any(tx_buffer->skb);
6376
6377 /* unmap skb header data */
6378 dma_unmap_single(tx_ring->dev,
6379 dma_unmap_addr(tx_buffer, dma),
6380 dma_unmap_len(tx_buffer, len),
6381 DMA_TO_DEVICE);
6382
6383 /* clear tx_buffer data */
6384 tx_buffer->skb = NULL;
6385 dma_unmap_len_set(tx_buffer, len, 0);
6386
6387 /* clear last DMA location and unmap remaining buffers */
6388 while (tx_desc != eop_desc) {
6389 tx_buffer++;
6390 tx_desc++;
6391 i++;
6392 if (unlikely(!i)) {
6393 i -= tx_ring->count;
6394 tx_buffer = tx_ring->tx_buffer_info;
6395 tx_desc = IGB_TX_DESC(tx_ring, 0);
6396 }
6397
6398 /* unmap any remaining paged data */
6399 if (dma_unmap_len(tx_buffer, len)) {
6400 dma_unmap_page(tx_ring->dev,
6401 dma_unmap_addr(tx_buffer, dma),
6402 dma_unmap_len(tx_buffer, len),
6403 DMA_TO_DEVICE);
6404 dma_unmap_len_set(tx_buffer, len, 0);
6405 }
6406 }
6407
6408 /* move us one more past the eop_desc for start of next pkt */
6409 tx_buffer++;
6410 tx_desc++;
6411 i++;
6412 if (unlikely(!i)) {
6413 i -= tx_ring->count;
6414 tx_buffer = tx_ring->tx_buffer_info;
6415 tx_desc = IGB_TX_DESC(tx_ring, 0);
6416 }
6417
6418 /* issue prefetch for next Tx descriptor */
6419 prefetch(tx_desc);
6420
6421 /* update budget accounting */
6422 budget--;
6423 } while (likely(budget));
6424
6425 netdev_tx_completed_queue(txring_txq(tx_ring),
6426 total_packets, total_bytes);
6427 i += tx_ring->count;
6428 tx_ring->next_to_clean = i;
6429 u64_stats_update_begin(&tx_ring->tx_syncp);
6430 tx_ring->tx_stats.bytes += total_bytes;
6431 tx_ring->tx_stats.packets += total_packets;
6432 u64_stats_update_end(&tx_ring->tx_syncp);
6433 q_vector->tx.total_bytes += total_bytes;
6434 q_vector->tx.total_packets += total_packets;
6435
6436 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6437 struct e1000_hw *hw = &adapter->hw;
6438
6439 /* Detect a transmit hang in hardware, this serializes the
6440 * check with the clearing of time_stamp and movement of i
6441 */
6442 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6443 if (tx_buffer->next_to_watch &&
6444 time_after(jiffies, tx_buffer->time_stamp +
6445 (adapter->tx_timeout_factor * HZ)) &&
6446 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6447
6448 /* detected Tx unit hang */
6449 dev_err(tx_ring->dev,
6450 "Detected Tx Unit Hang\n"
6451 " Tx Queue <%d>\n"
6452 " TDH <%x>\n"
6453 " TDT <%x>\n"
6454 " next_to_use <%x>\n"
6455 " next_to_clean <%x>\n"
6456 "buffer_info[next_to_clean]\n"
6457 " time_stamp <%lx>\n"
6458 " next_to_watch <%p>\n"
6459 " jiffies <%lx>\n"
6460 " desc.status <%x>\n",
6461 tx_ring->queue_index,
6462 rd32(E1000_TDH(tx_ring->reg_idx)),
6463 readl(tx_ring->tail),
6464 tx_ring->next_to_use,
6465 tx_ring->next_to_clean,
6466 tx_buffer->time_stamp,
6467 tx_buffer->next_to_watch,
6468 jiffies,
6469 tx_buffer->next_to_watch->wb.status);
6470 netif_stop_subqueue(tx_ring->netdev,
6471 tx_ring->queue_index);
6472
6473 /* we are about to reset, no point in enabling stuff */
6474 return true;
6475 }
6476 }
6477
6478 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6479 if (unlikely(total_packets &&
6480 netif_carrier_ok(tx_ring->netdev) &&
6481 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6482 /* Make sure that anybody stopping the queue after this
6483 * sees the new next_to_clean.
6484 */
6485 smp_mb();
6486 if (__netif_subqueue_stopped(tx_ring->netdev,
6487 tx_ring->queue_index) &&
6488 !(test_bit(__IGB_DOWN, &adapter->state))) {
6489 netif_wake_subqueue(tx_ring->netdev,
6490 tx_ring->queue_index);
6491
6492 u64_stats_update_begin(&tx_ring->tx_syncp);
6493 tx_ring->tx_stats.restart_queue++;
6494 u64_stats_update_end(&tx_ring->tx_syncp);
6495 }
6496 }
6497
6498 return !!budget;
6499 }
6500
6501 /**
6502 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6503 * @rx_ring: rx descriptor ring to store buffers on
6504 * @old_buff: donor buffer to have page reused
6505 *
6506 * Synchronizes page for reuse by the adapter
6507 **/
6508 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6509 struct igb_rx_buffer *old_buff)
6510 {
6511 struct igb_rx_buffer *new_buff;
6512 u16 nta = rx_ring->next_to_alloc;
6513
6514 new_buff = &rx_ring->rx_buffer_info[nta];
6515
6516 /* update, and store next to alloc */
6517 nta++;
6518 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6519
6520 /* transfer page from old buffer to new buffer */
6521 *new_buff = *old_buff;
6522
6523 /* sync the buffer for use by the device */
6524 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6525 old_buff->page_offset,
6526 IGB_RX_BUFSZ,
6527 DMA_FROM_DEVICE);
6528 }
6529
6530 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6531 struct page *page,
6532 unsigned int truesize)
6533 {
6534 /* avoid re-using remote pages */
6535 if (unlikely(page_to_nid(page) != numa_node_id()))
6536 return false;
6537
6538 if (unlikely(page->pfmemalloc))
6539 return false;
6540
6541 #if (PAGE_SIZE < 8192)
6542 /* if we are only owner of page we can reuse it */
6543 if (unlikely(page_count(page) != 1))
6544 return false;
6545
6546 /* flip page offset to other buffer */
6547 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6548
6549 /* Even if we own the page, we are not allowed to use atomic_set()
6550 * This would break get_page_unless_zero() users.
6551 */
6552 atomic_inc(&page->_count);
6553 #else
6554 /* move offset up to the next cache line */
6555 rx_buffer->page_offset += truesize;
6556
6557 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6558 return false;
6559
6560 /* bump ref count on page before it is given to the stack */
6561 get_page(page);
6562 #endif
6563
6564 return true;
6565 }
6566
6567 /**
6568 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6569 * @rx_ring: rx descriptor ring to transact packets on
6570 * @rx_buffer: buffer containing page to add
6571 * @rx_desc: descriptor containing length of buffer written by hardware
6572 * @skb: sk_buff to place the data into
6573 *
6574 * This function will add the data contained in rx_buffer->page to the skb.
6575 * This is done either through a direct copy if the data in the buffer is
6576 * less than the skb header size, otherwise it will just attach the page as
6577 * a frag to the skb.
6578 *
6579 * The function will then update the page offset if necessary and return
6580 * true if the buffer can be reused by the adapter.
6581 **/
6582 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6583 struct igb_rx_buffer *rx_buffer,
6584 union e1000_adv_rx_desc *rx_desc,
6585 struct sk_buff *skb)
6586 {
6587 struct page *page = rx_buffer->page;
6588 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6589 #if (PAGE_SIZE < 8192)
6590 unsigned int truesize = IGB_RX_BUFSZ;
6591 #else
6592 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6593 #endif
6594
6595 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6596 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6597
6598 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6599 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6600 va += IGB_TS_HDR_LEN;
6601 size -= IGB_TS_HDR_LEN;
6602 }
6603
6604 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6605
6606 /* we can reuse buffer as-is, just make sure it is local */
6607 if (likely((page_to_nid(page) == numa_node_id()) &&
6608 !page->pfmemalloc))
6609 return true;
6610
6611 /* this page cannot be reused so discard it */
6612 put_page(page);
6613 return false;
6614 }
6615
6616 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6617 rx_buffer->page_offset, size, truesize);
6618
6619 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6620 }
6621
6622 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6623 union e1000_adv_rx_desc *rx_desc,
6624 struct sk_buff *skb)
6625 {
6626 struct igb_rx_buffer *rx_buffer;
6627 struct page *page;
6628
6629 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6630
6631 page = rx_buffer->page;
6632 prefetchw(page);
6633
6634 if (likely(!skb)) {
6635 void *page_addr = page_address(page) +
6636 rx_buffer->page_offset;
6637
6638 /* prefetch first cache line of first page */
6639 prefetch(page_addr);
6640 #if L1_CACHE_BYTES < 128
6641 prefetch(page_addr + L1_CACHE_BYTES);
6642 #endif
6643
6644 /* allocate a skb to store the frags */
6645 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6646 IGB_RX_HDR_LEN);
6647 if (unlikely(!skb)) {
6648 rx_ring->rx_stats.alloc_failed++;
6649 return NULL;
6650 }
6651
6652 /* we will be copying header into skb->data in
6653 * pskb_may_pull so it is in our interest to prefetch
6654 * it now to avoid a possible cache miss
6655 */
6656 prefetchw(skb->data);
6657 }
6658
6659 /* we are reusing so sync this buffer for CPU use */
6660 dma_sync_single_range_for_cpu(rx_ring->dev,
6661 rx_buffer->dma,
6662 rx_buffer->page_offset,
6663 IGB_RX_BUFSZ,
6664 DMA_FROM_DEVICE);
6665
6666 /* pull page into skb */
6667 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6668 /* hand second half of page back to the ring */
6669 igb_reuse_rx_page(rx_ring, rx_buffer);
6670 } else {
6671 /* we are not reusing the buffer so unmap it */
6672 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6673 PAGE_SIZE, DMA_FROM_DEVICE);
6674 }
6675
6676 /* clear contents of rx_buffer */
6677 rx_buffer->page = NULL;
6678
6679 return skb;
6680 }
6681
6682 static inline void igb_rx_checksum(struct igb_ring *ring,
6683 union e1000_adv_rx_desc *rx_desc,
6684 struct sk_buff *skb)
6685 {
6686 skb_checksum_none_assert(skb);
6687
6688 /* Ignore Checksum bit is set */
6689 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6690 return;
6691
6692 /* Rx checksum disabled via ethtool */
6693 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6694 return;
6695
6696 /* TCP/UDP checksum error bit is set */
6697 if (igb_test_staterr(rx_desc,
6698 E1000_RXDEXT_STATERR_TCPE |
6699 E1000_RXDEXT_STATERR_IPE)) {
6700 /* work around errata with sctp packets where the TCPE aka
6701 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6702 * packets, (aka let the stack check the crc32c)
6703 */
6704 if (!((skb->len == 60) &&
6705 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6706 u64_stats_update_begin(&ring->rx_syncp);
6707 ring->rx_stats.csum_err++;
6708 u64_stats_update_end(&ring->rx_syncp);
6709 }
6710 /* let the stack verify checksum errors */
6711 return;
6712 }
6713 /* It must be a TCP or UDP packet with a valid checksum */
6714 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6715 E1000_RXD_STAT_UDPCS))
6716 skb->ip_summed = CHECKSUM_UNNECESSARY;
6717
6718 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6719 le32_to_cpu(rx_desc->wb.upper.status_error));
6720 }
6721
6722 static inline void igb_rx_hash(struct igb_ring *ring,
6723 union e1000_adv_rx_desc *rx_desc,
6724 struct sk_buff *skb)
6725 {
6726 if (ring->netdev->features & NETIF_F_RXHASH)
6727 skb_set_hash(skb,
6728 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6729 PKT_HASH_TYPE_L3);
6730 }
6731
6732 /**
6733 * igb_is_non_eop - process handling of non-EOP buffers
6734 * @rx_ring: Rx ring being processed
6735 * @rx_desc: Rx descriptor for current buffer
6736 * @skb: current socket buffer containing buffer in progress
6737 *
6738 * This function updates next to clean. If the buffer is an EOP buffer
6739 * this function exits returning false, otherwise it will place the
6740 * sk_buff in the next buffer to be chained and return true indicating
6741 * that this is in fact a non-EOP buffer.
6742 **/
6743 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6744 union e1000_adv_rx_desc *rx_desc)
6745 {
6746 u32 ntc = rx_ring->next_to_clean + 1;
6747
6748 /* fetch, update, and store next to clean */
6749 ntc = (ntc < rx_ring->count) ? ntc : 0;
6750 rx_ring->next_to_clean = ntc;
6751
6752 prefetch(IGB_RX_DESC(rx_ring, ntc));
6753
6754 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6755 return false;
6756
6757 return true;
6758 }
6759
6760 /**
6761 * igb_pull_tail - igb specific version of skb_pull_tail
6762 * @rx_ring: rx descriptor ring packet is being transacted on
6763 * @rx_desc: pointer to the EOP Rx descriptor
6764 * @skb: pointer to current skb being adjusted
6765 *
6766 * This function is an igb specific version of __pskb_pull_tail. The
6767 * main difference between this version and the original function is that
6768 * this function can make several assumptions about the state of things
6769 * that allow for significant optimizations versus the standard function.
6770 * As a result we can do things like drop a frag and maintain an accurate
6771 * truesize for the skb.
6772 */
6773 static void igb_pull_tail(struct igb_ring *rx_ring,
6774 union e1000_adv_rx_desc *rx_desc,
6775 struct sk_buff *skb)
6776 {
6777 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6778 unsigned char *va;
6779 unsigned int pull_len;
6780
6781 /* it is valid to use page_address instead of kmap since we are
6782 * working with pages allocated out of the lomem pool per
6783 * alloc_page(GFP_ATOMIC)
6784 */
6785 va = skb_frag_address(frag);
6786
6787 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6788 /* retrieve timestamp from buffer */
6789 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6790
6791 /* update pointers to remove timestamp header */
6792 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6793 frag->page_offset += IGB_TS_HDR_LEN;
6794 skb->data_len -= IGB_TS_HDR_LEN;
6795 skb->len -= IGB_TS_HDR_LEN;
6796
6797 /* move va to start of packet data */
6798 va += IGB_TS_HDR_LEN;
6799 }
6800
6801 /* we need the header to contain the greater of either ETH_HLEN or
6802 * 60 bytes if the skb->len is less than 60 for skb_pad.
6803 */
6804 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6805
6806 /* align pull length to size of long to optimize memcpy performance */
6807 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6808
6809 /* update all of the pointers */
6810 skb_frag_size_sub(frag, pull_len);
6811 frag->page_offset += pull_len;
6812 skb->data_len -= pull_len;
6813 skb->tail += pull_len;
6814 }
6815
6816 /**
6817 * igb_cleanup_headers - Correct corrupted or empty headers
6818 * @rx_ring: rx descriptor ring packet is being transacted on
6819 * @rx_desc: pointer to the EOP Rx descriptor
6820 * @skb: pointer to current skb being fixed
6821 *
6822 * Address the case where we are pulling data in on pages only
6823 * and as such no data is present in the skb header.
6824 *
6825 * In addition if skb is not at least 60 bytes we need to pad it so that
6826 * it is large enough to qualify as a valid Ethernet frame.
6827 *
6828 * Returns true if an error was encountered and skb was freed.
6829 **/
6830 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6831 union e1000_adv_rx_desc *rx_desc,
6832 struct sk_buff *skb)
6833 {
6834 if (unlikely((igb_test_staterr(rx_desc,
6835 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6836 struct net_device *netdev = rx_ring->netdev;
6837 if (!(netdev->features & NETIF_F_RXALL)) {
6838 dev_kfree_skb_any(skb);
6839 return true;
6840 }
6841 }
6842
6843 /* place header in linear portion of buffer */
6844 if (skb_is_nonlinear(skb))
6845 igb_pull_tail(rx_ring, rx_desc, skb);
6846
6847 /* if skb_pad returns an error the skb was freed */
6848 if (unlikely(skb->len < 60)) {
6849 int pad_len = 60 - skb->len;
6850
6851 if (skb_pad(skb, pad_len))
6852 return true;
6853 __skb_put(skb, pad_len);
6854 }
6855
6856 return false;
6857 }
6858
6859 /**
6860 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6861 * @rx_ring: rx descriptor ring packet is being transacted on
6862 * @rx_desc: pointer to the EOP Rx descriptor
6863 * @skb: pointer to current skb being populated
6864 *
6865 * This function checks the ring, descriptor, and packet information in
6866 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6867 * other fields within the skb.
6868 **/
6869 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6870 union e1000_adv_rx_desc *rx_desc,
6871 struct sk_buff *skb)
6872 {
6873 struct net_device *dev = rx_ring->netdev;
6874
6875 igb_rx_hash(rx_ring, rx_desc, skb);
6876
6877 igb_rx_checksum(rx_ring, rx_desc, skb);
6878
6879 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6880 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6881 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6882
6883 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6884 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6885 u16 vid;
6886
6887 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6888 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6889 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6890 else
6891 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6892
6893 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6894 }
6895
6896 skb_record_rx_queue(skb, rx_ring->queue_index);
6897
6898 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6899 }
6900
6901 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6902 {
6903 struct igb_ring *rx_ring = q_vector->rx.ring;
6904 struct sk_buff *skb = rx_ring->skb;
6905 unsigned int total_bytes = 0, total_packets = 0;
6906 u16 cleaned_count = igb_desc_unused(rx_ring);
6907
6908 while (likely(total_packets < budget)) {
6909 union e1000_adv_rx_desc *rx_desc;
6910
6911 /* return some buffers to hardware, one at a time is too slow */
6912 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6913 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6914 cleaned_count = 0;
6915 }
6916
6917 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6918
6919 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6920 break;
6921
6922 /* This memory barrier is needed to keep us from reading
6923 * any other fields out of the rx_desc until we know the
6924 * RXD_STAT_DD bit is set
6925 */
6926 rmb();
6927
6928 /* retrieve a buffer from the ring */
6929 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6930
6931 /* exit if we failed to retrieve a buffer */
6932 if (!skb)
6933 break;
6934
6935 cleaned_count++;
6936
6937 /* fetch next buffer in frame if non-eop */
6938 if (igb_is_non_eop(rx_ring, rx_desc))
6939 continue;
6940
6941 /* verify the packet layout is correct */
6942 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6943 skb = NULL;
6944 continue;
6945 }
6946
6947 /* probably a little skewed due to removing CRC */
6948 total_bytes += skb->len;
6949
6950 /* populate checksum, timestamp, VLAN, and protocol */
6951 igb_process_skb_fields(rx_ring, rx_desc, skb);
6952
6953 napi_gro_receive(&q_vector->napi, skb);
6954
6955 /* reset skb pointer */
6956 skb = NULL;
6957
6958 /* update budget accounting */
6959 total_packets++;
6960 }
6961
6962 /* place incomplete frames back on ring for completion */
6963 rx_ring->skb = skb;
6964
6965 u64_stats_update_begin(&rx_ring->rx_syncp);
6966 rx_ring->rx_stats.packets += total_packets;
6967 rx_ring->rx_stats.bytes += total_bytes;
6968 u64_stats_update_end(&rx_ring->rx_syncp);
6969 q_vector->rx.total_packets += total_packets;
6970 q_vector->rx.total_bytes += total_bytes;
6971
6972 if (cleaned_count)
6973 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6974
6975 return total_packets < budget;
6976 }
6977
6978 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6979 struct igb_rx_buffer *bi)
6980 {
6981 struct page *page = bi->page;
6982 dma_addr_t dma;
6983
6984 /* since we are recycling buffers we should seldom need to alloc */
6985 if (likely(page))
6986 return true;
6987
6988 /* alloc new page for storage */
6989 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6990 if (unlikely(!page)) {
6991 rx_ring->rx_stats.alloc_failed++;
6992 return false;
6993 }
6994
6995 /* map page for use */
6996 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6997
6998 /* if mapping failed free memory back to system since
6999 * there isn't much point in holding memory we can't use
7000 */
7001 if (dma_mapping_error(rx_ring->dev, dma)) {
7002 __free_page(page);
7003
7004 rx_ring->rx_stats.alloc_failed++;
7005 return false;
7006 }
7007
7008 bi->dma = dma;
7009 bi->page = page;
7010 bi->page_offset = 0;
7011
7012 return true;
7013 }
7014
7015 /**
7016 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7017 * @adapter: address of board private structure
7018 **/
7019 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7020 {
7021 union e1000_adv_rx_desc *rx_desc;
7022 struct igb_rx_buffer *bi;
7023 u16 i = rx_ring->next_to_use;
7024
7025 /* nothing to do */
7026 if (!cleaned_count)
7027 return;
7028
7029 rx_desc = IGB_RX_DESC(rx_ring, i);
7030 bi = &rx_ring->rx_buffer_info[i];
7031 i -= rx_ring->count;
7032
7033 do {
7034 if (!igb_alloc_mapped_page(rx_ring, bi))
7035 break;
7036
7037 /* Refresh the desc even if buffer_addrs didn't change
7038 * because each write-back erases this info.
7039 */
7040 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7041
7042 rx_desc++;
7043 bi++;
7044 i++;
7045 if (unlikely(!i)) {
7046 rx_desc = IGB_RX_DESC(rx_ring, 0);
7047 bi = rx_ring->rx_buffer_info;
7048 i -= rx_ring->count;
7049 }
7050
7051 /* clear the hdr_addr for the next_to_use descriptor */
7052 rx_desc->read.hdr_addr = 0;
7053
7054 cleaned_count--;
7055 } while (cleaned_count);
7056
7057 i += rx_ring->count;
7058
7059 if (rx_ring->next_to_use != i) {
7060 /* record the next descriptor to use */
7061 rx_ring->next_to_use = i;
7062
7063 /* update next to alloc since we have filled the ring */
7064 rx_ring->next_to_alloc = i;
7065
7066 /* Force memory writes to complete before letting h/w
7067 * know there are new descriptors to fetch. (Only
7068 * applicable for weak-ordered memory model archs,
7069 * such as IA-64).
7070 */
7071 wmb();
7072 writel(i, rx_ring->tail);
7073 }
7074 }
7075
7076 /**
7077 * igb_mii_ioctl -
7078 * @netdev:
7079 * @ifreq:
7080 * @cmd:
7081 **/
7082 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7083 {
7084 struct igb_adapter *adapter = netdev_priv(netdev);
7085 struct mii_ioctl_data *data = if_mii(ifr);
7086
7087 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7088 return -EOPNOTSUPP;
7089
7090 switch (cmd) {
7091 case SIOCGMIIPHY:
7092 data->phy_id = adapter->hw.phy.addr;
7093 break;
7094 case SIOCGMIIREG:
7095 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7096 &data->val_out))
7097 return -EIO;
7098 break;
7099 case SIOCSMIIREG:
7100 default:
7101 return -EOPNOTSUPP;
7102 }
7103 return 0;
7104 }
7105
7106 /**
7107 * igb_ioctl -
7108 * @netdev:
7109 * @ifreq:
7110 * @cmd:
7111 **/
7112 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7113 {
7114 switch (cmd) {
7115 case SIOCGMIIPHY:
7116 case SIOCGMIIREG:
7117 case SIOCSMIIREG:
7118 return igb_mii_ioctl(netdev, ifr, cmd);
7119 case SIOCGHWTSTAMP:
7120 return igb_ptp_get_ts_config(netdev, ifr);
7121 case SIOCSHWTSTAMP:
7122 return igb_ptp_set_ts_config(netdev, ifr);
7123 default:
7124 return -EOPNOTSUPP;
7125 }
7126 }
7127
7128 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7129 {
7130 struct igb_adapter *adapter = hw->back;
7131
7132 pci_read_config_word(adapter->pdev, reg, value);
7133 }
7134
7135 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7136 {
7137 struct igb_adapter *adapter = hw->back;
7138
7139 pci_write_config_word(adapter->pdev, reg, *value);
7140 }
7141
7142 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7143 {
7144 struct igb_adapter *adapter = hw->back;
7145
7146 if (pcie_capability_read_word(adapter->pdev, reg, value))
7147 return -E1000_ERR_CONFIG;
7148
7149 return 0;
7150 }
7151
7152 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7153 {
7154 struct igb_adapter *adapter = hw->back;
7155
7156 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7157 return -E1000_ERR_CONFIG;
7158
7159 return 0;
7160 }
7161
7162 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7163 {
7164 struct igb_adapter *adapter = netdev_priv(netdev);
7165 struct e1000_hw *hw = &adapter->hw;
7166 u32 ctrl, rctl;
7167 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7168
7169 if (enable) {
7170 /* enable VLAN tag insert/strip */
7171 ctrl = rd32(E1000_CTRL);
7172 ctrl |= E1000_CTRL_VME;
7173 wr32(E1000_CTRL, ctrl);
7174
7175 /* Disable CFI check */
7176 rctl = rd32(E1000_RCTL);
7177 rctl &= ~E1000_RCTL_CFIEN;
7178 wr32(E1000_RCTL, rctl);
7179 } else {
7180 /* disable VLAN tag insert/strip */
7181 ctrl = rd32(E1000_CTRL);
7182 ctrl &= ~E1000_CTRL_VME;
7183 wr32(E1000_CTRL, ctrl);
7184 }
7185
7186 igb_rlpml_set(adapter);
7187 }
7188
7189 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7190 __be16 proto, u16 vid)
7191 {
7192 struct igb_adapter *adapter = netdev_priv(netdev);
7193 struct e1000_hw *hw = &adapter->hw;
7194 int pf_id = adapter->vfs_allocated_count;
7195
7196 /* attempt to add filter to vlvf array */
7197 igb_vlvf_set(adapter, vid, true, pf_id);
7198
7199 /* add the filter since PF can receive vlans w/o entry in vlvf */
7200 igb_vfta_set(hw, vid, true);
7201
7202 set_bit(vid, adapter->active_vlans);
7203
7204 return 0;
7205 }
7206
7207 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7208 __be16 proto, u16 vid)
7209 {
7210 struct igb_adapter *adapter = netdev_priv(netdev);
7211 struct e1000_hw *hw = &adapter->hw;
7212 int pf_id = adapter->vfs_allocated_count;
7213 s32 err;
7214
7215 /* remove vlan from VLVF table array */
7216 err = igb_vlvf_set(adapter, vid, false, pf_id);
7217
7218 /* if vid was not present in VLVF just remove it from table */
7219 if (err)
7220 igb_vfta_set(hw, vid, false);
7221
7222 clear_bit(vid, adapter->active_vlans);
7223
7224 return 0;
7225 }
7226
7227 static void igb_restore_vlan(struct igb_adapter *adapter)
7228 {
7229 u16 vid;
7230
7231 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7232
7233 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7234 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7235 }
7236
7237 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7238 {
7239 struct pci_dev *pdev = adapter->pdev;
7240 struct e1000_mac_info *mac = &adapter->hw.mac;
7241
7242 mac->autoneg = 0;
7243
7244 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7245 * for the switch() below to work
7246 */
7247 if ((spd & 1) || (dplx & ~1))
7248 goto err_inval;
7249
7250 /* Fiber NIC's only allow 1000 gbps Full duplex
7251 * and 100Mbps Full duplex for 100baseFx sfp
7252 */
7253 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7254 switch (spd + dplx) {
7255 case SPEED_10 + DUPLEX_HALF:
7256 case SPEED_10 + DUPLEX_FULL:
7257 case SPEED_100 + DUPLEX_HALF:
7258 goto err_inval;
7259 default:
7260 break;
7261 }
7262 }
7263
7264 switch (spd + dplx) {
7265 case SPEED_10 + DUPLEX_HALF:
7266 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7267 break;
7268 case SPEED_10 + DUPLEX_FULL:
7269 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7270 break;
7271 case SPEED_100 + DUPLEX_HALF:
7272 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7273 break;
7274 case SPEED_100 + DUPLEX_FULL:
7275 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7276 break;
7277 case SPEED_1000 + DUPLEX_FULL:
7278 mac->autoneg = 1;
7279 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7280 break;
7281 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7282 default:
7283 goto err_inval;
7284 }
7285
7286 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7287 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7288
7289 return 0;
7290
7291 err_inval:
7292 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7293 return -EINVAL;
7294 }
7295
7296 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7297 bool runtime)
7298 {
7299 struct net_device *netdev = pci_get_drvdata(pdev);
7300 struct igb_adapter *adapter = netdev_priv(netdev);
7301 struct e1000_hw *hw = &adapter->hw;
7302 u32 ctrl, rctl, status;
7303 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7304 #ifdef CONFIG_PM
7305 int retval = 0;
7306 #endif
7307
7308 netif_device_detach(netdev);
7309
7310 if (netif_running(netdev))
7311 __igb_close(netdev, true);
7312
7313 igb_clear_interrupt_scheme(adapter);
7314
7315 #ifdef CONFIG_PM
7316 retval = pci_save_state(pdev);
7317 if (retval)
7318 return retval;
7319 #endif
7320
7321 status = rd32(E1000_STATUS);
7322 if (status & E1000_STATUS_LU)
7323 wufc &= ~E1000_WUFC_LNKC;
7324
7325 if (wufc) {
7326 igb_setup_rctl(adapter);
7327 igb_set_rx_mode(netdev);
7328
7329 /* turn on all-multi mode if wake on multicast is enabled */
7330 if (wufc & E1000_WUFC_MC) {
7331 rctl = rd32(E1000_RCTL);
7332 rctl |= E1000_RCTL_MPE;
7333 wr32(E1000_RCTL, rctl);
7334 }
7335
7336 ctrl = rd32(E1000_CTRL);
7337 /* advertise wake from D3Cold */
7338 #define E1000_CTRL_ADVD3WUC 0x00100000
7339 /* phy power management enable */
7340 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7341 ctrl |= E1000_CTRL_ADVD3WUC;
7342 wr32(E1000_CTRL, ctrl);
7343
7344 /* Allow time for pending master requests to run */
7345 igb_disable_pcie_master(hw);
7346
7347 wr32(E1000_WUC, E1000_WUC_PME_EN);
7348 wr32(E1000_WUFC, wufc);
7349 } else {
7350 wr32(E1000_WUC, 0);
7351 wr32(E1000_WUFC, 0);
7352 }
7353
7354 *enable_wake = wufc || adapter->en_mng_pt;
7355 if (!*enable_wake)
7356 igb_power_down_link(adapter);
7357 else
7358 igb_power_up_link(adapter);
7359
7360 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7361 * would have already happened in close and is redundant.
7362 */
7363 igb_release_hw_control(adapter);
7364
7365 pci_disable_device(pdev);
7366
7367 return 0;
7368 }
7369
7370 #ifdef CONFIG_PM
7371 #ifdef CONFIG_PM_SLEEP
7372 static int igb_suspend(struct device *dev)
7373 {
7374 int retval;
7375 bool wake;
7376 struct pci_dev *pdev = to_pci_dev(dev);
7377
7378 retval = __igb_shutdown(pdev, &wake, 0);
7379 if (retval)
7380 return retval;
7381
7382 if (wake) {
7383 pci_prepare_to_sleep(pdev);
7384 } else {
7385 pci_wake_from_d3(pdev, false);
7386 pci_set_power_state(pdev, PCI_D3hot);
7387 }
7388
7389 return 0;
7390 }
7391 #endif /* CONFIG_PM_SLEEP */
7392
7393 static int igb_resume(struct device *dev)
7394 {
7395 struct pci_dev *pdev = to_pci_dev(dev);
7396 struct net_device *netdev = pci_get_drvdata(pdev);
7397 struct igb_adapter *adapter = netdev_priv(netdev);
7398 struct e1000_hw *hw = &adapter->hw;
7399 u32 err;
7400
7401 pci_set_power_state(pdev, PCI_D0);
7402 pci_restore_state(pdev);
7403 pci_save_state(pdev);
7404
7405 err = pci_enable_device_mem(pdev);
7406 if (err) {
7407 dev_err(&pdev->dev,
7408 "igb: Cannot enable PCI device from suspend\n");
7409 return err;
7410 }
7411 pci_set_master(pdev);
7412
7413 pci_enable_wake(pdev, PCI_D3hot, 0);
7414 pci_enable_wake(pdev, PCI_D3cold, 0);
7415
7416 if (igb_init_interrupt_scheme(adapter, true)) {
7417 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7418 return -ENOMEM;
7419 }
7420
7421 igb_reset(adapter);
7422
7423 /* let the f/w know that the h/w is now under the control of the
7424 * driver.
7425 */
7426 igb_get_hw_control(adapter);
7427
7428 wr32(E1000_WUS, ~0);
7429
7430 if (netdev->flags & IFF_UP) {
7431 rtnl_lock();
7432 err = __igb_open(netdev, true);
7433 rtnl_unlock();
7434 if (err)
7435 return err;
7436 }
7437
7438 netif_device_attach(netdev);
7439 return 0;
7440 }
7441
7442 static int igb_runtime_idle(struct device *dev)
7443 {
7444 struct pci_dev *pdev = to_pci_dev(dev);
7445 struct net_device *netdev = pci_get_drvdata(pdev);
7446 struct igb_adapter *adapter = netdev_priv(netdev);
7447
7448 if (!igb_has_link(adapter))
7449 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7450
7451 return -EBUSY;
7452 }
7453
7454 static int igb_runtime_suspend(struct device *dev)
7455 {
7456 struct pci_dev *pdev = to_pci_dev(dev);
7457 int retval;
7458 bool wake;
7459
7460 retval = __igb_shutdown(pdev, &wake, 1);
7461 if (retval)
7462 return retval;
7463
7464 if (wake) {
7465 pci_prepare_to_sleep(pdev);
7466 } else {
7467 pci_wake_from_d3(pdev, false);
7468 pci_set_power_state(pdev, PCI_D3hot);
7469 }
7470
7471 return 0;
7472 }
7473
7474 static int igb_runtime_resume(struct device *dev)
7475 {
7476 return igb_resume(dev);
7477 }
7478 #endif /* CONFIG_PM */
7479
7480 static void igb_shutdown(struct pci_dev *pdev)
7481 {
7482 bool wake;
7483
7484 __igb_shutdown(pdev, &wake, 0);
7485
7486 if (system_state == SYSTEM_POWER_OFF) {
7487 pci_wake_from_d3(pdev, wake);
7488 pci_set_power_state(pdev, PCI_D3hot);
7489 }
7490 }
7491
7492 #ifdef CONFIG_PCI_IOV
7493 static int igb_sriov_reinit(struct pci_dev *dev)
7494 {
7495 struct net_device *netdev = pci_get_drvdata(dev);
7496 struct igb_adapter *adapter = netdev_priv(netdev);
7497 struct pci_dev *pdev = adapter->pdev;
7498
7499 rtnl_lock();
7500
7501 if (netif_running(netdev))
7502 igb_close(netdev);
7503 else
7504 igb_reset(adapter);
7505
7506 igb_clear_interrupt_scheme(adapter);
7507
7508 igb_init_queue_configuration(adapter);
7509
7510 if (igb_init_interrupt_scheme(adapter, true)) {
7511 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7512 return -ENOMEM;
7513 }
7514
7515 if (netif_running(netdev))
7516 igb_open(netdev);
7517
7518 rtnl_unlock();
7519
7520 return 0;
7521 }
7522
7523 static int igb_pci_disable_sriov(struct pci_dev *dev)
7524 {
7525 int err = igb_disable_sriov(dev);
7526
7527 if (!err)
7528 err = igb_sriov_reinit(dev);
7529
7530 return err;
7531 }
7532
7533 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7534 {
7535 int err = igb_enable_sriov(dev, num_vfs);
7536
7537 if (err)
7538 goto out;
7539
7540 err = igb_sriov_reinit(dev);
7541 if (!err)
7542 return num_vfs;
7543
7544 out:
7545 return err;
7546 }
7547
7548 #endif
7549 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7550 {
7551 #ifdef CONFIG_PCI_IOV
7552 if (num_vfs == 0)
7553 return igb_pci_disable_sriov(dev);
7554 else
7555 return igb_pci_enable_sriov(dev, num_vfs);
7556 #endif
7557 return 0;
7558 }
7559
7560 #ifdef CONFIG_NET_POLL_CONTROLLER
7561 /* Polling 'interrupt' - used by things like netconsole to send skbs
7562 * without having to re-enable interrupts. It's not called while
7563 * the interrupt routine is executing.
7564 */
7565 static void igb_netpoll(struct net_device *netdev)
7566 {
7567 struct igb_adapter *adapter = netdev_priv(netdev);
7568 struct e1000_hw *hw = &adapter->hw;
7569 struct igb_q_vector *q_vector;
7570 int i;
7571
7572 for (i = 0; i < adapter->num_q_vectors; i++) {
7573 q_vector = adapter->q_vector[i];
7574 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7575 wr32(E1000_EIMC, q_vector->eims_value);
7576 else
7577 igb_irq_disable(adapter);
7578 napi_schedule(&q_vector->napi);
7579 }
7580 }
7581 #endif /* CONFIG_NET_POLL_CONTROLLER */
7582
7583 /**
7584 * igb_io_error_detected - called when PCI error is detected
7585 * @pdev: Pointer to PCI device
7586 * @state: The current pci connection state
7587 *
7588 * This function is called after a PCI bus error affecting
7589 * this device has been detected.
7590 **/
7591 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7592 pci_channel_state_t state)
7593 {
7594 struct net_device *netdev = pci_get_drvdata(pdev);
7595 struct igb_adapter *adapter = netdev_priv(netdev);
7596
7597 netif_device_detach(netdev);
7598
7599 if (state == pci_channel_io_perm_failure)
7600 return PCI_ERS_RESULT_DISCONNECT;
7601
7602 if (netif_running(netdev))
7603 igb_down(adapter);
7604 pci_disable_device(pdev);
7605
7606 /* Request a slot slot reset. */
7607 return PCI_ERS_RESULT_NEED_RESET;
7608 }
7609
7610 /**
7611 * igb_io_slot_reset - called after the pci bus has been reset.
7612 * @pdev: Pointer to PCI device
7613 *
7614 * Restart the card from scratch, as if from a cold-boot. Implementation
7615 * resembles the first-half of the igb_resume routine.
7616 **/
7617 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7618 {
7619 struct net_device *netdev = pci_get_drvdata(pdev);
7620 struct igb_adapter *adapter = netdev_priv(netdev);
7621 struct e1000_hw *hw = &adapter->hw;
7622 pci_ers_result_t result;
7623 int err;
7624
7625 if (pci_enable_device_mem(pdev)) {
7626 dev_err(&pdev->dev,
7627 "Cannot re-enable PCI device after reset.\n");
7628 result = PCI_ERS_RESULT_DISCONNECT;
7629 } else {
7630 pci_set_master(pdev);
7631 pci_restore_state(pdev);
7632 pci_save_state(pdev);
7633
7634 pci_enable_wake(pdev, PCI_D3hot, 0);
7635 pci_enable_wake(pdev, PCI_D3cold, 0);
7636
7637 igb_reset(adapter);
7638 wr32(E1000_WUS, ~0);
7639 result = PCI_ERS_RESULT_RECOVERED;
7640 }
7641
7642 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7643 if (err) {
7644 dev_err(&pdev->dev,
7645 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7646 err);
7647 /* non-fatal, continue */
7648 }
7649
7650 return result;
7651 }
7652
7653 /**
7654 * igb_io_resume - called when traffic can start flowing again.
7655 * @pdev: Pointer to PCI device
7656 *
7657 * This callback is called when the error recovery driver tells us that
7658 * its OK to resume normal operation. Implementation resembles the
7659 * second-half of the igb_resume routine.
7660 */
7661 static void igb_io_resume(struct pci_dev *pdev)
7662 {
7663 struct net_device *netdev = pci_get_drvdata(pdev);
7664 struct igb_adapter *adapter = netdev_priv(netdev);
7665
7666 if (netif_running(netdev)) {
7667 if (igb_up(adapter)) {
7668 dev_err(&pdev->dev, "igb_up failed after reset\n");
7669 return;
7670 }
7671 }
7672
7673 netif_device_attach(netdev);
7674
7675 /* let the f/w know that the h/w is now under the control of the
7676 * driver.
7677 */
7678 igb_get_hw_control(adapter);
7679 }
7680
7681 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7682 u8 qsel)
7683 {
7684 u32 rar_low, rar_high;
7685 struct e1000_hw *hw = &adapter->hw;
7686
7687 /* HW expects these in little endian so we reverse the byte order
7688 * from network order (big endian) to little endian
7689 */
7690 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7691 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7692 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7693
7694 /* Indicate to hardware the Address is Valid. */
7695 rar_high |= E1000_RAH_AV;
7696
7697 if (hw->mac.type == e1000_82575)
7698 rar_high |= E1000_RAH_POOL_1 * qsel;
7699 else
7700 rar_high |= E1000_RAH_POOL_1 << qsel;
7701
7702 wr32(E1000_RAL(index), rar_low);
7703 wrfl();
7704 wr32(E1000_RAH(index), rar_high);
7705 wrfl();
7706 }
7707
7708 static int igb_set_vf_mac(struct igb_adapter *adapter,
7709 int vf, unsigned char *mac_addr)
7710 {
7711 struct e1000_hw *hw = &adapter->hw;
7712 /* VF MAC addresses start at end of receive addresses and moves
7713 * towards the first, as a result a collision should not be possible
7714 */
7715 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7716
7717 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7718
7719 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7720
7721 return 0;
7722 }
7723
7724 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7725 {
7726 struct igb_adapter *adapter = netdev_priv(netdev);
7727 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7728 return -EINVAL;
7729 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7730 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7731 dev_info(&adapter->pdev->dev,
7732 "Reload the VF driver to make this change effective.");
7733 if (test_bit(__IGB_DOWN, &adapter->state)) {
7734 dev_warn(&adapter->pdev->dev,
7735 "The VF MAC address has been set, but the PF device is not up.\n");
7736 dev_warn(&adapter->pdev->dev,
7737 "Bring the PF device up before attempting to use the VF device.\n");
7738 }
7739 return igb_set_vf_mac(adapter, vf, mac);
7740 }
7741
7742 static int igb_link_mbps(int internal_link_speed)
7743 {
7744 switch (internal_link_speed) {
7745 case SPEED_100:
7746 return 100;
7747 case SPEED_1000:
7748 return 1000;
7749 default:
7750 return 0;
7751 }
7752 }
7753
7754 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7755 int link_speed)
7756 {
7757 int rf_dec, rf_int;
7758 u32 bcnrc_val;
7759
7760 if (tx_rate != 0) {
7761 /* Calculate the rate factor values to set */
7762 rf_int = link_speed / tx_rate;
7763 rf_dec = (link_speed - (rf_int * tx_rate));
7764 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7765 tx_rate;
7766
7767 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7768 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7769 E1000_RTTBCNRC_RF_INT_MASK);
7770 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7771 } else {
7772 bcnrc_val = 0;
7773 }
7774
7775 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7776 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7777 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7778 */
7779 wr32(E1000_RTTBCNRM, 0x14);
7780 wr32(E1000_RTTBCNRC, bcnrc_val);
7781 }
7782
7783 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7784 {
7785 int actual_link_speed, i;
7786 bool reset_rate = false;
7787
7788 /* VF TX rate limit was not set or not supported */
7789 if ((adapter->vf_rate_link_speed == 0) ||
7790 (adapter->hw.mac.type != e1000_82576))
7791 return;
7792
7793 actual_link_speed = igb_link_mbps(adapter->link_speed);
7794 if (actual_link_speed != adapter->vf_rate_link_speed) {
7795 reset_rate = true;
7796 adapter->vf_rate_link_speed = 0;
7797 dev_info(&adapter->pdev->dev,
7798 "Link speed has been changed. VF Transmit rate is disabled\n");
7799 }
7800
7801 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7802 if (reset_rate)
7803 adapter->vf_data[i].tx_rate = 0;
7804
7805 igb_set_vf_rate_limit(&adapter->hw, i,
7806 adapter->vf_data[i].tx_rate,
7807 actual_link_speed);
7808 }
7809 }
7810
7811 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7812 int min_tx_rate, int max_tx_rate)
7813 {
7814 struct igb_adapter *adapter = netdev_priv(netdev);
7815 struct e1000_hw *hw = &adapter->hw;
7816 int actual_link_speed;
7817
7818 if (hw->mac.type != e1000_82576)
7819 return -EOPNOTSUPP;
7820
7821 if (min_tx_rate)
7822 return -EINVAL;
7823
7824 actual_link_speed = igb_link_mbps(adapter->link_speed);
7825 if ((vf >= adapter->vfs_allocated_count) ||
7826 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7827 (max_tx_rate < 0) ||
7828 (max_tx_rate > actual_link_speed))
7829 return -EINVAL;
7830
7831 adapter->vf_rate_link_speed = actual_link_speed;
7832 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7833 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7834
7835 return 0;
7836 }
7837
7838 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7839 bool setting)
7840 {
7841 struct igb_adapter *adapter = netdev_priv(netdev);
7842 struct e1000_hw *hw = &adapter->hw;
7843 u32 reg_val, reg_offset;
7844
7845 if (!adapter->vfs_allocated_count)
7846 return -EOPNOTSUPP;
7847
7848 if (vf >= adapter->vfs_allocated_count)
7849 return -EINVAL;
7850
7851 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7852 reg_val = rd32(reg_offset);
7853 if (setting)
7854 reg_val |= ((1 << vf) |
7855 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7856 else
7857 reg_val &= ~((1 << vf) |
7858 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7859 wr32(reg_offset, reg_val);
7860
7861 adapter->vf_data[vf].spoofchk_enabled = setting;
7862 return 0;
7863 }
7864
7865 static int igb_ndo_get_vf_config(struct net_device *netdev,
7866 int vf, struct ifla_vf_info *ivi)
7867 {
7868 struct igb_adapter *adapter = netdev_priv(netdev);
7869 if (vf >= adapter->vfs_allocated_count)
7870 return -EINVAL;
7871 ivi->vf = vf;
7872 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7873 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7874 ivi->min_tx_rate = 0;
7875 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7876 ivi->qos = adapter->vf_data[vf].pf_qos;
7877 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7878 return 0;
7879 }
7880
7881 static void igb_vmm_control(struct igb_adapter *adapter)
7882 {
7883 struct e1000_hw *hw = &adapter->hw;
7884 u32 reg;
7885
7886 switch (hw->mac.type) {
7887 case e1000_82575:
7888 case e1000_i210:
7889 case e1000_i211:
7890 case e1000_i354:
7891 default:
7892 /* replication is not supported for 82575 */
7893 return;
7894 case e1000_82576:
7895 /* notify HW that the MAC is adding vlan tags */
7896 reg = rd32(E1000_DTXCTL);
7897 reg |= E1000_DTXCTL_VLAN_ADDED;
7898 wr32(E1000_DTXCTL, reg);
7899 /* Fall through */
7900 case e1000_82580:
7901 /* enable replication vlan tag stripping */
7902 reg = rd32(E1000_RPLOLR);
7903 reg |= E1000_RPLOLR_STRVLAN;
7904 wr32(E1000_RPLOLR, reg);
7905 /* Fall through */
7906 case e1000_i350:
7907 /* none of the above registers are supported by i350 */
7908 break;
7909 }
7910
7911 if (adapter->vfs_allocated_count) {
7912 igb_vmdq_set_loopback_pf(hw, true);
7913 igb_vmdq_set_replication_pf(hw, true);
7914 igb_vmdq_set_anti_spoofing_pf(hw, true,
7915 adapter->vfs_allocated_count);
7916 } else {
7917 igb_vmdq_set_loopback_pf(hw, false);
7918 igb_vmdq_set_replication_pf(hw, false);
7919 }
7920 }
7921
7922 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7923 {
7924 struct e1000_hw *hw = &adapter->hw;
7925 u32 dmac_thr;
7926 u16 hwm;
7927
7928 if (hw->mac.type > e1000_82580) {
7929 if (adapter->flags & IGB_FLAG_DMAC) {
7930 u32 reg;
7931
7932 /* force threshold to 0. */
7933 wr32(E1000_DMCTXTH, 0);
7934
7935 /* DMA Coalescing high water mark needs to be greater
7936 * than the Rx threshold. Set hwm to PBA - max frame
7937 * size in 16B units, capping it at PBA - 6KB.
7938 */
7939 hwm = 64 * pba - adapter->max_frame_size / 16;
7940 if (hwm < 64 * (pba - 6))
7941 hwm = 64 * (pba - 6);
7942 reg = rd32(E1000_FCRTC);
7943 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7944 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7945 & E1000_FCRTC_RTH_COAL_MASK);
7946 wr32(E1000_FCRTC, reg);
7947
7948 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7949 * frame size, capping it at PBA - 10KB.
7950 */
7951 dmac_thr = pba - adapter->max_frame_size / 512;
7952 if (dmac_thr < pba - 10)
7953 dmac_thr = pba - 10;
7954 reg = rd32(E1000_DMACR);
7955 reg &= ~E1000_DMACR_DMACTHR_MASK;
7956 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7957 & E1000_DMACR_DMACTHR_MASK);
7958
7959 /* transition to L0x or L1 if available..*/
7960 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7961
7962 /* watchdog timer= +-1000 usec in 32usec intervals */
7963 reg |= (1000 >> 5);
7964
7965 /* Disable BMC-to-OS Watchdog Enable */
7966 if (hw->mac.type != e1000_i354)
7967 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7968
7969 wr32(E1000_DMACR, reg);
7970
7971 /* no lower threshold to disable
7972 * coalescing(smart fifb)-UTRESH=0
7973 */
7974 wr32(E1000_DMCRTRH, 0);
7975
7976 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7977
7978 wr32(E1000_DMCTLX, reg);
7979
7980 /* free space in tx packet buffer to wake from
7981 * DMA coal
7982 */
7983 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7984 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7985
7986 /* make low power state decision controlled
7987 * by DMA coal
7988 */
7989 reg = rd32(E1000_PCIEMISC);
7990 reg &= ~E1000_PCIEMISC_LX_DECISION;
7991 wr32(E1000_PCIEMISC, reg);
7992 } /* endif adapter->dmac is not disabled */
7993 } else if (hw->mac.type == e1000_82580) {
7994 u32 reg = rd32(E1000_PCIEMISC);
7995
7996 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7997 wr32(E1000_DMACR, 0);
7998 }
7999 }
8000
8001 /**
8002 * igb_read_i2c_byte - Reads 8 bit word over I2C
8003 * @hw: pointer to hardware structure
8004 * @byte_offset: byte offset to read
8005 * @dev_addr: device address
8006 * @data: value read
8007 *
8008 * Performs byte read operation over I2C interface at
8009 * a specified device address.
8010 **/
8011 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8012 u8 dev_addr, u8 *data)
8013 {
8014 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8015 struct i2c_client *this_client = adapter->i2c_client;
8016 s32 status;
8017 u16 swfw_mask = 0;
8018
8019 if (!this_client)
8020 return E1000_ERR_I2C;
8021
8022 swfw_mask = E1000_SWFW_PHY0_SM;
8023
8024 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8025 return E1000_ERR_SWFW_SYNC;
8026
8027 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8028 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8029
8030 if (status < 0)
8031 return E1000_ERR_I2C;
8032 else {
8033 *data = status;
8034 return 0;
8035 }
8036 }
8037
8038 /**
8039 * igb_write_i2c_byte - Writes 8 bit word over I2C
8040 * @hw: pointer to hardware structure
8041 * @byte_offset: byte offset to write
8042 * @dev_addr: device address
8043 * @data: value to write
8044 *
8045 * Performs byte write operation over I2C interface at
8046 * a specified device address.
8047 **/
8048 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8049 u8 dev_addr, u8 data)
8050 {
8051 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8052 struct i2c_client *this_client = adapter->i2c_client;
8053 s32 status;
8054 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8055
8056 if (!this_client)
8057 return E1000_ERR_I2C;
8058
8059 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8060 return E1000_ERR_SWFW_SYNC;
8061 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8062 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8063
8064 if (status)
8065 return E1000_ERR_I2C;
8066 else
8067 return 0;
8068
8069 }
8070
8071 int igb_reinit_queues(struct igb_adapter *adapter)
8072 {
8073 struct net_device *netdev = adapter->netdev;
8074 struct pci_dev *pdev = adapter->pdev;
8075 int err = 0;
8076
8077 if (netif_running(netdev))
8078 igb_close(netdev);
8079
8080 igb_reset_interrupt_capability(adapter);
8081
8082 if (igb_init_interrupt_scheme(adapter, true)) {
8083 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8084 return -ENOMEM;
8085 }
8086
8087 if (netif_running(netdev))
8088 err = igb_open(netdev);
8089
8090 return err;
8091 }
8092 /* igb_main.c */
Linux kernel - Deliverables
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