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igb: Fix NULL assignment to incorrect variable in igb_reset_q_vector
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
57 #include "igb.h"
58
59 #define MAJ 5
60 #define MIN 2
61 #define BUILD 15
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71 static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73 };
74
75 static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 #endif
183
184 #ifdef CONFIG_PM
185 #ifdef CONFIG_PM_SLEEP
186 static int igb_suspend(struct device *);
187 #endif
188 static int igb_resume(struct device *);
189 static int igb_runtime_suspend(struct device *dev);
190 static int igb_runtime_resume(struct device *dev);
191 static int igb_runtime_idle(struct device *dev);
192 static const struct dev_pm_ops igb_pm_ops = {
193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
195 igb_runtime_idle)
196 };
197 #endif
198 static void igb_shutdown(struct pci_dev *);
199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
200 #ifdef CONFIG_IGB_DCA
201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202 static struct notifier_block dca_notifier = {
203 .notifier_call = igb_notify_dca,
204 .next = NULL,
205 .priority = 0
206 };
207 #endif
208 #ifdef CONFIG_NET_POLL_CONTROLLER
209 /* for netdump / net console */
210 static void igb_netpoll(struct net_device *);
211 #endif
212 #ifdef CONFIG_PCI_IOV
213 static unsigned int max_vfs;
214 module_param(max_vfs, uint, 0);
215 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
216 #endif /* CONFIG_PCI_IOV */
217
218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221 static void igb_io_resume(struct pci_dev *);
222
223 static const struct pci_error_handlers igb_err_handler = {
224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227 };
228
229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
230
231 static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
235 .remove = igb_remove,
236 #ifdef CONFIG_PM
237 .driver.pm = &igb_pm_ops,
238 #endif
239 .shutdown = igb_shutdown,
240 .sriov_configure = igb_pci_sriov_configure,
241 .err_handler = &igb_err_handler
242 };
243
244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246 MODULE_LICENSE("GPL");
247 MODULE_VERSION(DRV_VERSION);
248
249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250 static int debug = -1;
251 module_param(debug, int, 0);
252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
254 struct igb_reg_info {
255 u32 ofs;
256 char *name;
257 };
258
259 static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293 };
294
295 /* igb_regdump - register printout routine */
296 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297 {
298 int n = 0;
299 char rname[16];
300 u32 regs[8];
301
302 switch (reginfo->ofs) {
303 case E1000_RDLEN(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_RDLEN(n));
306 break;
307 case E1000_RDH(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDH(n));
310 break;
311 case E1000_RDT(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDT(n));
314 break;
315 case E1000_RXDCTL(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RXDCTL(n));
318 break;
319 case E1000_RDBAL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RDBAL(n));
322 break;
323 case E1000_RDBAH(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAH(n));
326 break;
327 case E1000_TDBAL(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAL(n));
330 break;
331 case E1000_TDBAH(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_TDBAH(n));
334 break;
335 case E1000_TDLEN(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDLEN(n));
338 break;
339 case E1000_TDH(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDH(n));
342 break;
343 case E1000_TDT(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDT(n));
346 break;
347 case E1000_TXDCTL(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TXDCTL(n));
350 break;
351 default:
352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
353 return;
354 }
355
356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 regs[2], regs[3]);
359 }
360
361 /* igb_dump - Print registers, Tx-rings and Rx-rings */
362 static void igb_dump(struct igb_adapter *adapter)
363 {
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
373 u16 i, n;
374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
381 pr_info("Device Name state trans_start last_rx\n");
382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
388 pr_info(" Register Name Value\n");
389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
400 for (n = 0; n < adapter->num_tx_queues; n++) {
401 struct igb_tx_buffer *buffer_info;
402 tx_ring = adapter->tx_ring[n];
403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
435
436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
437 const char *next_desc;
438 struct igb_tx_buffer *buffer_info;
439 tx_desc = IGB_TX_DESC(tx_ring, i);
440 buffer_info = &tx_ring->tx_buffer_info[i];
441 u0 = (struct my_u0 *)tx_desc;
442 if (i == tx_ring->next_to_use &&
443 i == tx_ring->next_to_clean)
444 next_desc = " NTC/U";
445 else if (i == tx_ring->next_to_use)
446 next_desc = " NTU";
447 else if (i == tx_ring->next_to_clean)
448 next_desc = " NTC";
449 else
450 next_desc = "";
451
452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
453 i, le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(buffer_info, dma),
456 dma_unmap_len(buffer_info, len),
457 buffer_info->next_to_watch,
458 (u64)buffer_info->time_stamp,
459 buffer_info->skb, next_desc);
460
461 if (netif_msg_pktdata(adapter) && buffer_info->skb)
462 print_hex_dump(KERN_INFO, "",
463 DUMP_PREFIX_ADDRESS,
464 16, 1, buffer_info->skb->data,
465 dma_unmap_len(buffer_info, len),
466 true);
467 }
468 }
469
470 /* Print RX Rings Summary */
471 rx_ring_summary:
472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
473 pr_info("Queue [NTU] [NTC]\n");
474 for (n = 0; n < adapter->num_rx_queues; n++) {
475 rx_ring = adapter->rx_ring[n];
476 pr_info(" %5d %5X %5X\n",
477 n, rx_ring->next_to_use, rx_ring->next_to_clean);
478 }
479
480 /* Print RX Rings */
481 if (!netif_msg_rx_status(adapter))
482 goto exit;
483
484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
485
486 /* Advanced Receive Descriptor (Read) Format
487 * 63 1 0
488 * +-----------------------------------------------------+
489 * 0 | Packet Buffer Address [63:1] |A0/NSE|
490 * +----------------------------------------------+------+
491 * 8 | Header Buffer Address [63:1] | DD |
492 * +-----------------------------------------------------+
493 *
494 *
495 * Advanced Receive Descriptor (Write-Back) Format
496 *
497 * 63 48 47 32 31 30 21 20 17 16 4 3 0
498 * +------------------------------------------------------+
499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
500 * | Checksum Ident | | | | Type | Type |
501 * +------------------------------------------------------+
502 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 * +------------------------------------------------------+
504 * 63 48 47 32 31 20 19 0
505 */
506
507 for (n = 0; n < adapter->num_rx_queues; n++) {
508 rx_ring = adapter->rx_ring[n];
509 pr_info("------------------------------------\n");
510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
511 pr_info("------------------------------------\n");
512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
514
515 for (i = 0; i < rx_ring->count; i++) {
516 const char *next_desc;
517 struct igb_rx_buffer *buffer_info;
518 buffer_info = &rx_ring->rx_buffer_info[i];
519 rx_desc = IGB_RX_DESC(rx_ring, i);
520 u0 = (struct my_u0 *)rx_desc;
521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
522
523 if (i == rx_ring->next_to_use)
524 next_desc = " NTU";
525 else if (i == rx_ring->next_to_clean)
526 next_desc = " NTC";
527 else
528 next_desc = "";
529
530 if (staterr & E1000_RXD_STAT_DD) {
531 /* Descriptor Done */
532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
533 "RWB", i,
534 le64_to_cpu(u0->a),
535 le64_to_cpu(u0->b),
536 next_desc);
537 } else {
538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
539 "R ", i,
540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
542 (u64)buffer_info->dma,
543 next_desc);
544
545 if (netif_msg_pktdata(adapter) &&
546 buffer_info->dma && buffer_info->page) {
547 print_hex_dump(KERN_INFO, "",
548 DUMP_PREFIX_ADDRESS,
549 16, 1,
550 page_address(buffer_info->page) +
551 buffer_info->page_offset,
552 IGB_RX_BUFSZ, true);
553 }
554 }
555 }
556 }
557
558 exit:
559 return;
560 }
561
562 /**
563 * igb_get_i2c_data - Reads the I2C SDA data bit
564 * @hw: pointer to hardware structure
565 * @i2cctl: Current value of I2CCTL register
566 *
567 * Returns the I2C data bit value
568 **/
569 static int igb_get_i2c_data(void *data)
570 {
571 struct igb_adapter *adapter = (struct igb_adapter *)data;
572 struct e1000_hw *hw = &adapter->hw;
573 s32 i2cctl = rd32(E1000_I2CPARAMS);
574
575 return !!(i2cctl & E1000_I2C_DATA_IN);
576 }
577
578 /**
579 * igb_set_i2c_data - Sets the I2C data bit
580 * @data: pointer to hardware structure
581 * @state: I2C data value (0 or 1) to set
582 *
583 * Sets the I2C data bit
584 **/
585 static void igb_set_i2c_data(void *data, int state)
586 {
587 struct igb_adapter *adapter = (struct igb_adapter *)data;
588 struct e1000_hw *hw = &adapter->hw;
589 s32 i2cctl = rd32(E1000_I2CPARAMS);
590
591 if (state)
592 i2cctl |= E1000_I2C_DATA_OUT;
593 else
594 i2cctl &= ~E1000_I2C_DATA_OUT;
595
596 i2cctl &= ~E1000_I2C_DATA_OE_N;
597 i2cctl |= E1000_I2C_CLK_OE_N;
598 wr32(E1000_I2CPARAMS, i2cctl);
599 wrfl();
600
601 }
602
603 /**
604 * igb_set_i2c_clk - Sets the I2C SCL clock
605 * @data: pointer to hardware structure
606 * @state: state to set clock
607 *
608 * Sets the I2C clock line to state
609 **/
610 static void igb_set_i2c_clk(void *data, int state)
611 {
612 struct igb_adapter *adapter = (struct igb_adapter *)data;
613 struct e1000_hw *hw = &adapter->hw;
614 s32 i2cctl = rd32(E1000_I2CPARAMS);
615
616 if (state) {
617 i2cctl |= E1000_I2C_CLK_OUT;
618 i2cctl &= ~E1000_I2C_CLK_OE_N;
619 } else {
620 i2cctl &= ~E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 }
623 wr32(E1000_I2CPARAMS, i2cctl);
624 wrfl();
625 }
626
627 /**
628 * igb_get_i2c_clk - Gets the I2C SCL clock state
629 * @data: pointer to hardware structure
630 *
631 * Gets the I2C clock state
632 **/
633 static int igb_get_i2c_clk(void *data)
634 {
635 struct igb_adapter *adapter = (struct igb_adapter *)data;
636 struct e1000_hw *hw = &adapter->hw;
637 s32 i2cctl = rd32(E1000_I2CPARAMS);
638
639 return !!(i2cctl & E1000_I2C_CLK_IN);
640 }
641
642 static const struct i2c_algo_bit_data igb_i2c_algo = {
643 .setsda = igb_set_i2c_data,
644 .setscl = igb_set_i2c_clk,
645 .getsda = igb_get_i2c_data,
646 .getscl = igb_get_i2c_clk,
647 .udelay = 5,
648 .timeout = 20,
649 };
650
651 /**
652 * igb_get_hw_dev - return device
653 * @hw: pointer to hardware structure
654 *
655 * used by hardware layer to print debugging information
656 **/
657 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
658 {
659 struct igb_adapter *adapter = hw->back;
660 return adapter->netdev;
661 }
662
663 /**
664 * igb_init_module - Driver Registration Routine
665 *
666 * igb_init_module is the first routine called when the driver is
667 * loaded. All it does is register with the PCI subsystem.
668 **/
669 static int __init igb_init_module(void)
670 {
671 int ret;
672
673 pr_info("%s - version %s\n",
674 igb_driver_string, igb_driver_version);
675 pr_info("%s\n", igb_copyright);
676
677 #ifdef CONFIG_IGB_DCA
678 dca_register_notify(&dca_notifier);
679 #endif
680 ret = pci_register_driver(&igb_driver);
681 return ret;
682 }
683
684 module_init(igb_init_module);
685
686 /**
687 * igb_exit_module - Driver Exit Cleanup Routine
688 *
689 * igb_exit_module is called just before the driver is removed
690 * from memory.
691 **/
692 static void __exit igb_exit_module(void)
693 {
694 #ifdef CONFIG_IGB_DCA
695 dca_unregister_notify(&dca_notifier);
696 #endif
697 pci_unregister_driver(&igb_driver);
698 }
699
700 module_exit(igb_exit_module);
701
702 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703 /**
704 * igb_cache_ring_register - Descriptor ring to register mapping
705 * @adapter: board private structure to initialize
706 *
707 * Once we know the feature-set enabled for the device, we'll cache
708 * the register offset the descriptor ring is assigned to.
709 **/
710 static void igb_cache_ring_register(struct igb_adapter *adapter)
711 {
712 int i = 0, j = 0;
713 u32 rbase_offset = adapter->vfs_allocated_count;
714
715 switch (adapter->hw.mac.type) {
716 case e1000_82576:
717 /* The queues are allocated for virtualization such that VF 0
718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 * In order to avoid collision we start at the first free queue
720 * and continue consuming queues in the same sequence
721 */
722 if (adapter->vfs_allocated_count) {
723 for (; i < adapter->rss_queues; i++)
724 adapter->rx_ring[i]->reg_idx = rbase_offset +
725 Q_IDX_82576(i);
726 }
727 /* Fall through */
728 case e1000_82575:
729 case e1000_82580:
730 case e1000_i350:
731 case e1000_i354:
732 case e1000_i210:
733 case e1000_i211:
734 /* Fall through */
735 default:
736 for (; i < adapter->num_rx_queues; i++)
737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
738 for (; j < adapter->num_tx_queues; j++)
739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
740 break;
741 }
742 }
743
744 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
745 {
746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
748 u32 value = 0;
749
750 if (E1000_REMOVED(hw_addr))
751 return ~value;
752
753 value = readl(&hw_addr[reg]);
754
755 /* reads should not return all F's */
756 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
757 struct net_device *netdev = igb->netdev;
758 hw->hw_addr = NULL;
759 netif_device_detach(netdev);
760 netdev_err(netdev, "PCIe link lost, device now detached\n");
761 }
762
763 return value;
764 }
765
766 /**
767 * igb_write_ivar - configure ivar for given MSI-X vector
768 * @hw: pointer to the HW structure
769 * @msix_vector: vector number we are allocating to a given ring
770 * @index: row index of IVAR register to write within IVAR table
771 * @offset: column offset of in IVAR, should be multiple of 8
772 *
773 * This function is intended to handle the writing of the IVAR register
774 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
775 * each containing an cause allocation for an Rx and Tx ring, and a
776 * variable number of rows depending on the number of queues supported.
777 **/
778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
779 int index, int offset)
780 {
781 u32 ivar = array_rd32(E1000_IVAR0, index);
782
783 /* clear any bits that are currently set */
784 ivar &= ~((u32)0xFF << offset);
785
786 /* write vector and valid bit */
787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
788
789 array_wr32(E1000_IVAR0, index, ivar);
790 }
791
792 #define IGB_N0_QUEUE -1
793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
794 {
795 struct igb_adapter *adapter = q_vector->adapter;
796 struct e1000_hw *hw = &adapter->hw;
797 int rx_queue = IGB_N0_QUEUE;
798 int tx_queue = IGB_N0_QUEUE;
799 u32 msixbm = 0;
800
801 if (q_vector->rx.ring)
802 rx_queue = q_vector->rx.ring->reg_idx;
803 if (q_vector->tx.ring)
804 tx_queue = q_vector->tx.ring->reg_idx;
805
806 switch (hw->mac.type) {
807 case e1000_82575:
808 /* The 82575 assigns vectors using a bitmask, which matches the
809 * bitmask for the EICR/EIMS/EIMC registers. To assign one
810 * or more queues to a vector, we write the appropriate bits
811 * into the MSIXBM register for that vector.
812 */
813 if (rx_queue > IGB_N0_QUEUE)
814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
815 if (tx_queue > IGB_N0_QUEUE)
816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
818 msixbm |= E1000_EIMS_OTHER;
819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
820 q_vector->eims_value = msixbm;
821 break;
822 case e1000_82576:
823 /* 82576 uses a table that essentially consists of 2 columns
824 * with 8 rows. The ordering is column-major so we use the
825 * lower 3 bits as the row index, and the 4th bit as the
826 * column offset.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue & 0x7,
831 (rx_queue & 0x8) << 1);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue & 0x7,
835 ((tx_queue & 0x8) << 1) + 8);
836 q_vector->eims_value = 1 << msix_vector;
837 break;
838 case e1000_82580:
839 case e1000_i350:
840 case e1000_i354:
841 case e1000_i210:
842 case e1000_i211:
843 /* On 82580 and newer adapters the scheme is similar to 82576
844 * however instead of ordering column-major we have things
845 * ordered row-major. So we traverse the table by using
846 * bit 0 as the column offset, and the remaining bits as the
847 * row index.
848 */
849 if (rx_queue > IGB_N0_QUEUE)
850 igb_write_ivar(hw, msix_vector,
851 rx_queue >> 1,
852 (rx_queue & 0x1) << 4);
853 if (tx_queue > IGB_N0_QUEUE)
854 igb_write_ivar(hw, msix_vector,
855 tx_queue >> 1,
856 ((tx_queue & 0x1) << 4) + 8);
857 q_vector->eims_value = 1 << msix_vector;
858 break;
859 default:
860 BUG();
861 break;
862 }
863
864 /* add q_vector eims value to global eims_enable_mask */
865 adapter->eims_enable_mask |= q_vector->eims_value;
866
867 /* configure q_vector to set itr on first interrupt */
868 q_vector->set_itr = 1;
869 }
870
871 /**
872 * igb_configure_msix - Configure MSI-X hardware
873 * @adapter: board private structure to initialize
874 *
875 * igb_configure_msix sets up the hardware to properly
876 * generate MSI-X interrupts.
877 **/
878 static void igb_configure_msix(struct igb_adapter *adapter)
879 {
880 u32 tmp;
881 int i, vector = 0;
882 struct e1000_hw *hw = &adapter->hw;
883
884 adapter->eims_enable_mask = 0;
885
886 /* set vector for other causes, i.e. link changes */
887 switch (hw->mac.type) {
888 case e1000_82575:
889 tmp = rd32(E1000_CTRL_EXT);
890 /* enable MSI-X PBA support*/
891 tmp |= E1000_CTRL_EXT_PBA_CLR;
892
893 /* Auto-Mask interrupts upon ICR read. */
894 tmp |= E1000_CTRL_EXT_EIAME;
895 tmp |= E1000_CTRL_EXT_IRCA;
896
897 wr32(E1000_CTRL_EXT, tmp);
898
899 /* enable msix_other interrupt */
900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
901 adapter->eims_other = E1000_EIMS_OTHER;
902
903 break;
904
905 case e1000_82576:
906 case e1000_82580:
907 case e1000_i350:
908 case e1000_i354:
909 case e1000_i210:
910 case e1000_i211:
911 /* Turn on MSI-X capability first, or our settings
912 * won't stick. And it will take days to debug.
913 */
914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
915 E1000_GPIE_PBA | E1000_GPIE_EIAME |
916 E1000_GPIE_NSICR);
917
918 /* enable msix_other interrupt */
919 adapter->eims_other = 1 << vector;
920 tmp = (vector++ | E1000_IVAR_VALID) << 8;
921
922 wr32(E1000_IVAR_MISC, tmp);
923 break;
924 default:
925 /* do nothing, since nothing else supports MSI-X */
926 break;
927 } /* switch (hw->mac.type) */
928
929 adapter->eims_enable_mask |= adapter->eims_other;
930
931 for (i = 0; i < adapter->num_q_vectors; i++)
932 igb_assign_vector(adapter->q_vector[i], vector++);
933
934 wrfl();
935 }
936
937 /**
938 * igb_request_msix - Initialize MSI-X interrupts
939 * @adapter: board private structure to initialize
940 *
941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
942 * kernel.
943 **/
944 static int igb_request_msix(struct igb_adapter *adapter)
945 {
946 struct net_device *netdev = adapter->netdev;
947 struct e1000_hw *hw = &adapter->hw;
948 int i, err = 0, vector = 0, free_vector = 0;
949
950 err = request_irq(adapter->msix_entries[vector].vector,
951 igb_msix_other, 0, netdev->name, adapter);
952 if (err)
953 goto err_out;
954
955 for (i = 0; i < adapter->num_q_vectors; i++) {
956 struct igb_q_vector *q_vector = adapter->q_vector[i];
957
958 vector++;
959
960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
961
962 if (q_vector->rx.ring && q_vector->tx.ring)
963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
964 q_vector->rx.ring->queue_index);
965 else if (q_vector->tx.ring)
966 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
967 q_vector->tx.ring->queue_index);
968 else if (q_vector->rx.ring)
969 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
970 q_vector->rx.ring->queue_index);
971 else
972 sprintf(q_vector->name, "%s-unused", netdev->name);
973
974 err = request_irq(adapter->msix_entries[vector].vector,
975 igb_msix_ring, 0, q_vector->name,
976 q_vector);
977 if (err)
978 goto err_free;
979 }
980
981 igb_configure_msix(adapter);
982 return 0;
983
984 err_free:
985 /* free already assigned IRQs */
986 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
987
988 vector--;
989 for (i = 0; i < vector; i++) {
990 free_irq(adapter->msix_entries[free_vector++].vector,
991 adapter->q_vector[i]);
992 }
993 err_out:
994 return err;
995 }
996
997 /**
998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
1001 *
1002 * This function frees the memory allocated to the q_vector.
1003 **/
1004 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005 {
1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007
1008 adapter->q_vector[v_idx] = NULL;
1009
1010 /* igb_get_stats64() might access the rings on this vector,
1011 * we must wait a grace period before freeing it.
1012 */
1013 if (q_vector)
1014 kfree_rcu(q_vector, rcu);
1015 }
1016
1017 /**
1018 * igb_reset_q_vector - Reset config for interrupt vector
1019 * @adapter: board private structure to initialize
1020 * @v_idx: Index of vector to be reset
1021 *
1022 * If NAPI is enabled it will delete any references to the
1023 * NAPI struct. This is preparation for igb_free_q_vector.
1024 **/
1025 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1026 {
1027 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1028
1029 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1030 * allocated. So, q_vector is NULL so we should stop here.
1031 */
1032 if (!q_vector)
1033 return;
1034
1035 if (q_vector->tx.ring)
1036 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1037
1038 if (q_vector->rx.ring)
1039 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1040
1041 netif_napi_del(&q_vector->napi);
1042
1043 }
1044
1045 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1046 {
1047 int v_idx = adapter->num_q_vectors;
1048
1049 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1050 pci_disable_msix(adapter->pdev);
1051 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1052 pci_disable_msi(adapter->pdev);
1053
1054 while (v_idx--)
1055 igb_reset_q_vector(adapter, v_idx);
1056 }
1057
1058 /**
1059 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1060 * @adapter: board private structure to initialize
1061 *
1062 * This function frees the memory allocated to the q_vectors. In addition if
1063 * NAPI is enabled it will delete any references to the NAPI struct prior
1064 * to freeing the q_vector.
1065 **/
1066 static void igb_free_q_vectors(struct igb_adapter *adapter)
1067 {
1068 int v_idx = adapter->num_q_vectors;
1069
1070 adapter->num_tx_queues = 0;
1071 adapter->num_rx_queues = 0;
1072 adapter->num_q_vectors = 0;
1073
1074 while (v_idx--) {
1075 igb_reset_q_vector(adapter, v_idx);
1076 igb_free_q_vector(adapter, v_idx);
1077 }
1078 }
1079
1080 /**
1081 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1082 * @adapter: board private structure to initialize
1083 *
1084 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1085 * MSI-X interrupts allocated.
1086 */
1087 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1088 {
1089 igb_free_q_vectors(adapter);
1090 igb_reset_interrupt_capability(adapter);
1091 }
1092
1093 /**
1094 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1095 * @adapter: board private structure to initialize
1096 * @msix: boolean value of MSIX capability
1097 *
1098 * Attempt to configure interrupts using the best available
1099 * capabilities of the hardware and kernel.
1100 **/
1101 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1102 {
1103 int err;
1104 int numvecs, i;
1105
1106 if (!msix)
1107 goto msi_only;
1108 adapter->flags |= IGB_FLAG_HAS_MSIX;
1109
1110 /* Number of supported queues. */
1111 adapter->num_rx_queues = adapter->rss_queues;
1112 if (adapter->vfs_allocated_count)
1113 adapter->num_tx_queues = 1;
1114 else
1115 adapter->num_tx_queues = adapter->rss_queues;
1116
1117 /* start with one vector for every Rx queue */
1118 numvecs = adapter->num_rx_queues;
1119
1120 /* if Tx handler is separate add 1 for every Tx queue */
1121 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1122 numvecs += adapter->num_tx_queues;
1123
1124 /* store the number of vectors reserved for queues */
1125 adapter->num_q_vectors = numvecs;
1126
1127 /* add 1 vector for link status interrupts */
1128 numvecs++;
1129 for (i = 0; i < numvecs; i++)
1130 adapter->msix_entries[i].entry = i;
1131
1132 err = pci_enable_msix_range(adapter->pdev,
1133 adapter->msix_entries,
1134 numvecs,
1135 numvecs);
1136 if (err > 0)
1137 return;
1138
1139 igb_reset_interrupt_capability(adapter);
1140
1141 /* If we can't do MSI-X, try MSI */
1142 msi_only:
1143 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1144 #ifdef CONFIG_PCI_IOV
1145 /* disable SR-IOV for non MSI-X configurations */
1146 if (adapter->vf_data) {
1147 struct e1000_hw *hw = &adapter->hw;
1148 /* disable iov and allow time for transactions to clear */
1149 pci_disable_sriov(adapter->pdev);
1150 msleep(500);
1151
1152 kfree(adapter->vf_data);
1153 adapter->vf_data = NULL;
1154 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1155 wrfl();
1156 msleep(100);
1157 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1158 }
1159 #endif
1160 adapter->vfs_allocated_count = 0;
1161 adapter->rss_queues = 1;
1162 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1163 adapter->num_rx_queues = 1;
1164 adapter->num_tx_queues = 1;
1165 adapter->num_q_vectors = 1;
1166 if (!pci_enable_msi(adapter->pdev))
1167 adapter->flags |= IGB_FLAG_HAS_MSI;
1168 }
1169
1170 static void igb_add_ring(struct igb_ring *ring,
1171 struct igb_ring_container *head)
1172 {
1173 head->ring = ring;
1174 head->count++;
1175 }
1176
1177 /**
1178 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1179 * @adapter: board private structure to initialize
1180 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1181 * @v_idx: index of vector in adapter struct
1182 * @txr_count: total number of Tx rings to allocate
1183 * @txr_idx: index of first Tx ring to allocate
1184 * @rxr_count: total number of Rx rings to allocate
1185 * @rxr_idx: index of first Rx ring to allocate
1186 *
1187 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1188 **/
1189 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1190 int v_count, int v_idx,
1191 int txr_count, int txr_idx,
1192 int rxr_count, int rxr_idx)
1193 {
1194 struct igb_q_vector *q_vector;
1195 struct igb_ring *ring;
1196 int ring_count, size;
1197
1198 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1199 if (txr_count > 1 || rxr_count > 1)
1200 return -ENOMEM;
1201
1202 ring_count = txr_count + rxr_count;
1203 size = sizeof(struct igb_q_vector) +
1204 (sizeof(struct igb_ring) * ring_count);
1205
1206 /* allocate q_vector and rings */
1207 q_vector = adapter->q_vector[v_idx];
1208 if (!q_vector)
1209 q_vector = kzalloc(size, GFP_KERNEL);
1210 else
1211 memset(q_vector, 0, size);
1212 if (!q_vector)
1213 return -ENOMEM;
1214
1215 /* initialize NAPI */
1216 netif_napi_add(adapter->netdev, &q_vector->napi,
1217 igb_poll, 64);
1218
1219 /* tie q_vector and adapter together */
1220 adapter->q_vector[v_idx] = q_vector;
1221 q_vector->adapter = adapter;
1222
1223 /* initialize work limits */
1224 q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226 /* initialize ITR configuration */
1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1228 q_vector->itr_val = IGB_START_ITR;
1229
1230 /* initialize pointer to rings */
1231 ring = q_vector->ring;
1232
1233 /* intialize ITR */
1234 if (rxr_count) {
1235 /* rx or rx/tx vector */
1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237 q_vector->itr_val = adapter->rx_itr_setting;
1238 } else {
1239 /* tx only vector */
1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241 q_vector->itr_val = adapter->tx_itr_setting;
1242 }
1243
1244 if (txr_count) {
1245 /* assign generic ring traits */
1246 ring->dev = &adapter->pdev->dev;
1247 ring->netdev = adapter->netdev;
1248
1249 /* configure backlink on ring */
1250 ring->q_vector = q_vector;
1251
1252 /* update q_vector Tx values */
1253 igb_add_ring(ring, &q_vector->tx);
1254
1255 /* For 82575, context index must be unique per ring. */
1256 if (adapter->hw.mac.type == e1000_82575)
1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259 /* apply Tx specific ring traits */
1260 ring->count = adapter->tx_ring_count;
1261 ring->queue_index = txr_idx;
1262
1263 u64_stats_init(&ring->tx_syncp);
1264 u64_stats_init(&ring->tx_syncp2);
1265
1266 /* assign ring to adapter */
1267 adapter->tx_ring[txr_idx] = ring;
1268
1269 /* push pointer to next ring */
1270 ring++;
1271 }
1272
1273 if (rxr_count) {
1274 /* assign generic ring traits */
1275 ring->dev = &adapter->pdev->dev;
1276 ring->netdev = adapter->netdev;
1277
1278 /* configure backlink on ring */
1279 ring->q_vector = q_vector;
1280
1281 /* update q_vector Rx values */
1282 igb_add_ring(ring, &q_vector->rx);
1283
1284 /* set flag indicating ring supports SCTP checksum offload */
1285 if (adapter->hw.mac.type >= e1000_82576)
1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1287
1288 /* On i350, i354, i210, and i211, loopback VLAN packets
1289 * have the tag byte-swapped.
1290 */
1291 if (adapter->hw.mac.type >= e1000_i350)
1292 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1293
1294 /* apply Rx specific ring traits */
1295 ring->count = adapter->rx_ring_count;
1296 ring->queue_index = rxr_idx;
1297
1298 u64_stats_init(&ring->rx_syncp);
1299
1300 /* assign ring to adapter */
1301 adapter->rx_ring[rxr_idx] = ring;
1302 }
1303
1304 return 0;
1305 }
1306
1307
1308 /**
1309 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1310 * @adapter: board private structure to initialize
1311 *
1312 * We allocate one q_vector per queue interrupt. If allocation fails we
1313 * return -ENOMEM.
1314 **/
1315 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1316 {
1317 int q_vectors = adapter->num_q_vectors;
1318 int rxr_remaining = adapter->num_rx_queues;
1319 int txr_remaining = adapter->num_tx_queues;
1320 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1321 int err;
1322
1323 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1324 for (; rxr_remaining; v_idx++) {
1325 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1326 0, 0, 1, rxr_idx);
1327
1328 if (err)
1329 goto err_out;
1330
1331 /* update counts and index */
1332 rxr_remaining--;
1333 rxr_idx++;
1334 }
1335 }
1336
1337 for (; v_idx < q_vectors; v_idx++) {
1338 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1339 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1340
1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1342 tqpv, txr_idx, rqpv, rxr_idx);
1343
1344 if (err)
1345 goto err_out;
1346
1347 /* update counts and index */
1348 rxr_remaining -= rqpv;
1349 txr_remaining -= tqpv;
1350 rxr_idx++;
1351 txr_idx++;
1352 }
1353
1354 return 0;
1355
1356 err_out:
1357 adapter->num_tx_queues = 0;
1358 adapter->num_rx_queues = 0;
1359 adapter->num_q_vectors = 0;
1360
1361 while (v_idx--)
1362 igb_free_q_vector(adapter, v_idx);
1363
1364 return -ENOMEM;
1365 }
1366
1367 /**
1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1369 * @adapter: board private structure to initialize
1370 * @msix: boolean value of MSIX capability
1371 *
1372 * This function initializes the interrupts and allocates all of the queues.
1373 **/
1374 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1375 {
1376 struct pci_dev *pdev = adapter->pdev;
1377 int err;
1378
1379 igb_set_interrupt_capability(adapter, msix);
1380
1381 err = igb_alloc_q_vectors(adapter);
1382 if (err) {
1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1384 goto err_alloc_q_vectors;
1385 }
1386
1387 igb_cache_ring_register(adapter);
1388
1389 return 0;
1390
1391 err_alloc_q_vectors:
1392 igb_reset_interrupt_capability(adapter);
1393 return err;
1394 }
1395
1396 /**
1397 * igb_request_irq - initialize interrupts
1398 * @adapter: board private structure to initialize
1399 *
1400 * Attempts to configure interrupts using the best available
1401 * capabilities of the hardware and kernel.
1402 **/
1403 static int igb_request_irq(struct igb_adapter *adapter)
1404 {
1405 struct net_device *netdev = adapter->netdev;
1406 struct pci_dev *pdev = adapter->pdev;
1407 int err = 0;
1408
1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1410 err = igb_request_msix(adapter);
1411 if (!err)
1412 goto request_done;
1413 /* fall back to MSI */
1414 igb_free_all_tx_resources(adapter);
1415 igb_free_all_rx_resources(adapter);
1416
1417 igb_clear_interrupt_scheme(adapter);
1418 err = igb_init_interrupt_scheme(adapter, false);
1419 if (err)
1420 goto request_done;
1421
1422 igb_setup_all_tx_resources(adapter);
1423 igb_setup_all_rx_resources(adapter);
1424 igb_configure(adapter);
1425 }
1426
1427 igb_assign_vector(adapter->q_vector[0], 0);
1428
1429 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1430 err = request_irq(pdev->irq, igb_intr_msi, 0,
1431 netdev->name, adapter);
1432 if (!err)
1433 goto request_done;
1434
1435 /* fall back to legacy interrupts */
1436 igb_reset_interrupt_capability(adapter);
1437 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1438 }
1439
1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1441 netdev->name, adapter);
1442
1443 if (err)
1444 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1445 err);
1446
1447 request_done:
1448 return err;
1449 }
1450
1451 static void igb_free_irq(struct igb_adapter *adapter)
1452 {
1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1454 int vector = 0, i;
1455
1456 free_irq(adapter->msix_entries[vector++].vector, adapter);
1457
1458 for (i = 0; i < adapter->num_q_vectors; i++)
1459 free_irq(adapter->msix_entries[vector++].vector,
1460 adapter->q_vector[i]);
1461 } else {
1462 free_irq(adapter->pdev->irq, adapter);
1463 }
1464 }
1465
1466 /**
1467 * igb_irq_disable - Mask off interrupt generation on the NIC
1468 * @adapter: board private structure
1469 **/
1470 static void igb_irq_disable(struct igb_adapter *adapter)
1471 {
1472 struct e1000_hw *hw = &adapter->hw;
1473
1474 /* we need to be careful when disabling interrupts. The VFs are also
1475 * mapped into these registers and so clearing the bits can cause
1476 * issues on the VF drivers so we only need to clear what we set
1477 */
1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1479 u32 regval = rd32(E1000_EIAM);
1480
1481 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1482 wr32(E1000_EIMC, adapter->eims_enable_mask);
1483 regval = rd32(E1000_EIAC);
1484 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1485 }
1486
1487 wr32(E1000_IAM, 0);
1488 wr32(E1000_IMC, ~0);
1489 wrfl();
1490 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1491 int i;
1492
1493 for (i = 0; i < adapter->num_q_vectors; i++)
1494 synchronize_irq(adapter->msix_entries[i].vector);
1495 } else {
1496 synchronize_irq(adapter->pdev->irq);
1497 }
1498 }
1499
1500 /**
1501 * igb_irq_enable - Enable default interrupt generation settings
1502 * @adapter: board private structure
1503 **/
1504 static void igb_irq_enable(struct igb_adapter *adapter)
1505 {
1506 struct e1000_hw *hw = &adapter->hw;
1507
1508 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1509 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1510 u32 regval = rd32(E1000_EIAC);
1511
1512 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1513 regval = rd32(E1000_EIAM);
1514 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1515 wr32(E1000_EIMS, adapter->eims_enable_mask);
1516 if (adapter->vfs_allocated_count) {
1517 wr32(E1000_MBVFIMR, 0xFF);
1518 ims |= E1000_IMS_VMMB;
1519 }
1520 wr32(E1000_IMS, ims);
1521 } else {
1522 wr32(E1000_IMS, IMS_ENABLE_MASK |
1523 E1000_IMS_DRSTA);
1524 wr32(E1000_IAM, IMS_ENABLE_MASK |
1525 E1000_IMS_DRSTA);
1526 }
1527 }
1528
1529 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1530 {
1531 struct e1000_hw *hw = &adapter->hw;
1532 u16 vid = adapter->hw.mng_cookie.vlan_id;
1533 u16 old_vid = adapter->mng_vlan_id;
1534
1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1536 /* add VID to filter table */
1537 igb_vfta_set(hw, vid, true);
1538 adapter->mng_vlan_id = vid;
1539 } else {
1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1541 }
1542
1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1544 (vid != old_vid) &&
1545 !test_bit(old_vid, adapter->active_vlans)) {
1546 /* remove VID from filter table */
1547 igb_vfta_set(hw, old_vid, false);
1548 }
1549 }
1550
1551 /**
1552 * igb_release_hw_control - release control of the h/w to f/w
1553 * @adapter: address of board private structure
1554 *
1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1556 * For ASF and Pass Through versions of f/w this means that the
1557 * driver is no longer loaded.
1558 **/
1559 static void igb_release_hw_control(struct igb_adapter *adapter)
1560 {
1561 struct e1000_hw *hw = &adapter->hw;
1562 u32 ctrl_ext;
1563
1564 /* Let firmware take over control of h/w */
1565 ctrl_ext = rd32(E1000_CTRL_EXT);
1566 wr32(E1000_CTRL_EXT,
1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1568 }
1569
1570 /**
1571 * igb_get_hw_control - get control of the h/w from f/w
1572 * @adapter: address of board private structure
1573 *
1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1575 * For ASF and Pass Through versions of f/w this means that
1576 * the driver is loaded.
1577 **/
1578 static void igb_get_hw_control(struct igb_adapter *adapter)
1579 {
1580 struct e1000_hw *hw = &adapter->hw;
1581 u32 ctrl_ext;
1582
1583 /* Let firmware know the driver has taken over */
1584 ctrl_ext = rd32(E1000_CTRL_EXT);
1585 wr32(E1000_CTRL_EXT,
1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1587 }
1588
1589 /**
1590 * igb_configure - configure the hardware for RX and TX
1591 * @adapter: private board structure
1592 **/
1593 static void igb_configure(struct igb_adapter *adapter)
1594 {
1595 struct net_device *netdev = adapter->netdev;
1596 int i;
1597
1598 igb_get_hw_control(adapter);
1599 igb_set_rx_mode(netdev);
1600
1601 igb_restore_vlan(adapter);
1602
1603 igb_setup_tctl(adapter);
1604 igb_setup_mrqc(adapter);
1605 igb_setup_rctl(adapter);
1606
1607 igb_configure_tx(adapter);
1608 igb_configure_rx(adapter);
1609
1610 igb_rx_fifo_flush_82575(&adapter->hw);
1611
1612 /* call igb_desc_unused which always leaves
1613 * at least 1 descriptor unused to make sure
1614 * next_to_use != next_to_clean
1615 */
1616 for (i = 0; i < adapter->num_rx_queues; i++) {
1617 struct igb_ring *ring = adapter->rx_ring[i];
1618 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1619 }
1620 }
1621
1622 /**
1623 * igb_power_up_link - Power up the phy/serdes link
1624 * @adapter: address of board private structure
1625 **/
1626 void igb_power_up_link(struct igb_adapter *adapter)
1627 {
1628 igb_reset_phy(&adapter->hw);
1629
1630 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1631 igb_power_up_phy_copper(&adapter->hw);
1632 else
1633 igb_power_up_serdes_link_82575(&adapter->hw);
1634
1635 igb_setup_link(&adapter->hw);
1636 }
1637
1638 /**
1639 * igb_power_down_link - Power down the phy/serdes link
1640 * @adapter: address of board private structure
1641 */
1642 static void igb_power_down_link(struct igb_adapter *adapter)
1643 {
1644 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1645 igb_power_down_phy_copper_82575(&adapter->hw);
1646 else
1647 igb_shutdown_serdes_link_82575(&adapter->hw);
1648 }
1649
1650 /**
1651 * Detect and switch function for Media Auto Sense
1652 * @adapter: address of the board private structure
1653 **/
1654 static void igb_check_swap_media(struct igb_adapter *adapter)
1655 {
1656 struct e1000_hw *hw = &adapter->hw;
1657 u32 ctrl_ext, connsw;
1658 bool swap_now = false;
1659
1660 ctrl_ext = rd32(E1000_CTRL_EXT);
1661 connsw = rd32(E1000_CONNSW);
1662
1663 /* need to live swap if current media is copper and we have fiber/serdes
1664 * to go to.
1665 */
1666
1667 if ((hw->phy.media_type == e1000_media_type_copper) &&
1668 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1669 swap_now = true;
1670 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1671 /* copper signal takes time to appear */
1672 if (adapter->copper_tries < 4) {
1673 adapter->copper_tries++;
1674 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1675 wr32(E1000_CONNSW, connsw);
1676 return;
1677 } else {
1678 adapter->copper_tries = 0;
1679 if ((connsw & E1000_CONNSW_PHYSD) &&
1680 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1681 swap_now = true;
1682 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1683 wr32(E1000_CONNSW, connsw);
1684 }
1685 }
1686 }
1687
1688 if (!swap_now)
1689 return;
1690
1691 switch (hw->phy.media_type) {
1692 case e1000_media_type_copper:
1693 netdev_info(adapter->netdev,
1694 "MAS: changing media to fiber/serdes\n");
1695 ctrl_ext |=
1696 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1697 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1698 adapter->copper_tries = 0;
1699 break;
1700 case e1000_media_type_internal_serdes:
1701 case e1000_media_type_fiber:
1702 netdev_info(adapter->netdev,
1703 "MAS: changing media to copper\n");
1704 ctrl_ext &=
1705 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1706 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1707 break;
1708 default:
1709 /* shouldn't get here during regular operation */
1710 netdev_err(adapter->netdev,
1711 "AMS: Invalid media type found, returning\n");
1712 break;
1713 }
1714 wr32(E1000_CTRL_EXT, ctrl_ext);
1715 }
1716
1717 /**
1718 * igb_up - Open the interface and prepare it to handle traffic
1719 * @adapter: board private structure
1720 **/
1721 int igb_up(struct igb_adapter *adapter)
1722 {
1723 struct e1000_hw *hw = &adapter->hw;
1724 int i;
1725
1726 /* hardware has been reset, we need to reload some things */
1727 igb_configure(adapter);
1728
1729 clear_bit(__IGB_DOWN, &adapter->state);
1730
1731 for (i = 0; i < adapter->num_q_vectors; i++)
1732 napi_enable(&(adapter->q_vector[i]->napi));
1733
1734 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1735 igb_configure_msix(adapter);
1736 else
1737 igb_assign_vector(adapter->q_vector[0], 0);
1738
1739 /* Clear any pending interrupts. */
1740 rd32(E1000_ICR);
1741 igb_irq_enable(adapter);
1742
1743 /* notify VFs that reset has been completed */
1744 if (adapter->vfs_allocated_count) {
1745 u32 reg_data = rd32(E1000_CTRL_EXT);
1746
1747 reg_data |= E1000_CTRL_EXT_PFRSTD;
1748 wr32(E1000_CTRL_EXT, reg_data);
1749 }
1750
1751 netif_tx_start_all_queues(adapter->netdev);
1752
1753 /* start the watchdog. */
1754 hw->mac.get_link_status = 1;
1755 schedule_work(&adapter->watchdog_task);
1756
1757 if ((adapter->flags & IGB_FLAG_EEE) &&
1758 (!hw->dev_spec._82575.eee_disable))
1759 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1760
1761 return 0;
1762 }
1763
1764 void igb_down(struct igb_adapter *adapter)
1765 {
1766 struct net_device *netdev = adapter->netdev;
1767 struct e1000_hw *hw = &adapter->hw;
1768 u32 tctl, rctl;
1769 int i;
1770
1771 /* signal that we're down so the interrupt handler does not
1772 * reschedule our watchdog timer
1773 */
1774 set_bit(__IGB_DOWN, &adapter->state);
1775
1776 /* disable receives in the hardware */
1777 rctl = rd32(E1000_RCTL);
1778 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1779 /* flush and sleep below */
1780
1781 netif_carrier_off(netdev);
1782 netif_tx_stop_all_queues(netdev);
1783
1784 /* disable transmits in the hardware */
1785 tctl = rd32(E1000_TCTL);
1786 tctl &= ~E1000_TCTL_EN;
1787 wr32(E1000_TCTL, tctl);
1788 /* flush both disables and wait for them to finish */
1789 wrfl();
1790 usleep_range(10000, 11000);
1791
1792 igb_irq_disable(adapter);
1793
1794 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1795
1796 for (i = 0; i < adapter->num_q_vectors; i++) {
1797 if (adapter->q_vector[i]) {
1798 napi_synchronize(&adapter->q_vector[i]->napi);
1799 napi_disable(&adapter->q_vector[i]->napi);
1800 }
1801 }
1802
1803 del_timer_sync(&adapter->watchdog_timer);
1804 del_timer_sync(&adapter->phy_info_timer);
1805
1806 /* record the stats before reset*/
1807 spin_lock(&adapter->stats64_lock);
1808 igb_update_stats(adapter, &adapter->stats64);
1809 spin_unlock(&adapter->stats64_lock);
1810
1811 adapter->link_speed = 0;
1812 adapter->link_duplex = 0;
1813
1814 if (!pci_channel_offline(adapter->pdev))
1815 igb_reset(adapter);
1816 igb_clean_all_tx_rings(adapter);
1817 igb_clean_all_rx_rings(adapter);
1818 #ifdef CONFIG_IGB_DCA
1819
1820 /* since we reset the hardware DCA settings were cleared */
1821 igb_setup_dca(adapter);
1822 #endif
1823 }
1824
1825 void igb_reinit_locked(struct igb_adapter *adapter)
1826 {
1827 WARN_ON(in_interrupt());
1828 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1829 usleep_range(1000, 2000);
1830 igb_down(adapter);
1831 igb_up(adapter);
1832 clear_bit(__IGB_RESETTING, &adapter->state);
1833 }
1834
1835 /** igb_enable_mas - Media Autosense re-enable after swap
1836 *
1837 * @adapter: adapter struct
1838 **/
1839 static s32 igb_enable_mas(struct igb_adapter *adapter)
1840 {
1841 struct e1000_hw *hw = &adapter->hw;
1842 u32 connsw;
1843 s32 ret_val = 0;
1844
1845 connsw = rd32(E1000_CONNSW);
1846 if (!(hw->phy.media_type == e1000_media_type_copper))
1847 return ret_val;
1848
1849 /* configure for SerDes media detect */
1850 if (!(connsw & E1000_CONNSW_SERDESD)) {
1851 connsw |= E1000_CONNSW_ENRGSRC;
1852 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1853 wr32(E1000_CONNSW, connsw);
1854 wrfl();
1855 } else if (connsw & E1000_CONNSW_SERDESD) {
1856 /* already SerDes, no need to enable anything */
1857 return ret_val;
1858 } else {
1859 netdev_info(adapter->netdev,
1860 "MAS: Unable to configure feature, disabling..\n");
1861 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1862 }
1863 return ret_val;
1864 }
1865
1866 void igb_reset(struct igb_adapter *adapter)
1867 {
1868 struct pci_dev *pdev = adapter->pdev;
1869 struct e1000_hw *hw = &adapter->hw;
1870 struct e1000_mac_info *mac = &hw->mac;
1871 struct e1000_fc_info *fc = &hw->fc;
1872 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1873
1874 /* Repartition Pba for greater than 9k mtu
1875 * To take effect CTRL.RST is required.
1876 */
1877 switch (mac->type) {
1878 case e1000_i350:
1879 case e1000_i354:
1880 case e1000_82580:
1881 pba = rd32(E1000_RXPBS);
1882 pba = igb_rxpbs_adjust_82580(pba);
1883 break;
1884 case e1000_82576:
1885 pba = rd32(E1000_RXPBS);
1886 pba &= E1000_RXPBS_SIZE_MASK_82576;
1887 break;
1888 case e1000_82575:
1889 case e1000_i210:
1890 case e1000_i211:
1891 default:
1892 pba = E1000_PBA_34K;
1893 break;
1894 }
1895
1896 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1897 (mac->type < e1000_82576)) {
1898 /* adjust PBA for jumbo frames */
1899 wr32(E1000_PBA, pba);
1900
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
1906 * expressed in KB.
1907 */
1908 pba = rd32(E1000_PBA);
1909 /* upper 16 bits has Tx packet buffer allocation size in KB */
1910 tx_space = pba >> 16;
1911 /* lower 16 bits has Rx packet buffer allocation size in KB */
1912 pba &= 0xffff;
1913 /* the Tx fifo also stores 16 bytes of information about the Tx
1914 * but don't include ethernet FCS because hardware appends it
1915 */
1916 min_tx_space = (adapter->max_frame_size +
1917 sizeof(union e1000_adv_tx_desc) -
1918 ETH_FCS_LEN) * 2;
1919 min_tx_space = ALIGN(min_tx_space, 1024);
1920 min_tx_space >>= 10;
1921 /* software strips receive CRC, so leave room for it */
1922 min_rx_space = adapter->max_frame_size;
1923 min_rx_space = ALIGN(min_rx_space, 1024);
1924 min_rx_space >>= 10;
1925
1926 /* If current Tx allocation is less than the min Tx FIFO size,
1927 * and the min Tx FIFO size is less than the current Rx FIFO
1928 * allocation, take space away from current Rx allocation
1929 */
1930 if (tx_space < min_tx_space &&
1931 ((min_tx_space - tx_space) < pba)) {
1932 pba = pba - (min_tx_space - tx_space);
1933
1934 /* if short on Rx space, Rx wins and must trump Tx
1935 * adjustment
1936 */
1937 if (pba < min_rx_space)
1938 pba = min_rx_space;
1939 }
1940 wr32(E1000_PBA, pba);
1941 }
1942
1943 /* flow control settings */
1944 /* The high water mark must be low enough to fit one full frame
1945 * (or the size used for early receive) above it in the Rx FIFO.
1946 * Set it to the lower of:
1947 * - 90% of the Rx FIFO size, or
1948 * - the full Rx FIFO size minus one full frame
1949 */
1950 hwm = min(((pba << 10) * 9 / 10),
1951 ((pba << 10) - 2 * adapter->max_frame_size));
1952
1953 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1954 fc->low_water = fc->high_water - 16;
1955 fc->pause_time = 0xFFFF;
1956 fc->send_xon = 1;
1957 fc->current_mode = fc->requested_mode;
1958
1959 /* disable receive for all VFs and wait one second */
1960 if (adapter->vfs_allocated_count) {
1961 int i;
1962
1963 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1964 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1965
1966 /* ping all the active vfs to let them know we are going down */
1967 igb_ping_all_vfs(adapter);
1968
1969 /* disable transmits and receives */
1970 wr32(E1000_VFRE, 0);
1971 wr32(E1000_VFTE, 0);
1972 }
1973
1974 /* Allow time for pending master requests to run */
1975 hw->mac.ops.reset_hw(hw);
1976 wr32(E1000_WUC, 0);
1977
1978 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1979 /* need to resetup here after media swap */
1980 adapter->ei.get_invariants(hw);
1981 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1982 }
1983 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1984 if (igb_enable_mas(adapter))
1985 dev_err(&pdev->dev,
1986 "Error enabling Media Auto Sense\n");
1987 }
1988 if (hw->mac.ops.init_hw(hw))
1989 dev_err(&pdev->dev, "Hardware Error\n");
1990
1991 /* Flow control settings reset on hardware reset, so guarantee flow
1992 * control is off when forcing speed.
1993 */
1994 if (!hw->mac.autoneg)
1995 igb_force_mac_fc(hw);
1996
1997 igb_init_dmac(adapter, pba);
1998 #ifdef CONFIG_IGB_HWMON
1999 /* Re-initialize the thermal sensor on i350 devices. */
2000 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2001 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2002 /* If present, re-initialize the external thermal sensor
2003 * interface.
2004 */
2005 if (adapter->ets)
2006 mac->ops.init_thermal_sensor_thresh(hw);
2007 }
2008 }
2009 #endif
2010 /* Re-establish EEE setting */
2011 if (hw->phy.media_type == e1000_media_type_copper) {
2012 switch (mac->type) {
2013 case e1000_i350:
2014 case e1000_i210:
2015 case e1000_i211:
2016 igb_set_eee_i350(hw, true, true);
2017 break;
2018 case e1000_i354:
2019 igb_set_eee_i354(hw, true, true);
2020 break;
2021 default:
2022 break;
2023 }
2024 }
2025 if (!netif_running(adapter->netdev))
2026 igb_power_down_link(adapter);
2027
2028 igb_update_mng_vlan(adapter);
2029
2030 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2031 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2032
2033 /* Re-enable PTP, where applicable. */
2034 igb_ptp_reset(adapter);
2035
2036 igb_get_phy_info(hw);
2037 }
2038
2039 static netdev_features_t igb_fix_features(struct net_device *netdev,
2040 netdev_features_t features)
2041 {
2042 /* Since there is no support for separate Rx/Tx vlan accel
2043 * enable/disable make sure Tx flag is always in same state as Rx.
2044 */
2045 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2046 features |= NETIF_F_HW_VLAN_CTAG_TX;
2047 else
2048 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2049
2050 return features;
2051 }
2052
2053 static int igb_set_features(struct net_device *netdev,
2054 netdev_features_t features)
2055 {
2056 netdev_features_t changed = netdev->features ^ features;
2057 struct igb_adapter *adapter = netdev_priv(netdev);
2058
2059 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2060 igb_vlan_mode(netdev, features);
2061
2062 if (!(changed & NETIF_F_RXALL))
2063 return 0;
2064
2065 netdev->features = features;
2066
2067 if (netif_running(netdev))
2068 igb_reinit_locked(adapter);
2069 else
2070 igb_reset(adapter);
2071
2072 return 0;
2073 }
2074
2075 static const struct net_device_ops igb_netdev_ops = {
2076 .ndo_open = igb_open,
2077 .ndo_stop = igb_close,
2078 .ndo_start_xmit = igb_xmit_frame,
2079 .ndo_get_stats64 = igb_get_stats64,
2080 .ndo_set_rx_mode = igb_set_rx_mode,
2081 .ndo_set_mac_address = igb_set_mac,
2082 .ndo_change_mtu = igb_change_mtu,
2083 .ndo_do_ioctl = igb_ioctl,
2084 .ndo_tx_timeout = igb_tx_timeout,
2085 .ndo_validate_addr = eth_validate_addr,
2086 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2087 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2088 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2089 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2090 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2091 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2092 .ndo_get_vf_config = igb_ndo_get_vf_config,
2093 #ifdef CONFIG_NET_POLL_CONTROLLER
2094 .ndo_poll_controller = igb_netpoll,
2095 #endif
2096 .ndo_fix_features = igb_fix_features,
2097 .ndo_set_features = igb_set_features,
2098 .ndo_features_check = passthru_features_check,
2099 };
2100
2101 /**
2102 * igb_set_fw_version - Configure version string for ethtool
2103 * @adapter: adapter struct
2104 **/
2105 void igb_set_fw_version(struct igb_adapter *adapter)
2106 {
2107 struct e1000_hw *hw = &adapter->hw;
2108 struct e1000_fw_version fw;
2109
2110 igb_get_fw_version(hw, &fw);
2111
2112 switch (hw->mac.type) {
2113 case e1000_i210:
2114 case e1000_i211:
2115 if (!(igb_get_flash_presence_i210(hw))) {
2116 snprintf(adapter->fw_version,
2117 sizeof(adapter->fw_version),
2118 "%2d.%2d-%d",
2119 fw.invm_major, fw.invm_minor,
2120 fw.invm_img_type);
2121 break;
2122 }
2123 /* fall through */
2124 default:
2125 /* if option is rom valid, display its version too */
2126 if (fw.or_valid) {
2127 snprintf(adapter->fw_version,
2128 sizeof(adapter->fw_version),
2129 "%d.%d, 0x%08x, %d.%d.%d",
2130 fw.eep_major, fw.eep_minor, fw.etrack_id,
2131 fw.or_major, fw.or_build, fw.or_patch);
2132 /* no option rom */
2133 } else if (fw.etrack_id != 0X0000) {
2134 snprintf(adapter->fw_version,
2135 sizeof(adapter->fw_version),
2136 "%d.%d, 0x%08x",
2137 fw.eep_major, fw.eep_minor, fw.etrack_id);
2138 } else {
2139 snprintf(adapter->fw_version,
2140 sizeof(adapter->fw_version),
2141 "%d.%d.%d",
2142 fw.eep_major, fw.eep_minor, fw.eep_build);
2143 }
2144 break;
2145 }
2146 }
2147
2148 /**
2149 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2150 *
2151 * @adapter: adapter struct
2152 **/
2153 static void igb_init_mas(struct igb_adapter *adapter)
2154 {
2155 struct e1000_hw *hw = &adapter->hw;
2156 u16 eeprom_data;
2157
2158 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2159 switch (hw->bus.func) {
2160 case E1000_FUNC_0:
2161 if (eeprom_data & IGB_MAS_ENABLE_0) {
2162 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2163 netdev_info(adapter->netdev,
2164 "MAS: Enabling Media Autosense for port %d\n",
2165 hw->bus.func);
2166 }
2167 break;
2168 case E1000_FUNC_1:
2169 if (eeprom_data & IGB_MAS_ENABLE_1) {
2170 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2171 netdev_info(adapter->netdev,
2172 "MAS: Enabling Media Autosense for port %d\n",
2173 hw->bus.func);
2174 }
2175 break;
2176 case E1000_FUNC_2:
2177 if (eeprom_data & IGB_MAS_ENABLE_2) {
2178 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2179 netdev_info(adapter->netdev,
2180 "MAS: Enabling Media Autosense for port %d\n",
2181 hw->bus.func);
2182 }
2183 break;
2184 case E1000_FUNC_3:
2185 if (eeprom_data & IGB_MAS_ENABLE_3) {
2186 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2187 netdev_info(adapter->netdev,
2188 "MAS: Enabling Media Autosense for port %d\n",
2189 hw->bus.func);
2190 }
2191 break;
2192 default:
2193 /* Shouldn't get here */
2194 netdev_err(adapter->netdev,
2195 "MAS: Invalid port configuration, returning\n");
2196 break;
2197 }
2198 }
2199
2200 /**
2201 * igb_init_i2c - Init I2C interface
2202 * @adapter: pointer to adapter structure
2203 **/
2204 static s32 igb_init_i2c(struct igb_adapter *adapter)
2205 {
2206 s32 status = 0;
2207
2208 /* I2C interface supported on i350 devices */
2209 if (adapter->hw.mac.type != e1000_i350)
2210 return 0;
2211
2212 /* Initialize the i2c bus which is controlled by the registers.
2213 * This bus will use the i2c_algo_bit structue that implements
2214 * the protocol through toggling of the 4 bits in the register.
2215 */
2216 adapter->i2c_adap.owner = THIS_MODULE;
2217 adapter->i2c_algo = igb_i2c_algo;
2218 adapter->i2c_algo.data = adapter;
2219 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2220 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2221 strlcpy(adapter->i2c_adap.name, "igb BB",
2222 sizeof(adapter->i2c_adap.name));
2223 status = i2c_bit_add_bus(&adapter->i2c_adap);
2224 return status;
2225 }
2226
2227 /**
2228 * igb_probe - Device Initialization Routine
2229 * @pdev: PCI device information struct
2230 * @ent: entry in igb_pci_tbl
2231 *
2232 * Returns 0 on success, negative on failure
2233 *
2234 * igb_probe initializes an adapter identified by a pci_dev structure.
2235 * The OS initialization, configuring of the adapter private structure,
2236 * and a hardware reset occur.
2237 **/
2238 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2239 {
2240 struct net_device *netdev;
2241 struct igb_adapter *adapter;
2242 struct e1000_hw *hw;
2243 u16 eeprom_data = 0;
2244 s32 ret_val;
2245 static int global_quad_port_a; /* global quad port a indication */
2246 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2247 int err, pci_using_dac;
2248 u8 part_str[E1000_PBANUM_LENGTH];
2249
2250 /* Catch broken hardware that put the wrong VF device ID in
2251 * the PCIe SR-IOV capability.
2252 */
2253 if (pdev->is_virtfn) {
2254 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2255 pci_name(pdev), pdev->vendor, pdev->device);
2256 return -EINVAL;
2257 }
2258
2259 err = pci_enable_device_mem(pdev);
2260 if (err)
2261 return err;
2262
2263 pci_using_dac = 0;
2264 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2265 if (!err) {
2266 pci_using_dac = 1;
2267 } else {
2268 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2269 if (err) {
2270 dev_err(&pdev->dev,
2271 "No usable DMA configuration, aborting\n");
2272 goto err_dma;
2273 }
2274 }
2275
2276 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2277 IORESOURCE_MEM),
2278 igb_driver_name);
2279 if (err)
2280 goto err_pci_reg;
2281
2282 pci_enable_pcie_error_reporting(pdev);
2283
2284 pci_set_master(pdev);
2285 pci_save_state(pdev);
2286
2287 err = -ENOMEM;
2288 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2289 IGB_MAX_TX_QUEUES);
2290 if (!netdev)
2291 goto err_alloc_etherdev;
2292
2293 SET_NETDEV_DEV(netdev, &pdev->dev);
2294
2295 pci_set_drvdata(pdev, netdev);
2296 adapter = netdev_priv(netdev);
2297 adapter->netdev = netdev;
2298 adapter->pdev = pdev;
2299 hw = &adapter->hw;
2300 hw->back = adapter;
2301 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2302
2303 err = -EIO;
2304 hw->hw_addr = pci_iomap(pdev, 0, 0);
2305 if (!hw->hw_addr)
2306 goto err_ioremap;
2307
2308 netdev->netdev_ops = &igb_netdev_ops;
2309 igb_set_ethtool_ops(netdev);
2310 netdev->watchdog_timeo = 5 * HZ;
2311
2312 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2313
2314 netdev->mem_start = pci_resource_start(pdev, 0);
2315 netdev->mem_end = pci_resource_end(pdev, 0);
2316
2317 /* PCI config space info */
2318 hw->vendor_id = pdev->vendor;
2319 hw->device_id = pdev->device;
2320 hw->revision_id = pdev->revision;
2321 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2322 hw->subsystem_device_id = pdev->subsystem_device;
2323
2324 /* Copy the default MAC, PHY and NVM function pointers */
2325 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2326 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2327 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2328 /* Initialize skew-specific constants */
2329 err = ei->get_invariants(hw);
2330 if (err)
2331 goto err_sw_init;
2332
2333 /* setup the private structure */
2334 err = igb_sw_init(adapter);
2335 if (err)
2336 goto err_sw_init;
2337
2338 igb_get_bus_info_pcie(hw);
2339
2340 hw->phy.autoneg_wait_to_complete = false;
2341
2342 /* Copper options */
2343 if (hw->phy.media_type == e1000_media_type_copper) {
2344 hw->phy.mdix = AUTO_ALL_MODES;
2345 hw->phy.disable_polarity_correction = false;
2346 hw->phy.ms_type = e1000_ms_hw_default;
2347 }
2348
2349 if (igb_check_reset_block(hw))
2350 dev_info(&pdev->dev,
2351 "PHY reset is blocked due to SOL/IDER session.\n");
2352
2353 /* features is initialized to 0 in allocation, it might have bits
2354 * set by igb_sw_init so we should use an or instead of an
2355 * assignment.
2356 */
2357 netdev->features |= NETIF_F_SG |
2358 NETIF_F_IP_CSUM |
2359 NETIF_F_IPV6_CSUM |
2360 NETIF_F_TSO |
2361 NETIF_F_TSO6 |
2362 NETIF_F_RXHASH |
2363 NETIF_F_RXCSUM |
2364 NETIF_F_HW_VLAN_CTAG_RX |
2365 NETIF_F_HW_VLAN_CTAG_TX;
2366
2367 /* copy netdev features into list of user selectable features */
2368 netdev->hw_features |= netdev->features;
2369 netdev->hw_features |= NETIF_F_RXALL;
2370
2371 /* set this bit last since it cannot be part of hw_features */
2372 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2373
2374 netdev->vlan_features |= NETIF_F_TSO |
2375 NETIF_F_TSO6 |
2376 NETIF_F_IP_CSUM |
2377 NETIF_F_IPV6_CSUM |
2378 NETIF_F_SG;
2379
2380 netdev->priv_flags |= IFF_SUPP_NOFCS;
2381
2382 if (pci_using_dac) {
2383 netdev->features |= NETIF_F_HIGHDMA;
2384 netdev->vlan_features |= NETIF_F_HIGHDMA;
2385 }
2386
2387 if (hw->mac.type >= e1000_82576) {
2388 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2389 netdev->features |= NETIF_F_SCTP_CSUM;
2390 }
2391
2392 netdev->priv_flags |= IFF_UNICAST_FLT;
2393
2394 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2395
2396 /* before reading the NVM, reset the controller to put the device in a
2397 * known good starting state
2398 */
2399 hw->mac.ops.reset_hw(hw);
2400
2401 /* make sure the NVM is good , i211/i210 parts can have special NVM
2402 * that doesn't contain a checksum
2403 */
2404 switch (hw->mac.type) {
2405 case e1000_i210:
2406 case e1000_i211:
2407 if (igb_get_flash_presence_i210(hw)) {
2408 if (hw->nvm.ops.validate(hw) < 0) {
2409 dev_err(&pdev->dev,
2410 "The NVM Checksum Is Not Valid\n");
2411 err = -EIO;
2412 goto err_eeprom;
2413 }
2414 }
2415 break;
2416 default:
2417 if (hw->nvm.ops.validate(hw) < 0) {
2418 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2419 err = -EIO;
2420 goto err_eeprom;
2421 }
2422 break;
2423 }
2424
2425 /* copy the MAC address out of the NVM */
2426 if (hw->mac.ops.read_mac_addr(hw))
2427 dev_err(&pdev->dev, "NVM Read Error\n");
2428
2429 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2430
2431 if (!is_valid_ether_addr(netdev->dev_addr)) {
2432 dev_err(&pdev->dev, "Invalid MAC Address\n");
2433 err = -EIO;
2434 goto err_eeprom;
2435 }
2436
2437 /* get firmware version for ethtool -i */
2438 igb_set_fw_version(adapter);
2439
2440 /* configure RXPBSIZE and TXPBSIZE */
2441 if (hw->mac.type == e1000_i210) {
2442 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2443 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2444 }
2445
2446 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2447 (unsigned long) adapter);
2448 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2449 (unsigned long) adapter);
2450
2451 INIT_WORK(&adapter->reset_task, igb_reset_task);
2452 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2453
2454 /* Initialize link properties that are user-changeable */
2455 adapter->fc_autoneg = true;
2456 hw->mac.autoneg = true;
2457 hw->phy.autoneg_advertised = 0x2f;
2458
2459 hw->fc.requested_mode = e1000_fc_default;
2460 hw->fc.current_mode = e1000_fc_default;
2461
2462 igb_validate_mdi_setting(hw);
2463
2464 /* By default, support wake on port A */
2465 if (hw->bus.func == 0)
2466 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2467
2468 /* Check the NVM for wake support on non-port A ports */
2469 if (hw->mac.type >= e1000_82580)
2470 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2471 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2472 &eeprom_data);
2473 else if (hw->bus.func == 1)
2474 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2475
2476 if (eeprom_data & IGB_EEPROM_APME)
2477 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2478
2479 /* now that we have the eeprom settings, apply the special cases where
2480 * the eeprom may be wrong or the board simply won't support wake on
2481 * lan on a particular port
2482 */
2483 switch (pdev->device) {
2484 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2485 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2486 break;
2487 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2488 case E1000_DEV_ID_82576_FIBER:
2489 case E1000_DEV_ID_82576_SERDES:
2490 /* Wake events only supported on port A for dual fiber
2491 * regardless of eeprom setting
2492 */
2493 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2494 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2495 break;
2496 case E1000_DEV_ID_82576_QUAD_COPPER:
2497 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2498 /* if quad port adapter, disable WoL on all but port A */
2499 if (global_quad_port_a != 0)
2500 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2501 else
2502 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2503 /* Reset for multiple quad port adapters */
2504 if (++global_quad_port_a == 4)
2505 global_quad_port_a = 0;
2506 break;
2507 default:
2508 /* If the device can't wake, don't set software support */
2509 if (!device_can_wakeup(&adapter->pdev->dev))
2510 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2511 }
2512
2513 /* initialize the wol settings based on the eeprom settings */
2514 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2515 adapter->wol |= E1000_WUFC_MAG;
2516
2517 /* Some vendors want WoL disabled by default, but still supported */
2518 if ((hw->mac.type == e1000_i350) &&
2519 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2520 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2521 adapter->wol = 0;
2522 }
2523
2524 device_set_wakeup_enable(&adapter->pdev->dev,
2525 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2526
2527 /* reset the hardware with the new settings */
2528 igb_reset(adapter);
2529
2530 /* Init the I2C interface */
2531 err = igb_init_i2c(adapter);
2532 if (err) {
2533 dev_err(&pdev->dev, "failed to init i2c interface\n");
2534 goto err_eeprom;
2535 }
2536
2537 /* let the f/w know that the h/w is now under the control of the
2538 * driver.
2539 */
2540 igb_get_hw_control(adapter);
2541
2542 strcpy(netdev->name, "eth%d");
2543 err = register_netdev(netdev);
2544 if (err)
2545 goto err_register;
2546
2547 /* carrier off reporting is important to ethtool even BEFORE open */
2548 netif_carrier_off(netdev);
2549
2550 #ifdef CONFIG_IGB_DCA
2551 if (dca_add_requester(&pdev->dev) == 0) {
2552 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2553 dev_info(&pdev->dev, "DCA enabled\n");
2554 igb_setup_dca(adapter);
2555 }
2556
2557 #endif
2558 #ifdef CONFIG_IGB_HWMON
2559 /* Initialize the thermal sensor on i350 devices. */
2560 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2561 u16 ets_word;
2562
2563 /* Read the NVM to determine if this i350 device supports an
2564 * external thermal sensor.
2565 */
2566 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2567 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2568 adapter->ets = true;
2569 else
2570 adapter->ets = false;
2571 if (igb_sysfs_init(adapter))
2572 dev_err(&pdev->dev,
2573 "failed to allocate sysfs resources\n");
2574 } else {
2575 adapter->ets = false;
2576 }
2577 #endif
2578 /* Check if Media Autosense is enabled */
2579 adapter->ei = *ei;
2580 if (hw->dev_spec._82575.mas_capable)
2581 igb_init_mas(adapter);
2582
2583 /* do hw tstamp init after resetting */
2584 igb_ptp_init(adapter);
2585
2586 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2587 /* print bus type/speed/width info, not applicable to i354 */
2588 if (hw->mac.type != e1000_i354) {
2589 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2590 netdev->name,
2591 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2592 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2593 "unknown"),
2594 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2595 "Width x4" :
2596 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2597 "Width x2" :
2598 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2599 "Width x1" : "unknown"), netdev->dev_addr);
2600 }
2601
2602 if ((hw->mac.type >= e1000_i210 ||
2603 igb_get_flash_presence_i210(hw))) {
2604 ret_val = igb_read_part_string(hw, part_str,
2605 E1000_PBANUM_LENGTH);
2606 } else {
2607 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2608 }
2609
2610 if (ret_val)
2611 strcpy(part_str, "Unknown");
2612 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2613 dev_info(&pdev->dev,
2614 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2615 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2616 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2617 adapter->num_rx_queues, adapter->num_tx_queues);
2618 if (hw->phy.media_type == e1000_media_type_copper) {
2619 switch (hw->mac.type) {
2620 case e1000_i350:
2621 case e1000_i210:
2622 case e1000_i211:
2623 /* Enable EEE for internal copper PHY devices */
2624 err = igb_set_eee_i350(hw, true, true);
2625 if ((!err) &&
2626 (!hw->dev_spec._82575.eee_disable)) {
2627 adapter->eee_advert =
2628 MDIO_EEE_100TX | MDIO_EEE_1000T;
2629 adapter->flags |= IGB_FLAG_EEE;
2630 }
2631 break;
2632 case e1000_i354:
2633 if ((rd32(E1000_CTRL_EXT) &
2634 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2635 err = igb_set_eee_i354(hw, true, true);
2636 if ((!err) &&
2637 (!hw->dev_spec._82575.eee_disable)) {
2638 adapter->eee_advert =
2639 MDIO_EEE_100TX | MDIO_EEE_1000T;
2640 adapter->flags |= IGB_FLAG_EEE;
2641 }
2642 }
2643 break;
2644 default:
2645 break;
2646 }
2647 }
2648 pm_runtime_put_noidle(&pdev->dev);
2649 return 0;
2650
2651 err_register:
2652 igb_release_hw_control(adapter);
2653 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2654 err_eeprom:
2655 if (!igb_check_reset_block(hw))
2656 igb_reset_phy(hw);
2657
2658 if (hw->flash_address)
2659 iounmap(hw->flash_address);
2660 err_sw_init:
2661 igb_clear_interrupt_scheme(adapter);
2662 pci_iounmap(pdev, hw->hw_addr);
2663 err_ioremap:
2664 free_netdev(netdev);
2665 err_alloc_etherdev:
2666 pci_release_selected_regions(pdev,
2667 pci_select_bars(pdev, IORESOURCE_MEM));
2668 err_pci_reg:
2669 err_dma:
2670 pci_disable_device(pdev);
2671 return err;
2672 }
2673
2674 #ifdef CONFIG_PCI_IOV
2675 static int igb_disable_sriov(struct pci_dev *pdev)
2676 {
2677 struct net_device *netdev = pci_get_drvdata(pdev);
2678 struct igb_adapter *adapter = netdev_priv(netdev);
2679 struct e1000_hw *hw = &adapter->hw;
2680
2681 /* reclaim resources allocated to VFs */
2682 if (adapter->vf_data) {
2683 /* disable iov and allow time for transactions to clear */
2684 if (pci_vfs_assigned(pdev)) {
2685 dev_warn(&pdev->dev,
2686 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2687 return -EPERM;
2688 } else {
2689 pci_disable_sriov(pdev);
2690 msleep(500);
2691 }
2692
2693 kfree(adapter->vf_data);
2694 adapter->vf_data = NULL;
2695 adapter->vfs_allocated_count = 0;
2696 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2697 wrfl();
2698 msleep(100);
2699 dev_info(&pdev->dev, "IOV Disabled\n");
2700
2701 /* Re-enable DMA Coalescing flag since IOV is turned off */
2702 adapter->flags |= IGB_FLAG_DMAC;
2703 }
2704
2705 return 0;
2706 }
2707
2708 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2709 {
2710 struct net_device *netdev = pci_get_drvdata(pdev);
2711 struct igb_adapter *adapter = netdev_priv(netdev);
2712 int old_vfs = pci_num_vf(pdev);
2713 int err = 0;
2714 int i;
2715
2716 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2717 err = -EPERM;
2718 goto out;
2719 }
2720 if (!num_vfs)
2721 goto out;
2722
2723 if (old_vfs) {
2724 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2725 old_vfs, max_vfs);
2726 adapter->vfs_allocated_count = old_vfs;
2727 } else
2728 adapter->vfs_allocated_count = num_vfs;
2729
2730 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2731 sizeof(struct vf_data_storage), GFP_KERNEL);
2732
2733 /* if allocation failed then we do not support SR-IOV */
2734 if (!adapter->vf_data) {
2735 adapter->vfs_allocated_count = 0;
2736 dev_err(&pdev->dev,
2737 "Unable to allocate memory for VF Data Storage\n");
2738 err = -ENOMEM;
2739 goto out;
2740 }
2741
2742 /* only call pci_enable_sriov() if no VFs are allocated already */
2743 if (!old_vfs) {
2744 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2745 if (err)
2746 goto err_out;
2747 }
2748 dev_info(&pdev->dev, "%d VFs allocated\n",
2749 adapter->vfs_allocated_count);
2750 for (i = 0; i < adapter->vfs_allocated_count; i++)
2751 igb_vf_configure(adapter, i);
2752
2753 /* DMA Coalescing is not supported in IOV mode. */
2754 adapter->flags &= ~IGB_FLAG_DMAC;
2755 goto out;
2756
2757 err_out:
2758 kfree(adapter->vf_data);
2759 adapter->vf_data = NULL;
2760 adapter->vfs_allocated_count = 0;
2761 out:
2762 return err;
2763 }
2764
2765 #endif
2766 /**
2767 * igb_remove_i2c - Cleanup I2C interface
2768 * @adapter: pointer to adapter structure
2769 **/
2770 static void igb_remove_i2c(struct igb_adapter *adapter)
2771 {
2772 /* free the adapter bus structure */
2773 i2c_del_adapter(&adapter->i2c_adap);
2774 }
2775
2776 /**
2777 * igb_remove - Device Removal Routine
2778 * @pdev: PCI device information struct
2779 *
2780 * igb_remove is called by the PCI subsystem to alert the driver
2781 * that it should release a PCI device. The could be caused by a
2782 * Hot-Plug event, or because the driver is going to be removed from
2783 * memory.
2784 **/
2785 static void igb_remove(struct pci_dev *pdev)
2786 {
2787 struct net_device *netdev = pci_get_drvdata(pdev);
2788 struct igb_adapter *adapter = netdev_priv(netdev);
2789 struct e1000_hw *hw = &adapter->hw;
2790
2791 pm_runtime_get_noresume(&pdev->dev);
2792 #ifdef CONFIG_IGB_HWMON
2793 igb_sysfs_exit(adapter);
2794 #endif
2795 igb_remove_i2c(adapter);
2796 igb_ptp_stop(adapter);
2797 /* The watchdog timer may be rescheduled, so explicitly
2798 * disable watchdog from being rescheduled.
2799 */
2800 set_bit(__IGB_DOWN, &adapter->state);
2801 del_timer_sync(&adapter->watchdog_timer);
2802 del_timer_sync(&adapter->phy_info_timer);
2803
2804 cancel_work_sync(&adapter->reset_task);
2805 cancel_work_sync(&adapter->watchdog_task);
2806
2807 #ifdef CONFIG_IGB_DCA
2808 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2809 dev_info(&pdev->dev, "DCA disabled\n");
2810 dca_remove_requester(&pdev->dev);
2811 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2812 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2813 }
2814 #endif
2815
2816 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2817 * would have already happened in close and is redundant.
2818 */
2819 igb_release_hw_control(adapter);
2820
2821 unregister_netdev(netdev);
2822
2823 igb_clear_interrupt_scheme(adapter);
2824
2825 #ifdef CONFIG_PCI_IOV
2826 igb_disable_sriov(pdev);
2827 #endif
2828
2829 pci_iounmap(pdev, hw->hw_addr);
2830 if (hw->flash_address)
2831 iounmap(hw->flash_address);
2832 pci_release_selected_regions(pdev,
2833 pci_select_bars(pdev, IORESOURCE_MEM));
2834
2835 kfree(adapter->shadow_vfta);
2836 free_netdev(netdev);
2837
2838 pci_disable_pcie_error_reporting(pdev);
2839
2840 pci_disable_device(pdev);
2841 }
2842
2843 /**
2844 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2845 * @adapter: board private structure to initialize
2846 *
2847 * This function initializes the vf specific data storage and then attempts to
2848 * allocate the VFs. The reason for ordering it this way is because it is much
2849 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2850 * the memory for the VFs.
2851 **/
2852 static void igb_probe_vfs(struct igb_adapter *adapter)
2853 {
2854 #ifdef CONFIG_PCI_IOV
2855 struct pci_dev *pdev = adapter->pdev;
2856 struct e1000_hw *hw = &adapter->hw;
2857
2858 /* Virtualization features not supported on i210 family. */
2859 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2860 return;
2861
2862 pci_sriov_set_totalvfs(pdev, 7);
2863 igb_pci_enable_sriov(pdev, max_vfs);
2864
2865 #endif /* CONFIG_PCI_IOV */
2866 }
2867
2868 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2869 {
2870 struct e1000_hw *hw = &adapter->hw;
2871 u32 max_rss_queues;
2872
2873 /* Determine the maximum number of RSS queues supported. */
2874 switch (hw->mac.type) {
2875 case e1000_i211:
2876 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2877 break;
2878 case e1000_82575:
2879 case e1000_i210:
2880 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2881 break;
2882 case e1000_i350:
2883 /* I350 cannot do RSS and SR-IOV at the same time */
2884 if (!!adapter->vfs_allocated_count) {
2885 max_rss_queues = 1;
2886 break;
2887 }
2888 /* fall through */
2889 case e1000_82576:
2890 if (!!adapter->vfs_allocated_count) {
2891 max_rss_queues = 2;
2892 break;
2893 }
2894 /* fall through */
2895 case e1000_82580:
2896 case e1000_i354:
2897 default:
2898 max_rss_queues = IGB_MAX_RX_QUEUES;
2899 break;
2900 }
2901
2902 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2903
2904 /* Determine if we need to pair queues. */
2905 switch (hw->mac.type) {
2906 case e1000_82575:
2907 case e1000_i211:
2908 /* Device supports enough interrupts without queue pairing. */
2909 break;
2910 case e1000_82576:
2911 /* If VFs are going to be allocated with RSS queues then we
2912 * should pair the queues in order to conserve interrupts due
2913 * to limited supply.
2914 */
2915 if ((adapter->rss_queues > 1) &&
2916 (adapter->vfs_allocated_count > 6))
2917 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2918 /* fall through */
2919 case e1000_82580:
2920 case e1000_i350:
2921 case e1000_i354:
2922 case e1000_i210:
2923 default:
2924 /* If rss_queues > half of max_rss_queues, pair the queues in
2925 * order to conserve interrupts due to limited supply.
2926 */
2927 if (adapter->rss_queues > (max_rss_queues / 2))
2928 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2929 break;
2930 }
2931 }
2932
2933 /**
2934 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2935 * @adapter: board private structure to initialize
2936 *
2937 * igb_sw_init initializes the Adapter private data structure.
2938 * Fields are initialized based on PCI device information and
2939 * OS network device settings (MTU size).
2940 **/
2941 static int igb_sw_init(struct igb_adapter *adapter)
2942 {
2943 struct e1000_hw *hw = &adapter->hw;
2944 struct net_device *netdev = adapter->netdev;
2945 struct pci_dev *pdev = adapter->pdev;
2946
2947 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2948
2949 /* set default ring sizes */
2950 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2951 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2952
2953 /* set default ITR values */
2954 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2955 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2956
2957 /* set default work limits */
2958 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2959
2960 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2961 VLAN_HLEN;
2962 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2963
2964 spin_lock_init(&adapter->stats64_lock);
2965 #ifdef CONFIG_PCI_IOV
2966 switch (hw->mac.type) {
2967 case e1000_82576:
2968 case e1000_i350:
2969 if (max_vfs > 7) {
2970 dev_warn(&pdev->dev,
2971 "Maximum of 7 VFs per PF, using max\n");
2972 max_vfs = adapter->vfs_allocated_count = 7;
2973 } else
2974 adapter->vfs_allocated_count = max_vfs;
2975 if (adapter->vfs_allocated_count)
2976 dev_warn(&pdev->dev,
2977 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2978 break;
2979 default:
2980 break;
2981 }
2982 #endif /* CONFIG_PCI_IOV */
2983
2984 igb_init_queue_configuration(adapter);
2985
2986 /* Setup and initialize a copy of the hw vlan table array */
2987 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2988 GFP_ATOMIC);
2989
2990 /* This call may decrease the number of queues */
2991 if (igb_init_interrupt_scheme(adapter, true)) {
2992 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2993 return -ENOMEM;
2994 }
2995
2996 igb_probe_vfs(adapter);
2997
2998 /* Explicitly disable IRQ since the NIC can be in any state. */
2999 igb_irq_disable(adapter);
3000
3001 if (hw->mac.type >= e1000_i350)
3002 adapter->flags &= ~IGB_FLAG_DMAC;
3003
3004 set_bit(__IGB_DOWN, &adapter->state);
3005 return 0;
3006 }
3007
3008 /**
3009 * igb_open - Called when a network interface is made active
3010 * @netdev: network interface device structure
3011 *
3012 * Returns 0 on success, negative value on failure
3013 *
3014 * The open entry point is called when a network interface is made
3015 * active by the system (IFF_UP). At this point all resources needed
3016 * for transmit and receive operations are allocated, the interrupt
3017 * handler is registered with the OS, the watchdog timer is started,
3018 * and the stack is notified that the interface is ready.
3019 **/
3020 static int __igb_open(struct net_device *netdev, bool resuming)
3021 {
3022 struct igb_adapter *adapter = netdev_priv(netdev);
3023 struct e1000_hw *hw = &adapter->hw;
3024 struct pci_dev *pdev = adapter->pdev;
3025 int err;
3026 int i;
3027
3028 /* disallow open during test */
3029 if (test_bit(__IGB_TESTING, &adapter->state)) {
3030 WARN_ON(resuming);
3031 return -EBUSY;
3032 }
3033
3034 if (!resuming)
3035 pm_runtime_get_sync(&pdev->dev);
3036
3037 netif_carrier_off(netdev);
3038
3039 /* allocate transmit descriptors */
3040 err = igb_setup_all_tx_resources(adapter);
3041 if (err)
3042 goto err_setup_tx;
3043
3044 /* allocate receive descriptors */
3045 err = igb_setup_all_rx_resources(adapter);
3046 if (err)
3047 goto err_setup_rx;
3048
3049 igb_power_up_link(adapter);
3050
3051 /* before we allocate an interrupt, we must be ready to handle it.
3052 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3053 * as soon as we call pci_request_irq, so we have to setup our
3054 * clean_rx handler before we do so.
3055 */
3056 igb_configure(adapter);
3057
3058 err = igb_request_irq(adapter);
3059 if (err)
3060 goto err_req_irq;
3061
3062 /* Notify the stack of the actual queue counts. */
3063 err = netif_set_real_num_tx_queues(adapter->netdev,
3064 adapter->num_tx_queues);
3065 if (err)
3066 goto err_set_queues;
3067
3068 err = netif_set_real_num_rx_queues(adapter->netdev,
3069 adapter->num_rx_queues);
3070 if (err)
3071 goto err_set_queues;
3072
3073 /* From here on the code is the same as igb_up() */
3074 clear_bit(__IGB_DOWN, &adapter->state);
3075
3076 for (i = 0; i < adapter->num_q_vectors; i++)
3077 napi_enable(&(adapter->q_vector[i]->napi));
3078
3079 /* Clear any pending interrupts. */
3080 rd32(E1000_ICR);
3081
3082 igb_irq_enable(adapter);
3083
3084 /* notify VFs that reset has been completed */
3085 if (adapter->vfs_allocated_count) {
3086 u32 reg_data = rd32(E1000_CTRL_EXT);
3087
3088 reg_data |= E1000_CTRL_EXT_PFRSTD;
3089 wr32(E1000_CTRL_EXT, reg_data);
3090 }
3091
3092 netif_tx_start_all_queues(netdev);
3093
3094 if (!resuming)
3095 pm_runtime_put(&pdev->dev);
3096
3097 /* start the watchdog. */
3098 hw->mac.get_link_status = 1;
3099 schedule_work(&adapter->watchdog_task);
3100
3101 return 0;
3102
3103 err_set_queues:
3104 igb_free_irq(adapter);
3105 err_req_irq:
3106 igb_release_hw_control(adapter);
3107 igb_power_down_link(adapter);
3108 igb_free_all_rx_resources(adapter);
3109 err_setup_rx:
3110 igb_free_all_tx_resources(adapter);
3111 err_setup_tx:
3112 igb_reset(adapter);
3113 if (!resuming)
3114 pm_runtime_put(&pdev->dev);
3115
3116 return err;
3117 }
3118
3119 static int igb_open(struct net_device *netdev)
3120 {
3121 return __igb_open(netdev, false);
3122 }
3123
3124 /**
3125 * igb_close - Disables a network interface
3126 * @netdev: network interface device structure
3127 *
3128 * Returns 0, this is not allowed to fail
3129 *
3130 * The close entry point is called when an interface is de-activated
3131 * by the OS. The hardware is still under the driver's control, but
3132 * needs to be disabled. A global MAC reset is issued to stop the
3133 * hardware, and all transmit and receive resources are freed.
3134 **/
3135 static int __igb_close(struct net_device *netdev, bool suspending)
3136 {
3137 struct igb_adapter *adapter = netdev_priv(netdev);
3138 struct pci_dev *pdev = adapter->pdev;
3139
3140 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3141
3142 if (!suspending)
3143 pm_runtime_get_sync(&pdev->dev);
3144
3145 igb_down(adapter);
3146 igb_free_irq(adapter);
3147
3148 igb_free_all_tx_resources(adapter);
3149 igb_free_all_rx_resources(adapter);
3150
3151 if (!suspending)
3152 pm_runtime_put_sync(&pdev->dev);
3153 return 0;
3154 }
3155
3156 static int igb_close(struct net_device *netdev)
3157 {
3158 return __igb_close(netdev, false);
3159 }
3160
3161 /**
3162 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3163 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3164 *
3165 * Return 0 on success, negative on failure
3166 **/
3167 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3168 {
3169 struct device *dev = tx_ring->dev;
3170 int size;
3171
3172 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3173
3174 tx_ring->tx_buffer_info = vzalloc(size);
3175 if (!tx_ring->tx_buffer_info)
3176 goto err;
3177
3178 /* round up to nearest 4K */
3179 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3180 tx_ring->size = ALIGN(tx_ring->size, 4096);
3181
3182 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3183 &tx_ring->dma, GFP_KERNEL);
3184 if (!tx_ring->desc)
3185 goto err;
3186
3187 tx_ring->next_to_use = 0;
3188 tx_ring->next_to_clean = 0;
3189
3190 return 0;
3191
3192 err:
3193 vfree(tx_ring->tx_buffer_info);
3194 tx_ring->tx_buffer_info = NULL;
3195 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3196 return -ENOMEM;
3197 }
3198
3199 /**
3200 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3201 * (Descriptors) for all queues
3202 * @adapter: board private structure
3203 *
3204 * Return 0 on success, negative on failure
3205 **/
3206 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3207 {
3208 struct pci_dev *pdev = adapter->pdev;
3209 int i, err = 0;
3210
3211 for (i = 0; i < adapter->num_tx_queues; i++) {
3212 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3213 if (err) {
3214 dev_err(&pdev->dev,
3215 "Allocation for Tx Queue %u failed\n", i);
3216 for (i--; i >= 0; i--)
3217 igb_free_tx_resources(adapter->tx_ring[i]);
3218 break;
3219 }
3220 }
3221
3222 return err;
3223 }
3224
3225 /**
3226 * igb_setup_tctl - configure the transmit control registers
3227 * @adapter: Board private structure
3228 **/
3229 void igb_setup_tctl(struct igb_adapter *adapter)
3230 {
3231 struct e1000_hw *hw = &adapter->hw;
3232 u32 tctl;
3233
3234 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3235 wr32(E1000_TXDCTL(0), 0);
3236
3237 /* Program the Transmit Control Register */
3238 tctl = rd32(E1000_TCTL);
3239 tctl &= ~E1000_TCTL_CT;
3240 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3241 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3242
3243 igb_config_collision_dist(hw);
3244
3245 /* Enable transmits */
3246 tctl |= E1000_TCTL_EN;
3247
3248 wr32(E1000_TCTL, tctl);
3249 }
3250
3251 /**
3252 * igb_configure_tx_ring - Configure transmit ring after Reset
3253 * @adapter: board private structure
3254 * @ring: tx ring to configure
3255 *
3256 * Configure a transmit ring after a reset.
3257 **/
3258 void igb_configure_tx_ring(struct igb_adapter *adapter,
3259 struct igb_ring *ring)
3260 {
3261 struct e1000_hw *hw = &adapter->hw;
3262 u32 txdctl = 0;
3263 u64 tdba = ring->dma;
3264 int reg_idx = ring->reg_idx;
3265
3266 /* disable the queue */
3267 wr32(E1000_TXDCTL(reg_idx), 0);
3268 wrfl();
3269 mdelay(10);
3270
3271 wr32(E1000_TDLEN(reg_idx),
3272 ring->count * sizeof(union e1000_adv_tx_desc));
3273 wr32(E1000_TDBAL(reg_idx),
3274 tdba & 0x00000000ffffffffULL);
3275 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3276
3277 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3278 wr32(E1000_TDH(reg_idx), 0);
3279 writel(0, ring->tail);
3280
3281 txdctl |= IGB_TX_PTHRESH;
3282 txdctl |= IGB_TX_HTHRESH << 8;
3283 txdctl |= IGB_TX_WTHRESH << 16;
3284
3285 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3286 wr32(E1000_TXDCTL(reg_idx), txdctl);
3287 }
3288
3289 /**
3290 * igb_configure_tx - Configure transmit Unit after Reset
3291 * @adapter: board private structure
3292 *
3293 * Configure the Tx unit of the MAC after a reset.
3294 **/
3295 static void igb_configure_tx(struct igb_adapter *adapter)
3296 {
3297 int i;
3298
3299 for (i = 0; i < adapter->num_tx_queues; i++)
3300 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3301 }
3302
3303 /**
3304 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3305 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3306 *
3307 * Returns 0 on success, negative on failure
3308 **/
3309 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3310 {
3311 struct device *dev = rx_ring->dev;
3312 int size;
3313
3314 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3315
3316 rx_ring->rx_buffer_info = vzalloc(size);
3317 if (!rx_ring->rx_buffer_info)
3318 goto err;
3319
3320 /* Round up to nearest 4K */
3321 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3322 rx_ring->size = ALIGN(rx_ring->size, 4096);
3323
3324 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3325 &rx_ring->dma, GFP_KERNEL);
3326 if (!rx_ring->desc)
3327 goto err;
3328
3329 rx_ring->next_to_alloc = 0;
3330 rx_ring->next_to_clean = 0;
3331 rx_ring->next_to_use = 0;
3332
3333 return 0;
3334
3335 err:
3336 vfree(rx_ring->rx_buffer_info);
3337 rx_ring->rx_buffer_info = NULL;
3338 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3339 return -ENOMEM;
3340 }
3341
3342 /**
3343 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3344 * (Descriptors) for all queues
3345 * @adapter: board private structure
3346 *
3347 * Return 0 on success, negative on failure
3348 **/
3349 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3350 {
3351 struct pci_dev *pdev = adapter->pdev;
3352 int i, err = 0;
3353
3354 for (i = 0; i < adapter->num_rx_queues; i++) {
3355 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3356 if (err) {
3357 dev_err(&pdev->dev,
3358 "Allocation for Rx Queue %u failed\n", i);
3359 for (i--; i >= 0; i--)
3360 igb_free_rx_resources(adapter->rx_ring[i]);
3361 break;
3362 }
3363 }
3364
3365 return err;
3366 }
3367
3368 /**
3369 * igb_setup_mrqc - configure the multiple receive queue control registers
3370 * @adapter: Board private structure
3371 **/
3372 static void igb_setup_mrqc(struct igb_adapter *adapter)
3373 {
3374 struct e1000_hw *hw = &adapter->hw;
3375 u32 mrqc, rxcsum;
3376 u32 j, num_rx_queues;
3377 u32 rss_key[10];
3378
3379 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3380 for (j = 0; j < 10; j++)
3381 wr32(E1000_RSSRK(j), rss_key[j]);
3382
3383 num_rx_queues = adapter->rss_queues;
3384
3385 switch (hw->mac.type) {
3386 case e1000_82576:
3387 /* 82576 supports 2 RSS queues for SR-IOV */
3388 if (adapter->vfs_allocated_count)
3389 num_rx_queues = 2;
3390 break;
3391 default:
3392 break;
3393 }
3394
3395 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3396 for (j = 0; j < IGB_RETA_SIZE; j++)
3397 adapter->rss_indir_tbl[j] =
3398 (j * num_rx_queues) / IGB_RETA_SIZE;
3399 adapter->rss_indir_tbl_init = num_rx_queues;
3400 }
3401 igb_write_rss_indir_tbl(adapter);
3402
3403 /* Disable raw packet checksumming so that RSS hash is placed in
3404 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3405 * offloads as they are enabled by default
3406 */
3407 rxcsum = rd32(E1000_RXCSUM);
3408 rxcsum |= E1000_RXCSUM_PCSD;
3409
3410 if (adapter->hw.mac.type >= e1000_82576)
3411 /* Enable Receive Checksum Offload for SCTP */
3412 rxcsum |= E1000_RXCSUM_CRCOFL;
3413
3414 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3415 wr32(E1000_RXCSUM, rxcsum);
3416
3417 /* Generate RSS hash based on packet types, TCP/UDP
3418 * port numbers and/or IPv4/v6 src and dst addresses
3419 */
3420 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3421 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3422 E1000_MRQC_RSS_FIELD_IPV6 |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3425
3426 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3427 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3428 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3429 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3430
3431 /* If VMDq is enabled then we set the appropriate mode for that, else
3432 * we default to RSS so that an RSS hash is calculated per packet even
3433 * if we are only using one queue
3434 */
3435 if (adapter->vfs_allocated_count) {
3436 if (hw->mac.type > e1000_82575) {
3437 /* Set the default pool for the PF's first queue */
3438 u32 vtctl = rd32(E1000_VT_CTL);
3439
3440 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3441 E1000_VT_CTL_DISABLE_DEF_POOL);
3442 vtctl |= adapter->vfs_allocated_count <<
3443 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3444 wr32(E1000_VT_CTL, vtctl);
3445 }
3446 if (adapter->rss_queues > 1)
3447 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3448 else
3449 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3450 } else {
3451 if (hw->mac.type != e1000_i211)
3452 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3453 }
3454 igb_vmm_control(adapter);
3455
3456 wr32(E1000_MRQC, mrqc);
3457 }
3458
3459 /**
3460 * igb_setup_rctl - configure the receive control registers
3461 * @adapter: Board private structure
3462 **/
3463 void igb_setup_rctl(struct igb_adapter *adapter)
3464 {
3465 struct e1000_hw *hw = &adapter->hw;
3466 u32 rctl;
3467
3468 rctl = rd32(E1000_RCTL);
3469
3470 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3471 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3472
3473 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3474 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3475
3476 /* enable stripping of CRC. It's unlikely this will break BMC
3477 * redirection as it did with e1000. Newer features require
3478 * that the HW strips the CRC.
3479 */
3480 rctl |= E1000_RCTL_SECRC;
3481
3482 /* disable store bad packets and clear size bits. */
3483 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3484
3485 /* enable LPE to prevent packets larger than max_frame_size */
3486 rctl |= E1000_RCTL_LPE;
3487
3488 /* disable queue 0 to prevent tail write w/o re-config */
3489 wr32(E1000_RXDCTL(0), 0);
3490
3491 /* Attention!!! For SR-IOV PF driver operations you must enable
3492 * queue drop for all VF and PF queues to prevent head of line blocking
3493 * if an un-trusted VF does not provide descriptors to hardware.
3494 */
3495 if (adapter->vfs_allocated_count) {
3496 /* set all queue drop enable bits */
3497 wr32(E1000_QDE, ALL_QUEUES);
3498 }
3499
3500 /* This is useful for sniffing bad packets. */
3501 if (adapter->netdev->features & NETIF_F_RXALL) {
3502 /* UPE and MPE will be handled by normal PROMISC logic
3503 * in e1000e_set_rx_mode
3504 */
3505 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3506 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3507 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3508
3509 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3510 E1000_RCTL_DPF | /* Allow filtered pause */
3511 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3512 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3513 * and that breaks VLANs.
3514 */
3515 }
3516
3517 wr32(E1000_RCTL, rctl);
3518 }
3519
3520 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3521 int vfn)
3522 {
3523 struct e1000_hw *hw = &adapter->hw;
3524 u32 vmolr;
3525
3526 /* if it isn't the PF check to see if VFs are enabled and
3527 * increase the size to support vlan tags
3528 */
3529 if (vfn < adapter->vfs_allocated_count &&
3530 adapter->vf_data[vfn].vlans_enabled)
3531 size += VLAN_TAG_SIZE;
3532
3533 vmolr = rd32(E1000_VMOLR(vfn));
3534 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3535 vmolr |= size | E1000_VMOLR_LPE;
3536 wr32(E1000_VMOLR(vfn), vmolr);
3537
3538 return 0;
3539 }
3540
3541 /**
3542 * igb_rlpml_set - set maximum receive packet size
3543 * @adapter: board private structure
3544 *
3545 * Configure maximum receivable packet size.
3546 **/
3547 static void igb_rlpml_set(struct igb_adapter *adapter)
3548 {
3549 u32 max_frame_size = adapter->max_frame_size;
3550 struct e1000_hw *hw = &adapter->hw;
3551 u16 pf_id = adapter->vfs_allocated_count;
3552
3553 if (pf_id) {
3554 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3555 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3556 * to our max jumbo frame size, in case we need to enable
3557 * jumbo frames on one of the rings later.
3558 * This will not pass over-length frames into the default
3559 * queue because it's gated by the VMOLR.RLPML.
3560 */
3561 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3562 }
3563
3564 wr32(E1000_RLPML, max_frame_size);
3565 }
3566
3567 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3568 int vfn, bool aupe)
3569 {
3570 struct e1000_hw *hw = &adapter->hw;
3571 u32 vmolr;
3572
3573 /* This register exists only on 82576 and newer so if we are older then
3574 * we should exit and do nothing
3575 */
3576 if (hw->mac.type < e1000_82576)
3577 return;
3578
3579 vmolr = rd32(E1000_VMOLR(vfn));
3580 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3581 if (hw->mac.type == e1000_i350) {
3582 u32 dvmolr;
3583
3584 dvmolr = rd32(E1000_DVMOLR(vfn));
3585 dvmolr |= E1000_DVMOLR_STRVLAN;
3586 wr32(E1000_DVMOLR(vfn), dvmolr);
3587 }
3588 if (aupe)
3589 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3590 else
3591 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3592
3593 /* clear all bits that might not be set */
3594 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3595
3596 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3597 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3598 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3599 * multicast packets
3600 */
3601 if (vfn <= adapter->vfs_allocated_count)
3602 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3603
3604 wr32(E1000_VMOLR(vfn), vmolr);
3605 }
3606
3607 /**
3608 * igb_configure_rx_ring - Configure a receive ring after Reset
3609 * @adapter: board private structure
3610 * @ring: receive ring to be configured
3611 *
3612 * Configure the Rx unit of the MAC after a reset.
3613 **/
3614 void igb_configure_rx_ring(struct igb_adapter *adapter,
3615 struct igb_ring *ring)
3616 {
3617 struct e1000_hw *hw = &adapter->hw;
3618 u64 rdba = ring->dma;
3619 int reg_idx = ring->reg_idx;
3620 u32 srrctl = 0, rxdctl = 0;
3621
3622 /* disable the queue */
3623 wr32(E1000_RXDCTL(reg_idx), 0);
3624
3625 /* Set DMA base address registers */
3626 wr32(E1000_RDBAL(reg_idx),
3627 rdba & 0x00000000ffffffffULL);
3628 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3629 wr32(E1000_RDLEN(reg_idx),
3630 ring->count * sizeof(union e1000_adv_rx_desc));
3631
3632 /* initialize head and tail */
3633 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3634 wr32(E1000_RDH(reg_idx), 0);
3635 writel(0, ring->tail);
3636
3637 /* set descriptor configuration */
3638 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3639 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3640 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3641 if (hw->mac.type >= e1000_82580)
3642 srrctl |= E1000_SRRCTL_TIMESTAMP;
3643 /* Only set Drop Enable if we are supporting multiple queues */
3644 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3645 srrctl |= E1000_SRRCTL_DROP_EN;
3646
3647 wr32(E1000_SRRCTL(reg_idx), srrctl);
3648
3649 /* set filtering for VMDQ pools */
3650 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3651
3652 rxdctl |= IGB_RX_PTHRESH;
3653 rxdctl |= IGB_RX_HTHRESH << 8;
3654 rxdctl |= IGB_RX_WTHRESH << 16;
3655
3656 /* enable receive descriptor fetching */
3657 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3658 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3659 }
3660
3661 /**
3662 * igb_configure_rx - Configure receive Unit after Reset
3663 * @adapter: board private structure
3664 *
3665 * Configure the Rx unit of the MAC after a reset.
3666 **/
3667 static void igb_configure_rx(struct igb_adapter *adapter)
3668 {
3669 int i;
3670
3671 /* set UTA to appropriate mode */
3672 igb_set_uta(adapter);
3673
3674 /* set the correct pool for the PF default MAC address in entry 0 */
3675 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3676 adapter->vfs_allocated_count);
3677
3678 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3679 * the Base and Length of the Rx Descriptor Ring
3680 */
3681 for (i = 0; i < adapter->num_rx_queues; i++)
3682 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3683 }
3684
3685 /**
3686 * igb_free_tx_resources - Free Tx Resources per Queue
3687 * @tx_ring: Tx descriptor ring for a specific queue
3688 *
3689 * Free all transmit software resources
3690 **/
3691 void igb_free_tx_resources(struct igb_ring *tx_ring)
3692 {
3693 igb_clean_tx_ring(tx_ring);
3694
3695 vfree(tx_ring->tx_buffer_info);
3696 tx_ring->tx_buffer_info = NULL;
3697
3698 /* if not set, then don't free */
3699 if (!tx_ring->desc)
3700 return;
3701
3702 dma_free_coherent(tx_ring->dev, tx_ring->size,
3703 tx_ring->desc, tx_ring->dma);
3704
3705 tx_ring->desc = NULL;
3706 }
3707
3708 /**
3709 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3710 * @adapter: board private structure
3711 *
3712 * Free all transmit software resources
3713 **/
3714 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3715 {
3716 int i;
3717
3718 for (i = 0; i < adapter->num_tx_queues; i++)
3719 if (adapter->tx_ring[i])
3720 igb_free_tx_resources(adapter->tx_ring[i]);
3721 }
3722
3723 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3724 struct igb_tx_buffer *tx_buffer)
3725 {
3726 if (tx_buffer->skb) {
3727 dev_kfree_skb_any(tx_buffer->skb);
3728 if (dma_unmap_len(tx_buffer, len))
3729 dma_unmap_single(ring->dev,
3730 dma_unmap_addr(tx_buffer, dma),
3731 dma_unmap_len(tx_buffer, len),
3732 DMA_TO_DEVICE);
3733 } else if (dma_unmap_len(tx_buffer, len)) {
3734 dma_unmap_page(ring->dev,
3735 dma_unmap_addr(tx_buffer, dma),
3736 dma_unmap_len(tx_buffer, len),
3737 DMA_TO_DEVICE);
3738 }
3739 tx_buffer->next_to_watch = NULL;
3740 tx_buffer->skb = NULL;
3741 dma_unmap_len_set(tx_buffer, len, 0);
3742 /* buffer_info must be completely set up in the transmit path */
3743 }
3744
3745 /**
3746 * igb_clean_tx_ring - Free Tx Buffers
3747 * @tx_ring: ring to be cleaned
3748 **/
3749 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3750 {
3751 struct igb_tx_buffer *buffer_info;
3752 unsigned long size;
3753 u16 i;
3754
3755 if (!tx_ring->tx_buffer_info)
3756 return;
3757 /* Free all the Tx ring sk_buffs */
3758
3759 for (i = 0; i < tx_ring->count; i++) {
3760 buffer_info = &tx_ring->tx_buffer_info[i];
3761 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3762 }
3763
3764 netdev_tx_reset_queue(txring_txq(tx_ring));
3765
3766 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3767 memset(tx_ring->tx_buffer_info, 0, size);
3768
3769 /* Zero out the descriptor ring */
3770 memset(tx_ring->desc, 0, tx_ring->size);
3771
3772 tx_ring->next_to_use = 0;
3773 tx_ring->next_to_clean = 0;
3774 }
3775
3776 /**
3777 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3778 * @adapter: board private structure
3779 **/
3780 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3781 {
3782 int i;
3783
3784 for (i = 0; i < adapter->num_tx_queues; i++)
3785 if (adapter->tx_ring[i])
3786 igb_clean_tx_ring(adapter->tx_ring[i]);
3787 }
3788
3789 /**
3790 * igb_free_rx_resources - Free Rx Resources
3791 * @rx_ring: ring to clean the resources from
3792 *
3793 * Free all receive software resources
3794 **/
3795 void igb_free_rx_resources(struct igb_ring *rx_ring)
3796 {
3797 igb_clean_rx_ring(rx_ring);
3798
3799 vfree(rx_ring->rx_buffer_info);
3800 rx_ring->rx_buffer_info = NULL;
3801
3802 /* if not set, then don't free */
3803 if (!rx_ring->desc)
3804 return;
3805
3806 dma_free_coherent(rx_ring->dev, rx_ring->size,
3807 rx_ring->desc, rx_ring->dma);
3808
3809 rx_ring->desc = NULL;
3810 }
3811
3812 /**
3813 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3814 * @adapter: board private structure
3815 *
3816 * Free all receive software resources
3817 **/
3818 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3819 {
3820 int i;
3821
3822 for (i = 0; i < adapter->num_rx_queues; i++)
3823 if (adapter->rx_ring[i])
3824 igb_free_rx_resources(adapter->rx_ring[i]);
3825 }
3826
3827 /**
3828 * igb_clean_rx_ring - Free Rx Buffers per Queue
3829 * @rx_ring: ring to free buffers from
3830 **/
3831 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3832 {
3833 unsigned long size;
3834 u16 i;
3835
3836 if (rx_ring->skb)
3837 dev_kfree_skb(rx_ring->skb);
3838 rx_ring->skb = NULL;
3839
3840 if (!rx_ring->rx_buffer_info)
3841 return;
3842
3843 /* Free all the Rx ring sk_buffs */
3844 for (i = 0; i < rx_ring->count; i++) {
3845 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3846
3847 if (!buffer_info->page)
3848 continue;
3849
3850 dma_unmap_page(rx_ring->dev,
3851 buffer_info->dma,
3852 PAGE_SIZE,
3853 DMA_FROM_DEVICE);
3854 __free_page(buffer_info->page);
3855
3856 buffer_info->page = NULL;
3857 }
3858
3859 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3860 memset(rx_ring->rx_buffer_info, 0, size);
3861
3862 /* Zero out the descriptor ring */
3863 memset(rx_ring->desc, 0, rx_ring->size);
3864
3865 rx_ring->next_to_alloc = 0;
3866 rx_ring->next_to_clean = 0;
3867 rx_ring->next_to_use = 0;
3868 }
3869
3870 /**
3871 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3872 * @adapter: board private structure
3873 **/
3874 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3875 {
3876 int i;
3877
3878 for (i = 0; i < adapter->num_rx_queues; i++)
3879 if (adapter->rx_ring[i])
3880 igb_clean_rx_ring(adapter->rx_ring[i]);
3881 }
3882
3883 /**
3884 * igb_set_mac - Change the Ethernet Address of the NIC
3885 * @netdev: network interface device structure
3886 * @p: pointer to an address structure
3887 *
3888 * Returns 0 on success, negative on failure
3889 **/
3890 static int igb_set_mac(struct net_device *netdev, void *p)
3891 {
3892 struct igb_adapter *adapter = netdev_priv(netdev);
3893 struct e1000_hw *hw = &adapter->hw;
3894 struct sockaddr *addr = p;
3895
3896 if (!is_valid_ether_addr(addr->sa_data))
3897 return -EADDRNOTAVAIL;
3898
3899 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3900 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3901
3902 /* set the correct pool for the new PF MAC address in entry 0 */
3903 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3904 adapter->vfs_allocated_count);
3905
3906 return 0;
3907 }
3908
3909 /**
3910 * igb_write_mc_addr_list - write multicast addresses to MTA
3911 * @netdev: network interface device structure
3912 *
3913 * Writes multicast address list to the MTA hash table.
3914 * Returns: -ENOMEM on failure
3915 * 0 on no addresses written
3916 * X on writing X addresses to MTA
3917 **/
3918 static int igb_write_mc_addr_list(struct net_device *netdev)
3919 {
3920 struct igb_adapter *adapter = netdev_priv(netdev);
3921 struct e1000_hw *hw = &adapter->hw;
3922 struct netdev_hw_addr *ha;
3923 u8 *mta_list;
3924 int i;
3925
3926 if (netdev_mc_empty(netdev)) {
3927 /* nothing to program, so clear mc list */
3928 igb_update_mc_addr_list(hw, NULL, 0);
3929 igb_restore_vf_multicasts(adapter);
3930 return 0;
3931 }
3932
3933 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3934 if (!mta_list)
3935 return -ENOMEM;
3936
3937 /* The shared function expects a packed array of only addresses. */
3938 i = 0;
3939 netdev_for_each_mc_addr(ha, netdev)
3940 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3941
3942 igb_update_mc_addr_list(hw, mta_list, i);
3943 kfree(mta_list);
3944
3945 return netdev_mc_count(netdev);
3946 }
3947
3948 /**
3949 * igb_write_uc_addr_list - write unicast addresses to RAR table
3950 * @netdev: network interface device structure
3951 *
3952 * Writes unicast address list to the RAR table.
3953 * Returns: -ENOMEM on failure/insufficient address space
3954 * 0 on no addresses written
3955 * X on writing X addresses to the RAR table
3956 **/
3957 static int igb_write_uc_addr_list(struct net_device *netdev)
3958 {
3959 struct igb_adapter *adapter = netdev_priv(netdev);
3960 struct e1000_hw *hw = &adapter->hw;
3961 unsigned int vfn = adapter->vfs_allocated_count;
3962 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3963 int count = 0;
3964
3965 /* return ENOMEM indicating insufficient memory for addresses */
3966 if (netdev_uc_count(netdev) > rar_entries)
3967 return -ENOMEM;
3968
3969 if (!netdev_uc_empty(netdev) && rar_entries) {
3970 struct netdev_hw_addr *ha;
3971
3972 netdev_for_each_uc_addr(ha, netdev) {
3973 if (!rar_entries)
3974 break;
3975 igb_rar_set_qsel(adapter, ha->addr,
3976 rar_entries--,
3977 vfn);
3978 count++;
3979 }
3980 }
3981 /* write the addresses in reverse order to avoid write combining */
3982 for (; rar_entries > 0 ; rar_entries--) {
3983 wr32(E1000_RAH(rar_entries), 0);
3984 wr32(E1000_RAL(rar_entries), 0);
3985 }
3986 wrfl();
3987
3988 return count;
3989 }
3990
3991 /**
3992 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3993 * @netdev: network interface device structure
3994 *
3995 * The set_rx_mode entry point is called whenever the unicast or multicast
3996 * address lists or the network interface flags are updated. This routine is
3997 * responsible for configuring the hardware for proper unicast, multicast,
3998 * promiscuous mode, and all-multi behavior.
3999 **/
4000 static void igb_set_rx_mode(struct net_device *netdev)
4001 {
4002 struct igb_adapter *adapter = netdev_priv(netdev);
4003 struct e1000_hw *hw = &adapter->hw;
4004 unsigned int vfn = adapter->vfs_allocated_count;
4005 u32 rctl, vmolr = 0;
4006 int count;
4007
4008 /* Check for Promiscuous and All Multicast modes */
4009 rctl = rd32(E1000_RCTL);
4010
4011 /* clear the effected bits */
4012 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4013
4014 if (netdev->flags & IFF_PROMISC) {
4015 /* retain VLAN HW filtering if in VT mode */
4016 if (adapter->vfs_allocated_count)
4017 rctl |= E1000_RCTL_VFE;
4018 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4019 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4020 } else {
4021 if (netdev->flags & IFF_ALLMULTI) {
4022 rctl |= E1000_RCTL_MPE;
4023 vmolr |= E1000_VMOLR_MPME;
4024 } else {
4025 /* Write addresses to the MTA, if the attempt fails
4026 * then we should just turn on promiscuous mode so
4027 * that we can at least receive multicast traffic
4028 */
4029 count = igb_write_mc_addr_list(netdev);
4030 if (count < 0) {
4031 rctl |= E1000_RCTL_MPE;
4032 vmolr |= E1000_VMOLR_MPME;
4033 } else if (count) {
4034 vmolr |= E1000_VMOLR_ROMPE;
4035 }
4036 }
4037 /* Write addresses to available RAR registers, if there is not
4038 * sufficient space to store all the addresses then enable
4039 * unicast promiscuous mode
4040 */
4041 count = igb_write_uc_addr_list(netdev);
4042 if (count < 0) {
4043 rctl |= E1000_RCTL_UPE;
4044 vmolr |= E1000_VMOLR_ROPE;
4045 }
4046 rctl |= E1000_RCTL_VFE;
4047 }
4048 wr32(E1000_RCTL, rctl);
4049
4050 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4051 * the VMOLR to enable the appropriate modes. Without this workaround
4052 * we will have issues with VLAN tag stripping not being done for frames
4053 * that are only arriving because we are the default pool
4054 */
4055 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4056 return;
4057
4058 vmolr |= rd32(E1000_VMOLR(vfn)) &
4059 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4060 wr32(E1000_VMOLR(vfn), vmolr);
4061 igb_restore_vf_multicasts(adapter);
4062 }
4063
4064 static void igb_check_wvbr(struct igb_adapter *adapter)
4065 {
4066 struct e1000_hw *hw = &adapter->hw;
4067 u32 wvbr = 0;
4068
4069 switch (hw->mac.type) {
4070 case e1000_82576:
4071 case e1000_i350:
4072 wvbr = rd32(E1000_WVBR);
4073 if (!wvbr)
4074 return;
4075 break;
4076 default:
4077 break;
4078 }
4079
4080 adapter->wvbr |= wvbr;
4081 }
4082
4083 #define IGB_STAGGERED_QUEUE_OFFSET 8
4084
4085 static void igb_spoof_check(struct igb_adapter *adapter)
4086 {
4087 int j;
4088
4089 if (!adapter->wvbr)
4090 return;
4091
4092 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4093 if (adapter->wvbr & (1 << j) ||
4094 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4095 dev_warn(&adapter->pdev->dev,
4096 "Spoof event(s) detected on VF %d\n", j);
4097 adapter->wvbr &=
4098 ~((1 << j) |
4099 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4100 }
4101 }
4102 }
4103
4104 /* Need to wait a few seconds after link up to get diagnostic information from
4105 * the phy
4106 */
4107 static void igb_update_phy_info(unsigned long data)
4108 {
4109 struct igb_adapter *adapter = (struct igb_adapter *) data;
4110 igb_get_phy_info(&adapter->hw);
4111 }
4112
4113 /**
4114 * igb_has_link - check shared code for link and determine up/down
4115 * @adapter: pointer to driver private info
4116 **/
4117 bool igb_has_link(struct igb_adapter *adapter)
4118 {
4119 struct e1000_hw *hw = &adapter->hw;
4120 bool link_active = false;
4121
4122 /* get_link_status is set on LSC (link status) interrupt or
4123 * rx sequence error interrupt. get_link_status will stay
4124 * false until the e1000_check_for_link establishes link
4125 * for copper adapters ONLY
4126 */
4127 switch (hw->phy.media_type) {
4128 case e1000_media_type_copper:
4129 if (!hw->mac.get_link_status)
4130 return true;
4131 case e1000_media_type_internal_serdes:
4132 hw->mac.ops.check_for_link(hw);
4133 link_active = !hw->mac.get_link_status;
4134 break;
4135 default:
4136 case e1000_media_type_unknown:
4137 break;
4138 }
4139
4140 if (((hw->mac.type == e1000_i210) ||
4141 (hw->mac.type == e1000_i211)) &&
4142 (hw->phy.id == I210_I_PHY_ID)) {
4143 if (!netif_carrier_ok(adapter->netdev)) {
4144 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4145 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4146 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4147 adapter->link_check_timeout = jiffies;
4148 }
4149 }
4150
4151 return link_active;
4152 }
4153
4154 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4155 {
4156 bool ret = false;
4157 u32 ctrl_ext, thstat;
4158
4159 /* check for thermal sensor event on i350 copper only */
4160 if (hw->mac.type == e1000_i350) {
4161 thstat = rd32(E1000_THSTAT);
4162 ctrl_ext = rd32(E1000_CTRL_EXT);
4163
4164 if ((hw->phy.media_type == e1000_media_type_copper) &&
4165 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4166 ret = !!(thstat & event);
4167 }
4168
4169 return ret;
4170 }
4171
4172 /**
4173 * igb_check_lvmmc - check for malformed packets received
4174 * and indicated in LVMMC register
4175 * @adapter: pointer to adapter
4176 **/
4177 static void igb_check_lvmmc(struct igb_adapter *adapter)
4178 {
4179 struct e1000_hw *hw = &adapter->hw;
4180 u32 lvmmc;
4181
4182 lvmmc = rd32(E1000_LVMMC);
4183 if (lvmmc) {
4184 if (unlikely(net_ratelimit())) {
4185 netdev_warn(adapter->netdev,
4186 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4187 lvmmc);
4188 }
4189 }
4190 }
4191
4192 /**
4193 * igb_watchdog - Timer Call-back
4194 * @data: pointer to adapter cast into an unsigned long
4195 **/
4196 static void igb_watchdog(unsigned long data)
4197 {
4198 struct igb_adapter *adapter = (struct igb_adapter *)data;
4199 /* Do the rest outside of interrupt context */
4200 schedule_work(&adapter->watchdog_task);
4201 }
4202
4203 static void igb_watchdog_task(struct work_struct *work)
4204 {
4205 struct igb_adapter *adapter = container_of(work,
4206 struct igb_adapter,
4207 watchdog_task);
4208 struct e1000_hw *hw = &adapter->hw;
4209 struct e1000_phy_info *phy = &hw->phy;
4210 struct net_device *netdev = adapter->netdev;
4211 u32 link;
4212 int i;
4213 u32 connsw;
4214
4215 link = igb_has_link(adapter);
4216
4217 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4218 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4219 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4220 else
4221 link = false;
4222 }
4223
4224 /* Force link down if we have fiber to swap to */
4225 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4226 if (hw->phy.media_type == e1000_media_type_copper) {
4227 connsw = rd32(E1000_CONNSW);
4228 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4229 link = 0;
4230 }
4231 }
4232 if (link) {
4233 /* Perform a reset if the media type changed. */
4234 if (hw->dev_spec._82575.media_changed) {
4235 hw->dev_spec._82575.media_changed = false;
4236 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4237 igb_reset(adapter);
4238 }
4239 /* Cancel scheduled suspend requests. */
4240 pm_runtime_resume(netdev->dev.parent);
4241
4242 if (!netif_carrier_ok(netdev)) {
4243 u32 ctrl;
4244
4245 hw->mac.ops.get_speed_and_duplex(hw,
4246 &adapter->link_speed,
4247 &adapter->link_duplex);
4248
4249 ctrl = rd32(E1000_CTRL);
4250 /* Links status message must follow this format */
4251 netdev_info(netdev,
4252 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4253 netdev->name,
4254 adapter->link_speed,
4255 adapter->link_duplex == FULL_DUPLEX ?
4256 "Full" : "Half",
4257 (ctrl & E1000_CTRL_TFCE) &&
4258 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4259 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4260 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4261
4262 /* disable EEE if enabled */
4263 if ((adapter->flags & IGB_FLAG_EEE) &&
4264 (adapter->link_duplex == HALF_DUPLEX)) {
4265 dev_info(&adapter->pdev->dev,
4266 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4267 adapter->hw.dev_spec._82575.eee_disable = true;
4268 adapter->flags &= ~IGB_FLAG_EEE;
4269 }
4270
4271 /* check if SmartSpeed worked */
4272 igb_check_downshift(hw);
4273 if (phy->speed_downgraded)
4274 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4275
4276 /* check for thermal sensor event */
4277 if (igb_thermal_sensor_event(hw,
4278 E1000_THSTAT_LINK_THROTTLE))
4279 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4280
4281 /* adjust timeout factor according to speed/duplex */
4282 adapter->tx_timeout_factor = 1;
4283 switch (adapter->link_speed) {
4284 case SPEED_10:
4285 adapter->tx_timeout_factor = 14;
4286 break;
4287 case SPEED_100:
4288 /* maybe add some timeout factor ? */
4289 break;
4290 }
4291
4292 netif_carrier_on(netdev);
4293
4294 igb_ping_all_vfs(adapter);
4295 igb_check_vf_rate_limit(adapter);
4296
4297 /* link state has changed, schedule phy info update */
4298 if (!test_bit(__IGB_DOWN, &adapter->state))
4299 mod_timer(&adapter->phy_info_timer,
4300 round_jiffies(jiffies + 2 * HZ));
4301 }
4302 } else {
4303 if (netif_carrier_ok(netdev)) {
4304 adapter->link_speed = 0;
4305 adapter->link_duplex = 0;
4306
4307 /* check for thermal sensor event */
4308 if (igb_thermal_sensor_event(hw,
4309 E1000_THSTAT_PWR_DOWN)) {
4310 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4311 }
4312
4313 /* Links status message must follow this format */
4314 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4315 netdev->name);
4316 netif_carrier_off(netdev);
4317
4318 igb_ping_all_vfs(adapter);
4319
4320 /* link state has changed, schedule phy info update */
4321 if (!test_bit(__IGB_DOWN, &adapter->state))
4322 mod_timer(&adapter->phy_info_timer,
4323 round_jiffies(jiffies + 2 * HZ));
4324
4325 /* link is down, time to check for alternate media */
4326 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4327 igb_check_swap_media(adapter);
4328 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4329 schedule_work(&adapter->reset_task);
4330 /* return immediately */
4331 return;
4332 }
4333 }
4334 pm_schedule_suspend(netdev->dev.parent,
4335 MSEC_PER_SEC * 5);
4336
4337 /* also check for alternate media here */
4338 } else if (!netif_carrier_ok(netdev) &&
4339 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4340 igb_check_swap_media(adapter);
4341 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4342 schedule_work(&adapter->reset_task);
4343 /* return immediately */
4344 return;
4345 }
4346 }
4347 }
4348
4349 spin_lock(&adapter->stats64_lock);
4350 igb_update_stats(adapter, &adapter->stats64);
4351 spin_unlock(&adapter->stats64_lock);
4352
4353 for (i = 0; i < adapter->num_tx_queues; i++) {
4354 struct igb_ring *tx_ring = adapter->tx_ring[i];
4355 if (!netif_carrier_ok(netdev)) {
4356 /* We've lost link, so the controller stops DMA,
4357 * but we've got queued Tx work that's never going
4358 * to get done, so reset controller to flush Tx.
4359 * (Do the reset outside of interrupt context).
4360 */
4361 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4362 adapter->tx_timeout_count++;
4363 schedule_work(&adapter->reset_task);
4364 /* return immediately since reset is imminent */
4365 return;
4366 }
4367 }
4368
4369 /* Force detection of hung controller every watchdog period */
4370 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4371 }
4372
4373 /* Cause software interrupt to ensure Rx ring is cleaned */
4374 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4375 u32 eics = 0;
4376
4377 for (i = 0; i < adapter->num_q_vectors; i++)
4378 eics |= adapter->q_vector[i]->eims_value;
4379 wr32(E1000_EICS, eics);
4380 } else {
4381 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4382 }
4383
4384 igb_spoof_check(adapter);
4385 igb_ptp_rx_hang(adapter);
4386
4387 /* Check LVMMC register on i350/i354 only */
4388 if ((adapter->hw.mac.type == e1000_i350) ||
4389 (adapter->hw.mac.type == e1000_i354))
4390 igb_check_lvmmc(adapter);
4391
4392 /* Reset the timer */
4393 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4394 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4395 mod_timer(&adapter->watchdog_timer,
4396 round_jiffies(jiffies + HZ));
4397 else
4398 mod_timer(&adapter->watchdog_timer,
4399 round_jiffies(jiffies + 2 * HZ));
4400 }
4401 }
4402
4403 enum latency_range {
4404 lowest_latency = 0,
4405 low_latency = 1,
4406 bulk_latency = 2,
4407 latency_invalid = 255
4408 };
4409
4410 /**
4411 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4412 * @q_vector: pointer to q_vector
4413 *
4414 * Stores a new ITR value based on strictly on packet size. This
4415 * algorithm is less sophisticated than that used in igb_update_itr,
4416 * due to the difficulty of synchronizing statistics across multiple
4417 * receive rings. The divisors and thresholds used by this function
4418 * were determined based on theoretical maximum wire speed and testing
4419 * data, in order to minimize response time while increasing bulk
4420 * throughput.
4421 * This functionality is controlled by ethtool's coalescing settings.
4422 * NOTE: This function is called only when operating in a multiqueue
4423 * receive environment.
4424 **/
4425 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4426 {
4427 int new_val = q_vector->itr_val;
4428 int avg_wire_size = 0;
4429 struct igb_adapter *adapter = q_vector->adapter;
4430 unsigned int packets;
4431
4432 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4433 * ints/sec - ITR timer value of 120 ticks.
4434 */
4435 if (adapter->link_speed != SPEED_1000) {
4436 new_val = IGB_4K_ITR;
4437 goto set_itr_val;
4438 }
4439
4440 packets = q_vector->rx.total_packets;
4441 if (packets)
4442 avg_wire_size = q_vector->rx.total_bytes / packets;
4443
4444 packets = q_vector->tx.total_packets;
4445 if (packets)
4446 avg_wire_size = max_t(u32, avg_wire_size,
4447 q_vector->tx.total_bytes / packets);
4448
4449 /* if avg_wire_size isn't set no work was done */
4450 if (!avg_wire_size)
4451 goto clear_counts;
4452
4453 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4454 avg_wire_size += 24;
4455
4456 /* Don't starve jumbo frames */
4457 avg_wire_size = min(avg_wire_size, 3000);
4458
4459 /* Give a little boost to mid-size frames */
4460 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4461 new_val = avg_wire_size / 3;
4462 else
4463 new_val = avg_wire_size / 2;
4464
4465 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4466 if (new_val < IGB_20K_ITR &&
4467 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4468 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4469 new_val = IGB_20K_ITR;
4470
4471 set_itr_val:
4472 if (new_val != q_vector->itr_val) {
4473 q_vector->itr_val = new_val;
4474 q_vector->set_itr = 1;
4475 }
4476 clear_counts:
4477 q_vector->rx.total_bytes = 0;
4478 q_vector->rx.total_packets = 0;
4479 q_vector->tx.total_bytes = 0;
4480 q_vector->tx.total_packets = 0;
4481 }
4482
4483 /**
4484 * igb_update_itr - update the dynamic ITR value based on statistics
4485 * @q_vector: pointer to q_vector
4486 * @ring_container: ring info to update the itr for
4487 *
4488 * Stores a new ITR value based on packets and byte
4489 * counts during the last interrupt. The advantage of per interrupt
4490 * computation is faster updates and more accurate ITR for the current
4491 * traffic pattern. Constants in this function were computed
4492 * based on theoretical maximum wire speed and thresholds were set based
4493 * on testing data as well as attempting to minimize response time
4494 * while increasing bulk throughput.
4495 * This functionality is controlled by ethtool's coalescing settings.
4496 * NOTE: These calculations are only valid when operating in a single-
4497 * queue environment.
4498 **/
4499 static void igb_update_itr(struct igb_q_vector *q_vector,
4500 struct igb_ring_container *ring_container)
4501 {
4502 unsigned int packets = ring_container->total_packets;
4503 unsigned int bytes = ring_container->total_bytes;
4504 u8 itrval = ring_container->itr;
4505
4506 /* no packets, exit with status unchanged */
4507 if (packets == 0)
4508 return;
4509
4510 switch (itrval) {
4511 case lowest_latency:
4512 /* handle TSO and jumbo frames */
4513 if (bytes/packets > 8000)
4514 itrval = bulk_latency;
4515 else if ((packets < 5) && (bytes > 512))
4516 itrval = low_latency;
4517 break;
4518 case low_latency: /* 50 usec aka 20000 ints/s */
4519 if (bytes > 10000) {
4520 /* this if handles the TSO accounting */
4521 if (bytes/packets > 8000)
4522 itrval = bulk_latency;
4523 else if ((packets < 10) || ((bytes/packets) > 1200))
4524 itrval = bulk_latency;
4525 else if ((packets > 35))
4526 itrval = lowest_latency;
4527 } else if (bytes/packets > 2000) {
4528 itrval = bulk_latency;
4529 } else if (packets <= 2 && bytes < 512) {
4530 itrval = lowest_latency;
4531 }
4532 break;
4533 case bulk_latency: /* 250 usec aka 4000 ints/s */
4534 if (bytes > 25000) {
4535 if (packets > 35)
4536 itrval = low_latency;
4537 } else if (bytes < 1500) {
4538 itrval = low_latency;
4539 }
4540 break;
4541 }
4542
4543 /* clear work counters since we have the values we need */
4544 ring_container->total_bytes = 0;
4545 ring_container->total_packets = 0;
4546
4547 /* write updated itr to ring container */
4548 ring_container->itr = itrval;
4549 }
4550
4551 static void igb_set_itr(struct igb_q_vector *q_vector)
4552 {
4553 struct igb_adapter *adapter = q_vector->adapter;
4554 u32 new_itr = q_vector->itr_val;
4555 u8 current_itr = 0;
4556
4557 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4558 if (adapter->link_speed != SPEED_1000) {
4559 current_itr = 0;
4560 new_itr = IGB_4K_ITR;
4561 goto set_itr_now;
4562 }
4563
4564 igb_update_itr(q_vector, &q_vector->tx);
4565 igb_update_itr(q_vector, &q_vector->rx);
4566
4567 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4568
4569 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4570 if (current_itr == lowest_latency &&
4571 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4572 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4573 current_itr = low_latency;
4574
4575 switch (current_itr) {
4576 /* counts and packets in update_itr are dependent on these numbers */
4577 case lowest_latency:
4578 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4579 break;
4580 case low_latency:
4581 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4582 break;
4583 case bulk_latency:
4584 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4585 break;
4586 default:
4587 break;
4588 }
4589
4590 set_itr_now:
4591 if (new_itr != q_vector->itr_val) {
4592 /* this attempts to bias the interrupt rate towards Bulk
4593 * by adding intermediate steps when interrupt rate is
4594 * increasing
4595 */
4596 new_itr = new_itr > q_vector->itr_val ?
4597 max((new_itr * q_vector->itr_val) /
4598 (new_itr + (q_vector->itr_val >> 2)),
4599 new_itr) : new_itr;
4600 /* Don't write the value here; it resets the adapter's
4601 * internal timer, and causes us to delay far longer than
4602 * we should between interrupts. Instead, we write the ITR
4603 * value at the beginning of the next interrupt so the timing
4604 * ends up being correct.
4605 */
4606 q_vector->itr_val = new_itr;
4607 q_vector->set_itr = 1;
4608 }
4609 }
4610
4611 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4612 u32 type_tucmd, u32 mss_l4len_idx)
4613 {
4614 struct e1000_adv_tx_context_desc *context_desc;
4615 u16 i = tx_ring->next_to_use;
4616
4617 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4618
4619 i++;
4620 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4621
4622 /* set bits to identify this as an advanced context descriptor */
4623 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4624
4625 /* For 82575, context index must be unique per ring. */
4626 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4627 mss_l4len_idx |= tx_ring->reg_idx << 4;
4628
4629 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4630 context_desc->seqnum_seed = 0;
4631 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4632 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4633 }
4634
4635 static int igb_tso(struct igb_ring *tx_ring,
4636 struct igb_tx_buffer *first,
4637 u8 *hdr_len)
4638 {
4639 struct sk_buff *skb = first->skb;
4640 u32 vlan_macip_lens, type_tucmd;
4641 u32 mss_l4len_idx, l4len;
4642 int err;
4643
4644 if (skb->ip_summed != CHECKSUM_PARTIAL)
4645 return 0;
4646
4647 if (!skb_is_gso(skb))
4648 return 0;
4649
4650 err = skb_cow_head(skb, 0);
4651 if (err < 0)
4652 return err;
4653
4654 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4655 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4656
4657 if (first->protocol == htons(ETH_P_IP)) {
4658 struct iphdr *iph = ip_hdr(skb);
4659 iph->tot_len = 0;
4660 iph->check = 0;
4661 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4662 iph->daddr, 0,
4663 IPPROTO_TCP,
4664 0);
4665 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4666 first->tx_flags |= IGB_TX_FLAGS_TSO |
4667 IGB_TX_FLAGS_CSUM |
4668 IGB_TX_FLAGS_IPV4;
4669 } else if (skb_is_gso_v6(skb)) {
4670 ipv6_hdr(skb)->payload_len = 0;
4671 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4672 &ipv6_hdr(skb)->daddr,
4673 0, IPPROTO_TCP, 0);
4674 first->tx_flags |= IGB_TX_FLAGS_TSO |
4675 IGB_TX_FLAGS_CSUM;
4676 }
4677
4678 /* compute header lengths */
4679 l4len = tcp_hdrlen(skb);
4680 *hdr_len = skb_transport_offset(skb) + l4len;
4681
4682 /* update gso size and bytecount with header size */
4683 first->gso_segs = skb_shinfo(skb)->gso_segs;
4684 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4685
4686 /* MSS L4LEN IDX */
4687 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4688 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4689
4690 /* VLAN MACLEN IPLEN */
4691 vlan_macip_lens = skb_network_header_len(skb);
4692 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4693 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4694
4695 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4696
4697 return 1;
4698 }
4699
4700 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4701 {
4702 struct sk_buff *skb = first->skb;
4703 u32 vlan_macip_lens = 0;
4704 u32 mss_l4len_idx = 0;
4705 u32 type_tucmd = 0;
4706
4707 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4708 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4709 return;
4710 } else {
4711 u8 l4_hdr = 0;
4712
4713 switch (first->protocol) {
4714 case htons(ETH_P_IP):
4715 vlan_macip_lens |= skb_network_header_len(skb);
4716 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4717 l4_hdr = ip_hdr(skb)->protocol;
4718 break;
4719 case htons(ETH_P_IPV6):
4720 vlan_macip_lens |= skb_network_header_len(skb);
4721 l4_hdr = ipv6_hdr(skb)->nexthdr;
4722 break;
4723 default:
4724 if (unlikely(net_ratelimit())) {
4725 dev_warn(tx_ring->dev,
4726 "partial checksum but proto=%x!\n",
4727 first->protocol);
4728 }
4729 break;
4730 }
4731
4732 switch (l4_hdr) {
4733 case IPPROTO_TCP:
4734 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4735 mss_l4len_idx = tcp_hdrlen(skb) <<
4736 E1000_ADVTXD_L4LEN_SHIFT;
4737 break;
4738 case IPPROTO_SCTP:
4739 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4740 mss_l4len_idx = sizeof(struct sctphdr) <<
4741 E1000_ADVTXD_L4LEN_SHIFT;
4742 break;
4743 case IPPROTO_UDP:
4744 mss_l4len_idx = sizeof(struct udphdr) <<
4745 E1000_ADVTXD_L4LEN_SHIFT;
4746 break;
4747 default:
4748 if (unlikely(net_ratelimit())) {
4749 dev_warn(tx_ring->dev,
4750 "partial checksum but l4 proto=%x!\n",
4751 l4_hdr);
4752 }
4753 break;
4754 }
4755
4756 /* update TX checksum flag */
4757 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4758 }
4759
4760 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4761 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4762
4763 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4764 }
4765
4766 #define IGB_SET_FLAG(_input, _flag, _result) \
4767 ((_flag <= _result) ? \
4768 ((u32)(_input & _flag) * (_result / _flag)) : \
4769 ((u32)(_input & _flag) / (_flag / _result)))
4770
4771 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4772 {
4773 /* set type for advanced descriptor with frame checksum insertion */
4774 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4775 E1000_ADVTXD_DCMD_DEXT |
4776 E1000_ADVTXD_DCMD_IFCS;
4777
4778 /* set HW vlan bit if vlan is present */
4779 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4780 (E1000_ADVTXD_DCMD_VLE));
4781
4782 /* set segmentation bits for TSO */
4783 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4784 (E1000_ADVTXD_DCMD_TSE));
4785
4786 /* set timestamp bit if present */
4787 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4788 (E1000_ADVTXD_MAC_TSTAMP));
4789
4790 /* insert frame checksum */
4791 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4792
4793 return cmd_type;
4794 }
4795
4796 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4797 union e1000_adv_tx_desc *tx_desc,
4798 u32 tx_flags, unsigned int paylen)
4799 {
4800 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4801
4802 /* 82575 requires a unique index per ring */
4803 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4804 olinfo_status |= tx_ring->reg_idx << 4;
4805
4806 /* insert L4 checksum */
4807 olinfo_status |= IGB_SET_FLAG(tx_flags,
4808 IGB_TX_FLAGS_CSUM,
4809 (E1000_TXD_POPTS_TXSM << 8));
4810
4811 /* insert IPv4 checksum */
4812 olinfo_status |= IGB_SET_FLAG(tx_flags,
4813 IGB_TX_FLAGS_IPV4,
4814 (E1000_TXD_POPTS_IXSM << 8));
4815
4816 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4817 }
4818
4819 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4820 {
4821 struct net_device *netdev = tx_ring->netdev;
4822
4823 netif_stop_subqueue(netdev, tx_ring->queue_index);
4824
4825 /* Herbert's original patch had:
4826 * smp_mb__after_netif_stop_queue();
4827 * but since that doesn't exist yet, just open code it.
4828 */
4829 smp_mb();
4830
4831 /* We need to check again in a case another CPU has just
4832 * made room available.
4833 */
4834 if (igb_desc_unused(tx_ring) < size)
4835 return -EBUSY;
4836
4837 /* A reprieve! */
4838 netif_wake_subqueue(netdev, tx_ring->queue_index);
4839
4840 u64_stats_update_begin(&tx_ring->tx_syncp2);
4841 tx_ring->tx_stats.restart_queue2++;
4842 u64_stats_update_end(&tx_ring->tx_syncp2);
4843
4844 return 0;
4845 }
4846
4847 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4848 {
4849 if (igb_desc_unused(tx_ring) >= size)
4850 return 0;
4851 return __igb_maybe_stop_tx(tx_ring, size);
4852 }
4853
4854 static void igb_tx_map(struct igb_ring *tx_ring,
4855 struct igb_tx_buffer *first,
4856 const u8 hdr_len)
4857 {
4858 struct sk_buff *skb = first->skb;
4859 struct igb_tx_buffer *tx_buffer;
4860 union e1000_adv_tx_desc *tx_desc;
4861 struct skb_frag_struct *frag;
4862 dma_addr_t dma;
4863 unsigned int data_len, size;
4864 u32 tx_flags = first->tx_flags;
4865 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4866 u16 i = tx_ring->next_to_use;
4867
4868 tx_desc = IGB_TX_DESC(tx_ring, i);
4869
4870 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4871
4872 size = skb_headlen(skb);
4873 data_len = skb->data_len;
4874
4875 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4876
4877 tx_buffer = first;
4878
4879 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4880 if (dma_mapping_error(tx_ring->dev, dma))
4881 goto dma_error;
4882
4883 /* record length, and DMA address */
4884 dma_unmap_len_set(tx_buffer, len, size);
4885 dma_unmap_addr_set(tx_buffer, dma, dma);
4886
4887 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4888
4889 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4890 tx_desc->read.cmd_type_len =
4891 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4892
4893 i++;
4894 tx_desc++;
4895 if (i == tx_ring->count) {
4896 tx_desc = IGB_TX_DESC(tx_ring, 0);
4897 i = 0;
4898 }
4899 tx_desc->read.olinfo_status = 0;
4900
4901 dma += IGB_MAX_DATA_PER_TXD;
4902 size -= IGB_MAX_DATA_PER_TXD;
4903
4904 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4905 }
4906
4907 if (likely(!data_len))
4908 break;
4909
4910 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4911
4912 i++;
4913 tx_desc++;
4914 if (i == tx_ring->count) {
4915 tx_desc = IGB_TX_DESC(tx_ring, 0);
4916 i = 0;
4917 }
4918 tx_desc->read.olinfo_status = 0;
4919
4920 size = skb_frag_size(frag);
4921 data_len -= size;
4922
4923 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4924 size, DMA_TO_DEVICE);
4925
4926 tx_buffer = &tx_ring->tx_buffer_info[i];
4927 }
4928
4929 /* write last descriptor with RS and EOP bits */
4930 cmd_type |= size | IGB_TXD_DCMD;
4931 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4932
4933 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4934
4935 /* set the timestamp */
4936 first->time_stamp = jiffies;
4937
4938 /* Force memory writes to complete before letting h/w know there
4939 * are new descriptors to fetch. (Only applicable for weak-ordered
4940 * memory model archs, such as IA-64).
4941 *
4942 * We also need this memory barrier to make certain all of the
4943 * status bits have been updated before next_to_watch is written.
4944 */
4945 wmb();
4946
4947 /* set next_to_watch value indicating a packet is present */
4948 first->next_to_watch = tx_desc;
4949
4950 i++;
4951 if (i == tx_ring->count)
4952 i = 0;
4953
4954 tx_ring->next_to_use = i;
4955
4956 /* Make sure there is space in the ring for the next send. */
4957 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4958
4959 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4960 writel(i, tx_ring->tail);
4961
4962 /* we need this if more than one processor can write to our tail
4963 * at a time, it synchronizes IO on IA64/Altix systems
4964 */
4965 mmiowb();
4966 }
4967 return;
4968
4969 dma_error:
4970 dev_err(tx_ring->dev, "TX DMA map failed\n");
4971
4972 /* clear dma mappings for failed tx_buffer_info map */
4973 for (;;) {
4974 tx_buffer = &tx_ring->tx_buffer_info[i];
4975 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4976 if (tx_buffer == first)
4977 break;
4978 if (i == 0)
4979 i = tx_ring->count;
4980 i--;
4981 }
4982
4983 tx_ring->next_to_use = i;
4984 }
4985
4986 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4987 struct igb_ring *tx_ring)
4988 {
4989 struct igb_tx_buffer *first;
4990 int tso;
4991 u32 tx_flags = 0;
4992 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4993 __be16 protocol = vlan_get_protocol(skb);
4994 u8 hdr_len = 0;
4995
4996 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4997 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4998 * + 2 desc gap to keep tail from touching head,
4999 * + 1 desc for context descriptor,
5000 * otherwise try next time
5001 */
5002 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
5003 unsigned short f;
5004
5005 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5006 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5007 } else {
5008 count += skb_shinfo(skb)->nr_frags;
5009 }
5010
5011 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5012 /* this is a hard error */
5013 return NETDEV_TX_BUSY;
5014 }
5015
5016 /* record the location of the first descriptor for this packet */
5017 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5018 first->skb = skb;
5019 first->bytecount = skb->len;
5020 first->gso_segs = 1;
5021
5022 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5023 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5024
5025 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5026 &adapter->state)) {
5027 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5028 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5029
5030 adapter->ptp_tx_skb = skb_get(skb);
5031 adapter->ptp_tx_start = jiffies;
5032 if (adapter->hw.mac.type == e1000_82576)
5033 schedule_work(&adapter->ptp_tx_work);
5034 }
5035 }
5036
5037 skb_tx_timestamp(skb);
5038
5039 if (skb_vlan_tag_present(skb)) {
5040 tx_flags |= IGB_TX_FLAGS_VLAN;
5041 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5042 }
5043
5044 /* record initial flags and protocol */
5045 first->tx_flags = tx_flags;
5046 first->protocol = protocol;
5047
5048 tso = igb_tso(tx_ring, first, &hdr_len);
5049 if (tso < 0)
5050 goto out_drop;
5051 else if (!tso)
5052 igb_tx_csum(tx_ring, first);
5053
5054 igb_tx_map(tx_ring, first, hdr_len);
5055
5056 return NETDEV_TX_OK;
5057
5058 out_drop:
5059 igb_unmap_and_free_tx_resource(tx_ring, first);
5060
5061 return NETDEV_TX_OK;
5062 }
5063
5064 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5065 struct sk_buff *skb)
5066 {
5067 unsigned int r_idx = skb->queue_mapping;
5068
5069 if (r_idx >= adapter->num_tx_queues)
5070 r_idx = r_idx % adapter->num_tx_queues;
5071
5072 return adapter->tx_ring[r_idx];
5073 }
5074
5075 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5076 struct net_device *netdev)
5077 {
5078 struct igb_adapter *adapter = netdev_priv(netdev);
5079
5080 if (test_bit(__IGB_DOWN, &adapter->state)) {
5081 dev_kfree_skb_any(skb);
5082 return NETDEV_TX_OK;
5083 }
5084
5085 if (skb->len <= 0) {
5086 dev_kfree_skb_any(skb);
5087 return NETDEV_TX_OK;
5088 }
5089
5090 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5091 * in order to meet this minimum size requirement.
5092 */
5093 if (skb_put_padto(skb, 17))
5094 return NETDEV_TX_OK;
5095
5096 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5097 }
5098
5099 /**
5100 * igb_tx_timeout - Respond to a Tx Hang
5101 * @netdev: network interface device structure
5102 **/
5103 static void igb_tx_timeout(struct net_device *netdev)
5104 {
5105 struct igb_adapter *adapter = netdev_priv(netdev);
5106 struct e1000_hw *hw = &adapter->hw;
5107
5108 /* Do the reset outside of interrupt context */
5109 adapter->tx_timeout_count++;
5110
5111 if (hw->mac.type >= e1000_82580)
5112 hw->dev_spec._82575.global_device_reset = true;
5113
5114 schedule_work(&adapter->reset_task);
5115 wr32(E1000_EICS,
5116 (adapter->eims_enable_mask & ~adapter->eims_other));
5117 }
5118
5119 static void igb_reset_task(struct work_struct *work)
5120 {
5121 struct igb_adapter *adapter;
5122 adapter = container_of(work, struct igb_adapter, reset_task);
5123
5124 igb_dump(adapter);
5125 netdev_err(adapter->netdev, "Reset adapter\n");
5126 igb_reinit_locked(adapter);
5127 }
5128
5129 /**
5130 * igb_get_stats64 - Get System Network Statistics
5131 * @netdev: network interface device structure
5132 * @stats: rtnl_link_stats64 pointer
5133 **/
5134 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5135 struct rtnl_link_stats64 *stats)
5136 {
5137 struct igb_adapter *adapter = netdev_priv(netdev);
5138
5139 spin_lock(&adapter->stats64_lock);
5140 igb_update_stats(adapter, &adapter->stats64);
5141 memcpy(stats, &adapter->stats64, sizeof(*stats));
5142 spin_unlock(&adapter->stats64_lock);
5143
5144 return stats;
5145 }
5146
5147 /**
5148 * igb_change_mtu - Change the Maximum Transfer Unit
5149 * @netdev: network interface device structure
5150 * @new_mtu: new value for maximum frame size
5151 *
5152 * Returns 0 on success, negative on failure
5153 **/
5154 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5155 {
5156 struct igb_adapter *adapter = netdev_priv(netdev);
5157 struct pci_dev *pdev = adapter->pdev;
5158 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5159
5160 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5161 dev_err(&pdev->dev, "Invalid MTU setting\n");
5162 return -EINVAL;
5163 }
5164
5165 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5166 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5167 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5168 return -EINVAL;
5169 }
5170
5171 /* adjust max frame to be at least the size of a standard frame */
5172 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5173 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5174
5175 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5176 usleep_range(1000, 2000);
5177
5178 /* igb_down has a dependency on max_frame_size */
5179 adapter->max_frame_size = max_frame;
5180
5181 if (netif_running(netdev))
5182 igb_down(adapter);
5183
5184 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5185 netdev->mtu, new_mtu);
5186 netdev->mtu = new_mtu;
5187
5188 if (netif_running(netdev))
5189 igb_up(adapter);
5190 else
5191 igb_reset(adapter);
5192
5193 clear_bit(__IGB_RESETTING, &adapter->state);
5194
5195 return 0;
5196 }
5197
5198 /**
5199 * igb_update_stats - Update the board statistics counters
5200 * @adapter: board private structure
5201 **/
5202 void igb_update_stats(struct igb_adapter *adapter,
5203 struct rtnl_link_stats64 *net_stats)
5204 {
5205 struct e1000_hw *hw = &adapter->hw;
5206 struct pci_dev *pdev = adapter->pdev;
5207 u32 reg, mpc;
5208 int i;
5209 u64 bytes, packets;
5210 unsigned int start;
5211 u64 _bytes, _packets;
5212
5213 /* Prevent stats update while adapter is being reset, or if the pci
5214 * connection is down.
5215 */
5216 if (adapter->link_speed == 0)
5217 return;
5218 if (pci_channel_offline(pdev))
5219 return;
5220
5221 bytes = 0;
5222 packets = 0;
5223
5224 rcu_read_lock();
5225 for (i = 0; i < adapter->num_rx_queues; i++) {
5226 struct igb_ring *ring = adapter->rx_ring[i];
5227 u32 rqdpc = rd32(E1000_RQDPC(i));
5228 if (hw->mac.type >= e1000_i210)
5229 wr32(E1000_RQDPC(i), 0);
5230
5231 if (rqdpc) {
5232 ring->rx_stats.drops += rqdpc;
5233 net_stats->rx_fifo_errors += rqdpc;
5234 }
5235
5236 do {
5237 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5238 _bytes = ring->rx_stats.bytes;
5239 _packets = ring->rx_stats.packets;
5240 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5241 bytes += _bytes;
5242 packets += _packets;
5243 }
5244
5245 net_stats->rx_bytes = bytes;
5246 net_stats->rx_packets = packets;
5247
5248 bytes = 0;
5249 packets = 0;
5250 for (i = 0; i < adapter->num_tx_queues; i++) {
5251 struct igb_ring *ring = adapter->tx_ring[i];
5252 do {
5253 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5254 _bytes = ring->tx_stats.bytes;
5255 _packets = ring->tx_stats.packets;
5256 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5257 bytes += _bytes;
5258 packets += _packets;
5259 }
5260 net_stats->tx_bytes = bytes;
5261 net_stats->tx_packets = packets;
5262 rcu_read_unlock();
5263
5264 /* read stats registers */
5265 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5266 adapter->stats.gprc += rd32(E1000_GPRC);
5267 adapter->stats.gorc += rd32(E1000_GORCL);
5268 rd32(E1000_GORCH); /* clear GORCL */
5269 adapter->stats.bprc += rd32(E1000_BPRC);
5270 adapter->stats.mprc += rd32(E1000_MPRC);
5271 adapter->stats.roc += rd32(E1000_ROC);
5272
5273 adapter->stats.prc64 += rd32(E1000_PRC64);
5274 adapter->stats.prc127 += rd32(E1000_PRC127);
5275 adapter->stats.prc255 += rd32(E1000_PRC255);
5276 adapter->stats.prc511 += rd32(E1000_PRC511);
5277 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5278 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5279 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5280 adapter->stats.sec += rd32(E1000_SEC);
5281
5282 mpc = rd32(E1000_MPC);
5283 adapter->stats.mpc += mpc;
5284 net_stats->rx_fifo_errors += mpc;
5285 adapter->stats.scc += rd32(E1000_SCC);
5286 adapter->stats.ecol += rd32(E1000_ECOL);
5287 adapter->stats.mcc += rd32(E1000_MCC);
5288 adapter->stats.latecol += rd32(E1000_LATECOL);
5289 adapter->stats.dc += rd32(E1000_DC);
5290 adapter->stats.rlec += rd32(E1000_RLEC);
5291 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5292 adapter->stats.xontxc += rd32(E1000_XONTXC);
5293 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5294 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5295 adapter->stats.fcruc += rd32(E1000_FCRUC);
5296 adapter->stats.gptc += rd32(E1000_GPTC);
5297 adapter->stats.gotc += rd32(E1000_GOTCL);
5298 rd32(E1000_GOTCH); /* clear GOTCL */
5299 adapter->stats.rnbc += rd32(E1000_RNBC);
5300 adapter->stats.ruc += rd32(E1000_RUC);
5301 adapter->stats.rfc += rd32(E1000_RFC);
5302 adapter->stats.rjc += rd32(E1000_RJC);
5303 adapter->stats.tor += rd32(E1000_TORH);
5304 adapter->stats.tot += rd32(E1000_TOTH);
5305 adapter->stats.tpr += rd32(E1000_TPR);
5306
5307 adapter->stats.ptc64 += rd32(E1000_PTC64);
5308 adapter->stats.ptc127 += rd32(E1000_PTC127);
5309 adapter->stats.ptc255 += rd32(E1000_PTC255);
5310 adapter->stats.ptc511 += rd32(E1000_PTC511);
5311 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5312 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5313
5314 adapter->stats.mptc += rd32(E1000_MPTC);
5315 adapter->stats.bptc += rd32(E1000_BPTC);
5316
5317 adapter->stats.tpt += rd32(E1000_TPT);
5318 adapter->stats.colc += rd32(E1000_COLC);
5319
5320 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5321 /* read internal phy specific stats */
5322 reg = rd32(E1000_CTRL_EXT);
5323 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5324 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5325
5326 /* this stat has invalid values on i210/i211 */
5327 if ((hw->mac.type != e1000_i210) &&
5328 (hw->mac.type != e1000_i211))
5329 adapter->stats.tncrs += rd32(E1000_TNCRS);
5330 }
5331
5332 adapter->stats.tsctc += rd32(E1000_TSCTC);
5333 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5334
5335 adapter->stats.iac += rd32(E1000_IAC);
5336 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5337 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5338 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5339 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5340 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5341 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5342 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5343 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5344
5345 /* Fill out the OS statistics structure */
5346 net_stats->multicast = adapter->stats.mprc;
5347 net_stats->collisions = adapter->stats.colc;
5348
5349 /* Rx Errors */
5350
5351 /* RLEC on some newer hardware can be incorrect so build
5352 * our own version based on RUC and ROC
5353 */
5354 net_stats->rx_errors = adapter->stats.rxerrc +
5355 adapter->stats.crcerrs + adapter->stats.algnerrc +
5356 adapter->stats.ruc + adapter->stats.roc +
5357 adapter->stats.cexterr;
5358 net_stats->rx_length_errors = adapter->stats.ruc +
5359 adapter->stats.roc;
5360 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5361 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5362 net_stats->rx_missed_errors = adapter->stats.mpc;
5363
5364 /* Tx Errors */
5365 net_stats->tx_errors = adapter->stats.ecol +
5366 adapter->stats.latecol;
5367 net_stats->tx_aborted_errors = adapter->stats.ecol;
5368 net_stats->tx_window_errors = adapter->stats.latecol;
5369 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5370
5371 /* Tx Dropped needs to be maintained elsewhere */
5372
5373 /* Management Stats */
5374 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5375 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5376 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5377
5378 /* OS2BMC Stats */
5379 reg = rd32(E1000_MANC);
5380 if (reg & E1000_MANC_EN_BMC2OS) {
5381 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5382 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5383 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5384 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5385 }
5386 }
5387
5388 static void igb_tsync_interrupt(struct igb_adapter *adapter)
5389 {
5390 struct e1000_hw *hw = &adapter->hw;
5391 struct ptp_clock_event event;
5392 struct timespec ts;
5393 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5394
5395 if (tsicr & TSINTR_SYS_WRAP) {
5396 event.type = PTP_CLOCK_PPS;
5397 if (adapter->ptp_caps.pps)
5398 ptp_clock_event(adapter->ptp_clock, &event);
5399 else
5400 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5401 ack |= TSINTR_SYS_WRAP;
5402 }
5403
5404 if (tsicr & E1000_TSICR_TXTS) {
5405 /* retrieve hardware timestamp */
5406 schedule_work(&adapter->ptp_tx_work);
5407 ack |= E1000_TSICR_TXTS;
5408 }
5409
5410 if (tsicr & TSINTR_TT0) {
5411 spin_lock(&adapter->tmreg_lock);
5412 ts = timespec_add(adapter->perout[0].start,
5413 adapter->perout[0].period);
5414 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5415 wr32(E1000_TRGTTIMH0, ts.tv_sec);
5416 tsauxc = rd32(E1000_TSAUXC);
5417 tsauxc |= TSAUXC_EN_TT0;
5418 wr32(E1000_TSAUXC, tsauxc);
5419 adapter->perout[0].start = ts;
5420 spin_unlock(&adapter->tmreg_lock);
5421 ack |= TSINTR_TT0;
5422 }
5423
5424 if (tsicr & TSINTR_TT1) {
5425 spin_lock(&adapter->tmreg_lock);
5426 ts = timespec_add(adapter->perout[1].start,
5427 adapter->perout[1].period);
5428 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5429 wr32(E1000_TRGTTIMH1, ts.tv_sec);
5430 tsauxc = rd32(E1000_TSAUXC);
5431 tsauxc |= TSAUXC_EN_TT1;
5432 wr32(E1000_TSAUXC, tsauxc);
5433 adapter->perout[1].start = ts;
5434 spin_unlock(&adapter->tmreg_lock);
5435 ack |= TSINTR_TT1;
5436 }
5437
5438 if (tsicr & TSINTR_AUTT0) {
5439 nsec = rd32(E1000_AUXSTMPL0);
5440 sec = rd32(E1000_AUXSTMPH0);
5441 event.type = PTP_CLOCK_EXTTS;
5442 event.index = 0;
5443 event.timestamp = sec * 1000000000ULL + nsec;
5444 ptp_clock_event(adapter->ptp_clock, &event);
5445 ack |= TSINTR_AUTT0;
5446 }
5447
5448 if (tsicr & TSINTR_AUTT1) {
5449 nsec = rd32(E1000_AUXSTMPL1);
5450 sec = rd32(E1000_AUXSTMPH1);
5451 event.type = PTP_CLOCK_EXTTS;
5452 event.index = 1;
5453 event.timestamp = sec * 1000000000ULL + nsec;
5454 ptp_clock_event(adapter->ptp_clock, &event);
5455 ack |= TSINTR_AUTT1;
5456 }
5457
5458 /* acknowledge the interrupts */
5459 wr32(E1000_TSICR, ack);
5460 }
5461
5462 static irqreturn_t igb_msix_other(int irq, void *data)
5463 {
5464 struct igb_adapter *adapter = data;
5465 struct e1000_hw *hw = &adapter->hw;
5466 u32 icr = rd32(E1000_ICR);
5467 /* reading ICR causes bit 31 of EICR to be cleared */
5468
5469 if (icr & E1000_ICR_DRSTA)
5470 schedule_work(&adapter->reset_task);
5471
5472 if (icr & E1000_ICR_DOUTSYNC) {
5473 /* HW is reporting DMA is out of sync */
5474 adapter->stats.doosync++;
5475 /* The DMA Out of Sync is also indication of a spoof event
5476 * in IOV mode. Check the Wrong VM Behavior register to
5477 * see if it is really a spoof event.
5478 */
5479 igb_check_wvbr(adapter);
5480 }
5481
5482 /* Check for a mailbox event */
5483 if (icr & E1000_ICR_VMMB)
5484 igb_msg_task(adapter);
5485
5486 if (icr & E1000_ICR_LSC) {
5487 hw->mac.get_link_status = 1;
5488 /* guard against interrupt when we're going down */
5489 if (!test_bit(__IGB_DOWN, &adapter->state))
5490 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5491 }
5492
5493 if (icr & E1000_ICR_TS)
5494 igb_tsync_interrupt(adapter);
5495
5496 wr32(E1000_EIMS, adapter->eims_other);
5497
5498 return IRQ_HANDLED;
5499 }
5500
5501 static void igb_write_itr(struct igb_q_vector *q_vector)
5502 {
5503 struct igb_adapter *adapter = q_vector->adapter;
5504 u32 itr_val = q_vector->itr_val & 0x7FFC;
5505
5506 if (!q_vector->set_itr)
5507 return;
5508
5509 if (!itr_val)
5510 itr_val = 0x4;
5511
5512 if (adapter->hw.mac.type == e1000_82575)
5513 itr_val |= itr_val << 16;
5514 else
5515 itr_val |= E1000_EITR_CNT_IGNR;
5516
5517 writel(itr_val, q_vector->itr_register);
5518 q_vector->set_itr = 0;
5519 }
5520
5521 static irqreturn_t igb_msix_ring(int irq, void *data)
5522 {
5523 struct igb_q_vector *q_vector = data;
5524
5525 /* Write the ITR value calculated from the previous interrupt. */
5526 igb_write_itr(q_vector);
5527
5528 napi_schedule(&q_vector->napi);
5529
5530 return IRQ_HANDLED;
5531 }
5532
5533 #ifdef CONFIG_IGB_DCA
5534 static void igb_update_tx_dca(struct igb_adapter *adapter,
5535 struct igb_ring *tx_ring,
5536 int cpu)
5537 {
5538 struct e1000_hw *hw = &adapter->hw;
5539 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5540
5541 if (hw->mac.type != e1000_82575)
5542 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5543
5544 /* We can enable relaxed ordering for reads, but not writes when
5545 * DCA is enabled. This is due to a known issue in some chipsets
5546 * which will cause the DCA tag to be cleared.
5547 */
5548 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5549 E1000_DCA_TXCTRL_DATA_RRO_EN |
5550 E1000_DCA_TXCTRL_DESC_DCA_EN;
5551
5552 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5553 }
5554
5555 static void igb_update_rx_dca(struct igb_adapter *adapter,
5556 struct igb_ring *rx_ring,
5557 int cpu)
5558 {
5559 struct e1000_hw *hw = &adapter->hw;
5560 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5561
5562 if (hw->mac.type != e1000_82575)
5563 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5564
5565 /* We can enable relaxed ordering for reads, but not writes when
5566 * DCA is enabled. This is due to a known issue in some chipsets
5567 * which will cause the DCA tag to be cleared.
5568 */
5569 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5570 E1000_DCA_RXCTRL_DESC_DCA_EN;
5571
5572 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5573 }
5574
5575 static void igb_update_dca(struct igb_q_vector *q_vector)
5576 {
5577 struct igb_adapter *adapter = q_vector->adapter;
5578 int cpu = get_cpu();
5579
5580 if (q_vector->cpu == cpu)
5581 goto out_no_update;
5582
5583 if (q_vector->tx.ring)
5584 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5585
5586 if (q_vector->rx.ring)
5587 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5588
5589 q_vector->cpu = cpu;
5590 out_no_update:
5591 put_cpu();
5592 }
5593
5594 static void igb_setup_dca(struct igb_adapter *adapter)
5595 {
5596 struct e1000_hw *hw = &adapter->hw;
5597 int i;
5598
5599 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5600 return;
5601
5602 /* Always use CB2 mode, difference is masked in the CB driver. */
5603 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5604
5605 for (i = 0; i < adapter->num_q_vectors; i++) {
5606 adapter->q_vector[i]->cpu = -1;
5607 igb_update_dca(adapter->q_vector[i]);
5608 }
5609 }
5610
5611 static int __igb_notify_dca(struct device *dev, void *data)
5612 {
5613 struct net_device *netdev = dev_get_drvdata(dev);
5614 struct igb_adapter *adapter = netdev_priv(netdev);
5615 struct pci_dev *pdev = adapter->pdev;
5616 struct e1000_hw *hw = &adapter->hw;
5617 unsigned long event = *(unsigned long *)data;
5618
5619 switch (event) {
5620 case DCA_PROVIDER_ADD:
5621 /* if already enabled, don't do it again */
5622 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5623 break;
5624 if (dca_add_requester(dev) == 0) {
5625 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5626 dev_info(&pdev->dev, "DCA enabled\n");
5627 igb_setup_dca(adapter);
5628 break;
5629 }
5630 /* Fall Through since DCA is disabled. */
5631 case DCA_PROVIDER_REMOVE:
5632 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5633 /* without this a class_device is left
5634 * hanging around in the sysfs model
5635 */
5636 dca_remove_requester(dev);
5637 dev_info(&pdev->dev, "DCA disabled\n");
5638 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5639 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5640 }
5641 break;
5642 }
5643
5644 return 0;
5645 }
5646
5647 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5648 void *p)
5649 {
5650 int ret_val;
5651
5652 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5653 __igb_notify_dca);
5654
5655 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5656 }
5657 #endif /* CONFIG_IGB_DCA */
5658
5659 #ifdef CONFIG_PCI_IOV
5660 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5661 {
5662 unsigned char mac_addr[ETH_ALEN];
5663
5664 eth_zero_addr(mac_addr);
5665 igb_set_vf_mac(adapter, vf, mac_addr);
5666
5667 /* By default spoof check is enabled for all VFs */
5668 adapter->vf_data[vf].spoofchk_enabled = true;
5669
5670 return 0;
5671 }
5672
5673 #endif
5674 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5675 {
5676 struct e1000_hw *hw = &adapter->hw;
5677 u32 ping;
5678 int i;
5679
5680 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5681 ping = E1000_PF_CONTROL_MSG;
5682 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5683 ping |= E1000_VT_MSGTYPE_CTS;
5684 igb_write_mbx(hw, &ping, 1, i);
5685 }
5686 }
5687
5688 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5689 {
5690 struct e1000_hw *hw = &adapter->hw;
5691 u32 vmolr = rd32(E1000_VMOLR(vf));
5692 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5693
5694 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5695 IGB_VF_FLAG_MULTI_PROMISC);
5696 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5697
5698 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5699 vmolr |= E1000_VMOLR_MPME;
5700 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5701 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5702 } else {
5703 /* if we have hashes and we are clearing a multicast promisc
5704 * flag we need to write the hashes to the MTA as this step
5705 * was previously skipped
5706 */
5707 if (vf_data->num_vf_mc_hashes > 30) {
5708 vmolr |= E1000_VMOLR_MPME;
5709 } else if (vf_data->num_vf_mc_hashes) {
5710 int j;
5711
5712 vmolr |= E1000_VMOLR_ROMPE;
5713 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5714 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5715 }
5716 }
5717
5718 wr32(E1000_VMOLR(vf), vmolr);
5719
5720 /* there are flags left unprocessed, likely not supported */
5721 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5722 return -EINVAL;
5723
5724 return 0;
5725 }
5726
5727 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5728 u32 *msgbuf, u32 vf)
5729 {
5730 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5731 u16 *hash_list = (u16 *)&msgbuf[1];
5732 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5733 int i;
5734
5735 /* salt away the number of multicast addresses assigned
5736 * to this VF for later use to restore when the PF multi cast
5737 * list changes
5738 */
5739 vf_data->num_vf_mc_hashes = n;
5740
5741 /* only up to 30 hash values supported */
5742 if (n > 30)
5743 n = 30;
5744
5745 /* store the hashes for later use */
5746 for (i = 0; i < n; i++)
5747 vf_data->vf_mc_hashes[i] = hash_list[i];
5748
5749 /* Flush and reset the mta with the new values */
5750 igb_set_rx_mode(adapter->netdev);
5751
5752 return 0;
5753 }
5754
5755 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5756 {
5757 struct e1000_hw *hw = &adapter->hw;
5758 struct vf_data_storage *vf_data;
5759 int i, j;
5760
5761 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5762 u32 vmolr = rd32(E1000_VMOLR(i));
5763
5764 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5765
5766 vf_data = &adapter->vf_data[i];
5767
5768 if ((vf_data->num_vf_mc_hashes > 30) ||
5769 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5770 vmolr |= E1000_VMOLR_MPME;
5771 } else if (vf_data->num_vf_mc_hashes) {
5772 vmolr |= E1000_VMOLR_ROMPE;
5773 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5774 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5775 }
5776 wr32(E1000_VMOLR(i), vmolr);
5777 }
5778 }
5779
5780 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5781 {
5782 struct e1000_hw *hw = &adapter->hw;
5783 u32 pool_mask, reg, vid;
5784 int i;
5785
5786 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5787
5788 /* Find the vlan filter for this id */
5789 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5790 reg = rd32(E1000_VLVF(i));
5791
5792 /* remove the vf from the pool */
5793 reg &= ~pool_mask;
5794
5795 /* if pool is empty then remove entry from vfta */
5796 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5797 (reg & E1000_VLVF_VLANID_ENABLE)) {
5798 reg = 0;
5799 vid = reg & E1000_VLVF_VLANID_MASK;
5800 igb_vfta_set(hw, vid, false);
5801 }
5802
5803 wr32(E1000_VLVF(i), reg);
5804 }
5805
5806 adapter->vf_data[vf].vlans_enabled = 0;
5807 }
5808
5809 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5810 {
5811 struct e1000_hw *hw = &adapter->hw;
5812 u32 reg, i;
5813
5814 /* The vlvf table only exists on 82576 hardware and newer */
5815 if (hw->mac.type < e1000_82576)
5816 return -1;
5817
5818 /* we only need to do this if VMDq is enabled */
5819 if (!adapter->vfs_allocated_count)
5820 return -1;
5821
5822 /* Find the vlan filter for this id */
5823 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5824 reg = rd32(E1000_VLVF(i));
5825 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5826 vid == (reg & E1000_VLVF_VLANID_MASK))
5827 break;
5828 }
5829
5830 if (add) {
5831 if (i == E1000_VLVF_ARRAY_SIZE) {
5832 /* Did not find a matching VLAN ID entry that was
5833 * enabled. Search for a free filter entry, i.e.
5834 * one without the enable bit set
5835 */
5836 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5837 reg = rd32(E1000_VLVF(i));
5838 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5839 break;
5840 }
5841 }
5842 if (i < E1000_VLVF_ARRAY_SIZE) {
5843 /* Found an enabled/available entry */
5844 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5845
5846 /* if !enabled we need to set this up in vfta */
5847 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5848 /* add VID to filter table */
5849 igb_vfta_set(hw, vid, true);
5850 reg |= E1000_VLVF_VLANID_ENABLE;
5851 }
5852 reg &= ~E1000_VLVF_VLANID_MASK;
5853 reg |= vid;
5854 wr32(E1000_VLVF(i), reg);
5855
5856 /* do not modify RLPML for PF devices */
5857 if (vf >= adapter->vfs_allocated_count)
5858 return 0;
5859
5860 if (!adapter->vf_data[vf].vlans_enabled) {
5861 u32 size;
5862
5863 reg = rd32(E1000_VMOLR(vf));
5864 size = reg & E1000_VMOLR_RLPML_MASK;
5865 size += 4;
5866 reg &= ~E1000_VMOLR_RLPML_MASK;
5867 reg |= size;
5868 wr32(E1000_VMOLR(vf), reg);
5869 }
5870
5871 adapter->vf_data[vf].vlans_enabled++;
5872 }
5873 } else {
5874 if (i < E1000_VLVF_ARRAY_SIZE) {
5875 /* remove vf from the pool */
5876 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5877 /* if pool is empty then remove entry from vfta */
5878 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5879 reg = 0;
5880 igb_vfta_set(hw, vid, false);
5881 }
5882 wr32(E1000_VLVF(i), reg);
5883
5884 /* do not modify RLPML for PF devices */
5885 if (vf >= adapter->vfs_allocated_count)
5886 return 0;
5887
5888 adapter->vf_data[vf].vlans_enabled--;
5889 if (!adapter->vf_data[vf].vlans_enabled) {
5890 u32 size;
5891
5892 reg = rd32(E1000_VMOLR(vf));
5893 size = reg & E1000_VMOLR_RLPML_MASK;
5894 size -= 4;
5895 reg &= ~E1000_VMOLR_RLPML_MASK;
5896 reg |= size;
5897 wr32(E1000_VMOLR(vf), reg);
5898 }
5899 }
5900 }
5901 return 0;
5902 }
5903
5904 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5905 {
5906 struct e1000_hw *hw = &adapter->hw;
5907
5908 if (vid)
5909 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5910 else
5911 wr32(E1000_VMVIR(vf), 0);
5912 }
5913
5914 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5915 int vf, u16 vlan, u8 qos)
5916 {
5917 int err = 0;
5918 struct igb_adapter *adapter = netdev_priv(netdev);
5919
5920 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5921 return -EINVAL;
5922 if (vlan || qos) {
5923 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5924 if (err)
5925 goto out;
5926 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5927 igb_set_vmolr(adapter, vf, !vlan);
5928 adapter->vf_data[vf].pf_vlan = vlan;
5929 adapter->vf_data[vf].pf_qos = qos;
5930 dev_info(&adapter->pdev->dev,
5931 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5932 if (test_bit(__IGB_DOWN, &adapter->state)) {
5933 dev_warn(&adapter->pdev->dev,
5934 "The VF VLAN has been set, but the PF device is not up.\n");
5935 dev_warn(&adapter->pdev->dev,
5936 "Bring the PF device up before attempting to use the VF device.\n");
5937 }
5938 } else {
5939 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5940 false, vf);
5941 igb_set_vmvir(adapter, vlan, vf);
5942 igb_set_vmolr(adapter, vf, true);
5943 adapter->vf_data[vf].pf_vlan = 0;
5944 adapter->vf_data[vf].pf_qos = 0;
5945 }
5946 out:
5947 return err;
5948 }
5949
5950 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5951 {
5952 struct e1000_hw *hw = &adapter->hw;
5953 int i;
5954 u32 reg;
5955
5956 /* Find the vlan filter for this id */
5957 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5958 reg = rd32(E1000_VLVF(i));
5959 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5960 vid == (reg & E1000_VLVF_VLANID_MASK))
5961 break;
5962 }
5963
5964 if (i >= E1000_VLVF_ARRAY_SIZE)
5965 i = -1;
5966
5967 return i;
5968 }
5969
5970 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5971 {
5972 struct e1000_hw *hw = &adapter->hw;
5973 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5974 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5975 int err = 0;
5976
5977 /* If in promiscuous mode we need to make sure the PF also has
5978 * the VLAN filter set.
5979 */
5980 if (add && (adapter->netdev->flags & IFF_PROMISC))
5981 err = igb_vlvf_set(adapter, vid, add,
5982 adapter->vfs_allocated_count);
5983 if (err)
5984 goto out;
5985
5986 err = igb_vlvf_set(adapter, vid, add, vf);
5987
5988 if (err)
5989 goto out;
5990
5991 /* Go through all the checks to see if the VLAN filter should
5992 * be wiped completely.
5993 */
5994 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5995 u32 vlvf, bits;
5996 int regndx = igb_find_vlvf_entry(adapter, vid);
5997
5998 if (regndx < 0)
5999 goto out;
6000 /* See if any other pools are set for this VLAN filter
6001 * entry other than the PF.
6002 */
6003 vlvf = bits = rd32(E1000_VLVF(regndx));
6004 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6005 adapter->vfs_allocated_count);
6006 /* If the filter was removed then ensure PF pool bit
6007 * is cleared if the PF only added itself to the pool
6008 * because the PF is in promiscuous mode.
6009 */
6010 if ((vlvf & VLAN_VID_MASK) == vid &&
6011 !test_bit(vid, adapter->active_vlans) &&
6012 !bits)
6013 igb_vlvf_set(adapter, vid, add,
6014 adapter->vfs_allocated_count);
6015 }
6016
6017 out:
6018 return err;
6019 }
6020
6021 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6022 {
6023 /* clear flags - except flag that indicates PF has set the MAC */
6024 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
6025 adapter->vf_data[vf].last_nack = jiffies;
6026
6027 /* reset offloads to defaults */
6028 igb_set_vmolr(adapter, vf, true);
6029
6030 /* reset vlans for device */
6031 igb_clear_vf_vfta(adapter, vf);
6032 if (adapter->vf_data[vf].pf_vlan)
6033 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6034 adapter->vf_data[vf].pf_vlan,
6035 adapter->vf_data[vf].pf_qos);
6036 else
6037 igb_clear_vf_vfta(adapter, vf);
6038
6039 /* reset multicast table array for vf */
6040 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6041
6042 /* Flush and reset the mta with the new values */
6043 igb_set_rx_mode(adapter->netdev);
6044 }
6045
6046 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6047 {
6048 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6049
6050 /* clear mac address as we were hotplug removed/added */
6051 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6052 eth_zero_addr(vf_mac);
6053
6054 /* process remaining reset events */
6055 igb_vf_reset(adapter, vf);
6056 }
6057
6058 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6059 {
6060 struct e1000_hw *hw = &adapter->hw;
6061 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6062 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6063 u32 reg, msgbuf[3];
6064 u8 *addr = (u8 *)(&msgbuf[1]);
6065
6066 /* process all the same items cleared in a function level reset */
6067 igb_vf_reset(adapter, vf);
6068
6069 /* set vf mac address */
6070 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6071
6072 /* enable transmit and receive for vf */
6073 reg = rd32(E1000_VFTE);
6074 wr32(E1000_VFTE, reg | (1 << vf));
6075 reg = rd32(E1000_VFRE);
6076 wr32(E1000_VFRE, reg | (1 << vf));
6077
6078 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6079
6080 /* reply to reset with ack and vf mac address */
6081 if (!is_zero_ether_addr(vf_mac)) {
6082 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6083 memcpy(addr, vf_mac, ETH_ALEN);
6084 } else {
6085 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6086 }
6087 igb_write_mbx(hw, msgbuf, 3, vf);
6088 }
6089
6090 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6091 {
6092 /* The VF MAC Address is stored in a packed array of bytes
6093 * starting at the second 32 bit word of the msg array
6094 */
6095 unsigned char *addr = (char *)&msg[1];
6096 int err = -1;
6097
6098 if (is_valid_ether_addr(addr))
6099 err = igb_set_vf_mac(adapter, vf, addr);
6100
6101 return err;
6102 }
6103
6104 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6105 {
6106 struct e1000_hw *hw = &adapter->hw;
6107 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6108 u32 msg = E1000_VT_MSGTYPE_NACK;
6109
6110 /* if device isn't clear to send it shouldn't be reading either */
6111 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6112 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6113 igb_write_mbx(hw, &msg, 1, vf);
6114 vf_data->last_nack = jiffies;
6115 }
6116 }
6117
6118 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6119 {
6120 struct pci_dev *pdev = adapter->pdev;
6121 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6122 struct e1000_hw *hw = &adapter->hw;
6123 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6124 s32 retval;
6125
6126 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6127
6128 if (retval) {
6129 /* if receive failed revoke VF CTS stats and restart init */
6130 dev_err(&pdev->dev, "Error receiving message from VF\n");
6131 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6132 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6133 return;
6134 goto out;
6135 }
6136
6137 /* this is a message we already processed, do nothing */
6138 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6139 return;
6140
6141 /* until the vf completes a reset it should not be
6142 * allowed to start any configuration.
6143 */
6144 if (msgbuf[0] == E1000_VF_RESET) {
6145 igb_vf_reset_msg(adapter, vf);
6146 return;
6147 }
6148
6149 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6150 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6151 return;
6152 retval = -1;
6153 goto out;
6154 }
6155
6156 switch ((msgbuf[0] & 0xFFFF)) {
6157 case E1000_VF_SET_MAC_ADDR:
6158 retval = -EINVAL;
6159 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6160 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6161 else
6162 dev_warn(&pdev->dev,
6163 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6164 vf);
6165 break;
6166 case E1000_VF_SET_PROMISC:
6167 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6168 break;
6169 case E1000_VF_SET_MULTICAST:
6170 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6171 break;
6172 case E1000_VF_SET_LPE:
6173 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6174 break;
6175 case E1000_VF_SET_VLAN:
6176 retval = -1;
6177 if (vf_data->pf_vlan)
6178 dev_warn(&pdev->dev,
6179 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6180 vf);
6181 else
6182 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6183 break;
6184 default:
6185 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6186 retval = -1;
6187 break;
6188 }
6189
6190 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6191 out:
6192 /* notify the VF of the results of what it sent us */
6193 if (retval)
6194 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6195 else
6196 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6197
6198 igb_write_mbx(hw, msgbuf, 1, vf);
6199 }
6200
6201 static void igb_msg_task(struct igb_adapter *adapter)
6202 {
6203 struct e1000_hw *hw = &adapter->hw;
6204 u32 vf;
6205
6206 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6207 /* process any reset requests */
6208 if (!igb_check_for_rst(hw, vf))
6209 igb_vf_reset_event(adapter, vf);
6210
6211 /* process any messages pending */
6212 if (!igb_check_for_msg(hw, vf))
6213 igb_rcv_msg_from_vf(adapter, vf);
6214
6215 /* process any acks */
6216 if (!igb_check_for_ack(hw, vf))
6217 igb_rcv_ack_from_vf(adapter, vf);
6218 }
6219 }
6220
6221 /**
6222 * igb_set_uta - Set unicast filter table address
6223 * @adapter: board private structure
6224 *
6225 * The unicast table address is a register array of 32-bit registers.
6226 * The table is meant to be used in a way similar to how the MTA is used
6227 * however due to certain limitations in the hardware it is necessary to
6228 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6229 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6230 **/
6231 static void igb_set_uta(struct igb_adapter *adapter)
6232 {
6233 struct e1000_hw *hw = &adapter->hw;
6234 int i;
6235
6236 /* The UTA table only exists on 82576 hardware and newer */
6237 if (hw->mac.type < e1000_82576)
6238 return;
6239
6240 /* we only need to do this if VMDq is enabled */
6241 if (!adapter->vfs_allocated_count)
6242 return;
6243
6244 for (i = 0; i < hw->mac.uta_reg_count; i++)
6245 array_wr32(E1000_UTA, i, ~0);
6246 }
6247
6248 /**
6249 * igb_intr_msi - Interrupt Handler
6250 * @irq: interrupt number
6251 * @data: pointer to a network interface device structure
6252 **/
6253 static irqreturn_t igb_intr_msi(int irq, void *data)
6254 {
6255 struct igb_adapter *adapter = data;
6256 struct igb_q_vector *q_vector = adapter->q_vector[0];
6257 struct e1000_hw *hw = &adapter->hw;
6258 /* read ICR disables interrupts using IAM */
6259 u32 icr = rd32(E1000_ICR);
6260
6261 igb_write_itr(q_vector);
6262
6263 if (icr & E1000_ICR_DRSTA)
6264 schedule_work(&adapter->reset_task);
6265
6266 if (icr & E1000_ICR_DOUTSYNC) {
6267 /* HW is reporting DMA is out of sync */
6268 adapter->stats.doosync++;
6269 }
6270
6271 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6272 hw->mac.get_link_status = 1;
6273 if (!test_bit(__IGB_DOWN, &adapter->state))
6274 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6275 }
6276
6277 if (icr & E1000_ICR_TS)
6278 igb_tsync_interrupt(adapter);
6279
6280 napi_schedule(&q_vector->napi);
6281
6282 return IRQ_HANDLED;
6283 }
6284
6285 /**
6286 * igb_intr - Legacy Interrupt Handler
6287 * @irq: interrupt number
6288 * @data: pointer to a network interface device structure
6289 **/
6290 static irqreturn_t igb_intr(int irq, void *data)
6291 {
6292 struct igb_adapter *adapter = data;
6293 struct igb_q_vector *q_vector = adapter->q_vector[0];
6294 struct e1000_hw *hw = &adapter->hw;
6295 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6296 * need for the IMC write
6297 */
6298 u32 icr = rd32(E1000_ICR);
6299
6300 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6301 * not set, then the adapter didn't send an interrupt
6302 */
6303 if (!(icr & E1000_ICR_INT_ASSERTED))
6304 return IRQ_NONE;
6305
6306 igb_write_itr(q_vector);
6307
6308 if (icr & E1000_ICR_DRSTA)
6309 schedule_work(&adapter->reset_task);
6310
6311 if (icr & E1000_ICR_DOUTSYNC) {
6312 /* HW is reporting DMA is out of sync */
6313 adapter->stats.doosync++;
6314 }
6315
6316 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6317 hw->mac.get_link_status = 1;
6318 /* guard against interrupt when we're going down */
6319 if (!test_bit(__IGB_DOWN, &adapter->state))
6320 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6321 }
6322
6323 if (icr & E1000_ICR_TS)
6324 igb_tsync_interrupt(adapter);
6325
6326 napi_schedule(&q_vector->napi);
6327
6328 return IRQ_HANDLED;
6329 }
6330
6331 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6332 {
6333 struct igb_adapter *adapter = q_vector->adapter;
6334 struct e1000_hw *hw = &adapter->hw;
6335
6336 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6337 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6338 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6339 igb_set_itr(q_vector);
6340 else
6341 igb_update_ring_itr(q_vector);
6342 }
6343
6344 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6345 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6346 wr32(E1000_EIMS, q_vector->eims_value);
6347 else
6348 igb_irq_enable(adapter);
6349 }
6350 }
6351
6352 /**
6353 * igb_poll - NAPI Rx polling callback
6354 * @napi: napi polling structure
6355 * @budget: count of how many packets we should handle
6356 **/
6357 static int igb_poll(struct napi_struct *napi, int budget)
6358 {
6359 struct igb_q_vector *q_vector = container_of(napi,
6360 struct igb_q_vector,
6361 napi);
6362 bool clean_complete = true;
6363
6364 #ifdef CONFIG_IGB_DCA
6365 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6366 igb_update_dca(q_vector);
6367 #endif
6368 if (q_vector->tx.ring)
6369 clean_complete = igb_clean_tx_irq(q_vector);
6370
6371 if (q_vector->rx.ring)
6372 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6373
6374 /* If all work not completed, return budget and keep polling */
6375 if (!clean_complete)
6376 return budget;
6377
6378 /* If not enough Rx work done, exit the polling mode */
6379 napi_complete(napi);
6380 igb_ring_irq_enable(q_vector);
6381
6382 return 0;
6383 }
6384
6385 /**
6386 * igb_clean_tx_irq - Reclaim resources after transmit completes
6387 * @q_vector: pointer to q_vector containing needed info
6388 *
6389 * returns true if ring is completely cleaned
6390 **/
6391 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6392 {
6393 struct igb_adapter *adapter = q_vector->adapter;
6394 struct igb_ring *tx_ring = q_vector->tx.ring;
6395 struct igb_tx_buffer *tx_buffer;
6396 union e1000_adv_tx_desc *tx_desc;
6397 unsigned int total_bytes = 0, total_packets = 0;
6398 unsigned int budget = q_vector->tx.work_limit;
6399 unsigned int i = tx_ring->next_to_clean;
6400
6401 if (test_bit(__IGB_DOWN, &adapter->state))
6402 return true;
6403
6404 tx_buffer = &tx_ring->tx_buffer_info[i];
6405 tx_desc = IGB_TX_DESC(tx_ring, i);
6406 i -= tx_ring->count;
6407
6408 do {
6409 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6410
6411 /* if next_to_watch is not set then there is no work pending */
6412 if (!eop_desc)
6413 break;
6414
6415 /* prevent any other reads prior to eop_desc */
6416 read_barrier_depends();
6417
6418 /* if DD is not set pending work has not been completed */
6419 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6420 break;
6421
6422 /* clear next_to_watch to prevent false hangs */
6423 tx_buffer->next_to_watch = NULL;
6424
6425 /* update the statistics for this packet */
6426 total_bytes += tx_buffer->bytecount;
6427 total_packets += tx_buffer->gso_segs;
6428
6429 /* free the skb */
6430 dev_consume_skb_any(tx_buffer->skb);
6431
6432 /* unmap skb header data */
6433 dma_unmap_single(tx_ring->dev,
6434 dma_unmap_addr(tx_buffer, dma),
6435 dma_unmap_len(tx_buffer, len),
6436 DMA_TO_DEVICE);
6437
6438 /* clear tx_buffer data */
6439 tx_buffer->skb = NULL;
6440 dma_unmap_len_set(tx_buffer, len, 0);
6441
6442 /* clear last DMA location and unmap remaining buffers */
6443 while (tx_desc != eop_desc) {
6444 tx_buffer++;
6445 tx_desc++;
6446 i++;
6447 if (unlikely(!i)) {
6448 i -= tx_ring->count;
6449 tx_buffer = tx_ring->tx_buffer_info;
6450 tx_desc = IGB_TX_DESC(tx_ring, 0);
6451 }
6452
6453 /* unmap any remaining paged data */
6454 if (dma_unmap_len(tx_buffer, len)) {
6455 dma_unmap_page(tx_ring->dev,
6456 dma_unmap_addr(tx_buffer, dma),
6457 dma_unmap_len(tx_buffer, len),
6458 DMA_TO_DEVICE);
6459 dma_unmap_len_set(tx_buffer, len, 0);
6460 }
6461 }
6462
6463 /* move us one more past the eop_desc for start of next pkt */
6464 tx_buffer++;
6465 tx_desc++;
6466 i++;
6467 if (unlikely(!i)) {
6468 i -= tx_ring->count;
6469 tx_buffer = tx_ring->tx_buffer_info;
6470 tx_desc = IGB_TX_DESC(tx_ring, 0);
6471 }
6472
6473 /* issue prefetch for next Tx descriptor */
6474 prefetch(tx_desc);
6475
6476 /* update budget accounting */
6477 budget--;
6478 } while (likely(budget));
6479
6480 netdev_tx_completed_queue(txring_txq(tx_ring),
6481 total_packets, total_bytes);
6482 i += tx_ring->count;
6483 tx_ring->next_to_clean = i;
6484 u64_stats_update_begin(&tx_ring->tx_syncp);
6485 tx_ring->tx_stats.bytes += total_bytes;
6486 tx_ring->tx_stats.packets += total_packets;
6487 u64_stats_update_end(&tx_ring->tx_syncp);
6488 q_vector->tx.total_bytes += total_bytes;
6489 q_vector->tx.total_packets += total_packets;
6490
6491 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6492 struct e1000_hw *hw = &adapter->hw;
6493
6494 /* Detect a transmit hang in hardware, this serializes the
6495 * check with the clearing of time_stamp and movement of i
6496 */
6497 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6498 if (tx_buffer->next_to_watch &&
6499 time_after(jiffies, tx_buffer->time_stamp +
6500 (adapter->tx_timeout_factor * HZ)) &&
6501 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6502
6503 /* detected Tx unit hang */
6504 dev_err(tx_ring->dev,
6505 "Detected Tx Unit Hang\n"
6506 " Tx Queue <%d>\n"
6507 " TDH <%x>\n"
6508 " TDT <%x>\n"
6509 " next_to_use <%x>\n"
6510 " next_to_clean <%x>\n"
6511 "buffer_info[next_to_clean]\n"
6512 " time_stamp <%lx>\n"
6513 " next_to_watch <%p>\n"
6514 " jiffies <%lx>\n"
6515 " desc.status <%x>\n",
6516 tx_ring->queue_index,
6517 rd32(E1000_TDH(tx_ring->reg_idx)),
6518 readl(tx_ring->tail),
6519 tx_ring->next_to_use,
6520 tx_ring->next_to_clean,
6521 tx_buffer->time_stamp,
6522 tx_buffer->next_to_watch,
6523 jiffies,
6524 tx_buffer->next_to_watch->wb.status);
6525 netif_stop_subqueue(tx_ring->netdev,
6526 tx_ring->queue_index);
6527
6528 /* we are about to reset, no point in enabling stuff */
6529 return true;
6530 }
6531 }
6532
6533 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6534 if (unlikely(total_packets &&
6535 netif_carrier_ok(tx_ring->netdev) &&
6536 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6537 /* Make sure that anybody stopping the queue after this
6538 * sees the new next_to_clean.
6539 */
6540 smp_mb();
6541 if (__netif_subqueue_stopped(tx_ring->netdev,
6542 tx_ring->queue_index) &&
6543 !(test_bit(__IGB_DOWN, &adapter->state))) {
6544 netif_wake_subqueue(tx_ring->netdev,
6545 tx_ring->queue_index);
6546
6547 u64_stats_update_begin(&tx_ring->tx_syncp);
6548 tx_ring->tx_stats.restart_queue++;
6549 u64_stats_update_end(&tx_ring->tx_syncp);
6550 }
6551 }
6552
6553 return !!budget;
6554 }
6555
6556 /**
6557 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6558 * @rx_ring: rx descriptor ring to store buffers on
6559 * @old_buff: donor buffer to have page reused
6560 *
6561 * Synchronizes page for reuse by the adapter
6562 **/
6563 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6564 struct igb_rx_buffer *old_buff)
6565 {
6566 struct igb_rx_buffer *new_buff;
6567 u16 nta = rx_ring->next_to_alloc;
6568
6569 new_buff = &rx_ring->rx_buffer_info[nta];
6570
6571 /* update, and store next to alloc */
6572 nta++;
6573 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6574
6575 /* transfer page from old buffer to new buffer */
6576 *new_buff = *old_buff;
6577
6578 /* sync the buffer for use by the device */
6579 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6580 old_buff->page_offset,
6581 IGB_RX_BUFSZ,
6582 DMA_FROM_DEVICE);
6583 }
6584
6585 static inline bool igb_page_is_reserved(struct page *page)
6586 {
6587 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
6588 }
6589
6590 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6591 struct page *page,
6592 unsigned int truesize)
6593 {
6594 /* avoid re-using remote pages */
6595 if (unlikely(igb_page_is_reserved(page)))
6596 return false;
6597
6598 #if (PAGE_SIZE < 8192)
6599 /* if we are only owner of page we can reuse it */
6600 if (unlikely(page_count(page) != 1))
6601 return false;
6602
6603 /* flip page offset to other buffer */
6604 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6605 #else
6606 /* move offset up to the next cache line */
6607 rx_buffer->page_offset += truesize;
6608
6609 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6610 return false;
6611 #endif
6612
6613 /* Even if we own the page, we are not allowed to use atomic_set()
6614 * This would break get_page_unless_zero() users.
6615 */
6616 atomic_inc(&page->_count);
6617
6618 return true;
6619 }
6620
6621 /**
6622 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6623 * @rx_ring: rx descriptor ring to transact packets on
6624 * @rx_buffer: buffer containing page to add
6625 * @rx_desc: descriptor containing length of buffer written by hardware
6626 * @skb: sk_buff to place the data into
6627 *
6628 * This function will add the data contained in rx_buffer->page to the skb.
6629 * This is done either through a direct copy if the data in the buffer is
6630 * less than the skb header size, otherwise it will just attach the page as
6631 * a frag to the skb.
6632 *
6633 * The function will then update the page offset if necessary and return
6634 * true if the buffer can be reused by the adapter.
6635 **/
6636 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6637 struct igb_rx_buffer *rx_buffer,
6638 union e1000_adv_rx_desc *rx_desc,
6639 struct sk_buff *skb)
6640 {
6641 struct page *page = rx_buffer->page;
6642 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6643 #if (PAGE_SIZE < 8192)
6644 unsigned int truesize = IGB_RX_BUFSZ;
6645 #else
6646 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6647 #endif
6648
6649 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6650 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6651
6652 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6653 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6654 va += IGB_TS_HDR_LEN;
6655 size -= IGB_TS_HDR_LEN;
6656 }
6657
6658 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6659
6660 /* page is not reserved, we can reuse buffer as-is */
6661 if (likely(!igb_page_is_reserved(page)))
6662 return true;
6663
6664 /* this page cannot be reused so discard it */
6665 __free_page(page);
6666 return false;
6667 }
6668
6669 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6670 rx_buffer->page_offset, size, truesize);
6671
6672 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6673 }
6674
6675 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6676 union e1000_adv_rx_desc *rx_desc,
6677 struct sk_buff *skb)
6678 {
6679 struct igb_rx_buffer *rx_buffer;
6680 struct page *page;
6681
6682 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6683 page = rx_buffer->page;
6684 prefetchw(page);
6685
6686 if (likely(!skb)) {
6687 void *page_addr = page_address(page) +
6688 rx_buffer->page_offset;
6689
6690 /* prefetch first cache line of first page */
6691 prefetch(page_addr);
6692 #if L1_CACHE_BYTES < 128
6693 prefetch(page_addr + L1_CACHE_BYTES);
6694 #endif
6695
6696 /* allocate a skb to store the frags */
6697 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6698 if (unlikely(!skb)) {
6699 rx_ring->rx_stats.alloc_failed++;
6700 return NULL;
6701 }
6702
6703 /* we will be copying header into skb->data in
6704 * pskb_may_pull so it is in our interest to prefetch
6705 * it now to avoid a possible cache miss
6706 */
6707 prefetchw(skb->data);
6708 }
6709
6710 /* we are reusing so sync this buffer for CPU use */
6711 dma_sync_single_range_for_cpu(rx_ring->dev,
6712 rx_buffer->dma,
6713 rx_buffer->page_offset,
6714 IGB_RX_BUFSZ,
6715 DMA_FROM_DEVICE);
6716
6717 /* pull page into skb */
6718 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6719 /* hand second half of page back to the ring */
6720 igb_reuse_rx_page(rx_ring, rx_buffer);
6721 } else {
6722 /* we are not reusing the buffer so unmap it */
6723 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6724 PAGE_SIZE, DMA_FROM_DEVICE);
6725 }
6726
6727 /* clear contents of rx_buffer */
6728 rx_buffer->page = NULL;
6729
6730 return skb;
6731 }
6732
6733 static inline void igb_rx_checksum(struct igb_ring *ring,
6734 union e1000_adv_rx_desc *rx_desc,
6735 struct sk_buff *skb)
6736 {
6737 skb_checksum_none_assert(skb);
6738
6739 /* Ignore Checksum bit is set */
6740 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6741 return;
6742
6743 /* Rx checksum disabled via ethtool */
6744 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6745 return;
6746
6747 /* TCP/UDP checksum error bit is set */
6748 if (igb_test_staterr(rx_desc,
6749 E1000_RXDEXT_STATERR_TCPE |
6750 E1000_RXDEXT_STATERR_IPE)) {
6751 /* work around errata with sctp packets where the TCPE aka
6752 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6753 * packets, (aka let the stack check the crc32c)
6754 */
6755 if (!((skb->len == 60) &&
6756 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6757 u64_stats_update_begin(&ring->rx_syncp);
6758 ring->rx_stats.csum_err++;
6759 u64_stats_update_end(&ring->rx_syncp);
6760 }
6761 /* let the stack verify checksum errors */
6762 return;
6763 }
6764 /* It must be a TCP or UDP packet with a valid checksum */
6765 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6766 E1000_RXD_STAT_UDPCS))
6767 skb->ip_summed = CHECKSUM_UNNECESSARY;
6768
6769 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6770 le32_to_cpu(rx_desc->wb.upper.status_error));
6771 }
6772
6773 static inline void igb_rx_hash(struct igb_ring *ring,
6774 union e1000_adv_rx_desc *rx_desc,
6775 struct sk_buff *skb)
6776 {
6777 if (ring->netdev->features & NETIF_F_RXHASH)
6778 skb_set_hash(skb,
6779 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6780 PKT_HASH_TYPE_L3);
6781 }
6782
6783 /**
6784 * igb_is_non_eop - process handling of non-EOP buffers
6785 * @rx_ring: Rx ring being processed
6786 * @rx_desc: Rx descriptor for current buffer
6787 * @skb: current socket buffer containing buffer in progress
6788 *
6789 * This function updates next to clean. If the buffer is an EOP buffer
6790 * this function exits returning false, otherwise it will place the
6791 * sk_buff in the next buffer to be chained and return true indicating
6792 * that this is in fact a non-EOP buffer.
6793 **/
6794 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6795 union e1000_adv_rx_desc *rx_desc)
6796 {
6797 u32 ntc = rx_ring->next_to_clean + 1;
6798
6799 /* fetch, update, and store next to clean */
6800 ntc = (ntc < rx_ring->count) ? ntc : 0;
6801 rx_ring->next_to_clean = ntc;
6802
6803 prefetch(IGB_RX_DESC(rx_ring, ntc));
6804
6805 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6806 return false;
6807
6808 return true;
6809 }
6810
6811 /**
6812 * igb_pull_tail - igb specific version of skb_pull_tail
6813 * @rx_ring: rx descriptor ring packet is being transacted on
6814 * @rx_desc: pointer to the EOP Rx descriptor
6815 * @skb: pointer to current skb being adjusted
6816 *
6817 * This function is an igb specific version of __pskb_pull_tail. The
6818 * main difference between this version and the original function is that
6819 * this function can make several assumptions about the state of things
6820 * that allow for significant optimizations versus the standard function.
6821 * As a result we can do things like drop a frag and maintain an accurate
6822 * truesize for the skb.
6823 */
6824 static void igb_pull_tail(struct igb_ring *rx_ring,
6825 union e1000_adv_rx_desc *rx_desc,
6826 struct sk_buff *skb)
6827 {
6828 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6829 unsigned char *va;
6830 unsigned int pull_len;
6831
6832 /* it is valid to use page_address instead of kmap since we are
6833 * working with pages allocated out of the lomem pool per
6834 * alloc_page(GFP_ATOMIC)
6835 */
6836 va = skb_frag_address(frag);
6837
6838 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6839 /* retrieve timestamp from buffer */
6840 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6841
6842 /* update pointers to remove timestamp header */
6843 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6844 frag->page_offset += IGB_TS_HDR_LEN;
6845 skb->data_len -= IGB_TS_HDR_LEN;
6846 skb->len -= IGB_TS_HDR_LEN;
6847
6848 /* move va to start of packet data */
6849 va += IGB_TS_HDR_LEN;
6850 }
6851
6852 /* we need the header to contain the greater of either ETH_HLEN or
6853 * 60 bytes if the skb->len is less than 60 for skb_pad.
6854 */
6855 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6856
6857 /* align pull length to size of long to optimize memcpy performance */
6858 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6859
6860 /* update all of the pointers */
6861 skb_frag_size_sub(frag, pull_len);
6862 frag->page_offset += pull_len;
6863 skb->data_len -= pull_len;
6864 skb->tail += pull_len;
6865 }
6866
6867 /**
6868 * igb_cleanup_headers - Correct corrupted or empty headers
6869 * @rx_ring: rx descriptor ring packet is being transacted on
6870 * @rx_desc: pointer to the EOP Rx descriptor
6871 * @skb: pointer to current skb being fixed
6872 *
6873 * Address the case where we are pulling data in on pages only
6874 * and as such no data is present in the skb header.
6875 *
6876 * In addition if skb is not at least 60 bytes we need to pad it so that
6877 * it is large enough to qualify as a valid Ethernet frame.
6878 *
6879 * Returns true if an error was encountered and skb was freed.
6880 **/
6881 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6882 union e1000_adv_rx_desc *rx_desc,
6883 struct sk_buff *skb)
6884 {
6885 if (unlikely((igb_test_staterr(rx_desc,
6886 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6887 struct net_device *netdev = rx_ring->netdev;
6888 if (!(netdev->features & NETIF_F_RXALL)) {
6889 dev_kfree_skb_any(skb);
6890 return true;
6891 }
6892 }
6893
6894 /* place header in linear portion of buffer */
6895 if (skb_is_nonlinear(skb))
6896 igb_pull_tail(rx_ring, rx_desc, skb);
6897
6898 /* if eth_skb_pad returns an error the skb was freed */
6899 if (eth_skb_pad(skb))
6900 return true;
6901
6902 return false;
6903 }
6904
6905 /**
6906 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6907 * @rx_ring: rx descriptor ring packet is being transacted on
6908 * @rx_desc: pointer to the EOP Rx descriptor
6909 * @skb: pointer to current skb being populated
6910 *
6911 * This function checks the ring, descriptor, and packet information in
6912 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6913 * other fields within the skb.
6914 **/
6915 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6916 union e1000_adv_rx_desc *rx_desc,
6917 struct sk_buff *skb)
6918 {
6919 struct net_device *dev = rx_ring->netdev;
6920
6921 igb_rx_hash(rx_ring, rx_desc, skb);
6922
6923 igb_rx_checksum(rx_ring, rx_desc, skb);
6924
6925 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6926 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6927 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6928
6929 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6930 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6931 u16 vid;
6932
6933 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6934 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6935 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6936 else
6937 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6938
6939 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6940 }
6941
6942 skb_record_rx_queue(skb, rx_ring->queue_index);
6943
6944 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6945 }
6946
6947 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6948 {
6949 struct igb_ring *rx_ring = q_vector->rx.ring;
6950 struct sk_buff *skb = rx_ring->skb;
6951 unsigned int total_bytes = 0, total_packets = 0;
6952 u16 cleaned_count = igb_desc_unused(rx_ring);
6953
6954 while (likely(total_packets < budget)) {
6955 union e1000_adv_rx_desc *rx_desc;
6956
6957 /* return some buffers to hardware, one at a time is too slow */
6958 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6959 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6960 cleaned_count = 0;
6961 }
6962
6963 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6964
6965 if (!rx_desc->wb.upper.status_error)
6966 break;
6967
6968 /* This memory barrier is needed to keep us from reading
6969 * any other fields out of the rx_desc until we know the
6970 * descriptor has been written back
6971 */
6972 dma_rmb();
6973
6974 /* retrieve a buffer from the ring */
6975 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6976
6977 /* exit if we failed to retrieve a buffer */
6978 if (!skb)
6979 break;
6980
6981 cleaned_count++;
6982
6983 /* fetch next buffer in frame if non-eop */
6984 if (igb_is_non_eop(rx_ring, rx_desc))
6985 continue;
6986
6987 /* verify the packet layout is correct */
6988 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6989 skb = NULL;
6990 continue;
6991 }
6992
6993 /* probably a little skewed due to removing CRC */
6994 total_bytes += skb->len;
6995
6996 /* populate checksum, timestamp, VLAN, and protocol */
6997 igb_process_skb_fields(rx_ring, rx_desc, skb);
6998
6999 napi_gro_receive(&q_vector->napi, skb);
7000
7001 /* reset skb pointer */
7002 skb = NULL;
7003
7004 /* update budget accounting */
7005 total_packets++;
7006 }
7007
7008 /* place incomplete frames back on ring for completion */
7009 rx_ring->skb = skb;
7010
7011 u64_stats_update_begin(&rx_ring->rx_syncp);
7012 rx_ring->rx_stats.packets += total_packets;
7013 rx_ring->rx_stats.bytes += total_bytes;
7014 u64_stats_update_end(&rx_ring->rx_syncp);
7015 q_vector->rx.total_packets += total_packets;
7016 q_vector->rx.total_bytes += total_bytes;
7017
7018 if (cleaned_count)
7019 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7020
7021 return total_packets < budget;
7022 }
7023
7024 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
7025 struct igb_rx_buffer *bi)
7026 {
7027 struct page *page = bi->page;
7028 dma_addr_t dma;
7029
7030 /* since we are recycling buffers we should seldom need to alloc */
7031 if (likely(page))
7032 return true;
7033
7034 /* alloc new page for storage */
7035 page = dev_alloc_page();
7036 if (unlikely(!page)) {
7037 rx_ring->rx_stats.alloc_failed++;
7038 return false;
7039 }
7040
7041 /* map page for use */
7042 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7043
7044 /* if mapping failed free memory back to system since
7045 * there isn't much point in holding memory we can't use
7046 */
7047 if (dma_mapping_error(rx_ring->dev, dma)) {
7048 __free_page(page);
7049
7050 rx_ring->rx_stats.alloc_failed++;
7051 return false;
7052 }
7053
7054 bi->dma = dma;
7055 bi->page = page;
7056 bi->page_offset = 0;
7057
7058 return true;
7059 }
7060
7061 /**
7062 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7063 * @adapter: address of board private structure
7064 **/
7065 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7066 {
7067 union e1000_adv_rx_desc *rx_desc;
7068 struct igb_rx_buffer *bi;
7069 u16 i = rx_ring->next_to_use;
7070
7071 /* nothing to do */
7072 if (!cleaned_count)
7073 return;
7074
7075 rx_desc = IGB_RX_DESC(rx_ring, i);
7076 bi = &rx_ring->rx_buffer_info[i];
7077 i -= rx_ring->count;
7078
7079 do {
7080 if (!igb_alloc_mapped_page(rx_ring, bi))
7081 break;
7082
7083 /* Refresh the desc even if buffer_addrs didn't change
7084 * because each write-back erases this info.
7085 */
7086 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7087
7088 rx_desc++;
7089 bi++;
7090 i++;
7091 if (unlikely(!i)) {
7092 rx_desc = IGB_RX_DESC(rx_ring, 0);
7093 bi = rx_ring->rx_buffer_info;
7094 i -= rx_ring->count;
7095 }
7096
7097 /* clear the status bits for the next_to_use descriptor */
7098 rx_desc->wb.upper.status_error = 0;
7099
7100 cleaned_count--;
7101 } while (cleaned_count);
7102
7103 i += rx_ring->count;
7104
7105 if (rx_ring->next_to_use != i) {
7106 /* record the next descriptor to use */
7107 rx_ring->next_to_use = i;
7108
7109 /* update next to alloc since we have filled the ring */
7110 rx_ring->next_to_alloc = i;
7111
7112 /* Force memory writes to complete before letting h/w
7113 * know there are new descriptors to fetch. (Only
7114 * applicable for weak-ordered memory model archs,
7115 * such as IA-64).
7116 */
7117 wmb();
7118 writel(i, rx_ring->tail);
7119 }
7120 }
7121
7122 /**
7123 * igb_mii_ioctl -
7124 * @netdev:
7125 * @ifreq:
7126 * @cmd:
7127 **/
7128 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7129 {
7130 struct igb_adapter *adapter = netdev_priv(netdev);
7131 struct mii_ioctl_data *data = if_mii(ifr);
7132
7133 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7134 return -EOPNOTSUPP;
7135
7136 switch (cmd) {
7137 case SIOCGMIIPHY:
7138 data->phy_id = adapter->hw.phy.addr;
7139 break;
7140 case SIOCGMIIREG:
7141 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7142 &data->val_out))
7143 return -EIO;
7144 break;
7145 case SIOCSMIIREG:
7146 default:
7147 return -EOPNOTSUPP;
7148 }
7149 return 0;
7150 }
7151
7152 /**
7153 * igb_ioctl -
7154 * @netdev:
7155 * @ifreq:
7156 * @cmd:
7157 **/
7158 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7159 {
7160 switch (cmd) {
7161 case SIOCGMIIPHY:
7162 case SIOCGMIIREG:
7163 case SIOCSMIIREG:
7164 return igb_mii_ioctl(netdev, ifr, cmd);
7165 case SIOCGHWTSTAMP:
7166 return igb_ptp_get_ts_config(netdev, ifr);
7167 case SIOCSHWTSTAMP:
7168 return igb_ptp_set_ts_config(netdev, ifr);
7169 default:
7170 return -EOPNOTSUPP;
7171 }
7172 }
7173
7174 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7175 {
7176 struct igb_adapter *adapter = hw->back;
7177
7178 pci_read_config_word(adapter->pdev, reg, value);
7179 }
7180
7181 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7182 {
7183 struct igb_adapter *adapter = hw->back;
7184
7185 pci_write_config_word(adapter->pdev, reg, *value);
7186 }
7187
7188 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7189 {
7190 struct igb_adapter *adapter = hw->back;
7191
7192 if (pcie_capability_read_word(adapter->pdev, reg, value))
7193 return -E1000_ERR_CONFIG;
7194
7195 return 0;
7196 }
7197
7198 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7199 {
7200 struct igb_adapter *adapter = hw->back;
7201
7202 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7203 return -E1000_ERR_CONFIG;
7204
7205 return 0;
7206 }
7207
7208 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7209 {
7210 struct igb_adapter *adapter = netdev_priv(netdev);
7211 struct e1000_hw *hw = &adapter->hw;
7212 u32 ctrl, rctl;
7213 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7214
7215 if (enable) {
7216 /* enable VLAN tag insert/strip */
7217 ctrl = rd32(E1000_CTRL);
7218 ctrl |= E1000_CTRL_VME;
7219 wr32(E1000_CTRL, ctrl);
7220
7221 /* Disable CFI check */
7222 rctl = rd32(E1000_RCTL);
7223 rctl &= ~E1000_RCTL_CFIEN;
7224 wr32(E1000_RCTL, rctl);
7225 } else {
7226 /* disable VLAN tag insert/strip */
7227 ctrl = rd32(E1000_CTRL);
7228 ctrl &= ~E1000_CTRL_VME;
7229 wr32(E1000_CTRL, ctrl);
7230 }
7231
7232 igb_rlpml_set(adapter);
7233 }
7234
7235 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7236 __be16 proto, u16 vid)
7237 {
7238 struct igb_adapter *adapter = netdev_priv(netdev);
7239 struct e1000_hw *hw = &adapter->hw;
7240 int pf_id = adapter->vfs_allocated_count;
7241
7242 /* attempt to add filter to vlvf array */
7243 igb_vlvf_set(adapter, vid, true, pf_id);
7244
7245 /* add the filter since PF can receive vlans w/o entry in vlvf */
7246 igb_vfta_set(hw, vid, true);
7247
7248 set_bit(vid, adapter->active_vlans);
7249
7250 return 0;
7251 }
7252
7253 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7254 __be16 proto, u16 vid)
7255 {
7256 struct igb_adapter *adapter = netdev_priv(netdev);
7257 struct e1000_hw *hw = &adapter->hw;
7258 int pf_id = adapter->vfs_allocated_count;
7259 s32 err;
7260
7261 /* remove vlan from VLVF table array */
7262 err = igb_vlvf_set(adapter, vid, false, pf_id);
7263
7264 /* if vid was not present in VLVF just remove it from table */
7265 if (err)
7266 igb_vfta_set(hw, vid, false);
7267
7268 clear_bit(vid, adapter->active_vlans);
7269
7270 return 0;
7271 }
7272
7273 static void igb_restore_vlan(struct igb_adapter *adapter)
7274 {
7275 u16 vid;
7276
7277 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7278
7279 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7280 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7281 }
7282
7283 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7284 {
7285 struct pci_dev *pdev = adapter->pdev;
7286 struct e1000_mac_info *mac = &adapter->hw.mac;
7287
7288 mac->autoneg = 0;
7289
7290 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7291 * for the switch() below to work
7292 */
7293 if ((spd & 1) || (dplx & ~1))
7294 goto err_inval;
7295
7296 /* Fiber NIC's only allow 1000 gbps Full duplex
7297 * and 100Mbps Full duplex for 100baseFx sfp
7298 */
7299 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7300 switch (spd + dplx) {
7301 case SPEED_10 + DUPLEX_HALF:
7302 case SPEED_10 + DUPLEX_FULL:
7303 case SPEED_100 + DUPLEX_HALF:
7304 goto err_inval;
7305 default:
7306 break;
7307 }
7308 }
7309
7310 switch (spd + dplx) {
7311 case SPEED_10 + DUPLEX_HALF:
7312 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7313 break;
7314 case SPEED_10 + DUPLEX_FULL:
7315 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7316 break;
7317 case SPEED_100 + DUPLEX_HALF:
7318 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7319 break;
7320 case SPEED_100 + DUPLEX_FULL:
7321 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7322 break;
7323 case SPEED_1000 + DUPLEX_FULL:
7324 mac->autoneg = 1;
7325 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7326 break;
7327 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7328 default:
7329 goto err_inval;
7330 }
7331
7332 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7333 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7334
7335 return 0;
7336
7337 err_inval:
7338 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7339 return -EINVAL;
7340 }
7341
7342 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7343 bool runtime)
7344 {
7345 struct net_device *netdev = pci_get_drvdata(pdev);
7346 struct igb_adapter *adapter = netdev_priv(netdev);
7347 struct e1000_hw *hw = &adapter->hw;
7348 u32 ctrl, rctl, status;
7349 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7350 #ifdef CONFIG_PM
7351 int retval = 0;
7352 #endif
7353
7354 netif_device_detach(netdev);
7355
7356 if (netif_running(netdev))
7357 __igb_close(netdev, true);
7358
7359 igb_clear_interrupt_scheme(adapter);
7360
7361 #ifdef CONFIG_PM
7362 retval = pci_save_state(pdev);
7363 if (retval)
7364 return retval;
7365 #endif
7366
7367 status = rd32(E1000_STATUS);
7368 if (status & E1000_STATUS_LU)
7369 wufc &= ~E1000_WUFC_LNKC;
7370
7371 if (wufc) {
7372 igb_setup_rctl(adapter);
7373 igb_set_rx_mode(netdev);
7374
7375 /* turn on all-multi mode if wake on multicast is enabled */
7376 if (wufc & E1000_WUFC_MC) {
7377 rctl = rd32(E1000_RCTL);
7378 rctl |= E1000_RCTL_MPE;
7379 wr32(E1000_RCTL, rctl);
7380 }
7381
7382 ctrl = rd32(E1000_CTRL);
7383 /* advertise wake from D3Cold */
7384 #define E1000_CTRL_ADVD3WUC 0x00100000
7385 /* phy power management enable */
7386 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7387 ctrl |= E1000_CTRL_ADVD3WUC;
7388 wr32(E1000_CTRL, ctrl);
7389
7390 /* Allow time for pending master requests to run */
7391 igb_disable_pcie_master(hw);
7392
7393 wr32(E1000_WUC, E1000_WUC_PME_EN);
7394 wr32(E1000_WUFC, wufc);
7395 } else {
7396 wr32(E1000_WUC, 0);
7397 wr32(E1000_WUFC, 0);
7398 }
7399
7400 *enable_wake = wufc || adapter->en_mng_pt;
7401 if (!*enable_wake)
7402 igb_power_down_link(adapter);
7403 else
7404 igb_power_up_link(adapter);
7405
7406 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7407 * would have already happened in close and is redundant.
7408 */
7409 igb_release_hw_control(adapter);
7410
7411 pci_disable_device(pdev);
7412
7413 return 0;
7414 }
7415
7416 #ifdef CONFIG_PM
7417 #ifdef CONFIG_PM_SLEEP
7418 static int igb_suspend(struct device *dev)
7419 {
7420 int retval;
7421 bool wake;
7422 struct pci_dev *pdev = to_pci_dev(dev);
7423
7424 retval = __igb_shutdown(pdev, &wake, 0);
7425 if (retval)
7426 return retval;
7427
7428 if (wake) {
7429 pci_prepare_to_sleep(pdev);
7430 } else {
7431 pci_wake_from_d3(pdev, false);
7432 pci_set_power_state(pdev, PCI_D3hot);
7433 }
7434
7435 return 0;
7436 }
7437 #endif /* CONFIG_PM_SLEEP */
7438
7439 static int igb_resume(struct device *dev)
7440 {
7441 struct pci_dev *pdev = to_pci_dev(dev);
7442 struct net_device *netdev = pci_get_drvdata(pdev);
7443 struct igb_adapter *adapter = netdev_priv(netdev);
7444 struct e1000_hw *hw = &adapter->hw;
7445 u32 err;
7446
7447 pci_set_power_state(pdev, PCI_D0);
7448 pci_restore_state(pdev);
7449 pci_save_state(pdev);
7450
7451 if (!pci_device_is_present(pdev))
7452 return -ENODEV;
7453 err = pci_enable_device_mem(pdev);
7454 if (err) {
7455 dev_err(&pdev->dev,
7456 "igb: Cannot enable PCI device from suspend\n");
7457 return err;
7458 }
7459 pci_set_master(pdev);
7460
7461 pci_enable_wake(pdev, PCI_D3hot, 0);
7462 pci_enable_wake(pdev, PCI_D3cold, 0);
7463
7464 if (igb_init_interrupt_scheme(adapter, true)) {
7465 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7466 return -ENOMEM;
7467 }
7468
7469 igb_reset(adapter);
7470
7471 /* let the f/w know that the h/w is now under the control of the
7472 * driver.
7473 */
7474 igb_get_hw_control(adapter);
7475
7476 wr32(E1000_WUS, ~0);
7477
7478 if (netdev->flags & IFF_UP) {
7479 rtnl_lock();
7480 err = __igb_open(netdev, true);
7481 rtnl_unlock();
7482 if (err)
7483 return err;
7484 }
7485
7486 netif_device_attach(netdev);
7487 return 0;
7488 }
7489
7490 static int igb_runtime_idle(struct device *dev)
7491 {
7492 struct pci_dev *pdev = to_pci_dev(dev);
7493 struct net_device *netdev = pci_get_drvdata(pdev);
7494 struct igb_adapter *adapter = netdev_priv(netdev);
7495
7496 if (!igb_has_link(adapter))
7497 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7498
7499 return -EBUSY;
7500 }
7501
7502 static int igb_runtime_suspend(struct device *dev)
7503 {
7504 struct pci_dev *pdev = to_pci_dev(dev);
7505 int retval;
7506 bool wake;
7507
7508 retval = __igb_shutdown(pdev, &wake, 1);
7509 if (retval)
7510 return retval;
7511
7512 if (wake) {
7513 pci_prepare_to_sleep(pdev);
7514 } else {
7515 pci_wake_from_d3(pdev, false);
7516 pci_set_power_state(pdev, PCI_D3hot);
7517 }
7518
7519 return 0;
7520 }
7521
7522 static int igb_runtime_resume(struct device *dev)
7523 {
7524 return igb_resume(dev);
7525 }
7526 #endif /* CONFIG_PM */
7527
7528 static void igb_shutdown(struct pci_dev *pdev)
7529 {
7530 bool wake;
7531
7532 __igb_shutdown(pdev, &wake, 0);
7533
7534 if (system_state == SYSTEM_POWER_OFF) {
7535 pci_wake_from_d3(pdev, wake);
7536 pci_set_power_state(pdev, PCI_D3hot);
7537 }
7538 }
7539
7540 #ifdef CONFIG_PCI_IOV
7541 static int igb_sriov_reinit(struct pci_dev *dev)
7542 {
7543 struct net_device *netdev = pci_get_drvdata(dev);
7544 struct igb_adapter *adapter = netdev_priv(netdev);
7545 struct pci_dev *pdev = adapter->pdev;
7546
7547 rtnl_lock();
7548
7549 if (netif_running(netdev))
7550 igb_close(netdev);
7551 else
7552 igb_reset(adapter);
7553
7554 igb_clear_interrupt_scheme(adapter);
7555
7556 igb_init_queue_configuration(adapter);
7557
7558 if (igb_init_interrupt_scheme(adapter, true)) {
7559 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7560 return -ENOMEM;
7561 }
7562
7563 if (netif_running(netdev))
7564 igb_open(netdev);
7565
7566 rtnl_unlock();
7567
7568 return 0;
7569 }
7570
7571 static int igb_pci_disable_sriov(struct pci_dev *dev)
7572 {
7573 int err = igb_disable_sriov(dev);
7574
7575 if (!err)
7576 err = igb_sriov_reinit(dev);
7577
7578 return err;
7579 }
7580
7581 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7582 {
7583 int err = igb_enable_sriov(dev, num_vfs);
7584
7585 if (err)
7586 goto out;
7587
7588 err = igb_sriov_reinit(dev);
7589 if (!err)
7590 return num_vfs;
7591
7592 out:
7593 return err;
7594 }
7595
7596 #endif
7597 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7598 {
7599 #ifdef CONFIG_PCI_IOV
7600 if (num_vfs == 0)
7601 return igb_pci_disable_sriov(dev);
7602 else
7603 return igb_pci_enable_sriov(dev, num_vfs);
7604 #endif
7605 return 0;
7606 }
7607
7608 #ifdef CONFIG_NET_POLL_CONTROLLER
7609 /* Polling 'interrupt' - used by things like netconsole to send skbs
7610 * without having to re-enable interrupts. It's not called while
7611 * the interrupt routine is executing.
7612 */
7613 static void igb_netpoll(struct net_device *netdev)
7614 {
7615 struct igb_adapter *adapter = netdev_priv(netdev);
7616 struct e1000_hw *hw = &adapter->hw;
7617 struct igb_q_vector *q_vector;
7618 int i;
7619
7620 for (i = 0; i < adapter->num_q_vectors; i++) {
7621 q_vector = adapter->q_vector[i];
7622 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7623 wr32(E1000_EIMC, q_vector->eims_value);
7624 else
7625 igb_irq_disable(adapter);
7626 napi_schedule(&q_vector->napi);
7627 }
7628 }
7629 #endif /* CONFIG_NET_POLL_CONTROLLER */
7630
7631 /**
7632 * igb_io_error_detected - called when PCI error is detected
7633 * @pdev: Pointer to PCI device
7634 * @state: The current pci connection state
7635 *
7636 * This function is called after a PCI bus error affecting
7637 * this device has been detected.
7638 **/
7639 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7640 pci_channel_state_t state)
7641 {
7642 struct net_device *netdev = pci_get_drvdata(pdev);
7643 struct igb_adapter *adapter = netdev_priv(netdev);
7644
7645 netif_device_detach(netdev);
7646
7647 if (state == pci_channel_io_perm_failure)
7648 return PCI_ERS_RESULT_DISCONNECT;
7649
7650 if (netif_running(netdev))
7651 igb_down(adapter);
7652 pci_disable_device(pdev);
7653
7654 /* Request a slot slot reset. */
7655 return PCI_ERS_RESULT_NEED_RESET;
7656 }
7657
7658 /**
7659 * igb_io_slot_reset - called after the pci bus has been reset.
7660 * @pdev: Pointer to PCI device
7661 *
7662 * Restart the card from scratch, as if from a cold-boot. Implementation
7663 * resembles the first-half of the igb_resume routine.
7664 **/
7665 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7666 {
7667 struct net_device *netdev = pci_get_drvdata(pdev);
7668 struct igb_adapter *adapter = netdev_priv(netdev);
7669 struct e1000_hw *hw = &adapter->hw;
7670 pci_ers_result_t result;
7671 int err;
7672
7673 if (pci_enable_device_mem(pdev)) {
7674 dev_err(&pdev->dev,
7675 "Cannot re-enable PCI device after reset.\n");
7676 result = PCI_ERS_RESULT_DISCONNECT;
7677 } else {
7678 pci_set_master(pdev);
7679 pci_restore_state(pdev);
7680 pci_save_state(pdev);
7681
7682 pci_enable_wake(pdev, PCI_D3hot, 0);
7683 pci_enable_wake(pdev, PCI_D3cold, 0);
7684
7685 igb_reset(adapter);
7686 wr32(E1000_WUS, ~0);
7687 result = PCI_ERS_RESULT_RECOVERED;
7688 }
7689
7690 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7691 if (err) {
7692 dev_err(&pdev->dev,
7693 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7694 err);
7695 /* non-fatal, continue */
7696 }
7697
7698 return result;
7699 }
7700
7701 /**
7702 * igb_io_resume - called when traffic can start flowing again.
7703 * @pdev: Pointer to PCI device
7704 *
7705 * This callback is called when the error recovery driver tells us that
7706 * its OK to resume normal operation. Implementation resembles the
7707 * second-half of the igb_resume routine.
7708 */
7709 static void igb_io_resume(struct pci_dev *pdev)
7710 {
7711 struct net_device *netdev = pci_get_drvdata(pdev);
7712 struct igb_adapter *adapter = netdev_priv(netdev);
7713
7714 if (netif_running(netdev)) {
7715 if (igb_up(adapter)) {
7716 dev_err(&pdev->dev, "igb_up failed after reset\n");
7717 return;
7718 }
7719 }
7720
7721 netif_device_attach(netdev);
7722
7723 /* let the f/w know that the h/w is now under the control of the
7724 * driver.
7725 */
7726 igb_get_hw_control(adapter);
7727 }
7728
7729 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7730 u8 qsel)
7731 {
7732 u32 rar_low, rar_high;
7733 struct e1000_hw *hw = &adapter->hw;
7734
7735 /* HW expects these in little endian so we reverse the byte order
7736 * from network order (big endian) to little endian
7737 */
7738 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7739 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7740 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7741
7742 /* Indicate to hardware the Address is Valid. */
7743 rar_high |= E1000_RAH_AV;
7744
7745 if (hw->mac.type == e1000_82575)
7746 rar_high |= E1000_RAH_POOL_1 * qsel;
7747 else
7748 rar_high |= E1000_RAH_POOL_1 << qsel;
7749
7750 wr32(E1000_RAL(index), rar_low);
7751 wrfl();
7752 wr32(E1000_RAH(index), rar_high);
7753 wrfl();
7754 }
7755
7756 static int igb_set_vf_mac(struct igb_adapter *adapter,
7757 int vf, unsigned char *mac_addr)
7758 {
7759 struct e1000_hw *hw = &adapter->hw;
7760 /* VF MAC addresses start at end of receive addresses and moves
7761 * towards the first, as a result a collision should not be possible
7762 */
7763 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7764
7765 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7766
7767 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7768
7769 return 0;
7770 }
7771
7772 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7773 {
7774 struct igb_adapter *adapter = netdev_priv(netdev);
7775 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7776 return -EINVAL;
7777 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7778 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7779 dev_info(&adapter->pdev->dev,
7780 "Reload the VF driver to make this change effective.");
7781 if (test_bit(__IGB_DOWN, &adapter->state)) {
7782 dev_warn(&adapter->pdev->dev,
7783 "The VF MAC address has been set, but the PF device is not up.\n");
7784 dev_warn(&adapter->pdev->dev,
7785 "Bring the PF device up before attempting to use the VF device.\n");
7786 }
7787 return igb_set_vf_mac(adapter, vf, mac);
7788 }
7789
7790 static int igb_link_mbps(int internal_link_speed)
7791 {
7792 switch (internal_link_speed) {
7793 case SPEED_100:
7794 return 100;
7795 case SPEED_1000:
7796 return 1000;
7797 default:
7798 return 0;
7799 }
7800 }
7801
7802 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7803 int link_speed)
7804 {
7805 int rf_dec, rf_int;
7806 u32 bcnrc_val;
7807
7808 if (tx_rate != 0) {
7809 /* Calculate the rate factor values to set */
7810 rf_int = link_speed / tx_rate;
7811 rf_dec = (link_speed - (rf_int * tx_rate));
7812 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7813 tx_rate;
7814
7815 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7816 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7817 E1000_RTTBCNRC_RF_INT_MASK);
7818 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7819 } else {
7820 bcnrc_val = 0;
7821 }
7822
7823 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7824 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7825 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7826 */
7827 wr32(E1000_RTTBCNRM, 0x14);
7828 wr32(E1000_RTTBCNRC, bcnrc_val);
7829 }
7830
7831 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7832 {
7833 int actual_link_speed, i;
7834 bool reset_rate = false;
7835
7836 /* VF TX rate limit was not set or not supported */
7837 if ((adapter->vf_rate_link_speed == 0) ||
7838 (adapter->hw.mac.type != e1000_82576))
7839 return;
7840
7841 actual_link_speed = igb_link_mbps(adapter->link_speed);
7842 if (actual_link_speed != adapter->vf_rate_link_speed) {
7843 reset_rate = true;
7844 adapter->vf_rate_link_speed = 0;
7845 dev_info(&adapter->pdev->dev,
7846 "Link speed has been changed. VF Transmit rate is disabled\n");
7847 }
7848
7849 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7850 if (reset_rate)
7851 adapter->vf_data[i].tx_rate = 0;
7852
7853 igb_set_vf_rate_limit(&adapter->hw, i,
7854 adapter->vf_data[i].tx_rate,
7855 actual_link_speed);
7856 }
7857 }
7858
7859 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7860 int min_tx_rate, int max_tx_rate)
7861 {
7862 struct igb_adapter *adapter = netdev_priv(netdev);
7863 struct e1000_hw *hw = &adapter->hw;
7864 int actual_link_speed;
7865
7866 if (hw->mac.type != e1000_82576)
7867 return -EOPNOTSUPP;
7868
7869 if (min_tx_rate)
7870 return -EINVAL;
7871
7872 actual_link_speed = igb_link_mbps(adapter->link_speed);
7873 if ((vf >= adapter->vfs_allocated_count) ||
7874 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7875 (max_tx_rate < 0) ||
7876 (max_tx_rate > actual_link_speed))
7877 return -EINVAL;
7878
7879 adapter->vf_rate_link_speed = actual_link_speed;
7880 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7881 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7882
7883 return 0;
7884 }
7885
7886 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7887 bool setting)
7888 {
7889 struct igb_adapter *adapter = netdev_priv(netdev);
7890 struct e1000_hw *hw = &adapter->hw;
7891 u32 reg_val, reg_offset;
7892
7893 if (!adapter->vfs_allocated_count)
7894 return -EOPNOTSUPP;
7895
7896 if (vf >= adapter->vfs_allocated_count)
7897 return -EINVAL;
7898
7899 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7900 reg_val = rd32(reg_offset);
7901 if (setting)
7902 reg_val |= ((1 << vf) |
7903 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7904 else
7905 reg_val &= ~((1 << vf) |
7906 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7907 wr32(reg_offset, reg_val);
7908
7909 adapter->vf_data[vf].spoofchk_enabled = setting;
7910 return 0;
7911 }
7912
7913 static int igb_ndo_get_vf_config(struct net_device *netdev,
7914 int vf, struct ifla_vf_info *ivi)
7915 {
7916 struct igb_adapter *adapter = netdev_priv(netdev);
7917 if (vf >= adapter->vfs_allocated_count)
7918 return -EINVAL;
7919 ivi->vf = vf;
7920 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7921 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7922 ivi->min_tx_rate = 0;
7923 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7924 ivi->qos = adapter->vf_data[vf].pf_qos;
7925 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7926 return 0;
7927 }
7928
7929 static void igb_vmm_control(struct igb_adapter *adapter)
7930 {
7931 struct e1000_hw *hw = &adapter->hw;
7932 u32 reg;
7933
7934 switch (hw->mac.type) {
7935 case e1000_82575:
7936 case e1000_i210:
7937 case e1000_i211:
7938 case e1000_i354:
7939 default:
7940 /* replication is not supported for 82575 */
7941 return;
7942 case e1000_82576:
7943 /* notify HW that the MAC is adding vlan tags */
7944 reg = rd32(E1000_DTXCTL);
7945 reg |= E1000_DTXCTL_VLAN_ADDED;
7946 wr32(E1000_DTXCTL, reg);
7947 /* Fall through */
7948 case e1000_82580:
7949 /* enable replication vlan tag stripping */
7950 reg = rd32(E1000_RPLOLR);
7951 reg |= E1000_RPLOLR_STRVLAN;
7952 wr32(E1000_RPLOLR, reg);
7953 /* Fall through */
7954 case e1000_i350:
7955 /* none of the above registers are supported by i350 */
7956 break;
7957 }
7958
7959 if (adapter->vfs_allocated_count) {
7960 igb_vmdq_set_loopback_pf(hw, true);
7961 igb_vmdq_set_replication_pf(hw, true);
7962 igb_vmdq_set_anti_spoofing_pf(hw, true,
7963 adapter->vfs_allocated_count);
7964 } else {
7965 igb_vmdq_set_loopback_pf(hw, false);
7966 igb_vmdq_set_replication_pf(hw, false);
7967 }
7968 }
7969
7970 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7971 {
7972 struct e1000_hw *hw = &adapter->hw;
7973 u32 dmac_thr;
7974 u16 hwm;
7975
7976 if (hw->mac.type > e1000_82580) {
7977 if (adapter->flags & IGB_FLAG_DMAC) {
7978 u32 reg;
7979
7980 /* force threshold to 0. */
7981 wr32(E1000_DMCTXTH, 0);
7982
7983 /* DMA Coalescing high water mark needs to be greater
7984 * than the Rx threshold. Set hwm to PBA - max frame
7985 * size in 16B units, capping it at PBA - 6KB.
7986 */
7987 hwm = 64 * pba - adapter->max_frame_size / 16;
7988 if (hwm < 64 * (pba - 6))
7989 hwm = 64 * (pba - 6);
7990 reg = rd32(E1000_FCRTC);
7991 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7992 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7993 & E1000_FCRTC_RTH_COAL_MASK);
7994 wr32(E1000_FCRTC, reg);
7995
7996 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7997 * frame size, capping it at PBA - 10KB.
7998 */
7999 dmac_thr = pba - adapter->max_frame_size / 512;
8000 if (dmac_thr < pba - 10)
8001 dmac_thr = pba - 10;
8002 reg = rd32(E1000_DMACR);
8003 reg &= ~E1000_DMACR_DMACTHR_MASK;
8004 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8005 & E1000_DMACR_DMACTHR_MASK);
8006
8007 /* transition to L0x or L1 if available..*/
8008 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8009
8010 /* watchdog timer= +-1000 usec in 32usec intervals */
8011 reg |= (1000 >> 5);
8012
8013 /* Disable BMC-to-OS Watchdog Enable */
8014 if (hw->mac.type != e1000_i354)
8015 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8016
8017 wr32(E1000_DMACR, reg);
8018
8019 /* no lower threshold to disable
8020 * coalescing(smart fifb)-UTRESH=0
8021 */
8022 wr32(E1000_DMCRTRH, 0);
8023
8024 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8025
8026 wr32(E1000_DMCTLX, reg);
8027
8028 /* free space in tx packet buffer to wake from
8029 * DMA coal
8030 */
8031 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8032 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8033
8034 /* make low power state decision controlled
8035 * by DMA coal
8036 */
8037 reg = rd32(E1000_PCIEMISC);
8038 reg &= ~E1000_PCIEMISC_LX_DECISION;
8039 wr32(E1000_PCIEMISC, reg);
8040 } /* endif adapter->dmac is not disabled */
8041 } else if (hw->mac.type == e1000_82580) {
8042 u32 reg = rd32(E1000_PCIEMISC);
8043
8044 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8045 wr32(E1000_DMACR, 0);
8046 }
8047 }
8048
8049 /**
8050 * igb_read_i2c_byte - Reads 8 bit word over I2C
8051 * @hw: pointer to hardware structure
8052 * @byte_offset: byte offset to read
8053 * @dev_addr: device address
8054 * @data: value read
8055 *
8056 * Performs byte read operation over I2C interface at
8057 * a specified device address.
8058 **/
8059 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8060 u8 dev_addr, u8 *data)
8061 {
8062 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8063 struct i2c_client *this_client = adapter->i2c_client;
8064 s32 status;
8065 u16 swfw_mask = 0;
8066
8067 if (!this_client)
8068 return E1000_ERR_I2C;
8069
8070 swfw_mask = E1000_SWFW_PHY0_SM;
8071
8072 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8073 return E1000_ERR_SWFW_SYNC;
8074
8075 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8076 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8077
8078 if (status < 0)
8079 return E1000_ERR_I2C;
8080 else {
8081 *data = status;
8082 return 0;
8083 }
8084 }
8085
8086 /**
8087 * igb_write_i2c_byte - Writes 8 bit word over I2C
8088 * @hw: pointer to hardware structure
8089 * @byte_offset: byte offset to write
8090 * @dev_addr: device address
8091 * @data: value to write
8092 *
8093 * Performs byte write operation over I2C interface at
8094 * a specified device address.
8095 **/
8096 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8097 u8 dev_addr, u8 data)
8098 {
8099 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8100 struct i2c_client *this_client = adapter->i2c_client;
8101 s32 status;
8102 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8103
8104 if (!this_client)
8105 return E1000_ERR_I2C;
8106
8107 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8108 return E1000_ERR_SWFW_SYNC;
8109 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8110 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8111
8112 if (status)
8113 return E1000_ERR_I2C;
8114 else
8115 return 0;
8116
8117 }
8118
8119 int igb_reinit_queues(struct igb_adapter *adapter)
8120 {
8121 struct net_device *netdev = adapter->netdev;
8122 struct pci_dev *pdev = adapter->pdev;
8123 int err = 0;
8124
8125 if (netif_running(netdev))
8126 igb_close(netdev);
8127
8128 igb_reset_interrupt_capability(adapter);
8129
8130 if (igb_init_interrupt_scheme(adapter, true)) {
8131 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8132 return -ENOMEM;
8133 }
8134
8135 if (netif_running(netdev))
8136 err = igb_open(netdev);
8137
8138 return err;
8139 }
8140 /* igb_main.c */
Linux kernel - Deliverables
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