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igb: Add device support for flashless SKU of i210 device
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/init.h>
33 #include <linux/bitops.h>
34 #include <linux/vmalloc.h>
35 #include <linux/pagemap.h>
36 #include <linux/netdevice.h>
37 #include <linux/ipv6.h>
38 #include <linux/slab.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/net_tstamp.h>
42 #include <linux/mii.h>
43 #include <linux/ethtool.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/pci.h>
47 #include <linux/pci-aspm.h>
48 #include <linux/delay.h>
49 #include <linux/interrupt.h>
50 #include <linux/ip.h>
51 #include <linux/tcp.h>
52 #include <linux/sctp.h>
53 #include <linux/if_ether.h>
54 #include <linux/aer.h>
55 #include <linux/prefetch.h>
56 #include <linux/pm_runtime.h>
57 #ifdef CONFIG_IGB_DCA
58 #include <linux/dca.h>
59 #endif
60 #include <linux/i2c.h>
61 #include "igb.h"
62
63 #define MAJ 5
64 #define MIN 0
65 #define BUILD 3
66 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
67 __stringify(BUILD) "-k"
68 char igb_driver_name[] = "igb";
69 char igb_driver_version[] = DRV_VERSION;
70 static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
72 static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
74
75 static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77 };
78
79 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117 };
118
119 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121 void igb_reset(struct igb_adapter *);
122 static int igb_setup_all_tx_resources(struct igb_adapter *);
123 static int igb_setup_all_rx_resources(struct igb_adapter *);
124 static void igb_free_all_tx_resources(struct igb_adapter *);
125 static void igb_free_all_rx_resources(struct igb_adapter *);
126 static void igb_setup_mrqc(struct igb_adapter *);
127 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
128 static void igb_remove(struct pci_dev *pdev);
129 static int igb_sw_init(struct igb_adapter *);
130 static int igb_open(struct net_device *);
131 static int igb_close(struct net_device *);
132 static void igb_configure(struct igb_adapter *);
133 static void igb_configure_tx(struct igb_adapter *);
134 static void igb_configure_rx(struct igb_adapter *);
135 static void igb_clean_all_tx_rings(struct igb_adapter *);
136 static void igb_clean_all_rx_rings(struct igb_adapter *);
137 static void igb_clean_tx_ring(struct igb_ring *);
138 static void igb_clean_rx_ring(struct igb_ring *);
139 static void igb_set_rx_mode(struct net_device *);
140 static void igb_update_phy_info(unsigned long);
141 static void igb_watchdog(unsigned long);
142 static void igb_watchdog_task(struct work_struct *);
143 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
144 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
146 static int igb_change_mtu(struct net_device *, int);
147 static int igb_set_mac(struct net_device *, void *);
148 static void igb_set_uta(struct igb_adapter *adapter);
149 static irqreturn_t igb_intr(int irq, void *);
150 static irqreturn_t igb_intr_msi(int irq, void *);
151 static irqreturn_t igb_msix_other(int irq, void *);
152 static irqreturn_t igb_msix_ring(int irq, void *);
153 #ifdef CONFIG_IGB_DCA
154 static void igb_update_dca(struct igb_q_vector *);
155 static void igb_setup_dca(struct igb_adapter *);
156 #endif /* CONFIG_IGB_DCA */
157 static int igb_poll(struct napi_struct *, int);
158 static bool igb_clean_tx_irq(struct igb_q_vector *);
159 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
160 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161 static void igb_tx_timeout(struct net_device *);
162 static void igb_reset_task(struct work_struct *);
163 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
164 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
166 static void igb_restore_vlan(struct igb_adapter *);
167 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
168 static void igb_ping_all_vfs(struct igb_adapter *);
169 static void igb_msg_task(struct igb_adapter *);
170 static void igb_vmm_control(struct igb_adapter *);
171 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
172 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
173 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
177 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
179 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
181 static void igb_check_vf_rate_limit(struct igb_adapter *);
182
183 #ifdef CONFIG_PCI_IOV
184 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
185 #endif
186
187 #ifdef CONFIG_PM
188 #ifdef CONFIG_PM_SLEEP
189 static int igb_suspend(struct device *);
190 #endif
191 static int igb_resume(struct device *);
192 #ifdef CONFIG_PM_RUNTIME
193 static int igb_runtime_suspend(struct device *dev);
194 static int igb_runtime_resume(struct device *dev);
195 static int igb_runtime_idle(struct device *dev);
196 #endif
197 static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201 };
202 #endif
203 static void igb_shutdown(struct pci_dev *);
204 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
205 #ifdef CONFIG_IGB_DCA
206 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207 static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211 };
212 #endif
213 #ifdef CONFIG_NET_POLL_CONTROLLER
214 /* for netdump / net console */
215 static void igb_netpoll(struct net_device *);
216 #endif
217 #ifdef CONFIG_PCI_IOV
218 static unsigned int max_vfs = 0;
219 module_param(max_vfs, uint, 0);
220 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
221 "per physical function");
222 #endif /* CONFIG_PCI_IOV */
223
224 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227 static void igb_io_resume(struct pci_dev *);
228
229 static const struct pci_error_handlers igb_err_handler = {
230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233 };
234
235 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
236
237 static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
241 .remove = igb_remove,
242 #ifdef CONFIG_PM
243 .driver.pm = &igb_pm_ops,
244 #endif
245 .shutdown = igb_shutdown,
246 .sriov_configure = igb_pci_sriov_configure,
247 .err_handler = &igb_err_handler
248 };
249
250 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252 MODULE_LICENSE("GPL");
253 MODULE_VERSION(DRV_VERSION);
254
255 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256 static int debug = -1;
257 module_param(debug, int, 0);
258 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
260 struct igb_reg_info {
261 u32 ofs;
262 char *name;
263 };
264
265 static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299 };
300
301 /* igb_regdump - register printout routine */
302 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303 {
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
365 }
366
367 /* igb_dump - Print registers, Tx-rings and Rx-rings */
368 static void igb_dump(struct igb_adapter *adapter)
369 {
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
379 u16 i, n;
380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
387 pr_info("Device Name state trans_start "
388 "last_rx\n");
389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
390 netdev->state, netdev->trans_start, netdev->last_rx);
391 }
392
393 /* Print Registers */
394 dev_info(&adapter->pdev->dev, "Register Dump\n");
395 pr_info(" Register Name Value\n");
396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
397 reginfo->name; reginfo++) {
398 igb_regdump(hw, reginfo);
399 }
400
401 /* Print TX Ring Summary */
402 if (!netdev || !netif_running(netdev))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
407 for (n = 0; n < adapter->num_tx_queues; n++) {
408 struct igb_tx_buffer *buffer_info;
409 tx_ring = adapter->tx_ring[n];
410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
412 n, tx_ring->next_to_use, tx_ring->next_to_clean,
413 (u64)dma_unmap_addr(buffer_info, dma),
414 dma_unmap_len(buffer_info, len),
415 buffer_info->next_to_watch,
416 (u64)buffer_info->time_stamp);
417 }
418
419 /* Print TX Rings */
420 if (!netif_msg_tx_done(adapter))
421 goto rx_ring_summary;
422
423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
424
425 /* Transmit Descriptor Formats
426 *
427 * Advanced Transmit Descriptor
428 * +--------------------------------------------------------------+
429 * 0 | Buffer Address [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
432 * +--------------------------------------------------------------+
433 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
442 "[bi->dma ] leng ntw timestamp "
443 "bi->skb\n");
444
445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
446 const char *next_desc;
447 struct igb_tx_buffer *buffer_info;
448 tx_desc = IGB_TX_DESC(tx_ring, i);
449 buffer_info = &tx_ring->tx_buffer_info[i];
450 u0 = (struct my_u0 *)tx_desc;
451 if (i == tx_ring->next_to_use &&
452 i == tx_ring->next_to_clean)
453 next_desc = " NTC/U";
454 else if (i == tx_ring->next_to_use)
455 next_desc = " NTU";
456 else if (i == tx_ring->next_to_clean)
457 next_desc = " NTC";
458 else
459 next_desc = "";
460
461 pr_info("T [0x%03X] %016llX %016llX %016llX"
462 " %04X %p %016llX %p%s\n", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)dma_unmap_addr(buffer_info, dma),
466 dma_unmap_len(buffer_info, len),
467 buffer_info->next_to_watch,
468 (u64)buffer_info->time_stamp,
469 buffer_info->skb, next_desc);
470
471 if (netif_msg_pktdata(adapter) && buffer_info->skb)
472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS,
474 16, 1, buffer_info->skb->data,
475 dma_unmap_len(buffer_info, len),
476 true);
477 }
478 }
479
480 /* Print RX Rings Summary */
481 rx_ring_summary:
482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
483 pr_info("Queue [NTU] [NTC]\n");
484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
486 pr_info(" %5d %5X %5X\n",
487 n, rx_ring->next_to_use, rx_ring->next_to_clean);
488 }
489
490 /* Print RX Rings */
491 if (!netif_msg_rx_status(adapter))
492 goto exit;
493
494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
495
496 /* Advanced Receive Descriptor (Read) Format
497 * 63 1 0
498 * +-----------------------------------------------------+
499 * 0 | Packet Buffer Address [63:1] |A0/NSE|
500 * +----------------------------------------------+------+
501 * 8 | Header Buffer Address [63:1] | DD |
502 * +-----------------------------------------------------+
503 *
504 *
505 * Advanced Receive Descriptor (Write-Back) Format
506 *
507 * 63 48 47 32 31 30 21 20 17 16 4 3 0
508 * +------------------------------------------------------+
509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
510 * | Checksum Ident | | | | Type | Type |
511 * +------------------------------------------------------+
512 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
513 * +------------------------------------------------------+
514 * 63 48 47 32 31 20 19 0
515 */
516
517 for (n = 0; n < adapter->num_rx_queues; n++) {
518 rx_ring = adapter->rx_ring[n];
519 pr_info("------------------------------------\n");
520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
526
527 for (i = 0; i < rx_ring->count; i++) {
528 const char *next_desc;
529 struct igb_rx_buffer *buffer_info;
530 buffer_info = &rx_ring->rx_buffer_info[i];
531 rx_desc = IGB_RX_DESC(rx_ring, i);
532 u0 = (struct my_u0 *)rx_desc;
533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
534
535 if (i == rx_ring->next_to_use)
536 next_desc = " NTU";
537 else if (i == rx_ring->next_to_clean)
538 next_desc = " NTC";
539 else
540 next_desc = "";
541
542 if (staterr & E1000_RXD_STAT_DD) {
543 /* Descriptor Done */
544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
545 "RWB", i,
546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
548 next_desc);
549 } else {
550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
551 "R ", i,
552 le64_to_cpu(u0->a),
553 le64_to_cpu(u0->b),
554 (u64)buffer_info->dma,
555 next_desc);
556
557 if (netif_msg_pktdata(adapter) &&
558 buffer_info->dma && buffer_info->page) {
559 print_hex_dump(KERN_INFO, "",
560 DUMP_PREFIX_ADDRESS,
561 16, 1,
562 page_address(buffer_info->page) +
563 buffer_info->page_offset,
564 IGB_RX_BUFSZ, true);
565 }
566 }
567 }
568 }
569
570 exit:
571 return;
572 }
573
574 /**
575 * igb_get_i2c_data - Reads the I2C SDA data bit
576 * @hw: pointer to hardware structure
577 * @i2cctl: Current value of I2CCTL register
578 *
579 * Returns the I2C data bit value
580 **/
581 static int igb_get_i2c_data(void *data)
582 {
583 struct igb_adapter *adapter = (struct igb_adapter *)data;
584 struct e1000_hw *hw = &adapter->hw;
585 s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
588 }
589
590 /**
591 * igb_set_i2c_data - Sets the I2C data bit
592 * @data: pointer to hardware structure
593 * @state: I2C data value (0 or 1) to set
594 *
595 * Sets the I2C data bit
596 **/
597 static void igb_set_i2c_data(void *data, int state)
598 {
599 struct igb_adapter *adapter = (struct igb_adapter *)data;
600 struct e1000_hw *hw = &adapter->hw;
601 s32 i2cctl = rd32(E1000_I2CPARAMS);
602
603 if (state)
604 i2cctl |= E1000_I2C_DATA_OUT;
605 else
606 i2cctl &= ~E1000_I2C_DATA_OUT;
607
608 i2cctl &= ~E1000_I2C_DATA_OE_N;
609 i2cctl |= E1000_I2C_CLK_OE_N;
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612
613 }
614
615 /**
616 * igb_set_i2c_clk - Sets the I2C SCL clock
617 * @data: pointer to hardware structure
618 * @state: state to set clock
619 *
620 * Sets the I2C clock line to state
621 **/
622 static void igb_set_i2c_clk(void *data, int state)
623 {
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 if (state) {
629 i2cctl |= E1000_I2C_CLK_OUT;
630 i2cctl &= ~E1000_I2C_CLK_OE_N;
631 } else {
632 i2cctl &= ~E1000_I2C_CLK_OUT;
633 i2cctl &= ~E1000_I2C_CLK_OE_N;
634 }
635 wr32(E1000_I2CPARAMS, i2cctl);
636 wrfl();
637 }
638
639 /**
640 * igb_get_i2c_clk - Gets the I2C SCL clock state
641 * @data: pointer to hardware structure
642 *
643 * Gets the I2C clock state
644 **/
645 static int igb_get_i2c_clk(void *data)
646 {
647 struct igb_adapter *adapter = (struct igb_adapter *)data;
648 struct e1000_hw *hw = &adapter->hw;
649 s32 i2cctl = rd32(E1000_I2CPARAMS);
650
651 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
652 }
653
654 static const struct i2c_algo_bit_data igb_i2c_algo = {
655 .setsda = igb_set_i2c_data,
656 .setscl = igb_set_i2c_clk,
657 .getsda = igb_get_i2c_data,
658 .getscl = igb_get_i2c_clk,
659 .udelay = 5,
660 .timeout = 20,
661 };
662
663 /**
664 * igb_get_hw_dev - return device
665 * @hw: pointer to hardware structure
666 *
667 * used by hardware layer to print debugging information
668 **/
669 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
670 {
671 struct igb_adapter *adapter = hw->back;
672 return adapter->netdev;
673 }
674
675 /**
676 * igb_init_module - Driver Registration Routine
677 *
678 * igb_init_module is the first routine called when the driver is
679 * loaded. All it does is register with the PCI subsystem.
680 **/
681 static int __init igb_init_module(void)
682 {
683 int ret;
684 pr_info("%s - version %s\n",
685 igb_driver_string, igb_driver_version);
686
687 pr_info("%s\n", igb_copyright);
688
689 #ifdef CONFIG_IGB_DCA
690 dca_register_notify(&dca_notifier);
691 #endif
692 ret = pci_register_driver(&igb_driver);
693 return ret;
694 }
695
696 module_init(igb_init_module);
697
698 /**
699 * igb_exit_module - Driver Exit Cleanup Routine
700 *
701 * igb_exit_module is called just before the driver is removed
702 * from memory.
703 **/
704 static void __exit igb_exit_module(void)
705 {
706 #ifdef CONFIG_IGB_DCA
707 dca_unregister_notify(&dca_notifier);
708 #endif
709 pci_unregister_driver(&igb_driver);
710 }
711
712 module_exit(igb_exit_module);
713
714 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
715 /**
716 * igb_cache_ring_register - Descriptor ring to register mapping
717 * @adapter: board private structure to initialize
718 *
719 * Once we know the feature-set enabled for the device, we'll cache
720 * the register offset the descriptor ring is assigned to.
721 **/
722 static void igb_cache_ring_register(struct igb_adapter *adapter)
723 {
724 int i = 0, j = 0;
725 u32 rbase_offset = adapter->vfs_allocated_count;
726
727 switch (adapter->hw.mac.type) {
728 case e1000_82576:
729 /* The queues are allocated for virtualization such that VF 0
730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
731 * In order to avoid collision we start at the first free queue
732 * and continue consuming queues in the same sequence
733 */
734 if (adapter->vfs_allocated_count) {
735 for (; i < adapter->rss_queues; i++)
736 adapter->rx_ring[i]->reg_idx = rbase_offset +
737 Q_IDX_82576(i);
738 }
739 case e1000_82575:
740 case e1000_82580:
741 case e1000_i350:
742 case e1000_i354:
743 case e1000_i210:
744 case e1000_i211:
745 default:
746 for (; i < adapter->num_rx_queues; i++)
747 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
748 for (; j < adapter->num_tx_queues; j++)
749 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
750 break;
751 }
752 }
753
754 /**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768 {
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778 }
779
780 #define IGB_N0_QUEUE -1
781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
782 {
783 struct igb_adapter *adapter = q_vector->adapter;
784 struct e1000_hw *hw = &adapter->hw;
785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
787 u32 msixbm = 0;
788
789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
793
794 switch (hw->mac.type) {
795 case e1000_82575:
796 /* The 82575 assigns vectors using a bitmask, which matches the
797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
801 if (rx_queue > IGB_N0_QUEUE)
802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
803 if (tx_queue > IGB_N0_QUEUE)
804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
805 if (!adapter->msix_entries && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
808 q_vector->eims_value = msixbm;
809 break;
810 case e1000_82576:
811 /* 82576 uses a table that essentially consists of 2 columns
812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
824 q_vector->eims_value = 1 << msix_vector;
825 break;
826 case e1000_82580:
827 case e1000_i350:
828 case e1000_i354:
829 case e1000_i210:
830 case e1000_i211:
831 /* On 82580 and newer adapters the scheme is similar to 82576
832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
845 q_vector->eims_value = 1 << msix_vector;
846 break;
847 default:
848 BUG();
849 break;
850 }
851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
857 }
858
859 /**
860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
862 *
863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
865 **/
866 static void igb_configure_msix(struct igb_adapter *adapter)
867 {
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
873
874 /* set vector for other causes, i.e. link changes */
875 switch (hw->mac.type) {
876 case e1000_82575:
877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
886
887 /* enable msix_other interrupt */
888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
889 adapter->eims_other = E1000_EIMS_OTHER;
890
891 break;
892
893 case e1000_82576:
894 case e1000_82580:
895 case e1000_i350:
896 case e1000_i354:
897 case e1000_i210:
898 case e1000_i211:
899 /* Turn on MSI-X capability first, or our settings
900 * won't stick. And it will take days to debug.
901 */
902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
905
906 /* enable msix_other interrupt */
907 adapter->eims_other = 1 << vector;
908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
909
910 wr32(E1000_IVAR_MISC, tmp);
911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
921
922 wrfl();
923 }
924
925 /**
926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
928 *
929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
931 **/
932 static int igb_request_msix(struct igb_adapter *adapter)
933 {
934 struct net_device *netdev = adapter->netdev;
935 struct e1000_hw *hw = &adapter->hw;
936 int i, err = 0, vector = 0, free_vector = 0;
937
938 err = request_irq(adapter->msix_entries[vector].vector,
939 igb_msix_other, 0, netdev->name, adapter);
940 if (err)
941 goto err_out;
942
943 for (i = 0; i < adapter->num_q_vectors; i++) {
944 struct igb_q_vector *q_vector = adapter->q_vector[i];
945
946 vector++;
947
948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
949
950 if (q_vector->rx.ring && q_vector->tx.ring)
951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
952 q_vector->rx.ring->queue_index);
953 else if (q_vector->tx.ring)
954 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
955 q_vector->tx.ring->queue_index);
956 else if (q_vector->rx.ring)
957 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
958 q_vector->rx.ring->queue_index);
959 else
960 sprintf(q_vector->name, "%s-unused", netdev->name);
961
962 err = request_irq(adapter->msix_entries[vector].vector,
963 igb_msix_ring, 0, q_vector->name,
964 q_vector);
965 if (err)
966 goto err_free;
967 }
968
969 igb_configure_msix(adapter);
970 return 0;
971
972 err_free:
973 /* free already assigned IRQs */
974 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
975
976 vector--;
977 for (i = 0; i < vector; i++) {
978 free_irq(adapter->msix_entries[free_vector++].vector,
979 adapter->q_vector[i]);
980 }
981 err_out:
982 return err;
983 }
984
985 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
986 {
987 if (adapter->msix_entries) {
988 pci_disable_msix(adapter->pdev);
989 kfree(adapter->msix_entries);
990 adapter->msix_entries = NULL;
991 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
992 pci_disable_msi(adapter->pdev);
993 }
994 }
995
996 /**
997 * igb_free_q_vector - Free memory allocated for specific interrupt vector
998 * @adapter: board private structure to initialize
999 * @v_idx: Index of vector to be freed
1000 *
1001 * This function frees the memory allocated to the q_vector. In addition if
1002 * NAPI is enabled it will delete any references to the NAPI struct prior
1003 * to freeing the q_vector.
1004 **/
1005 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006 {
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 if (q_vector->tx.ring)
1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1011
1012 if (q_vector->rx.ring)
1013 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1014
1015 adapter->q_vector[v_idx] = NULL;
1016 netif_napi_del(&q_vector->napi);
1017
1018 /* igb_get_stats64() might access the rings on this vector,
1019 * we must wait a grace period before freeing it.
1020 */
1021 kfree_rcu(q_vector, rcu);
1022 }
1023
1024 /**
1025 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1026 * @adapter: board private structure to initialize
1027 *
1028 * This function frees the memory allocated to the q_vectors. In addition if
1029 * NAPI is enabled it will delete any references to the NAPI struct prior
1030 * to freeing the q_vector.
1031 **/
1032 static void igb_free_q_vectors(struct igb_adapter *adapter)
1033 {
1034 int v_idx = adapter->num_q_vectors;
1035
1036 adapter->num_tx_queues = 0;
1037 adapter->num_rx_queues = 0;
1038 adapter->num_q_vectors = 0;
1039
1040 while (v_idx--)
1041 igb_free_q_vector(adapter, v_idx);
1042 }
1043
1044 /**
1045 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1046 * @adapter: board private structure to initialize
1047 *
1048 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1049 * MSI-X interrupts allocated.
1050 */
1051 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1052 {
1053 igb_free_q_vectors(adapter);
1054 igb_reset_interrupt_capability(adapter);
1055 }
1056
1057 /**
1058 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1059 * @adapter: board private structure to initialize
1060 * @msix: boolean value of MSIX capability
1061 *
1062 * Attempt to configure interrupts using the best available
1063 * capabilities of the hardware and kernel.
1064 **/
1065 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1066 {
1067 int err;
1068 int numvecs, i;
1069
1070 if (!msix)
1071 goto msi_only;
1072
1073 /* Number of supported queues. */
1074 adapter->num_rx_queues = adapter->rss_queues;
1075 if (adapter->vfs_allocated_count)
1076 adapter->num_tx_queues = 1;
1077 else
1078 adapter->num_tx_queues = adapter->rss_queues;
1079
1080 /* start with one vector for every Rx queue */
1081 numvecs = adapter->num_rx_queues;
1082
1083 /* if Tx handler is separate add 1 for every Tx queue */
1084 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1085 numvecs += adapter->num_tx_queues;
1086
1087 /* store the number of vectors reserved for queues */
1088 adapter->num_q_vectors = numvecs;
1089
1090 /* add 1 vector for link status interrupts */
1091 numvecs++;
1092 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1093 GFP_KERNEL);
1094
1095 if (!adapter->msix_entries)
1096 goto msi_only;
1097
1098 for (i = 0; i < numvecs; i++)
1099 adapter->msix_entries[i].entry = i;
1100
1101 err = pci_enable_msix(adapter->pdev,
1102 adapter->msix_entries,
1103 numvecs);
1104 if (err == 0)
1105 return;
1106
1107 igb_reset_interrupt_capability(adapter);
1108
1109 /* If we can't do MSI-X, try MSI */
1110 msi_only:
1111 #ifdef CONFIG_PCI_IOV
1112 /* disable SR-IOV for non MSI-X configurations */
1113 if (adapter->vf_data) {
1114 struct e1000_hw *hw = &adapter->hw;
1115 /* disable iov and allow time for transactions to clear */
1116 pci_disable_sriov(adapter->pdev);
1117 msleep(500);
1118
1119 kfree(adapter->vf_data);
1120 adapter->vf_data = NULL;
1121 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1122 wrfl();
1123 msleep(100);
1124 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1125 }
1126 #endif
1127 adapter->vfs_allocated_count = 0;
1128 adapter->rss_queues = 1;
1129 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1130 adapter->num_rx_queues = 1;
1131 adapter->num_tx_queues = 1;
1132 adapter->num_q_vectors = 1;
1133 if (!pci_enable_msi(adapter->pdev))
1134 adapter->flags |= IGB_FLAG_HAS_MSI;
1135 }
1136
1137 static void igb_add_ring(struct igb_ring *ring,
1138 struct igb_ring_container *head)
1139 {
1140 head->ring = ring;
1141 head->count++;
1142 }
1143
1144 /**
1145 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1146 * @adapter: board private structure to initialize
1147 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1148 * @v_idx: index of vector in adapter struct
1149 * @txr_count: total number of Tx rings to allocate
1150 * @txr_idx: index of first Tx ring to allocate
1151 * @rxr_count: total number of Rx rings to allocate
1152 * @rxr_idx: index of first Rx ring to allocate
1153 *
1154 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1155 **/
1156 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1157 int v_count, int v_idx,
1158 int txr_count, int txr_idx,
1159 int rxr_count, int rxr_idx)
1160 {
1161 struct igb_q_vector *q_vector;
1162 struct igb_ring *ring;
1163 int ring_count, size;
1164
1165 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1166 if (txr_count > 1 || rxr_count > 1)
1167 return -ENOMEM;
1168
1169 ring_count = txr_count + rxr_count;
1170 size = sizeof(struct igb_q_vector) +
1171 (sizeof(struct igb_ring) * ring_count);
1172
1173 /* allocate q_vector and rings */
1174 q_vector = kzalloc(size, GFP_KERNEL);
1175 if (!q_vector)
1176 return -ENOMEM;
1177
1178 /* initialize NAPI */
1179 netif_napi_add(adapter->netdev, &q_vector->napi,
1180 igb_poll, 64);
1181
1182 /* tie q_vector and adapter together */
1183 adapter->q_vector[v_idx] = q_vector;
1184 q_vector->adapter = adapter;
1185
1186 /* initialize work limits */
1187 q_vector->tx.work_limit = adapter->tx_work_limit;
1188
1189 /* initialize ITR configuration */
1190 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1191 q_vector->itr_val = IGB_START_ITR;
1192
1193 /* initialize pointer to rings */
1194 ring = q_vector->ring;
1195
1196 /* intialize ITR */
1197 if (rxr_count) {
1198 /* rx or rx/tx vector */
1199 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1200 q_vector->itr_val = adapter->rx_itr_setting;
1201 } else {
1202 /* tx only vector */
1203 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1204 q_vector->itr_val = adapter->tx_itr_setting;
1205 }
1206
1207 if (txr_count) {
1208 /* assign generic ring traits */
1209 ring->dev = &adapter->pdev->dev;
1210 ring->netdev = adapter->netdev;
1211
1212 /* configure backlink on ring */
1213 ring->q_vector = q_vector;
1214
1215 /* update q_vector Tx values */
1216 igb_add_ring(ring, &q_vector->tx);
1217
1218 /* For 82575, context index must be unique per ring. */
1219 if (adapter->hw.mac.type == e1000_82575)
1220 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1221
1222 /* apply Tx specific ring traits */
1223 ring->count = adapter->tx_ring_count;
1224 ring->queue_index = txr_idx;
1225
1226 /* assign ring to adapter */
1227 adapter->tx_ring[txr_idx] = ring;
1228
1229 /* push pointer to next ring */
1230 ring++;
1231 }
1232
1233 if (rxr_count) {
1234 /* assign generic ring traits */
1235 ring->dev = &adapter->pdev->dev;
1236 ring->netdev = adapter->netdev;
1237
1238 /* configure backlink on ring */
1239 ring->q_vector = q_vector;
1240
1241 /* update q_vector Rx values */
1242 igb_add_ring(ring, &q_vector->rx);
1243
1244 /* set flag indicating ring supports SCTP checksum offload */
1245 if (adapter->hw.mac.type >= e1000_82576)
1246 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1247
1248 /*
1249 * On i350, i354, i210, and i211, loopback VLAN packets
1250 * have the tag byte-swapped.
1251 */
1252 if (adapter->hw.mac.type >= e1000_i350)
1253 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1254
1255 /* apply Rx specific ring traits */
1256 ring->count = adapter->rx_ring_count;
1257 ring->queue_index = rxr_idx;
1258
1259 /* assign ring to adapter */
1260 adapter->rx_ring[rxr_idx] = ring;
1261 }
1262
1263 return 0;
1264 }
1265
1266
1267 /**
1268 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1269 * @adapter: board private structure to initialize
1270 *
1271 * We allocate one q_vector per queue interrupt. If allocation fails we
1272 * return -ENOMEM.
1273 **/
1274 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1275 {
1276 int q_vectors = adapter->num_q_vectors;
1277 int rxr_remaining = adapter->num_rx_queues;
1278 int txr_remaining = adapter->num_tx_queues;
1279 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1280 int err;
1281
1282 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1283 for (; rxr_remaining; v_idx++) {
1284 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1285 0, 0, 1, rxr_idx);
1286
1287 if (err)
1288 goto err_out;
1289
1290 /* update counts and index */
1291 rxr_remaining--;
1292 rxr_idx++;
1293 }
1294 }
1295
1296 for (; v_idx < q_vectors; v_idx++) {
1297 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1298 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1299 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1300 tqpv, txr_idx, rqpv, rxr_idx);
1301
1302 if (err)
1303 goto err_out;
1304
1305 /* update counts and index */
1306 rxr_remaining -= rqpv;
1307 txr_remaining -= tqpv;
1308 rxr_idx++;
1309 txr_idx++;
1310 }
1311
1312 return 0;
1313
1314 err_out:
1315 adapter->num_tx_queues = 0;
1316 adapter->num_rx_queues = 0;
1317 adapter->num_q_vectors = 0;
1318
1319 while (v_idx--)
1320 igb_free_q_vector(adapter, v_idx);
1321
1322 return -ENOMEM;
1323 }
1324
1325 /**
1326 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1327 * @adapter: board private structure to initialize
1328 * @msix: boolean value of MSIX capability
1329 *
1330 * This function initializes the interrupts and allocates all of the queues.
1331 **/
1332 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1333 {
1334 struct pci_dev *pdev = adapter->pdev;
1335 int err;
1336
1337 igb_set_interrupt_capability(adapter, msix);
1338
1339 err = igb_alloc_q_vectors(adapter);
1340 if (err) {
1341 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1342 goto err_alloc_q_vectors;
1343 }
1344
1345 igb_cache_ring_register(adapter);
1346
1347 return 0;
1348
1349 err_alloc_q_vectors:
1350 igb_reset_interrupt_capability(adapter);
1351 return err;
1352 }
1353
1354 /**
1355 * igb_request_irq - initialize interrupts
1356 * @adapter: board private structure to initialize
1357 *
1358 * Attempts to configure interrupts using the best available
1359 * capabilities of the hardware and kernel.
1360 **/
1361 static int igb_request_irq(struct igb_adapter *adapter)
1362 {
1363 struct net_device *netdev = adapter->netdev;
1364 struct pci_dev *pdev = adapter->pdev;
1365 int err = 0;
1366
1367 if (adapter->msix_entries) {
1368 err = igb_request_msix(adapter);
1369 if (!err)
1370 goto request_done;
1371 /* fall back to MSI */
1372 igb_free_all_tx_resources(adapter);
1373 igb_free_all_rx_resources(adapter);
1374
1375 igb_clear_interrupt_scheme(adapter);
1376 err = igb_init_interrupt_scheme(adapter, false);
1377 if (err)
1378 goto request_done;
1379
1380 igb_setup_all_tx_resources(adapter);
1381 igb_setup_all_rx_resources(adapter);
1382 igb_configure(adapter);
1383 }
1384
1385 igb_assign_vector(adapter->q_vector[0], 0);
1386
1387 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1388 err = request_irq(pdev->irq, igb_intr_msi, 0,
1389 netdev->name, adapter);
1390 if (!err)
1391 goto request_done;
1392
1393 /* fall back to legacy interrupts */
1394 igb_reset_interrupt_capability(adapter);
1395 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1396 }
1397
1398 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1399 netdev->name, adapter);
1400
1401 if (err)
1402 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1403 err);
1404
1405 request_done:
1406 return err;
1407 }
1408
1409 static void igb_free_irq(struct igb_adapter *adapter)
1410 {
1411 if (adapter->msix_entries) {
1412 int vector = 0, i;
1413
1414 free_irq(adapter->msix_entries[vector++].vector, adapter);
1415
1416 for (i = 0; i < adapter->num_q_vectors; i++)
1417 free_irq(adapter->msix_entries[vector++].vector,
1418 adapter->q_vector[i]);
1419 } else {
1420 free_irq(adapter->pdev->irq, adapter);
1421 }
1422 }
1423
1424 /**
1425 * igb_irq_disable - Mask off interrupt generation on the NIC
1426 * @adapter: board private structure
1427 **/
1428 static void igb_irq_disable(struct igb_adapter *adapter)
1429 {
1430 struct e1000_hw *hw = &adapter->hw;
1431
1432 /* we need to be careful when disabling interrupts. The VFs are also
1433 * mapped into these registers and so clearing the bits can cause
1434 * issues on the VF drivers so we only need to clear what we set
1435 */
1436 if (adapter->msix_entries) {
1437 u32 regval = rd32(E1000_EIAM);
1438 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1439 wr32(E1000_EIMC, adapter->eims_enable_mask);
1440 regval = rd32(E1000_EIAC);
1441 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1442 }
1443
1444 wr32(E1000_IAM, 0);
1445 wr32(E1000_IMC, ~0);
1446 wrfl();
1447 if (adapter->msix_entries) {
1448 int i;
1449 for (i = 0; i < adapter->num_q_vectors; i++)
1450 synchronize_irq(adapter->msix_entries[i].vector);
1451 } else {
1452 synchronize_irq(adapter->pdev->irq);
1453 }
1454 }
1455
1456 /**
1457 * igb_irq_enable - Enable default interrupt generation settings
1458 * @adapter: board private structure
1459 **/
1460 static void igb_irq_enable(struct igb_adapter *adapter)
1461 {
1462 struct e1000_hw *hw = &adapter->hw;
1463
1464 if (adapter->msix_entries) {
1465 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1466 u32 regval = rd32(E1000_EIAC);
1467 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1468 regval = rd32(E1000_EIAM);
1469 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1470 wr32(E1000_EIMS, adapter->eims_enable_mask);
1471 if (adapter->vfs_allocated_count) {
1472 wr32(E1000_MBVFIMR, 0xFF);
1473 ims |= E1000_IMS_VMMB;
1474 }
1475 wr32(E1000_IMS, ims);
1476 } else {
1477 wr32(E1000_IMS, IMS_ENABLE_MASK |
1478 E1000_IMS_DRSTA);
1479 wr32(E1000_IAM, IMS_ENABLE_MASK |
1480 E1000_IMS_DRSTA);
1481 }
1482 }
1483
1484 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1485 {
1486 struct e1000_hw *hw = &adapter->hw;
1487 u16 vid = adapter->hw.mng_cookie.vlan_id;
1488 u16 old_vid = adapter->mng_vlan_id;
1489
1490 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1491 /* add VID to filter table */
1492 igb_vfta_set(hw, vid, true);
1493 adapter->mng_vlan_id = vid;
1494 } else {
1495 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1496 }
1497
1498 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1499 (vid != old_vid) &&
1500 !test_bit(old_vid, adapter->active_vlans)) {
1501 /* remove VID from filter table */
1502 igb_vfta_set(hw, old_vid, false);
1503 }
1504 }
1505
1506 /**
1507 * igb_release_hw_control - release control of the h/w to f/w
1508 * @adapter: address of board private structure
1509 *
1510 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1511 * For ASF and Pass Through versions of f/w this means that the
1512 * driver is no longer loaded.
1513 **/
1514 static void igb_release_hw_control(struct igb_adapter *adapter)
1515 {
1516 struct e1000_hw *hw = &adapter->hw;
1517 u32 ctrl_ext;
1518
1519 /* Let firmware take over control of h/w */
1520 ctrl_ext = rd32(E1000_CTRL_EXT);
1521 wr32(E1000_CTRL_EXT,
1522 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1523 }
1524
1525 /**
1526 * igb_get_hw_control - get control of the h/w from f/w
1527 * @adapter: address of board private structure
1528 *
1529 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1530 * For ASF and Pass Through versions of f/w this means that
1531 * the driver is loaded.
1532 **/
1533 static void igb_get_hw_control(struct igb_adapter *adapter)
1534 {
1535 struct e1000_hw *hw = &adapter->hw;
1536 u32 ctrl_ext;
1537
1538 /* Let firmware know the driver has taken over */
1539 ctrl_ext = rd32(E1000_CTRL_EXT);
1540 wr32(E1000_CTRL_EXT,
1541 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1542 }
1543
1544 /**
1545 * igb_configure - configure the hardware for RX and TX
1546 * @adapter: private board structure
1547 **/
1548 static void igb_configure(struct igb_adapter *adapter)
1549 {
1550 struct net_device *netdev = adapter->netdev;
1551 int i;
1552
1553 igb_get_hw_control(adapter);
1554 igb_set_rx_mode(netdev);
1555
1556 igb_restore_vlan(adapter);
1557
1558 igb_setup_tctl(adapter);
1559 igb_setup_mrqc(adapter);
1560 igb_setup_rctl(adapter);
1561
1562 igb_configure_tx(adapter);
1563 igb_configure_rx(adapter);
1564
1565 igb_rx_fifo_flush_82575(&adapter->hw);
1566
1567 /* call igb_desc_unused which always leaves
1568 * at least 1 descriptor unused to make sure
1569 * next_to_use != next_to_clean
1570 */
1571 for (i = 0; i < adapter->num_rx_queues; i++) {
1572 struct igb_ring *ring = adapter->rx_ring[i];
1573 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1574 }
1575 }
1576
1577 /**
1578 * igb_power_up_link - Power up the phy/serdes link
1579 * @adapter: address of board private structure
1580 **/
1581 void igb_power_up_link(struct igb_adapter *adapter)
1582 {
1583 igb_reset_phy(&adapter->hw);
1584
1585 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1586 igb_power_up_phy_copper(&adapter->hw);
1587 else
1588 igb_power_up_serdes_link_82575(&adapter->hw);
1589 }
1590
1591 /**
1592 * igb_power_down_link - Power down the phy/serdes link
1593 * @adapter: address of board private structure
1594 */
1595 static void igb_power_down_link(struct igb_adapter *adapter)
1596 {
1597 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1598 igb_power_down_phy_copper_82575(&adapter->hw);
1599 else
1600 igb_shutdown_serdes_link_82575(&adapter->hw);
1601 }
1602
1603 /**
1604 * igb_up - Open the interface and prepare it to handle traffic
1605 * @adapter: board private structure
1606 **/
1607 int igb_up(struct igb_adapter *adapter)
1608 {
1609 struct e1000_hw *hw = &adapter->hw;
1610 int i;
1611
1612 /* hardware has been reset, we need to reload some things */
1613 igb_configure(adapter);
1614
1615 clear_bit(__IGB_DOWN, &adapter->state);
1616
1617 for (i = 0; i < adapter->num_q_vectors; i++)
1618 napi_enable(&(adapter->q_vector[i]->napi));
1619
1620 if (adapter->msix_entries)
1621 igb_configure_msix(adapter);
1622 else
1623 igb_assign_vector(adapter->q_vector[0], 0);
1624
1625 /* Clear any pending interrupts. */
1626 rd32(E1000_ICR);
1627 igb_irq_enable(adapter);
1628
1629 /* notify VFs that reset has been completed */
1630 if (adapter->vfs_allocated_count) {
1631 u32 reg_data = rd32(E1000_CTRL_EXT);
1632 reg_data |= E1000_CTRL_EXT_PFRSTD;
1633 wr32(E1000_CTRL_EXT, reg_data);
1634 }
1635
1636 netif_tx_start_all_queues(adapter->netdev);
1637
1638 /* start the watchdog. */
1639 hw->mac.get_link_status = 1;
1640 schedule_work(&adapter->watchdog_task);
1641
1642 return 0;
1643 }
1644
1645 void igb_down(struct igb_adapter *adapter)
1646 {
1647 struct net_device *netdev = adapter->netdev;
1648 struct e1000_hw *hw = &adapter->hw;
1649 u32 tctl, rctl;
1650 int i;
1651
1652 /* signal that we're down so the interrupt handler does not
1653 * reschedule our watchdog timer
1654 */
1655 set_bit(__IGB_DOWN, &adapter->state);
1656
1657 /* disable receives in the hardware */
1658 rctl = rd32(E1000_RCTL);
1659 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1660 /* flush and sleep below */
1661
1662 netif_tx_stop_all_queues(netdev);
1663
1664 /* disable transmits in the hardware */
1665 tctl = rd32(E1000_TCTL);
1666 tctl &= ~E1000_TCTL_EN;
1667 wr32(E1000_TCTL, tctl);
1668 /* flush both disables and wait for them to finish */
1669 wrfl();
1670 msleep(10);
1671
1672 igb_irq_disable(adapter);
1673
1674 for (i = 0; i < adapter->num_q_vectors; i++) {
1675 napi_synchronize(&(adapter->q_vector[i]->napi));
1676 napi_disable(&(adapter->q_vector[i]->napi));
1677 }
1678
1679
1680 del_timer_sync(&adapter->watchdog_timer);
1681 del_timer_sync(&adapter->phy_info_timer);
1682
1683 netif_carrier_off(netdev);
1684
1685 /* record the stats before reset*/
1686 spin_lock(&adapter->stats64_lock);
1687 igb_update_stats(adapter, &adapter->stats64);
1688 spin_unlock(&adapter->stats64_lock);
1689
1690 adapter->link_speed = 0;
1691 adapter->link_duplex = 0;
1692
1693 if (!pci_channel_offline(adapter->pdev))
1694 igb_reset(adapter);
1695 igb_clean_all_tx_rings(adapter);
1696 igb_clean_all_rx_rings(adapter);
1697 #ifdef CONFIG_IGB_DCA
1698
1699 /* since we reset the hardware DCA settings were cleared */
1700 igb_setup_dca(adapter);
1701 #endif
1702 }
1703
1704 void igb_reinit_locked(struct igb_adapter *adapter)
1705 {
1706 WARN_ON(in_interrupt());
1707 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1708 msleep(1);
1709 igb_down(adapter);
1710 igb_up(adapter);
1711 clear_bit(__IGB_RESETTING, &adapter->state);
1712 }
1713
1714 void igb_reset(struct igb_adapter *adapter)
1715 {
1716 struct pci_dev *pdev = adapter->pdev;
1717 struct e1000_hw *hw = &adapter->hw;
1718 struct e1000_mac_info *mac = &hw->mac;
1719 struct e1000_fc_info *fc = &hw->fc;
1720 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1721
1722 /* Repartition Pba for greater than 9k mtu
1723 * To take effect CTRL.RST is required.
1724 */
1725 switch (mac->type) {
1726 case e1000_i350:
1727 case e1000_i354:
1728 case e1000_82580:
1729 pba = rd32(E1000_RXPBS);
1730 pba = igb_rxpbs_adjust_82580(pba);
1731 break;
1732 case e1000_82576:
1733 pba = rd32(E1000_RXPBS);
1734 pba &= E1000_RXPBS_SIZE_MASK_82576;
1735 break;
1736 case e1000_82575:
1737 case e1000_i210:
1738 case e1000_i211:
1739 default:
1740 pba = E1000_PBA_34K;
1741 break;
1742 }
1743
1744 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1745 (mac->type < e1000_82576)) {
1746 /* adjust PBA for jumbo frames */
1747 wr32(E1000_PBA, pba);
1748
1749 /* To maintain wire speed transmits, the Tx FIFO should be
1750 * large enough to accommodate two full transmit packets,
1751 * rounded up to the next 1KB and expressed in KB. Likewise,
1752 * the Rx FIFO should be large enough to accommodate at least
1753 * one full receive packet and is similarly rounded up and
1754 * expressed in KB.
1755 */
1756 pba = rd32(E1000_PBA);
1757 /* upper 16 bits has Tx packet buffer allocation size in KB */
1758 tx_space = pba >> 16;
1759 /* lower 16 bits has Rx packet buffer allocation size in KB */
1760 pba &= 0xffff;
1761 /* the Tx fifo also stores 16 bytes of information about the Tx
1762 * but don't include ethernet FCS because hardware appends it
1763 */
1764 min_tx_space = (adapter->max_frame_size +
1765 sizeof(union e1000_adv_tx_desc) -
1766 ETH_FCS_LEN) * 2;
1767 min_tx_space = ALIGN(min_tx_space, 1024);
1768 min_tx_space >>= 10;
1769 /* software strips receive CRC, so leave room for it */
1770 min_rx_space = adapter->max_frame_size;
1771 min_rx_space = ALIGN(min_rx_space, 1024);
1772 min_rx_space >>= 10;
1773
1774 /* If current Tx allocation is less than the min Tx FIFO size,
1775 * and the min Tx FIFO size is less than the current Rx FIFO
1776 * allocation, take space away from current Rx allocation
1777 */
1778 if (tx_space < min_tx_space &&
1779 ((min_tx_space - tx_space) < pba)) {
1780 pba = pba - (min_tx_space - tx_space);
1781
1782 /* if short on Rx space, Rx wins and must trump Tx
1783 * adjustment
1784 */
1785 if (pba < min_rx_space)
1786 pba = min_rx_space;
1787 }
1788 wr32(E1000_PBA, pba);
1789 }
1790
1791 /* flow control settings */
1792 /* The high water mark must be low enough to fit one full frame
1793 * (or the size used for early receive) above it in the Rx FIFO.
1794 * Set it to the lower of:
1795 * - 90% of the Rx FIFO size, or
1796 * - the full Rx FIFO size minus one full frame
1797 */
1798 hwm = min(((pba << 10) * 9 / 10),
1799 ((pba << 10) - 2 * adapter->max_frame_size));
1800
1801 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1802 fc->low_water = fc->high_water - 16;
1803 fc->pause_time = 0xFFFF;
1804 fc->send_xon = 1;
1805 fc->current_mode = fc->requested_mode;
1806
1807 /* disable receive for all VFs and wait one second */
1808 if (adapter->vfs_allocated_count) {
1809 int i;
1810 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1811 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1812
1813 /* ping all the active vfs to let them know we are going down */
1814 igb_ping_all_vfs(adapter);
1815
1816 /* disable transmits and receives */
1817 wr32(E1000_VFRE, 0);
1818 wr32(E1000_VFTE, 0);
1819 }
1820
1821 /* Allow time for pending master requests to run */
1822 hw->mac.ops.reset_hw(hw);
1823 wr32(E1000_WUC, 0);
1824
1825 if (hw->mac.ops.init_hw(hw))
1826 dev_err(&pdev->dev, "Hardware Error\n");
1827
1828 /* Flow control settings reset on hardware reset, so guarantee flow
1829 * control is off when forcing speed.
1830 */
1831 if (!hw->mac.autoneg)
1832 igb_force_mac_fc(hw);
1833
1834 igb_init_dmac(adapter, pba);
1835 #ifdef CONFIG_IGB_HWMON
1836 /* Re-initialize the thermal sensor on i350 devices. */
1837 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1838 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1839 /* If present, re-initialize the external thermal sensor
1840 * interface.
1841 */
1842 if (adapter->ets)
1843 mac->ops.init_thermal_sensor_thresh(hw);
1844 }
1845 }
1846 #endif
1847 if (!netif_running(adapter->netdev))
1848 igb_power_down_link(adapter);
1849
1850 igb_update_mng_vlan(adapter);
1851
1852 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1853 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1854
1855 /* Re-enable PTP, where applicable. */
1856 igb_ptp_reset(adapter);
1857
1858 igb_get_phy_info(hw);
1859 }
1860
1861 static netdev_features_t igb_fix_features(struct net_device *netdev,
1862 netdev_features_t features)
1863 {
1864 /* Since there is no support for separate Rx/Tx vlan accel
1865 * enable/disable make sure Tx flag is always in same state as Rx.
1866 */
1867 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1868 features |= NETIF_F_HW_VLAN_CTAG_TX;
1869 else
1870 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1871
1872 return features;
1873 }
1874
1875 static int igb_set_features(struct net_device *netdev,
1876 netdev_features_t features)
1877 {
1878 netdev_features_t changed = netdev->features ^ features;
1879 struct igb_adapter *adapter = netdev_priv(netdev);
1880
1881 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1882 igb_vlan_mode(netdev, features);
1883
1884 if (!(changed & NETIF_F_RXALL))
1885 return 0;
1886
1887 netdev->features = features;
1888
1889 if (netif_running(netdev))
1890 igb_reinit_locked(adapter);
1891 else
1892 igb_reset(adapter);
1893
1894 return 0;
1895 }
1896
1897 static const struct net_device_ops igb_netdev_ops = {
1898 .ndo_open = igb_open,
1899 .ndo_stop = igb_close,
1900 .ndo_start_xmit = igb_xmit_frame,
1901 .ndo_get_stats64 = igb_get_stats64,
1902 .ndo_set_rx_mode = igb_set_rx_mode,
1903 .ndo_set_mac_address = igb_set_mac,
1904 .ndo_change_mtu = igb_change_mtu,
1905 .ndo_do_ioctl = igb_ioctl,
1906 .ndo_tx_timeout = igb_tx_timeout,
1907 .ndo_validate_addr = eth_validate_addr,
1908 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1909 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1910 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1911 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1912 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1913 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
1914 .ndo_get_vf_config = igb_ndo_get_vf_config,
1915 #ifdef CONFIG_NET_POLL_CONTROLLER
1916 .ndo_poll_controller = igb_netpoll,
1917 #endif
1918 .ndo_fix_features = igb_fix_features,
1919 .ndo_set_features = igb_set_features,
1920 };
1921
1922 /**
1923 * igb_set_fw_version - Configure version string for ethtool
1924 * @adapter: adapter struct
1925 **/
1926 void igb_set_fw_version(struct igb_adapter *adapter)
1927 {
1928 struct e1000_hw *hw = &adapter->hw;
1929 struct e1000_fw_version fw;
1930
1931 igb_get_fw_version(hw, &fw);
1932
1933 switch (hw->mac.type) {
1934 case e1000_i211:
1935 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1936 "%2d.%2d-%d",
1937 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1938 break;
1939
1940 default:
1941 /* if option is rom valid, display its version too */
1942 if (fw.or_valid) {
1943 snprintf(adapter->fw_version,
1944 sizeof(adapter->fw_version),
1945 "%d.%d, 0x%08x, %d.%d.%d",
1946 fw.eep_major, fw.eep_minor, fw.etrack_id,
1947 fw.or_major, fw.or_build, fw.or_patch);
1948 /* no option rom */
1949 } else {
1950 snprintf(adapter->fw_version,
1951 sizeof(adapter->fw_version),
1952 "%d.%d, 0x%08x",
1953 fw.eep_major, fw.eep_minor, fw.etrack_id);
1954 }
1955 break;
1956 }
1957 return;
1958 }
1959
1960 /**
1961 * igb_init_i2c - Init I2C interface
1962 * @adapter: pointer to adapter structure
1963 **/
1964 static s32 igb_init_i2c(struct igb_adapter *adapter)
1965 {
1966 s32 status = E1000_SUCCESS;
1967
1968 /* I2C interface supported on i350 devices */
1969 if (adapter->hw.mac.type != e1000_i350)
1970 return E1000_SUCCESS;
1971
1972 /* Initialize the i2c bus which is controlled by the registers.
1973 * This bus will use the i2c_algo_bit structue that implements
1974 * the protocol through toggling of the 4 bits in the register.
1975 */
1976 adapter->i2c_adap.owner = THIS_MODULE;
1977 adapter->i2c_algo = igb_i2c_algo;
1978 adapter->i2c_algo.data = adapter;
1979 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1980 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1981 strlcpy(adapter->i2c_adap.name, "igb BB",
1982 sizeof(adapter->i2c_adap.name));
1983 status = i2c_bit_add_bus(&adapter->i2c_adap);
1984 return status;
1985 }
1986
1987 /**
1988 * igb_probe - Device Initialization Routine
1989 * @pdev: PCI device information struct
1990 * @ent: entry in igb_pci_tbl
1991 *
1992 * Returns 0 on success, negative on failure
1993 *
1994 * igb_probe initializes an adapter identified by a pci_dev structure.
1995 * The OS initialization, configuring of the adapter private structure,
1996 * and a hardware reset occur.
1997 **/
1998 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1999 {
2000 struct net_device *netdev;
2001 struct igb_adapter *adapter;
2002 struct e1000_hw *hw;
2003 u16 eeprom_data = 0;
2004 s32 ret_val;
2005 static int global_quad_port_a; /* global quad port a indication */
2006 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2007 unsigned long mmio_start, mmio_len;
2008 int err, pci_using_dac;
2009 u8 part_str[E1000_PBANUM_LENGTH];
2010
2011 /* Catch broken hardware that put the wrong VF device ID in
2012 * the PCIe SR-IOV capability.
2013 */
2014 if (pdev->is_virtfn) {
2015 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2016 pci_name(pdev), pdev->vendor, pdev->device);
2017 return -EINVAL;
2018 }
2019
2020 err = pci_enable_device_mem(pdev);
2021 if (err)
2022 return err;
2023
2024 pci_using_dac = 0;
2025 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
2026 if (!err) {
2027 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
2028 if (!err)
2029 pci_using_dac = 1;
2030 } else {
2031 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2032 if (err) {
2033 err = dma_set_coherent_mask(&pdev->dev,
2034 DMA_BIT_MASK(32));
2035 if (err) {
2036 dev_err(&pdev->dev,
2037 "No usable DMA configuration, aborting\n");
2038 goto err_dma;
2039 }
2040 }
2041 }
2042
2043 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2044 IORESOURCE_MEM),
2045 igb_driver_name);
2046 if (err)
2047 goto err_pci_reg;
2048
2049 pci_enable_pcie_error_reporting(pdev);
2050
2051 pci_set_master(pdev);
2052 pci_save_state(pdev);
2053
2054 err = -ENOMEM;
2055 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2056 IGB_MAX_TX_QUEUES);
2057 if (!netdev)
2058 goto err_alloc_etherdev;
2059
2060 SET_NETDEV_DEV(netdev, &pdev->dev);
2061
2062 pci_set_drvdata(pdev, netdev);
2063 adapter = netdev_priv(netdev);
2064 adapter->netdev = netdev;
2065 adapter->pdev = pdev;
2066 hw = &adapter->hw;
2067 hw->back = adapter;
2068 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2069
2070 mmio_start = pci_resource_start(pdev, 0);
2071 mmio_len = pci_resource_len(pdev, 0);
2072
2073 err = -EIO;
2074 hw->hw_addr = ioremap(mmio_start, mmio_len);
2075 if (!hw->hw_addr)
2076 goto err_ioremap;
2077
2078 netdev->netdev_ops = &igb_netdev_ops;
2079 igb_set_ethtool_ops(netdev);
2080 netdev->watchdog_timeo = 5 * HZ;
2081
2082 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2083
2084 netdev->mem_start = mmio_start;
2085 netdev->mem_end = mmio_start + mmio_len;
2086
2087 /* PCI config space info */
2088 hw->vendor_id = pdev->vendor;
2089 hw->device_id = pdev->device;
2090 hw->revision_id = pdev->revision;
2091 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2092 hw->subsystem_device_id = pdev->subsystem_device;
2093
2094 /* Copy the default MAC, PHY and NVM function pointers */
2095 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2096 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2097 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2098 /* Initialize skew-specific constants */
2099 err = ei->get_invariants(hw);
2100 if (err)
2101 goto err_sw_init;
2102
2103 /* setup the private structure */
2104 err = igb_sw_init(adapter);
2105 if (err)
2106 goto err_sw_init;
2107
2108 igb_get_bus_info_pcie(hw);
2109
2110 hw->phy.autoneg_wait_to_complete = false;
2111
2112 /* Copper options */
2113 if (hw->phy.media_type == e1000_media_type_copper) {
2114 hw->phy.mdix = AUTO_ALL_MODES;
2115 hw->phy.disable_polarity_correction = false;
2116 hw->phy.ms_type = e1000_ms_hw_default;
2117 }
2118
2119 if (igb_check_reset_block(hw))
2120 dev_info(&pdev->dev,
2121 "PHY reset is blocked due to SOL/IDER session.\n");
2122
2123 /* features is initialized to 0 in allocation, it might have bits
2124 * set by igb_sw_init so we should use an or instead of an
2125 * assignment.
2126 */
2127 netdev->features |= NETIF_F_SG |
2128 NETIF_F_IP_CSUM |
2129 NETIF_F_IPV6_CSUM |
2130 NETIF_F_TSO |
2131 NETIF_F_TSO6 |
2132 NETIF_F_RXHASH |
2133 NETIF_F_RXCSUM |
2134 NETIF_F_HW_VLAN_CTAG_RX |
2135 NETIF_F_HW_VLAN_CTAG_TX;
2136
2137 /* copy netdev features into list of user selectable features */
2138 netdev->hw_features |= netdev->features;
2139 netdev->hw_features |= NETIF_F_RXALL;
2140
2141 /* set this bit last since it cannot be part of hw_features */
2142 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2143
2144 netdev->vlan_features |= NETIF_F_TSO |
2145 NETIF_F_TSO6 |
2146 NETIF_F_IP_CSUM |
2147 NETIF_F_IPV6_CSUM |
2148 NETIF_F_SG;
2149
2150 netdev->priv_flags |= IFF_SUPP_NOFCS;
2151
2152 if (pci_using_dac) {
2153 netdev->features |= NETIF_F_HIGHDMA;
2154 netdev->vlan_features |= NETIF_F_HIGHDMA;
2155 }
2156
2157 if (hw->mac.type >= e1000_82576) {
2158 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2159 netdev->features |= NETIF_F_SCTP_CSUM;
2160 }
2161
2162 netdev->priv_flags |= IFF_UNICAST_FLT;
2163
2164 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2165
2166 /* before reading the NVM, reset the controller to put the device in a
2167 * known good starting state
2168 */
2169 hw->mac.ops.reset_hw(hw);
2170
2171 /* make sure the NVM is good , i211/i210 parts can have special NVM
2172 * that doesn't contain a checksum
2173 */
2174 switch (hw->mac.type) {
2175 case e1000_i210:
2176 case e1000_i211:
2177 if (igb_get_flash_presence_i210(hw)) {
2178 if (hw->nvm.ops.validate(hw) < 0) {
2179 dev_err(&pdev->dev,
2180 "The NVM Checksum Is Not Valid\n");
2181 err = -EIO;
2182 goto err_eeprom;
2183 }
2184 }
2185 break;
2186 default:
2187 if (hw->nvm.ops.validate(hw) < 0) {
2188 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2189 err = -EIO;
2190 goto err_eeprom;
2191 }
2192 break;
2193 }
2194
2195 /* copy the MAC address out of the NVM */
2196 if (hw->mac.ops.read_mac_addr(hw))
2197 dev_err(&pdev->dev, "NVM Read Error\n");
2198
2199 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2200
2201 if (!is_valid_ether_addr(netdev->dev_addr)) {
2202 dev_err(&pdev->dev, "Invalid MAC Address\n");
2203 err = -EIO;
2204 goto err_eeprom;
2205 }
2206
2207 /* get firmware version for ethtool -i */
2208 igb_set_fw_version(adapter);
2209
2210 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2211 (unsigned long) adapter);
2212 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2213 (unsigned long) adapter);
2214
2215 INIT_WORK(&adapter->reset_task, igb_reset_task);
2216 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2217
2218 /* Initialize link properties that are user-changeable */
2219 adapter->fc_autoneg = true;
2220 hw->mac.autoneg = true;
2221 hw->phy.autoneg_advertised = 0x2f;
2222
2223 hw->fc.requested_mode = e1000_fc_default;
2224 hw->fc.current_mode = e1000_fc_default;
2225
2226 igb_validate_mdi_setting(hw);
2227
2228 /* By default, support wake on port A */
2229 if (hw->bus.func == 0)
2230 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2231
2232 /* Check the NVM for wake support on non-port A ports */
2233 if (hw->mac.type >= e1000_82580)
2234 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2235 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2236 &eeprom_data);
2237 else if (hw->bus.func == 1)
2238 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2239
2240 if (eeprom_data & IGB_EEPROM_APME)
2241 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2242
2243 /* now that we have the eeprom settings, apply the special cases where
2244 * the eeprom may be wrong or the board simply won't support wake on
2245 * lan on a particular port
2246 */
2247 switch (pdev->device) {
2248 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2249 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2250 break;
2251 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2252 case E1000_DEV_ID_82576_FIBER:
2253 case E1000_DEV_ID_82576_SERDES:
2254 /* Wake events only supported on port A for dual fiber
2255 * regardless of eeprom setting
2256 */
2257 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2258 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2259 break;
2260 case E1000_DEV_ID_82576_QUAD_COPPER:
2261 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2262 /* if quad port adapter, disable WoL on all but port A */
2263 if (global_quad_port_a != 0)
2264 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2265 else
2266 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2267 /* Reset for multiple quad port adapters */
2268 if (++global_quad_port_a == 4)
2269 global_quad_port_a = 0;
2270 break;
2271 default:
2272 /* If the device can't wake, don't set software support */
2273 if (!device_can_wakeup(&adapter->pdev->dev))
2274 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2275 }
2276
2277 /* initialize the wol settings based on the eeprom settings */
2278 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2279 adapter->wol |= E1000_WUFC_MAG;
2280
2281 /* Some vendors want WoL disabled by default, but still supported */
2282 if ((hw->mac.type == e1000_i350) &&
2283 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2284 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2285 adapter->wol = 0;
2286 }
2287
2288 device_set_wakeup_enable(&adapter->pdev->dev,
2289 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2290
2291 /* reset the hardware with the new settings */
2292 igb_reset(adapter);
2293
2294 /* Init the I2C interface */
2295 err = igb_init_i2c(adapter);
2296 if (err) {
2297 dev_err(&pdev->dev, "failed to init i2c interface\n");
2298 goto err_eeprom;
2299 }
2300
2301 /* let the f/w know that the h/w is now under the control of the
2302 * driver. */
2303 igb_get_hw_control(adapter);
2304
2305 strcpy(netdev->name, "eth%d");
2306 err = register_netdev(netdev);
2307 if (err)
2308 goto err_register;
2309
2310 /* carrier off reporting is important to ethtool even BEFORE open */
2311 netif_carrier_off(netdev);
2312
2313 #ifdef CONFIG_IGB_DCA
2314 if (dca_add_requester(&pdev->dev) == 0) {
2315 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2316 dev_info(&pdev->dev, "DCA enabled\n");
2317 igb_setup_dca(adapter);
2318 }
2319
2320 #endif
2321 #ifdef CONFIG_IGB_HWMON
2322 /* Initialize the thermal sensor on i350 devices. */
2323 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2324 u16 ets_word;
2325
2326 /* Read the NVM to determine if this i350 device supports an
2327 * external thermal sensor.
2328 */
2329 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2330 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2331 adapter->ets = true;
2332 else
2333 adapter->ets = false;
2334 if (igb_sysfs_init(adapter))
2335 dev_err(&pdev->dev,
2336 "failed to allocate sysfs resources\n");
2337 } else {
2338 adapter->ets = false;
2339 }
2340 #endif
2341 /* do hw tstamp init after resetting */
2342 igb_ptp_init(adapter);
2343
2344 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2345 /* print bus type/speed/width info, not applicable to i354 */
2346 if (hw->mac.type != e1000_i354) {
2347 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2348 netdev->name,
2349 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2350 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2351 "unknown"),
2352 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2353 "Width x4" :
2354 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2355 "Width x2" :
2356 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2357 "Width x1" : "unknown"), netdev->dev_addr);
2358 }
2359
2360 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2361 if (ret_val)
2362 strcpy(part_str, "Unknown");
2363 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2364 dev_info(&pdev->dev,
2365 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2366 adapter->msix_entries ? "MSI-X" :
2367 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2368 adapter->num_rx_queues, adapter->num_tx_queues);
2369 switch (hw->mac.type) {
2370 case e1000_i350:
2371 case e1000_i210:
2372 case e1000_i211:
2373 igb_set_eee_i350(hw);
2374 break;
2375 case e1000_i354:
2376 if (hw->phy.media_type == e1000_media_type_copper) {
2377 if ((rd32(E1000_CTRL_EXT) &
2378 E1000_CTRL_EXT_LINK_MODE_SGMII))
2379 igb_set_eee_i354(hw);
2380 }
2381 break;
2382 default:
2383 break;
2384 }
2385
2386 pm_runtime_put_noidle(&pdev->dev);
2387 return 0;
2388
2389 err_register:
2390 igb_release_hw_control(adapter);
2391 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2392 err_eeprom:
2393 if (!igb_check_reset_block(hw))
2394 igb_reset_phy(hw);
2395
2396 if (hw->flash_address)
2397 iounmap(hw->flash_address);
2398 err_sw_init:
2399 igb_clear_interrupt_scheme(adapter);
2400 iounmap(hw->hw_addr);
2401 err_ioremap:
2402 free_netdev(netdev);
2403 err_alloc_etherdev:
2404 pci_release_selected_regions(pdev,
2405 pci_select_bars(pdev, IORESOURCE_MEM));
2406 err_pci_reg:
2407 err_dma:
2408 pci_disable_device(pdev);
2409 return err;
2410 }
2411
2412 #ifdef CONFIG_PCI_IOV
2413 static int igb_disable_sriov(struct pci_dev *pdev)
2414 {
2415 struct net_device *netdev = pci_get_drvdata(pdev);
2416 struct igb_adapter *adapter = netdev_priv(netdev);
2417 struct e1000_hw *hw = &adapter->hw;
2418
2419 /* reclaim resources allocated to VFs */
2420 if (adapter->vf_data) {
2421 /* disable iov and allow time for transactions to clear */
2422 if (pci_vfs_assigned(pdev)) {
2423 dev_warn(&pdev->dev,
2424 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2425 return -EPERM;
2426 } else {
2427 pci_disable_sriov(pdev);
2428 msleep(500);
2429 }
2430
2431 kfree(adapter->vf_data);
2432 adapter->vf_data = NULL;
2433 adapter->vfs_allocated_count = 0;
2434 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2435 wrfl();
2436 msleep(100);
2437 dev_info(&pdev->dev, "IOV Disabled\n");
2438
2439 /* Re-enable DMA Coalescing flag since IOV is turned off */
2440 adapter->flags |= IGB_FLAG_DMAC;
2441 }
2442
2443 return 0;
2444 }
2445
2446 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2447 {
2448 struct net_device *netdev = pci_get_drvdata(pdev);
2449 struct igb_adapter *adapter = netdev_priv(netdev);
2450 int old_vfs = pci_num_vf(pdev);
2451 int err = 0;
2452 int i;
2453
2454 if (!adapter->msix_entries) {
2455 err = -EPERM;
2456 goto out;
2457 }
2458
2459 if (!num_vfs)
2460 goto out;
2461 else if (old_vfs && old_vfs == num_vfs)
2462 goto out;
2463 else if (old_vfs && old_vfs != num_vfs)
2464 err = igb_disable_sriov(pdev);
2465
2466 if (err)
2467 goto out;
2468
2469 if (num_vfs > 7) {
2470 err = -EPERM;
2471 goto out;
2472 }
2473
2474 adapter->vfs_allocated_count = num_vfs;
2475
2476 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2477 sizeof(struct vf_data_storage), GFP_KERNEL);
2478
2479 /* if allocation failed then we do not support SR-IOV */
2480 if (!adapter->vf_data) {
2481 adapter->vfs_allocated_count = 0;
2482 dev_err(&pdev->dev,
2483 "Unable to allocate memory for VF Data Storage\n");
2484 err = -ENOMEM;
2485 goto out;
2486 }
2487
2488 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2489 if (err)
2490 goto err_out;
2491
2492 dev_info(&pdev->dev, "%d VFs allocated\n",
2493 adapter->vfs_allocated_count);
2494 for (i = 0; i < adapter->vfs_allocated_count; i++)
2495 igb_vf_configure(adapter, i);
2496
2497 /* DMA Coalescing is not supported in IOV mode. */
2498 adapter->flags &= ~IGB_FLAG_DMAC;
2499 goto out;
2500
2501 err_out:
2502 kfree(adapter->vf_data);
2503 adapter->vf_data = NULL;
2504 adapter->vfs_allocated_count = 0;
2505 out:
2506 return err;
2507 }
2508
2509 #endif
2510 /**
2511 * igb_remove_i2c - Cleanup I2C interface
2512 * @adapter: pointer to adapter structure
2513 **/
2514 static void igb_remove_i2c(struct igb_adapter *adapter)
2515 {
2516 /* free the adapter bus structure */
2517 i2c_del_adapter(&adapter->i2c_adap);
2518 }
2519
2520 /**
2521 * igb_remove - Device Removal Routine
2522 * @pdev: PCI device information struct
2523 *
2524 * igb_remove is called by the PCI subsystem to alert the driver
2525 * that it should release a PCI device. The could be caused by a
2526 * Hot-Plug event, or because the driver is going to be removed from
2527 * memory.
2528 **/
2529 static void igb_remove(struct pci_dev *pdev)
2530 {
2531 struct net_device *netdev = pci_get_drvdata(pdev);
2532 struct igb_adapter *adapter = netdev_priv(netdev);
2533 struct e1000_hw *hw = &adapter->hw;
2534
2535 pm_runtime_get_noresume(&pdev->dev);
2536 #ifdef CONFIG_IGB_HWMON
2537 igb_sysfs_exit(adapter);
2538 #endif
2539 igb_remove_i2c(adapter);
2540 igb_ptp_stop(adapter);
2541 /* The watchdog timer may be rescheduled, so explicitly
2542 * disable watchdog from being rescheduled.
2543 */
2544 set_bit(__IGB_DOWN, &adapter->state);
2545 del_timer_sync(&adapter->watchdog_timer);
2546 del_timer_sync(&adapter->phy_info_timer);
2547
2548 cancel_work_sync(&adapter->reset_task);
2549 cancel_work_sync(&adapter->watchdog_task);
2550
2551 #ifdef CONFIG_IGB_DCA
2552 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2553 dev_info(&pdev->dev, "DCA disabled\n");
2554 dca_remove_requester(&pdev->dev);
2555 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2556 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2557 }
2558 #endif
2559
2560 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2561 * would have already happened in close and is redundant.
2562 */
2563 igb_release_hw_control(adapter);
2564
2565 unregister_netdev(netdev);
2566
2567 igb_clear_interrupt_scheme(adapter);
2568
2569 #ifdef CONFIG_PCI_IOV
2570 igb_disable_sriov(pdev);
2571 #endif
2572
2573 iounmap(hw->hw_addr);
2574 if (hw->flash_address)
2575 iounmap(hw->flash_address);
2576 pci_release_selected_regions(pdev,
2577 pci_select_bars(pdev, IORESOURCE_MEM));
2578
2579 kfree(adapter->shadow_vfta);
2580 free_netdev(netdev);
2581
2582 pci_disable_pcie_error_reporting(pdev);
2583
2584 pci_disable_device(pdev);
2585 }
2586
2587 /**
2588 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2589 * @adapter: board private structure to initialize
2590 *
2591 * This function initializes the vf specific data storage and then attempts to
2592 * allocate the VFs. The reason for ordering it this way is because it is much
2593 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2594 * the memory for the VFs.
2595 **/
2596 static void igb_probe_vfs(struct igb_adapter *adapter)
2597 {
2598 #ifdef CONFIG_PCI_IOV
2599 struct pci_dev *pdev = adapter->pdev;
2600 struct e1000_hw *hw = &adapter->hw;
2601
2602 /* Virtualization features not supported on i210 family. */
2603 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2604 return;
2605
2606 pci_sriov_set_totalvfs(pdev, 7);
2607 igb_enable_sriov(pdev, max_vfs);
2608
2609 #endif /* CONFIG_PCI_IOV */
2610 }
2611
2612 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2613 {
2614 struct e1000_hw *hw = &adapter->hw;
2615 u32 max_rss_queues;
2616
2617 /* Determine the maximum number of RSS queues supported. */
2618 switch (hw->mac.type) {
2619 case e1000_i211:
2620 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2621 break;
2622 case e1000_82575:
2623 case e1000_i210:
2624 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2625 break;
2626 case e1000_i350:
2627 /* I350 cannot do RSS and SR-IOV at the same time */
2628 if (!!adapter->vfs_allocated_count) {
2629 max_rss_queues = 1;
2630 break;
2631 }
2632 /* fall through */
2633 case e1000_82576:
2634 if (!!adapter->vfs_allocated_count) {
2635 max_rss_queues = 2;
2636 break;
2637 }
2638 /* fall through */
2639 case e1000_82580:
2640 case e1000_i354:
2641 default:
2642 max_rss_queues = IGB_MAX_RX_QUEUES;
2643 break;
2644 }
2645
2646 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2647
2648 /* Determine if we need to pair queues. */
2649 switch (hw->mac.type) {
2650 case e1000_82575:
2651 case e1000_i211:
2652 /* Device supports enough interrupts without queue pairing. */
2653 break;
2654 case e1000_82576:
2655 /* If VFs are going to be allocated with RSS queues then we
2656 * should pair the queues in order to conserve interrupts due
2657 * to limited supply.
2658 */
2659 if ((adapter->rss_queues > 1) &&
2660 (adapter->vfs_allocated_count > 6))
2661 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2662 /* fall through */
2663 case e1000_82580:
2664 case e1000_i350:
2665 case e1000_i354:
2666 case e1000_i210:
2667 default:
2668 /* If rss_queues > half of max_rss_queues, pair the queues in
2669 * order to conserve interrupts due to limited supply.
2670 */
2671 if (adapter->rss_queues > (max_rss_queues / 2))
2672 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2673 break;
2674 }
2675 }
2676
2677 /**
2678 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2679 * @adapter: board private structure to initialize
2680 *
2681 * igb_sw_init initializes the Adapter private data structure.
2682 * Fields are initialized based on PCI device information and
2683 * OS network device settings (MTU size).
2684 **/
2685 static int igb_sw_init(struct igb_adapter *adapter)
2686 {
2687 struct e1000_hw *hw = &adapter->hw;
2688 struct net_device *netdev = adapter->netdev;
2689 struct pci_dev *pdev = adapter->pdev;
2690
2691 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2692
2693 /* set default ring sizes */
2694 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2695 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2696
2697 /* set default ITR values */
2698 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2699 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2700
2701 /* set default work limits */
2702 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2703
2704 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2705 VLAN_HLEN;
2706 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2707
2708 spin_lock_init(&adapter->stats64_lock);
2709 #ifdef CONFIG_PCI_IOV
2710 switch (hw->mac.type) {
2711 case e1000_82576:
2712 case e1000_i350:
2713 if (max_vfs > 7) {
2714 dev_warn(&pdev->dev,
2715 "Maximum of 7 VFs per PF, using max\n");
2716 max_vfs = adapter->vfs_allocated_count = 7;
2717 } else
2718 adapter->vfs_allocated_count = max_vfs;
2719 if (adapter->vfs_allocated_count)
2720 dev_warn(&pdev->dev,
2721 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2722 break;
2723 default:
2724 break;
2725 }
2726 #endif /* CONFIG_PCI_IOV */
2727
2728 igb_init_queue_configuration(adapter);
2729
2730 /* Setup and initialize a copy of the hw vlan table array */
2731 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2732 GFP_ATOMIC);
2733
2734 /* This call may decrease the number of queues */
2735 if (igb_init_interrupt_scheme(adapter, true)) {
2736 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2737 return -ENOMEM;
2738 }
2739
2740 igb_probe_vfs(adapter);
2741
2742 /* Explicitly disable IRQ since the NIC can be in any state. */
2743 igb_irq_disable(adapter);
2744
2745 if (hw->mac.type >= e1000_i350)
2746 adapter->flags &= ~IGB_FLAG_DMAC;
2747
2748 set_bit(__IGB_DOWN, &adapter->state);
2749 return 0;
2750 }
2751
2752 /**
2753 * igb_open - Called when a network interface is made active
2754 * @netdev: network interface device structure
2755 *
2756 * Returns 0 on success, negative value on failure
2757 *
2758 * The open entry point is called when a network interface is made
2759 * active by the system (IFF_UP). At this point all resources needed
2760 * for transmit and receive operations are allocated, the interrupt
2761 * handler is registered with the OS, the watchdog timer is started,
2762 * and the stack is notified that the interface is ready.
2763 **/
2764 static int __igb_open(struct net_device *netdev, bool resuming)
2765 {
2766 struct igb_adapter *adapter = netdev_priv(netdev);
2767 struct e1000_hw *hw = &adapter->hw;
2768 struct pci_dev *pdev = adapter->pdev;
2769 int err;
2770 int i;
2771
2772 /* disallow open during test */
2773 if (test_bit(__IGB_TESTING, &adapter->state)) {
2774 WARN_ON(resuming);
2775 return -EBUSY;
2776 }
2777
2778 if (!resuming)
2779 pm_runtime_get_sync(&pdev->dev);
2780
2781 netif_carrier_off(netdev);
2782
2783 /* allocate transmit descriptors */
2784 err = igb_setup_all_tx_resources(adapter);
2785 if (err)
2786 goto err_setup_tx;
2787
2788 /* allocate receive descriptors */
2789 err = igb_setup_all_rx_resources(adapter);
2790 if (err)
2791 goto err_setup_rx;
2792
2793 igb_power_up_link(adapter);
2794
2795 /* before we allocate an interrupt, we must be ready to handle it.
2796 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2797 * as soon as we call pci_request_irq, so we have to setup our
2798 * clean_rx handler before we do so.
2799 */
2800 igb_configure(adapter);
2801
2802 err = igb_request_irq(adapter);
2803 if (err)
2804 goto err_req_irq;
2805
2806 /* Notify the stack of the actual queue counts. */
2807 err = netif_set_real_num_tx_queues(adapter->netdev,
2808 adapter->num_tx_queues);
2809 if (err)
2810 goto err_set_queues;
2811
2812 err = netif_set_real_num_rx_queues(adapter->netdev,
2813 adapter->num_rx_queues);
2814 if (err)
2815 goto err_set_queues;
2816
2817 /* From here on the code is the same as igb_up() */
2818 clear_bit(__IGB_DOWN, &adapter->state);
2819
2820 for (i = 0; i < adapter->num_q_vectors; i++)
2821 napi_enable(&(adapter->q_vector[i]->napi));
2822
2823 /* Clear any pending interrupts. */
2824 rd32(E1000_ICR);
2825
2826 igb_irq_enable(adapter);
2827
2828 /* notify VFs that reset has been completed */
2829 if (adapter->vfs_allocated_count) {
2830 u32 reg_data = rd32(E1000_CTRL_EXT);
2831 reg_data |= E1000_CTRL_EXT_PFRSTD;
2832 wr32(E1000_CTRL_EXT, reg_data);
2833 }
2834
2835 netif_tx_start_all_queues(netdev);
2836
2837 if (!resuming)
2838 pm_runtime_put(&pdev->dev);
2839
2840 /* start the watchdog. */
2841 hw->mac.get_link_status = 1;
2842 schedule_work(&adapter->watchdog_task);
2843
2844 return 0;
2845
2846 err_set_queues:
2847 igb_free_irq(adapter);
2848 err_req_irq:
2849 igb_release_hw_control(adapter);
2850 igb_power_down_link(adapter);
2851 igb_free_all_rx_resources(adapter);
2852 err_setup_rx:
2853 igb_free_all_tx_resources(adapter);
2854 err_setup_tx:
2855 igb_reset(adapter);
2856 if (!resuming)
2857 pm_runtime_put(&pdev->dev);
2858
2859 return err;
2860 }
2861
2862 static int igb_open(struct net_device *netdev)
2863 {
2864 return __igb_open(netdev, false);
2865 }
2866
2867 /**
2868 * igb_close - Disables a network interface
2869 * @netdev: network interface device structure
2870 *
2871 * Returns 0, this is not allowed to fail
2872 *
2873 * The close entry point is called when an interface is de-activated
2874 * by the OS. The hardware is still under the driver's control, but
2875 * needs to be disabled. A global MAC reset is issued to stop the
2876 * hardware, and all transmit and receive resources are freed.
2877 **/
2878 static int __igb_close(struct net_device *netdev, bool suspending)
2879 {
2880 struct igb_adapter *adapter = netdev_priv(netdev);
2881 struct pci_dev *pdev = adapter->pdev;
2882
2883 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2884
2885 if (!suspending)
2886 pm_runtime_get_sync(&pdev->dev);
2887
2888 igb_down(adapter);
2889 igb_free_irq(adapter);
2890
2891 igb_free_all_tx_resources(adapter);
2892 igb_free_all_rx_resources(adapter);
2893
2894 if (!suspending)
2895 pm_runtime_put_sync(&pdev->dev);
2896 return 0;
2897 }
2898
2899 static int igb_close(struct net_device *netdev)
2900 {
2901 return __igb_close(netdev, false);
2902 }
2903
2904 /**
2905 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2906 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2907 *
2908 * Return 0 on success, negative on failure
2909 **/
2910 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2911 {
2912 struct device *dev = tx_ring->dev;
2913 int size;
2914
2915 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2916
2917 tx_ring->tx_buffer_info = vzalloc(size);
2918 if (!tx_ring->tx_buffer_info)
2919 goto err;
2920
2921 /* round up to nearest 4K */
2922 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2923 tx_ring->size = ALIGN(tx_ring->size, 4096);
2924
2925 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2926 &tx_ring->dma, GFP_KERNEL);
2927 if (!tx_ring->desc)
2928 goto err;
2929
2930 tx_ring->next_to_use = 0;
2931 tx_ring->next_to_clean = 0;
2932
2933 return 0;
2934
2935 err:
2936 vfree(tx_ring->tx_buffer_info);
2937 tx_ring->tx_buffer_info = NULL;
2938 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2939 return -ENOMEM;
2940 }
2941
2942 /**
2943 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2944 * (Descriptors) for all queues
2945 * @adapter: board private structure
2946 *
2947 * Return 0 on success, negative on failure
2948 **/
2949 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2950 {
2951 struct pci_dev *pdev = adapter->pdev;
2952 int i, err = 0;
2953
2954 for (i = 0; i < adapter->num_tx_queues; i++) {
2955 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2956 if (err) {
2957 dev_err(&pdev->dev,
2958 "Allocation for Tx Queue %u failed\n", i);
2959 for (i--; i >= 0; i--)
2960 igb_free_tx_resources(adapter->tx_ring[i]);
2961 break;
2962 }
2963 }
2964
2965 return err;
2966 }
2967
2968 /**
2969 * igb_setup_tctl - configure the transmit control registers
2970 * @adapter: Board private structure
2971 **/
2972 void igb_setup_tctl(struct igb_adapter *adapter)
2973 {
2974 struct e1000_hw *hw = &adapter->hw;
2975 u32 tctl;
2976
2977 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2978 wr32(E1000_TXDCTL(0), 0);
2979
2980 /* Program the Transmit Control Register */
2981 tctl = rd32(E1000_TCTL);
2982 tctl &= ~E1000_TCTL_CT;
2983 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2984 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2985
2986 igb_config_collision_dist(hw);
2987
2988 /* Enable transmits */
2989 tctl |= E1000_TCTL_EN;
2990
2991 wr32(E1000_TCTL, tctl);
2992 }
2993
2994 /**
2995 * igb_configure_tx_ring - Configure transmit ring after Reset
2996 * @adapter: board private structure
2997 * @ring: tx ring to configure
2998 *
2999 * Configure a transmit ring after a reset.
3000 **/
3001 void igb_configure_tx_ring(struct igb_adapter *adapter,
3002 struct igb_ring *ring)
3003 {
3004 struct e1000_hw *hw = &adapter->hw;
3005 u32 txdctl = 0;
3006 u64 tdba = ring->dma;
3007 int reg_idx = ring->reg_idx;
3008
3009 /* disable the queue */
3010 wr32(E1000_TXDCTL(reg_idx), 0);
3011 wrfl();
3012 mdelay(10);
3013
3014 wr32(E1000_TDLEN(reg_idx),
3015 ring->count * sizeof(union e1000_adv_tx_desc));
3016 wr32(E1000_TDBAL(reg_idx),
3017 tdba & 0x00000000ffffffffULL);
3018 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3019
3020 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3021 wr32(E1000_TDH(reg_idx), 0);
3022 writel(0, ring->tail);
3023
3024 txdctl |= IGB_TX_PTHRESH;
3025 txdctl |= IGB_TX_HTHRESH << 8;
3026 txdctl |= IGB_TX_WTHRESH << 16;
3027
3028 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3029 wr32(E1000_TXDCTL(reg_idx), txdctl);
3030 }
3031
3032 /**
3033 * igb_configure_tx - Configure transmit Unit after Reset
3034 * @adapter: board private structure
3035 *
3036 * Configure the Tx unit of the MAC after a reset.
3037 **/
3038 static void igb_configure_tx(struct igb_adapter *adapter)
3039 {
3040 int i;
3041
3042 for (i = 0; i < adapter->num_tx_queues; i++)
3043 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3044 }
3045
3046 /**
3047 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3048 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3049 *
3050 * Returns 0 on success, negative on failure
3051 **/
3052 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3053 {
3054 struct device *dev = rx_ring->dev;
3055 int size;
3056
3057 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3058
3059 rx_ring->rx_buffer_info = vzalloc(size);
3060 if (!rx_ring->rx_buffer_info)
3061 goto err;
3062
3063 /* Round up to nearest 4K */
3064 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3065 rx_ring->size = ALIGN(rx_ring->size, 4096);
3066
3067 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3068 &rx_ring->dma, GFP_KERNEL);
3069 if (!rx_ring->desc)
3070 goto err;
3071
3072 rx_ring->next_to_alloc = 0;
3073 rx_ring->next_to_clean = 0;
3074 rx_ring->next_to_use = 0;
3075
3076 return 0;
3077
3078 err:
3079 vfree(rx_ring->rx_buffer_info);
3080 rx_ring->rx_buffer_info = NULL;
3081 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3082 return -ENOMEM;
3083 }
3084
3085 /**
3086 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3087 * (Descriptors) for all queues
3088 * @adapter: board private structure
3089 *
3090 * Return 0 on success, negative on failure
3091 **/
3092 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3093 {
3094 struct pci_dev *pdev = adapter->pdev;
3095 int i, err = 0;
3096
3097 for (i = 0; i < adapter->num_rx_queues; i++) {
3098 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3099 if (err) {
3100 dev_err(&pdev->dev,
3101 "Allocation for Rx Queue %u failed\n", i);
3102 for (i--; i >= 0; i--)
3103 igb_free_rx_resources(adapter->rx_ring[i]);
3104 break;
3105 }
3106 }
3107
3108 return err;
3109 }
3110
3111 /**
3112 * igb_setup_mrqc - configure the multiple receive queue control registers
3113 * @adapter: Board private structure
3114 **/
3115 static void igb_setup_mrqc(struct igb_adapter *adapter)
3116 {
3117 struct e1000_hw *hw = &adapter->hw;
3118 u32 mrqc, rxcsum;
3119 u32 j, num_rx_queues, shift = 0;
3120 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3121 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3122 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3123 0xFA01ACBE };
3124
3125 /* Fill out hash function seeds */
3126 for (j = 0; j < 10; j++)
3127 wr32(E1000_RSSRK(j), rsskey[j]);
3128
3129 num_rx_queues = adapter->rss_queues;
3130
3131 switch (hw->mac.type) {
3132 case e1000_82575:
3133 shift = 6;
3134 break;
3135 case e1000_82576:
3136 /* 82576 supports 2 RSS queues for SR-IOV */
3137 if (adapter->vfs_allocated_count) {
3138 shift = 3;
3139 num_rx_queues = 2;
3140 }
3141 break;
3142 default:
3143 break;
3144 }
3145
3146 /* Populate the indirection table 4 entries at a time. To do this
3147 * we are generating the results for n and n+2 and then interleaving
3148 * those with the results with n+1 and n+3.
3149 */
3150 for (j = 0; j < 32; j++) {
3151 /* first pass generates n and n+2 */
3152 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3153 u32 reta = (base & 0x07800780) >> (7 - shift);
3154
3155 /* second pass generates n+1 and n+3 */
3156 base += 0x00010001 * num_rx_queues;
3157 reta |= (base & 0x07800780) << (1 + shift);
3158
3159 wr32(E1000_RETA(j), reta);
3160 }
3161
3162 /* Disable raw packet checksumming so that RSS hash is placed in
3163 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3164 * offloads as they are enabled by default
3165 */
3166 rxcsum = rd32(E1000_RXCSUM);
3167 rxcsum |= E1000_RXCSUM_PCSD;
3168
3169 if (adapter->hw.mac.type >= e1000_82576)
3170 /* Enable Receive Checksum Offload for SCTP */
3171 rxcsum |= E1000_RXCSUM_CRCOFL;
3172
3173 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3174 wr32(E1000_RXCSUM, rxcsum);
3175
3176 /* Generate RSS hash based on packet types, TCP/UDP
3177 * port numbers and/or IPv4/v6 src and dst addresses
3178 */
3179 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3180 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3181 E1000_MRQC_RSS_FIELD_IPV6 |
3182 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3183 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3184
3185 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3186 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3187 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3188 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3189
3190 /* If VMDq is enabled then we set the appropriate mode for that, else
3191 * we default to RSS so that an RSS hash is calculated per packet even
3192 * if we are only using one queue
3193 */
3194 if (adapter->vfs_allocated_count) {
3195 if (hw->mac.type > e1000_82575) {
3196 /* Set the default pool for the PF's first queue */
3197 u32 vtctl = rd32(E1000_VT_CTL);
3198 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3199 E1000_VT_CTL_DISABLE_DEF_POOL);
3200 vtctl |= adapter->vfs_allocated_count <<
3201 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3202 wr32(E1000_VT_CTL, vtctl);
3203 }
3204 if (adapter->rss_queues > 1)
3205 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3206 else
3207 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3208 } else {
3209 if (hw->mac.type != e1000_i211)
3210 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3211 }
3212 igb_vmm_control(adapter);
3213
3214 wr32(E1000_MRQC, mrqc);
3215 }
3216
3217 /**
3218 * igb_setup_rctl - configure the receive control registers
3219 * @adapter: Board private structure
3220 **/
3221 void igb_setup_rctl(struct igb_adapter *adapter)
3222 {
3223 struct e1000_hw *hw = &adapter->hw;
3224 u32 rctl;
3225
3226 rctl = rd32(E1000_RCTL);
3227
3228 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3229 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3230
3231 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3232 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3233
3234 /* enable stripping of CRC. It's unlikely this will break BMC
3235 * redirection as it did with e1000. Newer features require
3236 * that the HW strips the CRC.
3237 */
3238 rctl |= E1000_RCTL_SECRC;
3239
3240 /* disable store bad packets and clear size bits. */
3241 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3242
3243 /* enable LPE to prevent packets larger than max_frame_size */
3244 rctl |= E1000_RCTL_LPE;
3245
3246 /* disable queue 0 to prevent tail write w/o re-config */
3247 wr32(E1000_RXDCTL(0), 0);
3248
3249 /* Attention!!! For SR-IOV PF driver operations you must enable
3250 * queue drop for all VF and PF queues to prevent head of line blocking
3251 * if an un-trusted VF does not provide descriptors to hardware.
3252 */
3253 if (adapter->vfs_allocated_count) {
3254 /* set all queue drop enable bits */
3255 wr32(E1000_QDE, ALL_QUEUES);
3256 }
3257
3258 /* This is useful for sniffing bad packets. */
3259 if (adapter->netdev->features & NETIF_F_RXALL) {
3260 /* UPE and MPE will be handled by normal PROMISC logic
3261 * in e1000e_set_rx_mode
3262 */
3263 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3264 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3265 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3266
3267 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3268 E1000_RCTL_DPF | /* Allow filtered pause */
3269 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3270 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3271 * and that breaks VLANs.
3272 */
3273 }
3274
3275 wr32(E1000_RCTL, rctl);
3276 }
3277
3278 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3279 int vfn)
3280 {
3281 struct e1000_hw *hw = &adapter->hw;
3282 u32 vmolr;
3283
3284 /* if it isn't the PF check to see if VFs are enabled and
3285 * increase the size to support vlan tags
3286 */
3287 if (vfn < adapter->vfs_allocated_count &&
3288 adapter->vf_data[vfn].vlans_enabled)
3289 size += VLAN_TAG_SIZE;
3290
3291 vmolr = rd32(E1000_VMOLR(vfn));
3292 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3293 vmolr |= size | E1000_VMOLR_LPE;
3294 wr32(E1000_VMOLR(vfn), vmolr);
3295
3296 return 0;
3297 }
3298
3299 /**
3300 * igb_rlpml_set - set maximum receive packet size
3301 * @adapter: board private structure
3302 *
3303 * Configure maximum receivable packet size.
3304 **/
3305 static void igb_rlpml_set(struct igb_adapter *adapter)
3306 {
3307 u32 max_frame_size = adapter->max_frame_size;
3308 struct e1000_hw *hw = &adapter->hw;
3309 u16 pf_id = adapter->vfs_allocated_count;
3310
3311 if (pf_id) {
3312 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3313 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3314 * to our max jumbo frame size, in case we need to enable
3315 * jumbo frames on one of the rings later.
3316 * This will not pass over-length frames into the default
3317 * queue because it's gated by the VMOLR.RLPML.
3318 */
3319 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3320 }
3321
3322 wr32(E1000_RLPML, max_frame_size);
3323 }
3324
3325 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3326 int vfn, bool aupe)
3327 {
3328 struct e1000_hw *hw = &adapter->hw;
3329 u32 vmolr;
3330
3331 /* This register exists only on 82576 and newer so if we are older then
3332 * we should exit and do nothing
3333 */
3334 if (hw->mac.type < e1000_82576)
3335 return;
3336
3337 vmolr = rd32(E1000_VMOLR(vfn));
3338 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3339 if (aupe)
3340 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3341 else
3342 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3343
3344 /* clear all bits that might not be set */
3345 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3346
3347 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3348 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3349 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3350 * multicast packets
3351 */
3352 if (vfn <= adapter->vfs_allocated_count)
3353 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3354
3355 wr32(E1000_VMOLR(vfn), vmolr);
3356 }
3357
3358 /**
3359 * igb_configure_rx_ring - Configure a receive ring after Reset
3360 * @adapter: board private structure
3361 * @ring: receive ring to be configured
3362 *
3363 * Configure the Rx unit of the MAC after a reset.
3364 **/
3365 void igb_configure_rx_ring(struct igb_adapter *adapter,
3366 struct igb_ring *ring)
3367 {
3368 struct e1000_hw *hw = &adapter->hw;
3369 u64 rdba = ring->dma;
3370 int reg_idx = ring->reg_idx;
3371 u32 srrctl = 0, rxdctl = 0;
3372
3373 /* disable the queue */
3374 wr32(E1000_RXDCTL(reg_idx), 0);
3375
3376 /* Set DMA base address registers */
3377 wr32(E1000_RDBAL(reg_idx),
3378 rdba & 0x00000000ffffffffULL);
3379 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3380 wr32(E1000_RDLEN(reg_idx),
3381 ring->count * sizeof(union e1000_adv_rx_desc));
3382
3383 /* initialize head and tail */
3384 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3385 wr32(E1000_RDH(reg_idx), 0);
3386 writel(0, ring->tail);
3387
3388 /* set descriptor configuration */
3389 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3390 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3391 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3392 if (hw->mac.type >= e1000_82580)
3393 srrctl |= E1000_SRRCTL_TIMESTAMP;
3394 /* Only set Drop Enable if we are supporting multiple queues */
3395 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3396 srrctl |= E1000_SRRCTL_DROP_EN;
3397
3398 wr32(E1000_SRRCTL(reg_idx), srrctl);
3399
3400 /* set filtering for VMDQ pools */
3401 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3402
3403 rxdctl |= IGB_RX_PTHRESH;
3404 rxdctl |= IGB_RX_HTHRESH << 8;
3405 rxdctl |= IGB_RX_WTHRESH << 16;
3406
3407 /* enable receive descriptor fetching */
3408 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3409 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3410 }
3411
3412 /**
3413 * igb_configure_rx - Configure receive Unit after Reset
3414 * @adapter: board private structure
3415 *
3416 * Configure the Rx unit of the MAC after a reset.
3417 **/
3418 static void igb_configure_rx(struct igb_adapter *adapter)
3419 {
3420 int i;
3421
3422 /* set UTA to appropriate mode */
3423 igb_set_uta(adapter);
3424
3425 /* set the correct pool for the PF default MAC address in entry 0 */
3426 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3427 adapter->vfs_allocated_count);
3428
3429 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3430 * the Base and Length of the Rx Descriptor Ring
3431 */
3432 for (i = 0; i < adapter->num_rx_queues; i++)
3433 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3434 }
3435
3436 /**
3437 * igb_free_tx_resources - Free Tx Resources per Queue
3438 * @tx_ring: Tx descriptor ring for a specific queue
3439 *
3440 * Free all transmit software resources
3441 **/
3442 void igb_free_tx_resources(struct igb_ring *tx_ring)
3443 {
3444 igb_clean_tx_ring(tx_ring);
3445
3446 vfree(tx_ring->tx_buffer_info);
3447 tx_ring->tx_buffer_info = NULL;
3448
3449 /* if not set, then don't free */
3450 if (!tx_ring->desc)
3451 return;
3452
3453 dma_free_coherent(tx_ring->dev, tx_ring->size,
3454 tx_ring->desc, tx_ring->dma);
3455
3456 tx_ring->desc = NULL;
3457 }
3458
3459 /**
3460 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3461 * @adapter: board private structure
3462 *
3463 * Free all transmit software resources
3464 **/
3465 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3466 {
3467 int i;
3468
3469 for (i = 0; i < adapter->num_tx_queues; i++)
3470 igb_free_tx_resources(adapter->tx_ring[i]);
3471 }
3472
3473 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3474 struct igb_tx_buffer *tx_buffer)
3475 {
3476 if (tx_buffer->skb) {
3477 dev_kfree_skb_any(tx_buffer->skb);
3478 if (dma_unmap_len(tx_buffer, len))
3479 dma_unmap_single(ring->dev,
3480 dma_unmap_addr(tx_buffer, dma),
3481 dma_unmap_len(tx_buffer, len),
3482 DMA_TO_DEVICE);
3483 } else if (dma_unmap_len(tx_buffer, len)) {
3484 dma_unmap_page(ring->dev,
3485 dma_unmap_addr(tx_buffer, dma),
3486 dma_unmap_len(tx_buffer, len),
3487 DMA_TO_DEVICE);
3488 }
3489 tx_buffer->next_to_watch = NULL;
3490 tx_buffer->skb = NULL;
3491 dma_unmap_len_set(tx_buffer, len, 0);
3492 /* buffer_info must be completely set up in the transmit path */
3493 }
3494
3495 /**
3496 * igb_clean_tx_ring - Free Tx Buffers
3497 * @tx_ring: ring to be cleaned
3498 **/
3499 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3500 {
3501 struct igb_tx_buffer *buffer_info;
3502 unsigned long size;
3503 u16 i;
3504
3505 if (!tx_ring->tx_buffer_info)
3506 return;
3507 /* Free all the Tx ring sk_buffs */
3508
3509 for (i = 0; i < tx_ring->count; i++) {
3510 buffer_info = &tx_ring->tx_buffer_info[i];
3511 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3512 }
3513
3514 netdev_tx_reset_queue(txring_txq(tx_ring));
3515
3516 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3517 memset(tx_ring->tx_buffer_info, 0, size);
3518
3519 /* Zero out the descriptor ring */
3520 memset(tx_ring->desc, 0, tx_ring->size);
3521
3522 tx_ring->next_to_use = 0;
3523 tx_ring->next_to_clean = 0;
3524 }
3525
3526 /**
3527 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3528 * @adapter: board private structure
3529 **/
3530 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3531 {
3532 int i;
3533
3534 for (i = 0; i < adapter->num_tx_queues; i++)
3535 igb_clean_tx_ring(adapter->tx_ring[i]);
3536 }
3537
3538 /**
3539 * igb_free_rx_resources - Free Rx Resources
3540 * @rx_ring: ring to clean the resources from
3541 *
3542 * Free all receive software resources
3543 **/
3544 void igb_free_rx_resources(struct igb_ring *rx_ring)
3545 {
3546 igb_clean_rx_ring(rx_ring);
3547
3548 vfree(rx_ring->rx_buffer_info);
3549 rx_ring->rx_buffer_info = NULL;
3550
3551 /* if not set, then don't free */
3552 if (!rx_ring->desc)
3553 return;
3554
3555 dma_free_coherent(rx_ring->dev, rx_ring->size,
3556 rx_ring->desc, rx_ring->dma);
3557
3558 rx_ring->desc = NULL;
3559 }
3560
3561 /**
3562 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3563 * @adapter: board private structure
3564 *
3565 * Free all receive software resources
3566 **/
3567 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3568 {
3569 int i;
3570
3571 for (i = 0; i < adapter->num_rx_queues; i++)
3572 igb_free_rx_resources(adapter->rx_ring[i]);
3573 }
3574
3575 /**
3576 * igb_clean_rx_ring - Free Rx Buffers per Queue
3577 * @rx_ring: ring to free buffers from
3578 **/
3579 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3580 {
3581 unsigned long size;
3582 u16 i;
3583
3584 if (rx_ring->skb)
3585 dev_kfree_skb(rx_ring->skb);
3586 rx_ring->skb = NULL;
3587
3588 if (!rx_ring->rx_buffer_info)
3589 return;
3590
3591 /* Free all the Rx ring sk_buffs */
3592 for (i = 0; i < rx_ring->count; i++) {
3593 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3594
3595 if (!buffer_info->page)
3596 continue;
3597
3598 dma_unmap_page(rx_ring->dev,
3599 buffer_info->dma,
3600 PAGE_SIZE,
3601 DMA_FROM_DEVICE);
3602 __free_page(buffer_info->page);
3603
3604 buffer_info->page = NULL;
3605 }
3606
3607 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3608 memset(rx_ring->rx_buffer_info, 0, size);
3609
3610 /* Zero out the descriptor ring */
3611 memset(rx_ring->desc, 0, rx_ring->size);
3612
3613 rx_ring->next_to_alloc = 0;
3614 rx_ring->next_to_clean = 0;
3615 rx_ring->next_to_use = 0;
3616 }
3617
3618 /**
3619 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3620 * @adapter: board private structure
3621 **/
3622 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3623 {
3624 int i;
3625
3626 for (i = 0; i < adapter->num_rx_queues; i++)
3627 igb_clean_rx_ring(adapter->rx_ring[i]);
3628 }
3629
3630 /**
3631 * igb_set_mac - Change the Ethernet Address of the NIC
3632 * @netdev: network interface device structure
3633 * @p: pointer to an address structure
3634 *
3635 * Returns 0 on success, negative on failure
3636 **/
3637 static int igb_set_mac(struct net_device *netdev, void *p)
3638 {
3639 struct igb_adapter *adapter = netdev_priv(netdev);
3640 struct e1000_hw *hw = &adapter->hw;
3641 struct sockaddr *addr = p;
3642
3643 if (!is_valid_ether_addr(addr->sa_data))
3644 return -EADDRNOTAVAIL;
3645
3646 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3647 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3648
3649 /* set the correct pool for the new PF MAC address in entry 0 */
3650 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3651 adapter->vfs_allocated_count);
3652
3653 return 0;
3654 }
3655
3656 /**
3657 * igb_write_mc_addr_list - write multicast addresses to MTA
3658 * @netdev: network interface device structure
3659 *
3660 * Writes multicast address list to the MTA hash table.
3661 * Returns: -ENOMEM on failure
3662 * 0 on no addresses written
3663 * X on writing X addresses to MTA
3664 **/
3665 static int igb_write_mc_addr_list(struct net_device *netdev)
3666 {
3667 struct igb_adapter *adapter = netdev_priv(netdev);
3668 struct e1000_hw *hw = &adapter->hw;
3669 struct netdev_hw_addr *ha;
3670 u8 *mta_list;
3671 int i;
3672
3673 if (netdev_mc_empty(netdev)) {
3674 /* nothing to program, so clear mc list */
3675 igb_update_mc_addr_list(hw, NULL, 0);
3676 igb_restore_vf_multicasts(adapter);
3677 return 0;
3678 }
3679
3680 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3681 if (!mta_list)
3682 return -ENOMEM;
3683
3684 /* The shared function expects a packed array of only addresses. */
3685 i = 0;
3686 netdev_for_each_mc_addr(ha, netdev)
3687 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3688
3689 igb_update_mc_addr_list(hw, mta_list, i);
3690 kfree(mta_list);
3691
3692 return netdev_mc_count(netdev);
3693 }
3694
3695 /**
3696 * igb_write_uc_addr_list - write unicast addresses to RAR table
3697 * @netdev: network interface device structure
3698 *
3699 * Writes unicast address list to the RAR table.
3700 * Returns: -ENOMEM on failure/insufficient address space
3701 * 0 on no addresses written
3702 * X on writing X addresses to the RAR table
3703 **/
3704 static int igb_write_uc_addr_list(struct net_device *netdev)
3705 {
3706 struct igb_adapter *adapter = netdev_priv(netdev);
3707 struct e1000_hw *hw = &adapter->hw;
3708 unsigned int vfn = adapter->vfs_allocated_count;
3709 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3710 int count = 0;
3711
3712 /* return ENOMEM indicating insufficient memory for addresses */
3713 if (netdev_uc_count(netdev) > rar_entries)
3714 return -ENOMEM;
3715
3716 if (!netdev_uc_empty(netdev) && rar_entries) {
3717 struct netdev_hw_addr *ha;
3718
3719 netdev_for_each_uc_addr(ha, netdev) {
3720 if (!rar_entries)
3721 break;
3722 igb_rar_set_qsel(adapter, ha->addr,
3723 rar_entries--,
3724 vfn);
3725 count++;
3726 }
3727 }
3728 /* write the addresses in reverse order to avoid write combining */
3729 for (; rar_entries > 0 ; rar_entries--) {
3730 wr32(E1000_RAH(rar_entries), 0);
3731 wr32(E1000_RAL(rar_entries), 0);
3732 }
3733 wrfl();
3734
3735 return count;
3736 }
3737
3738 /**
3739 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3740 * @netdev: network interface device structure
3741 *
3742 * The set_rx_mode entry point is called whenever the unicast or multicast
3743 * address lists or the network interface flags are updated. This routine is
3744 * responsible for configuring the hardware for proper unicast, multicast,
3745 * promiscuous mode, and all-multi behavior.
3746 **/
3747 static void igb_set_rx_mode(struct net_device *netdev)
3748 {
3749 struct igb_adapter *adapter = netdev_priv(netdev);
3750 struct e1000_hw *hw = &adapter->hw;
3751 unsigned int vfn = adapter->vfs_allocated_count;
3752 u32 rctl, vmolr = 0;
3753 int count;
3754
3755 /* Check for Promiscuous and All Multicast modes */
3756 rctl = rd32(E1000_RCTL);
3757
3758 /* clear the effected bits */
3759 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3760
3761 if (netdev->flags & IFF_PROMISC) {
3762 /* retain VLAN HW filtering if in VT mode */
3763 if (adapter->vfs_allocated_count)
3764 rctl |= E1000_RCTL_VFE;
3765 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3766 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3767 } else {
3768 if (netdev->flags & IFF_ALLMULTI) {
3769 rctl |= E1000_RCTL_MPE;
3770 vmolr |= E1000_VMOLR_MPME;
3771 } else {
3772 /* Write addresses to the MTA, if the attempt fails
3773 * then we should just turn on promiscuous mode so
3774 * that we can at least receive multicast traffic
3775 */
3776 count = igb_write_mc_addr_list(netdev);
3777 if (count < 0) {
3778 rctl |= E1000_RCTL_MPE;
3779 vmolr |= E1000_VMOLR_MPME;
3780 } else if (count) {
3781 vmolr |= E1000_VMOLR_ROMPE;
3782 }
3783 }
3784 /* Write addresses to available RAR registers, if there is not
3785 * sufficient space to store all the addresses then enable
3786 * unicast promiscuous mode
3787 */
3788 count = igb_write_uc_addr_list(netdev);
3789 if (count < 0) {
3790 rctl |= E1000_RCTL_UPE;
3791 vmolr |= E1000_VMOLR_ROPE;
3792 }
3793 rctl |= E1000_RCTL_VFE;
3794 }
3795 wr32(E1000_RCTL, rctl);
3796
3797 /* In order to support SR-IOV and eventually VMDq it is necessary to set
3798 * the VMOLR to enable the appropriate modes. Without this workaround
3799 * we will have issues with VLAN tag stripping not being done for frames
3800 * that are only arriving because we are the default pool
3801 */
3802 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3803 return;
3804
3805 vmolr |= rd32(E1000_VMOLR(vfn)) &
3806 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3807 wr32(E1000_VMOLR(vfn), vmolr);
3808 igb_restore_vf_multicasts(adapter);
3809 }
3810
3811 static void igb_check_wvbr(struct igb_adapter *adapter)
3812 {
3813 struct e1000_hw *hw = &adapter->hw;
3814 u32 wvbr = 0;
3815
3816 switch (hw->mac.type) {
3817 case e1000_82576:
3818 case e1000_i350:
3819 if (!(wvbr = rd32(E1000_WVBR)))
3820 return;
3821 break;
3822 default:
3823 break;
3824 }
3825
3826 adapter->wvbr |= wvbr;
3827 }
3828
3829 #define IGB_STAGGERED_QUEUE_OFFSET 8
3830
3831 static void igb_spoof_check(struct igb_adapter *adapter)
3832 {
3833 int j;
3834
3835 if (!adapter->wvbr)
3836 return;
3837
3838 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3839 if (adapter->wvbr & (1 << j) ||
3840 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3841 dev_warn(&adapter->pdev->dev,
3842 "Spoof event(s) detected on VF %d\n", j);
3843 adapter->wvbr &=
3844 ~((1 << j) |
3845 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3846 }
3847 }
3848 }
3849
3850 /* Need to wait a few seconds after link up to get diagnostic information from
3851 * the phy
3852 */
3853 static void igb_update_phy_info(unsigned long data)
3854 {
3855 struct igb_adapter *adapter = (struct igb_adapter *) data;
3856 igb_get_phy_info(&adapter->hw);
3857 }
3858
3859 /**
3860 * igb_has_link - check shared code for link and determine up/down
3861 * @adapter: pointer to driver private info
3862 **/
3863 bool igb_has_link(struct igb_adapter *adapter)
3864 {
3865 struct e1000_hw *hw = &adapter->hw;
3866 bool link_active = false;
3867
3868 /* get_link_status is set on LSC (link status) interrupt or
3869 * rx sequence error interrupt. get_link_status will stay
3870 * false until the e1000_check_for_link establishes link
3871 * for copper adapters ONLY
3872 */
3873 switch (hw->phy.media_type) {
3874 case e1000_media_type_copper:
3875 if (!hw->mac.get_link_status)
3876 return true;
3877 case e1000_media_type_internal_serdes:
3878 hw->mac.ops.check_for_link(hw);
3879 link_active = !hw->mac.get_link_status;
3880 break;
3881 default:
3882 case e1000_media_type_unknown:
3883 break;
3884 }
3885
3886 return link_active;
3887 }
3888
3889 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3890 {
3891 bool ret = false;
3892 u32 ctrl_ext, thstat;
3893
3894 /* check for thermal sensor event on i350 copper only */
3895 if (hw->mac.type == e1000_i350) {
3896 thstat = rd32(E1000_THSTAT);
3897 ctrl_ext = rd32(E1000_CTRL_EXT);
3898
3899 if ((hw->phy.media_type == e1000_media_type_copper) &&
3900 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
3901 ret = !!(thstat & event);
3902 }
3903
3904 return ret;
3905 }
3906
3907 /**
3908 * igb_watchdog - Timer Call-back
3909 * @data: pointer to adapter cast into an unsigned long
3910 **/
3911 static void igb_watchdog(unsigned long data)
3912 {
3913 struct igb_adapter *adapter = (struct igb_adapter *)data;
3914 /* Do the rest outside of interrupt context */
3915 schedule_work(&adapter->watchdog_task);
3916 }
3917
3918 static void igb_watchdog_task(struct work_struct *work)
3919 {
3920 struct igb_adapter *adapter = container_of(work,
3921 struct igb_adapter,
3922 watchdog_task);
3923 struct e1000_hw *hw = &adapter->hw;
3924 struct e1000_phy_info *phy = &hw->phy;
3925 struct net_device *netdev = adapter->netdev;
3926 u32 link;
3927 int i;
3928
3929 link = igb_has_link(adapter);
3930 if (link) {
3931 /* Cancel scheduled suspend requests. */
3932 pm_runtime_resume(netdev->dev.parent);
3933
3934 if (!netif_carrier_ok(netdev)) {
3935 u32 ctrl;
3936 hw->mac.ops.get_speed_and_duplex(hw,
3937 &adapter->link_speed,
3938 &adapter->link_duplex);
3939
3940 ctrl = rd32(E1000_CTRL);
3941 /* Links status message must follow this format */
3942 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3943 "Duplex, Flow Control: %s\n",
3944 netdev->name,
3945 adapter->link_speed,
3946 adapter->link_duplex == FULL_DUPLEX ?
3947 "Full" : "Half",
3948 (ctrl & E1000_CTRL_TFCE) &&
3949 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3950 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3951 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
3952
3953 /* check if SmartSpeed worked */
3954 igb_check_downshift(hw);
3955 if (phy->speed_downgraded)
3956 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3957
3958 /* check for thermal sensor event */
3959 if (igb_thermal_sensor_event(hw,
3960 E1000_THSTAT_LINK_THROTTLE)) {
3961 netdev_info(netdev, "The network adapter link "
3962 "speed was downshifted because it "
3963 "overheated\n");
3964 }
3965
3966 /* adjust timeout factor according to speed/duplex */
3967 adapter->tx_timeout_factor = 1;
3968 switch (adapter->link_speed) {
3969 case SPEED_10:
3970 adapter->tx_timeout_factor = 14;
3971 break;
3972 case SPEED_100:
3973 /* maybe add some timeout factor ? */
3974 break;
3975 }
3976
3977 netif_carrier_on(netdev);
3978
3979 igb_ping_all_vfs(adapter);
3980 igb_check_vf_rate_limit(adapter);
3981
3982 /* link state has changed, schedule phy info update */
3983 if (!test_bit(__IGB_DOWN, &adapter->state))
3984 mod_timer(&adapter->phy_info_timer,
3985 round_jiffies(jiffies + 2 * HZ));
3986 }
3987 } else {
3988 if (netif_carrier_ok(netdev)) {
3989 adapter->link_speed = 0;
3990 adapter->link_duplex = 0;
3991
3992 /* check for thermal sensor event */
3993 if (igb_thermal_sensor_event(hw,
3994 E1000_THSTAT_PWR_DOWN)) {
3995 netdev_err(netdev, "The network adapter was "
3996 "stopped because it overheated\n");
3997 }
3998
3999 /* Links status message must follow this format */
4000 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4001 netdev->name);
4002 netif_carrier_off(netdev);
4003
4004 igb_ping_all_vfs(adapter);
4005
4006 /* link state has changed, schedule phy info update */
4007 if (!test_bit(__IGB_DOWN, &adapter->state))
4008 mod_timer(&adapter->phy_info_timer,
4009 round_jiffies(jiffies + 2 * HZ));
4010
4011 pm_schedule_suspend(netdev->dev.parent,
4012 MSEC_PER_SEC * 5);
4013 }
4014 }
4015
4016 spin_lock(&adapter->stats64_lock);
4017 igb_update_stats(adapter, &adapter->stats64);
4018 spin_unlock(&adapter->stats64_lock);
4019
4020 for (i = 0; i < adapter->num_tx_queues; i++) {
4021 struct igb_ring *tx_ring = adapter->tx_ring[i];
4022 if (!netif_carrier_ok(netdev)) {
4023 /* We've lost link, so the controller stops DMA,
4024 * but we've got queued Tx work that's never going
4025 * to get done, so reset controller to flush Tx.
4026 * (Do the reset outside of interrupt context).
4027 */
4028 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4029 adapter->tx_timeout_count++;
4030 schedule_work(&adapter->reset_task);
4031 /* return immediately since reset is imminent */
4032 return;
4033 }
4034 }
4035
4036 /* Force detection of hung controller every watchdog period */
4037 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4038 }
4039
4040 /* Cause software interrupt to ensure Rx ring is cleaned */
4041 if (adapter->msix_entries) {
4042 u32 eics = 0;
4043 for (i = 0; i < adapter->num_q_vectors; i++)
4044 eics |= adapter->q_vector[i]->eims_value;
4045 wr32(E1000_EICS, eics);
4046 } else {
4047 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4048 }
4049
4050 igb_spoof_check(adapter);
4051 igb_ptp_rx_hang(adapter);
4052
4053 /* Reset the timer */
4054 if (!test_bit(__IGB_DOWN, &adapter->state))
4055 mod_timer(&adapter->watchdog_timer,
4056 round_jiffies(jiffies + 2 * HZ));
4057 }
4058
4059 enum latency_range {
4060 lowest_latency = 0,
4061 low_latency = 1,
4062 bulk_latency = 2,
4063 latency_invalid = 255
4064 };
4065
4066 /**
4067 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4068 * @q_vector: pointer to q_vector
4069 *
4070 * Stores a new ITR value based on strictly on packet size. This
4071 * algorithm is less sophisticated than that used in igb_update_itr,
4072 * due to the difficulty of synchronizing statistics across multiple
4073 * receive rings. The divisors and thresholds used by this function
4074 * were determined based on theoretical maximum wire speed and testing
4075 * data, in order to minimize response time while increasing bulk
4076 * throughput.
4077 * This functionality is controlled by the InterruptThrottleRate module
4078 * parameter (see igb_param.c)
4079 * NOTE: This function is called only when operating in a multiqueue
4080 * receive environment.
4081 **/
4082 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4083 {
4084 int new_val = q_vector->itr_val;
4085 int avg_wire_size = 0;
4086 struct igb_adapter *adapter = q_vector->adapter;
4087 unsigned int packets;
4088
4089 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4090 * ints/sec - ITR timer value of 120 ticks.
4091 */
4092 if (adapter->link_speed != SPEED_1000) {
4093 new_val = IGB_4K_ITR;
4094 goto set_itr_val;
4095 }
4096
4097 packets = q_vector->rx.total_packets;
4098 if (packets)
4099 avg_wire_size = q_vector->rx.total_bytes / packets;
4100
4101 packets = q_vector->tx.total_packets;
4102 if (packets)
4103 avg_wire_size = max_t(u32, avg_wire_size,
4104 q_vector->tx.total_bytes / packets);
4105
4106 /* if avg_wire_size isn't set no work was done */
4107 if (!avg_wire_size)
4108 goto clear_counts;
4109
4110 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4111 avg_wire_size += 24;
4112
4113 /* Don't starve jumbo frames */
4114 avg_wire_size = min(avg_wire_size, 3000);
4115
4116 /* Give a little boost to mid-size frames */
4117 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4118 new_val = avg_wire_size / 3;
4119 else
4120 new_val = avg_wire_size / 2;
4121
4122 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4123 if (new_val < IGB_20K_ITR &&
4124 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4125 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4126 new_val = IGB_20K_ITR;
4127
4128 set_itr_val:
4129 if (new_val != q_vector->itr_val) {
4130 q_vector->itr_val = new_val;
4131 q_vector->set_itr = 1;
4132 }
4133 clear_counts:
4134 q_vector->rx.total_bytes = 0;
4135 q_vector->rx.total_packets = 0;
4136 q_vector->tx.total_bytes = 0;
4137 q_vector->tx.total_packets = 0;
4138 }
4139
4140 /**
4141 * igb_update_itr - update the dynamic ITR value based on statistics
4142 * @q_vector: pointer to q_vector
4143 * @ring_container: ring info to update the itr for
4144 *
4145 * Stores a new ITR value based on packets and byte
4146 * counts during the last interrupt. The advantage of per interrupt
4147 * computation is faster updates and more accurate ITR for the current
4148 * traffic pattern. Constants in this function were computed
4149 * based on theoretical maximum wire speed and thresholds were set based
4150 * on testing data as well as attempting to minimize response time
4151 * while increasing bulk throughput.
4152 * this functionality is controlled by the InterruptThrottleRate module
4153 * parameter (see igb_param.c)
4154 * NOTE: These calculations are only valid when operating in a single-
4155 * queue environment.
4156 **/
4157 static void igb_update_itr(struct igb_q_vector *q_vector,
4158 struct igb_ring_container *ring_container)
4159 {
4160 unsigned int packets = ring_container->total_packets;
4161 unsigned int bytes = ring_container->total_bytes;
4162 u8 itrval = ring_container->itr;
4163
4164 /* no packets, exit with status unchanged */
4165 if (packets == 0)
4166 return;
4167
4168 switch (itrval) {
4169 case lowest_latency:
4170 /* handle TSO and jumbo frames */
4171 if (bytes/packets > 8000)
4172 itrval = bulk_latency;
4173 else if ((packets < 5) && (bytes > 512))
4174 itrval = low_latency;
4175 break;
4176 case low_latency: /* 50 usec aka 20000 ints/s */
4177 if (bytes > 10000) {
4178 /* this if handles the TSO accounting */
4179 if (bytes/packets > 8000) {
4180 itrval = bulk_latency;
4181 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
4182 itrval = bulk_latency;
4183 } else if ((packets > 35)) {
4184 itrval = lowest_latency;
4185 }
4186 } else if (bytes/packets > 2000) {
4187 itrval = bulk_latency;
4188 } else if (packets <= 2 && bytes < 512) {
4189 itrval = lowest_latency;
4190 }
4191 break;
4192 case bulk_latency: /* 250 usec aka 4000 ints/s */
4193 if (bytes > 25000) {
4194 if (packets > 35)
4195 itrval = low_latency;
4196 } else if (bytes < 1500) {
4197 itrval = low_latency;
4198 }
4199 break;
4200 }
4201
4202 /* clear work counters since we have the values we need */
4203 ring_container->total_bytes = 0;
4204 ring_container->total_packets = 0;
4205
4206 /* write updated itr to ring container */
4207 ring_container->itr = itrval;
4208 }
4209
4210 static void igb_set_itr(struct igb_q_vector *q_vector)
4211 {
4212 struct igb_adapter *adapter = q_vector->adapter;
4213 u32 new_itr = q_vector->itr_val;
4214 u8 current_itr = 0;
4215
4216 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4217 if (adapter->link_speed != SPEED_1000) {
4218 current_itr = 0;
4219 new_itr = IGB_4K_ITR;
4220 goto set_itr_now;
4221 }
4222
4223 igb_update_itr(q_vector, &q_vector->tx);
4224 igb_update_itr(q_vector, &q_vector->rx);
4225
4226 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4227
4228 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4229 if (current_itr == lowest_latency &&
4230 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4231 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4232 current_itr = low_latency;
4233
4234 switch (current_itr) {
4235 /* counts and packets in update_itr are dependent on these numbers */
4236 case lowest_latency:
4237 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4238 break;
4239 case low_latency:
4240 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4241 break;
4242 case bulk_latency:
4243 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4244 break;
4245 default:
4246 break;
4247 }
4248
4249 set_itr_now:
4250 if (new_itr != q_vector->itr_val) {
4251 /* this attempts to bias the interrupt rate towards Bulk
4252 * by adding intermediate steps when interrupt rate is
4253 * increasing
4254 */
4255 new_itr = new_itr > q_vector->itr_val ?
4256 max((new_itr * q_vector->itr_val) /
4257 (new_itr + (q_vector->itr_val >> 2)),
4258 new_itr) : new_itr;
4259 /* Don't write the value here; it resets the adapter's
4260 * internal timer, and causes us to delay far longer than
4261 * we should between interrupts. Instead, we write the ITR
4262 * value at the beginning of the next interrupt so the timing
4263 * ends up being correct.
4264 */
4265 q_vector->itr_val = new_itr;
4266 q_vector->set_itr = 1;
4267 }
4268 }
4269
4270 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4271 u32 type_tucmd, u32 mss_l4len_idx)
4272 {
4273 struct e1000_adv_tx_context_desc *context_desc;
4274 u16 i = tx_ring->next_to_use;
4275
4276 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4277
4278 i++;
4279 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4280
4281 /* set bits to identify this as an advanced context descriptor */
4282 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4283
4284 /* For 82575, context index must be unique per ring. */
4285 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4286 mss_l4len_idx |= tx_ring->reg_idx << 4;
4287
4288 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4289 context_desc->seqnum_seed = 0;
4290 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4291 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4292 }
4293
4294 static int igb_tso(struct igb_ring *tx_ring,
4295 struct igb_tx_buffer *first,
4296 u8 *hdr_len)
4297 {
4298 struct sk_buff *skb = first->skb;
4299 u32 vlan_macip_lens, type_tucmd;
4300 u32 mss_l4len_idx, l4len;
4301
4302 if (skb->ip_summed != CHECKSUM_PARTIAL)
4303 return 0;
4304
4305 if (!skb_is_gso(skb))
4306 return 0;
4307
4308 if (skb_header_cloned(skb)) {
4309 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4310 if (err)
4311 return err;
4312 }
4313
4314 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4315 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4316
4317 if (first->protocol == __constant_htons(ETH_P_IP)) {
4318 struct iphdr *iph = ip_hdr(skb);
4319 iph->tot_len = 0;
4320 iph->check = 0;
4321 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4322 iph->daddr, 0,
4323 IPPROTO_TCP,
4324 0);
4325 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4326 first->tx_flags |= IGB_TX_FLAGS_TSO |
4327 IGB_TX_FLAGS_CSUM |
4328 IGB_TX_FLAGS_IPV4;
4329 } else if (skb_is_gso_v6(skb)) {
4330 ipv6_hdr(skb)->payload_len = 0;
4331 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4332 &ipv6_hdr(skb)->daddr,
4333 0, IPPROTO_TCP, 0);
4334 first->tx_flags |= IGB_TX_FLAGS_TSO |
4335 IGB_TX_FLAGS_CSUM;
4336 }
4337
4338 /* compute header lengths */
4339 l4len = tcp_hdrlen(skb);
4340 *hdr_len = skb_transport_offset(skb) + l4len;
4341
4342 /* update gso size and bytecount with header size */
4343 first->gso_segs = skb_shinfo(skb)->gso_segs;
4344 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4345
4346 /* MSS L4LEN IDX */
4347 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4348 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4349
4350 /* VLAN MACLEN IPLEN */
4351 vlan_macip_lens = skb_network_header_len(skb);
4352 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4353 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4354
4355 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4356
4357 return 1;
4358 }
4359
4360 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4361 {
4362 struct sk_buff *skb = first->skb;
4363 u32 vlan_macip_lens = 0;
4364 u32 mss_l4len_idx = 0;
4365 u32 type_tucmd = 0;
4366
4367 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4368 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4369 return;
4370 } else {
4371 u8 l4_hdr = 0;
4372 switch (first->protocol) {
4373 case __constant_htons(ETH_P_IP):
4374 vlan_macip_lens |= skb_network_header_len(skb);
4375 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4376 l4_hdr = ip_hdr(skb)->protocol;
4377 break;
4378 case __constant_htons(ETH_P_IPV6):
4379 vlan_macip_lens |= skb_network_header_len(skb);
4380 l4_hdr = ipv6_hdr(skb)->nexthdr;
4381 break;
4382 default:
4383 if (unlikely(net_ratelimit())) {
4384 dev_warn(tx_ring->dev,
4385 "partial checksum but proto=%x!\n",
4386 first->protocol);
4387 }
4388 break;
4389 }
4390
4391 switch (l4_hdr) {
4392 case IPPROTO_TCP:
4393 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4394 mss_l4len_idx = tcp_hdrlen(skb) <<
4395 E1000_ADVTXD_L4LEN_SHIFT;
4396 break;
4397 case IPPROTO_SCTP:
4398 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4399 mss_l4len_idx = sizeof(struct sctphdr) <<
4400 E1000_ADVTXD_L4LEN_SHIFT;
4401 break;
4402 case IPPROTO_UDP:
4403 mss_l4len_idx = sizeof(struct udphdr) <<
4404 E1000_ADVTXD_L4LEN_SHIFT;
4405 break;
4406 default:
4407 if (unlikely(net_ratelimit())) {
4408 dev_warn(tx_ring->dev,
4409 "partial checksum but l4 proto=%x!\n",
4410 l4_hdr);
4411 }
4412 break;
4413 }
4414
4415 /* update TX checksum flag */
4416 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4417 }
4418
4419 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4420 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4421
4422 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4423 }
4424
4425 #define IGB_SET_FLAG(_input, _flag, _result) \
4426 ((_flag <= _result) ? \
4427 ((u32)(_input & _flag) * (_result / _flag)) : \
4428 ((u32)(_input & _flag) / (_flag / _result)))
4429
4430 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4431 {
4432 /* set type for advanced descriptor with frame checksum insertion */
4433 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4434 E1000_ADVTXD_DCMD_DEXT |
4435 E1000_ADVTXD_DCMD_IFCS;
4436
4437 /* set HW vlan bit if vlan is present */
4438 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4439 (E1000_ADVTXD_DCMD_VLE));
4440
4441 /* set segmentation bits for TSO */
4442 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4443 (E1000_ADVTXD_DCMD_TSE));
4444
4445 /* set timestamp bit if present */
4446 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4447 (E1000_ADVTXD_MAC_TSTAMP));
4448
4449 /* insert frame checksum */
4450 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4451
4452 return cmd_type;
4453 }
4454
4455 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4456 union e1000_adv_tx_desc *tx_desc,
4457 u32 tx_flags, unsigned int paylen)
4458 {
4459 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4460
4461 /* 82575 requires a unique index per ring */
4462 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4463 olinfo_status |= tx_ring->reg_idx << 4;
4464
4465 /* insert L4 checksum */
4466 olinfo_status |= IGB_SET_FLAG(tx_flags,
4467 IGB_TX_FLAGS_CSUM,
4468 (E1000_TXD_POPTS_TXSM << 8));
4469
4470 /* insert IPv4 checksum */
4471 olinfo_status |= IGB_SET_FLAG(tx_flags,
4472 IGB_TX_FLAGS_IPV4,
4473 (E1000_TXD_POPTS_IXSM << 8));
4474
4475 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4476 }
4477
4478 static void igb_tx_map(struct igb_ring *tx_ring,
4479 struct igb_tx_buffer *first,
4480 const u8 hdr_len)
4481 {
4482 struct sk_buff *skb = first->skb;
4483 struct igb_tx_buffer *tx_buffer;
4484 union e1000_adv_tx_desc *tx_desc;
4485 struct skb_frag_struct *frag;
4486 dma_addr_t dma;
4487 unsigned int data_len, size;
4488 u32 tx_flags = first->tx_flags;
4489 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4490 u16 i = tx_ring->next_to_use;
4491
4492 tx_desc = IGB_TX_DESC(tx_ring, i);
4493
4494 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4495
4496 size = skb_headlen(skb);
4497 data_len = skb->data_len;
4498
4499 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4500
4501 tx_buffer = first;
4502
4503 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4504 if (dma_mapping_error(tx_ring->dev, dma))
4505 goto dma_error;
4506
4507 /* record length, and DMA address */
4508 dma_unmap_len_set(tx_buffer, len, size);
4509 dma_unmap_addr_set(tx_buffer, dma, dma);
4510
4511 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4512
4513 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4514 tx_desc->read.cmd_type_len =
4515 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4516
4517 i++;
4518 tx_desc++;
4519 if (i == tx_ring->count) {
4520 tx_desc = IGB_TX_DESC(tx_ring, 0);
4521 i = 0;
4522 }
4523 tx_desc->read.olinfo_status = 0;
4524
4525 dma += IGB_MAX_DATA_PER_TXD;
4526 size -= IGB_MAX_DATA_PER_TXD;
4527
4528 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4529 }
4530
4531 if (likely(!data_len))
4532 break;
4533
4534 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4535
4536 i++;
4537 tx_desc++;
4538 if (i == tx_ring->count) {
4539 tx_desc = IGB_TX_DESC(tx_ring, 0);
4540 i = 0;
4541 }
4542 tx_desc->read.olinfo_status = 0;
4543
4544 size = skb_frag_size(frag);
4545 data_len -= size;
4546
4547 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4548 size, DMA_TO_DEVICE);
4549
4550 tx_buffer = &tx_ring->tx_buffer_info[i];
4551 }
4552
4553 /* write last descriptor with RS and EOP bits */
4554 cmd_type |= size | IGB_TXD_DCMD;
4555 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4556
4557 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4558
4559 /* set the timestamp */
4560 first->time_stamp = jiffies;
4561
4562 /* Force memory writes to complete before letting h/w know there
4563 * are new descriptors to fetch. (Only applicable for weak-ordered
4564 * memory model archs, such as IA-64).
4565 *
4566 * We also need this memory barrier to make certain all of the
4567 * status bits have been updated before next_to_watch is written.
4568 */
4569 wmb();
4570
4571 /* set next_to_watch value indicating a packet is present */
4572 first->next_to_watch = tx_desc;
4573
4574 i++;
4575 if (i == tx_ring->count)
4576 i = 0;
4577
4578 tx_ring->next_to_use = i;
4579
4580 writel(i, tx_ring->tail);
4581
4582 /* we need this if more than one processor can write to our tail
4583 * at a time, it synchronizes IO on IA64/Altix systems
4584 */
4585 mmiowb();
4586
4587 return;
4588
4589 dma_error:
4590 dev_err(tx_ring->dev, "TX DMA map failed\n");
4591
4592 /* clear dma mappings for failed tx_buffer_info map */
4593 for (;;) {
4594 tx_buffer = &tx_ring->tx_buffer_info[i];
4595 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4596 if (tx_buffer == first)
4597 break;
4598 if (i == 0)
4599 i = tx_ring->count;
4600 i--;
4601 }
4602
4603 tx_ring->next_to_use = i;
4604 }
4605
4606 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4607 {
4608 struct net_device *netdev = tx_ring->netdev;
4609
4610 netif_stop_subqueue(netdev, tx_ring->queue_index);
4611
4612 /* Herbert's original patch had:
4613 * smp_mb__after_netif_stop_queue();
4614 * but since that doesn't exist yet, just open code it.
4615 */
4616 smp_mb();
4617
4618 /* We need to check again in a case another CPU has just
4619 * made room available.
4620 */
4621 if (igb_desc_unused(tx_ring) < size)
4622 return -EBUSY;
4623
4624 /* A reprieve! */
4625 netif_wake_subqueue(netdev, tx_ring->queue_index);
4626
4627 u64_stats_update_begin(&tx_ring->tx_syncp2);
4628 tx_ring->tx_stats.restart_queue2++;
4629 u64_stats_update_end(&tx_ring->tx_syncp2);
4630
4631 return 0;
4632 }
4633
4634 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4635 {
4636 if (igb_desc_unused(tx_ring) >= size)
4637 return 0;
4638 return __igb_maybe_stop_tx(tx_ring, size);
4639 }
4640
4641 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4642 struct igb_ring *tx_ring)
4643 {
4644 struct igb_tx_buffer *first;
4645 int tso;
4646 u32 tx_flags = 0;
4647 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4648 __be16 protocol = vlan_get_protocol(skb);
4649 u8 hdr_len = 0;
4650
4651 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4652 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4653 * + 2 desc gap to keep tail from touching head,
4654 * + 1 desc for context descriptor,
4655 * otherwise try next time
4656 */
4657 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4658 unsigned short f;
4659 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4660 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4661 } else {
4662 count += skb_shinfo(skb)->nr_frags;
4663 }
4664
4665 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4666 /* this is a hard error */
4667 return NETDEV_TX_BUSY;
4668 }
4669
4670 /* record the location of the first descriptor for this packet */
4671 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4672 first->skb = skb;
4673 first->bytecount = skb->len;
4674 first->gso_segs = 1;
4675
4676 skb_tx_timestamp(skb);
4677
4678 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4679 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4680
4681 if (!(adapter->ptp_tx_skb)) {
4682 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4683 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4684
4685 adapter->ptp_tx_skb = skb_get(skb);
4686 adapter->ptp_tx_start = jiffies;
4687 if (adapter->hw.mac.type == e1000_82576)
4688 schedule_work(&adapter->ptp_tx_work);
4689 }
4690 }
4691
4692 if (vlan_tx_tag_present(skb)) {
4693 tx_flags |= IGB_TX_FLAGS_VLAN;
4694 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4695 }
4696
4697 /* record initial flags and protocol */
4698 first->tx_flags = tx_flags;
4699 first->protocol = protocol;
4700
4701 tso = igb_tso(tx_ring, first, &hdr_len);
4702 if (tso < 0)
4703 goto out_drop;
4704 else if (!tso)
4705 igb_tx_csum(tx_ring, first);
4706
4707 igb_tx_map(tx_ring, first, hdr_len);
4708
4709 /* Make sure there is space in the ring for the next send. */
4710 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4711
4712 return NETDEV_TX_OK;
4713
4714 out_drop:
4715 igb_unmap_and_free_tx_resource(tx_ring, first);
4716
4717 return NETDEV_TX_OK;
4718 }
4719
4720 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4721 struct sk_buff *skb)
4722 {
4723 unsigned int r_idx = skb->queue_mapping;
4724
4725 if (r_idx >= adapter->num_tx_queues)
4726 r_idx = r_idx % adapter->num_tx_queues;
4727
4728 return adapter->tx_ring[r_idx];
4729 }
4730
4731 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4732 struct net_device *netdev)
4733 {
4734 struct igb_adapter *adapter = netdev_priv(netdev);
4735
4736 if (test_bit(__IGB_DOWN, &adapter->state)) {
4737 dev_kfree_skb_any(skb);
4738 return NETDEV_TX_OK;
4739 }
4740
4741 if (skb->len <= 0) {
4742 dev_kfree_skb_any(skb);
4743 return NETDEV_TX_OK;
4744 }
4745
4746 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
4747 * in order to meet this minimum size requirement.
4748 */
4749 if (unlikely(skb->len < 17)) {
4750 if (skb_pad(skb, 17 - skb->len))
4751 return NETDEV_TX_OK;
4752 skb->len = 17;
4753 skb_set_tail_pointer(skb, 17);
4754 }
4755
4756 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4757 }
4758
4759 /**
4760 * igb_tx_timeout - Respond to a Tx Hang
4761 * @netdev: network interface device structure
4762 **/
4763 static void igb_tx_timeout(struct net_device *netdev)
4764 {
4765 struct igb_adapter *adapter = netdev_priv(netdev);
4766 struct e1000_hw *hw = &adapter->hw;
4767
4768 /* Do the reset outside of interrupt context */
4769 adapter->tx_timeout_count++;
4770
4771 if (hw->mac.type >= e1000_82580)
4772 hw->dev_spec._82575.global_device_reset = true;
4773
4774 schedule_work(&adapter->reset_task);
4775 wr32(E1000_EICS,
4776 (adapter->eims_enable_mask & ~adapter->eims_other));
4777 }
4778
4779 static void igb_reset_task(struct work_struct *work)
4780 {
4781 struct igb_adapter *adapter;
4782 adapter = container_of(work, struct igb_adapter, reset_task);
4783
4784 igb_dump(adapter);
4785 netdev_err(adapter->netdev, "Reset adapter\n");
4786 igb_reinit_locked(adapter);
4787 }
4788
4789 /**
4790 * igb_get_stats64 - Get System Network Statistics
4791 * @netdev: network interface device structure
4792 * @stats: rtnl_link_stats64 pointer
4793 **/
4794 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4795 struct rtnl_link_stats64 *stats)
4796 {
4797 struct igb_adapter *adapter = netdev_priv(netdev);
4798
4799 spin_lock(&adapter->stats64_lock);
4800 igb_update_stats(adapter, &adapter->stats64);
4801 memcpy(stats, &adapter->stats64, sizeof(*stats));
4802 spin_unlock(&adapter->stats64_lock);
4803
4804 return stats;
4805 }
4806
4807 /**
4808 * igb_change_mtu - Change the Maximum Transfer Unit
4809 * @netdev: network interface device structure
4810 * @new_mtu: new value for maximum frame size
4811 *
4812 * Returns 0 on success, negative on failure
4813 **/
4814 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4815 {
4816 struct igb_adapter *adapter = netdev_priv(netdev);
4817 struct pci_dev *pdev = adapter->pdev;
4818 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4819
4820 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4821 dev_err(&pdev->dev, "Invalid MTU setting\n");
4822 return -EINVAL;
4823 }
4824
4825 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4826 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4827 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4828 return -EINVAL;
4829 }
4830
4831 /* adjust max frame to be at least the size of a standard frame */
4832 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4833 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4834
4835 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4836 msleep(1);
4837
4838 /* igb_down has a dependency on max_frame_size */
4839 adapter->max_frame_size = max_frame;
4840
4841 if (netif_running(netdev))
4842 igb_down(adapter);
4843
4844 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4845 netdev->mtu, new_mtu);
4846 netdev->mtu = new_mtu;
4847
4848 if (netif_running(netdev))
4849 igb_up(adapter);
4850 else
4851 igb_reset(adapter);
4852
4853 clear_bit(__IGB_RESETTING, &adapter->state);
4854
4855 return 0;
4856 }
4857
4858 /**
4859 * igb_update_stats - Update the board statistics counters
4860 * @adapter: board private structure
4861 **/
4862 void igb_update_stats(struct igb_adapter *adapter,
4863 struct rtnl_link_stats64 *net_stats)
4864 {
4865 struct e1000_hw *hw = &adapter->hw;
4866 struct pci_dev *pdev = adapter->pdev;
4867 u32 reg, mpc;
4868 u16 phy_tmp;
4869 int i;
4870 u64 bytes, packets;
4871 unsigned int start;
4872 u64 _bytes, _packets;
4873
4874 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4875
4876 /* Prevent stats update while adapter is being reset, or if the pci
4877 * connection is down.
4878 */
4879 if (adapter->link_speed == 0)
4880 return;
4881 if (pci_channel_offline(pdev))
4882 return;
4883
4884 bytes = 0;
4885 packets = 0;
4886
4887 rcu_read_lock();
4888 for (i = 0; i < adapter->num_rx_queues; i++) {
4889 u32 rqdpc = rd32(E1000_RQDPC(i));
4890 struct igb_ring *ring = adapter->rx_ring[i];
4891
4892 if (rqdpc) {
4893 ring->rx_stats.drops += rqdpc;
4894 net_stats->rx_fifo_errors += rqdpc;
4895 }
4896
4897 do {
4898 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4899 _bytes = ring->rx_stats.bytes;
4900 _packets = ring->rx_stats.packets;
4901 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4902 bytes += _bytes;
4903 packets += _packets;
4904 }
4905
4906 net_stats->rx_bytes = bytes;
4907 net_stats->rx_packets = packets;
4908
4909 bytes = 0;
4910 packets = 0;
4911 for (i = 0; i < adapter->num_tx_queues; i++) {
4912 struct igb_ring *ring = adapter->tx_ring[i];
4913 do {
4914 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4915 _bytes = ring->tx_stats.bytes;
4916 _packets = ring->tx_stats.packets;
4917 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4918 bytes += _bytes;
4919 packets += _packets;
4920 }
4921 net_stats->tx_bytes = bytes;
4922 net_stats->tx_packets = packets;
4923 rcu_read_unlock();
4924
4925 /* read stats registers */
4926 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4927 adapter->stats.gprc += rd32(E1000_GPRC);
4928 adapter->stats.gorc += rd32(E1000_GORCL);
4929 rd32(E1000_GORCH); /* clear GORCL */
4930 adapter->stats.bprc += rd32(E1000_BPRC);
4931 adapter->stats.mprc += rd32(E1000_MPRC);
4932 adapter->stats.roc += rd32(E1000_ROC);
4933
4934 adapter->stats.prc64 += rd32(E1000_PRC64);
4935 adapter->stats.prc127 += rd32(E1000_PRC127);
4936 adapter->stats.prc255 += rd32(E1000_PRC255);
4937 adapter->stats.prc511 += rd32(E1000_PRC511);
4938 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4939 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4940 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4941 adapter->stats.sec += rd32(E1000_SEC);
4942
4943 mpc = rd32(E1000_MPC);
4944 adapter->stats.mpc += mpc;
4945 net_stats->rx_fifo_errors += mpc;
4946 adapter->stats.scc += rd32(E1000_SCC);
4947 adapter->stats.ecol += rd32(E1000_ECOL);
4948 adapter->stats.mcc += rd32(E1000_MCC);
4949 adapter->stats.latecol += rd32(E1000_LATECOL);
4950 adapter->stats.dc += rd32(E1000_DC);
4951 adapter->stats.rlec += rd32(E1000_RLEC);
4952 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4953 adapter->stats.xontxc += rd32(E1000_XONTXC);
4954 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4955 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4956 adapter->stats.fcruc += rd32(E1000_FCRUC);
4957 adapter->stats.gptc += rd32(E1000_GPTC);
4958 adapter->stats.gotc += rd32(E1000_GOTCL);
4959 rd32(E1000_GOTCH); /* clear GOTCL */
4960 adapter->stats.rnbc += rd32(E1000_RNBC);
4961 adapter->stats.ruc += rd32(E1000_RUC);
4962 adapter->stats.rfc += rd32(E1000_RFC);
4963 adapter->stats.rjc += rd32(E1000_RJC);
4964 adapter->stats.tor += rd32(E1000_TORH);
4965 adapter->stats.tot += rd32(E1000_TOTH);
4966 adapter->stats.tpr += rd32(E1000_TPR);
4967
4968 adapter->stats.ptc64 += rd32(E1000_PTC64);
4969 adapter->stats.ptc127 += rd32(E1000_PTC127);
4970 adapter->stats.ptc255 += rd32(E1000_PTC255);
4971 adapter->stats.ptc511 += rd32(E1000_PTC511);
4972 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4973 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4974
4975 adapter->stats.mptc += rd32(E1000_MPTC);
4976 adapter->stats.bptc += rd32(E1000_BPTC);
4977
4978 adapter->stats.tpt += rd32(E1000_TPT);
4979 adapter->stats.colc += rd32(E1000_COLC);
4980
4981 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4982 /* read internal phy specific stats */
4983 reg = rd32(E1000_CTRL_EXT);
4984 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4985 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4986
4987 /* this stat has invalid values on i210/i211 */
4988 if ((hw->mac.type != e1000_i210) &&
4989 (hw->mac.type != e1000_i211))
4990 adapter->stats.tncrs += rd32(E1000_TNCRS);
4991 }
4992
4993 adapter->stats.tsctc += rd32(E1000_TSCTC);
4994 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4995
4996 adapter->stats.iac += rd32(E1000_IAC);
4997 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4998 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4999 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5000 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5001 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5002 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5003 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5004 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5005
5006 /* Fill out the OS statistics structure */
5007 net_stats->multicast = adapter->stats.mprc;
5008 net_stats->collisions = adapter->stats.colc;
5009
5010 /* Rx Errors */
5011
5012 /* RLEC on some newer hardware can be incorrect so build
5013 * our own version based on RUC and ROC
5014 */
5015 net_stats->rx_errors = adapter->stats.rxerrc +
5016 adapter->stats.crcerrs + adapter->stats.algnerrc +
5017 adapter->stats.ruc + adapter->stats.roc +
5018 adapter->stats.cexterr;
5019 net_stats->rx_length_errors = adapter->stats.ruc +
5020 adapter->stats.roc;
5021 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5022 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5023 net_stats->rx_missed_errors = adapter->stats.mpc;
5024
5025 /* Tx Errors */
5026 net_stats->tx_errors = adapter->stats.ecol +
5027 adapter->stats.latecol;
5028 net_stats->tx_aborted_errors = adapter->stats.ecol;
5029 net_stats->tx_window_errors = adapter->stats.latecol;
5030 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5031
5032 /* Tx Dropped needs to be maintained elsewhere */
5033
5034 /* Phy Stats */
5035 if (hw->phy.media_type == e1000_media_type_copper) {
5036 if ((adapter->link_speed == SPEED_1000) &&
5037 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
5038 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5039 adapter->phy_stats.idle_errors += phy_tmp;
5040 }
5041 }
5042
5043 /* Management Stats */
5044 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5045 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5046 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5047
5048 /* OS2BMC Stats */
5049 reg = rd32(E1000_MANC);
5050 if (reg & E1000_MANC_EN_BMC2OS) {
5051 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5052 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5053 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5054 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5055 }
5056 }
5057
5058 static irqreturn_t igb_msix_other(int irq, void *data)
5059 {
5060 struct igb_adapter *adapter = data;
5061 struct e1000_hw *hw = &adapter->hw;
5062 u32 icr = rd32(E1000_ICR);
5063 /* reading ICR causes bit 31 of EICR to be cleared */
5064
5065 if (icr & E1000_ICR_DRSTA)
5066 schedule_work(&adapter->reset_task);
5067
5068 if (icr & E1000_ICR_DOUTSYNC) {
5069 /* HW is reporting DMA is out of sync */
5070 adapter->stats.doosync++;
5071 /* The DMA Out of Sync is also indication of a spoof event
5072 * in IOV mode. Check the Wrong VM Behavior register to
5073 * see if it is really a spoof event.
5074 */
5075 igb_check_wvbr(adapter);
5076 }
5077
5078 /* Check for a mailbox event */
5079 if (icr & E1000_ICR_VMMB)
5080 igb_msg_task(adapter);
5081
5082 if (icr & E1000_ICR_LSC) {
5083 hw->mac.get_link_status = 1;
5084 /* guard against interrupt when we're going down */
5085 if (!test_bit(__IGB_DOWN, &adapter->state))
5086 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5087 }
5088
5089 if (icr & E1000_ICR_TS) {
5090 u32 tsicr = rd32(E1000_TSICR);
5091
5092 if (tsicr & E1000_TSICR_TXTS) {
5093 /* acknowledge the interrupt */
5094 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5095 /* retrieve hardware timestamp */
5096 schedule_work(&adapter->ptp_tx_work);
5097 }
5098 }
5099
5100 wr32(E1000_EIMS, adapter->eims_other);
5101
5102 return IRQ_HANDLED;
5103 }
5104
5105 static void igb_write_itr(struct igb_q_vector *q_vector)
5106 {
5107 struct igb_adapter *adapter = q_vector->adapter;
5108 u32 itr_val = q_vector->itr_val & 0x7FFC;
5109
5110 if (!q_vector->set_itr)
5111 return;
5112
5113 if (!itr_val)
5114 itr_val = 0x4;
5115
5116 if (adapter->hw.mac.type == e1000_82575)
5117 itr_val |= itr_val << 16;
5118 else
5119 itr_val |= E1000_EITR_CNT_IGNR;
5120
5121 writel(itr_val, q_vector->itr_register);
5122 q_vector->set_itr = 0;
5123 }
5124
5125 static irqreturn_t igb_msix_ring(int irq, void *data)
5126 {
5127 struct igb_q_vector *q_vector = data;
5128
5129 /* Write the ITR value calculated from the previous interrupt. */
5130 igb_write_itr(q_vector);
5131
5132 napi_schedule(&q_vector->napi);
5133
5134 return IRQ_HANDLED;
5135 }
5136
5137 #ifdef CONFIG_IGB_DCA
5138 static void igb_update_tx_dca(struct igb_adapter *adapter,
5139 struct igb_ring *tx_ring,
5140 int cpu)
5141 {
5142 struct e1000_hw *hw = &adapter->hw;
5143 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5144
5145 if (hw->mac.type != e1000_82575)
5146 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5147
5148 /* We can enable relaxed ordering for reads, but not writes when
5149 * DCA is enabled. This is due to a known issue in some chipsets
5150 * which will cause the DCA tag to be cleared.
5151 */
5152 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5153 E1000_DCA_TXCTRL_DATA_RRO_EN |
5154 E1000_DCA_TXCTRL_DESC_DCA_EN;
5155
5156 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5157 }
5158
5159 static void igb_update_rx_dca(struct igb_adapter *adapter,
5160 struct igb_ring *rx_ring,
5161 int cpu)
5162 {
5163 struct e1000_hw *hw = &adapter->hw;
5164 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5165
5166 if (hw->mac.type != e1000_82575)
5167 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5168
5169 /* We can enable relaxed ordering for reads, but not writes when
5170 * DCA is enabled. This is due to a known issue in some chipsets
5171 * which will cause the DCA tag to be cleared.
5172 */
5173 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5174 E1000_DCA_RXCTRL_DESC_DCA_EN;
5175
5176 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5177 }
5178
5179 static void igb_update_dca(struct igb_q_vector *q_vector)
5180 {
5181 struct igb_adapter *adapter = q_vector->adapter;
5182 int cpu = get_cpu();
5183
5184 if (q_vector->cpu == cpu)
5185 goto out_no_update;
5186
5187 if (q_vector->tx.ring)
5188 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5189
5190 if (q_vector->rx.ring)
5191 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5192
5193 q_vector->cpu = cpu;
5194 out_no_update:
5195 put_cpu();
5196 }
5197
5198 static void igb_setup_dca(struct igb_adapter *adapter)
5199 {
5200 struct e1000_hw *hw = &adapter->hw;
5201 int i;
5202
5203 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5204 return;
5205
5206 /* Always use CB2 mode, difference is masked in the CB driver. */
5207 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5208
5209 for (i = 0; i < adapter->num_q_vectors; i++) {
5210 adapter->q_vector[i]->cpu = -1;
5211 igb_update_dca(adapter->q_vector[i]);
5212 }
5213 }
5214
5215 static int __igb_notify_dca(struct device *dev, void *data)
5216 {
5217 struct net_device *netdev = dev_get_drvdata(dev);
5218 struct igb_adapter *adapter = netdev_priv(netdev);
5219 struct pci_dev *pdev = adapter->pdev;
5220 struct e1000_hw *hw = &adapter->hw;
5221 unsigned long event = *(unsigned long *)data;
5222
5223 switch (event) {
5224 case DCA_PROVIDER_ADD:
5225 /* if already enabled, don't do it again */
5226 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5227 break;
5228 if (dca_add_requester(dev) == 0) {
5229 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5230 dev_info(&pdev->dev, "DCA enabled\n");
5231 igb_setup_dca(adapter);
5232 break;
5233 }
5234 /* Fall Through since DCA is disabled. */
5235 case DCA_PROVIDER_REMOVE:
5236 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5237 /* without this a class_device is left
5238 * hanging around in the sysfs model
5239 */
5240 dca_remove_requester(dev);
5241 dev_info(&pdev->dev, "DCA disabled\n");
5242 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5243 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5244 }
5245 break;
5246 }
5247
5248 return 0;
5249 }
5250
5251 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5252 void *p)
5253 {
5254 int ret_val;
5255
5256 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5257 __igb_notify_dca);
5258
5259 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5260 }
5261 #endif /* CONFIG_IGB_DCA */
5262
5263 #ifdef CONFIG_PCI_IOV
5264 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5265 {
5266 unsigned char mac_addr[ETH_ALEN];
5267
5268 eth_zero_addr(mac_addr);
5269 igb_set_vf_mac(adapter, vf, mac_addr);
5270
5271 /* By default spoof check is enabled for all VFs */
5272 adapter->vf_data[vf].spoofchk_enabled = true;
5273
5274 return 0;
5275 }
5276
5277 #endif
5278 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5279 {
5280 struct e1000_hw *hw = &adapter->hw;
5281 u32 ping;
5282 int i;
5283
5284 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5285 ping = E1000_PF_CONTROL_MSG;
5286 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5287 ping |= E1000_VT_MSGTYPE_CTS;
5288 igb_write_mbx(hw, &ping, 1, i);
5289 }
5290 }
5291
5292 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5293 {
5294 struct e1000_hw *hw = &adapter->hw;
5295 u32 vmolr = rd32(E1000_VMOLR(vf));
5296 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5297
5298 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5299 IGB_VF_FLAG_MULTI_PROMISC);
5300 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5301
5302 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5303 vmolr |= E1000_VMOLR_MPME;
5304 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5305 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5306 } else {
5307 /* if we have hashes and we are clearing a multicast promisc
5308 * flag we need to write the hashes to the MTA as this step
5309 * was previously skipped
5310 */
5311 if (vf_data->num_vf_mc_hashes > 30) {
5312 vmolr |= E1000_VMOLR_MPME;
5313 } else if (vf_data->num_vf_mc_hashes) {
5314 int j;
5315 vmolr |= E1000_VMOLR_ROMPE;
5316 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5317 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5318 }
5319 }
5320
5321 wr32(E1000_VMOLR(vf), vmolr);
5322
5323 /* there are flags left unprocessed, likely not supported */
5324 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5325 return -EINVAL;
5326
5327 return 0;
5328 }
5329
5330 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5331 u32 *msgbuf, u32 vf)
5332 {
5333 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5334 u16 *hash_list = (u16 *)&msgbuf[1];
5335 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5336 int i;
5337
5338 /* salt away the number of multicast addresses assigned
5339 * to this VF for later use to restore when the PF multi cast
5340 * list changes
5341 */
5342 vf_data->num_vf_mc_hashes = n;
5343
5344 /* only up to 30 hash values supported */
5345 if (n > 30)
5346 n = 30;
5347
5348 /* store the hashes for later use */
5349 for (i = 0; i < n; i++)
5350 vf_data->vf_mc_hashes[i] = hash_list[i];
5351
5352 /* Flush and reset the mta with the new values */
5353 igb_set_rx_mode(adapter->netdev);
5354
5355 return 0;
5356 }
5357
5358 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5359 {
5360 struct e1000_hw *hw = &adapter->hw;
5361 struct vf_data_storage *vf_data;
5362 int i, j;
5363
5364 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5365 u32 vmolr = rd32(E1000_VMOLR(i));
5366 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5367
5368 vf_data = &adapter->vf_data[i];
5369
5370 if ((vf_data->num_vf_mc_hashes > 30) ||
5371 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5372 vmolr |= E1000_VMOLR_MPME;
5373 } else if (vf_data->num_vf_mc_hashes) {
5374 vmolr |= E1000_VMOLR_ROMPE;
5375 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5376 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5377 }
5378 wr32(E1000_VMOLR(i), vmolr);
5379 }
5380 }
5381
5382 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5383 {
5384 struct e1000_hw *hw = &adapter->hw;
5385 u32 pool_mask, reg, vid;
5386 int i;
5387
5388 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5389
5390 /* Find the vlan filter for this id */
5391 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5392 reg = rd32(E1000_VLVF(i));
5393
5394 /* remove the vf from the pool */
5395 reg &= ~pool_mask;
5396
5397 /* if pool is empty then remove entry from vfta */
5398 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5399 (reg & E1000_VLVF_VLANID_ENABLE)) {
5400 reg = 0;
5401 vid = reg & E1000_VLVF_VLANID_MASK;
5402 igb_vfta_set(hw, vid, false);
5403 }
5404
5405 wr32(E1000_VLVF(i), reg);
5406 }
5407
5408 adapter->vf_data[vf].vlans_enabled = 0;
5409 }
5410
5411 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5412 {
5413 struct e1000_hw *hw = &adapter->hw;
5414 u32 reg, i;
5415
5416 /* The vlvf table only exists on 82576 hardware and newer */
5417 if (hw->mac.type < e1000_82576)
5418 return -1;
5419
5420 /* we only need to do this if VMDq is enabled */
5421 if (!adapter->vfs_allocated_count)
5422 return -1;
5423
5424 /* Find the vlan filter for this id */
5425 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5426 reg = rd32(E1000_VLVF(i));
5427 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5428 vid == (reg & E1000_VLVF_VLANID_MASK))
5429 break;
5430 }
5431
5432 if (add) {
5433 if (i == E1000_VLVF_ARRAY_SIZE) {
5434 /* Did not find a matching VLAN ID entry that was
5435 * enabled. Search for a free filter entry, i.e.
5436 * one without the enable bit set
5437 */
5438 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5439 reg = rd32(E1000_VLVF(i));
5440 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5441 break;
5442 }
5443 }
5444 if (i < E1000_VLVF_ARRAY_SIZE) {
5445 /* Found an enabled/available entry */
5446 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5447
5448 /* if !enabled we need to set this up in vfta */
5449 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5450 /* add VID to filter table */
5451 igb_vfta_set(hw, vid, true);
5452 reg |= E1000_VLVF_VLANID_ENABLE;
5453 }
5454 reg &= ~E1000_VLVF_VLANID_MASK;
5455 reg |= vid;
5456 wr32(E1000_VLVF(i), reg);
5457
5458 /* do not modify RLPML for PF devices */
5459 if (vf >= adapter->vfs_allocated_count)
5460 return 0;
5461
5462 if (!adapter->vf_data[vf].vlans_enabled) {
5463 u32 size;
5464 reg = rd32(E1000_VMOLR(vf));
5465 size = reg & E1000_VMOLR_RLPML_MASK;
5466 size += 4;
5467 reg &= ~E1000_VMOLR_RLPML_MASK;
5468 reg |= size;
5469 wr32(E1000_VMOLR(vf), reg);
5470 }
5471
5472 adapter->vf_data[vf].vlans_enabled++;
5473 }
5474 } else {
5475 if (i < E1000_VLVF_ARRAY_SIZE) {
5476 /* remove vf from the pool */
5477 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5478 /* if pool is empty then remove entry from vfta */
5479 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5480 reg = 0;
5481 igb_vfta_set(hw, vid, false);
5482 }
5483 wr32(E1000_VLVF(i), reg);
5484
5485 /* do not modify RLPML for PF devices */
5486 if (vf >= adapter->vfs_allocated_count)
5487 return 0;
5488
5489 adapter->vf_data[vf].vlans_enabled--;
5490 if (!adapter->vf_data[vf].vlans_enabled) {
5491 u32 size;
5492 reg = rd32(E1000_VMOLR(vf));
5493 size = reg & E1000_VMOLR_RLPML_MASK;
5494 size -= 4;
5495 reg &= ~E1000_VMOLR_RLPML_MASK;
5496 reg |= size;
5497 wr32(E1000_VMOLR(vf), reg);
5498 }
5499 }
5500 }
5501 return 0;
5502 }
5503
5504 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5505 {
5506 struct e1000_hw *hw = &adapter->hw;
5507
5508 if (vid)
5509 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5510 else
5511 wr32(E1000_VMVIR(vf), 0);
5512 }
5513
5514 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5515 int vf, u16 vlan, u8 qos)
5516 {
5517 int err = 0;
5518 struct igb_adapter *adapter = netdev_priv(netdev);
5519
5520 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5521 return -EINVAL;
5522 if (vlan || qos) {
5523 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5524 if (err)
5525 goto out;
5526 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5527 igb_set_vmolr(adapter, vf, !vlan);
5528 adapter->vf_data[vf].pf_vlan = vlan;
5529 adapter->vf_data[vf].pf_qos = qos;
5530 dev_info(&adapter->pdev->dev,
5531 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5532 if (test_bit(__IGB_DOWN, &adapter->state)) {
5533 dev_warn(&adapter->pdev->dev,
5534 "The VF VLAN has been set, but the PF device is not up.\n");
5535 dev_warn(&adapter->pdev->dev,
5536 "Bring the PF device up before attempting to use the VF device.\n");
5537 }
5538 } else {
5539 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5540 false, vf);
5541 igb_set_vmvir(adapter, vlan, vf);
5542 igb_set_vmolr(adapter, vf, true);
5543 adapter->vf_data[vf].pf_vlan = 0;
5544 adapter->vf_data[vf].pf_qos = 0;
5545 }
5546 out:
5547 return err;
5548 }
5549
5550 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5551 {
5552 struct e1000_hw *hw = &adapter->hw;
5553 int i;
5554 u32 reg;
5555
5556 /* Find the vlan filter for this id */
5557 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5558 reg = rd32(E1000_VLVF(i));
5559 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5560 vid == (reg & E1000_VLVF_VLANID_MASK))
5561 break;
5562 }
5563
5564 if (i >= E1000_VLVF_ARRAY_SIZE)
5565 i = -1;
5566
5567 return i;
5568 }
5569
5570 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5571 {
5572 struct e1000_hw *hw = &adapter->hw;
5573 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5574 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5575 int err = 0;
5576
5577 /* If in promiscuous mode we need to make sure the PF also has
5578 * the VLAN filter set.
5579 */
5580 if (add && (adapter->netdev->flags & IFF_PROMISC))
5581 err = igb_vlvf_set(adapter, vid, add,
5582 adapter->vfs_allocated_count);
5583 if (err)
5584 goto out;
5585
5586 err = igb_vlvf_set(adapter, vid, add, vf);
5587
5588 if (err)
5589 goto out;
5590
5591 /* Go through all the checks to see if the VLAN filter should
5592 * be wiped completely.
5593 */
5594 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5595 u32 vlvf, bits;
5596
5597 int regndx = igb_find_vlvf_entry(adapter, vid);
5598 if (regndx < 0)
5599 goto out;
5600 /* See if any other pools are set for this VLAN filter
5601 * entry other than the PF.
5602 */
5603 vlvf = bits = rd32(E1000_VLVF(regndx));
5604 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5605 adapter->vfs_allocated_count);
5606 /* If the filter was removed then ensure PF pool bit
5607 * is cleared if the PF only added itself to the pool
5608 * because the PF is in promiscuous mode.
5609 */
5610 if ((vlvf & VLAN_VID_MASK) == vid &&
5611 !test_bit(vid, adapter->active_vlans) &&
5612 !bits)
5613 igb_vlvf_set(adapter, vid, add,
5614 adapter->vfs_allocated_count);
5615 }
5616
5617 out:
5618 return err;
5619 }
5620
5621 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5622 {
5623 /* clear flags - except flag that indicates PF has set the MAC */
5624 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5625 adapter->vf_data[vf].last_nack = jiffies;
5626
5627 /* reset offloads to defaults */
5628 igb_set_vmolr(adapter, vf, true);
5629
5630 /* reset vlans for device */
5631 igb_clear_vf_vfta(adapter, vf);
5632 if (adapter->vf_data[vf].pf_vlan)
5633 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5634 adapter->vf_data[vf].pf_vlan,
5635 adapter->vf_data[vf].pf_qos);
5636 else
5637 igb_clear_vf_vfta(adapter, vf);
5638
5639 /* reset multicast table array for vf */
5640 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5641
5642 /* Flush and reset the mta with the new values */
5643 igb_set_rx_mode(adapter->netdev);
5644 }
5645
5646 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5647 {
5648 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5649
5650 /* clear mac address as we were hotplug removed/added */
5651 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5652 eth_zero_addr(vf_mac);
5653
5654 /* process remaining reset events */
5655 igb_vf_reset(adapter, vf);
5656 }
5657
5658 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5659 {
5660 struct e1000_hw *hw = &adapter->hw;
5661 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5662 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5663 u32 reg, msgbuf[3];
5664 u8 *addr = (u8 *)(&msgbuf[1]);
5665
5666 /* process all the same items cleared in a function level reset */
5667 igb_vf_reset(adapter, vf);
5668
5669 /* set vf mac address */
5670 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5671
5672 /* enable transmit and receive for vf */
5673 reg = rd32(E1000_VFTE);
5674 wr32(E1000_VFTE, reg | (1 << vf));
5675 reg = rd32(E1000_VFRE);
5676 wr32(E1000_VFRE, reg | (1 << vf));
5677
5678 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5679
5680 /* reply to reset with ack and vf mac address */
5681 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5682 memcpy(addr, vf_mac, 6);
5683 igb_write_mbx(hw, msgbuf, 3, vf);
5684 }
5685
5686 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5687 {
5688 /* The VF MAC Address is stored in a packed array of bytes
5689 * starting at the second 32 bit word of the msg array
5690 */
5691 unsigned char *addr = (char *)&msg[1];
5692 int err = -1;
5693
5694 if (is_valid_ether_addr(addr))
5695 err = igb_set_vf_mac(adapter, vf, addr);
5696
5697 return err;
5698 }
5699
5700 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5701 {
5702 struct e1000_hw *hw = &adapter->hw;
5703 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5704 u32 msg = E1000_VT_MSGTYPE_NACK;
5705
5706 /* if device isn't clear to send it shouldn't be reading either */
5707 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5708 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5709 igb_write_mbx(hw, &msg, 1, vf);
5710 vf_data->last_nack = jiffies;
5711 }
5712 }
5713
5714 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5715 {
5716 struct pci_dev *pdev = adapter->pdev;
5717 u32 msgbuf[E1000_VFMAILBOX_SIZE];
5718 struct e1000_hw *hw = &adapter->hw;
5719 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5720 s32 retval;
5721
5722 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5723
5724 if (retval) {
5725 /* if receive failed revoke VF CTS stats and restart init */
5726 dev_err(&pdev->dev, "Error receiving message from VF\n");
5727 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5728 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5729 return;
5730 goto out;
5731 }
5732
5733 /* this is a message we already processed, do nothing */
5734 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5735 return;
5736
5737 /* until the vf completes a reset it should not be
5738 * allowed to start any configuration.
5739 */
5740 if (msgbuf[0] == E1000_VF_RESET) {
5741 igb_vf_reset_msg(adapter, vf);
5742 return;
5743 }
5744
5745 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5746 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5747 return;
5748 retval = -1;
5749 goto out;
5750 }
5751
5752 switch ((msgbuf[0] & 0xFFFF)) {
5753 case E1000_VF_SET_MAC_ADDR:
5754 retval = -EINVAL;
5755 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5756 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5757 else
5758 dev_warn(&pdev->dev,
5759 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5760 vf);
5761 break;
5762 case E1000_VF_SET_PROMISC:
5763 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5764 break;
5765 case E1000_VF_SET_MULTICAST:
5766 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5767 break;
5768 case E1000_VF_SET_LPE:
5769 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5770 break;
5771 case E1000_VF_SET_VLAN:
5772 retval = -1;
5773 if (vf_data->pf_vlan)
5774 dev_warn(&pdev->dev,
5775 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5776 vf);
5777 else
5778 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5779 break;
5780 default:
5781 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5782 retval = -1;
5783 break;
5784 }
5785
5786 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5787 out:
5788 /* notify the VF of the results of what it sent us */
5789 if (retval)
5790 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5791 else
5792 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5793
5794 igb_write_mbx(hw, msgbuf, 1, vf);
5795 }
5796
5797 static void igb_msg_task(struct igb_adapter *adapter)
5798 {
5799 struct e1000_hw *hw = &adapter->hw;
5800 u32 vf;
5801
5802 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5803 /* process any reset requests */
5804 if (!igb_check_for_rst(hw, vf))
5805 igb_vf_reset_event(adapter, vf);
5806
5807 /* process any messages pending */
5808 if (!igb_check_for_msg(hw, vf))
5809 igb_rcv_msg_from_vf(adapter, vf);
5810
5811 /* process any acks */
5812 if (!igb_check_for_ack(hw, vf))
5813 igb_rcv_ack_from_vf(adapter, vf);
5814 }
5815 }
5816
5817 /**
5818 * igb_set_uta - Set unicast filter table address
5819 * @adapter: board private structure
5820 *
5821 * The unicast table address is a register array of 32-bit registers.
5822 * The table is meant to be used in a way similar to how the MTA is used
5823 * however due to certain limitations in the hardware it is necessary to
5824 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5825 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
5826 **/
5827 static void igb_set_uta(struct igb_adapter *adapter)
5828 {
5829 struct e1000_hw *hw = &adapter->hw;
5830 int i;
5831
5832 /* The UTA table only exists on 82576 hardware and newer */
5833 if (hw->mac.type < e1000_82576)
5834 return;
5835
5836 /* we only need to do this if VMDq is enabled */
5837 if (!adapter->vfs_allocated_count)
5838 return;
5839
5840 for (i = 0; i < hw->mac.uta_reg_count; i++)
5841 array_wr32(E1000_UTA, i, ~0);
5842 }
5843
5844 /**
5845 * igb_intr_msi - Interrupt Handler
5846 * @irq: interrupt number
5847 * @data: pointer to a network interface device structure
5848 **/
5849 static irqreturn_t igb_intr_msi(int irq, void *data)
5850 {
5851 struct igb_adapter *adapter = data;
5852 struct igb_q_vector *q_vector = adapter->q_vector[0];
5853 struct e1000_hw *hw = &adapter->hw;
5854 /* read ICR disables interrupts using IAM */
5855 u32 icr = rd32(E1000_ICR);
5856
5857 igb_write_itr(q_vector);
5858
5859 if (icr & E1000_ICR_DRSTA)
5860 schedule_work(&adapter->reset_task);
5861
5862 if (icr & E1000_ICR_DOUTSYNC) {
5863 /* HW is reporting DMA is out of sync */
5864 adapter->stats.doosync++;
5865 }
5866
5867 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5868 hw->mac.get_link_status = 1;
5869 if (!test_bit(__IGB_DOWN, &adapter->state))
5870 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5871 }
5872
5873 if (icr & E1000_ICR_TS) {
5874 u32 tsicr = rd32(E1000_TSICR);
5875
5876 if (tsicr & E1000_TSICR_TXTS) {
5877 /* acknowledge the interrupt */
5878 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5879 /* retrieve hardware timestamp */
5880 schedule_work(&adapter->ptp_tx_work);
5881 }
5882 }
5883
5884 napi_schedule(&q_vector->napi);
5885
5886 return IRQ_HANDLED;
5887 }
5888
5889 /**
5890 * igb_intr - Legacy Interrupt Handler
5891 * @irq: interrupt number
5892 * @data: pointer to a network interface device structure
5893 **/
5894 static irqreturn_t igb_intr(int irq, void *data)
5895 {
5896 struct igb_adapter *adapter = data;
5897 struct igb_q_vector *q_vector = adapter->q_vector[0];
5898 struct e1000_hw *hw = &adapter->hw;
5899 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5900 * need for the IMC write
5901 */
5902 u32 icr = rd32(E1000_ICR);
5903
5904 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5905 * not set, then the adapter didn't send an interrupt
5906 */
5907 if (!(icr & E1000_ICR_INT_ASSERTED))
5908 return IRQ_NONE;
5909
5910 igb_write_itr(q_vector);
5911
5912 if (icr & E1000_ICR_DRSTA)
5913 schedule_work(&adapter->reset_task);
5914
5915 if (icr & E1000_ICR_DOUTSYNC) {
5916 /* HW is reporting DMA is out of sync */
5917 adapter->stats.doosync++;
5918 }
5919
5920 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5921 hw->mac.get_link_status = 1;
5922 /* guard against interrupt when we're going down */
5923 if (!test_bit(__IGB_DOWN, &adapter->state))
5924 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5925 }
5926
5927 if (icr & E1000_ICR_TS) {
5928 u32 tsicr = rd32(E1000_TSICR);
5929
5930 if (tsicr & E1000_TSICR_TXTS) {
5931 /* acknowledge the interrupt */
5932 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5933 /* retrieve hardware timestamp */
5934 schedule_work(&adapter->ptp_tx_work);
5935 }
5936 }
5937
5938 napi_schedule(&q_vector->napi);
5939
5940 return IRQ_HANDLED;
5941 }
5942
5943 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5944 {
5945 struct igb_adapter *adapter = q_vector->adapter;
5946 struct e1000_hw *hw = &adapter->hw;
5947
5948 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5949 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5950 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5951 igb_set_itr(q_vector);
5952 else
5953 igb_update_ring_itr(q_vector);
5954 }
5955
5956 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5957 if (adapter->msix_entries)
5958 wr32(E1000_EIMS, q_vector->eims_value);
5959 else
5960 igb_irq_enable(adapter);
5961 }
5962 }
5963
5964 /**
5965 * igb_poll - NAPI Rx polling callback
5966 * @napi: napi polling structure
5967 * @budget: count of how many packets we should handle
5968 **/
5969 static int igb_poll(struct napi_struct *napi, int budget)
5970 {
5971 struct igb_q_vector *q_vector = container_of(napi,
5972 struct igb_q_vector,
5973 napi);
5974 bool clean_complete = true;
5975
5976 #ifdef CONFIG_IGB_DCA
5977 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5978 igb_update_dca(q_vector);
5979 #endif
5980 if (q_vector->tx.ring)
5981 clean_complete = igb_clean_tx_irq(q_vector);
5982
5983 if (q_vector->rx.ring)
5984 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5985
5986 /* If all work not completed, return budget and keep polling */
5987 if (!clean_complete)
5988 return budget;
5989
5990 /* If not enough Rx work done, exit the polling mode */
5991 napi_complete(napi);
5992 igb_ring_irq_enable(q_vector);
5993
5994 return 0;
5995 }
5996
5997 /**
5998 * igb_clean_tx_irq - Reclaim resources after transmit completes
5999 * @q_vector: pointer to q_vector containing needed info
6000 *
6001 * returns true if ring is completely cleaned
6002 **/
6003 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6004 {
6005 struct igb_adapter *adapter = q_vector->adapter;
6006 struct igb_ring *tx_ring = q_vector->tx.ring;
6007 struct igb_tx_buffer *tx_buffer;
6008 union e1000_adv_tx_desc *tx_desc;
6009 unsigned int total_bytes = 0, total_packets = 0;
6010 unsigned int budget = q_vector->tx.work_limit;
6011 unsigned int i = tx_ring->next_to_clean;
6012
6013 if (test_bit(__IGB_DOWN, &adapter->state))
6014 return true;
6015
6016 tx_buffer = &tx_ring->tx_buffer_info[i];
6017 tx_desc = IGB_TX_DESC(tx_ring, i);
6018 i -= tx_ring->count;
6019
6020 do {
6021 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6022
6023 /* if next_to_watch is not set then there is no work pending */
6024 if (!eop_desc)
6025 break;
6026
6027 /* prevent any other reads prior to eop_desc */
6028 read_barrier_depends();
6029
6030 /* if DD is not set pending work has not been completed */
6031 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6032 break;
6033
6034 /* clear next_to_watch to prevent false hangs */
6035 tx_buffer->next_to_watch = NULL;
6036
6037 /* update the statistics for this packet */
6038 total_bytes += tx_buffer->bytecount;
6039 total_packets += tx_buffer->gso_segs;
6040
6041 /* free the skb */
6042 dev_kfree_skb_any(tx_buffer->skb);
6043
6044 /* unmap skb header data */
6045 dma_unmap_single(tx_ring->dev,
6046 dma_unmap_addr(tx_buffer, dma),
6047 dma_unmap_len(tx_buffer, len),
6048 DMA_TO_DEVICE);
6049
6050 /* clear tx_buffer data */
6051 tx_buffer->skb = NULL;
6052 dma_unmap_len_set(tx_buffer, len, 0);
6053
6054 /* clear last DMA location and unmap remaining buffers */
6055 while (tx_desc != eop_desc) {
6056 tx_buffer++;
6057 tx_desc++;
6058 i++;
6059 if (unlikely(!i)) {
6060 i -= tx_ring->count;
6061 tx_buffer = tx_ring->tx_buffer_info;
6062 tx_desc = IGB_TX_DESC(tx_ring, 0);
6063 }
6064
6065 /* unmap any remaining paged data */
6066 if (dma_unmap_len(tx_buffer, len)) {
6067 dma_unmap_page(tx_ring->dev,
6068 dma_unmap_addr(tx_buffer, dma),
6069 dma_unmap_len(tx_buffer, len),
6070 DMA_TO_DEVICE);
6071 dma_unmap_len_set(tx_buffer, len, 0);
6072 }
6073 }
6074
6075 /* move us one more past the eop_desc for start of next pkt */
6076 tx_buffer++;
6077 tx_desc++;
6078 i++;
6079 if (unlikely(!i)) {
6080 i -= tx_ring->count;
6081 tx_buffer = tx_ring->tx_buffer_info;
6082 tx_desc = IGB_TX_DESC(tx_ring, 0);
6083 }
6084
6085 /* issue prefetch for next Tx descriptor */
6086 prefetch(tx_desc);
6087
6088 /* update budget accounting */
6089 budget--;
6090 } while (likely(budget));
6091
6092 netdev_tx_completed_queue(txring_txq(tx_ring),
6093 total_packets, total_bytes);
6094 i += tx_ring->count;
6095 tx_ring->next_to_clean = i;
6096 u64_stats_update_begin(&tx_ring->tx_syncp);
6097 tx_ring->tx_stats.bytes += total_bytes;
6098 tx_ring->tx_stats.packets += total_packets;
6099 u64_stats_update_end(&tx_ring->tx_syncp);
6100 q_vector->tx.total_bytes += total_bytes;
6101 q_vector->tx.total_packets += total_packets;
6102
6103 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6104 struct e1000_hw *hw = &adapter->hw;
6105
6106 /* Detect a transmit hang in hardware, this serializes the
6107 * check with the clearing of time_stamp and movement of i
6108 */
6109 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6110 if (tx_buffer->next_to_watch &&
6111 time_after(jiffies, tx_buffer->time_stamp +
6112 (adapter->tx_timeout_factor * HZ)) &&
6113 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6114
6115 /* detected Tx unit hang */
6116 dev_err(tx_ring->dev,
6117 "Detected Tx Unit Hang\n"
6118 " Tx Queue <%d>\n"
6119 " TDH <%x>\n"
6120 " TDT <%x>\n"
6121 " next_to_use <%x>\n"
6122 " next_to_clean <%x>\n"
6123 "buffer_info[next_to_clean]\n"
6124 " time_stamp <%lx>\n"
6125 " next_to_watch <%p>\n"
6126 " jiffies <%lx>\n"
6127 " desc.status <%x>\n",
6128 tx_ring->queue_index,
6129 rd32(E1000_TDH(tx_ring->reg_idx)),
6130 readl(tx_ring->tail),
6131 tx_ring->next_to_use,
6132 tx_ring->next_to_clean,
6133 tx_buffer->time_stamp,
6134 tx_buffer->next_to_watch,
6135 jiffies,
6136 tx_buffer->next_to_watch->wb.status);
6137 netif_stop_subqueue(tx_ring->netdev,
6138 tx_ring->queue_index);
6139
6140 /* we are about to reset, no point in enabling stuff */
6141 return true;
6142 }
6143 }
6144
6145 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6146 if (unlikely(total_packets &&
6147 netif_carrier_ok(tx_ring->netdev) &&
6148 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6149 /* Make sure that anybody stopping the queue after this
6150 * sees the new next_to_clean.
6151 */
6152 smp_mb();
6153 if (__netif_subqueue_stopped(tx_ring->netdev,
6154 tx_ring->queue_index) &&
6155 !(test_bit(__IGB_DOWN, &adapter->state))) {
6156 netif_wake_subqueue(tx_ring->netdev,
6157 tx_ring->queue_index);
6158
6159 u64_stats_update_begin(&tx_ring->tx_syncp);
6160 tx_ring->tx_stats.restart_queue++;
6161 u64_stats_update_end(&tx_ring->tx_syncp);
6162 }
6163 }
6164
6165 return !!budget;
6166 }
6167
6168 /**
6169 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6170 * @rx_ring: rx descriptor ring to store buffers on
6171 * @old_buff: donor buffer to have page reused
6172 *
6173 * Synchronizes page for reuse by the adapter
6174 **/
6175 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6176 struct igb_rx_buffer *old_buff)
6177 {
6178 struct igb_rx_buffer *new_buff;
6179 u16 nta = rx_ring->next_to_alloc;
6180
6181 new_buff = &rx_ring->rx_buffer_info[nta];
6182
6183 /* update, and store next to alloc */
6184 nta++;
6185 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6186
6187 /* transfer page from old buffer to new buffer */
6188 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6189
6190 /* sync the buffer for use by the device */
6191 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6192 old_buff->page_offset,
6193 IGB_RX_BUFSZ,
6194 DMA_FROM_DEVICE);
6195 }
6196
6197 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6198 struct page *page,
6199 unsigned int truesize)
6200 {
6201 /* avoid re-using remote pages */
6202 if (unlikely(page_to_nid(page) != numa_node_id()))
6203 return false;
6204
6205 #if (PAGE_SIZE < 8192)
6206 /* if we are only owner of page we can reuse it */
6207 if (unlikely(page_count(page) != 1))
6208 return false;
6209
6210 /* flip page offset to other buffer */
6211 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6212
6213 /* since we are the only owner of the page and we need to
6214 * increment it, just set the value to 2 in order to avoid
6215 * an unnecessary locked operation
6216 */
6217 atomic_set(&page->_count, 2);
6218 #else
6219 /* move offset up to the next cache line */
6220 rx_buffer->page_offset += truesize;
6221
6222 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6223 return false;
6224
6225 /* bump ref count on page before it is given to the stack */
6226 get_page(page);
6227 #endif
6228
6229 return true;
6230 }
6231
6232 /**
6233 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6234 * @rx_ring: rx descriptor ring to transact packets on
6235 * @rx_buffer: buffer containing page to add
6236 * @rx_desc: descriptor containing length of buffer written by hardware
6237 * @skb: sk_buff to place the data into
6238 *
6239 * This function will add the data contained in rx_buffer->page to the skb.
6240 * This is done either through a direct copy if the data in the buffer is
6241 * less than the skb header size, otherwise it will just attach the page as
6242 * a frag to the skb.
6243 *
6244 * The function will then update the page offset if necessary and return
6245 * true if the buffer can be reused by the adapter.
6246 **/
6247 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6248 struct igb_rx_buffer *rx_buffer,
6249 union e1000_adv_rx_desc *rx_desc,
6250 struct sk_buff *skb)
6251 {
6252 struct page *page = rx_buffer->page;
6253 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6254 #if (PAGE_SIZE < 8192)
6255 unsigned int truesize = IGB_RX_BUFSZ;
6256 #else
6257 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6258 #endif
6259
6260 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6261 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6262
6263 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6264 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6265 va += IGB_TS_HDR_LEN;
6266 size -= IGB_TS_HDR_LEN;
6267 }
6268
6269 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6270
6271 /* we can reuse buffer as-is, just make sure it is local */
6272 if (likely(page_to_nid(page) == numa_node_id()))
6273 return true;
6274
6275 /* this page cannot be reused so discard it */
6276 put_page(page);
6277 return false;
6278 }
6279
6280 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6281 rx_buffer->page_offset, size, truesize);
6282
6283 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6284 }
6285
6286 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6287 union e1000_adv_rx_desc *rx_desc,
6288 struct sk_buff *skb)
6289 {
6290 struct igb_rx_buffer *rx_buffer;
6291 struct page *page;
6292
6293 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6294
6295 page = rx_buffer->page;
6296 prefetchw(page);
6297
6298 if (likely(!skb)) {
6299 void *page_addr = page_address(page) +
6300 rx_buffer->page_offset;
6301
6302 /* prefetch first cache line of first page */
6303 prefetch(page_addr);
6304 #if L1_CACHE_BYTES < 128
6305 prefetch(page_addr + L1_CACHE_BYTES);
6306 #endif
6307
6308 /* allocate a skb to store the frags */
6309 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6310 IGB_RX_HDR_LEN);
6311 if (unlikely(!skb)) {
6312 rx_ring->rx_stats.alloc_failed++;
6313 return NULL;
6314 }
6315
6316 /* we will be copying header into skb->data in
6317 * pskb_may_pull so it is in our interest to prefetch
6318 * it now to avoid a possible cache miss
6319 */
6320 prefetchw(skb->data);
6321 }
6322
6323 /* we are reusing so sync this buffer for CPU use */
6324 dma_sync_single_range_for_cpu(rx_ring->dev,
6325 rx_buffer->dma,
6326 rx_buffer->page_offset,
6327 IGB_RX_BUFSZ,
6328 DMA_FROM_DEVICE);
6329
6330 /* pull page into skb */
6331 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6332 /* hand second half of page back to the ring */
6333 igb_reuse_rx_page(rx_ring, rx_buffer);
6334 } else {
6335 /* we are not reusing the buffer so unmap it */
6336 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6337 PAGE_SIZE, DMA_FROM_DEVICE);
6338 }
6339
6340 /* clear contents of rx_buffer */
6341 rx_buffer->page = NULL;
6342
6343 return skb;
6344 }
6345
6346 static inline void igb_rx_checksum(struct igb_ring *ring,
6347 union e1000_adv_rx_desc *rx_desc,
6348 struct sk_buff *skb)
6349 {
6350 skb_checksum_none_assert(skb);
6351
6352 /* Ignore Checksum bit is set */
6353 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6354 return;
6355
6356 /* Rx checksum disabled via ethtool */
6357 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6358 return;
6359
6360 /* TCP/UDP checksum error bit is set */
6361 if (igb_test_staterr(rx_desc,
6362 E1000_RXDEXT_STATERR_TCPE |
6363 E1000_RXDEXT_STATERR_IPE)) {
6364 /* work around errata with sctp packets where the TCPE aka
6365 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6366 * packets, (aka let the stack check the crc32c)
6367 */
6368 if (!((skb->len == 60) &&
6369 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6370 u64_stats_update_begin(&ring->rx_syncp);
6371 ring->rx_stats.csum_err++;
6372 u64_stats_update_end(&ring->rx_syncp);
6373 }
6374 /* let the stack verify checksum errors */
6375 return;
6376 }
6377 /* It must be a TCP or UDP packet with a valid checksum */
6378 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6379 E1000_RXD_STAT_UDPCS))
6380 skb->ip_summed = CHECKSUM_UNNECESSARY;
6381
6382 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6383 le32_to_cpu(rx_desc->wb.upper.status_error));
6384 }
6385
6386 static inline void igb_rx_hash(struct igb_ring *ring,
6387 union e1000_adv_rx_desc *rx_desc,
6388 struct sk_buff *skb)
6389 {
6390 if (ring->netdev->features & NETIF_F_RXHASH)
6391 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6392 }
6393
6394 /**
6395 * igb_is_non_eop - process handling of non-EOP buffers
6396 * @rx_ring: Rx ring being processed
6397 * @rx_desc: Rx descriptor for current buffer
6398 * @skb: current socket buffer containing buffer in progress
6399 *
6400 * This function updates next to clean. If the buffer is an EOP buffer
6401 * this function exits returning false, otherwise it will place the
6402 * sk_buff in the next buffer to be chained and return true indicating
6403 * that this is in fact a non-EOP buffer.
6404 **/
6405 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6406 union e1000_adv_rx_desc *rx_desc)
6407 {
6408 u32 ntc = rx_ring->next_to_clean + 1;
6409
6410 /* fetch, update, and store next to clean */
6411 ntc = (ntc < rx_ring->count) ? ntc : 0;
6412 rx_ring->next_to_clean = ntc;
6413
6414 prefetch(IGB_RX_DESC(rx_ring, ntc));
6415
6416 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6417 return false;
6418
6419 return true;
6420 }
6421
6422 /**
6423 * igb_get_headlen - determine size of header for LRO/GRO
6424 * @data: pointer to the start of the headers
6425 * @max_len: total length of section to find headers in
6426 *
6427 * This function is meant to determine the length of headers that will
6428 * be recognized by hardware for LRO, and GRO offloads. The main
6429 * motivation of doing this is to only perform one pull for IPv4 TCP
6430 * packets so that we can do basic things like calculating the gso_size
6431 * based on the average data per packet.
6432 **/
6433 static unsigned int igb_get_headlen(unsigned char *data,
6434 unsigned int max_len)
6435 {
6436 union {
6437 unsigned char *network;
6438 /* l2 headers */
6439 struct ethhdr *eth;
6440 struct vlan_hdr *vlan;
6441 /* l3 headers */
6442 struct iphdr *ipv4;
6443 struct ipv6hdr *ipv6;
6444 } hdr;
6445 __be16 protocol;
6446 u8 nexthdr = 0; /* default to not TCP */
6447 u8 hlen;
6448
6449 /* this should never happen, but better safe than sorry */
6450 if (max_len < ETH_HLEN)
6451 return max_len;
6452
6453 /* initialize network frame pointer */
6454 hdr.network = data;
6455
6456 /* set first protocol and move network header forward */
6457 protocol = hdr.eth->h_proto;
6458 hdr.network += ETH_HLEN;
6459
6460 /* handle any vlan tag if present */
6461 if (protocol == __constant_htons(ETH_P_8021Q)) {
6462 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6463 return max_len;
6464
6465 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6466 hdr.network += VLAN_HLEN;
6467 }
6468
6469 /* handle L3 protocols */
6470 if (protocol == __constant_htons(ETH_P_IP)) {
6471 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6472 return max_len;
6473
6474 /* access ihl as a u8 to avoid unaligned access on ia64 */
6475 hlen = (hdr.network[0] & 0x0F) << 2;
6476
6477 /* verify hlen meets minimum size requirements */
6478 if (hlen < sizeof(struct iphdr))
6479 return hdr.network - data;
6480
6481 /* record next protocol if header is present */
6482 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
6483 nexthdr = hdr.ipv4->protocol;
6484 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6485 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6486 return max_len;
6487
6488 /* record next protocol */
6489 nexthdr = hdr.ipv6->nexthdr;
6490 hlen = sizeof(struct ipv6hdr);
6491 } else {
6492 return hdr.network - data;
6493 }
6494
6495 /* relocate pointer to start of L4 header */
6496 hdr.network += hlen;
6497
6498 /* finally sort out TCP */
6499 if (nexthdr == IPPROTO_TCP) {
6500 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6501 return max_len;
6502
6503 /* access doff as a u8 to avoid unaligned access on ia64 */
6504 hlen = (hdr.network[12] & 0xF0) >> 2;
6505
6506 /* verify hlen meets minimum size requirements */
6507 if (hlen < sizeof(struct tcphdr))
6508 return hdr.network - data;
6509
6510 hdr.network += hlen;
6511 } else if (nexthdr == IPPROTO_UDP) {
6512 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6513 return max_len;
6514
6515 hdr.network += sizeof(struct udphdr);
6516 }
6517
6518 /* If everything has gone correctly hdr.network should be the
6519 * data section of the packet and will be the end of the header.
6520 * If not then it probably represents the end of the last recognized
6521 * header.
6522 */
6523 if ((hdr.network - data) < max_len)
6524 return hdr.network - data;
6525 else
6526 return max_len;
6527 }
6528
6529 /**
6530 * igb_pull_tail - igb specific version of skb_pull_tail
6531 * @rx_ring: rx descriptor ring packet is being transacted on
6532 * @rx_desc: pointer to the EOP Rx descriptor
6533 * @skb: pointer to current skb being adjusted
6534 *
6535 * This function is an igb specific version of __pskb_pull_tail. The
6536 * main difference between this version and the original function is that
6537 * this function can make several assumptions about the state of things
6538 * that allow for significant optimizations versus the standard function.
6539 * As a result we can do things like drop a frag and maintain an accurate
6540 * truesize for the skb.
6541 */
6542 static void igb_pull_tail(struct igb_ring *rx_ring,
6543 union e1000_adv_rx_desc *rx_desc,
6544 struct sk_buff *skb)
6545 {
6546 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6547 unsigned char *va;
6548 unsigned int pull_len;
6549
6550 /* it is valid to use page_address instead of kmap since we are
6551 * working with pages allocated out of the lomem pool per
6552 * alloc_page(GFP_ATOMIC)
6553 */
6554 va = skb_frag_address(frag);
6555
6556 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6557 /* retrieve timestamp from buffer */
6558 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6559
6560 /* update pointers to remove timestamp header */
6561 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6562 frag->page_offset += IGB_TS_HDR_LEN;
6563 skb->data_len -= IGB_TS_HDR_LEN;
6564 skb->len -= IGB_TS_HDR_LEN;
6565
6566 /* move va to start of packet data */
6567 va += IGB_TS_HDR_LEN;
6568 }
6569
6570 /* we need the header to contain the greater of either ETH_HLEN or
6571 * 60 bytes if the skb->len is less than 60 for skb_pad.
6572 */
6573 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6574
6575 /* align pull length to size of long to optimize memcpy performance */
6576 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6577
6578 /* update all of the pointers */
6579 skb_frag_size_sub(frag, pull_len);
6580 frag->page_offset += pull_len;
6581 skb->data_len -= pull_len;
6582 skb->tail += pull_len;
6583 }
6584
6585 /**
6586 * igb_cleanup_headers - Correct corrupted or empty headers
6587 * @rx_ring: rx descriptor ring packet is being transacted on
6588 * @rx_desc: pointer to the EOP Rx descriptor
6589 * @skb: pointer to current skb being fixed
6590 *
6591 * Address the case where we are pulling data in on pages only
6592 * and as such no data is present in the skb header.
6593 *
6594 * In addition if skb is not at least 60 bytes we need to pad it so that
6595 * it is large enough to qualify as a valid Ethernet frame.
6596 *
6597 * Returns true if an error was encountered and skb was freed.
6598 **/
6599 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6600 union e1000_adv_rx_desc *rx_desc,
6601 struct sk_buff *skb)
6602 {
6603 if (unlikely((igb_test_staterr(rx_desc,
6604 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6605 struct net_device *netdev = rx_ring->netdev;
6606 if (!(netdev->features & NETIF_F_RXALL)) {
6607 dev_kfree_skb_any(skb);
6608 return true;
6609 }
6610 }
6611
6612 /* place header in linear portion of buffer */
6613 if (skb_is_nonlinear(skb))
6614 igb_pull_tail(rx_ring, rx_desc, skb);
6615
6616 /* if skb_pad returns an error the skb was freed */
6617 if (unlikely(skb->len < 60)) {
6618 int pad_len = 60 - skb->len;
6619
6620 if (skb_pad(skb, pad_len))
6621 return true;
6622 __skb_put(skb, pad_len);
6623 }
6624
6625 return false;
6626 }
6627
6628 /**
6629 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6630 * @rx_ring: rx descriptor ring packet is being transacted on
6631 * @rx_desc: pointer to the EOP Rx descriptor
6632 * @skb: pointer to current skb being populated
6633 *
6634 * This function checks the ring, descriptor, and packet information in
6635 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6636 * other fields within the skb.
6637 **/
6638 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6639 union e1000_adv_rx_desc *rx_desc,
6640 struct sk_buff *skb)
6641 {
6642 struct net_device *dev = rx_ring->netdev;
6643
6644 igb_rx_hash(rx_ring, rx_desc, skb);
6645
6646 igb_rx_checksum(rx_ring, rx_desc, skb);
6647
6648 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
6649
6650 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6651 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6652 u16 vid;
6653 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6654 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6655 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6656 else
6657 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6658
6659 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6660 }
6661
6662 skb_record_rx_queue(skb, rx_ring->queue_index);
6663
6664 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6665 }
6666
6667 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6668 {
6669 struct igb_ring *rx_ring = q_vector->rx.ring;
6670 struct sk_buff *skb = rx_ring->skb;
6671 unsigned int total_bytes = 0, total_packets = 0;
6672 u16 cleaned_count = igb_desc_unused(rx_ring);
6673
6674 do {
6675 union e1000_adv_rx_desc *rx_desc;
6676
6677 /* return some buffers to hardware, one at a time is too slow */
6678 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6679 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6680 cleaned_count = 0;
6681 }
6682
6683 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6684
6685 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6686 break;
6687
6688 /* This memory barrier is needed to keep us from reading
6689 * any other fields out of the rx_desc until we know the
6690 * RXD_STAT_DD bit is set
6691 */
6692 rmb();
6693
6694 /* retrieve a buffer from the ring */
6695 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6696
6697 /* exit if we failed to retrieve a buffer */
6698 if (!skb)
6699 break;
6700
6701 cleaned_count++;
6702
6703 /* fetch next buffer in frame if non-eop */
6704 if (igb_is_non_eop(rx_ring, rx_desc))
6705 continue;
6706
6707 /* verify the packet layout is correct */
6708 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6709 skb = NULL;
6710 continue;
6711 }
6712
6713 /* probably a little skewed due to removing CRC */
6714 total_bytes += skb->len;
6715
6716 /* populate checksum, timestamp, VLAN, and protocol */
6717 igb_process_skb_fields(rx_ring, rx_desc, skb);
6718
6719 napi_gro_receive(&q_vector->napi, skb);
6720
6721 /* reset skb pointer */
6722 skb = NULL;
6723
6724 /* update budget accounting */
6725 total_packets++;
6726 } while (likely(total_packets < budget));
6727
6728 /* place incomplete frames back on ring for completion */
6729 rx_ring->skb = skb;
6730
6731 u64_stats_update_begin(&rx_ring->rx_syncp);
6732 rx_ring->rx_stats.packets += total_packets;
6733 rx_ring->rx_stats.bytes += total_bytes;
6734 u64_stats_update_end(&rx_ring->rx_syncp);
6735 q_vector->rx.total_packets += total_packets;
6736 q_vector->rx.total_bytes += total_bytes;
6737
6738 if (cleaned_count)
6739 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6740
6741 return (total_packets < budget);
6742 }
6743
6744 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6745 struct igb_rx_buffer *bi)
6746 {
6747 struct page *page = bi->page;
6748 dma_addr_t dma;
6749
6750 /* since we are recycling buffers we should seldom need to alloc */
6751 if (likely(page))
6752 return true;
6753
6754 /* alloc new page for storage */
6755 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6756 if (unlikely(!page)) {
6757 rx_ring->rx_stats.alloc_failed++;
6758 return false;
6759 }
6760
6761 /* map page for use */
6762 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6763
6764 /* if mapping failed free memory back to system since
6765 * there isn't much point in holding memory we can't use
6766 */
6767 if (dma_mapping_error(rx_ring->dev, dma)) {
6768 __free_page(page);
6769
6770 rx_ring->rx_stats.alloc_failed++;
6771 return false;
6772 }
6773
6774 bi->dma = dma;
6775 bi->page = page;
6776 bi->page_offset = 0;
6777
6778 return true;
6779 }
6780
6781 /**
6782 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6783 * @adapter: address of board private structure
6784 **/
6785 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6786 {
6787 union e1000_adv_rx_desc *rx_desc;
6788 struct igb_rx_buffer *bi;
6789 u16 i = rx_ring->next_to_use;
6790
6791 /* nothing to do */
6792 if (!cleaned_count)
6793 return;
6794
6795 rx_desc = IGB_RX_DESC(rx_ring, i);
6796 bi = &rx_ring->rx_buffer_info[i];
6797 i -= rx_ring->count;
6798
6799 do {
6800 if (!igb_alloc_mapped_page(rx_ring, bi))
6801 break;
6802
6803 /* Refresh the desc even if buffer_addrs didn't change
6804 * because each write-back erases this info.
6805 */
6806 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6807
6808 rx_desc++;
6809 bi++;
6810 i++;
6811 if (unlikely(!i)) {
6812 rx_desc = IGB_RX_DESC(rx_ring, 0);
6813 bi = rx_ring->rx_buffer_info;
6814 i -= rx_ring->count;
6815 }
6816
6817 /* clear the hdr_addr for the next_to_use descriptor */
6818 rx_desc->read.hdr_addr = 0;
6819
6820 cleaned_count--;
6821 } while (cleaned_count);
6822
6823 i += rx_ring->count;
6824
6825 if (rx_ring->next_to_use != i) {
6826 /* record the next descriptor to use */
6827 rx_ring->next_to_use = i;
6828
6829 /* update next to alloc since we have filled the ring */
6830 rx_ring->next_to_alloc = i;
6831
6832 /* Force memory writes to complete before letting h/w
6833 * know there are new descriptors to fetch. (Only
6834 * applicable for weak-ordered memory model archs,
6835 * such as IA-64).
6836 */
6837 wmb();
6838 writel(i, rx_ring->tail);
6839 }
6840 }
6841
6842 /**
6843 * igb_mii_ioctl -
6844 * @netdev:
6845 * @ifreq:
6846 * @cmd:
6847 **/
6848 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6849 {
6850 struct igb_adapter *adapter = netdev_priv(netdev);
6851 struct mii_ioctl_data *data = if_mii(ifr);
6852
6853 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6854 return -EOPNOTSUPP;
6855
6856 switch (cmd) {
6857 case SIOCGMIIPHY:
6858 data->phy_id = adapter->hw.phy.addr;
6859 break;
6860 case SIOCGMIIREG:
6861 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6862 &data->val_out))
6863 return -EIO;
6864 break;
6865 case SIOCSMIIREG:
6866 default:
6867 return -EOPNOTSUPP;
6868 }
6869 return 0;
6870 }
6871
6872 /**
6873 * igb_ioctl -
6874 * @netdev:
6875 * @ifreq:
6876 * @cmd:
6877 **/
6878 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6879 {
6880 switch (cmd) {
6881 case SIOCGMIIPHY:
6882 case SIOCGMIIREG:
6883 case SIOCSMIIREG:
6884 return igb_mii_ioctl(netdev, ifr, cmd);
6885 case SIOCSHWTSTAMP:
6886 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6887 default:
6888 return -EOPNOTSUPP;
6889 }
6890 }
6891
6892 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6893 {
6894 struct igb_adapter *adapter = hw->back;
6895
6896 if (pcie_capability_read_word(adapter->pdev, reg, value))
6897 return -E1000_ERR_CONFIG;
6898
6899 return 0;
6900 }
6901
6902 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6903 {
6904 struct igb_adapter *adapter = hw->back;
6905
6906 if (pcie_capability_write_word(adapter->pdev, reg, *value))
6907 return -E1000_ERR_CONFIG;
6908
6909 return 0;
6910 }
6911
6912 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6913 {
6914 struct igb_adapter *adapter = netdev_priv(netdev);
6915 struct e1000_hw *hw = &adapter->hw;
6916 u32 ctrl, rctl;
6917 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
6918
6919 if (enable) {
6920 /* enable VLAN tag insert/strip */
6921 ctrl = rd32(E1000_CTRL);
6922 ctrl |= E1000_CTRL_VME;
6923 wr32(E1000_CTRL, ctrl);
6924
6925 /* Disable CFI check */
6926 rctl = rd32(E1000_RCTL);
6927 rctl &= ~E1000_RCTL_CFIEN;
6928 wr32(E1000_RCTL, rctl);
6929 } else {
6930 /* disable VLAN tag insert/strip */
6931 ctrl = rd32(E1000_CTRL);
6932 ctrl &= ~E1000_CTRL_VME;
6933 wr32(E1000_CTRL, ctrl);
6934 }
6935
6936 igb_rlpml_set(adapter);
6937 }
6938
6939 static int igb_vlan_rx_add_vid(struct net_device *netdev,
6940 __be16 proto, u16 vid)
6941 {
6942 struct igb_adapter *adapter = netdev_priv(netdev);
6943 struct e1000_hw *hw = &adapter->hw;
6944 int pf_id = adapter->vfs_allocated_count;
6945
6946 /* attempt to add filter to vlvf array */
6947 igb_vlvf_set(adapter, vid, true, pf_id);
6948
6949 /* add the filter since PF can receive vlans w/o entry in vlvf */
6950 igb_vfta_set(hw, vid, true);
6951
6952 set_bit(vid, adapter->active_vlans);
6953
6954 return 0;
6955 }
6956
6957 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6958 __be16 proto, u16 vid)
6959 {
6960 struct igb_adapter *adapter = netdev_priv(netdev);
6961 struct e1000_hw *hw = &adapter->hw;
6962 int pf_id = adapter->vfs_allocated_count;
6963 s32 err;
6964
6965 /* remove vlan from VLVF table array */
6966 err = igb_vlvf_set(adapter, vid, false, pf_id);
6967
6968 /* if vid was not present in VLVF just remove it from table */
6969 if (err)
6970 igb_vfta_set(hw, vid, false);
6971
6972 clear_bit(vid, adapter->active_vlans);
6973
6974 return 0;
6975 }
6976
6977 static void igb_restore_vlan(struct igb_adapter *adapter)
6978 {
6979 u16 vid;
6980
6981 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6982
6983 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6984 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
6985 }
6986
6987 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6988 {
6989 struct pci_dev *pdev = adapter->pdev;
6990 struct e1000_mac_info *mac = &adapter->hw.mac;
6991
6992 mac->autoneg = 0;
6993
6994 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6995 * for the switch() below to work
6996 */
6997 if ((spd & 1) || (dplx & ~1))
6998 goto err_inval;
6999
7000 /* Fiber NIC's only allow 1000 gbps Full duplex
7001 * and 100Mbps Full duplex for 100baseFx sfp
7002 */
7003 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7004 switch (spd + dplx) {
7005 case SPEED_10 + DUPLEX_HALF:
7006 case SPEED_10 + DUPLEX_FULL:
7007 case SPEED_100 + DUPLEX_HALF:
7008 goto err_inval;
7009 default:
7010 break;
7011 }
7012 }
7013
7014 switch (spd + dplx) {
7015 case SPEED_10 + DUPLEX_HALF:
7016 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7017 break;
7018 case SPEED_10 + DUPLEX_FULL:
7019 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7020 break;
7021 case SPEED_100 + DUPLEX_HALF:
7022 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7023 break;
7024 case SPEED_100 + DUPLEX_FULL:
7025 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7026 break;
7027 case SPEED_1000 + DUPLEX_FULL:
7028 mac->autoneg = 1;
7029 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7030 break;
7031 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7032 default:
7033 goto err_inval;
7034 }
7035
7036 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7037 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7038
7039 return 0;
7040
7041 err_inval:
7042 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7043 return -EINVAL;
7044 }
7045
7046 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7047 bool runtime)
7048 {
7049 struct net_device *netdev = pci_get_drvdata(pdev);
7050 struct igb_adapter *adapter = netdev_priv(netdev);
7051 struct e1000_hw *hw = &adapter->hw;
7052 u32 ctrl, rctl, status;
7053 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7054 #ifdef CONFIG_PM
7055 int retval = 0;
7056 #endif
7057
7058 netif_device_detach(netdev);
7059
7060 if (netif_running(netdev))
7061 __igb_close(netdev, true);
7062
7063 igb_clear_interrupt_scheme(adapter);
7064
7065 #ifdef CONFIG_PM
7066 retval = pci_save_state(pdev);
7067 if (retval)
7068 return retval;
7069 #endif
7070
7071 status = rd32(E1000_STATUS);
7072 if (status & E1000_STATUS_LU)
7073 wufc &= ~E1000_WUFC_LNKC;
7074
7075 if (wufc) {
7076 igb_setup_rctl(adapter);
7077 igb_set_rx_mode(netdev);
7078
7079 /* turn on all-multi mode if wake on multicast is enabled */
7080 if (wufc & E1000_WUFC_MC) {
7081 rctl = rd32(E1000_RCTL);
7082 rctl |= E1000_RCTL_MPE;
7083 wr32(E1000_RCTL, rctl);
7084 }
7085
7086 ctrl = rd32(E1000_CTRL);
7087 /* advertise wake from D3Cold */
7088 #define E1000_CTRL_ADVD3WUC 0x00100000
7089 /* phy power management enable */
7090 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7091 ctrl |= E1000_CTRL_ADVD3WUC;
7092 wr32(E1000_CTRL, ctrl);
7093
7094 /* Allow time for pending master requests to run */
7095 igb_disable_pcie_master(hw);
7096
7097 wr32(E1000_WUC, E1000_WUC_PME_EN);
7098 wr32(E1000_WUFC, wufc);
7099 } else {
7100 wr32(E1000_WUC, 0);
7101 wr32(E1000_WUFC, 0);
7102 }
7103
7104 *enable_wake = wufc || adapter->en_mng_pt;
7105 if (!*enable_wake)
7106 igb_power_down_link(adapter);
7107 else
7108 igb_power_up_link(adapter);
7109
7110 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7111 * would have already happened in close and is redundant.
7112 */
7113 igb_release_hw_control(adapter);
7114
7115 pci_disable_device(pdev);
7116
7117 return 0;
7118 }
7119
7120 #ifdef CONFIG_PM
7121 #ifdef CONFIG_PM_SLEEP
7122 static int igb_suspend(struct device *dev)
7123 {
7124 int retval;
7125 bool wake;
7126 struct pci_dev *pdev = to_pci_dev(dev);
7127
7128 retval = __igb_shutdown(pdev, &wake, 0);
7129 if (retval)
7130 return retval;
7131
7132 if (wake) {
7133 pci_prepare_to_sleep(pdev);
7134 } else {
7135 pci_wake_from_d3(pdev, false);
7136 pci_set_power_state(pdev, PCI_D3hot);
7137 }
7138
7139 return 0;
7140 }
7141 #endif /* CONFIG_PM_SLEEP */
7142
7143 static int igb_resume(struct device *dev)
7144 {
7145 struct pci_dev *pdev = to_pci_dev(dev);
7146 struct net_device *netdev = pci_get_drvdata(pdev);
7147 struct igb_adapter *adapter = netdev_priv(netdev);
7148 struct e1000_hw *hw = &adapter->hw;
7149 u32 err;
7150
7151 pci_set_power_state(pdev, PCI_D0);
7152 pci_restore_state(pdev);
7153 pci_save_state(pdev);
7154
7155 err = pci_enable_device_mem(pdev);
7156 if (err) {
7157 dev_err(&pdev->dev,
7158 "igb: Cannot enable PCI device from suspend\n");
7159 return err;
7160 }
7161 pci_set_master(pdev);
7162
7163 pci_enable_wake(pdev, PCI_D3hot, 0);
7164 pci_enable_wake(pdev, PCI_D3cold, 0);
7165
7166 if (igb_init_interrupt_scheme(adapter, true)) {
7167 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7168 return -ENOMEM;
7169 }
7170
7171 igb_reset(adapter);
7172
7173 /* let the f/w know that the h/w is now under the control of the
7174 * driver.
7175 */
7176 igb_get_hw_control(adapter);
7177
7178 wr32(E1000_WUS, ~0);
7179
7180 if (netdev->flags & IFF_UP) {
7181 rtnl_lock();
7182 err = __igb_open(netdev, true);
7183 rtnl_unlock();
7184 if (err)
7185 return err;
7186 }
7187
7188 netif_device_attach(netdev);
7189 return 0;
7190 }
7191
7192 #ifdef CONFIG_PM_RUNTIME
7193 static int igb_runtime_idle(struct device *dev)
7194 {
7195 struct pci_dev *pdev = to_pci_dev(dev);
7196 struct net_device *netdev = pci_get_drvdata(pdev);
7197 struct igb_adapter *adapter = netdev_priv(netdev);
7198
7199 if (!igb_has_link(adapter))
7200 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7201
7202 return -EBUSY;
7203 }
7204
7205 static int igb_runtime_suspend(struct device *dev)
7206 {
7207 struct pci_dev *pdev = to_pci_dev(dev);
7208 int retval;
7209 bool wake;
7210
7211 retval = __igb_shutdown(pdev, &wake, 1);
7212 if (retval)
7213 return retval;
7214
7215 if (wake) {
7216 pci_prepare_to_sleep(pdev);
7217 } else {
7218 pci_wake_from_d3(pdev, false);
7219 pci_set_power_state(pdev, PCI_D3hot);
7220 }
7221
7222 return 0;
7223 }
7224
7225 static int igb_runtime_resume(struct device *dev)
7226 {
7227 return igb_resume(dev);
7228 }
7229 #endif /* CONFIG_PM_RUNTIME */
7230 #endif
7231
7232 static void igb_shutdown(struct pci_dev *pdev)
7233 {
7234 bool wake;
7235
7236 __igb_shutdown(pdev, &wake, 0);
7237
7238 if (system_state == SYSTEM_POWER_OFF) {
7239 pci_wake_from_d3(pdev, wake);
7240 pci_set_power_state(pdev, PCI_D3hot);
7241 }
7242 }
7243
7244 #ifdef CONFIG_PCI_IOV
7245 static int igb_sriov_reinit(struct pci_dev *dev)
7246 {
7247 struct net_device *netdev = pci_get_drvdata(dev);
7248 struct igb_adapter *adapter = netdev_priv(netdev);
7249 struct pci_dev *pdev = adapter->pdev;
7250
7251 rtnl_lock();
7252
7253 if (netif_running(netdev))
7254 igb_close(netdev);
7255
7256 igb_clear_interrupt_scheme(adapter);
7257
7258 igb_init_queue_configuration(adapter);
7259
7260 if (igb_init_interrupt_scheme(adapter, true)) {
7261 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7262 return -ENOMEM;
7263 }
7264
7265 if (netif_running(netdev))
7266 igb_open(netdev);
7267
7268 rtnl_unlock();
7269
7270 return 0;
7271 }
7272
7273 static int igb_pci_disable_sriov(struct pci_dev *dev)
7274 {
7275 int err = igb_disable_sriov(dev);
7276
7277 if (!err)
7278 err = igb_sriov_reinit(dev);
7279
7280 return err;
7281 }
7282
7283 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7284 {
7285 int err = igb_enable_sriov(dev, num_vfs);
7286
7287 if (err)
7288 goto out;
7289
7290 err = igb_sriov_reinit(dev);
7291 if (!err)
7292 return num_vfs;
7293
7294 out:
7295 return err;
7296 }
7297
7298 #endif
7299 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7300 {
7301 #ifdef CONFIG_PCI_IOV
7302 if (num_vfs == 0)
7303 return igb_pci_disable_sriov(dev);
7304 else
7305 return igb_pci_enable_sriov(dev, num_vfs);
7306 #endif
7307 return 0;
7308 }
7309
7310 #ifdef CONFIG_NET_POLL_CONTROLLER
7311 /* Polling 'interrupt' - used by things like netconsole to send skbs
7312 * without having to re-enable interrupts. It's not called while
7313 * the interrupt routine is executing.
7314 */
7315 static void igb_netpoll(struct net_device *netdev)
7316 {
7317 struct igb_adapter *adapter = netdev_priv(netdev);
7318 struct e1000_hw *hw = &adapter->hw;
7319 struct igb_q_vector *q_vector;
7320 int i;
7321
7322 for (i = 0; i < adapter->num_q_vectors; i++) {
7323 q_vector = adapter->q_vector[i];
7324 if (adapter->msix_entries)
7325 wr32(E1000_EIMC, q_vector->eims_value);
7326 else
7327 igb_irq_disable(adapter);
7328 napi_schedule(&q_vector->napi);
7329 }
7330 }
7331 #endif /* CONFIG_NET_POLL_CONTROLLER */
7332
7333 /**
7334 * igb_io_error_detected - called when PCI error is detected
7335 * @pdev: Pointer to PCI device
7336 * @state: The current pci connection state
7337 *
7338 * This function is called after a PCI bus error affecting
7339 * this device has been detected.
7340 **/
7341 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7342 pci_channel_state_t state)
7343 {
7344 struct net_device *netdev = pci_get_drvdata(pdev);
7345 struct igb_adapter *adapter = netdev_priv(netdev);
7346
7347 netif_device_detach(netdev);
7348
7349 if (state == pci_channel_io_perm_failure)
7350 return PCI_ERS_RESULT_DISCONNECT;
7351
7352 if (netif_running(netdev))
7353 igb_down(adapter);
7354 pci_disable_device(pdev);
7355
7356 /* Request a slot slot reset. */
7357 return PCI_ERS_RESULT_NEED_RESET;
7358 }
7359
7360 /**
7361 * igb_io_slot_reset - called after the pci bus has been reset.
7362 * @pdev: Pointer to PCI device
7363 *
7364 * Restart the card from scratch, as if from a cold-boot. Implementation
7365 * resembles the first-half of the igb_resume routine.
7366 **/
7367 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7368 {
7369 struct net_device *netdev = pci_get_drvdata(pdev);
7370 struct igb_adapter *adapter = netdev_priv(netdev);
7371 struct e1000_hw *hw = &adapter->hw;
7372 pci_ers_result_t result;
7373 int err;
7374
7375 if (pci_enable_device_mem(pdev)) {
7376 dev_err(&pdev->dev,
7377 "Cannot re-enable PCI device after reset.\n");
7378 result = PCI_ERS_RESULT_DISCONNECT;
7379 } else {
7380 pci_set_master(pdev);
7381 pci_restore_state(pdev);
7382 pci_save_state(pdev);
7383
7384 pci_enable_wake(pdev, PCI_D3hot, 0);
7385 pci_enable_wake(pdev, PCI_D3cold, 0);
7386
7387 igb_reset(adapter);
7388 wr32(E1000_WUS, ~0);
7389 result = PCI_ERS_RESULT_RECOVERED;
7390 }
7391
7392 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7393 if (err) {
7394 dev_err(&pdev->dev,
7395 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7396 err);
7397 /* non-fatal, continue */
7398 }
7399
7400 return result;
7401 }
7402
7403 /**
7404 * igb_io_resume - called when traffic can start flowing again.
7405 * @pdev: Pointer to PCI device
7406 *
7407 * This callback is called when the error recovery driver tells us that
7408 * its OK to resume normal operation. Implementation resembles the
7409 * second-half of the igb_resume routine.
7410 */
7411 static void igb_io_resume(struct pci_dev *pdev)
7412 {
7413 struct net_device *netdev = pci_get_drvdata(pdev);
7414 struct igb_adapter *adapter = netdev_priv(netdev);
7415
7416 if (netif_running(netdev)) {
7417 if (igb_up(adapter)) {
7418 dev_err(&pdev->dev, "igb_up failed after reset\n");
7419 return;
7420 }
7421 }
7422
7423 netif_device_attach(netdev);
7424
7425 /* let the f/w know that the h/w is now under the control of the
7426 * driver.
7427 */
7428 igb_get_hw_control(adapter);
7429 }
7430
7431 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7432 u8 qsel)
7433 {
7434 u32 rar_low, rar_high;
7435 struct e1000_hw *hw = &adapter->hw;
7436
7437 /* HW expects these in little endian so we reverse the byte order
7438 * from network order (big endian) to little endian
7439 */
7440 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7441 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7442 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7443
7444 /* Indicate to hardware the Address is Valid. */
7445 rar_high |= E1000_RAH_AV;
7446
7447 if (hw->mac.type == e1000_82575)
7448 rar_high |= E1000_RAH_POOL_1 * qsel;
7449 else
7450 rar_high |= E1000_RAH_POOL_1 << qsel;
7451
7452 wr32(E1000_RAL(index), rar_low);
7453 wrfl();
7454 wr32(E1000_RAH(index), rar_high);
7455 wrfl();
7456 }
7457
7458 static int igb_set_vf_mac(struct igb_adapter *adapter,
7459 int vf, unsigned char *mac_addr)
7460 {
7461 struct e1000_hw *hw = &adapter->hw;
7462 /* VF MAC addresses start at end of receive addresses and moves
7463 * towards the first, as a result a collision should not be possible
7464 */
7465 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7466
7467 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7468
7469 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7470
7471 return 0;
7472 }
7473
7474 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7475 {
7476 struct igb_adapter *adapter = netdev_priv(netdev);
7477 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7478 return -EINVAL;
7479 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7480 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7481 dev_info(&adapter->pdev->dev,
7482 "Reload the VF driver to make this change effective.");
7483 if (test_bit(__IGB_DOWN, &adapter->state)) {
7484 dev_warn(&adapter->pdev->dev,
7485 "The VF MAC address has been set, but the PF device is not up.\n");
7486 dev_warn(&adapter->pdev->dev,
7487 "Bring the PF device up before attempting to use the VF device.\n");
7488 }
7489 return igb_set_vf_mac(adapter, vf, mac);
7490 }
7491
7492 static int igb_link_mbps(int internal_link_speed)
7493 {
7494 switch (internal_link_speed) {
7495 case SPEED_100:
7496 return 100;
7497 case SPEED_1000:
7498 return 1000;
7499 default:
7500 return 0;
7501 }
7502 }
7503
7504 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7505 int link_speed)
7506 {
7507 int rf_dec, rf_int;
7508 u32 bcnrc_val;
7509
7510 if (tx_rate != 0) {
7511 /* Calculate the rate factor values to set */
7512 rf_int = link_speed / tx_rate;
7513 rf_dec = (link_speed - (rf_int * tx_rate));
7514 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7515 tx_rate;
7516
7517 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7518 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7519 E1000_RTTBCNRC_RF_INT_MASK);
7520 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7521 } else {
7522 bcnrc_val = 0;
7523 }
7524
7525 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7526 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7527 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7528 */
7529 wr32(E1000_RTTBCNRM, 0x14);
7530 wr32(E1000_RTTBCNRC, bcnrc_val);
7531 }
7532
7533 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7534 {
7535 int actual_link_speed, i;
7536 bool reset_rate = false;
7537
7538 /* VF TX rate limit was not set or not supported */
7539 if ((adapter->vf_rate_link_speed == 0) ||
7540 (adapter->hw.mac.type != e1000_82576))
7541 return;
7542
7543 actual_link_speed = igb_link_mbps(adapter->link_speed);
7544 if (actual_link_speed != adapter->vf_rate_link_speed) {
7545 reset_rate = true;
7546 adapter->vf_rate_link_speed = 0;
7547 dev_info(&adapter->pdev->dev,
7548 "Link speed has been changed. VF Transmit rate is disabled\n");
7549 }
7550
7551 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7552 if (reset_rate)
7553 adapter->vf_data[i].tx_rate = 0;
7554
7555 igb_set_vf_rate_limit(&adapter->hw, i,
7556 adapter->vf_data[i].tx_rate,
7557 actual_link_speed);
7558 }
7559 }
7560
7561 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7562 {
7563 struct igb_adapter *adapter = netdev_priv(netdev);
7564 struct e1000_hw *hw = &adapter->hw;
7565 int actual_link_speed;
7566
7567 if (hw->mac.type != e1000_82576)
7568 return -EOPNOTSUPP;
7569
7570 actual_link_speed = igb_link_mbps(adapter->link_speed);
7571 if ((vf >= adapter->vfs_allocated_count) ||
7572 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7573 (tx_rate < 0) || (tx_rate > actual_link_speed))
7574 return -EINVAL;
7575
7576 adapter->vf_rate_link_speed = actual_link_speed;
7577 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7578 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7579
7580 return 0;
7581 }
7582
7583 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7584 bool setting)
7585 {
7586 struct igb_adapter *adapter = netdev_priv(netdev);
7587 struct e1000_hw *hw = &adapter->hw;
7588 u32 reg_val, reg_offset;
7589
7590 if (!adapter->vfs_allocated_count)
7591 return -EOPNOTSUPP;
7592
7593 if (vf >= adapter->vfs_allocated_count)
7594 return -EINVAL;
7595
7596 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7597 reg_val = rd32(reg_offset);
7598 if (setting)
7599 reg_val |= ((1 << vf) |
7600 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7601 else
7602 reg_val &= ~((1 << vf) |
7603 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7604 wr32(reg_offset, reg_val);
7605
7606 adapter->vf_data[vf].spoofchk_enabled = setting;
7607 return E1000_SUCCESS;
7608 }
7609
7610 static int igb_ndo_get_vf_config(struct net_device *netdev,
7611 int vf, struct ifla_vf_info *ivi)
7612 {
7613 struct igb_adapter *adapter = netdev_priv(netdev);
7614 if (vf >= adapter->vfs_allocated_count)
7615 return -EINVAL;
7616 ivi->vf = vf;
7617 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7618 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7619 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7620 ivi->qos = adapter->vf_data[vf].pf_qos;
7621 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7622 return 0;
7623 }
7624
7625 static void igb_vmm_control(struct igb_adapter *adapter)
7626 {
7627 struct e1000_hw *hw = &adapter->hw;
7628 u32 reg;
7629
7630 switch (hw->mac.type) {
7631 case e1000_82575:
7632 case e1000_i210:
7633 case e1000_i211:
7634 case e1000_i354:
7635 default:
7636 /* replication is not supported for 82575 */
7637 return;
7638 case e1000_82576:
7639 /* notify HW that the MAC is adding vlan tags */
7640 reg = rd32(E1000_DTXCTL);
7641 reg |= E1000_DTXCTL_VLAN_ADDED;
7642 wr32(E1000_DTXCTL, reg);
7643 case e1000_82580:
7644 /* enable replication vlan tag stripping */
7645 reg = rd32(E1000_RPLOLR);
7646 reg |= E1000_RPLOLR_STRVLAN;
7647 wr32(E1000_RPLOLR, reg);
7648 case e1000_i350:
7649 /* none of the above registers are supported by i350 */
7650 break;
7651 }
7652
7653 if (adapter->vfs_allocated_count) {
7654 igb_vmdq_set_loopback_pf(hw, true);
7655 igb_vmdq_set_replication_pf(hw, true);
7656 igb_vmdq_set_anti_spoofing_pf(hw, true,
7657 adapter->vfs_allocated_count);
7658 } else {
7659 igb_vmdq_set_loopback_pf(hw, false);
7660 igb_vmdq_set_replication_pf(hw, false);
7661 }
7662 }
7663
7664 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7665 {
7666 struct e1000_hw *hw = &adapter->hw;
7667 u32 dmac_thr;
7668 u16 hwm;
7669
7670 if (hw->mac.type > e1000_82580) {
7671 if (adapter->flags & IGB_FLAG_DMAC) {
7672 u32 reg;
7673
7674 /* force threshold to 0. */
7675 wr32(E1000_DMCTXTH, 0);
7676
7677 /* DMA Coalescing high water mark needs to be greater
7678 * than the Rx threshold. Set hwm to PBA - max frame
7679 * size in 16B units, capping it at PBA - 6KB.
7680 */
7681 hwm = 64 * pba - adapter->max_frame_size / 16;
7682 if (hwm < 64 * (pba - 6))
7683 hwm = 64 * (pba - 6);
7684 reg = rd32(E1000_FCRTC);
7685 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7686 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7687 & E1000_FCRTC_RTH_COAL_MASK);
7688 wr32(E1000_FCRTC, reg);
7689
7690 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7691 * frame size, capping it at PBA - 10KB.
7692 */
7693 dmac_thr = pba - adapter->max_frame_size / 512;
7694 if (dmac_thr < pba - 10)
7695 dmac_thr = pba - 10;
7696 reg = rd32(E1000_DMACR);
7697 reg &= ~E1000_DMACR_DMACTHR_MASK;
7698 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7699 & E1000_DMACR_DMACTHR_MASK);
7700
7701 /* transition to L0x or L1 if available..*/
7702 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7703
7704 /* watchdog timer= +-1000 usec in 32usec intervals */
7705 reg |= (1000 >> 5);
7706
7707 /* Disable BMC-to-OS Watchdog Enable */
7708 if (hw->mac.type != e1000_i354)
7709 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7710
7711 wr32(E1000_DMACR, reg);
7712
7713 /* no lower threshold to disable
7714 * coalescing(smart fifb)-UTRESH=0
7715 */
7716 wr32(E1000_DMCRTRH, 0);
7717
7718 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7719
7720 wr32(E1000_DMCTLX, reg);
7721
7722 /* free space in tx packet buffer to wake from
7723 * DMA coal
7724 */
7725 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7726 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7727
7728 /* make low power state decision controlled
7729 * by DMA coal
7730 */
7731 reg = rd32(E1000_PCIEMISC);
7732 reg &= ~E1000_PCIEMISC_LX_DECISION;
7733 wr32(E1000_PCIEMISC, reg);
7734 } /* endif adapter->dmac is not disabled */
7735 } else if (hw->mac.type == e1000_82580) {
7736 u32 reg = rd32(E1000_PCIEMISC);
7737 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7738 wr32(E1000_DMACR, 0);
7739 }
7740 }
7741
7742 /**
7743 * igb_read_i2c_byte - Reads 8 bit word over I2C
7744 * @hw: pointer to hardware structure
7745 * @byte_offset: byte offset to read
7746 * @dev_addr: device address
7747 * @data: value read
7748 *
7749 * Performs byte read operation over I2C interface at
7750 * a specified device address.
7751 **/
7752 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7753 u8 dev_addr, u8 *data)
7754 {
7755 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7756 struct i2c_client *this_client = adapter->i2c_client;
7757 s32 status;
7758 u16 swfw_mask = 0;
7759
7760 if (!this_client)
7761 return E1000_ERR_I2C;
7762
7763 swfw_mask = E1000_SWFW_PHY0_SM;
7764
7765 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7766 != E1000_SUCCESS)
7767 return E1000_ERR_SWFW_SYNC;
7768
7769 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7770 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7771
7772 if (status < 0)
7773 return E1000_ERR_I2C;
7774 else {
7775 *data = status;
7776 return E1000_SUCCESS;
7777 }
7778 }
7779
7780 /**
7781 * igb_write_i2c_byte - Writes 8 bit word over I2C
7782 * @hw: pointer to hardware structure
7783 * @byte_offset: byte offset to write
7784 * @dev_addr: device address
7785 * @data: value to write
7786 *
7787 * Performs byte write operation over I2C interface at
7788 * a specified device address.
7789 **/
7790 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7791 u8 dev_addr, u8 data)
7792 {
7793 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7794 struct i2c_client *this_client = adapter->i2c_client;
7795 s32 status;
7796 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7797
7798 if (!this_client)
7799 return E1000_ERR_I2C;
7800
7801 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7802 return E1000_ERR_SWFW_SYNC;
7803 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7804 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7805
7806 if (status)
7807 return E1000_ERR_I2C;
7808 else
7809 return E1000_SUCCESS;
7810
7811 }
7812 /* igb_main.c */
Linux kernel - Deliverables
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