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igb: simplify and clean up igb_enable_mas()
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
57 #include "igb.h"
58
59 #define MAJ 5
60 #define MIN 2
61 #define BUILD 15
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71 static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73 };
74
75 static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 #endif
183
184 #ifdef CONFIG_PM
185 #ifdef CONFIG_PM_SLEEP
186 static int igb_suspend(struct device *);
187 #endif
188 static int igb_resume(struct device *);
189 static int igb_runtime_suspend(struct device *dev);
190 static int igb_runtime_resume(struct device *dev);
191 static int igb_runtime_idle(struct device *dev);
192 static const struct dev_pm_ops igb_pm_ops = {
193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
195 igb_runtime_idle)
196 };
197 #endif
198 static void igb_shutdown(struct pci_dev *);
199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
200 #ifdef CONFIG_IGB_DCA
201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202 static struct notifier_block dca_notifier = {
203 .notifier_call = igb_notify_dca,
204 .next = NULL,
205 .priority = 0
206 };
207 #endif
208 #ifdef CONFIG_NET_POLL_CONTROLLER
209 /* for netdump / net console */
210 static void igb_netpoll(struct net_device *);
211 #endif
212 #ifdef CONFIG_PCI_IOV
213 static unsigned int max_vfs;
214 module_param(max_vfs, uint, 0);
215 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
216 #endif /* CONFIG_PCI_IOV */
217
218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221 static void igb_io_resume(struct pci_dev *);
222
223 static const struct pci_error_handlers igb_err_handler = {
224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227 };
228
229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
230
231 static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
235 .remove = igb_remove,
236 #ifdef CONFIG_PM
237 .driver.pm = &igb_pm_ops,
238 #endif
239 .shutdown = igb_shutdown,
240 .sriov_configure = igb_pci_sriov_configure,
241 .err_handler = &igb_err_handler
242 };
243
244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246 MODULE_LICENSE("GPL");
247 MODULE_VERSION(DRV_VERSION);
248
249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250 static int debug = -1;
251 module_param(debug, int, 0);
252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
254 struct igb_reg_info {
255 u32 ofs;
256 char *name;
257 };
258
259 static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293 };
294
295 /* igb_regdump - register printout routine */
296 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297 {
298 int n = 0;
299 char rname[16];
300 u32 regs[8];
301
302 switch (reginfo->ofs) {
303 case E1000_RDLEN(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_RDLEN(n));
306 break;
307 case E1000_RDH(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDH(n));
310 break;
311 case E1000_RDT(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDT(n));
314 break;
315 case E1000_RXDCTL(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RXDCTL(n));
318 break;
319 case E1000_RDBAL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RDBAL(n));
322 break;
323 case E1000_RDBAH(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAH(n));
326 break;
327 case E1000_TDBAL(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAL(n));
330 break;
331 case E1000_TDBAH(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_TDBAH(n));
334 break;
335 case E1000_TDLEN(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDLEN(n));
338 break;
339 case E1000_TDH(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDH(n));
342 break;
343 case E1000_TDT(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDT(n));
346 break;
347 case E1000_TXDCTL(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TXDCTL(n));
350 break;
351 default:
352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
353 return;
354 }
355
356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 regs[2], regs[3]);
359 }
360
361 /* igb_dump - Print registers, Tx-rings and Rx-rings */
362 static void igb_dump(struct igb_adapter *adapter)
363 {
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
373 u16 i, n;
374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
381 pr_info("Device Name state trans_start last_rx\n");
382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
388 pr_info(" Register Name Value\n");
389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
400 for (n = 0; n < adapter->num_tx_queues; n++) {
401 struct igb_tx_buffer *buffer_info;
402 tx_ring = adapter->tx_ring[n];
403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
435
436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
437 const char *next_desc;
438 struct igb_tx_buffer *buffer_info;
439 tx_desc = IGB_TX_DESC(tx_ring, i);
440 buffer_info = &tx_ring->tx_buffer_info[i];
441 u0 = (struct my_u0 *)tx_desc;
442 if (i == tx_ring->next_to_use &&
443 i == tx_ring->next_to_clean)
444 next_desc = " NTC/U";
445 else if (i == tx_ring->next_to_use)
446 next_desc = " NTU";
447 else if (i == tx_ring->next_to_clean)
448 next_desc = " NTC";
449 else
450 next_desc = "";
451
452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
453 i, le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(buffer_info, dma),
456 dma_unmap_len(buffer_info, len),
457 buffer_info->next_to_watch,
458 (u64)buffer_info->time_stamp,
459 buffer_info->skb, next_desc);
460
461 if (netif_msg_pktdata(adapter) && buffer_info->skb)
462 print_hex_dump(KERN_INFO, "",
463 DUMP_PREFIX_ADDRESS,
464 16, 1, buffer_info->skb->data,
465 dma_unmap_len(buffer_info, len),
466 true);
467 }
468 }
469
470 /* Print RX Rings Summary */
471 rx_ring_summary:
472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
473 pr_info("Queue [NTU] [NTC]\n");
474 for (n = 0; n < adapter->num_rx_queues; n++) {
475 rx_ring = adapter->rx_ring[n];
476 pr_info(" %5d %5X %5X\n",
477 n, rx_ring->next_to_use, rx_ring->next_to_clean);
478 }
479
480 /* Print RX Rings */
481 if (!netif_msg_rx_status(adapter))
482 goto exit;
483
484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
485
486 /* Advanced Receive Descriptor (Read) Format
487 * 63 1 0
488 * +-----------------------------------------------------+
489 * 0 | Packet Buffer Address [63:1] |A0/NSE|
490 * +----------------------------------------------+------+
491 * 8 | Header Buffer Address [63:1] | DD |
492 * +-----------------------------------------------------+
493 *
494 *
495 * Advanced Receive Descriptor (Write-Back) Format
496 *
497 * 63 48 47 32 31 30 21 20 17 16 4 3 0
498 * +------------------------------------------------------+
499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
500 * | Checksum Ident | | | | Type | Type |
501 * +------------------------------------------------------+
502 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 * +------------------------------------------------------+
504 * 63 48 47 32 31 20 19 0
505 */
506
507 for (n = 0; n < adapter->num_rx_queues; n++) {
508 rx_ring = adapter->rx_ring[n];
509 pr_info("------------------------------------\n");
510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
511 pr_info("------------------------------------\n");
512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
514
515 for (i = 0; i < rx_ring->count; i++) {
516 const char *next_desc;
517 struct igb_rx_buffer *buffer_info;
518 buffer_info = &rx_ring->rx_buffer_info[i];
519 rx_desc = IGB_RX_DESC(rx_ring, i);
520 u0 = (struct my_u0 *)rx_desc;
521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
522
523 if (i == rx_ring->next_to_use)
524 next_desc = " NTU";
525 else if (i == rx_ring->next_to_clean)
526 next_desc = " NTC";
527 else
528 next_desc = "";
529
530 if (staterr & E1000_RXD_STAT_DD) {
531 /* Descriptor Done */
532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
533 "RWB", i,
534 le64_to_cpu(u0->a),
535 le64_to_cpu(u0->b),
536 next_desc);
537 } else {
538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
539 "R ", i,
540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
542 (u64)buffer_info->dma,
543 next_desc);
544
545 if (netif_msg_pktdata(adapter) &&
546 buffer_info->dma && buffer_info->page) {
547 print_hex_dump(KERN_INFO, "",
548 DUMP_PREFIX_ADDRESS,
549 16, 1,
550 page_address(buffer_info->page) +
551 buffer_info->page_offset,
552 IGB_RX_BUFSZ, true);
553 }
554 }
555 }
556 }
557
558 exit:
559 return;
560 }
561
562 /**
563 * igb_get_i2c_data - Reads the I2C SDA data bit
564 * @hw: pointer to hardware structure
565 * @i2cctl: Current value of I2CCTL register
566 *
567 * Returns the I2C data bit value
568 **/
569 static int igb_get_i2c_data(void *data)
570 {
571 struct igb_adapter *adapter = (struct igb_adapter *)data;
572 struct e1000_hw *hw = &adapter->hw;
573 s32 i2cctl = rd32(E1000_I2CPARAMS);
574
575 return !!(i2cctl & E1000_I2C_DATA_IN);
576 }
577
578 /**
579 * igb_set_i2c_data - Sets the I2C data bit
580 * @data: pointer to hardware structure
581 * @state: I2C data value (0 or 1) to set
582 *
583 * Sets the I2C data bit
584 **/
585 static void igb_set_i2c_data(void *data, int state)
586 {
587 struct igb_adapter *adapter = (struct igb_adapter *)data;
588 struct e1000_hw *hw = &adapter->hw;
589 s32 i2cctl = rd32(E1000_I2CPARAMS);
590
591 if (state)
592 i2cctl |= E1000_I2C_DATA_OUT;
593 else
594 i2cctl &= ~E1000_I2C_DATA_OUT;
595
596 i2cctl &= ~E1000_I2C_DATA_OE_N;
597 i2cctl |= E1000_I2C_CLK_OE_N;
598 wr32(E1000_I2CPARAMS, i2cctl);
599 wrfl();
600
601 }
602
603 /**
604 * igb_set_i2c_clk - Sets the I2C SCL clock
605 * @data: pointer to hardware structure
606 * @state: state to set clock
607 *
608 * Sets the I2C clock line to state
609 **/
610 static void igb_set_i2c_clk(void *data, int state)
611 {
612 struct igb_adapter *adapter = (struct igb_adapter *)data;
613 struct e1000_hw *hw = &adapter->hw;
614 s32 i2cctl = rd32(E1000_I2CPARAMS);
615
616 if (state) {
617 i2cctl |= E1000_I2C_CLK_OUT;
618 i2cctl &= ~E1000_I2C_CLK_OE_N;
619 } else {
620 i2cctl &= ~E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 }
623 wr32(E1000_I2CPARAMS, i2cctl);
624 wrfl();
625 }
626
627 /**
628 * igb_get_i2c_clk - Gets the I2C SCL clock state
629 * @data: pointer to hardware structure
630 *
631 * Gets the I2C clock state
632 **/
633 static int igb_get_i2c_clk(void *data)
634 {
635 struct igb_adapter *adapter = (struct igb_adapter *)data;
636 struct e1000_hw *hw = &adapter->hw;
637 s32 i2cctl = rd32(E1000_I2CPARAMS);
638
639 return !!(i2cctl & E1000_I2C_CLK_IN);
640 }
641
642 static const struct i2c_algo_bit_data igb_i2c_algo = {
643 .setsda = igb_set_i2c_data,
644 .setscl = igb_set_i2c_clk,
645 .getsda = igb_get_i2c_data,
646 .getscl = igb_get_i2c_clk,
647 .udelay = 5,
648 .timeout = 20,
649 };
650
651 /**
652 * igb_get_hw_dev - return device
653 * @hw: pointer to hardware structure
654 *
655 * used by hardware layer to print debugging information
656 **/
657 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
658 {
659 struct igb_adapter *adapter = hw->back;
660 return adapter->netdev;
661 }
662
663 /**
664 * igb_init_module - Driver Registration Routine
665 *
666 * igb_init_module is the first routine called when the driver is
667 * loaded. All it does is register with the PCI subsystem.
668 **/
669 static int __init igb_init_module(void)
670 {
671 int ret;
672
673 pr_info("%s - version %s\n",
674 igb_driver_string, igb_driver_version);
675 pr_info("%s\n", igb_copyright);
676
677 #ifdef CONFIG_IGB_DCA
678 dca_register_notify(&dca_notifier);
679 #endif
680 ret = pci_register_driver(&igb_driver);
681 return ret;
682 }
683
684 module_init(igb_init_module);
685
686 /**
687 * igb_exit_module - Driver Exit Cleanup Routine
688 *
689 * igb_exit_module is called just before the driver is removed
690 * from memory.
691 **/
692 static void __exit igb_exit_module(void)
693 {
694 #ifdef CONFIG_IGB_DCA
695 dca_unregister_notify(&dca_notifier);
696 #endif
697 pci_unregister_driver(&igb_driver);
698 }
699
700 module_exit(igb_exit_module);
701
702 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703 /**
704 * igb_cache_ring_register - Descriptor ring to register mapping
705 * @adapter: board private structure to initialize
706 *
707 * Once we know the feature-set enabled for the device, we'll cache
708 * the register offset the descriptor ring is assigned to.
709 **/
710 static void igb_cache_ring_register(struct igb_adapter *adapter)
711 {
712 int i = 0, j = 0;
713 u32 rbase_offset = adapter->vfs_allocated_count;
714
715 switch (adapter->hw.mac.type) {
716 case e1000_82576:
717 /* The queues are allocated for virtualization such that VF 0
718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 * In order to avoid collision we start at the first free queue
720 * and continue consuming queues in the same sequence
721 */
722 if (adapter->vfs_allocated_count) {
723 for (; i < adapter->rss_queues; i++)
724 adapter->rx_ring[i]->reg_idx = rbase_offset +
725 Q_IDX_82576(i);
726 }
727 /* Fall through */
728 case e1000_82575:
729 case e1000_82580:
730 case e1000_i350:
731 case e1000_i354:
732 case e1000_i210:
733 case e1000_i211:
734 /* Fall through */
735 default:
736 for (; i < adapter->num_rx_queues; i++)
737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
738 for (; j < adapter->num_tx_queues; j++)
739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
740 break;
741 }
742 }
743
744 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
745 {
746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
748 u32 value = 0;
749
750 if (E1000_REMOVED(hw_addr))
751 return ~value;
752
753 value = readl(&hw_addr[reg]);
754
755 /* reads should not return all F's */
756 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
757 struct net_device *netdev = igb->netdev;
758 hw->hw_addr = NULL;
759 netif_device_detach(netdev);
760 netdev_err(netdev, "PCIe link lost, device now detached\n");
761 }
762
763 return value;
764 }
765
766 /**
767 * igb_write_ivar - configure ivar for given MSI-X vector
768 * @hw: pointer to the HW structure
769 * @msix_vector: vector number we are allocating to a given ring
770 * @index: row index of IVAR register to write within IVAR table
771 * @offset: column offset of in IVAR, should be multiple of 8
772 *
773 * This function is intended to handle the writing of the IVAR register
774 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
775 * each containing an cause allocation for an Rx and Tx ring, and a
776 * variable number of rows depending on the number of queues supported.
777 **/
778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
779 int index, int offset)
780 {
781 u32 ivar = array_rd32(E1000_IVAR0, index);
782
783 /* clear any bits that are currently set */
784 ivar &= ~((u32)0xFF << offset);
785
786 /* write vector and valid bit */
787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
788
789 array_wr32(E1000_IVAR0, index, ivar);
790 }
791
792 #define IGB_N0_QUEUE -1
793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
794 {
795 struct igb_adapter *adapter = q_vector->adapter;
796 struct e1000_hw *hw = &adapter->hw;
797 int rx_queue = IGB_N0_QUEUE;
798 int tx_queue = IGB_N0_QUEUE;
799 u32 msixbm = 0;
800
801 if (q_vector->rx.ring)
802 rx_queue = q_vector->rx.ring->reg_idx;
803 if (q_vector->tx.ring)
804 tx_queue = q_vector->tx.ring->reg_idx;
805
806 switch (hw->mac.type) {
807 case e1000_82575:
808 /* The 82575 assigns vectors using a bitmask, which matches the
809 * bitmask for the EICR/EIMS/EIMC registers. To assign one
810 * or more queues to a vector, we write the appropriate bits
811 * into the MSIXBM register for that vector.
812 */
813 if (rx_queue > IGB_N0_QUEUE)
814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
815 if (tx_queue > IGB_N0_QUEUE)
816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
818 msixbm |= E1000_EIMS_OTHER;
819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
820 q_vector->eims_value = msixbm;
821 break;
822 case e1000_82576:
823 /* 82576 uses a table that essentially consists of 2 columns
824 * with 8 rows. The ordering is column-major so we use the
825 * lower 3 bits as the row index, and the 4th bit as the
826 * column offset.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue & 0x7,
831 (rx_queue & 0x8) << 1);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue & 0x7,
835 ((tx_queue & 0x8) << 1) + 8);
836 q_vector->eims_value = 1 << msix_vector;
837 break;
838 case e1000_82580:
839 case e1000_i350:
840 case e1000_i354:
841 case e1000_i210:
842 case e1000_i211:
843 /* On 82580 and newer adapters the scheme is similar to 82576
844 * however instead of ordering column-major we have things
845 * ordered row-major. So we traverse the table by using
846 * bit 0 as the column offset, and the remaining bits as the
847 * row index.
848 */
849 if (rx_queue > IGB_N0_QUEUE)
850 igb_write_ivar(hw, msix_vector,
851 rx_queue >> 1,
852 (rx_queue & 0x1) << 4);
853 if (tx_queue > IGB_N0_QUEUE)
854 igb_write_ivar(hw, msix_vector,
855 tx_queue >> 1,
856 ((tx_queue & 0x1) << 4) + 8);
857 q_vector->eims_value = 1 << msix_vector;
858 break;
859 default:
860 BUG();
861 break;
862 }
863
864 /* add q_vector eims value to global eims_enable_mask */
865 adapter->eims_enable_mask |= q_vector->eims_value;
866
867 /* configure q_vector to set itr on first interrupt */
868 q_vector->set_itr = 1;
869 }
870
871 /**
872 * igb_configure_msix - Configure MSI-X hardware
873 * @adapter: board private structure to initialize
874 *
875 * igb_configure_msix sets up the hardware to properly
876 * generate MSI-X interrupts.
877 **/
878 static void igb_configure_msix(struct igb_adapter *adapter)
879 {
880 u32 tmp;
881 int i, vector = 0;
882 struct e1000_hw *hw = &adapter->hw;
883
884 adapter->eims_enable_mask = 0;
885
886 /* set vector for other causes, i.e. link changes */
887 switch (hw->mac.type) {
888 case e1000_82575:
889 tmp = rd32(E1000_CTRL_EXT);
890 /* enable MSI-X PBA support*/
891 tmp |= E1000_CTRL_EXT_PBA_CLR;
892
893 /* Auto-Mask interrupts upon ICR read. */
894 tmp |= E1000_CTRL_EXT_EIAME;
895 tmp |= E1000_CTRL_EXT_IRCA;
896
897 wr32(E1000_CTRL_EXT, tmp);
898
899 /* enable msix_other interrupt */
900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
901 adapter->eims_other = E1000_EIMS_OTHER;
902
903 break;
904
905 case e1000_82576:
906 case e1000_82580:
907 case e1000_i350:
908 case e1000_i354:
909 case e1000_i210:
910 case e1000_i211:
911 /* Turn on MSI-X capability first, or our settings
912 * won't stick. And it will take days to debug.
913 */
914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
915 E1000_GPIE_PBA | E1000_GPIE_EIAME |
916 E1000_GPIE_NSICR);
917
918 /* enable msix_other interrupt */
919 adapter->eims_other = 1 << vector;
920 tmp = (vector++ | E1000_IVAR_VALID) << 8;
921
922 wr32(E1000_IVAR_MISC, tmp);
923 break;
924 default:
925 /* do nothing, since nothing else supports MSI-X */
926 break;
927 } /* switch (hw->mac.type) */
928
929 adapter->eims_enable_mask |= adapter->eims_other;
930
931 for (i = 0; i < adapter->num_q_vectors; i++)
932 igb_assign_vector(adapter->q_vector[i], vector++);
933
934 wrfl();
935 }
936
937 /**
938 * igb_request_msix - Initialize MSI-X interrupts
939 * @adapter: board private structure to initialize
940 *
941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
942 * kernel.
943 **/
944 static int igb_request_msix(struct igb_adapter *adapter)
945 {
946 struct net_device *netdev = adapter->netdev;
947 struct e1000_hw *hw = &adapter->hw;
948 int i, err = 0, vector = 0, free_vector = 0;
949
950 err = request_irq(adapter->msix_entries[vector].vector,
951 igb_msix_other, 0, netdev->name, adapter);
952 if (err)
953 goto err_out;
954
955 for (i = 0; i < adapter->num_q_vectors; i++) {
956 struct igb_q_vector *q_vector = adapter->q_vector[i];
957
958 vector++;
959
960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
961
962 if (q_vector->rx.ring && q_vector->tx.ring)
963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
964 q_vector->rx.ring->queue_index);
965 else if (q_vector->tx.ring)
966 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
967 q_vector->tx.ring->queue_index);
968 else if (q_vector->rx.ring)
969 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
970 q_vector->rx.ring->queue_index);
971 else
972 sprintf(q_vector->name, "%s-unused", netdev->name);
973
974 err = request_irq(adapter->msix_entries[vector].vector,
975 igb_msix_ring, 0, q_vector->name,
976 q_vector);
977 if (err)
978 goto err_free;
979 }
980
981 igb_configure_msix(adapter);
982 return 0;
983
984 err_free:
985 /* free already assigned IRQs */
986 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
987
988 vector--;
989 for (i = 0; i < vector; i++) {
990 free_irq(adapter->msix_entries[free_vector++].vector,
991 adapter->q_vector[i]);
992 }
993 err_out:
994 return err;
995 }
996
997 /**
998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
1001 *
1002 * This function frees the memory allocated to the q_vector.
1003 **/
1004 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005 {
1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007
1008 adapter->q_vector[v_idx] = NULL;
1009
1010 /* igb_get_stats64() might access the rings on this vector,
1011 * we must wait a grace period before freeing it.
1012 */
1013 if (q_vector)
1014 kfree_rcu(q_vector, rcu);
1015 }
1016
1017 /**
1018 * igb_reset_q_vector - Reset config for interrupt vector
1019 * @adapter: board private structure to initialize
1020 * @v_idx: Index of vector to be reset
1021 *
1022 * If NAPI is enabled it will delete any references to the
1023 * NAPI struct. This is preparation for igb_free_q_vector.
1024 **/
1025 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1026 {
1027 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1028
1029 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1030 * allocated. So, q_vector is NULL so we should stop here.
1031 */
1032 if (!q_vector)
1033 return;
1034
1035 if (q_vector->tx.ring)
1036 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1037
1038 if (q_vector->rx.ring)
1039 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1040
1041 netif_napi_del(&q_vector->napi);
1042
1043 }
1044
1045 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1046 {
1047 int v_idx = adapter->num_q_vectors;
1048
1049 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1050 pci_disable_msix(adapter->pdev);
1051 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1052 pci_disable_msi(adapter->pdev);
1053
1054 while (v_idx--)
1055 igb_reset_q_vector(adapter, v_idx);
1056 }
1057
1058 /**
1059 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1060 * @adapter: board private structure to initialize
1061 *
1062 * This function frees the memory allocated to the q_vectors. In addition if
1063 * NAPI is enabled it will delete any references to the NAPI struct prior
1064 * to freeing the q_vector.
1065 **/
1066 static void igb_free_q_vectors(struct igb_adapter *adapter)
1067 {
1068 int v_idx = adapter->num_q_vectors;
1069
1070 adapter->num_tx_queues = 0;
1071 adapter->num_rx_queues = 0;
1072 adapter->num_q_vectors = 0;
1073
1074 while (v_idx--) {
1075 igb_reset_q_vector(adapter, v_idx);
1076 igb_free_q_vector(adapter, v_idx);
1077 }
1078 }
1079
1080 /**
1081 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1082 * @adapter: board private structure to initialize
1083 *
1084 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1085 * MSI-X interrupts allocated.
1086 */
1087 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1088 {
1089 igb_free_q_vectors(adapter);
1090 igb_reset_interrupt_capability(adapter);
1091 }
1092
1093 /**
1094 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1095 * @adapter: board private structure to initialize
1096 * @msix: boolean value of MSIX capability
1097 *
1098 * Attempt to configure interrupts using the best available
1099 * capabilities of the hardware and kernel.
1100 **/
1101 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1102 {
1103 int err;
1104 int numvecs, i;
1105
1106 if (!msix)
1107 goto msi_only;
1108 adapter->flags |= IGB_FLAG_HAS_MSIX;
1109
1110 /* Number of supported queues. */
1111 adapter->num_rx_queues = adapter->rss_queues;
1112 if (adapter->vfs_allocated_count)
1113 adapter->num_tx_queues = 1;
1114 else
1115 adapter->num_tx_queues = adapter->rss_queues;
1116
1117 /* start with one vector for every Rx queue */
1118 numvecs = adapter->num_rx_queues;
1119
1120 /* if Tx handler is separate add 1 for every Tx queue */
1121 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1122 numvecs += adapter->num_tx_queues;
1123
1124 /* store the number of vectors reserved for queues */
1125 adapter->num_q_vectors = numvecs;
1126
1127 /* add 1 vector for link status interrupts */
1128 numvecs++;
1129 for (i = 0; i < numvecs; i++)
1130 adapter->msix_entries[i].entry = i;
1131
1132 err = pci_enable_msix_range(adapter->pdev,
1133 adapter->msix_entries,
1134 numvecs,
1135 numvecs);
1136 if (err > 0)
1137 return;
1138
1139 igb_reset_interrupt_capability(adapter);
1140
1141 /* If we can't do MSI-X, try MSI */
1142 msi_only:
1143 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1144 #ifdef CONFIG_PCI_IOV
1145 /* disable SR-IOV for non MSI-X configurations */
1146 if (adapter->vf_data) {
1147 struct e1000_hw *hw = &adapter->hw;
1148 /* disable iov and allow time for transactions to clear */
1149 pci_disable_sriov(adapter->pdev);
1150 msleep(500);
1151
1152 kfree(adapter->vf_data);
1153 adapter->vf_data = NULL;
1154 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1155 wrfl();
1156 msleep(100);
1157 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1158 }
1159 #endif
1160 adapter->vfs_allocated_count = 0;
1161 adapter->rss_queues = 1;
1162 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1163 adapter->num_rx_queues = 1;
1164 adapter->num_tx_queues = 1;
1165 adapter->num_q_vectors = 1;
1166 if (!pci_enable_msi(adapter->pdev))
1167 adapter->flags |= IGB_FLAG_HAS_MSI;
1168 }
1169
1170 static void igb_add_ring(struct igb_ring *ring,
1171 struct igb_ring_container *head)
1172 {
1173 head->ring = ring;
1174 head->count++;
1175 }
1176
1177 /**
1178 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1179 * @adapter: board private structure to initialize
1180 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1181 * @v_idx: index of vector in adapter struct
1182 * @txr_count: total number of Tx rings to allocate
1183 * @txr_idx: index of first Tx ring to allocate
1184 * @rxr_count: total number of Rx rings to allocate
1185 * @rxr_idx: index of first Rx ring to allocate
1186 *
1187 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1188 **/
1189 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1190 int v_count, int v_idx,
1191 int txr_count, int txr_idx,
1192 int rxr_count, int rxr_idx)
1193 {
1194 struct igb_q_vector *q_vector;
1195 struct igb_ring *ring;
1196 int ring_count, size;
1197
1198 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1199 if (txr_count > 1 || rxr_count > 1)
1200 return -ENOMEM;
1201
1202 ring_count = txr_count + rxr_count;
1203 size = sizeof(struct igb_q_vector) +
1204 (sizeof(struct igb_ring) * ring_count);
1205
1206 /* allocate q_vector and rings */
1207 q_vector = adapter->q_vector[v_idx];
1208 if (!q_vector)
1209 q_vector = kzalloc(size, GFP_KERNEL);
1210 if (!q_vector)
1211 return -ENOMEM;
1212
1213 /* initialize NAPI */
1214 netif_napi_add(adapter->netdev, &q_vector->napi,
1215 igb_poll, 64);
1216
1217 /* tie q_vector and adapter together */
1218 adapter->q_vector[v_idx] = q_vector;
1219 q_vector->adapter = adapter;
1220
1221 /* initialize work limits */
1222 q_vector->tx.work_limit = adapter->tx_work_limit;
1223
1224 /* initialize ITR configuration */
1225 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1226 q_vector->itr_val = IGB_START_ITR;
1227
1228 /* initialize pointer to rings */
1229 ring = q_vector->ring;
1230
1231 /* intialize ITR */
1232 if (rxr_count) {
1233 /* rx or rx/tx vector */
1234 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1235 q_vector->itr_val = adapter->rx_itr_setting;
1236 } else {
1237 /* tx only vector */
1238 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1239 q_vector->itr_val = adapter->tx_itr_setting;
1240 }
1241
1242 if (txr_count) {
1243 /* assign generic ring traits */
1244 ring->dev = &adapter->pdev->dev;
1245 ring->netdev = adapter->netdev;
1246
1247 /* configure backlink on ring */
1248 ring->q_vector = q_vector;
1249
1250 /* update q_vector Tx values */
1251 igb_add_ring(ring, &q_vector->tx);
1252
1253 /* For 82575, context index must be unique per ring. */
1254 if (adapter->hw.mac.type == e1000_82575)
1255 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1256
1257 /* apply Tx specific ring traits */
1258 ring->count = adapter->tx_ring_count;
1259 ring->queue_index = txr_idx;
1260
1261 u64_stats_init(&ring->tx_syncp);
1262 u64_stats_init(&ring->tx_syncp2);
1263
1264 /* assign ring to adapter */
1265 adapter->tx_ring[txr_idx] = ring;
1266
1267 /* push pointer to next ring */
1268 ring++;
1269 }
1270
1271 if (rxr_count) {
1272 /* assign generic ring traits */
1273 ring->dev = &adapter->pdev->dev;
1274 ring->netdev = adapter->netdev;
1275
1276 /* configure backlink on ring */
1277 ring->q_vector = q_vector;
1278
1279 /* update q_vector Rx values */
1280 igb_add_ring(ring, &q_vector->rx);
1281
1282 /* set flag indicating ring supports SCTP checksum offload */
1283 if (adapter->hw.mac.type >= e1000_82576)
1284 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1285
1286 /* On i350, i354, i210, and i211, loopback VLAN packets
1287 * have the tag byte-swapped.
1288 */
1289 if (adapter->hw.mac.type >= e1000_i350)
1290 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1291
1292 /* apply Rx specific ring traits */
1293 ring->count = adapter->rx_ring_count;
1294 ring->queue_index = rxr_idx;
1295
1296 u64_stats_init(&ring->rx_syncp);
1297
1298 /* assign ring to adapter */
1299 adapter->rx_ring[rxr_idx] = ring;
1300 }
1301
1302 return 0;
1303 }
1304
1305
1306 /**
1307 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1308 * @adapter: board private structure to initialize
1309 *
1310 * We allocate one q_vector per queue interrupt. If allocation fails we
1311 * return -ENOMEM.
1312 **/
1313 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1314 {
1315 int q_vectors = adapter->num_q_vectors;
1316 int rxr_remaining = adapter->num_rx_queues;
1317 int txr_remaining = adapter->num_tx_queues;
1318 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1319 int err;
1320
1321 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1322 for (; rxr_remaining; v_idx++) {
1323 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1324 0, 0, 1, rxr_idx);
1325
1326 if (err)
1327 goto err_out;
1328
1329 /* update counts and index */
1330 rxr_remaining--;
1331 rxr_idx++;
1332 }
1333 }
1334
1335 for (; v_idx < q_vectors; v_idx++) {
1336 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1337 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1338
1339 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1340 tqpv, txr_idx, rqpv, rxr_idx);
1341
1342 if (err)
1343 goto err_out;
1344
1345 /* update counts and index */
1346 rxr_remaining -= rqpv;
1347 txr_remaining -= tqpv;
1348 rxr_idx++;
1349 txr_idx++;
1350 }
1351
1352 return 0;
1353
1354 err_out:
1355 adapter->num_tx_queues = 0;
1356 adapter->num_rx_queues = 0;
1357 adapter->num_q_vectors = 0;
1358
1359 while (v_idx--)
1360 igb_free_q_vector(adapter, v_idx);
1361
1362 return -ENOMEM;
1363 }
1364
1365 /**
1366 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1367 * @adapter: board private structure to initialize
1368 * @msix: boolean value of MSIX capability
1369 *
1370 * This function initializes the interrupts and allocates all of the queues.
1371 **/
1372 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1373 {
1374 struct pci_dev *pdev = adapter->pdev;
1375 int err;
1376
1377 igb_set_interrupt_capability(adapter, msix);
1378
1379 err = igb_alloc_q_vectors(adapter);
1380 if (err) {
1381 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1382 goto err_alloc_q_vectors;
1383 }
1384
1385 igb_cache_ring_register(adapter);
1386
1387 return 0;
1388
1389 err_alloc_q_vectors:
1390 igb_reset_interrupt_capability(adapter);
1391 return err;
1392 }
1393
1394 /**
1395 * igb_request_irq - initialize interrupts
1396 * @adapter: board private structure to initialize
1397 *
1398 * Attempts to configure interrupts using the best available
1399 * capabilities of the hardware and kernel.
1400 **/
1401 static int igb_request_irq(struct igb_adapter *adapter)
1402 {
1403 struct net_device *netdev = adapter->netdev;
1404 struct pci_dev *pdev = adapter->pdev;
1405 int err = 0;
1406
1407 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1408 err = igb_request_msix(adapter);
1409 if (!err)
1410 goto request_done;
1411 /* fall back to MSI */
1412 igb_free_all_tx_resources(adapter);
1413 igb_free_all_rx_resources(adapter);
1414
1415 igb_clear_interrupt_scheme(adapter);
1416 err = igb_init_interrupt_scheme(adapter, false);
1417 if (err)
1418 goto request_done;
1419
1420 igb_setup_all_tx_resources(adapter);
1421 igb_setup_all_rx_resources(adapter);
1422 igb_configure(adapter);
1423 }
1424
1425 igb_assign_vector(adapter->q_vector[0], 0);
1426
1427 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1428 err = request_irq(pdev->irq, igb_intr_msi, 0,
1429 netdev->name, adapter);
1430 if (!err)
1431 goto request_done;
1432
1433 /* fall back to legacy interrupts */
1434 igb_reset_interrupt_capability(adapter);
1435 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1436 }
1437
1438 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1439 netdev->name, adapter);
1440
1441 if (err)
1442 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1443 err);
1444
1445 request_done:
1446 return err;
1447 }
1448
1449 static void igb_free_irq(struct igb_adapter *adapter)
1450 {
1451 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1452 int vector = 0, i;
1453
1454 free_irq(adapter->msix_entries[vector++].vector, adapter);
1455
1456 for (i = 0; i < adapter->num_q_vectors; i++)
1457 free_irq(adapter->msix_entries[vector++].vector,
1458 adapter->q_vector[i]);
1459 } else {
1460 free_irq(adapter->pdev->irq, adapter);
1461 }
1462 }
1463
1464 /**
1465 * igb_irq_disable - Mask off interrupt generation on the NIC
1466 * @adapter: board private structure
1467 **/
1468 static void igb_irq_disable(struct igb_adapter *adapter)
1469 {
1470 struct e1000_hw *hw = &adapter->hw;
1471
1472 /* we need to be careful when disabling interrupts. The VFs are also
1473 * mapped into these registers and so clearing the bits can cause
1474 * issues on the VF drivers so we only need to clear what we set
1475 */
1476 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1477 u32 regval = rd32(E1000_EIAM);
1478
1479 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1480 wr32(E1000_EIMC, adapter->eims_enable_mask);
1481 regval = rd32(E1000_EIAC);
1482 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1483 }
1484
1485 wr32(E1000_IAM, 0);
1486 wr32(E1000_IMC, ~0);
1487 wrfl();
1488 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1489 int i;
1490
1491 for (i = 0; i < adapter->num_q_vectors; i++)
1492 synchronize_irq(adapter->msix_entries[i].vector);
1493 } else {
1494 synchronize_irq(adapter->pdev->irq);
1495 }
1496 }
1497
1498 /**
1499 * igb_irq_enable - Enable default interrupt generation settings
1500 * @adapter: board private structure
1501 **/
1502 static void igb_irq_enable(struct igb_adapter *adapter)
1503 {
1504 struct e1000_hw *hw = &adapter->hw;
1505
1506 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1507 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1508 u32 regval = rd32(E1000_EIAC);
1509
1510 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1511 regval = rd32(E1000_EIAM);
1512 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1513 wr32(E1000_EIMS, adapter->eims_enable_mask);
1514 if (adapter->vfs_allocated_count) {
1515 wr32(E1000_MBVFIMR, 0xFF);
1516 ims |= E1000_IMS_VMMB;
1517 }
1518 wr32(E1000_IMS, ims);
1519 } else {
1520 wr32(E1000_IMS, IMS_ENABLE_MASK |
1521 E1000_IMS_DRSTA);
1522 wr32(E1000_IAM, IMS_ENABLE_MASK |
1523 E1000_IMS_DRSTA);
1524 }
1525 }
1526
1527 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1528 {
1529 struct e1000_hw *hw = &adapter->hw;
1530 u16 vid = adapter->hw.mng_cookie.vlan_id;
1531 u16 old_vid = adapter->mng_vlan_id;
1532
1533 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1534 /* add VID to filter table */
1535 igb_vfta_set(hw, vid, true);
1536 adapter->mng_vlan_id = vid;
1537 } else {
1538 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1539 }
1540
1541 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1542 (vid != old_vid) &&
1543 !test_bit(old_vid, adapter->active_vlans)) {
1544 /* remove VID from filter table */
1545 igb_vfta_set(hw, old_vid, false);
1546 }
1547 }
1548
1549 /**
1550 * igb_release_hw_control - release control of the h/w to f/w
1551 * @adapter: address of board private structure
1552 *
1553 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1554 * For ASF and Pass Through versions of f/w this means that the
1555 * driver is no longer loaded.
1556 **/
1557 static void igb_release_hw_control(struct igb_adapter *adapter)
1558 {
1559 struct e1000_hw *hw = &adapter->hw;
1560 u32 ctrl_ext;
1561
1562 /* Let firmware take over control of h/w */
1563 ctrl_ext = rd32(E1000_CTRL_EXT);
1564 wr32(E1000_CTRL_EXT,
1565 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1566 }
1567
1568 /**
1569 * igb_get_hw_control - get control of the h/w from f/w
1570 * @adapter: address of board private structure
1571 *
1572 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1573 * For ASF and Pass Through versions of f/w this means that
1574 * the driver is loaded.
1575 **/
1576 static void igb_get_hw_control(struct igb_adapter *adapter)
1577 {
1578 struct e1000_hw *hw = &adapter->hw;
1579 u32 ctrl_ext;
1580
1581 /* Let firmware know the driver has taken over */
1582 ctrl_ext = rd32(E1000_CTRL_EXT);
1583 wr32(E1000_CTRL_EXT,
1584 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1585 }
1586
1587 /**
1588 * igb_configure - configure the hardware for RX and TX
1589 * @adapter: private board structure
1590 **/
1591 static void igb_configure(struct igb_adapter *adapter)
1592 {
1593 struct net_device *netdev = adapter->netdev;
1594 int i;
1595
1596 igb_get_hw_control(adapter);
1597 igb_set_rx_mode(netdev);
1598
1599 igb_restore_vlan(adapter);
1600
1601 igb_setup_tctl(adapter);
1602 igb_setup_mrqc(adapter);
1603 igb_setup_rctl(adapter);
1604
1605 igb_configure_tx(adapter);
1606 igb_configure_rx(adapter);
1607
1608 igb_rx_fifo_flush_82575(&adapter->hw);
1609
1610 /* call igb_desc_unused which always leaves
1611 * at least 1 descriptor unused to make sure
1612 * next_to_use != next_to_clean
1613 */
1614 for (i = 0; i < adapter->num_rx_queues; i++) {
1615 struct igb_ring *ring = adapter->rx_ring[i];
1616 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1617 }
1618 }
1619
1620 /**
1621 * igb_power_up_link - Power up the phy/serdes link
1622 * @adapter: address of board private structure
1623 **/
1624 void igb_power_up_link(struct igb_adapter *adapter)
1625 {
1626 igb_reset_phy(&adapter->hw);
1627
1628 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1629 igb_power_up_phy_copper(&adapter->hw);
1630 else
1631 igb_power_up_serdes_link_82575(&adapter->hw);
1632
1633 igb_setup_link(&adapter->hw);
1634 }
1635
1636 /**
1637 * igb_power_down_link - Power down the phy/serdes link
1638 * @adapter: address of board private structure
1639 */
1640 static void igb_power_down_link(struct igb_adapter *adapter)
1641 {
1642 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1643 igb_power_down_phy_copper_82575(&adapter->hw);
1644 else
1645 igb_shutdown_serdes_link_82575(&adapter->hw);
1646 }
1647
1648 /**
1649 * Detect and switch function for Media Auto Sense
1650 * @adapter: address of the board private structure
1651 **/
1652 static void igb_check_swap_media(struct igb_adapter *adapter)
1653 {
1654 struct e1000_hw *hw = &adapter->hw;
1655 u32 ctrl_ext, connsw;
1656 bool swap_now = false;
1657
1658 ctrl_ext = rd32(E1000_CTRL_EXT);
1659 connsw = rd32(E1000_CONNSW);
1660
1661 /* need to live swap if current media is copper and we have fiber/serdes
1662 * to go to.
1663 */
1664
1665 if ((hw->phy.media_type == e1000_media_type_copper) &&
1666 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1667 swap_now = true;
1668 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1669 /* copper signal takes time to appear */
1670 if (adapter->copper_tries < 4) {
1671 adapter->copper_tries++;
1672 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1673 wr32(E1000_CONNSW, connsw);
1674 return;
1675 } else {
1676 adapter->copper_tries = 0;
1677 if ((connsw & E1000_CONNSW_PHYSD) &&
1678 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1679 swap_now = true;
1680 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 }
1683 }
1684 }
1685
1686 if (!swap_now)
1687 return;
1688
1689 switch (hw->phy.media_type) {
1690 case e1000_media_type_copper:
1691 netdev_info(adapter->netdev,
1692 "MAS: changing media to fiber/serdes\n");
1693 ctrl_ext |=
1694 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1695 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1696 adapter->copper_tries = 0;
1697 break;
1698 case e1000_media_type_internal_serdes:
1699 case e1000_media_type_fiber:
1700 netdev_info(adapter->netdev,
1701 "MAS: changing media to copper\n");
1702 ctrl_ext &=
1703 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1704 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1705 break;
1706 default:
1707 /* shouldn't get here during regular operation */
1708 netdev_err(adapter->netdev,
1709 "AMS: Invalid media type found, returning\n");
1710 break;
1711 }
1712 wr32(E1000_CTRL_EXT, ctrl_ext);
1713 }
1714
1715 /**
1716 * igb_up - Open the interface and prepare it to handle traffic
1717 * @adapter: board private structure
1718 **/
1719 int igb_up(struct igb_adapter *adapter)
1720 {
1721 struct e1000_hw *hw = &adapter->hw;
1722 int i;
1723
1724 /* hardware has been reset, we need to reload some things */
1725 igb_configure(adapter);
1726
1727 clear_bit(__IGB_DOWN, &adapter->state);
1728
1729 for (i = 0; i < adapter->num_q_vectors; i++)
1730 napi_enable(&(adapter->q_vector[i]->napi));
1731
1732 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1733 igb_configure_msix(adapter);
1734 else
1735 igb_assign_vector(adapter->q_vector[0], 0);
1736
1737 /* Clear any pending interrupts. */
1738 rd32(E1000_ICR);
1739 igb_irq_enable(adapter);
1740
1741 /* notify VFs that reset has been completed */
1742 if (adapter->vfs_allocated_count) {
1743 u32 reg_data = rd32(E1000_CTRL_EXT);
1744
1745 reg_data |= E1000_CTRL_EXT_PFRSTD;
1746 wr32(E1000_CTRL_EXT, reg_data);
1747 }
1748
1749 netif_tx_start_all_queues(adapter->netdev);
1750
1751 /* start the watchdog. */
1752 hw->mac.get_link_status = 1;
1753 schedule_work(&adapter->watchdog_task);
1754
1755 if ((adapter->flags & IGB_FLAG_EEE) &&
1756 (!hw->dev_spec._82575.eee_disable))
1757 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1758
1759 return 0;
1760 }
1761
1762 void igb_down(struct igb_adapter *adapter)
1763 {
1764 struct net_device *netdev = adapter->netdev;
1765 struct e1000_hw *hw = &adapter->hw;
1766 u32 tctl, rctl;
1767 int i;
1768
1769 /* signal that we're down so the interrupt handler does not
1770 * reschedule our watchdog timer
1771 */
1772 set_bit(__IGB_DOWN, &adapter->state);
1773
1774 /* disable receives in the hardware */
1775 rctl = rd32(E1000_RCTL);
1776 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1777 /* flush and sleep below */
1778
1779 netif_carrier_off(netdev);
1780 netif_tx_stop_all_queues(netdev);
1781
1782 /* disable transmits in the hardware */
1783 tctl = rd32(E1000_TCTL);
1784 tctl &= ~E1000_TCTL_EN;
1785 wr32(E1000_TCTL, tctl);
1786 /* flush both disables and wait for them to finish */
1787 wrfl();
1788 usleep_range(10000, 11000);
1789
1790 igb_irq_disable(adapter);
1791
1792 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1793
1794 for (i = 0; i < adapter->num_q_vectors; i++) {
1795 if (adapter->q_vector[i]) {
1796 napi_synchronize(&adapter->q_vector[i]->napi);
1797 napi_disable(&adapter->q_vector[i]->napi);
1798 }
1799 }
1800
1801 del_timer_sync(&adapter->watchdog_timer);
1802 del_timer_sync(&adapter->phy_info_timer);
1803
1804 /* record the stats before reset*/
1805 spin_lock(&adapter->stats64_lock);
1806 igb_update_stats(adapter, &adapter->stats64);
1807 spin_unlock(&adapter->stats64_lock);
1808
1809 adapter->link_speed = 0;
1810 adapter->link_duplex = 0;
1811
1812 if (!pci_channel_offline(adapter->pdev))
1813 igb_reset(adapter);
1814 igb_clean_all_tx_rings(adapter);
1815 igb_clean_all_rx_rings(adapter);
1816 #ifdef CONFIG_IGB_DCA
1817
1818 /* since we reset the hardware DCA settings were cleared */
1819 igb_setup_dca(adapter);
1820 #endif
1821 }
1822
1823 void igb_reinit_locked(struct igb_adapter *adapter)
1824 {
1825 WARN_ON(in_interrupt());
1826 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1827 usleep_range(1000, 2000);
1828 igb_down(adapter);
1829 igb_up(adapter);
1830 clear_bit(__IGB_RESETTING, &adapter->state);
1831 }
1832
1833 /** igb_enable_mas - Media Autosense re-enable after swap
1834 *
1835 * @adapter: adapter struct
1836 **/
1837 static void igb_enable_mas(struct igb_adapter *adapter)
1838 {
1839 struct e1000_hw *hw = &adapter->hw;
1840 u32 connsw = rd32(E1000_CONNSW);
1841
1842 /* configure for SerDes media detect */
1843 if ((hw->phy.media_type == e1000_media_type_copper) &&
1844 (!(connsw & E1000_CONNSW_SERDESD))) {
1845 connsw |= E1000_CONNSW_ENRGSRC;
1846 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1847 wr32(E1000_CONNSW, connsw);
1848 wrfl();
1849 }
1850 }
1851
1852 void igb_reset(struct igb_adapter *adapter)
1853 {
1854 struct pci_dev *pdev = adapter->pdev;
1855 struct e1000_hw *hw = &adapter->hw;
1856 struct e1000_mac_info *mac = &hw->mac;
1857 struct e1000_fc_info *fc = &hw->fc;
1858 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1859
1860 /* Repartition Pba for greater than 9k mtu
1861 * To take effect CTRL.RST is required.
1862 */
1863 switch (mac->type) {
1864 case e1000_i350:
1865 case e1000_i354:
1866 case e1000_82580:
1867 pba = rd32(E1000_RXPBS);
1868 pba = igb_rxpbs_adjust_82580(pba);
1869 break;
1870 case e1000_82576:
1871 pba = rd32(E1000_RXPBS);
1872 pba &= E1000_RXPBS_SIZE_MASK_82576;
1873 break;
1874 case e1000_82575:
1875 case e1000_i210:
1876 case e1000_i211:
1877 default:
1878 pba = E1000_PBA_34K;
1879 break;
1880 }
1881
1882 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1883 (mac->type < e1000_82576)) {
1884 /* adjust PBA for jumbo frames */
1885 wr32(E1000_PBA, pba);
1886
1887 /* To maintain wire speed transmits, the Tx FIFO should be
1888 * large enough to accommodate two full transmit packets,
1889 * rounded up to the next 1KB and expressed in KB. Likewise,
1890 * the Rx FIFO should be large enough to accommodate at least
1891 * one full receive packet and is similarly rounded up and
1892 * expressed in KB.
1893 */
1894 pba = rd32(E1000_PBA);
1895 /* upper 16 bits has Tx packet buffer allocation size in KB */
1896 tx_space = pba >> 16;
1897 /* lower 16 bits has Rx packet buffer allocation size in KB */
1898 pba &= 0xffff;
1899 /* the Tx fifo also stores 16 bytes of information about the Tx
1900 * but don't include ethernet FCS because hardware appends it
1901 */
1902 min_tx_space = (adapter->max_frame_size +
1903 sizeof(union e1000_adv_tx_desc) -
1904 ETH_FCS_LEN) * 2;
1905 min_tx_space = ALIGN(min_tx_space, 1024);
1906 min_tx_space >>= 10;
1907 /* software strips receive CRC, so leave room for it */
1908 min_rx_space = adapter->max_frame_size;
1909 min_rx_space = ALIGN(min_rx_space, 1024);
1910 min_rx_space >>= 10;
1911
1912 /* If current Tx allocation is less than the min Tx FIFO size,
1913 * and the min Tx FIFO size is less than the current Rx FIFO
1914 * allocation, take space away from current Rx allocation
1915 */
1916 if (tx_space < min_tx_space &&
1917 ((min_tx_space - tx_space) < pba)) {
1918 pba = pba - (min_tx_space - tx_space);
1919
1920 /* if short on Rx space, Rx wins and must trump Tx
1921 * adjustment
1922 */
1923 if (pba < min_rx_space)
1924 pba = min_rx_space;
1925 }
1926 wr32(E1000_PBA, pba);
1927 }
1928
1929 /* flow control settings */
1930 /* The high water mark must be low enough to fit one full frame
1931 * (or the size used for early receive) above it in the Rx FIFO.
1932 * Set it to the lower of:
1933 * - 90% of the Rx FIFO size, or
1934 * - the full Rx FIFO size minus one full frame
1935 */
1936 hwm = min(((pba << 10) * 9 / 10),
1937 ((pba << 10) - 2 * adapter->max_frame_size));
1938
1939 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1940 fc->low_water = fc->high_water - 16;
1941 fc->pause_time = 0xFFFF;
1942 fc->send_xon = 1;
1943 fc->current_mode = fc->requested_mode;
1944
1945 /* disable receive for all VFs and wait one second */
1946 if (adapter->vfs_allocated_count) {
1947 int i;
1948
1949 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1950 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1951
1952 /* ping all the active vfs to let them know we are going down */
1953 igb_ping_all_vfs(adapter);
1954
1955 /* disable transmits and receives */
1956 wr32(E1000_VFRE, 0);
1957 wr32(E1000_VFTE, 0);
1958 }
1959
1960 /* Allow time for pending master requests to run */
1961 hw->mac.ops.reset_hw(hw);
1962 wr32(E1000_WUC, 0);
1963
1964 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1965 /* need to resetup here after media swap */
1966 adapter->ei.get_invariants(hw);
1967 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1968 }
1969 if ((mac->type == e1000_82575) &&
1970 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1971 igb_enable_mas(adapter);
1972 }
1973 if (hw->mac.ops.init_hw(hw))
1974 dev_err(&pdev->dev, "Hardware Error\n");
1975
1976 /* Flow control settings reset on hardware reset, so guarantee flow
1977 * control is off when forcing speed.
1978 */
1979 if (!hw->mac.autoneg)
1980 igb_force_mac_fc(hw);
1981
1982 igb_init_dmac(adapter, pba);
1983 #ifdef CONFIG_IGB_HWMON
1984 /* Re-initialize the thermal sensor on i350 devices. */
1985 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1986 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1987 /* If present, re-initialize the external thermal sensor
1988 * interface.
1989 */
1990 if (adapter->ets)
1991 mac->ops.init_thermal_sensor_thresh(hw);
1992 }
1993 }
1994 #endif
1995 /* Re-establish EEE setting */
1996 if (hw->phy.media_type == e1000_media_type_copper) {
1997 switch (mac->type) {
1998 case e1000_i350:
1999 case e1000_i210:
2000 case e1000_i211:
2001 igb_set_eee_i350(hw, true, true);
2002 break;
2003 case e1000_i354:
2004 igb_set_eee_i354(hw, true, true);
2005 break;
2006 default:
2007 break;
2008 }
2009 }
2010 if (!netif_running(adapter->netdev))
2011 igb_power_down_link(adapter);
2012
2013 igb_update_mng_vlan(adapter);
2014
2015 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2016 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2017
2018 /* Re-enable PTP, where applicable. */
2019 igb_ptp_reset(adapter);
2020
2021 igb_get_phy_info(hw);
2022 }
2023
2024 static netdev_features_t igb_fix_features(struct net_device *netdev,
2025 netdev_features_t features)
2026 {
2027 /* Since there is no support for separate Rx/Tx vlan accel
2028 * enable/disable make sure Tx flag is always in same state as Rx.
2029 */
2030 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2031 features |= NETIF_F_HW_VLAN_CTAG_TX;
2032 else
2033 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2034
2035 return features;
2036 }
2037
2038 static int igb_set_features(struct net_device *netdev,
2039 netdev_features_t features)
2040 {
2041 netdev_features_t changed = netdev->features ^ features;
2042 struct igb_adapter *adapter = netdev_priv(netdev);
2043
2044 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2045 igb_vlan_mode(netdev, features);
2046
2047 if (!(changed & NETIF_F_RXALL))
2048 return 0;
2049
2050 netdev->features = features;
2051
2052 if (netif_running(netdev))
2053 igb_reinit_locked(adapter);
2054 else
2055 igb_reset(adapter);
2056
2057 return 0;
2058 }
2059
2060 static const struct net_device_ops igb_netdev_ops = {
2061 .ndo_open = igb_open,
2062 .ndo_stop = igb_close,
2063 .ndo_start_xmit = igb_xmit_frame,
2064 .ndo_get_stats64 = igb_get_stats64,
2065 .ndo_set_rx_mode = igb_set_rx_mode,
2066 .ndo_set_mac_address = igb_set_mac,
2067 .ndo_change_mtu = igb_change_mtu,
2068 .ndo_do_ioctl = igb_ioctl,
2069 .ndo_tx_timeout = igb_tx_timeout,
2070 .ndo_validate_addr = eth_validate_addr,
2071 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2072 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2073 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2074 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2075 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2076 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2077 .ndo_get_vf_config = igb_ndo_get_vf_config,
2078 #ifdef CONFIG_NET_POLL_CONTROLLER
2079 .ndo_poll_controller = igb_netpoll,
2080 #endif
2081 .ndo_fix_features = igb_fix_features,
2082 .ndo_set_features = igb_set_features,
2083 .ndo_features_check = passthru_features_check,
2084 };
2085
2086 /**
2087 * igb_set_fw_version - Configure version string for ethtool
2088 * @adapter: adapter struct
2089 **/
2090 void igb_set_fw_version(struct igb_adapter *adapter)
2091 {
2092 struct e1000_hw *hw = &adapter->hw;
2093 struct e1000_fw_version fw;
2094
2095 igb_get_fw_version(hw, &fw);
2096
2097 switch (hw->mac.type) {
2098 case e1000_i210:
2099 case e1000_i211:
2100 if (!(igb_get_flash_presence_i210(hw))) {
2101 snprintf(adapter->fw_version,
2102 sizeof(adapter->fw_version),
2103 "%2d.%2d-%d",
2104 fw.invm_major, fw.invm_minor,
2105 fw.invm_img_type);
2106 break;
2107 }
2108 /* fall through */
2109 default:
2110 /* if option is rom valid, display its version too */
2111 if (fw.or_valid) {
2112 snprintf(adapter->fw_version,
2113 sizeof(adapter->fw_version),
2114 "%d.%d, 0x%08x, %d.%d.%d",
2115 fw.eep_major, fw.eep_minor, fw.etrack_id,
2116 fw.or_major, fw.or_build, fw.or_patch);
2117 /* no option rom */
2118 } else if (fw.etrack_id != 0X0000) {
2119 snprintf(adapter->fw_version,
2120 sizeof(adapter->fw_version),
2121 "%d.%d, 0x%08x",
2122 fw.eep_major, fw.eep_minor, fw.etrack_id);
2123 } else {
2124 snprintf(adapter->fw_version,
2125 sizeof(adapter->fw_version),
2126 "%d.%d.%d",
2127 fw.eep_major, fw.eep_minor, fw.eep_build);
2128 }
2129 break;
2130 }
2131 }
2132
2133 /**
2134 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2135 *
2136 * @adapter: adapter struct
2137 **/
2138 static void igb_init_mas(struct igb_adapter *adapter)
2139 {
2140 struct e1000_hw *hw = &adapter->hw;
2141 u16 eeprom_data;
2142
2143 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2144 switch (hw->bus.func) {
2145 case E1000_FUNC_0:
2146 if (eeprom_data & IGB_MAS_ENABLE_0) {
2147 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2148 netdev_info(adapter->netdev,
2149 "MAS: Enabling Media Autosense for port %d\n",
2150 hw->bus.func);
2151 }
2152 break;
2153 case E1000_FUNC_1:
2154 if (eeprom_data & IGB_MAS_ENABLE_1) {
2155 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2156 netdev_info(adapter->netdev,
2157 "MAS: Enabling Media Autosense for port %d\n",
2158 hw->bus.func);
2159 }
2160 break;
2161 case E1000_FUNC_2:
2162 if (eeprom_data & IGB_MAS_ENABLE_2) {
2163 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2164 netdev_info(adapter->netdev,
2165 "MAS: Enabling Media Autosense for port %d\n",
2166 hw->bus.func);
2167 }
2168 break;
2169 case E1000_FUNC_3:
2170 if (eeprom_data & IGB_MAS_ENABLE_3) {
2171 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2172 netdev_info(adapter->netdev,
2173 "MAS: Enabling Media Autosense for port %d\n",
2174 hw->bus.func);
2175 }
2176 break;
2177 default:
2178 /* Shouldn't get here */
2179 netdev_err(adapter->netdev,
2180 "MAS: Invalid port configuration, returning\n");
2181 break;
2182 }
2183 }
2184
2185 /**
2186 * igb_init_i2c - Init I2C interface
2187 * @adapter: pointer to adapter structure
2188 **/
2189 static s32 igb_init_i2c(struct igb_adapter *adapter)
2190 {
2191 s32 status = 0;
2192
2193 /* I2C interface supported on i350 devices */
2194 if (adapter->hw.mac.type != e1000_i350)
2195 return 0;
2196
2197 /* Initialize the i2c bus which is controlled by the registers.
2198 * This bus will use the i2c_algo_bit structue that implements
2199 * the protocol through toggling of the 4 bits in the register.
2200 */
2201 adapter->i2c_adap.owner = THIS_MODULE;
2202 adapter->i2c_algo = igb_i2c_algo;
2203 adapter->i2c_algo.data = adapter;
2204 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2205 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2206 strlcpy(adapter->i2c_adap.name, "igb BB",
2207 sizeof(adapter->i2c_adap.name));
2208 status = i2c_bit_add_bus(&adapter->i2c_adap);
2209 return status;
2210 }
2211
2212 /**
2213 * igb_probe - Device Initialization Routine
2214 * @pdev: PCI device information struct
2215 * @ent: entry in igb_pci_tbl
2216 *
2217 * Returns 0 on success, negative on failure
2218 *
2219 * igb_probe initializes an adapter identified by a pci_dev structure.
2220 * The OS initialization, configuring of the adapter private structure,
2221 * and a hardware reset occur.
2222 **/
2223 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2224 {
2225 struct net_device *netdev;
2226 struct igb_adapter *adapter;
2227 struct e1000_hw *hw;
2228 u16 eeprom_data = 0;
2229 s32 ret_val;
2230 static int global_quad_port_a; /* global quad port a indication */
2231 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2232 int err, pci_using_dac;
2233 u8 part_str[E1000_PBANUM_LENGTH];
2234
2235 /* Catch broken hardware that put the wrong VF device ID in
2236 * the PCIe SR-IOV capability.
2237 */
2238 if (pdev->is_virtfn) {
2239 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2240 pci_name(pdev), pdev->vendor, pdev->device);
2241 return -EINVAL;
2242 }
2243
2244 err = pci_enable_device_mem(pdev);
2245 if (err)
2246 return err;
2247
2248 pci_using_dac = 0;
2249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2250 if (!err) {
2251 pci_using_dac = 1;
2252 } else {
2253 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2254 if (err) {
2255 dev_err(&pdev->dev,
2256 "No usable DMA configuration, aborting\n");
2257 goto err_dma;
2258 }
2259 }
2260
2261 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2262 IORESOURCE_MEM),
2263 igb_driver_name);
2264 if (err)
2265 goto err_pci_reg;
2266
2267 pci_enable_pcie_error_reporting(pdev);
2268
2269 pci_set_master(pdev);
2270 pci_save_state(pdev);
2271
2272 err = -ENOMEM;
2273 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2274 IGB_MAX_TX_QUEUES);
2275 if (!netdev)
2276 goto err_alloc_etherdev;
2277
2278 SET_NETDEV_DEV(netdev, &pdev->dev);
2279
2280 pci_set_drvdata(pdev, netdev);
2281 adapter = netdev_priv(netdev);
2282 adapter->netdev = netdev;
2283 adapter->pdev = pdev;
2284 hw = &adapter->hw;
2285 hw->back = adapter;
2286 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2287
2288 err = -EIO;
2289 hw->hw_addr = pci_iomap(pdev, 0, 0);
2290 if (!hw->hw_addr)
2291 goto err_ioremap;
2292
2293 netdev->netdev_ops = &igb_netdev_ops;
2294 igb_set_ethtool_ops(netdev);
2295 netdev->watchdog_timeo = 5 * HZ;
2296
2297 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2298
2299 netdev->mem_start = pci_resource_start(pdev, 0);
2300 netdev->mem_end = pci_resource_end(pdev, 0);
2301
2302 /* PCI config space info */
2303 hw->vendor_id = pdev->vendor;
2304 hw->device_id = pdev->device;
2305 hw->revision_id = pdev->revision;
2306 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2307 hw->subsystem_device_id = pdev->subsystem_device;
2308
2309 /* Copy the default MAC, PHY and NVM function pointers */
2310 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2311 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2312 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2313 /* Initialize skew-specific constants */
2314 err = ei->get_invariants(hw);
2315 if (err)
2316 goto err_sw_init;
2317
2318 /* setup the private structure */
2319 err = igb_sw_init(adapter);
2320 if (err)
2321 goto err_sw_init;
2322
2323 igb_get_bus_info_pcie(hw);
2324
2325 hw->phy.autoneg_wait_to_complete = false;
2326
2327 /* Copper options */
2328 if (hw->phy.media_type == e1000_media_type_copper) {
2329 hw->phy.mdix = AUTO_ALL_MODES;
2330 hw->phy.disable_polarity_correction = false;
2331 hw->phy.ms_type = e1000_ms_hw_default;
2332 }
2333
2334 if (igb_check_reset_block(hw))
2335 dev_info(&pdev->dev,
2336 "PHY reset is blocked due to SOL/IDER session.\n");
2337
2338 /* features is initialized to 0 in allocation, it might have bits
2339 * set by igb_sw_init so we should use an or instead of an
2340 * assignment.
2341 */
2342 netdev->features |= NETIF_F_SG |
2343 NETIF_F_IP_CSUM |
2344 NETIF_F_IPV6_CSUM |
2345 NETIF_F_TSO |
2346 NETIF_F_TSO6 |
2347 NETIF_F_RXHASH |
2348 NETIF_F_RXCSUM |
2349 NETIF_F_HW_VLAN_CTAG_RX |
2350 NETIF_F_HW_VLAN_CTAG_TX;
2351
2352 /* copy netdev features into list of user selectable features */
2353 netdev->hw_features |= netdev->features;
2354 netdev->hw_features |= NETIF_F_RXALL;
2355
2356 /* set this bit last since it cannot be part of hw_features */
2357 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2358
2359 netdev->vlan_features |= NETIF_F_TSO |
2360 NETIF_F_TSO6 |
2361 NETIF_F_IP_CSUM |
2362 NETIF_F_IPV6_CSUM |
2363 NETIF_F_SG;
2364
2365 netdev->priv_flags |= IFF_SUPP_NOFCS;
2366
2367 if (pci_using_dac) {
2368 netdev->features |= NETIF_F_HIGHDMA;
2369 netdev->vlan_features |= NETIF_F_HIGHDMA;
2370 }
2371
2372 if (hw->mac.type >= e1000_82576) {
2373 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2374 netdev->features |= NETIF_F_SCTP_CSUM;
2375 }
2376
2377 netdev->priv_flags |= IFF_UNICAST_FLT;
2378
2379 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2380
2381 /* before reading the NVM, reset the controller to put the device in a
2382 * known good starting state
2383 */
2384 hw->mac.ops.reset_hw(hw);
2385
2386 /* make sure the NVM is good , i211/i210 parts can have special NVM
2387 * that doesn't contain a checksum
2388 */
2389 switch (hw->mac.type) {
2390 case e1000_i210:
2391 case e1000_i211:
2392 if (igb_get_flash_presence_i210(hw)) {
2393 if (hw->nvm.ops.validate(hw) < 0) {
2394 dev_err(&pdev->dev,
2395 "The NVM Checksum Is Not Valid\n");
2396 err = -EIO;
2397 goto err_eeprom;
2398 }
2399 }
2400 break;
2401 default:
2402 if (hw->nvm.ops.validate(hw) < 0) {
2403 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2404 err = -EIO;
2405 goto err_eeprom;
2406 }
2407 break;
2408 }
2409
2410 /* copy the MAC address out of the NVM */
2411 if (hw->mac.ops.read_mac_addr(hw))
2412 dev_err(&pdev->dev, "NVM Read Error\n");
2413
2414 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2415
2416 if (!is_valid_ether_addr(netdev->dev_addr)) {
2417 dev_err(&pdev->dev, "Invalid MAC Address\n");
2418 err = -EIO;
2419 goto err_eeprom;
2420 }
2421
2422 /* get firmware version for ethtool -i */
2423 igb_set_fw_version(adapter);
2424
2425 /* configure RXPBSIZE and TXPBSIZE */
2426 if (hw->mac.type == e1000_i210) {
2427 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2428 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2429 }
2430
2431 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2432 (unsigned long) adapter);
2433 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2434 (unsigned long) adapter);
2435
2436 INIT_WORK(&adapter->reset_task, igb_reset_task);
2437 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2438
2439 /* Initialize link properties that are user-changeable */
2440 adapter->fc_autoneg = true;
2441 hw->mac.autoneg = true;
2442 hw->phy.autoneg_advertised = 0x2f;
2443
2444 hw->fc.requested_mode = e1000_fc_default;
2445 hw->fc.current_mode = e1000_fc_default;
2446
2447 igb_validate_mdi_setting(hw);
2448
2449 /* By default, support wake on port A */
2450 if (hw->bus.func == 0)
2451 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2452
2453 /* Check the NVM for wake support on non-port A ports */
2454 if (hw->mac.type >= e1000_82580)
2455 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2456 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2457 &eeprom_data);
2458 else if (hw->bus.func == 1)
2459 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2460
2461 if (eeprom_data & IGB_EEPROM_APME)
2462 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2463
2464 /* now that we have the eeprom settings, apply the special cases where
2465 * the eeprom may be wrong or the board simply won't support wake on
2466 * lan on a particular port
2467 */
2468 switch (pdev->device) {
2469 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2470 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2471 break;
2472 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2473 case E1000_DEV_ID_82576_FIBER:
2474 case E1000_DEV_ID_82576_SERDES:
2475 /* Wake events only supported on port A for dual fiber
2476 * regardless of eeprom setting
2477 */
2478 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2479 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2480 break;
2481 case E1000_DEV_ID_82576_QUAD_COPPER:
2482 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2483 /* if quad port adapter, disable WoL on all but port A */
2484 if (global_quad_port_a != 0)
2485 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2486 else
2487 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2488 /* Reset for multiple quad port adapters */
2489 if (++global_quad_port_a == 4)
2490 global_quad_port_a = 0;
2491 break;
2492 default:
2493 /* If the device can't wake, don't set software support */
2494 if (!device_can_wakeup(&adapter->pdev->dev))
2495 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2496 }
2497
2498 /* initialize the wol settings based on the eeprom settings */
2499 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2500 adapter->wol |= E1000_WUFC_MAG;
2501
2502 /* Some vendors want WoL disabled by default, but still supported */
2503 if ((hw->mac.type == e1000_i350) &&
2504 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2505 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2506 adapter->wol = 0;
2507 }
2508
2509 device_set_wakeup_enable(&adapter->pdev->dev,
2510 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2511
2512 /* reset the hardware with the new settings */
2513 igb_reset(adapter);
2514
2515 /* Init the I2C interface */
2516 err = igb_init_i2c(adapter);
2517 if (err) {
2518 dev_err(&pdev->dev, "failed to init i2c interface\n");
2519 goto err_eeprom;
2520 }
2521
2522 /* let the f/w know that the h/w is now under the control of the
2523 * driver.
2524 */
2525 igb_get_hw_control(adapter);
2526
2527 strcpy(netdev->name, "eth%d");
2528 err = register_netdev(netdev);
2529 if (err)
2530 goto err_register;
2531
2532 /* carrier off reporting is important to ethtool even BEFORE open */
2533 netif_carrier_off(netdev);
2534
2535 #ifdef CONFIG_IGB_DCA
2536 if (dca_add_requester(&pdev->dev) == 0) {
2537 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2538 dev_info(&pdev->dev, "DCA enabled\n");
2539 igb_setup_dca(adapter);
2540 }
2541
2542 #endif
2543 #ifdef CONFIG_IGB_HWMON
2544 /* Initialize the thermal sensor on i350 devices. */
2545 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2546 u16 ets_word;
2547
2548 /* Read the NVM to determine if this i350 device supports an
2549 * external thermal sensor.
2550 */
2551 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2552 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2553 adapter->ets = true;
2554 else
2555 adapter->ets = false;
2556 if (igb_sysfs_init(adapter))
2557 dev_err(&pdev->dev,
2558 "failed to allocate sysfs resources\n");
2559 } else {
2560 adapter->ets = false;
2561 }
2562 #endif
2563 /* Check if Media Autosense is enabled */
2564 adapter->ei = *ei;
2565 if (hw->dev_spec._82575.mas_capable)
2566 igb_init_mas(adapter);
2567
2568 /* do hw tstamp init after resetting */
2569 igb_ptp_init(adapter);
2570
2571 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2572 /* print bus type/speed/width info, not applicable to i354 */
2573 if (hw->mac.type != e1000_i354) {
2574 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2575 netdev->name,
2576 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2577 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2578 "unknown"),
2579 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2580 "Width x4" :
2581 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2582 "Width x2" :
2583 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2584 "Width x1" : "unknown"), netdev->dev_addr);
2585 }
2586
2587 if ((hw->mac.type >= e1000_i210 ||
2588 igb_get_flash_presence_i210(hw))) {
2589 ret_val = igb_read_part_string(hw, part_str,
2590 E1000_PBANUM_LENGTH);
2591 } else {
2592 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2593 }
2594
2595 if (ret_val)
2596 strcpy(part_str, "Unknown");
2597 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2598 dev_info(&pdev->dev,
2599 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2600 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2601 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2602 adapter->num_rx_queues, adapter->num_tx_queues);
2603 if (hw->phy.media_type == e1000_media_type_copper) {
2604 switch (hw->mac.type) {
2605 case e1000_i350:
2606 case e1000_i210:
2607 case e1000_i211:
2608 /* Enable EEE for internal copper PHY devices */
2609 err = igb_set_eee_i350(hw, true, true);
2610 if ((!err) &&
2611 (!hw->dev_spec._82575.eee_disable)) {
2612 adapter->eee_advert =
2613 MDIO_EEE_100TX | MDIO_EEE_1000T;
2614 adapter->flags |= IGB_FLAG_EEE;
2615 }
2616 break;
2617 case e1000_i354:
2618 if ((rd32(E1000_CTRL_EXT) &
2619 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2620 err = igb_set_eee_i354(hw, true, true);
2621 if ((!err) &&
2622 (!hw->dev_spec._82575.eee_disable)) {
2623 adapter->eee_advert =
2624 MDIO_EEE_100TX | MDIO_EEE_1000T;
2625 adapter->flags |= IGB_FLAG_EEE;
2626 }
2627 }
2628 break;
2629 default:
2630 break;
2631 }
2632 }
2633 pm_runtime_put_noidle(&pdev->dev);
2634 return 0;
2635
2636 err_register:
2637 igb_release_hw_control(adapter);
2638 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2639 err_eeprom:
2640 if (!igb_check_reset_block(hw))
2641 igb_reset_phy(hw);
2642
2643 if (hw->flash_address)
2644 iounmap(hw->flash_address);
2645 err_sw_init:
2646 igb_clear_interrupt_scheme(adapter);
2647 pci_iounmap(pdev, hw->hw_addr);
2648 err_ioremap:
2649 free_netdev(netdev);
2650 err_alloc_etherdev:
2651 pci_release_selected_regions(pdev,
2652 pci_select_bars(pdev, IORESOURCE_MEM));
2653 err_pci_reg:
2654 err_dma:
2655 pci_disable_device(pdev);
2656 return err;
2657 }
2658
2659 #ifdef CONFIG_PCI_IOV
2660 static int igb_disable_sriov(struct pci_dev *pdev)
2661 {
2662 struct net_device *netdev = pci_get_drvdata(pdev);
2663 struct igb_adapter *adapter = netdev_priv(netdev);
2664 struct e1000_hw *hw = &adapter->hw;
2665
2666 /* reclaim resources allocated to VFs */
2667 if (adapter->vf_data) {
2668 /* disable iov and allow time for transactions to clear */
2669 if (pci_vfs_assigned(pdev)) {
2670 dev_warn(&pdev->dev,
2671 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2672 return -EPERM;
2673 } else {
2674 pci_disable_sriov(pdev);
2675 msleep(500);
2676 }
2677
2678 kfree(adapter->vf_data);
2679 adapter->vf_data = NULL;
2680 adapter->vfs_allocated_count = 0;
2681 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2682 wrfl();
2683 msleep(100);
2684 dev_info(&pdev->dev, "IOV Disabled\n");
2685
2686 /* Re-enable DMA Coalescing flag since IOV is turned off */
2687 adapter->flags |= IGB_FLAG_DMAC;
2688 }
2689
2690 return 0;
2691 }
2692
2693 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2694 {
2695 struct net_device *netdev = pci_get_drvdata(pdev);
2696 struct igb_adapter *adapter = netdev_priv(netdev);
2697 int old_vfs = pci_num_vf(pdev);
2698 int err = 0;
2699 int i;
2700
2701 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2702 err = -EPERM;
2703 goto out;
2704 }
2705 if (!num_vfs)
2706 goto out;
2707
2708 if (old_vfs) {
2709 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2710 old_vfs, max_vfs);
2711 adapter->vfs_allocated_count = old_vfs;
2712 } else
2713 adapter->vfs_allocated_count = num_vfs;
2714
2715 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2716 sizeof(struct vf_data_storage), GFP_KERNEL);
2717
2718 /* if allocation failed then we do not support SR-IOV */
2719 if (!adapter->vf_data) {
2720 adapter->vfs_allocated_count = 0;
2721 dev_err(&pdev->dev,
2722 "Unable to allocate memory for VF Data Storage\n");
2723 err = -ENOMEM;
2724 goto out;
2725 }
2726
2727 /* only call pci_enable_sriov() if no VFs are allocated already */
2728 if (!old_vfs) {
2729 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2730 if (err)
2731 goto err_out;
2732 }
2733 dev_info(&pdev->dev, "%d VFs allocated\n",
2734 adapter->vfs_allocated_count);
2735 for (i = 0; i < adapter->vfs_allocated_count; i++)
2736 igb_vf_configure(adapter, i);
2737
2738 /* DMA Coalescing is not supported in IOV mode. */
2739 adapter->flags &= ~IGB_FLAG_DMAC;
2740 goto out;
2741
2742 err_out:
2743 kfree(adapter->vf_data);
2744 adapter->vf_data = NULL;
2745 adapter->vfs_allocated_count = 0;
2746 out:
2747 return err;
2748 }
2749
2750 #endif
2751 /**
2752 * igb_remove_i2c - Cleanup I2C interface
2753 * @adapter: pointer to adapter structure
2754 **/
2755 static void igb_remove_i2c(struct igb_adapter *adapter)
2756 {
2757 /* free the adapter bus structure */
2758 i2c_del_adapter(&adapter->i2c_adap);
2759 }
2760
2761 /**
2762 * igb_remove - Device Removal Routine
2763 * @pdev: PCI device information struct
2764 *
2765 * igb_remove is called by the PCI subsystem to alert the driver
2766 * that it should release a PCI device. The could be caused by a
2767 * Hot-Plug event, or because the driver is going to be removed from
2768 * memory.
2769 **/
2770 static void igb_remove(struct pci_dev *pdev)
2771 {
2772 struct net_device *netdev = pci_get_drvdata(pdev);
2773 struct igb_adapter *adapter = netdev_priv(netdev);
2774 struct e1000_hw *hw = &adapter->hw;
2775
2776 pm_runtime_get_noresume(&pdev->dev);
2777 #ifdef CONFIG_IGB_HWMON
2778 igb_sysfs_exit(adapter);
2779 #endif
2780 igb_remove_i2c(adapter);
2781 igb_ptp_stop(adapter);
2782 /* The watchdog timer may be rescheduled, so explicitly
2783 * disable watchdog from being rescheduled.
2784 */
2785 set_bit(__IGB_DOWN, &adapter->state);
2786 del_timer_sync(&adapter->watchdog_timer);
2787 del_timer_sync(&adapter->phy_info_timer);
2788
2789 cancel_work_sync(&adapter->reset_task);
2790 cancel_work_sync(&adapter->watchdog_task);
2791
2792 #ifdef CONFIG_IGB_DCA
2793 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2794 dev_info(&pdev->dev, "DCA disabled\n");
2795 dca_remove_requester(&pdev->dev);
2796 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2797 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2798 }
2799 #endif
2800
2801 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2802 * would have already happened in close and is redundant.
2803 */
2804 igb_release_hw_control(adapter);
2805
2806 unregister_netdev(netdev);
2807
2808 igb_clear_interrupt_scheme(adapter);
2809
2810 #ifdef CONFIG_PCI_IOV
2811 igb_disable_sriov(pdev);
2812 #endif
2813
2814 pci_iounmap(pdev, hw->hw_addr);
2815 if (hw->flash_address)
2816 iounmap(hw->flash_address);
2817 pci_release_selected_regions(pdev,
2818 pci_select_bars(pdev, IORESOURCE_MEM));
2819
2820 kfree(adapter->shadow_vfta);
2821 free_netdev(netdev);
2822
2823 pci_disable_pcie_error_reporting(pdev);
2824
2825 pci_disable_device(pdev);
2826 }
2827
2828 /**
2829 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2830 * @adapter: board private structure to initialize
2831 *
2832 * This function initializes the vf specific data storage and then attempts to
2833 * allocate the VFs. The reason for ordering it this way is because it is much
2834 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2835 * the memory for the VFs.
2836 **/
2837 static void igb_probe_vfs(struct igb_adapter *adapter)
2838 {
2839 #ifdef CONFIG_PCI_IOV
2840 struct pci_dev *pdev = adapter->pdev;
2841 struct e1000_hw *hw = &adapter->hw;
2842
2843 /* Virtualization features not supported on i210 family. */
2844 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2845 return;
2846
2847 pci_sriov_set_totalvfs(pdev, 7);
2848 igb_pci_enable_sriov(pdev, max_vfs);
2849
2850 #endif /* CONFIG_PCI_IOV */
2851 }
2852
2853 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2854 {
2855 struct e1000_hw *hw = &adapter->hw;
2856 u32 max_rss_queues;
2857
2858 /* Determine the maximum number of RSS queues supported. */
2859 switch (hw->mac.type) {
2860 case e1000_i211:
2861 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2862 break;
2863 case e1000_82575:
2864 case e1000_i210:
2865 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2866 break;
2867 case e1000_i350:
2868 /* I350 cannot do RSS and SR-IOV at the same time */
2869 if (!!adapter->vfs_allocated_count) {
2870 max_rss_queues = 1;
2871 break;
2872 }
2873 /* fall through */
2874 case e1000_82576:
2875 if (!!adapter->vfs_allocated_count) {
2876 max_rss_queues = 2;
2877 break;
2878 }
2879 /* fall through */
2880 case e1000_82580:
2881 case e1000_i354:
2882 default:
2883 max_rss_queues = IGB_MAX_RX_QUEUES;
2884 break;
2885 }
2886
2887 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2888
2889 /* Determine if we need to pair queues. */
2890 switch (hw->mac.type) {
2891 case e1000_82575:
2892 case e1000_i211:
2893 /* Device supports enough interrupts without queue pairing. */
2894 break;
2895 case e1000_82576:
2896 /* If VFs are going to be allocated with RSS queues then we
2897 * should pair the queues in order to conserve interrupts due
2898 * to limited supply.
2899 */
2900 if ((adapter->rss_queues > 1) &&
2901 (adapter->vfs_allocated_count > 6))
2902 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2903 /* fall through */
2904 case e1000_82580:
2905 case e1000_i350:
2906 case e1000_i354:
2907 case e1000_i210:
2908 default:
2909 /* If rss_queues > half of max_rss_queues, pair the queues in
2910 * order to conserve interrupts due to limited supply.
2911 */
2912 if (adapter->rss_queues > (max_rss_queues / 2))
2913 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2914 break;
2915 }
2916 }
2917
2918 /**
2919 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2920 * @adapter: board private structure to initialize
2921 *
2922 * igb_sw_init initializes the Adapter private data structure.
2923 * Fields are initialized based on PCI device information and
2924 * OS network device settings (MTU size).
2925 **/
2926 static int igb_sw_init(struct igb_adapter *adapter)
2927 {
2928 struct e1000_hw *hw = &adapter->hw;
2929 struct net_device *netdev = adapter->netdev;
2930 struct pci_dev *pdev = adapter->pdev;
2931
2932 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2933
2934 /* set default ring sizes */
2935 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2936 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2937
2938 /* set default ITR values */
2939 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2940 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2941
2942 /* set default work limits */
2943 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2944
2945 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2946 VLAN_HLEN;
2947 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2948
2949 spin_lock_init(&adapter->stats64_lock);
2950 #ifdef CONFIG_PCI_IOV
2951 switch (hw->mac.type) {
2952 case e1000_82576:
2953 case e1000_i350:
2954 if (max_vfs > 7) {
2955 dev_warn(&pdev->dev,
2956 "Maximum of 7 VFs per PF, using max\n");
2957 max_vfs = adapter->vfs_allocated_count = 7;
2958 } else
2959 adapter->vfs_allocated_count = max_vfs;
2960 if (adapter->vfs_allocated_count)
2961 dev_warn(&pdev->dev,
2962 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2963 break;
2964 default:
2965 break;
2966 }
2967 #endif /* CONFIG_PCI_IOV */
2968
2969 igb_init_queue_configuration(adapter);
2970
2971 /* Setup and initialize a copy of the hw vlan table array */
2972 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2973 GFP_ATOMIC);
2974
2975 /* This call may decrease the number of queues */
2976 if (igb_init_interrupt_scheme(adapter, true)) {
2977 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2978 return -ENOMEM;
2979 }
2980
2981 igb_probe_vfs(adapter);
2982
2983 /* Explicitly disable IRQ since the NIC can be in any state. */
2984 igb_irq_disable(adapter);
2985
2986 if (hw->mac.type >= e1000_i350)
2987 adapter->flags &= ~IGB_FLAG_DMAC;
2988
2989 set_bit(__IGB_DOWN, &adapter->state);
2990 return 0;
2991 }
2992
2993 /**
2994 * igb_open - Called when a network interface is made active
2995 * @netdev: network interface device structure
2996 *
2997 * Returns 0 on success, negative value on failure
2998 *
2999 * The open entry point is called when a network interface is made
3000 * active by the system (IFF_UP). At this point all resources needed
3001 * for transmit and receive operations are allocated, the interrupt
3002 * handler is registered with the OS, the watchdog timer is started,
3003 * and the stack is notified that the interface is ready.
3004 **/
3005 static int __igb_open(struct net_device *netdev, bool resuming)
3006 {
3007 struct igb_adapter *adapter = netdev_priv(netdev);
3008 struct e1000_hw *hw = &adapter->hw;
3009 struct pci_dev *pdev = adapter->pdev;
3010 int err;
3011 int i;
3012
3013 /* disallow open during test */
3014 if (test_bit(__IGB_TESTING, &adapter->state)) {
3015 WARN_ON(resuming);
3016 return -EBUSY;
3017 }
3018
3019 if (!resuming)
3020 pm_runtime_get_sync(&pdev->dev);
3021
3022 netif_carrier_off(netdev);
3023
3024 /* allocate transmit descriptors */
3025 err = igb_setup_all_tx_resources(adapter);
3026 if (err)
3027 goto err_setup_tx;
3028
3029 /* allocate receive descriptors */
3030 err = igb_setup_all_rx_resources(adapter);
3031 if (err)
3032 goto err_setup_rx;
3033
3034 igb_power_up_link(adapter);
3035
3036 /* before we allocate an interrupt, we must be ready to handle it.
3037 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3038 * as soon as we call pci_request_irq, so we have to setup our
3039 * clean_rx handler before we do so.
3040 */
3041 igb_configure(adapter);
3042
3043 err = igb_request_irq(adapter);
3044 if (err)
3045 goto err_req_irq;
3046
3047 /* Notify the stack of the actual queue counts. */
3048 err = netif_set_real_num_tx_queues(adapter->netdev,
3049 adapter->num_tx_queues);
3050 if (err)
3051 goto err_set_queues;
3052
3053 err = netif_set_real_num_rx_queues(adapter->netdev,
3054 adapter->num_rx_queues);
3055 if (err)
3056 goto err_set_queues;
3057
3058 /* From here on the code is the same as igb_up() */
3059 clear_bit(__IGB_DOWN, &adapter->state);
3060
3061 for (i = 0; i < adapter->num_q_vectors; i++)
3062 napi_enable(&(adapter->q_vector[i]->napi));
3063
3064 /* Clear any pending interrupts. */
3065 rd32(E1000_ICR);
3066
3067 igb_irq_enable(adapter);
3068
3069 /* notify VFs that reset has been completed */
3070 if (adapter->vfs_allocated_count) {
3071 u32 reg_data = rd32(E1000_CTRL_EXT);
3072
3073 reg_data |= E1000_CTRL_EXT_PFRSTD;
3074 wr32(E1000_CTRL_EXT, reg_data);
3075 }
3076
3077 netif_tx_start_all_queues(netdev);
3078
3079 if (!resuming)
3080 pm_runtime_put(&pdev->dev);
3081
3082 /* start the watchdog. */
3083 hw->mac.get_link_status = 1;
3084 schedule_work(&adapter->watchdog_task);
3085
3086 return 0;
3087
3088 err_set_queues:
3089 igb_free_irq(adapter);
3090 err_req_irq:
3091 igb_release_hw_control(adapter);
3092 igb_power_down_link(adapter);
3093 igb_free_all_rx_resources(adapter);
3094 err_setup_rx:
3095 igb_free_all_tx_resources(adapter);
3096 err_setup_tx:
3097 igb_reset(adapter);
3098 if (!resuming)
3099 pm_runtime_put(&pdev->dev);
3100
3101 return err;
3102 }
3103
3104 static int igb_open(struct net_device *netdev)
3105 {
3106 return __igb_open(netdev, false);
3107 }
3108
3109 /**
3110 * igb_close - Disables a network interface
3111 * @netdev: network interface device structure
3112 *
3113 * Returns 0, this is not allowed to fail
3114 *
3115 * The close entry point is called when an interface is de-activated
3116 * by the OS. The hardware is still under the driver's control, but
3117 * needs to be disabled. A global MAC reset is issued to stop the
3118 * hardware, and all transmit and receive resources are freed.
3119 **/
3120 static int __igb_close(struct net_device *netdev, bool suspending)
3121 {
3122 struct igb_adapter *adapter = netdev_priv(netdev);
3123 struct pci_dev *pdev = adapter->pdev;
3124
3125 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3126
3127 if (!suspending)
3128 pm_runtime_get_sync(&pdev->dev);
3129
3130 igb_down(adapter);
3131 igb_free_irq(adapter);
3132
3133 igb_free_all_tx_resources(adapter);
3134 igb_free_all_rx_resources(adapter);
3135
3136 if (!suspending)
3137 pm_runtime_put_sync(&pdev->dev);
3138 return 0;
3139 }
3140
3141 static int igb_close(struct net_device *netdev)
3142 {
3143 return __igb_close(netdev, false);
3144 }
3145
3146 /**
3147 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3148 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3149 *
3150 * Return 0 on success, negative on failure
3151 **/
3152 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3153 {
3154 struct device *dev = tx_ring->dev;
3155 int size;
3156
3157 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3158
3159 tx_ring->tx_buffer_info = vzalloc(size);
3160 if (!tx_ring->tx_buffer_info)
3161 goto err;
3162
3163 /* round up to nearest 4K */
3164 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3165 tx_ring->size = ALIGN(tx_ring->size, 4096);
3166
3167 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3168 &tx_ring->dma, GFP_KERNEL);
3169 if (!tx_ring->desc)
3170 goto err;
3171
3172 tx_ring->next_to_use = 0;
3173 tx_ring->next_to_clean = 0;
3174
3175 return 0;
3176
3177 err:
3178 vfree(tx_ring->tx_buffer_info);
3179 tx_ring->tx_buffer_info = NULL;
3180 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3181 return -ENOMEM;
3182 }
3183
3184 /**
3185 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3186 * (Descriptors) for all queues
3187 * @adapter: board private structure
3188 *
3189 * Return 0 on success, negative on failure
3190 **/
3191 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3192 {
3193 struct pci_dev *pdev = adapter->pdev;
3194 int i, err = 0;
3195
3196 for (i = 0; i < adapter->num_tx_queues; i++) {
3197 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3198 if (err) {
3199 dev_err(&pdev->dev,
3200 "Allocation for Tx Queue %u failed\n", i);
3201 for (i--; i >= 0; i--)
3202 igb_free_tx_resources(adapter->tx_ring[i]);
3203 break;
3204 }
3205 }
3206
3207 return err;
3208 }
3209
3210 /**
3211 * igb_setup_tctl - configure the transmit control registers
3212 * @adapter: Board private structure
3213 **/
3214 void igb_setup_tctl(struct igb_adapter *adapter)
3215 {
3216 struct e1000_hw *hw = &adapter->hw;
3217 u32 tctl;
3218
3219 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3220 wr32(E1000_TXDCTL(0), 0);
3221
3222 /* Program the Transmit Control Register */
3223 tctl = rd32(E1000_TCTL);
3224 tctl &= ~E1000_TCTL_CT;
3225 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3226 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3227
3228 igb_config_collision_dist(hw);
3229
3230 /* Enable transmits */
3231 tctl |= E1000_TCTL_EN;
3232
3233 wr32(E1000_TCTL, tctl);
3234 }
3235
3236 /**
3237 * igb_configure_tx_ring - Configure transmit ring after Reset
3238 * @adapter: board private structure
3239 * @ring: tx ring to configure
3240 *
3241 * Configure a transmit ring after a reset.
3242 **/
3243 void igb_configure_tx_ring(struct igb_adapter *adapter,
3244 struct igb_ring *ring)
3245 {
3246 struct e1000_hw *hw = &adapter->hw;
3247 u32 txdctl = 0;
3248 u64 tdba = ring->dma;
3249 int reg_idx = ring->reg_idx;
3250
3251 /* disable the queue */
3252 wr32(E1000_TXDCTL(reg_idx), 0);
3253 wrfl();
3254 mdelay(10);
3255
3256 wr32(E1000_TDLEN(reg_idx),
3257 ring->count * sizeof(union e1000_adv_tx_desc));
3258 wr32(E1000_TDBAL(reg_idx),
3259 tdba & 0x00000000ffffffffULL);
3260 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3261
3262 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3263 wr32(E1000_TDH(reg_idx), 0);
3264 writel(0, ring->tail);
3265
3266 txdctl |= IGB_TX_PTHRESH;
3267 txdctl |= IGB_TX_HTHRESH << 8;
3268 txdctl |= IGB_TX_WTHRESH << 16;
3269
3270 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3271 wr32(E1000_TXDCTL(reg_idx), txdctl);
3272 }
3273
3274 /**
3275 * igb_configure_tx - Configure transmit Unit after Reset
3276 * @adapter: board private structure
3277 *
3278 * Configure the Tx unit of the MAC after a reset.
3279 **/
3280 static void igb_configure_tx(struct igb_adapter *adapter)
3281 {
3282 int i;
3283
3284 for (i = 0; i < adapter->num_tx_queues; i++)
3285 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3286 }
3287
3288 /**
3289 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3290 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3291 *
3292 * Returns 0 on success, negative on failure
3293 **/
3294 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3295 {
3296 struct device *dev = rx_ring->dev;
3297 int size;
3298
3299 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3300
3301 rx_ring->rx_buffer_info = vzalloc(size);
3302 if (!rx_ring->rx_buffer_info)
3303 goto err;
3304
3305 /* Round up to nearest 4K */
3306 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3307 rx_ring->size = ALIGN(rx_ring->size, 4096);
3308
3309 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3310 &rx_ring->dma, GFP_KERNEL);
3311 if (!rx_ring->desc)
3312 goto err;
3313
3314 rx_ring->next_to_alloc = 0;
3315 rx_ring->next_to_clean = 0;
3316 rx_ring->next_to_use = 0;
3317
3318 return 0;
3319
3320 err:
3321 vfree(rx_ring->rx_buffer_info);
3322 rx_ring->rx_buffer_info = NULL;
3323 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3324 return -ENOMEM;
3325 }
3326
3327 /**
3328 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3329 * (Descriptors) for all queues
3330 * @adapter: board private structure
3331 *
3332 * Return 0 on success, negative on failure
3333 **/
3334 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3335 {
3336 struct pci_dev *pdev = adapter->pdev;
3337 int i, err = 0;
3338
3339 for (i = 0; i < adapter->num_rx_queues; i++) {
3340 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3341 if (err) {
3342 dev_err(&pdev->dev,
3343 "Allocation for Rx Queue %u failed\n", i);
3344 for (i--; i >= 0; i--)
3345 igb_free_rx_resources(adapter->rx_ring[i]);
3346 break;
3347 }
3348 }
3349
3350 return err;
3351 }
3352
3353 /**
3354 * igb_setup_mrqc - configure the multiple receive queue control registers
3355 * @adapter: Board private structure
3356 **/
3357 static void igb_setup_mrqc(struct igb_adapter *adapter)
3358 {
3359 struct e1000_hw *hw = &adapter->hw;
3360 u32 mrqc, rxcsum;
3361 u32 j, num_rx_queues;
3362 u32 rss_key[10];
3363
3364 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3365 for (j = 0; j < 10; j++)
3366 wr32(E1000_RSSRK(j), rss_key[j]);
3367
3368 num_rx_queues = adapter->rss_queues;
3369
3370 switch (hw->mac.type) {
3371 case e1000_82576:
3372 /* 82576 supports 2 RSS queues for SR-IOV */
3373 if (adapter->vfs_allocated_count)
3374 num_rx_queues = 2;
3375 break;
3376 default:
3377 break;
3378 }
3379
3380 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3381 for (j = 0; j < IGB_RETA_SIZE; j++)
3382 adapter->rss_indir_tbl[j] =
3383 (j * num_rx_queues) / IGB_RETA_SIZE;
3384 adapter->rss_indir_tbl_init = num_rx_queues;
3385 }
3386 igb_write_rss_indir_tbl(adapter);
3387
3388 /* Disable raw packet checksumming so that RSS hash is placed in
3389 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3390 * offloads as they are enabled by default
3391 */
3392 rxcsum = rd32(E1000_RXCSUM);
3393 rxcsum |= E1000_RXCSUM_PCSD;
3394
3395 if (adapter->hw.mac.type >= e1000_82576)
3396 /* Enable Receive Checksum Offload for SCTP */
3397 rxcsum |= E1000_RXCSUM_CRCOFL;
3398
3399 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3400 wr32(E1000_RXCSUM, rxcsum);
3401
3402 /* Generate RSS hash based on packet types, TCP/UDP
3403 * port numbers and/or IPv4/v6 src and dst addresses
3404 */
3405 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3406 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3407 E1000_MRQC_RSS_FIELD_IPV6 |
3408 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3409 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3410
3411 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3412 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3413 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3414 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3415
3416 /* If VMDq is enabled then we set the appropriate mode for that, else
3417 * we default to RSS so that an RSS hash is calculated per packet even
3418 * if we are only using one queue
3419 */
3420 if (adapter->vfs_allocated_count) {
3421 if (hw->mac.type > e1000_82575) {
3422 /* Set the default pool for the PF's first queue */
3423 u32 vtctl = rd32(E1000_VT_CTL);
3424
3425 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3426 E1000_VT_CTL_DISABLE_DEF_POOL);
3427 vtctl |= adapter->vfs_allocated_count <<
3428 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3429 wr32(E1000_VT_CTL, vtctl);
3430 }
3431 if (adapter->rss_queues > 1)
3432 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3433 else
3434 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3435 } else {
3436 if (hw->mac.type != e1000_i211)
3437 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3438 }
3439 igb_vmm_control(adapter);
3440
3441 wr32(E1000_MRQC, mrqc);
3442 }
3443
3444 /**
3445 * igb_setup_rctl - configure the receive control registers
3446 * @adapter: Board private structure
3447 **/
3448 void igb_setup_rctl(struct igb_adapter *adapter)
3449 {
3450 struct e1000_hw *hw = &adapter->hw;
3451 u32 rctl;
3452
3453 rctl = rd32(E1000_RCTL);
3454
3455 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3456 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3457
3458 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3459 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3460
3461 /* enable stripping of CRC. It's unlikely this will break BMC
3462 * redirection as it did with e1000. Newer features require
3463 * that the HW strips the CRC.
3464 */
3465 rctl |= E1000_RCTL_SECRC;
3466
3467 /* disable store bad packets and clear size bits. */
3468 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3469
3470 /* enable LPE to prevent packets larger than max_frame_size */
3471 rctl |= E1000_RCTL_LPE;
3472
3473 /* disable queue 0 to prevent tail write w/o re-config */
3474 wr32(E1000_RXDCTL(0), 0);
3475
3476 /* Attention!!! For SR-IOV PF driver operations you must enable
3477 * queue drop for all VF and PF queues to prevent head of line blocking
3478 * if an un-trusted VF does not provide descriptors to hardware.
3479 */
3480 if (adapter->vfs_allocated_count) {
3481 /* set all queue drop enable bits */
3482 wr32(E1000_QDE, ALL_QUEUES);
3483 }
3484
3485 /* This is useful for sniffing bad packets. */
3486 if (adapter->netdev->features & NETIF_F_RXALL) {
3487 /* UPE and MPE will be handled by normal PROMISC logic
3488 * in e1000e_set_rx_mode
3489 */
3490 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3491 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3492 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3493
3494 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3495 E1000_RCTL_DPF | /* Allow filtered pause */
3496 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3497 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3498 * and that breaks VLANs.
3499 */
3500 }
3501
3502 wr32(E1000_RCTL, rctl);
3503 }
3504
3505 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3506 int vfn)
3507 {
3508 struct e1000_hw *hw = &adapter->hw;
3509 u32 vmolr;
3510
3511 /* if it isn't the PF check to see if VFs are enabled and
3512 * increase the size to support vlan tags
3513 */
3514 if (vfn < adapter->vfs_allocated_count &&
3515 adapter->vf_data[vfn].vlans_enabled)
3516 size += VLAN_TAG_SIZE;
3517
3518 vmolr = rd32(E1000_VMOLR(vfn));
3519 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3520 vmolr |= size | E1000_VMOLR_LPE;
3521 wr32(E1000_VMOLR(vfn), vmolr);
3522
3523 return 0;
3524 }
3525
3526 /**
3527 * igb_rlpml_set - set maximum receive packet size
3528 * @adapter: board private structure
3529 *
3530 * Configure maximum receivable packet size.
3531 **/
3532 static void igb_rlpml_set(struct igb_adapter *adapter)
3533 {
3534 u32 max_frame_size = adapter->max_frame_size;
3535 struct e1000_hw *hw = &adapter->hw;
3536 u16 pf_id = adapter->vfs_allocated_count;
3537
3538 if (pf_id) {
3539 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3540 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3541 * to our max jumbo frame size, in case we need to enable
3542 * jumbo frames on one of the rings later.
3543 * This will not pass over-length frames into the default
3544 * queue because it's gated by the VMOLR.RLPML.
3545 */
3546 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3547 }
3548
3549 wr32(E1000_RLPML, max_frame_size);
3550 }
3551
3552 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3553 int vfn, bool aupe)
3554 {
3555 struct e1000_hw *hw = &adapter->hw;
3556 u32 vmolr;
3557
3558 /* This register exists only on 82576 and newer so if we are older then
3559 * we should exit and do nothing
3560 */
3561 if (hw->mac.type < e1000_82576)
3562 return;
3563
3564 vmolr = rd32(E1000_VMOLR(vfn));
3565 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3566 if (hw->mac.type == e1000_i350) {
3567 u32 dvmolr;
3568
3569 dvmolr = rd32(E1000_DVMOLR(vfn));
3570 dvmolr |= E1000_DVMOLR_STRVLAN;
3571 wr32(E1000_DVMOLR(vfn), dvmolr);
3572 }
3573 if (aupe)
3574 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3575 else
3576 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3577
3578 /* clear all bits that might not be set */
3579 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3580
3581 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3582 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3583 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3584 * multicast packets
3585 */
3586 if (vfn <= adapter->vfs_allocated_count)
3587 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3588
3589 wr32(E1000_VMOLR(vfn), vmolr);
3590 }
3591
3592 /**
3593 * igb_configure_rx_ring - Configure a receive ring after Reset
3594 * @adapter: board private structure
3595 * @ring: receive ring to be configured
3596 *
3597 * Configure the Rx unit of the MAC after a reset.
3598 **/
3599 void igb_configure_rx_ring(struct igb_adapter *adapter,
3600 struct igb_ring *ring)
3601 {
3602 struct e1000_hw *hw = &adapter->hw;
3603 u64 rdba = ring->dma;
3604 int reg_idx = ring->reg_idx;
3605 u32 srrctl = 0, rxdctl = 0;
3606
3607 /* disable the queue */
3608 wr32(E1000_RXDCTL(reg_idx), 0);
3609
3610 /* Set DMA base address registers */
3611 wr32(E1000_RDBAL(reg_idx),
3612 rdba & 0x00000000ffffffffULL);
3613 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3614 wr32(E1000_RDLEN(reg_idx),
3615 ring->count * sizeof(union e1000_adv_rx_desc));
3616
3617 /* initialize head and tail */
3618 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3619 wr32(E1000_RDH(reg_idx), 0);
3620 writel(0, ring->tail);
3621
3622 /* set descriptor configuration */
3623 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3624 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3625 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3626 if (hw->mac.type >= e1000_82580)
3627 srrctl |= E1000_SRRCTL_TIMESTAMP;
3628 /* Only set Drop Enable if we are supporting multiple queues */
3629 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3630 srrctl |= E1000_SRRCTL_DROP_EN;
3631
3632 wr32(E1000_SRRCTL(reg_idx), srrctl);
3633
3634 /* set filtering for VMDQ pools */
3635 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3636
3637 rxdctl |= IGB_RX_PTHRESH;
3638 rxdctl |= IGB_RX_HTHRESH << 8;
3639 rxdctl |= IGB_RX_WTHRESH << 16;
3640
3641 /* enable receive descriptor fetching */
3642 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3643 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3644 }
3645
3646 /**
3647 * igb_configure_rx - Configure receive Unit after Reset
3648 * @adapter: board private structure
3649 *
3650 * Configure the Rx unit of the MAC after a reset.
3651 **/
3652 static void igb_configure_rx(struct igb_adapter *adapter)
3653 {
3654 int i;
3655
3656 /* set UTA to appropriate mode */
3657 igb_set_uta(adapter);
3658
3659 /* set the correct pool for the PF default MAC address in entry 0 */
3660 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3661 adapter->vfs_allocated_count);
3662
3663 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3664 * the Base and Length of the Rx Descriptor Ring
3665 */
3666 for (i = 0; i < adapter->num_rx_queues; i++)
3667 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3668 }
3669
3670 /**
3671 * igb_free_tx_resources - Free Tx Resources per Queue
3672 * @tx_ring: Tx descriptor ring for a specific queue
3673 *
3674 * Free all transmit software resources
3675 **/
3676 void igb_free_tx_resources(struct igb_ring *tx_ring)
3677 {
3678 igb_clean_tx_ring(tx_ring);
3679
3680 vfree(tx_ring->tx_buffer_info);
3681 tx_ring->tx_buffer_info = NULL;
3682
3683 /* if not set, then don't free */
3684 if (!tx_ring->desc)
3685 return;
3686
3687 dma_free_coherent(tx_ring->dev, tx_ring->size,
3688 tx_ring->desc, tx_ring->dma);
3689
3690 tx_ring->desc = NULL;
3691 }
3692
3693 /**
3694 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3695 * @adapter: board private structure
3696 *
3697 * Free all transmit software resources
3698 **/
3699 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3700 {
3701 int i;
3702
3703 for (i = 0; i < adapter->num_tx_queues; i++)
3704 if (adapter->tx_ring[i])
3705 igb_free_tx_resources(adapter->tx_ring[i]);
3706 }
3707
3708 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3709 struct igb_tx_buffer *tx_buffer)
3710 {
3711 if (tx_buffer->skb) {
3712 dev_kfree_skb_any(tx_buffer->skb);
3713 if (dma_unmap_len(tx_buffer, len))
3714 dma_unmap_single(ring->dev,
3715 dma_unmap_addr(tx_buffer, dma),
3716 dma_unmap_len(tx_buffer, len),
3717 DMA_TO_DEVICE);
3718 } else if (dma_unmap_len(tx_buffer, len)) {
3719 dma_unmap_page(ring->dev,
3720 dma_unmap_addr(tx_buffer, dma),
3721 dma_unmap_len(tx_buffer, len),
3722 DMA_TO_DEVICE);
3723 }
3724 tx_buffer->next_to_watch = NULL;
3725 tx_buffer->skb = NULL;
3726 dma_unmap_len_set(tx_buffer, len, 0);
3727 /* buffer_info must be completely set up in the transmit path */
3728 }
3729
3730 /**
3731 * igb_clean_tx_ring - Free Tx Buffers
3732 * @tx_ring: ring to be cleaned
3733 **/
3734 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3735 {
3736 struct igb_tx_buffer *buffer_info;
3737 unsigned long size;
3738 u16 i;
3739
3740 if (!tx_ring->tx_buffer_info)
3741 return;
3742 /* Free all the Tx ring sk_buffs */
3743
3744 for (i = 0; i < tx_ring->count; i++) {
3745 buffer_info = &tx_ring->tx_buffer_info[i];
3746 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3747 }
3748
3749 netdev_tx_reset_queue(txring_txq(tx_ring));
3750
3751 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3752 memset(tx_ring->tx_buffer_info, 0, size);
3753
3754 /* Zero out the descriptor ring */
3755 memset(tx_ring->desc, 0, tx_ring->size);
3756
3757 tx_ring->next_to_use = 0;
3758 tx_ring->next_to_clean = 0;
3759 }
3760
3761 /**
3762 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3763 * @adapter: board private structure
3764 **/
3765 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3766 {
3767 int i;
3768
3769 for (i = 0; i < adapter->num_tx_queues; i++)
3770 if (adapter->tx_ring[i])
3771 igb_clean_tx_ring(adapter->tx_ring[i]);
3772 }
3773
3774 /**
3775 * igb_free_rx_resources - Free Rx Resources
3776 * @rx_ring: ring to clean the resources from
3777 *
3778 * Free all receive software resources
3779 **/
3780 void igb_free_rx_resources(struct igb_ring *rx_ring)
3781 {
3782 igb_clean_rx_ring(rx_ring);
3783
3784 vfree(rx_ring->rx_buffer_info);
3785 rx_ring->rx_buffer_info = NULL;
3786
3787 /* if not set, then don't free */
3788 if (!rx_ring->desc)
3789 return;
3790
3791 dma_free_coherent(rx_ring->dev, rx_ring->size,
3792 rx_ring->desc, rx_ring->dma);
3793
3794 rx_ring->desc = NULL;
3795 }
3796
3797 /**
3798 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3799 * @adapter: board private structure
3800 *
3801 * Free all receive software resources
3802 **/
3803 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3804 {
3805 int i;
3806
3807 for (i = 0; i < adapter->num_rx_queues; i++)
3808 if (adapter->rx_ring[i])
3809 igb_free_rx_resources(adapter->rx_ring[i]);
3810 }
3811
3812 /**
3813 * igb_clean_rx_ring - Free Rx Buffers per Queue
3814 * @rx_ring: ring to free buffers from
3815 **/
3816 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3817 {
3818 unsigned long size;
3819 u16 i;
3820
3821 if (rx_ring->skb)
3822 dev_kfree_skb(rx_ring->skb);
3823 rx_ring->skb = NULL;
3824
3825 if (!rx_ring->rx_buffer_info)
3826 return;
3827
3828 /* Free all the Rx ring sk_buffs */
3829 for (i = 0; i < rx_ring->count; i++) {
3830 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3831
3832 if (!buffer_info->page)
3833 continue;
3834
3835 dma_unmap_page(rx_ring->dev,
3836 buffer_info->dma,
3837 PAGE_SIZE,
3838 DMA_FROM_DEVICE);
3839 __free_page(buffer_info->page);
3840
3841 buffer_info->page = NULL;
3842 }
3843
3844 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3845 memset(rx_ring->rx_buffer_info, 0, size);
3846
3847 /* Zero out the descriptor ring */
3848 memset(rx_ring->desc, 0, rx_ring->size);
3849
3850 rx_ring->next_to_alloc = 0;
3851 rx_ring->next_to_clean = 0;
3852 rx_ring->next_to_use = 0;
3853 }
3854
3855 /**
3856 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3857 * @adapter: board private structure
3858 **/
3859 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3860 {
3861 int i;
3862
3863 for (i = 0; i < adapter->num_rx_queues; i++)
3864 if (adapter->rx_ring[i])
3865 igb_clean_rx_ring(adapter->rx_ring[i]);
3866 }
3867
3868 /**
3869 * igb_set_mac - Change the Ethernet Address of the NIC
3870 * @netdev: network interface device structure
3871 * @p: pointer to an address structure
3872 *
3873 * Returns 0 on success, negative on failure
3874 **/
3875 static int igb_set_mac(struct net_device *netdev, void *p)
3876 {
3877 struct igb_adapter *adapter = netdev_priv(netdev);
3878 struct e1000_hw *hw = &adapter->hw;
3879 struct sockaddr *addr = p;
3880
3881 if (!is_valid_ether_addr(addr->sa_data))
3882 return -EADDRNOTAVAIL;
3883
3884 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3885 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3886
3887 /* set the correct pool for the new PF MAC address in entry 0 */
3888 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3889 adapter->vfs_allocated_count);
3890
3891 return 0;
3892 }
3893
3894 /**
3895 * igb_write_mc_addr_list - write multicast addresses to MTA
3896 * @netdev: network interface device structure
3897 *
3898 * Writes multicast address list to the MTA hash table.
3899 * Returns: -ENOMEM on failure
3900 * 0 on no addresses written
3901 * X on writing X addresses to MTA
3902 **/
3903 static int igb_write_mc_addr_list(struct net_device *netdev)
3904 {
3905 struct igb_adapter *adapter = netdev_priv(netdev);
3906 struct e1000_hw *hw = &adapter->hw;
3907 struct netdev_hw_addr *ha;
3908 u8 *mta_list;
3909 int i;
3910
3911 if (netdev_mc_empty(netdev)) {
3912 /* nothing to program, so clear mc list */
3913 igb_update_mc_addr_list(hw, NULL, 0);
3914 igb_restore_vf_multicasts(adapter);
3915 return 0;
3916 }
3917
3918 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3919 if (!mta_list)
3920 return -ENOMEM;
3921
3922 /* The shared function expects a packed array of only addresses. */
3923 i = 0;
3924 netdev_for_each_mc_addr(ha, netdev)
3925 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3926
3927 igb_update_mc_addr_list(hw, mta_list, i);
3928 kfree(mta_list);
3929
3930 return netdev_mc_count(netdev);
3931 }
3932
3933 /**
3934 * igb_write_uc_addr_list - write unicast addresses to RAR table
3935 * @netdev: network interface device structure
3936 *
3937 * Writes unicast address list to the RAR table.
3938 * Returns: -ENOMEM on failure/insufficient address space
3939 * 0 on no addresses written
3940 * X on writing X addresses to the RAR table
3941 **/
3942 static int igb_write_uc_addr_list(struct net_device *netdev)
3943 {
3944 struct igb_adapter *adapter = netdev_priv(netdev);
3945 struct e1000_hw *hw = &adapter->hw;
3946 unsigned int vfn = adapter->vfs_allocated_count;
3947 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3948 int count = 0;
3949
3950 /* return ENOMEM indicating insufficient memory for addresses */
3951 if (netdev_uc_count(netdev) > rar_entries)
3952 return -ENOMEM;
3953
3954 if (!netdev_uc_empty(netdev) && rar_entries) {
3955 struct netdev_hw_addr *ha;
3956
3957 netdev_for_each_uc_addr(ha, netdev) {
3958 if (!rar_entries)
3959 break;
3960 igb_rar_set_qsel(adapter, ha->addr,
3961 rar_entries--,
3962 vfn);
3963 count++;
3964 }
3965 }
3966 /* write the addresses in reverse order to avoid write combining */
3967 for (; rar_entries > 0 ; rar_entries--) {
3968 wr32(E1000_RAH(rar_entries), 0);
3969 wr32(E1000_RAL(rar_entries), 0);
3970 }
3971 wrfl();
3972
3973 return count;
3974 }
3975
3976 /**
3977 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3978 * @netdev: network interface device structure
3979 *
3980 * The set_rx_mode entry point is called whenever the unicast or multicast
3981 * address lists or the network interface flags are updated. This routine is
3982 * responsible for configuring the hardware for proper unicast, multicast,
3983 * promiscuous mode, and all-multi behavior.
3984 **/
3985 static void igb_set_rx_mode(struct net_device *netdev)
3986 {
3987 struct igb_adapter *adapter = netdev_priv(netdev);
3988 struct e1000_hw *hw = &adapter->hw;
3989 unsigned int vfn = adapter->vfs_allocated_count;
3990 u32 rctl, vmolr = 0;
3991 int count;
3992
3993 /* Check for Promiscuous and All Multicast modes */
3994 rctl = rd32(E1000_RCTL);
3995
3996 /* clear the effected bits */
3997 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3998
3999 if (netdev->flags & IFF_PROMISC) {
4000 /* retain VLAN HW filtering if in VT mode */
4001 if (adapter->vfs_allocated_count)
4002 rctl |= E1000_RCTL_VFE;
4003 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4004 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4005 } else {
4006 if (netdev->flags & IFF_ALLMULTI) {
4007 rctl |= E1000_RCTL_MPE;
4008 vmolr |= E1000_VMOLR_MPME;
4009 } else {
4010 /* Write addresses to the MTA, if the attempt fails
4011 * then we should just turn on promiscuous mode so
4012 * that we can at least receive multicast traffic
4013 */
4014 count = igb_write_mc_addr_list(netdev);
4015 if (count < 0) {
4016 rctl |= E1000_RCTL_MPE;
4017 vmolr |= E1000_VMOLR_MPME;
4018 } else if (count) {
4019 vmolr |= E1000_VMOLR_ROMPE;
4020 }
4021 }
4022 /* Write addresses to available RAR registers, if there is not
4023 * sufficient space to store all the addresses then enable
4024 * unicast promiscuous mode
4025 */
4026 count = igb_write_uc_addr_list(netdev);
4027 if (count < 0) {
4028 rctl |= E1000_RCTL_UPE;
4029 vmolr |= E1000_VMOLR_ROPE;
4030 }
4031 rctl |= E1000_RCTL_VFE;
4032 }
4033 wr32(E1000_RCTL, rctl);
4034
4035 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4036 * the VMOLR to enable the appropriate modes. Without this workaround
4037 * we will have issues with VLAN tag stripping not being done for frames
4038 * that are only arriving because we are the default pool
4039 */
4040 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4041 return;
4042
4043 vmolr |= rd32(E1000_VMOLR(vfn)) &
4044 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4045 wr32(E1000_VMOLR(vfn), vmolr);
4046 igb_restore_vf_multicasts(adapter);
4047 }
4048
4049 static void igb_check_wvbr(struct igb_adapter *adapter)
4050 {
4051 struct e1000_hw *hw = &adapter->hw;
4052 u32 wvbr = 0;
4053
4054 switch (hw->mac.type) {
4055 case e1000_82576:
4056 case e1000_i350:
4057 wvbr = rd32(E1000_WVBR);
4058 if (!wvbr)
4059 return;
4060 break;
4061 default:
4062 break;
4063 }
4064
4065 adapter->wvbr |= wvbr;
4066 }
4067
4068 #define IGB_STAGGERED_QUEUE_OFFSET 8
4069
4070 static void igb_spoof_check(struct igb_adapter *adapter)
4071 {
4072 int j;
4073
4074 if (!adapter->wvbr)
4075 return;
4076
4077 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4078 if (adapter->wvbr & (1 << j) ||
4079 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4080 dev_warn(&adapter->pdev->dev,
4081 "Spoof event(s) detected on VF %d\n", j);
4082 adapter->wvbr &=
4083 ~((1 << j) |
4084 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4085 }
4086 }
4087 }
4088
4089 /* Need to wait a few seconds after link up to get diagnostic information from
4090 * the phy
4091 */
4092 static void igb_update_phy_info(unsigned long data)
4093 {
4094 struct igb_adapter *adapter = (struct igb_adapter *) data;
4095 igb_get_phy_info(&adapter->hw);
4096 }
4097
4098 /**
4099 * igb_has_link - check shared code for link and determine up/down
4100 * @adapter: pointer to driver private info
4101 **/
4102 bool igb_has_link(struct igb_adapter *adapter)
4103 {
4104 struct e1000_hw *hw = &adapter->hw;
4105 bool link_active = false;
4106
4107 /* get_link_status is set on LSC (link status) interrupt or
4108 * rx sequence error interrupt. get_link_status will stay
4109 * false until the e1000_check_for_link establishes link
4110 * for copper adapters ONLY
4111 */
4112 switch (hw->phy.media_type) {
4113 case e1000_media_type_copper:
4114 if (!hw->mac.get_link_status)
4115 return true;
4116 case e1000_media_type_internal_serdes:
4117 hw->mac.ops.check_for_link(hw);
4118 link_active = !hw->mac.get_link_status;
4119 break;
4120 default:
4121 case e1000_media_type_unknown:
4122 break;
4123 }
4124
4125 if (((hw->mac.type == e1000_i210) ||
4126 (hw->mac.type == e1000_i211)) &&
4127 (hw->phy.id == I210_I_PHY_ID)) {
4128 if (!netif_carrier_ok(adapter->netdev)) {
4129 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4130 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4131 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4132 adapter->link_check_timeout = jiffies;
4133 }
4134 }
4135
4136 return link_active;
4137 }
4138
4139 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4140 {
4141 bool ret = false;
4142 u32 ctrl_ext, thstat;
4143
4144 /* check for thermal sensor event on i350 copper only */
4145 if (hw->mac.type == e1000_i350) {
4146 thstat = rd32(E1000_THSTAT);
4147 ctrl_ext = rd32(E1000_CTRL_EXT);
4148
4149 if ((hw->phy.media_type == e1000_media_type_copper) &&
4150 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4151 ret = !!(thstat & event);
4152 }
4153
4154 return ret;
4155 }
4156
4157 /**
4158 * igb_check_lvmmc - check for malformed packets received
4159 * and indicated in LVMMC register
4160 * @adapter: pointer to adapter
4161 **/
4162 static void igb_check_lvmmc(struct igb_adapter *adapter)
4163 {
4164 struct e1000_hw *hw = &adapter->hw;
4165 u32 lvmmc;
4166
4167 lvmmc = rd32(E1000_LVMMC);
4168 if (lvmmc) {
4169 if (unlikely(net_ratelimit())) {
4170 netdev_warn(adapter->netdev,
4171 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4172 lvmmc);
4173 }
4174 }
4175 }
4176
4177 /**
4178 * igb_watchdog - Timer Call-back
4179 * @data: pointer to adapter cast into an unsigned long
4180 **/
4181 static void igb_watchdog(unsigned long data)
4182 {
4183 struct igb_adapter *adapter = (struct igb_adapter *)data;
4184 /* Do the rest outside of interrupt context */
4185 schedule_work(&adapter->watchdog_task);
4186 }
4187
4188 static void igb_watchdog_task(struct work_struct *work)
4189 {
4190 struct igb_adapter *adapter = container_of(work,
4191 struct igb_adapter,
4192 watchdog_task);
4193 struct e1000_hw *hw = &adapter->hw;
4194 struct e1000_phy_info *phy = &hw->phy;
4195 struct net_device *netdev = adapter->netdev;
4196 u32 link;
4197 int i;
4198 u32 connsw;
4199
4200 link = igb_has_link(adapter);
4201
4202 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4203 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4204 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4205 else
4206 link = false;
4207 }
4208
4209 /* Force link down if we have fiber to swap to */
4210 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4211 if (hw->phy.media_type == e1000_media_type_copper) {
4212 connsw = rd32(E1000_CONNSW);
4213 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4214 link = 0;
4215 }
4216 }
4217 if (link) {
4218 /* Perform a reset if the media type changed. */
4219 if (hw->dev_spec._82575.media_changed) {
4220 hw->dev_spec._82575.media_changed = false;
4221 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4222 igb_reset(adapter);
4223 }
4224 /* Cancel scheduled suspend requests. */
4225 pm_runtime_resume(netdev->dev.parent);
4226
4227 if (!netif_carrier_ok(netdev)) {
4228 u32 ctrl;
4229
4230 hw->mac.ops.get_speed_and_duplex(hw,
4231 &adapter->link_speed,
4232 &adapter->link_duplex);
4233
4234 ctrl = rd32(E1000_CTRL);
4235 /* Links status message must follow this format */
4236 netdev_info(netdev,
4237 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4238 netdev->name,
4239 adapter->link_speed,
4240 adapter->link_duplex == FULL_DUPLEX ?
4241 "Full" : "Half",
4242 (ctrl & E1000_CTRL_TFCE) &&
4243 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4244 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4245 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4246
4247 /* disable EEE if enabled */
4248 if ((adapter->flags & IGB_FLAG_EEE) &&
4249 (adapter->link_duplex == HALF_DUPLEX)) {
4250 dev_info(&adapter->pdev->dev,
4251 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4252 adapter->hw.dev_spec._82575.eee_disable = true;
4253 adapter->flags &= ~IGB_FLAG_EEE;
4254 }
4255
4256 /* check if SmartSpeed worked */
4257 igb_check_downshift(hw);
4258 if (phy->speed_downgraded)
4259 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4260
4261 /* check for thermal sensor event */
4262 if (igb_thermal_sensor_event(hw,
4263 E1000_THSTAT_LINK_THROTTLE))
4264 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4265
4266 /* adjust timeout factor according to speed/duplex */
4267 adapter->tx_timeout_factor = 1;
4268 switch (adapter->link_speed) {
4269 case SPEED_10:
4270 adapter->tx_timeout_factor = 14;
4271 break;
4272 case SPEED_100:
4273 /* maybe add some timeout factor ? */
4274 break;
4275 }
4276
4277 netif_carrier_on(netdev);
4278
4279 igb_ping_all_vfs(adapter);
4280 igb_check_vf_rate_limit(adapter);
4281
4282 /* link state has changed, schedule phy info update */
4283 if (!test_bit(__IGB_DOWN, &adapter->state))
4284 mod_timer(&adapter->phy_info_timer,
4285 round_jiffies(jiffies + 2 * HZ));
4286 }
4287 } else {
4288 if (netif_carrier_ok(netdev)) {
4289 adapter->link_speed = 0;
4290 adapter->link_duplex = 0;
4291
4292 /* check for thermal sensor event */
4293 if (igb_thermal_sensor_event(hw,
4294 E1000_THSTAT_PWR_DOWN)) {
4295 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4296 }
4297
4298 /* Links status message must follow this format */
4299 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4300 netdev->name);
4301 netif_carrier_off(netdev);
4302
4303 igb_ping_all_vfs(adapter);
4304
4305 /* link state has changed, schedule phy info update */
4306 if (!test_bit(__IGB_DOWN, &adapter->state))
4307 mod_timer(&adapter->phy_info_timer,
4308 round_jiffies(jiffies + 2 * HZ));
4309
4310 /* link is down, time to check for alternate media */
4311 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4312 igb_check_swap_media(adapter);
4313 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4314 schedule_work(&adapter->reset_task);
4315 /* return immediately */
4316 return;
4317 }
4318 }
4319 pm_schedule_suspend(netdev->dev.parent,
4320 MSEC_PER_SEC * 5);
4321
4322 /* also check for alternate media here */
4323 } else if (!netif_carrier_ok(netdev) &&
4324 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4325 igb_check_swap_media(adapter);
4326 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4327 schedule_work(&adapter->reset_task);
4328 /* return immediately */
4329 return;
4330 }
4331 }
4332 }
4333
4334 spin_lock(&adapter->stats64_lock);
4335 igb_update_stats(adapter, &adapter->stats64);
4336 spin_unlock(&adapter->stats64_lock);
4337
4338 for (i = 0; i < adapter->num_tx_queues; i++) {
4339 struct igb_ring *tx_ring = adapter->tx_ring[i];
4340 if (!netif_carrier_ok(netdev)) {
4341 /* We've lost link, so the controller stops DMA,
4342 * but we've got queued Tx work that's never going
4343 * to get done, so reset controller to flush Tx.
4344 * (Do the reset outside of interrupt context).
4345 */
4346 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4347 adapter->tx_timeout_count++;
4348 schedule_work(&adapter->reset_task);
4349 /* return immediately since reset is imminent */
4350 return;
4351 }
4352 }
4353
4354 /* Force detection of hung controller every watchdog period */
4355 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4356 }
4357
4358 /* Cause software interrupt to ensure Rx ring is cleaned */
4359 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4360 u32 eics = 0;
4361
4362 for (i = 0; i < adapter->num_q_vectors; i++)
4363 eics |= adapter->q_vector[i]->eims_value;
4364 wr32(E1000_EICS, eics);
4365 } else {
4366 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4367 }
4368
4369 igb_spoof_check(adapter);
4370 igb_ptp_rx_hang(adapter);
4371
4372 /* Check LVMMC register on i350/i354 only */
4373 if ((adapter->hw.mac.type == e1000_i350) ||
4374 (adapter->hw.mac.type == e1000_i354))
4375 igb_check_lvmmc(adapter);
4376
4377 /* Reset the timer */
4378 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4379 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4380 mod_timer(&adapter->watchdog_timer,
4381 round_jiffies(jiffies + HZ));
4382 else
4383 mod_timer(&adapter->watchdog_timer,
4384 round_jiffies(jiffies + 2 * HZ));
4385 }
4386 }
4387
4388 enum latency_range {
4389 lowest_latency = 0,
4390 low_latency = 1,
4391 bulk_latency = 2,
4392 latency_invalid = 255
4393 };
4394
4395 /**
4396 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4397 * @q_vector: pointer to q_vector
4398 *
4399 * Stores a new ITR value based on strictly on packet size. This
4400 * algorithm is less sophisticated than that used in igb_update_itr,
4401 * due to the difficulty of synchronizing statistics across multiple
4402 * receive rings. The divisors and thresholds used by this function
4403 * were determined based on theoretical maximum wire speed and testing
4404 * data, in order to minimize response time while increasing bulk
4405 * throughput.
4406 * This functionality is controlled by ethtool's coalescing settings.
4407 * NOTE: This function is called only when operating in a multiqueue
4408 * receive environment.
4409 **/
4410 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4411 {
4412 int new_val = q_vector->itr_val;
4413 int avg_wire_size = 0;
4414 struct igb_adapter *adapter = q_vector->adapter;
4415 unsigned int packets;
4416
4417 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4418 * ints/sec - ITR timer value of 120 ticks.
4419 */
4420 if (adapter->link_speed != SPEED_1000) {
4421 new_val = IGB_4K_ITR;
4422 goto set_itr_val;
4423 }
4424
4425 packets = q_vector->rx.total_packets;
4426 if (packets)
4427 avg_wire_size = q_vector->rx.total_bytes / packets;
4428
4429 packets = q_vector->tx.total_packets;
4430 if (packets)
4431 avg_wire_size = max_t(u32, avg_wire_size,
4432 q_vector->tx.total_bytes / packets);
4433
4434 /* if avg_wire_size isn't set no work was done */
4435 if (!avg_wire_size)
4436 goto clear_counts;
4437
4438 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4439 avg_wire_size += 24;
4440
4441 /* Don't starve jumbo frames */
4442 avg_wire_size = min(avg_wire_size, 3000);
4443
4444 /* Give a little boost to mid-size frames */
4445 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4446 new_val = avg_wire_size / 3;
4447 else
4448 new_val = avg_wire_size / 2;
4449
4450 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4451 if (new_val < IGB_20K_ITR &&
4452 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4453 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4454 new_val = IGB_20K_ITR;
4455
4456 set_itr_val:
4457 if (new_val != q_vector->itr_val) {
4458 q_vector->itr_val = new_val;
4459 q_vector->set_itr = 1;
4460 }
4461 clear_counts:
4462 q_vector->rx.total_bytes = 0;
4463 q_vector->rx.total_packets = 0;
4464 q_vector->tx.total_bytes = 0;
4465 q_vector->tx.total_packets = 0;
4466 }
4467
4468 /**
4469 * igb_update_itr - update the dynamic ITR value based on statistics
4470 * @q_vector: pointer to q_vector
4471 * @ring_container: ring info to update the itr for
4472 *
4473 * Stores a new ITR value based on packets and byte
4474 * counts during the last interrupt. The advantage of per interrupt
4475 * computation is faster updates and more accurate ITR for the current
4476 * traffic pattern. Constants in this function were computed
4477 * based on theoretical maximum wire speed and thresholds were set based
4478 * on testing data as well as attempting to minimize response time
4479 * while increasing bulk throughput.
4480 * This functionality is controlled by ethtool's coalescing settings.
4481 * NOTE: These calculations are only valid when operating in a single-
4482 * queue environment.
4483 **/
4484 static void igb_update_itr(struct igb_q_vector *q_vector,
4485 struct igb_ring_container *ring_container)
4486 {
4487 unsigned int packets = ring_container->total_packets;
4488 unsigned int bytes = ring_container->total_bytes;
4489 u8 itrval = ring_container->itr;
4490
4491 /* no packets, exit with status unchanged */
4492 if (packets == 0)
4493 return;
4494
4495 switch (itrval) {
4496 case lowest_latency:
4497 /* handle TSO and jumbo frames */
4498 if (bytes/packets > 8000)
4499 itrval = bulk_latency;
4500 else if ((packets < 5) && (bytes > 512))
4501 itrval = low_latency;
4502 break;
4503 case low_latency: /* 50 usec aka 20000 ints/s */
4504 if (bytes > 10000) {
4505 /* this if handles the TSO accounting */
4506 if (bytes/packets > 8000)
4507 itrval = bulk_latency;
4508 else if ((packets < 10) || ((bytes/packets) > 1200))
4509 itrval = bulk_latency;
4510 else if ((packets > 35))
4511 itrval = lowest_latency;
4512 } else if (bytes/packets > 2000) {
4513 itrval = bulk_latency;
4514 } else if (packets <= 2 && bytes < 512) {
4515 itrval = lowest_latency;
4516 }
4517 break;
4518 case bulk_latency: /* 250 usec aka 4000 ints/s */
4519 if (bytes > 25000) {
4520 if (packets > 35)
4521 itrval = low_latency;
4522 } else if (bytes < 1500) {
4523 itrval = low_latency;
4524 }
4525 break;
4526 }
4527
4528 /* clear work counters since we have the values we need */
4529 ring_container->total_bytes = 0;
4530 ring_container->total_packets = 0;
4531
4532 /* write updated itr to ring container */
4533 ring_container->itr = itrval;
4534 }
4535
4536 static void igb_set_itr(struct igb_q_vector *q_vector)
4537 {
4538 struct igb_adapter *adapter = q_vector->adapter;
4539 u32 new_itr = q_vector->itr_val;
4540 u8 current_itr = 0;
4541
4542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4543 if (adapter->link_speed != SPEED_1000) {
4544 current_itr = 0;
4545 new_itr = IGB_4K_ITR;
4546 goto set_itr_now;
4547 }
4548
4549 igb_update_itr(q_vector, &q_vector->tx);
4550 igb_update_itr(q_vector, &q_vector->rx);
4551
4552 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4553
4554 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4555 if (current_itr == lowest_latency &&
4556 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4557 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4558 current_itr = low_latency;
4559
4560 switch (current_itr) {
4561 /* counts and packets in update_itr are dependent on these numbers */
4562 case lowest_latency:
4563 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4564 break;
4565 case low_latency:
4566 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4567 break;
4568 case bulk_latency:
4569 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4570 break;
4571 default:
4572 break;
4573 }
4574
4575 set_itr_now:
4576 if (new_itr != q_vector->itr_val) {
4577 /* this attempts to bias the interrupt rate towards Bulk
4578 * by adding intermediate steps when interrupt rate is
4579 * increasing
4580 */
4581 new_itr = new_itr > q_vector->itr_val ?
4582 max((new_itr * q_vector->itr_val) /
4583 (new_itr + (q_vector->itr_val >> 2)),
4584 new_itr) : new_itr;
4585 /* Don't write the value here; it resets the adapter's
4586 * internal timer, and causes us to delay far longer than
4587 * we should between interrupts. Instead, we write the ITR
4588 * value at the beginning of the next interrupt so the timing
4589 * ends up being correct.
4590 */
4591 q_vector->itr_val = new_itr;
4592 q_vector->set_itr = 1;
4593 }
4594 }
4595
4596 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4597 u32 type_tucmd, u32 mss_l4len_idx)
4598 {
4599 struct e1000_adv_tx_context_desc *context_desc;
4600 u16 i = tx_ring->next_to_use;
4601
4602 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4603
4604 i++;
4605 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4606
4607 /* set bits to identify this as an advanced context descriptor */
4608 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4609
4610 /* For 82575, context index must be unique per ring. */
4611 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4612 mss_l4len_idx |= tx_ring->reg_idx << 4;
4613
4614 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4615 context_desc->seqnum_seed = 0;
4616 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4617 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4618 }
4619
4620 static int igb_tso(struct igb_ring *tx_ring,
4621 struct igb_tx_buffer *first,
4622 u8 *hdr_len)
4623 {
4624 struct sk_buff *skb = first->skb;
4625 u32 vlan_macip_lens, type_tucmd;
4626 u32 mss_l4len_idx, l4len;
4627 int err;
4628
4629 if (skb->ip_summed != CHECKSUM_PARTIAL)
4630 return 0;
4631
4632 if (!skb_is_gso(skb))
4633 return 0;
4634
4635 err = skb_cow_head(skb, 0);
4636 if (err < 0)
4637 return err;
4638
4639 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4640 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4641
4642 if (first->protocol == htons(ETH_P_IP)) {
4643 struct iphdr *iph = ip_hdr(skb);
4644 iph->tot_len = 0;
4645 iph->check = 0;
4646 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4647 iph->daddr, 0,
4648 IPPROTO_TCP,
4649 0);
4650 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4651 first->tx_flags |= IGB_TX_FLAGS_TSO |
4652 IGB_TX_FLAGS_CSUM |
4653 IGB_TX_FLAGS_IPV4;
4654 } else if (skb_is_gso_v6(skb)) {
4655 ipv6_hdr(skb)->payload_len = 0;
4656 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4657 &ipv6_hdr(skb)->daddr,
4658 0, IPPROTO_TCP, 0);
4659 first->tx_flags |= IGB_TX_FLAGS_TSO |
4660 IGB_TX_FLAGS_CSUM;
4661 }
4662
4663 /* compute header lengths */
4664 l4len = tcp_hdrlen(skb);
4665 *hdr_len = skb_transport_offset(skb) + l4len;
4666
4667 /* update gso size and bytecount with header size */
4668 first->gso_segs = skb_shinfo(skb)->gso_segs;
4669 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4670
4671 /* MSS L4LEN IDX */
4672 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4673 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4674
4675 /* VLAN MACLEN IPLEN */
4676 vlan_macip_lens = skb_network_header_len(skb);
4677 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4678 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4679
4680 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4681
4682 return 1;
4683 }
4684
4685 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4686 {
4687 struct sk_buff *skb = first->skb;
4688 u32 vlan_macip_lens = 0;
4689 u32 mss_l4len_idx = 0;
4690 u32 type_tucmd = 0;
4691
4692 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4693 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4694 return;
4695 } else {
4696 u8 l4_hdr = 0;
4697
4698 switch (first->protocol) {
4699 case htons(ETH_P_IP):
4700 vlan_macip_lens |= skb_network_header_len(skb);
4701 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4702 l4_hdr = ip_hdr(skb)->protocol;
4703 break;
4704 case htons(ETH_P_IPV6):
4705 vlan_macip_lens |= skb_network_header_len(skb);
4706 l4_hdr = ipv6_hdr(skb)->nexthdr;
4707 break;
4708 default:
4709 if (unlikely(net_ratelimit())) {
4710 dev_warn(tx_ring->dev,
4711 "partial checksum but proto=%x!\n",
4712 first->protocol);
4713 }
4714 break;
4715 }
4716
4717 switch (l4_hdr) {
4718 case IPPROTO_TCP:
4719 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4720 mss_l4len_idx = tcp_hdrlen(skb) <<
4721 E1000_ADVTXD_L4LEN_SHIFT;
4722 break;
4723 case IPPROTO_SCTP:
4724 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4725 mss_l4len_idx = sizeof(struct sctphdr) <<
4726 E1000_ADVTXD_L4LEN_SHIFT;
4727 break;
4728 case IPPROTO_UDP:
4729 mss_l4len_idx = sizeof(struct udphdr) <<
4730 E1000_ADVTXD_L4LEN_SHIFT;
4731 break;
4732 default:
4733 if (unlikely(net_ratelimit())) {
4734 dev_warn(tx_ring->dev,
4735 "partial checksum but l4 proto=%x!\n",
4736 l4_hdr);
4737 }
4738 break;
4739 }
4740
4741 /* update TX checksum flag */
4742 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4743 }
4744
4745 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4746 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4747
4748 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4749 }
4750
4751 #define IGB_SET_FLAG(_input, _flag, _result) \
4752 ((_flag <= _result) ? \
4753 ((u32)(_input & _flag) * (_result / _flag)) : \
4754 ((u32)(_input & _flag) / (_flag / _result)))
4755
4756 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4757 {
4758 /* set type for advanced descriptor with frame checksum insertion */
4759 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4760 E1000_ADVTXD_DCMD_DEXT |
4761 E1000_ADVTXD_DCMD_IFCS;
4762
4763 /* set HW vlan bit if vlan is present */
4764 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4765 (E1000_ADVTXD_DCMD_VLE));
4766
4767 /* set segmentation bits for TSO */
4768 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4769 (E1000_ADVTXD_DCMD_TSE));
4770
4771 /* set timestamp bit if present */
4772 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4773 (E1000_ADVTXD_MAC_TSTAMP));
4774
4775 /* insert frame checksum */
4776 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4777
4778 return cmd_type;
4779 }
4780
4781 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4782 union e1000_adv_tx_desc *tx_desc,
4783 u32 tx_flags, unsigned int paylen)
4784 {
4785 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4786
4787 /* 82575 requires a unique index per ring */
4788 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4789 olinfo_status |= tx_ring->reg_idx << 4;
4790
4791 /* insert L4 checksum */
4792 olinfo_status |= IGB_SET_FLAG(tx_flags,
4793 IGB_TX_FLAGS_CSUM,
4794 (E1000_TXD_POPTS_TXSM << 8));
4795
4796 /* insert IPv4 checksum */
4797 olinfo_status |= IGB_SET_FLAG(tx_flags,
4798 IGB_TX_FLAGS_IPV4,
4799 (E1000_TXD_POPTS_IXSM << 8));
4800
4801 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4802 }
4803
4804 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4805 {
4806 struct net_device *netdev = tx_ring->netdev;
4807
4808 netif_stop_subqueue(netdev, tx_ring->queue_index);
4809
4810 /* Herbert's original patch had:
4811 * smp_mb__after_netif_stop_queue();
4812 * but since that doesn't exist yet, just open code it.
4813 */
4814 smp_mb();
4815
4816 /* We need to check again in a case another CPU has just
4817 * made room available.
4818 */
4819 if (igb_desc_unused(tx_ring) < size)
4820 return -EBUSY;
4821
4822 /* A reprieve! */
4823 netif_wake_subqueue(netdev, tx_ring->queue_index);
4824
4825 u64_stats_update_begin(&tx_ring->tx_syncp2);
4826 tx_ring->tx_stats.restart_queue2++;
4827 u64_stats_update_end(&tx_ring->tx_syncp2);
4828
4829 return 0;
4830 }
4831
4832 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4833 {
4834 if (igb_desc_unused(tx_ring) >= size)
4835 return 0;
4836 return __igb_maybe_stop_tx(tx_ring, size);
4837 }
4838
4839 static void igb_tx_map(struct igb_ring *tx_ring,
4840 struct igb_tx_buffer *first,
4841 const u8 hdr_len)
4842 {
4843 struct sk_buff *skb = first->skb;
4844 struct igb_tx_buffer *tx_buffer;
4845 union e1000_adv_tx_desc *tx_desc;
4846 struct skb_frag_struct *frag;
4847 dma_addr_t dma;
4848 unsigned int data_len, size;
4849 u32 tx_flags = first->tx_flags;
4850 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4851 u16 i = tx_ring->next_to_use;
4852
4853 tx_desc = IGB_TX_DESC(tx_ring, i);
4854
4855 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4856
4857 size = skb_headlen(skb);
4858 data_len = skb->data_len;
4859
4860 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4861
4862 tx_buffer = first;
4863
4864 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4865 if (dma_mapping_error(tx_ring->dev, dma))
4866 goto dma_error;
4867
4868 /* record length, and DMA address */
4869 dma_unmap_len_set(tx_buffer, len, size);
4870 dma_unmap_addr_set(tx_buffer, dma, dma);
4871
4872 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4873
4874 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4875 tx_desc->read.cmd_type_len =
4876 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4877
4878 i++;
4879 tx_desc++;
4880 if (i == tx_ring->count) {
4881 tx_desc = IGB_TX_DESC(tx_ring, 0);
4882 i = 0;
4883 }
4884 tx_desc->read.olinfo_status = 0;
4885
4886 dma += IGB_MAX_DATA_PER_TXD;
4887 size -= IGB_MAX_DATA_PER_TXD;
4888
4889 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4890 }
4891
4892 if (likely(!data_len))
4893 break;
4894
4895 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4896
4897 i++;
4898 tx_desc++;
4899 if (i == tx_ring->count) {
4900 tx_desc = IGB_TX_DESC(tx_ring, 0);
4901 i = 0;
4902 }
4903 tx_desc->read.olinfo_status = 0;
4904
4905 size = skb_frag_size(frag);
4906 data_len -= size;
4907
4908 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4909 size, DMA_TO_DEVICE);
4910
4911 tx_buffer = &tx_ring->tx_buffer_info[i];
4912 }
4913
4914 /* write last descriptor with RS and EOP bits */
4915 cmd_type |= size | IGB_TXD_DCMD;
4916 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4917
4918 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4919
4920 /* set the timestamp */
4921 first->time_stamp = jiffies;
4922
4923 /* Force memory writes to complete before letting h/w know there
4924 * are new descriptors to fetch. (Only applicable for weak-ordered
4925 * memory model archs, such as IA-64).
4926 *
4927 * We also need this memory barrier to make certain all of the
4928 * status bits have been updated before next_to_watch is written.
4929 */
4930 wmb();
4931
4932 /* set next_to_watch value indicating a packet is present */
4933 first->next_to_watch = tx_desc;
4934
4935 i++;
4936 if (i == tx_ring->count)
4937 i = 0;
4938
4939 tx_ring->next_to_use = i;
4940
4941 /* Make sure there is space in the ring for the next send. */
4942 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4943
4944 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4945 writel(i, tx_ring->tail);
4946
4947 /* we need this if more than one processor can write to our tail
4948 * at a time, it synchronizes IO on IA64/Altix systems
4949 */
4950 mmiowb();
4951 }
4952 return;
4953
4954 dma_error:
4955 dev_err(tx_ring->dev, "TX DMA map failed\n");
4956
4957 /* clear dma mappings for failed tx_buffer_info map */
4958 for (;;) {
4959 tx_buffer = &tx_ring->tx_buffer_info[i];
4960 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4961 if (tx_buffer == first)
4962 break;
4963 if (i == 0)
4964 i = tx_ring->count;
4965 i--;
4966 }
4967
4968 tx_ring->next_to_use = i;
4969 }
4970
4971 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4972 struct igb_ring *tx_ring)
4973 {
4974 struct igb_tx_buffer *first;
4975 int tso;
4976 u32 tx_flags = 0;
4977 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4978 __be16 protocol = vlan_get_protocol(skb);
4979 u8 hdr_len = 0;
4980
4981 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4982 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4983 * + 2 desc gap to keep tail from touching head,
4984 * + 1 desc for context descriptor,
4985 * otherwise try next time
4986 */
4987 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4988 unsigned short f;
4989
4990 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4991 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4992 } else {
4993 count += skb_shinfo(skb)->nr_frags;
4994 }
4995
4996 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4997 /* this is a hard error */
4998 return NETDEV_TX_BUSY;
4999 }
5000
5001 /* record the location of the first descriptor for this packet */
5002 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5003 first->skb = skb;
5004 first->bytecount = skb->len;
5005 first->gso_segs = 1;
5006
5007 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5008 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5009
5010 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5011 &adapter->state)) {
5012 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5013 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5014
5015 adapter->ptp_tx_skb = skb_get(skb);
5016 adapter->ptp_tx_start = jiffies;
5017 if (adapter->hw.mac.type == e1000_82576)
5018 schedule_work(&adapter->ptp_tx_work);
5019 }
5020 }
5021
5022 skb_tx_timestamp(skb);
5023
5024 if (skb_vlan_tag_present(skb)) {
5025 tx_flags |= IGB_TX_FLAGS_VLAN;
5026 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5027 }
5028
5029 /* record initial flags and protocol */
5030 first->tx_flags = tx_flags;
5031 first->protocol = protocol;
5032
5033 tso = igb_tso(tx_ring, first, &hdr_len);
5034 if (tso < 0)
5035 goto out_drop;
5036 else if (!tso)
5037 igb_tx_csum(tx_ring, first);
5038
5039 igb_tx_map(tx_ring, first, hdr_len);
5040
5041 return NETDEV_TX_OK;
5042
5043 out_drop:
5044 igb_unmap_and_free_tx_resource(tx_ring, first);
5045
5046 return NETDEV_TX_OK;
5047 }
5048
5049 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5050 struct sk_buff *skb)
5051 {
5052 unsigned int r_idx = skb->queue_mapping;
5053
5054 if (r_idx >= adapter->num_tx_queues)
5055 r_idx = r_idx % adapter->num_tx_queues;
5056
5057 return adapter->tx_ring[r_idx];
5058 }
5059
5060 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5061 struct net_device *netdev)
5062 {
5063 struct igb_adapter *adapter = netdev_priv(netdev);
5064
5065 if (test_bit(__IGB_DOWN, &adapter->state)) {
5066 dev_kfree_skb_any(skb);
5067 return NETDEV_TX_OK;
5068 }
5069
5070 if (skb->len <= 0) {
5071 dev_kfree_skb_any(skb);
5072 return NETDEV_TX_OK;
5073 }
5074
5075 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5076 * in order to meet this minimum size requirement.
5077 */
5078 if (skb_put_padto(skb, 17))
5079 return NETDEV_TX_OK;
5080
5081 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5082 }
5083
5084 /**
5085 * igb_tx_timeout - Respond to a Tx Hang
5086 * @netdev: network interface device structure
5087 **/
5088 static void igb_tx_timeout(struct net_device *netdev)
5089 {
5090 struct igb_adapter *adapter = netdev_priv(netdev);
5091 struct e1000_hw *hw = &adapter->hw;
5092
5093 /* Do the reset outside of interrupt context */
5094 adapter->tx_timeout_count++;
5095
5096 if (hw->mac.type >= e1000_82580)
5097 hw->dev_spec._82575.global_device_reset = true;
5098
5099 schedule_work(&adapter->reset_task);
5100 wr32(E1000_EICS,
5101 (adapter->eims_enable_mask & ~adapter->eims_other));
5102 }
5103
5104 static void igb_reset_task(struct work_struct *work)
5105 {
5106 struct igb_adapter *adapter;
5107 adapter = container_of(work, struct igb_adapter, reset_task);
5108
5109 igb_dump(adapter);
5110 netdev_err(adapter->netdev, "Reset adapter\n");
5111 igb_reinit_locked(adapter);
5112 }
5113
5114 /**
5115 * igb_get_stats64 - Get System Network Statistics
5116 * @netdev: network interface device structure
5117 * @stats: rtnl_link_stats64 pointer
5118 **/
5119 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5120 struct rtnl_link_stats64 *stats)
5121 {
5122 struct igb_adapter *adapter = netdev_priv(netdev);
5123
5124 spin_lock(&adapter->stats64_lock);
5125 igb_update_stats(adapter, &adapter->stats64);
5126 memcpy(stats, &adapter->stats64, sizeof(*stats));
5127 spin_unlock(&adapter->stats64_lock);
5128
5129 return stats;
5130 }
5131
5132 /**
5133 * igb_change_mtu - Change the Maximum Transfer Unit
5134 * @netdev: network interface device structure
5135 * @new_mtu: new value for maximum frame size
5136 *
5137 * Returns 0 on success, negative on failure
5138 **/
5139 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5140 {
5141 struct igb_adapter *adapter = netdev_priv(netdev);
5142 struct pci_dev *pdev = adapter->pdev;
5143 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5144
5145 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5146 dev_err(&pdev->dev, "Invalid MTU setting\n");
5147 return -EINVAL;
5148 }
5149
5150 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5151 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5152 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5153 return -EINVAL;
5154 }
5155
5156 /* adjust max frame to be at least the size of a standard frame */
5157 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5158 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5159
5160 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5161 usleep_range(1000, 2000);
5162
5163 /* igb_down has a dependency on max_frame_size */
5164 adapter->max_frame_size = max_frame;
5165
5166 if (netif_running(netdev))
5167 igb_down(adapter);
5168
5169 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5170 netdev->mtu, new_mtu);
5171 netdev->mtu = new_mtu;
5172
5173 if (netif_running(netdev))
5174 igb_up(adapter);
5175 else
5176 igb_reset(adapter);
5177
5178 clear_bit(__IGB_RESETTING, &adapter->state);
5179
5180 return 0;
5181 }
5182
5183 /**
5184 * igb_update_stats - Update the board statistics counters
5185 * @adapter: board private structure
5186 **/
5187 void igb_update_stats(struct igb_adapter *adapter,
5188 struct rtnl_link_stats64 *net_stats)
5189 {
5190 struct e1000_hw *hw = &adapter->hw;
5191 struct pci_dev *pdev = adapter->pdev;
5192 u32 reg, mpc;
5193 int i;
5194 u64 bytes, packets;
5195 unsigned int start;
5196 u64 _bytes, _packets;
5197
5198 /* Prevent stats update while adapter is being reset, or if the pci
5199 * connection is down.
5200 */
5201 if (adapter->link_speed == 0)
5202 return;
5203 if (pci_channel_offline(pdev))
5204 return;
5205
5206 bytes = 0;
5207 packets = 0;
5208
5209 rcu_read_lock();
5210 for (i = 0; i < adapter->num_rx_queues; i++) {
5211 struct igb_ring *ring = adapter->rx_ring[i];
5212 u32 rqdpc = rd32(E1000_RQDPC(i));
5213 if (hw->mac.type >= e1000_i210)
5214 wr32(E1000_RQDPC(i), 0);
5215
5216 if (rqdpc) {
5217 ring->rx_stats.drops += rqdpc;
5218 net_stats->rx_fifo_errors += rqdpc;
5219 }
5220
5221 do {
5222 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5223 _bytes = ring->rx_stats.bytes;
5224 _packets = ring->rx_stats.packets;
5225 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5226 bytes += _bytes;
5227 packets += _packets;
5228 }
5229
5230 net_stats->rx_bytes = bytes;
5231 net_stats->rx_packets = packets;
5232
5233 bytes = 0;
5234 packets = 0;
5235 for (i = 0; i < adapter->num_tx_queues; i++) {
5236 struct igb_ring *ring = adapter->tx_ring[i];
5237 do {
5238 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5239 _bytes = ring->tx_stats.bytes;
5240 _packets = ring->tx_stats.packets;
5241 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5242 bytes += _bytes;
5243 packets += _packets;
5244 }
5245 net_stats->tx_bytes = bytes;
5246 net_stats->tx_packets = packets;
5247 rcu_read_unlock();
5248
5249 /* read stats registers */
5250 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5251 adapter->stats.gprc += rd32(E1000_GPRC);
5252 adapter->stats.gorc += rd32(E1000_GORCL);
5253 rd32(E1000_GORCH); /* clear GORCL */
5254 adapter->stats.bprc += rd32(E1000_BPRC);
5255 adapter->stats.mprc += rd32(E1000_MPRC);
5256 adapter->stats.roc += rd32(E1000_ROC);
5257
5258 adapter->stats.prc64 += rd32(E1000_PRC64);
5259 adapter->stats.prc127 += rd32(E1000_PRC127);
5260 adapter->stats.prc255 += rd32(E1000_PRC255);
5261 adapter->stats.prc511 += rd32(E1000_PRC511);
5262 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5263 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5264 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5265 adapter->stats.sec += rd32(E1000_SEC);
5266
5267 mpc = rd32(E1000_MPC);
5268 adapter->stats.mpc += mpc;
5269 net_stats->rx_fifo_errors += mpc;
5270 adapter->stats.scc += rd32(E1000_SCC);
5271 adapter->stats.ecol += rd32(E1000_ECOL);
5272 adapter->stats.mcc += rd32(E1000_MCC);
5273 adapter->stats.latecol += rd32(E1000_LATECOL);
5274 adapter->stats.dc += rd32(E1000_DC);
5275 adapter->stats.rlec += rd32(E1000_RLEC);
5276 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5277 adapter->stats.xontxc += rd32(E1000_XONTXC);
5278 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5279 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5280 adapter->stats.fcruc += rd32(E1000_FCRUC);
5281 adapter->stats.gptc += rd32(E1000_GPTC);
5282 adapter->stats.gotc += rd32(E1000_GOTCL);
5283 rd32(E1000_GOTCH); /* clear GOTCL */
5284 adapter->stats.rnbc += rd32(E1000_RNBC);
5285 adapter->stats.ruc += rd32(E1000_RUC);
5286 adapter->stats.rfc += rd32(E1000_RFC);
5287 adapter->stats.rjc += rd32(E1000_RJC);
5288 adapter->stats.tor += rd32(E1000_TORH);
5289 adapter->stats.tot += rd32(E1000_TOTH);
5290 adapter->stats.tpr += rd32(E1000_TPR);
5291
5292 adapter->stats.ptc64 += rd32(E1000_PTC64);
5293 adapter->stats.ptc127 += rd32(E1000_PTC127);
5294 adapter->stats.ptc255 += rd32(E1000_PTC255);
5295 adapter->stats.ptc511 += rd32(E1000_PTC511);
5296 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5297 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5298
5299 adapter->stats.mptc += rd32(E1000_MPTC);
5300 adapter->stats.bptc += rd32(E1000_BPTC);
5301
5302 adapter->stats.tpt += rd32(E1000_TPT);
5303 adapter->stats.colc += rd32(E1000_COLC);
5304
5305 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5306 /* read internal phy specific stats */
5307 reg = rd32(E1000_CTRL_EXT);
5308 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5309 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5310
5311 /* this stat has invalid values on i210/i211 */
5312 if ((hw->mac.type != e1000_i210) &&
5313 (hw->mac.type != e1000_i211))
5314 adapter->stats.tncrs += rd32(E1000_TNCRS);
5315 }
5316
5317 adapter->stats.tsctc += rd32(E1000_TSCTC);
5318 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5319
5320 adapter->stats.iac += rd32(E1000_IAC);
5321 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5322 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5323 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5324 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5325 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5326 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5327 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5328 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5329
5330 /* Fill out the OS statistics structure */
5331 net_stats->multicast = adapter->stats.mprc;
5332 net_stats->collisions = adapter->stats.colc;
5333
5334 /* Rx Errors */
5335
5336 /* RLEC on some newer hardware can be incorrect so build
5337 * our own version based on RUC and ROC
5338 */
5339 net_stats->rx_errors = adapter->stats.rxerrc +
5340 adapter->stats.crcerrs + adapter->stats.algnerrc +
5341 adapter->stats.ruc + adapter->stats.roc +
5342 adapter->stats.cexterr;
5343 net_stats->rx_length_errors = adapter->stats.ruc +
5344 adapter->stats.roc;
5345 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5346 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5347 net_stats->rx_missed_errors = adapter->stats.mpc;
5348
5349 /* Tx Errors */
5350 net_stats->tx_errors = adapter->stats.ecol +
5351 adapter->stats.latecol;
5352 net_stats->tx_aborted_errors = adapter->stats.ecol;
5353 net_stats->tx_window_errors = adapter->stats.latecol;
5354 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5355
5356 /* Tx Dropped needs to be maintained elsewhere */
5357
5358 /* Management Stats */
5359 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5360 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5361 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5362
5363 /* OS2BMC Stats */
5364 reg = rd32(E1000_MANC);
5365 if (reg & E1000_MANC_EN_BMC2OS) {
5366 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5367 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5368 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5369 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5370 }
5371 }
5372
5373 static void igb_tsync_interrupt(struct igb_adapter *adapter)
5374 {
5375 struct e1000_hw *hw = &adapter->hw;
5376 struct ptp_clock_event event;
5377 struct timespec ts;
5378 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5379
5380 if (tsicr & TSINTR_SYS_WRAP) {
5381 event.type = PTP_CLOCK_PPS;
5382 if (adapter->ptp_caps.pps)
5383 ptp_clock_event(adapter->ptp_clock, &event);
5384 else
5385 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5386 ack |= TSINTR_SYS_WRAP;
5387 }
5388
5389 if (tsicr & E1000_TSICR_TXTS) {
5390 /* retrieve hardware timestamp */
5391 schedule_work(&adapter->ptp_tx_work);
5392 ack |= E1000_TSICR_TXTS;
5393 }
5394
5395 if (tsicr & TSINTR_TT0) {
5396 spin_lock(&adapter->tmreg_lock);
5397 ts = timespec_add(adapter->perout[0].start,
5398 adapter->perout[0].period);
5399 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5400 wr32(E1000_TRGTTIMH0, ts.tv_sec);
5401 tsauxc = rd32(E1000_TSAUXC);
5402 tsauxc |= TSAUXC_EN_TT0;
5403 wr32(E1000_TSAUXC, tsauxc);
5404 adapter->perout[0].start = ts;
5405 spin_unlock(&adapter->tmreg_lock);
5406 ack |= TSINTR_TT0;
5407 }
5408
5409 if (tsicr & TSINTR_TT1) {
5410 spin_lock(&adapter->tmreg_lock);
5411 ts = timespec_add(adapter->perout[1].start,
5412 adapter->perout[1].period);
5413 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5414 wr32(E1000_TRGTTIMH1, ts.tv_sec);
5415 tsauxc = rd32(E1000_TSAUXC);
5416 tsauxc |= TSAUXC_EN_TT1;
5417 wr32(E1000_TSAUXC, tsauxc);
5418 adapter->perout[1].start = ts;
5419 spin_unlock(&adapter->tmreg_lock);
5420 ack |= TSINTR_TT1;
5421 }
5422
5423 if (tsicr & TSINTR_AUTT0) {
5424 nsec = rd32(E1000_AUXSTMPL0);
5425 sec = rd32(E1000_AUXSTMPH0);
5426 event.type = PTP_CLOCK_EXTTS;
5427 event.index = 0;
5428 event.timestamp = sec * 1000000000ULL + nsec;
5429 ptp_clock_event(adapter->ptp_clock, &event);
5430 ack |= TSINTR_AUTT0;
5431 }
5432
5433 if (tsicr & TSINTR_AUTT1) {
5434 nsec = rd32(E1000_AUXSTMPL1);
5435 sec = rd32(E1000_AUXSTMPH1);
5436 event.type = PTP_CLOCK_EXTTS;
5437 event.index = 1;
5438 event.timestamp = sec * 1000000000ULL + nsec;
5439 ptp_clock_event(adapter->ptp_clock, &event);
5440 ack |= TSINTR_AUTT1;
5441 }
5442
5443 /* acknowledge the interrupts */
5444 wr32(E1000_TSICR, ack);
5445 }
5446
5447 static irqreturn_t igb_msix_other(int irq, void *data)
5448 {
5449 struct igb_adapter *adapter = data;
5450 struct e1000_hw *hw = &adapter->hw;
5451 u32 icr = rd32(E1000_ICR);
5452 /* reading ICR causes bit 31 of EICR to be cleared */
5453
5454 if (icr & E1000_ICR_DRSTA)
5455 schedule_work(&adapter->reset_task);
5456
5457 if (icr & E1000_ICR_DOUTSYNC) {
5458 /* HW is reporting DMA is out of sync */
5459 adapter->stats.doosync++;
5460 /* The DMA Out of Sync is also indication of a spoof event
5461 * in IOV mode. Check the Wrong VM Behavior register to
5462 * see if it is really a spoof event.
5463 */
5464 igb_check_wvbr(adapter);
5465 }
5466
5467 /* Check for a mailbox event */
5468 if (icr & E1000_ICR_VMMB)
5469 igb_msg_task(adapter);
5470
5471 if (icr & E1000_ICR_LSC) {
5472 hw->mac.get_link_status = 1;
5473 /* guard against interrupt when we're going down */
5474 if (!test_bit(__IGB_DOWN, &adapter->state))
5475 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5476 }
5477
5478 if (icr & E1000_ICR_TS)
5479 igb_tsync_interrupt(adapter);
5480
5481 wr32(E1000_EIMS, adapter->eims_other);
5482
5483 return IRQ_HANDLED;
5484 }
5485
5486 static void igb_write_itr(struct igb_q_vector *q_vector)
5487 {
5488 struct igb_adapter *adapter = q_vector->adapter;
5489 u32 itr_val = q_vector->itr_val & 0x7FFC;
5490
5491 if (!q_vector->set_itr)
5492 return;
5493
5494 if (!itr_val)
5495 itr_val = 0x4;
5496
5497 if (adapter->hw.mac.type == e1000_82575)
5498 itr_val |= itr_val << 16;
5499 else
5500 itr_val |= E1000_EITR_CNT_IGNR;
5501
5502 writel(itr_val, q_vector->itr_register);
5503 q_vector->set_itr = 0;
5504 }
5505
5506 static irqreturn_t igb_msix_ring(int irq, void *data)
5507 {
5508 struct igb_q_vector *q_vector = data;
5509
5510 /* Write the ITR value calculated from the previous interrupt. */
5511 igb_write_itr(q_vector);
5512
5513 napi_schedule(&q_vector->napi);
5514
5515 return IRQ_HANDLED;
5516 }
5517
5518 #ifdef CONFIG_IGB_DCA
5519 static void igb_update_tx_dca(struct igb_adapter *adapter,
5520 struct igb_ring *tx_ring,
5521 int cpu)
5522 {
5523 struct e1000_hw *hw = &adapter->hw;
5524 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5525
5526 if (hw->mac.type != e1000_82575)
5527 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5528
5529 /* We can enable relaxed ordering for reads, but not writes when
5530 * DCA is enabled. This is due to a known issue in some chipsets
5531 * which will cause the DCA tag to be cleared.
5532 */
5533 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5534 E1000_DCA_TXCTRL_DATA_RRO_EN |
5535 E1000_DCA_TXCTRL_DESC_DCA_EN;
5536
5537 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5538 }
5539
5540 static void igb_update_rx_dca(struct igb_adapter *adapter,
5541 struct igb_ring *rx_ring,
5542 int cpu)
5543 {
5544 struct e1000_hw *hw = &adapter->hw;
5545 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5546
5547 if (hw->mac.type != e1000_82575)
5548 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5549
5550 /* We can enable relaxed ordering for reads, but not writes when
5551 * DCA is enabled. This is due to a known issue in some chipsets
5552 * which will cause the DCA tag to be cleared.
5553 */
5554 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5555 E1000_DCA_RXCTRL_DESC_DCA_EN;
5556
5557 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5558 }
5559
5560 static void igb_update_dca(struct igb_q_vector *q_vector)
5561 {
5562 struct igb_adapter *adapter = q_vector->adapter;
5563 int cpu = get_cpu();
5564
5565 if (q_vector->cpu == cpu)
5566 goto out_no_update;
5567
5568 if (q_vector->tx.ring)
5569 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5570
5571 if (q_vector->rx.ring)
5572 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5573
5574 q_vector->cpu = cpu;
5575 out_no_update:
5576 put_cpu();
5577 }
5578
5579 static void igb_setup_dca(struct igb_adapter *adapter)
5580 {
5581 struct e1000_hw *hw = &adapter->hw;
5582 int i;
5583
5584 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5585 return;
5586
5587 /* Always use CB2 mode, difference is masked in the CB driver. */
5588 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5589
5590 for (i = 0; i < adapter->num_q_vectors; i++) {
5591 adapter->q_vector[i]->cpu = -1;
5592 igb_update_dca(adapter->q_vector[i]);
5593 }
5594 }
5595
5596 static int __igb_notify_dca(struct device *dev, void *data)
5597 {
5598 struct net_device *netdev = dev_get_drvdata(dev);
5599 struct igb_adapter *adapter = netdev_priv(netdev);
5600 struct pci_dev *pdev = adapter->pdev;
5601 struct e1000_hw *hw = &adapter->hw;
5602 unsigned long event = *(unsigned long *)data;
5603
5604 switch (event) {
5605 case DCA_PROVIDER_ADD:
5606 /* if already enabled, don't do it again */
5607 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5608 break;
5609 if (dca_add_requester(dev) == 0) {
5610 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5611 dev_info(&pdev->dev, "DCA enabled\n");
5612 igb_setup_dca(adapter);
5613 break;
5614 }
5615 /* Fall Through since DCA is disabled. */
5616 case DCA_PROVIDER_REMOVE:
5617 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5618 /* without this a class_device is left
5619 * hanging around in the sysfs model
5620 */
5621 dca_remove_requester(dev);
5622 dev_info(&pdev->dev, "DCA disabled\n");
5623 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5624 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5625 }
5626 break;
5627 }
5628
5629 return 0;
5630 }
5631
5632 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5633 void *p)
5634 {
5635 int ret_val;
5636
5637 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5638 __igb_notify_dca);
5639
5640 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5641 }
5642 #endif /* CONFIG_IGB_DCA */
5643
5644 #ifdef CONFIG_PCI_IOV
5645 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5646 {
5647 unsigned char mac_addr[ETH_ALEN];
5648
5649 eth_zero_addr(mac_addr);
5650 igb_set_vf_mac(adapter, vf, mac_addr);
5651
5652 /* By default spoof check is enabled for all VFs */
5653 adapter->vf_data[vf].spoofchk_enabled = true;
5654
5655 return 0;
5656 }
5657
5658 #endif
5659 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5660 {
5661 struct e1000_hw *hw = &adapter->hw;
5662 u32 ping;
5663 int i;
5664
5665 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5666 ping = E1000_PF_CONTROL_MSG;
5667 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5668 ping |= E1000_VT_MSGTYPE_CTS;
5669 igb_write_mbx(hw, &ping, 1, i);
5670 }
5671 }
5672
5673 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5674 {
5675 struct e1000_hw *hw = &adapter->hw;
5676 u32 vmolr = rd32(E1000_VMOLR(vf));
5677 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5678
5679 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5680 IGB_VF_FLAG_MULTI_PROMISC);
5681 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5682
5683 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5684 vmolr |= E1000_VMOLR_MPME;
5685 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5686 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5687 } else {
5688 /* if we have hashes and we are clearing a multicast promisc
5689 * flag we need to write the hashes to the MTA as this step
5690 * was previously skipped
5691 */
5692 if (vf_data->num_vf_mc_hashes > 30) {
5693 vmolr |= E1000_VMOLR_MPME;
5694 } else if (vf_data->num_vf_mc_hashes) {
5695 int j;
5696
5697 vmolr |= E1000_VMOLR_ROMPE;
5698 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5699 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5700 }
5701 }
5702
5703 wr32(E1000_VMOLR(vf), vmolr);
5704
5705 /* there are flags left unprocessed, likely not supported */
5706 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5707 return -EINVAL;
5708
5709 return 0;
5710 }
5711
5712 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5713 u32 *msgbuf, u32 vf)
5714 {
5715 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5716 u16 *hash_list = (u16 *)&msgbuf[1];
5717 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5718 int i;
5719
5720 /* salt away the number of multicast addresses assigned
5721 * to this VF for later use to restore when the PF multi cast
5722 * list changes
5723 */
5724 vf_data->num_vf_mc_hashes = n;
5725
5726 /* only up to 30 hash values supported */
5727 if (n > 30)
5728 n = 30;
5729
5730 /* store the hashes for later use */
5731 for (i = 0; i < n; i++)
5732 vf_data->vf_mc_hashes[i] = hash_list[i];
5733
5734 /* Flush and reset the mta with the new values */
5735 igb_set_rx_mode(adapter->netdev);
5736
5737 return 0;
5738 }
5739
5740 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5741 {
5742 struct e1000_hw *hw = &adapter->hw;
5743 struct vf_data_storage *vf_data;
5744 int i, j;
5745
5746 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5747 u32 vmolr = rd32(E1000_VMOLR(i));
5748
5749 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5750
5751 vf_data = &adapter->vf_data[i];
5752
5753 if ((vf_data->num_vf_mc_hashes > 30) ||
5754 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5755 vmolr |= E1000_VMOLR_MPME;
5756 } else if (vf_data->num_vf_mc_hashes) {
5757 vmolr |= E1000_VMOLR_ROMPE;
5758 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5759 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5760 }
5761 wr32(E1000_VMOLR(i), vmolr);
5762 }
5763 }
5764
5765 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5766 {
5767 struct e1000_hw *hw = &adapter->hw;
5768 u32 pool_mask, reg, vid;
5769 int i;
5770
5771 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5772
5773 /* Find the vlan filter for this id */
5774 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5775 reg = rd32(E1000_VLVF(i));
5776
5777 /* remove the vf from the pool */
5778 reg &= ~pool_mask;
5779
5780 /* if pool is empty then remove entry from vfta */
5781 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5782 (reg & E1000_VLVF_VLANID_ENABLE)) {
5783 reg = 0;
5784 vid = reg & E1000_VLVF_VLANID_MASK;
5785 igb_vfta_set(hw, vid, false);
5786 }
5787
5788 wr32(E1000_VLVF(i), reg);
5789 }
5790
5791 adapter->vf_data[vf].vlans_enabled = 0;
5792 }
5793
5794 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5795 {
5796 struct e1000_hw *hw = &adapter->hw;
5797 u32 reg, i;
5798
5799 /* The vlvf table only exists on 82576 hardware and newer */
5800 if (hw->mac.type < e1000_82576)
5801 return -1;
5802
5803 /* we only need to do this if VMDq is enabled */
5804 if (!adapter->vfs_allocated_count)
5805 return -1;
5806
5807 /* Find the vlan filter for this id */
5808 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5809 reg = rd32(E1000_VLVF(i));
5810 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5811 vid == (reg & E1000_VLVF_VLANID_MASK))
5812 break;
5813 }
5814
5815 if (add) {
5816 if (i == E1000_VLVF_ARRAY_SIZE) {
5817 /* Did not find a matching VLAN ID entry that was
5818 * enabled. Search for a free filter entry, i.e.
5819 * one without the enable bit set
5820 */
5821 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5822 reg = rd32(E1000_VLVF(i));
5823 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5824 break;
5825 }
5826 }
5827 if (i < E1000_VLVF_ARRAY_SIZE) {
5828 /* Found an enabled/available entry */
5829 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5830
5831 /* if !enabled we need to set this up in vfta */
5832 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5833 /* add VID to filter table */
5834 igb_vfta_set(hw, vid, true);
5835 reg |= E1000_VLVF_VLANID_ENABLE;
5836 }
5837 reg &= ~E1000_VLVF_VLANID_MASK;
5838 reg |= vid;
5839 wr32(E1000_VLVF(i), reg);
5840
5841 /* do not modify RLPML for PF devices */
5842 if (vf >= adapter->vfs_allocated_count)
5843 return 0;
5844
5845 if (!adapter->vf_data[vf].vlans_enabled) {
5846 u32 size;
5847
5848 reg = rd32(E1000_VMOLR(vf));
5849 size = reg & E1000_VMOLR_RLPML_MASK;
5850 size += 4;
5851 reg &= ~E1000_VMOLR_RLPML_MASK;
5852 reg |= size;
5853 wr32(E1000_VMOLR(vf), reg);
5854 }
5855
5856 adapter->vf_data[vf].vlans_enabled++;
5857 }
5858 } else {
5859 if (i < E1000_VLVF_ARRAY_SIZE) {
5860 /* remove vf from the pool */
5861 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5862 /* if pool is empty then remove entry from vfta */
5863 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5864 reg = 0;
5865 igb_vfta_set(hw, vid, false);
5866 }
5867 wr32(E1000_VLVF(i), reg);
5868
5869 /* do not modify RLPML for PF devices */
5870 if (vf >= adapter->vfs_allocated_count)
5871 return 0;
5872
5873 adapter->vf_data[vf].vlans_enabled--;
5874 if (!adapter->vf_data[vf].vlans_enabled) {
5875 u32 size;
5876
5877 reg = rd32(E1000_VMOLR(vf));
5878 size = reg & E1000_VMOLR_RLPML_MASK;
5879 size -= 4;
5880 reg &= ~E1000_VMOLR_RLPML_MASK;
5881 reg |= size;
5882 wr32(E1000_VMOLR(vf), reg);
5883 }
5884 }
5885 }
5886 return 0;
5887 }
5888
5889 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5890 {
5891 struct e1000_hw *hw = &adapter->hw;
5892
5893 if (vid)
5894 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5895 else
5896 wr32(E1000_VMVIR(vf), 0);
5897 }
5898
5899 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5900 int vf, u16 vlan, u8 qos)
5901 {
5902 int err = 0;
5903 struct igb_adapter *adapter = netdev_priv(netdev);
5904
5905 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5906 return -EINVAL;
5907 if (vlan || qos) {
5908 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5909 if (err)
5910 goto out;
5911 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5912 igb_set_vmolr(adapter, vf, !vlan);
5913 adapter->vf_data[vf].pf_vlan = vlan;
5914 adapter->vf_data[vf].pf_qos = qos;
5915 dev_info(&adapter->pdev->dev,
5916 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5917 if (test_bit(__IGB_DOWN, &adapter->state)) {
5918 dev_warn(&adapter->pdev->dev,
5919 "The VF VLAN has been set, but the PF device is not up.\n");
5920 dev_warn(&adapter->pdev->dev,
5921 "Bring the PF device up before attempting to use the VF device.\n");
5922 }
5923 } else {
5924 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5925 false, vf);
5926 igb_set_vmvir(adapter, vlan, vf);
5927 igb_set_vmolr(adapter, vf, true);
5928 adapter->vf_data[vf].pf_vlan = 0;
5929 adapter->vf_data[vf].pf_qos = 0;
5930 }
5931 out:
5932 return err;
5933 }
5934
5935 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5936 {
5937 struct e1000_hw *hw = &adapter->hw;
5938 int i;
5939 u32 reg;
5940
5941 /* Find the vlan filter for this id */
5942 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5943 reg = rd32(E1000_VLVF(i));
5944 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5945 vid == (reg & E1000_VLVF_VLANID_MASK))
5946 break;
5947 }
5948
5949 if (i >= E1000_VLVF_ARRAY_SIZE)
5950 i = -1;
5951
5952 return i;
5953 }
5954
5955 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5956 {
5957 struct e1000_hw *hw = &adapter->hw;
5958 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5959 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5960 int err = 0;
5961
5962 /* If in promiscuous mode we need to make sure the PF also has
5963 * the VLAN filter set.
5964 */
5965 if (add && (adapter->netdev->flags & IFF_PROMISC))
5966 err = igb_vlvf_set(adapter, vid, add,
5967 adapter->vfs_allocated_count);
5968 if (err)
5969 goto out;
5970
5971 err = igb_vlvf_set(adapter, vid, add, vf);
5972
5973 if (err)
5974 goto out;
5975
5976 /* Go through all the checks to see if the VLAN filter should
5977 * be wiped completely.
5978 */
5979 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5980 u32 vlvf, bits;
5981 int regndx = igb_find_vlvf_entry(adapter, vid);
5982
5983 if (regndx < 0)
5984 goto out;
5985 /* See if any other pools are set for this VLAN filter
5986 * entry other than the PF.
5987 */
5988 vlvf = bits = rd32(E1000_VLVF(regndx));
5989 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5990 adapter->vfs_allocated_count);
5991 /* If the filter was removed then ensure PF pool bit
5992 * is cleared if the PF only added itself to the pool
5993 * because the PF is in promiscuous mode.
5994 */
5995 if ((vlvf & VLAN_VID_MASK) == vid &&
5996 !test_bit(vid, adapter->active_vlans) &&
5997 !bits)
5998 igb_vlvf_set(adapter, vid, add,
5999 adapter->vfs_allocated_count);
6000 }
6001
6002 out:
6003 return err;
6004 }
6005
6006 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6007 {
6008 /* clear flags - except flag that indicates PF has set the MAC */
6009 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
6010 adapter->vf_data[vf].last_nack = jiffies;
6011
6012 /* reset offloads to defaults */
6013 igb_set_vmolr(adapter, vf, true);
6014
6015 /* reset vlans for device */
6016 igb_clear_vf_vfta(adapter, vf);
6017 if (adapter->vf_data[vf].pf_vlan)
6018 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6019 adapter->vf_data[vf].pf_vlan,
6020 adapter->vf_data[vf].pf_qos);
6021 else
6022 igb_clear_vf_vfta(adapter, vf);
6023
6024 /* reset multicast table array for vf */
6025 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6026
6027 /* Flush and reset the mta with the new values */
6028 igb_set_rx_mode(adapter->netdev);
6029 }
6030
6031 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6032 {
6033 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6034
6035 /* clear mac address as we were hotplug removed/added */
6036 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6037 eth_zero_addr(vf_mac);
6038
6039 /* process remaining reset events */
6040 igb_vf_reset(adapter, vf);
6041 }
6042
6043 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6044 {
6045 struct e1000_hw *hw = &adapter->hw;
6046 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6047 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6048 u32 reg, msgbuf[3];
6049 u8 *addr = (u8 *)(&msgbuf[1]);
6050
6051 /* process all the same items cleared in a function level reset */
6052 igb_vf_reset(adapter, vf);
6053
6054 /* set vf mac address */
6055 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6056
6057 /* enable transmit and receive for vf */
6058 reg = rd32(E1000_VFTE);
6059 wr32(E1000_VFTE, reg | (1 << vf));
6060 reg = rd32(E1000_VFRE);
6061 wr32(E1000_VFRE, reg | (1 << vf));
6062
6063 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6064
6065 /* reply to reset with ack and vf mac address */
6066 if (!is_zero_ether_addr(vf_mac)) {
6067 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6068 memcpy(addr, vf_mac, ETH_ALEN);
6069 } else {
6070 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6071 }
6072 igb_write_mbx(hw, msgbuf, 3, vf);
6073 }
6074
6075 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6076 {
6077 /* The VF MAC Address is stored in a packed array of bytes
6078 * starting at the second 32 bit word of the msg array
6079 */
6080 unsigned char *addr = (char *)&msg[1];
6081 int err = -1;
6082
6083 if (is_valid_ether_addr(addr))
6084 err = igb_set_vf_mac(adapter, vf, addr);
6085
6086 return err;
6087 }
6088
6089 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6090 {
6091 struct e1000_hw *hw = &adapter->hw;
6092 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6093 u32 msg = E1000_VT_MSGTYPE_NACK;
6094
6095 /* if device isn't clear to send it shouldn't be reading either */
6096 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6097 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6098 igb_write_mbx(hw, &msg, 1, vf);
6099 vf_data->last_nack = jiffies;
6100 }
6101 }
6102
6103 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6104 {
6105 struct pci_dev *pdev = adapter->pdev;
6106 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6107 struct e1000_hw *hw = &adapter->hw;
6108 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6109 s32 retval;
6110
6111 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6112
6113 if (retval) {
6114 /* if receive failed revoke VF CTS stats and restart init */
6115 dev_err(&pdev->dev, "Error receiving message from VF\n");
6116 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6117 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6118 return;
6119 goto out;
6120 }
6121
6122 /* this is a message we already processed, do nothing */
6123 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6124 return;
6125
6126 /* until the vf completes a reset it should not be
6127 * allowed to start any configuration.
6128 */
6129 if (msgbuf[0] == E1000_VF_RESET) {
6130 igb_vf_reset_msg(adapter, vf);
6131 return;
6132 }
6133
6134 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6135 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6136 return;
6137 retval = -1;
6138 goto out;
6139 }
6140
6141 switch ((msgbuf[0] & 0xFFFF)) {
6142 case E1000_VF_SET_MAC_ADDR:
6143 retval = -EINVAL;
6144 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6145 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6146 else
6147 dev_warn(&pdev->dev,
6148 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6149 vf);
6150 break;
6151 case E1000_VF_SET_PROMISC:
6152 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6153 break;
6154 case E1000_VF_SET_MULTICAST:
6155 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6156 break;
6157 case E1000_VF_SET_LPE:
6158 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6159 break;
6160 case E1000_VF_SET_VLAN:
6161 retval = -1;
6162 if (vf_data->pf_vlan)
6163 dev_warn(&pdev->dev,
6164 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6165 vf);
6166 else
6167 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6168 break;
6169 default:
6170 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6171 retval = -1;
6172 break;
6173 }
6174
6175 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6176 out:
6177 /* notify the VF of the results of what it sent us */
6178 if (retval)
6179 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6180 else
6181 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6182
6183 igb_write_mbx(hw, msgbuf, 1, vf);
6184 }
6185
6186 static void igb_msg_task(struct igb_adapter *adapter)
6187 {
6188 struct e1000_hw *hw = &adapter->hw;
6189 u32 vf;
6190
6191 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6192 /* process any reset requests */
6193 if (!igb_check_for_rst(hw, vf))
6194 igb_vf_reset_event(adapter, vf);
6195
6196 /* process any messages pending */
6197 if (!igb_check_for_msg(hw, vf))
6198 igb_rcv_msg_from_vf(adapter, vf);
6199
6200 /* process any acks */
6201 if (!igb_check_for_ack(hw, vf))
6202 igb_rcv_ack_from_vf(adapter, vf);
6203 }
6204 }
6205
6206 /**
6207 * igb_set_uta - Set unicast filter table address
6208 * @adapter: board private structure
6209 *
6210 * The unicast table address is a register array of 32-bit registers.
6211 * The table is meant to be used in a way similar to how the MTA is used
6212 * however due to certain limitations in the hardware it is necessary to
6213 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6214 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6215 **/
6216 static void igb_set_uta(struct igb_adapter *adapter)
6217 {
6218 struct e1000_hw *hw = &adapter->hw;
6219 int i;
6220
6221 /* The UTA table only exists on 82576 hardware and newer */
6222 if (hw->mac.type < e1000_82576)
6223 return;
6224
6225 /* we only need to do this if VMDq is enabled */
6226 if (!adapter->vfs_allocated_count)
6227 return;
6228
6229 for (i = 0; i < hw->mac.uta_reg_count; i++)
6230 array_wr32(E1000_UTA, i, ~0);
6231 }
6232
6233 /**
6234 * igb_intr_msi - Interrupt Handler
6235 * @irq: interrupt number
6236 * @data: pointer to a network interface device structure
6237 **/
6238 static irqreturn_t igb_intr_msi(int irq, void *data)
6239 {
6240 struct igb_adapter *adapter = data;
6241 struct igb_q_vector *q_vector = adapter->q_vector[0];
6242 struct e1000_hw *hw = &adapter->hw;
6243 /* read ICR disables interrupts using IAM */
6244 u32 icr = rd32(E1000_ICR);
6245
6246 igb_write_itr(q_vector);
6247
6248 if (icr & E1000_ICR_DRSTA)
6249 schedule_work(&adapter->reset_task);
6250
6251 if (icr & E1000_ICR_DOUTSYNC) {
6252 /* HW is reporting DMA is out of sync */
6253 adapter->stats.doosync++;
6254 }
6255
6256 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6257 hw->mac.get_link_status = 1;
6258 if (!test_bit(__IGB_DOWN, &adapter->state))
6259 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6260 }
6261
6262 if (icr & E1000_ICR_TS)
6263 igb_tsync_interrupt(adapter);
6264
6265 napi_schedule(&q_vector->napi);
6266
6267 return IRQ_HANDLED;
6268 }
6269
6270 /**
6271 * igb_intr - Legacy Interrupt Handler
6272 * @irq: interrupt number
6273 * @data: pointer to a network interface device structure
6274 **/
6275 static irqreturn_t igb_intr(int irq, void *data)
6276 {
6277 struct igb_adapter *adapter = data;
6278 struct igb_q_vector *q_vector = adapter->q_vector[0];
6279 struct e1000_hw *hw = &adapter->hw;
6280 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6281 * need for the IMC write
6282 */
6283 u32 icr = rd32(E1000_ICR);
6284
6285 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6286 * not set, then the adapter didn't send an interrupt
6287 */
6288 if (!(icr & E1000_ICR_INT_ASSERTED))
6289 return IRQ_NONE;
6290
6291 igb_write_itr(q_vector);
6292
6293 if (icr & E1000_ICR_DRSTA)
6294 schedule_work(&adapter->reset_task);
6295
6296 if (icr & E1000_ICR_DOUTSYNC) {
6297 /* HW is reporting DMA is out of sync */
6298 adapter->stats.doosync++;
6299 }
6300
6301 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6302 hw->mac.get_link_status = 1;
6303 /* guard against interrupt when we're going down */
6304 if (!test_bit(__IGB_DOWN, &adapter->state))
6305 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6306 }
6307
6308 if (icr & E1000_ICR_TS)
6309 igb_tsync_interrupt(adapter);
6310
6311 napi_schedule(&q_vector->napi);
6312
6313 return IRQ_HANDLED;
6314 }
6315
6316 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6317 {
6318 struct igb_adapter *adapter = q_vector->adapter;
6319 struct e1000_hw *hw = &adapter->hw;
6320
6321 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6322 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6323 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6324 igb_set_itr(q_vector);
6325 else
6326 igb_update_ring_itr(q_vector);
6327 }
6328
6329 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6330 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6331 wr32(E1000_EIMS, q_vector->eims_value);
6332 else
6333 igb_irq_enable(adapter);
6334 }
6335 }
6336
6337 /**
6338 * igb_poll - NAPI Rx polling callback
6339 * @napi: napi polling structure
6340 * @budget: count of how many packets we should handle
6341 **/
6342 static int igb_poll(struct napi_struct *napi, int budget)
6343 {
6344 struct igb_q_vector *q_vector = container_of(napi,
6345 struct igb_q_vector,
6346 napi);
6347 bool clean_complete = true;
6348
6349 #ifdef CONFIG_IGB_DCA
6350 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6351 igb_update_dca(q_vector);
6352 #endif
6353 if (q_vector->tx.ring)
6354 clean_complete = igb_clean_tx_irq(q_vector);
6355
6356 if (q_vector->rx.ring)
6357 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6358
6359 /* If all work not completed, return budget and keep polling */
6360 if (!clean_complete)
6361 return budget;
6362
6363 /* If not enough Rx work done, exit the polling mode */
6364 napi_complete(napi);
6365 igb_ring_irq_enable(q_vector);
6366
6367 return 0;
6368 }
6369
6370 /**
6371 * igb_clean_tx_irq - Reclaim resources after transmit completes
6372 * @q_vector: pointer to q_vector containing needed info
6373 *
6374 * returns true if ring is completely cleaned
6375 **/
6376 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6377 {
6378 struct igb_adapter *adapter = q_vector->adapter;
6379 struct igb_ring *tx_ring = q_vector->tx.ring;
6380 struct igb_tx_buffer *tx_buffer;
6381 union e1000_adv_tx_desc *tx_desc;
6382 unsigned int total_bytes = 0, total_packets = 0;
6383 unsigned int budget = q_vector->tx.work_limit;
6384 unsigned int i = tx_ring->next_to_clean;
6385
6386 if (test_bit(__IGB_DOWN, &adapter->state))
6387 return true;
6388
6389 tx_buffer = &tx_ring->tx_buffer_info[i];
6390 tx_desc = IGB_TX_DESC(tx_ring, i);
6391 i -= tx_ring->count;
6392
6393 do {
6394 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6395
6396 /* if next_to_watch is not set then there is no work pending */
6397 if (!eop_desc)
6398 break;
6399
6400 /* prevent any other reads prior to eop_desc */
6401 read_barrier_depends();
6402
6403 /* if DD is not set pending work has not been completed */
6404 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6405 break;
6406
6407 /* clear next_to_watch to prevent false hangs */
6408 tx_buffer->next_to_watch = NULL;
6409
6410 /* update the statistics for this packet */
6411 total_bytes += tx_buffer->bytecount;
6412 total_packets += tx_buffer->gso_segs;
6413
6414 /* free the skb */
6415 dev_consume_skb_any(tx_buffer->skb);
6416
6417 /* unmap skb header data */
6418 dma_unmap_single(tx_ring->dev,
6419 dma_unmap_addr(tx_buffer, dma),
6420 dma_unmap_len(tx_buffer, len),
6421 DMA_TO_DEVICE);
6422
6423 /* clear tx_buffer data */
6424 tx_buffer->skb = NULL;
6425 dma_unmap_len_set(tx_buffer, len, 0);
6426
6427 /* clear last DMA location and unmap remaining buffers */
6428 while (tx_desc != eop_desc) {
6429 tx_buffer++;
6430 tx_desc++;
6431 i++;
6432 if (unlikely(!i)) {
6433 i -= tx_ring->count;
6434 tx_buffer = tx_ring->tx_buffer_info;
6435 tx_desc = IGB_TX_DESC(tx_ring, 0);
6436 }
6437
6438 /* unmap any remaining paged data */
6439 if (dma_unmap_len(tx_buffer, len)) {
6440 dma_unmap_page(tx_ring->dev,
6441 dma_unmap_addr(tx_buffer, dma),
6442 dma_unmap_len(tx_buffer, len),
6443 DMA_TO_DEVICE);
6444 dma_unmap_len_set(tx_buffer, len, 0);
6445 }
6446 }
6447
6448 /* move us one more past the eop_desc for start of next pkt */
6449 tx_buffer++;
6450 tx_desc++;
6451 i++;
6452 if (unlikely(!i)) {
6453 i -= tx_ring->count;
6454 tx_buffer = tx_ring->tx_buffer_info;
6455 tx_desc = IGB_TX_DESC(tx_ring, 0);
6456 }
6457
6458 /* issue prefetch for next Tx descriptor */
6459 prefetch(tx_desc);
6460
6461 /* update budget accounting */
6462 budget--;
6463 } while (likely(budget));
6464
6465 netdev_tx_completed_queue(txring_txq(tx_ring),
6466 total_packets, total_bytes);
6467 i += tx_ring->count;
6468 tx_ring->next_to_clean = i;
6469 u64_stats_update_begin(&tx_ring->tx_syncp);
6470 tx_ring->tx_stats.bytes += total_bytes;
6471 tx_ring->tx_stats.packets += total_packets;
6472 u64_stats_update_end(&tx_ring->tx_syncp);
6473 q_vector->tx.total_bytes += total_bytes;
6474 q_vector->tx.total_packets += total_packets;
6475
6476 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6477 struct e1000_hw *hw = &adapter->hw;
6478
6479 /* Detect a transmit hang in hardware, this serializes the
6480 * check with the clearing of time_stamp and movement of i
6481 */
6482 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6483 if (tx_buffer->next_to_watch &&
6484 time_after(jiffies, tx_buffer->time_stamp +
6485 (adapter->tx_timeout_factor * HZ)) &&
6486 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6487
6488 /* detected Tx unit hang */
6489 dev_err(tx_ring->dev,
6490 "Detected Tx Unit Hang\n"
6491 " Tx Queue <%d>\n"
6492 " TDH <%x>\n"
6493 " TDT <%x>\n"
6494 " next_to_use <%x>\n"
6495 " next_to_clean <%x>\n"
6496 "buffer_info[next_to_clean]\n"
6497 " time_stamp <%lx>\n"
6498 " next_to_watch <%p>\n"
6499 " jiffies <%lx>\n"
6500 " desc.status <%x>\n",
6501 tx_ring->queue_index,
6502 rd32(E1000_TDH(tx_ring->reg_idx)),
6503 readl(tx_ring->tail),
6504 tx_ring->next_to_use,
6505 tx_ring->next_to_clean,
6506 tx_buffer->time_stamp,
6507 tx_buffer->next_to_watch,
6508 jiffies,
6509 tx_buffer->next_to_watch->wb.status);
6510 netif_stop_subqueue(tx_ring->netdev,
6511 tx_ring->queue_index);
6512
6513 /* we are about to reset, no point in enabling stuff */
6514 return true;
6515 }
6516 }
6517
6518 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6519 if (unlikely(total_packets &&
6520 netif_carrier_ok(tx_ring->netdev) &&
6521 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6522 /* Make sure that anybody stopping the queue after this
6523 * sees the new next_to_clean.
6524 */
6525 smp_mb();
6526 if (__netif_subqueue_stopped(tx_ring->netdev,
6527 tx_ring->queue_index) &&
6528 !(test_bit(__IGB_DOWN, &adapter->state))) {
6529 netif_wake_subqueue(tx_ring->netdev,
6530 tx_ring->queue_index);
6531
6532 u64_stats_update_begin(&tx_ring->tx_syncp);
6533 tx_ring->tx_stats.restart_queue++;
6534 u64_stats_update_end(&tx_ring->tx_syncp);
6535 }
6536 }
6537
6538 return !!budget;
6539 }
6540
6541 /**
6542 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6543 * @rx_ring: rx descriptor ring to store buffers on
6544 * @old_buff: donor buffer to have page reused
6545 *
6546 * Synchronizes page for reuse by the adapter
6547 **/
6548 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6549 struct igb_rx_buffer *old_buff)
6550 {
6551 struct igb_rx_buffer *new_buff;
6552 u16 nta = rx_ring->next_to_alloc;
6553
6554 new_buff = &rx_ring->rx_buffer_info[nta];
6555
6556 /* update, and store next to alloc */
6557 nta++;
6558 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6559
6560 /* transfer page from old buffer to new buffer */
6561 *new_buff = *old_buff;
6562
6563 /* sync the buffer for use by the device */
6564 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6565 old_buff->page_offset,
6566 IGB_RX_BUFSZ,
6567 DMA_FROM_DEVICE);
6568 }
6569
6570 static inline bool igb_page_is_reserved(struct page *page)
6571 {
6572 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
6573 }
6574
6575 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6576 struct page *page,
6577 unsigned int truesize)
6578 {
6579 /* avoid re-using remote pages */
6580 if (unlikely(igb_page_is_reserved(page)))
6581 return false;
6582
6583 #if (PAGE_SIZE < 8192)
6584 /* if we are only owner of page we can reuse it */
6585 if (unlikely(page_count(page) != 1))
6586 return false;
6587
6588 /* flip page offset to other buffer */
6589 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6590 #else
6591 /* move offset up to the next cache line */
6592 rx_buffer->page_offset += truesize;
6593
6594 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6595 return false;
6596 #endif
6597
6598 /* Even if we own the page, we are not allowed to use atomic_set()
6599 * This would break get_page_unless_zero() users.
6600 */
6601 atomic_inc(&page->_count);
6602
6603 return true;
6604 }
6605
6606 /**
6607 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6608 * @rx_ring: rx descriptor ring to transact packets on
6609 * @rx_buffer: buffer containing page to add
6610 * @rx_desc: descriptor containing length of buffer written by hardware
6611 * @skb: sk_buff to place the data into
6612 *
6613 * This function will add the data contained in rx_buffer->page to the skb.
6614 * This is done either through a direct copy if the data in the buffer is
6615 * less than the skb header size, otherwise it will just attach the page as
6616 * a frag to the skb.
6617 *
6618 * The function will then update the page offset if necessary and return
6619 * true if the buffer can be reused by the adapter.
6620 **/
6621 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6622 struct igb_rx_buffer *rx_buffer,
6623 union e1000_adv_rx_desc *rx_desc,
6624 struct sk_buff *skb)
6625 {
6626 struct page *page = rx_buffer->page;
6627 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6628 #if (PAGE_SIZE < 8192)
6629 unsigned int truesize = IGB_RX_BUFSZ;
6630 #else
6631 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6632 #endif
6633
6634 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6635 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6636
6637 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6638 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6639 va += IGB_TS_HDR_LEN;
6640 size -= IGB_TS_HDR_LEN;
6641 }
6642
6643 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6644
6645 /* page is not reserved, we can reuse buffer as-is */
6646 if (likely(!igb_page_is_reserved(page)))
6647 return true;
6648
6649 /* this page cannot be reused so discard it */
6650 __free_page(page);
6651 return false;
6652 }
6653
6654 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6655 rx_buffer->page_offset, size, truesize);
6656
6657 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6658 }
6659
6660 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6661 union e1000_adv_rx_desc *rx_desc,
6662 struct sk_buff *skb)
6663 {
6664 struct igb_rx_buffer *rx_buffer;
6665 struct page *page;
6666
6667 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6668 page = rx_buffer->page;
6669 prefetchw(page);
6670
6671 if (likely(!skb)) {
6672 void *page_addr = page_address(page) +
6673 rx_buffer->page_offset;
6674
6675 /* prefetch first cache line of first page */
6676 prefetch(page_addr);
6677 #if L1_CACHE_BYTES < 128
6678 prefetch(page_addr + L1_CACHE_BYTES);
6679 #endif
6680
6681 /* allocate a skb to store the frags */
6682 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6683 if (unlikely(!skb)) {
6684 rx_ring->rx_stats.alloc_failed++;
6685 return NULL;
6686 }
6687
6688 /* we will be copying header into skb->data in
6689 * pskb_may_pull so it is in our interest to prefetch
6690 * it now to avoid a possible cache miss
6691 */
6692 prefetchw(skb->data);
6693 }
6694
6695 /* we are reusing so sync this buffer for CPU use */
6696 dma_sync_single_range_for_cpu(rx_ring->dev,
6697 rx_buffer->dma,
6698 rx_buffer->page_offset,
6699 IGB_RX_BUFSZ,
6700 DMA_FROM_DEVICE);
6701
6702 /* pull page into skb */
6703 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6704 /* hand second half of page back to the ring */
6705 igb_reuse_rx_page(rx_ring, rx_buffer);
6706 } else {
6707 /* we are not reusing the buffer so unmap it */
6708 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6709 PAGE_SIZE, DMA_FROM_DEVICE);
6710 }
6711
6712 /* clear contents of rx_buffer */
6713 rx_buffer->page = NULL;
6714
6715 return skb;
6716 }
6717
6718 static inline void igb_rx_checksum(struct igb_ring *ring,
6719 union e1000_adv_rx_desc *rx_desc,
6720 struct sk_buff *skb)
6721 {
6722 skb_checksum_none_assert(skb);
6723
6724 /* Ignore Checksum bit is set */
6725 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6726 return;
6727
6728 /* Rx checksum disabled via ethtool */
6729 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6730 return;
6731
6732 /* TCP/UDP checksum error bit is set */
6733 if (igb_test_staterr(rx_desc,
6734 E1000_RXDEXT_STATERR_TCPE |
6735 E1000_RXDEXT_STATERR_IPE)) {
6736 /* work around errata with sctp packets where the TCPE aka
6737 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6738 * packets, (aka let the stack check the crc32c)
6739 */
6740 if (!((skb->len == 60) &&
6741 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6742 u64_stats_update_begin(&ring->rx_syncp);
6743 ring->rx_stats.csum_err++;
6744 u64_stats_update_end(&ring->rx_syncp);
6745 }
6746 /* let the stack verify checksum errors */
6747 return;
6748 }
6749 /* It must be a TCP or UDP packet with a valid checksum */
6750 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6751 E1000_RXD_STAT_UDPCS))
6752 skb->ip_summed = CHECKSUM_UNNECESSARY;
6753
6754 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6755 le32_to_cpu(rx_desc->wb.upper.status_error));
6756 }
6757
6758 static inline void igb_rx_hash(struct igb_ring *ring,
6759 union e1000_adv_rx_desc *rx_desc,
6760 struct sk_buff *skb)
6761 {
6762 if (ring->netdev->features & NETIF_F_RXHASH)
6763 skb_set_hash(skb,
6764 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6765 PKT_HASH_TYPE_L3);
6766 }
6767
6768 /**
6769 * igb_is_non_eop - process handling of non-EOP buffers
6770 * @rx_ring: Rx ring being processed
6771 * @rx_desc: Rx descriptor for current buffer
6772 * @skb: current socket buffer containing buffer in progress
6773 *
6774 * This function updates next to clean. If the buffer is an EOP buffer
6775 * this function exits returning false, otherwise it will place the
6776 * sk_buff in the next buffer to be chained and return true indicating
6777 * that this is in fact a non-EOP buffer.
6778 **/
6779 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6780 union e1000_adv_rx_desc *rx_desc)
6781 {
6782 u32 ntc = rx_ring->next_to_clean + 1;
6783
6784 /* fetch, update, and store next to clean */
6785 ntc = (ntc < rx_ring->count) ? ntc : 0;
6786 rx_ring->next_to_clean = ntc;
6787
6788 prefetch(IGB_RX_DESC(rx_ring, ntc));
6789
6790 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6791 return false;
6792
6793 return true;
6794 }
6795
6796 /**
6797 * igb_pull_tail - igb specific version of skb_pull_tail
6798 * @rx_ring: rx descriptor ring packet is being transacted on
6799 * @rx_desc: pointer to the EOP Rx descriptor
6800 * @skb: pointer to current skb being adjusted
6801 *
6802 * This function is an igb specific version of __pskb_pull_tail. The
6803 * main difference between this version and the original function is that
6804 * this function can make several assumptions about the state of things
6805 * that allow for significant optimizations versus the standard function.
6806 * As a result we can do things like drop a frag and maintain an accurate
6807 * truesize for the skb.
6808 */
6809 static void igb_pull_tail(struct igb_ring *rx_ring,
6810 union e1000_adv_rx_desc *rx_desc,
6811 struct sk_buff *skb)
6812 {
6813 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6814 unsigned char *va;
6815 unsigned int pull_len;
6816
6817 /* it is valid to use page_address instead of kmap since we are
6818 * working with pages allocated out of the lomem pool per
6819 * alloc_page(GFP_ATOMIC)
6820 */
6821 va = skb_frag_address(frag);
6822
6823 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6824 /* retrieve timestamp from buffer */
6825 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6826
6827 /* update pointers to remove timestamp header */
6828 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6829 frag->page_offset += IGB_TS_HDR_LEN;
6830 skb->data_len -= IGB_TS_HDR_LEN;
6831 skb->len -= IGB_TS_HDR_LEN;
6832
6833 /* move va to start of packet data */
6834 va += IGB_TS_HDR_LEN;
6835 }
6836
6837 /* we need the header to contain the greater of either ETH_HLEN or
6838 * 60 bytes if the skb->len is less than 60 for skb_pad.
6839 */
6840 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6841
6842 /* align pull length to size of long to optimize memcpy performance */
6843 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6844
6845 /* update all of the pointers */
6846 skb_frag_size_sub(frag, pull_len);
6847 frag->page_offset += pull_len;
6848 skb->data_len -= pull_len;
6849 skb->tail += pull_len;
6850 }
6851
6852 /**
6853 * igb_cleanup_headers - Correct corrupted or empty headers
6854 * @rx_ring: rx descriptor ring packet is being transacted on
6855 * @rx_desc: pointer to the EOP Rx descriptor
6856 * @skb: pointer to current skb being fixed
6857 *
6858 * Address the case where we are pulling data in on pages only
6859 * and as such no data is present in the skb header.
6860 *
6861 * In addition if skb is not at least 60 bytes we need to pad it so that
6862 * it is large enough to qualify as a valid Ethernet frame.
6863 *
6864 * Returns true if an error was encountered and skb was freed.
6865 **/
6866 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6867 union e1000_adv_rx_desc *rx_desc,
6868 struct sk_buff *skb)
6869 {
6870 if (unlikely((igb_test_staterr(rx_desc,
6871 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6872 struct net_device *netdev = rx_ring->netdev;
6873 if (!(netdev->features & NETIF_F_RXALL)) {
6874 dev_kfree_skb_any(skb);
6875 return true;
6876 }
6877 }
6878
6879 /* place header in linear portion of buffer */
6880 if (skb_is_nonlinear(skb))
6881 igb_pull_tail(rx_ring, rx_desc, skb);
6882
6883 /* if eth_skb_pad returns an error the skb was freed */
6884 if (eth_skb_pad(skb))
6885 return true;
6886
6887 return false;
6888 }
6889
6890 /**
6891 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6892 * @rx_ring: rx descriptor ring packet is being transacted on
6893 * @rx_desc: pointer to the EOP Rx descriptor
6894 * @skb: pointer to current skb being populated
6895 *
6896 * This function checks the ring, descriptor, and packet information in
6897 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6898 * other fields within the skb.
6899 **/
6900 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6901 union e1000_adv_rx_desc *rx_desc,
6902 struct sk_buff *skb)
6903 {
6904 struct net_device *dev = rx_ring->netdev;
6905
6906 igb_rx_hash(rx_ring, rx_desc, skb);
6907
6908 igb_rx_checksum(rx_ring, rx_desc, skb);
6909
6910 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6911 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6912 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6913
6914 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6915 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6916 u16 vid;
6917
6918 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6919 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6920 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6921 else
6922 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6923
6924 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6925 }
6926
6927 skb_record_rx_queue(skb, rx_ring->queue_index);
6928
6929 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6930 }
6931
6932 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6933 {
6934 struct igb_ring *rx_ring = q_vector->rx.ring;
6935 struct sk_buff *skb = rx_ring->skb;
6936 unsigned int total_bytes = 0, total_packets = 0;
6937 u16 cleaned_count = igb_desc_unused(rx_ring);
6938
6939 while (likely(total_packets < budget)) {
6940 union e1000_adv_rx_desc *rx_desc;
6941
6942 /* return some buffers to hardware, one at a time is too slow */
6943 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6944 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6945 cleaned_count = 0;
6946 }
6947
6948 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6949
6950 if (!rx_desc->wb.upper.status_error)
6951 break;
6952
6953 /* This memory barrier is needed to keep us from reading
6954 * any other fields out of the rx_desc until we know the
6955 * descriptor has been written back
6956 */
6957 dma_rmb();
6958
6959 /* retrieve a buffer from the ring */
6960 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6961
6962 /* exit if we failed to retrieve a buffer */
6963 if (!skb)
6964 break;
6965
6966 cleaned_count++;
6967
6968 /* fetch next buffer in frame if non-eop */
6969 if (igb_is_non_eop(rx_ring, rx_desc))
6970 continue;
6971
6972 /* verify the packet layout is correct */
6973 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6974 skb = NULL;
6975 continue;
6976 }
6977
6978 /* probably a little skewed due to removing CRC */
6979 total_bytes += skb->len;
6980
6981 /* populate checksum, timestamp, VLAN, and protocol */
6982 igb_process_skb_fields(rx_ring, rx_desc, skb);
6983
6984 napi_gro_receive(&q_vector->napi, skb);
6985
6986 /* reset skb pointer */
6987 skb = NULL;
6988
6989 /* update budget accounting */
6990 total_packets++;
6991 }
6992
6993 /* place incomplete frames back on ring for completion */
6994 rx_ring->skb = skb;
6995
6996 u64_stats_update_begin(&rx_ring->rx_syncp);
6997 rx_ring->rx_stats.packets += total_packets;
6998 rx_ring->rx_stats.bytes += total_bytes;
6999 u64_stats_update_end(&rx_ring->rx_syncp);
7000 q_vector->rx.total_packets += total_packets;
7001 q_vector->rx.total_bytes += total_bytes;
7002
7003 if (cleaned_count)
7004 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7005
7006 return total_packets < budget;
7007 }
7008
7009 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
7010 struct igb_rx_buffer *bi)
7011 {
7012 struct page *page = bi->page;
7013 dma_addr_t dma;
7014
7015 /* since we are recycling buffers we should seldom need to alloc */
7016 if (likely(page))
7017 return true;
7018
7019 /* alloc new page for storage */
7020 page = dev_alloc_page();
7021 if (unlikely(!page)) {
7022 rx_ring->rx_stats.alloc_failed++;
7023 return false;
7024 }
7025
7026 /* map page for use */
7027 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7028
7029 /* if mapping failed free memory back to system since
7030 * there isn't much point in holding memory we can't use
7031 */
7032 if (dma_mapping_error(rx_ring->dev, dma)) {
7033 __free_page(page);
7034
7035 rx_ring->rx_stats.alloc_failed++;
7036 return false;
7037 }
7038
7039 bi->dma = dma;
7040 bi->page = page;
7041 bi->page_offset = 0;
7042
7043 return true;
7044 }
7045
7046 /**
7047 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7048 * @adapter: address of board private structure
7049 **/
7050 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7051 {
7052 union e1000_adv_rx_desc *rx_desc;
7053 struct igb_rx_buffer *bi;
7054 u16 i = rx_ring->next_to_use;
7055
7056 /* nothing to do */
7057 if (!cleaned_count)
7058 return;
7059
7060 rx_desc = IGB_RX_DESC(rx_ring, i);
7061 bi = &rx_ring->rx_buffer_info[i];
7062 i -= rx_ring->count;
7063
7064 do {
7065 if (!igb_alloc_mapped_page(rx_ring, bi))
7066 break;
7067
7068 /* Refresh the desc even if buffer_addrs didn't change
7069 * because each write-back erases this info.
7070 */
7071 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7072
7073 rx_desc++;
7074 bi++;
7075 i++;
7076 if (unlikely(!i)) {
7077 rx_desc = IGB_RX_DESC(rx_ring, 0);
7078 bi = rx_ring->rx_buffer_info;
7079 i -= rx_ring->count;
7080 }
7081
7082 /* clear the status bits for the next_to_use descriptor */
7083 rx_desc->wb.upper.status_error = 0;
7084
7085 cleaned_count--;
7086 } while (cleaned_count);
7087
7088 i += rx_ring->count;
7089
7090 if (rx_ring->next_to_use != i) {
7091 /* record the next descriptor to use */
7092 rx_ring->next_to_use = i;
7093
7094 /* update next to alloc since we have filled the ring */
7095 rx_ring->next_to_alloc = i;
7096
7097 /* Force memory writes to complete before letting h/w
7098 * know there are new descriptors to fetch. (Only
7099 * applicable for weak-ordered memory model archs,
7100 * such as IA-64).
7101 */
7102 wmb();
7103 writel(i, rx_ring->tail);
7104 }
7105 }
7106
7107 /**
7108 * igb_mii_ioctl -
7109 * @netdev:
7110 * @ifreq:
7111 * @cmd:
7112 **/
7113 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7114 {
7115 struct igb_adapter *adapter = netdev_priv(netdev);
7116 struct mii_ioctl_data *data = if_mii(ifr);
7117
7118 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7119 return -EOPNOTSUPP;
7120
7121 switch (cmd) {
7122 case SIOCGMIIPHY:
7123 data->phy_id = adapter->hw.phy.addr;
7124 break;
7125 case SIOCGMIIREG:
7126 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7127 &data->val_out))
7128 return -EIO;
7129 break;
7130 case SIOCSMIIREG:
7131 default:
7132 return -EOPNOTSUPP;
7133 }
7134 return 0;
7135 }
7136
7137 /**
7138 * igb_ioctl -
7139 * @netdev:
7140 * @ifreq:
7141 * @cmd:
7142 **/
7143 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7144 {
7145 switch (cmd) {
7146 case SIOCGMIIPHY:
7147 case SIOCGMIIREG:
7148 case SIOCSMIIREG:
7149 return igb_mii_ioctl(netdev, ifr, cmd);
7150 case SIOCGHWTSTAMP:
7151 return igb_ptp_get_ts_config(netdev, ifr);
7152 case SIOCSHWTSTAMP:
7153 return igb_ptp_set_ts_config(netdev, ifr);
7154 default:
7155 return -EOPNOTSUPP;
7156 }
7157 }
7158
7159 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7160 {
7161 struct igb_adapter *adapter = hw->back;
7162
7163 pci_read_config_word(adapter->pdev, reg, value);
7164 }
7165
7166 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7167 {
7168 struct igb_adapter *adapter = hw->back;
7169
7170 pci_write_config_word(adapter->pdev, reg, *value);
7171 }
7172
7173 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7174 {
7175 struct igb_adapter *adapter = hw->back;
7176
7177 if (pcie_capability_read_word(adapter->pdev, reg, value))
7178 return -E1000_ERR_CONFIG;
7179
7180 return 0;
7181 }
7182
7183 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7184 {
7185 struct igb_adapter *adapter = hw->back;
7186
7187 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7188 return -E1000_ERR_CONFIG;
7189
7190 return 0;
7191 }
7192
7193 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7194 {
7195 struct igb_adapter *adapter = netdev_priv(netdev);
7196 struct e1000_hw *hw = &adapter->hw;
7197 u32 ctrl, rctl;
7198 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7199
7200 if (enable) {
7201 /* enable VLAN tag insert/strip */
7202 ctrl = rd32(E1000_CTRL);
7203 ctrl |= E1000_CTRL_VME;
7204 wr32(E1000_CTRL, ctrl);
7205
7206 /* Disable CFI check */
7207 rctl = rd32(E1000_RCTL);
7208 rctl &= ~E1000_RCTL_CFIEN;
7209 wr32(E1000_RCTL, rctl);
7210 } else {
7211 /* disable VLAN tag insert/strip */
7212 ctrl = rd32(E1000_CTRL);
7213 ctrl &= ~E1000_CTRL_VME;
7214 wr32(E1000_CTRL, ctrl);
7215 }
7216
7217 igb_rlpml_set(adapter);
7218 }
7219
7220 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7221 __be16 proto, u16 vid)
7222 {
7223 struct igb_adapter *adapter = netdev_priv(netdev);
7224 struct e1000_hw *hw = &adapter->hw;
7225 int pf_id = adapter->vfs_allocated_count;
7226
7227 /* attempt to add filter to vlvf array */
7228 igb_vlvf_set(adapter, vid, true, pf_id);
7229
7230 /* add the filter since PF can receive vlans w/o entry in vlvf */
7231 igb_vfta_set(hw, vid, true);
7232
7233 set_bit(vid, adapter->active_vlans);
7234
7235 return 0;
7236 }
7237
7238 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7239 __be16 proto, u16 vid)
7240 {
7241 struct igb_adapter *adapter = netdev_priv(netdev);
7242 struct e1000_hw *hw = &adapter->hw;
7243 int pf_id = adapter->vfs_allocated_count;
7244 s32 err;
7245
7246 /* remove vlan from VLVF table array */
7247 err = igb_vlvf_set(adapter, vid, false, pf_id);
7248
7249 /* if vid was not present in VLVF just remove it from table */
7250 if (err)
7251 igb_vfta_set(hw, vid, false);
7252
7253 clear_bit(vid, adapter->active_vlans);
7254
7255 return 0;
7256 }
7257
7258 static void igb_restore_vlan(struct igb_adapter *adapter)
7259 {
7260 u16 vid;
7261
7262 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7263
7264 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7265 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7266 }
7267
7268 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7269 {
7270 struct pci_dev *pdev = adapter->pdev;
7271 struct e1000_mac_info *mac = &adapter->hw.mac;
7272
7273 mac->autoneg = 0;
7274
7275 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7276 * for the switch() below to work
7277 */
7278 if ((spd & 1) || (dplx & ~1))
7279 goto err_inval;
7280
7281 /* Fiber NIC's only allow 1000 gbps Full duplex
7282 * and 100Mbps Full duplex for 100baseFx sfp
7283 */
7284 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7285 switch (spd + dplx) {
7286 case SPEED_10 + DUPLEX_HALF:
7287 case SPEED_10 + DUPLEX_FULL:
7288 case SPEED_100 + DUPLEX_HALF:
7289 goto err_inval;
7290 default:
7291 break;
7292 }
7293 }
7294
7295 switch (spd + dplx) {
7296 case SPEED_10 + DUPLEX_HALF:
7297 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7298 break;
7299 case SPEED_10 + DUPLEX_FULL:
7300 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7301 break;
7302 case SPEED_100 + DUPLEX_HALF:
7303 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7304 break;
7305 case SPEED_100 + DUPLEX_FULL:
7306 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7307 break;
7308 case SPEED_1000 + DUPLEX_FULL:
7309 mac->autoneg = 1;
7310 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7311 break;
7312 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7313 default:
7314 goto err_inval;
7315 }
7316
7317 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7318 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7319
7320 return 0;
7321
7322 err_inval:
7323 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7324 return -EINVAL;
7325 }
7326
7327 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7328 bool runtime)
7329 {
7330 struct net_device *netdev = pci_get_drvdata(pdev);
7331 struct igb_adapter *adapter = netdev_priv(netdev);
7332 struct e1000_hw *hw = &adapter->hw;
7333 u32 ctrl, rctl, status;
7334 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7335 #ifdef CONFIG_PM
7336 int retval = 0;
7337 #endif
7338
7339 netif_device_detach(netdev);
7340
7341 if (netif_running(netdev))
7342 __igb_close(netdev, true);
7343
7344 igb_clear_interrupt_scheme(adapter);
7345
7346 #ifdef CONFIG_PM
7347 retval = pci_save_state(pdev);
7348 if (retval)
7349 return retval;
7350 #endif
7351
7352 status = rd32(E1000_STATUS);
7353 if (status & E1000_STATUS_LU)
7354 wufc &= ~E1000_WUFC_LNKC;
7355
7356 if (wufc) {
7357 igb_setup_rctl(adapter);
7358 igb_set_rx_mode(netdev);
7359
7360 /* turn on all-multi mode if wake on multicast is enabled */
7361 if (wufc & E1000_WUFC_MC) {
7362 rctl = rd32(E1000_RCTL);
7363 rctl |= E1000_RCTL_MPE;
7364 wr32(E1000_RCTL, rctl);
7365 }
7366
7367 ctrl = rd32(E1000_CTRL);
7368 /* advertise wake from D3Cold */
7369 #define E1000_CTRL_ADVD3WUC 0x00100000
7370 /* phy power management enable */
7371 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7372 ctrl |= E1000_CTRL_ADVD3WUC;
7373 wr32(E1000_CTRL, ctrl);
7374
7375 /* Allow time for pending master requests to run */
7376 igb_disable_pcie_master(hw);
7377
7378 wr32(E1000_WUC, E1000_WUC_PME_EN);
7379 wr32(E1000_WUFC, wufc);
7380 } else {
7381 wr32(E1000_WUC, 0);
7382 wr32(E1000_WUFC, 0);
7383 }
7384
7385 *enable_wake = wufc || adapter->en_mng_pt;
7386 if (!*enable_wake)
7387 igb_power_down_link(adapter);
7388 else
7389 igb_power_up_link(adapter);
7390
7391 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7392 * would have already happened in close and is redundant.
7393 */
7394 igb_release_hw_control(adapter);
7395
7396 pci_disable_device(pdev);
7397
7398 return 0;
7399 }
7400
7401 #ifdef CONFIG_PM
7402 #ifdef CONFIG_PM_SLEEP
7403 static int igb_suspend(struct device *dev)
7404 {
7405 int retval;
7406 bool wake;
7407 struct pci_dev *pdev = to_pci_dev(dev);
7408
7409 retval = __igb_shutdown(pdev, &wake, 0);
7410 if (retval)
7411 return retval;
7412
7413 if (wake) {
7414 pci_prepare_to_sleep(pdev);
7415 } else {
7416 pci_wake_from_d3(pdev, false);
7417 pci_set_power_state(pdev, PCI_D3hot);
7418 }
7419
7420 return 0;
7421 }
7422 #endif /* CONFIG_PM_SLEEP */
7423
7424 static int igb_resume(struct device *dev)
7425 {
7426 struct pci_dev *pdev = to_pci_dev(dev);
7427 struct net_device *netdev = pci_get_drvdata(pdev);
7428 struct igb_adapter *adapter = netdev_priv(netdev);
7429 struct e1000_hw *hw = &adapter->hw;
7430 u32 err;
7431
7432 pci_set_power_state(pdev, PCI_D0);
7433 pci_restore_state(pdev);
7434 pci_save_state(pdev);
7435
7436 if (!pci_device_is_present(pdev))
7437 return -ENODEV;
7438 err = pci_enable_device_mem(pdev);
7439 if (err) {
7440 dev_err(&pdev->dev,
7441 "igb: Cannot enable PCI device from suspend\n");
7442 return err;
7443 }
7444 pci_set_master(pdev);
7445
7446 pci_enable_wake(pdev, PCI_D3hot, 0);
7447 pci_enable_wake(pdev, PCI_D3cold, 0);
7448
7449 if (igb_init_interrupt_scheme(adapter, true)) {
7450 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7451 return -ENOMEM;
7452 }
7453
7454 igb_reset(adapter);
7455
7456 /* let the f/w know that the h/w is now under the control of the
7457 * driver.
7458 */
7459 igb_get_hw_control(adapter);
7460
7461 wr32(E1000_WUS, ~0);
7462
7463 if (netdev->flags & IFF_UP) {
7464 rtnl_lock();
7465 err = __igb_open(netdev, true);
7466 rtnl_unlock();
7467 if (err)
7468 return err;
7469 }
7470
7471 netif_device_attach(netdev);
7472 return 0;
7473 }
7474
7475 static int igb_runtime_idle(struct device *dev)
7476 {
7477 struct pci_dev *pdev = to_pci_dev(dev);
7478 struct net_device *netdev = pci_get_drvdata(pdev);
7479 struct igb_adapter *adapter = netdev_priv(netdev);
7480
7481 if (!igb_has_link(adapter))
7482 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7483
7484 return -EBUSY;
7485 }
7486
7487 static int igb_runtime_suspend(struct device *dev)
7488 {
7489 struct pci_dev *pdev = to_pci_dev(dev);
7490 int retval;
7491 bool wake;
7492
7493 retval = __igb_shutdown(pdev, &wake, 1);
7494 if (retval)
7495 return retval;
7496
7497 if (wake) {
7498 pci_prepare_to_sleep(pdev);
7499 } else {
7500 pci_wake_from_d3(pdev, false);
7501 pci_set_power_state(pdev, PCI_D3hot);
7502 }
7503
7504 return 0;
7505 }
7506
7507 static int igb_runtime_resume(struct device *dev)
7508 {
7509 return igb_resume(dev);
7510 }
7511 #endif /* CONFIG_PM */
7512
7513 static void igb_shutdown(struct pci_dev *pdev)
7514 {
7515 bool wake;
7516
7517 __igb_shutdown(pdev, &wake, 0);
7518
7519 if (system_state == SYSTEM_POWER_OFF) {
7520 pci_wake_from_d3(pdev, wake);
7521 pci_set_power_state(pdev, PCI_D3hot);
7522 }
7523 }
7524
7525 #ifdef CONFIG_PCI_IOV
7526 static int igb_sriov_reinit(struct pci_dev *dev)
7527 {
7528 struct net_device *netdev = pci_get_drvdata(dev);
7529 struct igb_adapter *adapter = netdev_priv(netdev);
7530 struct pci_dev *pdev = adapter->pdev;
7531
7532 rtnl_lock();
7533
7534 if (netif_running(netdev))
7535 igb_close(netdev);
7536 else
7537 igb_reset(adapter);
7538
7539 igb_clear_interrupt_scheme(adapter);
7540
7541 igb_init_queue_configuration(adapter);
7542
7543 if (igb_init_interrupt_scheme(adapter, true)) {
7544 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7545 return -ENOMEM;
7546 }
7547
7548 if (netif_running(netdev))
7549 igb_open(netdev);
7550
7551 rtnl_unlock();
7552
7553 return 0;
7554 }
7555
7556 static int igb_pci_disable_sriov(struct pci_dev *dev)
7557 {
7558 int err = igb_disable_sriov(dev);
7559
7560 if (!err)
7561 err = igb_sriov_reinit(dev);
7562
7563 return err;
7564 }
7565
7566 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7567 {
7568 int err = igb_enable_sriov(dev, num_vfs);
7569
7570 if (err)
7571 goto out;
7572
7573 err = igb_sriov_reinit(dev);
7574 if (!err)
7575 return num_vfs;
7576
7577 out:
7578 return err;
7579 }
7580
7581 #endif
7582 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7583 {
7584 #ifdef CONFIG_PCI_IOV
7585 if (num_vfs == 0)
7586 return igb_pci_disable_sriov(dev);
7587 else
7588 return igb_pci_enable_sriov(dev, num_vfs);
7589 #endif
7590 return 0;
7591 }
7592
7593 #ifdef CONFIG_NET_POLL_CONTROLLER
7594 /* Polling 'interrupt' - used by things like netconsole to send skbs
7595 * without having to re-enable interrupts. It's not called while
7596 * the interrupt routine is executing.
7597 */
7598 static void igb_netpoll(struct net_device *netdev)
7599 {
7600 struct igb_adapter *adapter = netdev_priv(netdev);
7601 struct e1000_hw *hw = &adapter->hw;
7602 struct igb_q_vector *q_vector;
7603 int i;
7604
7605 for (i = 0; i < adapter->num_q_vectors; i++) {
7606 q_vector = adapter->q_vector[i];
7607 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7608 wr32(E1000_EIMC, q_vector->eims_value);
7609 else
7610 igb_irq_disable(adapter);
7611 napi_schedule(&q_vector->napi);
7612 }
7613 }
7614 #endif /* CONFIG_NET_POLL_CONTROLLER */
7615
7616 /**
7617 * igb_io_error_detected - called when PCI error is detected
7618 * @pdev: Pointer to PCI device
7619 * @state: The current pci connection state
7620 *
7621 * This function is called after a PCI bus error affecting
7622 * this device has been detected.
7623 **/
7624 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7625 pci_channel_state_t state)
7626 {
7627 struct net_device *netdev = pci_get_drvdata(pdev);
7628 struct igb_adapter *adapter = netdev_priv(netdev);
7629
7630 netif_device_detach(netdev);
7631
7632 if (state == pci_channel_io_perm_failure)
7633 return PCI_ERS_RESULT_DISCONNECT;
7634
7635 if (netif_running(netdev))
7636 igb_down(adapter);
7637 pci_disable_device(pdev);
7638
7639 /* Request a slot slot reset. */
7640 return PCI_ERS_RESULT_NEED_RESET;
7641 }
7642
7643 /**
7644 * igb_io_slot_reset - called after the pci bus has been reset.
7645 * @pdev: Pointer to PCI device
7646 *
7647 * Restart the card from scratch, as if from a cold-boot. Implementation
7648 * resembles the first-half of the igb_resume routine.
7649 **/
7650 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7651 {
7652 struct net_device *netdev = pci_get_drvdata(pdev);
7653 struct igb_adapter *adapter = netdev_priv(netdev);
7654 struct e1000_hw *hw = &adapter->hw;
7655 pci_ers_result_t result;
7656 int err;
7657
7658 if (pci_enable_device_mem(pdev)) {
7659 dev_err(&pdev->dev,
7660 "Cannot re-enable PCI device after reset.\n");
7661 result = PCI_ERS_RESULT_DISCONNECT;
7662 } else {
7663 pci_set_master(pdev);
7664 pci_restore_state(pdev);
7665 pci_save_state(pdev);
7666
7667 pci_enable_wake(pdev, PCI_D3hot, 0);
7668 pci_enable_wake(pdev, PCI_D3cold, 0);
7669
7670 igb_reset(adapter);
7671 wr32(E1000_WUS, ~0);
7672 result = PCI_ERS_RESULT_RECOVERED;
7673 }
7674
7675 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7676 if (err) {
7677 dev_err(&pdev->dev,
7678 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7679 err);
7680 /* non-fatal, continue */
7681 }
7682
7683 return result;
7684 }
7685
7686 /**
7687 * igb_io_resume - called when traffic can start flowing again.
7688 * @pdev: Pointer to PCI device
7689 *
7690 * This callback is called when the error recovery driver tells us that
7691 * its OK to resume normal operation. Implementation resembles the
7692 * second-half of the igb_resume routine.
7693 */
7694 static void igb_io_resume(struct pci_dev *pdev)
7695 {
7696 struct net_device *netdev = pci_get_drvdata(pdev);
7697 struct igb_adapter *adapter = netdev_priv(netdev);
7698
7699 if (netif_running(netdev)) {
7700 if (igb_up(adapter)) {
7701 dev_err(&pdev->dev, "igb_up failed after reset\n");
7702 return;
7703 }
7704 }
7705
7706 netif_device_attach(netdev);
7707
7708 /* let the f/w know that the h/w is now under the control of the
7709 * driver.
7710 */
7711 igb_get_hw_control(adapter);
7712 }
7713
7714 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7715 u8 qsel)
7716 {
7717 u32 rar_low, rar_high;
7718 struct e1000_hw *hw = &adapter->hw;
7719
7720 /* HW expects these in little endian so we reverse the byte order
7721 * from network order (big endian) to little endian
7722 */
7723 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7724 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7725 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7726
7727 /* Indicate to hardware the Address is Valid. */
7728 rar_high |= E1000_RAH_AV;
7729
7730 if (hw->mac.type == e1000_82575)
7731 rar_high |= E1000_RAH_POOL_1 * qsel;
7732 else
7733 rar_high |= E1000_RAH_POOL_1 << qsel;
7734
7735 wr32(E1000_RAL(index), rar_low);
7736 wrfl();
7737 wr32(E1000_RAH(index), rar_high);
7738 wrfl();
7739 }
7740
7741 static int igb_set_vf_mac(struct igb_adapter *adapter,
7742 int vf, unsigned char *mac_addr)
7743 {
7744 struct e1000_hw *hw = &adapter->hw;
7745 /* VF MAC addresses start at end of receive addresses and moves
7746 * towards the first, as a result a collision should not be possible
7747 */
7748 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7749
7750 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7751
7752 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7753
7754 return 0;
7755 }
7756
7757 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7758 {
7759 struct igb_adapter *adapter = netdev_priv(netdev);
7760 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7761 return -EINVAL;
7762 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7763 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7764 dev_info(&adapter->pdev->dev,
7765 "Reload the VF driver to make this change effective.");
7766 if (test_bit(__IGB_DOWN, &adapter->state)) {
7767 dev_warn(&adapter->pdev->dev,
7768 "The VF MAC address has been set, but the PF device is not up.\n");
7769 dev_warn(&adapter->pdev->dev,
7770 "Bring the PF device up before attempting to use the VF device.\n");
7771 }
7772 return igb_set_vf_mac(adapter, vf, mac);
7773 }
7774
7775 static int igb_link_mbps(int internal_link_speed)
7776 {
7777 switch (internal_link_speed) {
7778 case SPEED_100:
7779 return 100;
7780 case SPEED_1000:
7781 return 1000;
7782 default:
7783 return 0;
7784 }
7785 }
7786
7787 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7788 int link_speed)
7789 {
7790 int rf_dec, rf_int;
7791 u32 bcnrc_val;
7792
7793 if (tx_rate != 0) {
7794 /* Calculate the rate factor values to set */
7795 rf_int = link_speed / tx_rate;
7796 rf_dec = (link_speed - (rf_int * tx_rate));
7797 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7798 tx_rate;
7799
7800 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7801 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7802 E1000_RTTBCNRC_RF_INT_MASK);
7803 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7804 } else {
7805 bcnrc_val = 0;
7806 }
7807
7808 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7809 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7810 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7811 */
7812 wr32(E1000_RTTBCNRM, 0x14);
7813 wr32(E1000_RTTBCNRC, bcnrc_val);
7814 }
7815
7816 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7817 {
7818 int actual_link_speed, i;
7819 bool reset_rate = false;
7820
7821 /* VF TX rate limit was not set or not supported */
7822 if ((adapter->vf_rate_link_speed == 0) ||
7823 (adapter->hw.mac.type != e1000_82576))
7824 return;
7825
7826 actual_link_speed = igb_link_mbps(adapter->link_speed);
7827 if (actual_link_speed != adapter->vf_rate_link_speed) {
7828 reset_rate = true;
7829 adapter->vf_rate_link_speed = 0;
7830 dev_info(&adapter->pdev->dev,
7831 "Link speed has been changed. VF Transmit rate is disabled\n");
7832 }
7833
7834 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7835 if (reset_rate)
7836 adapter->vf_data[i].tx_rate = 0;
7837
7838 igb_set_vf_rate_limit(&adapter->hw, i,
7839 adapter->vf_data[i].tx_rate,
7840 actual_link_speed);
7841 }
7842 }
7843
7844 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7845 int min_tx_rate, int max_tx_rate)
7846 {
7847 struct igb_adapter *adapter = netdev_priv(netdev);
7848 struct e1000_hw *hw = &adapter->hw;
7849 int actual_link_speed;
7850
7851 if (hw->mac.type != e1000_82576)
7852 return -EOPNOTSUPP;
7853
7854 if (min_tx_rate)
7855 return -EINVAL;
7856
7857 actual_link_speed = igb_link_mbps(adapter->link_speed);
7858 if ((vf >= adapter->vfs_allocated_count) ||
7859 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7860 (max_tx_rate < 0) ||
7861 (max_tx_rate > actual_link_speed))
7862 return -EINVAL;
7863
7864 adapter->vf_rate_link_speed = actual_link_speed;
7865 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7866 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7867
7868 return 0;
7869 }
7870
7871 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7872 bool setting)
7873 {
7874 struct igb_adapter *adapter = netdev_priv(netdev);
7875 struct e1000_hw *hw = &adapter->hw;
7876 u32 reg_val, reg_offset;
7877
7878 if (!adapter->vfs_allocated_count)
7879 return -EOPNOTSUPP;
7880
7881 if (vf >= adapter->vfs_allocated_count)
7882 return -EINVAL;
7883
7884 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7885 reg_val = rd32(reg_offset);
7886 if (setting)
7887 reg_val |= ((1 << vf) |
7888 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7889 else
7890 reg_val &= ~((1 << vf) |
7891 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7892 wr32(reg_offset, reg_val);
7893
7894 adapter->vf_data[vf].spoofchk_enabled = setting;
7895 return 0;
7896 }
7897
7898 static int igb_ndo_get_vf_config(struct net_device *netdev,
7899 int vf, struct ifla_vf_info *ivi)
7900 {
7901 struct igb_adapter *adapter = netdev_priv(netdev);
7902 if (vf >= adapter->vfs_allocated_count)
7903 return -EINVAL;
7904 ivi->vf = vf;
7905 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7906 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7907 ivi->min_tx_rate = 0;
7908 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7909 ivi->qos = adapter->vf_data[vf].pf_qos;
7910 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7911 return 0;
7912 }
7913
7914 static void igb_vmm_control(struct igb_adapter *adapter)
7915 {
7916 struct e1000_hw *hw = &adapter->hw;
7917 u32 reg;
7918
7919 switch (hw->mac.type) {
7920 case e1000_82575:
7921 case e1000_i210:
7922 case e1000_i211:
7923 case e1000_i354:
7924 default:
7925 /* replication is not supported for 82575 */
7926 return;
7927 case e1000_82576:
7928 /* notify HW that the MAC is adding vlan tags */
7929 reg = rd32(E1000_DTXCTL);
7930 reg |= E1000_DTXCTL_VLAN_ADDED;
7931 wr32(E1000_DTXCTL, reg);
7932 /* Fall through */
7933 case e1000_82580:
7934 /* enable replication vlan tag stripping */
7935 reg = rd32(E1000_RPLOLR);
7936 reg |= E1000_RPLOLR_STRVLAN;
7937 wr32(E1000_RPLOLR, reg);
7938 /* Fall through */
7939 case e1000_i350:
7940 /* none of the above registers are supported by i350 */
7941 break;
7942 }
7943
7944 if (adapter->vfs_allocated_count) {
7945 igb_vmdq_set_loopback_pf(hw, true);
7946 igb_vmdq_set_replication_pf(hw, true);
7947 igb_vmdq_set_anti_spoofing_pf(hw, true,
7948 adapter->vfs_allocated_count);
7949 } else {
7950 igb_vmdq_set_loopback_pf(hw, false);
7951 igb_vmdq_set_replication_pf(hw, false);
7952 }
7953 }
7954
7955 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7956 {
7957 struct e1000_hw *hw = &adapter->hw;
7958 u32 dmac_thr;
7959 u16 hwm;
7960
7961 if (hw->mac.type > e1000_82580) {
7962 if (adapter->flags & IGB_FLAG_DMAC) {
7963 u32 reg;
7964
7965 /* force threshold to 0. */
7966 wr32(E1000_DMCTXTH, 0);
7967
7968 /* DMA Coalescing high water mark needs to be greater
7969 * than the Rx threshold. Set hwm to PBA - max frame
7970 * size in 16B units, capping it at PBA - 6KB.
7971 */
7972 hwm = 64 * pba - adapter->max_frame_size / 16;
7973 if (hwm < 64 * (pba - 6))
7974 hwm = 64 * (pba - 6);
7975 reg = rd32(E1000_FCRTC);
7976 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7977 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7978 & E1000_FCRTC_RTH_COAL_MASK);
7979 wr32(E1000_FCRTC, reg);
7980
7981 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7982 * frame size, capping it at PBA - 10KB.
7983 */
7984 dmac_thr = pba - adapter->max_frame_size / 512;
7985 if (dmac_thr < pba - 10)
7986 dmac_thr = pba - 10;
7987 reg = rd32(E1000_DMACR);
7988 reg &= ~E1000_DMACR_DMACTHR_MASK;
7989 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7990 & E1000_DMACR_DMACTHR_MASK);
7991
7992 /* transition to L0x or L1 if available..*/
7993 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7994
7995 /* watchdog timer= +-1000 usec in 32usec intervals */
7996 reg |= (1000 >> 5);
7997
7998 /* Disable BMC-to-OS Watchdog Enable */
7999 if (hw->mac.type != e1000_i354)
8000 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8001
8002 wr32(E1000_DMACR, reg);
8003
8004 /* no lower threshold to disable
8005 * coalescing(smart fifb)-UTRESH=0
8006 */
8007 wr32(E1000_DMCRTRH, 0);
8008
8009 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8010
8011 wr32(E1000_DMCTLX, reg);
8012
8013 /* free space in tx packet buffer to wake from
8014 * DMA coal
8015 */
8016 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8017 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8018
8019 /* make low power state decision controlled
8020 * by DMA coal
8021 */
8022 reg = rd32(E1000_PCIEMISC);
8023 reg &= ~E1000_PCIEMISC_LX_DECISION;
8024 wr32(E1000_PCIEMISC, reg);
8025 } /* endif adapter->dmac is not disabled */
8026 } else if (hw->mac.type == e1000_82580) {
8027 u32 reg = rd32(E1000_PCIEMISC);
8028
8029 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8030 wr32(E1000_DMACR, 0);
8031 }
8032 }
8033
8034 /**
8035 * igb_read_i2c_byte - Reads 8 bit word over I2C
8036 * @hw: pointer to hardware structure
8037 * @byte_offset: byte offset to read
8038 * @dev_addr: device address
8039 * @data: value read
8040 *
8041 * Performs byte read operation over I2C interface at
8042 * a specified device address.
8043 **/
8044 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8045 u8 dev_addr, u8 *data)
8046 {
8047 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8048 struct i2c_client *this_client = adapter->i2c_client;
8049 s32 status;
8050 u16 swfw_mask = 0;
8051
8052 if (!this_client)
8053 return E1000_ERR_I2C;
8054
8055 swfw_mask = E1000_SWFW_PHY0_SM;
8056
8057 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8058 return E1000_ERR_SWFW_SYNC;
8059
8060 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8061 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8062
8063 if (status < 0)
8064 return E1000_ERR_I2C;
8065 else {
8066 *data = status;
8067 return 0;
8068 }
8069 }
8070
8071 /**
8072 * igb_write_i2c_byte - Writes 8 bit word over I2C
8073 * @hw: pointer to hardware structure
8074 * @byte_offset: byte offset to write
8075 * @dev_addr: device address
8076 * @data: value to write
8077 *
8078 * Performs byte write operation over I2C interface at
8079 * a specified device address.
8080 **/
8081 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8082 u8 dev_addr, u8 data)
8083 {
8084 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8085 struct i2c_client *this_client = adapter->i2c_client;
8086 s32 status;
8087 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8088
8089 if (!this_client)
8090 return E1000_ERR_I2C;
8091
8092 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8093 return E1000_ERR_SWFW_SYNC;
8094 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8095 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8096
8097 if (status)
8098 return E1000_ERR_I2C;
8099 else
8100 return 0;
8101
8102 }
8103
8104 int igb_reinit_queues(struct igb_adapter *adapter)
8105 {
8106 struct net_device *netdev = adapter->netdev;
8107 struct pci_dev *pdev = adapter->pdev;
8108 int err = 0;
8109
8110 if (netif_running(netdev))
8111 igb_close(netdev);
8112
8113 igb_reset_interrupt_capability(adapter);
8114
8115 if (igb_init_interrupt_scheme(adapter, true)) {
8116 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8117 return -ENOMEM;
8118 }
8119
8120 if (netif_running(netdev))
8121 err = igb_open(netdev);
8122
8123 return err;
8124 }
8125 /* igb_main.c */
Linux kernel - Deliverables
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