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[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/bitops.h>
32 #include <linux/vmalloc.h>
33 #include <linux/pagemap.h>
34 #include <linux/netdevice.h>
35 #include <linux/ipv6.h>
36 #include <linux/slab.h>
37 #include <net/checksum.h>
38 #include <net/ip6_checksum.h>
39 #include <linux/net_tstamp.h>
40 #include <linux/mii.h>
41 #include <linux/ethtool.h>
42 #include <linux/if.h>
43 #include <linux/if_vlan.h>
44 #include <linux/pci.h>
45 #include <linux/pci-aspm.h>
46 #include <linux/delay.h>
47 #include <linux/interrupt.h>
48 #include <linux/ip.h>
49 #include <linux/tcp.h>
50 #include <linux/sctp.h>
51 #include <linux/if_ether.h>
52 #include <linux/aer.h>
53 #include <linux/prefetch.h>
54 #ifdef CONFIG_IGB_DCA
55 #include <linux/dca.h>
56 #endif
57 #include "igb.h"
58
59 #define MAJ 3
60 #define MIN 0
61 #define BUILD 6
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation.";
69
70 static const struct e1000_info *igb_info_tbl[] = {
71 [board_82575] = &e1000_82575_info,
72 };
73
74 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
100 /* required last entry */
101 {0, }
102 };
103
104 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
105
106 void igb_reset(struct igb_adapter *);
107 static int igb_setup_all_tx_resources(struct igb_adapter *);
108 static int igb_setup_all_rx_resources(struct igb_adapter *);
109 static void igb_free_all_tx_resources(struct igb_adapter *);
110 static void igb_free_all_rx_resources(struct igb_adapter *);
111 static void igb_setup_mrqc(struct igb_adapter *);
112 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
113 static void __devexit igb_remove(struct pci_dev *pdev);
114 static void igb_init_hw_timer(struct igb_adapter *adapter);
115 static int igb_sw_init(struct igb_adapter *);
116 static int igb_open(struct net_device *);
117 static int igb_close(struct net_device *);
118 static void igb_configure_tx(struct igb_adapter *);
119 static void igb_configure_rx(struct igb_adapter *);
120 static void igb_clean_all_tx_rings(struct igb_adapter *);
121 static void igb_clean_all_rx_rings(struct igb_adapter *);
122 static void igb_clean_tx_ring(struct igb_ring *);
123 static void igb_clean_rx_ring(struct igb_ring *);
124 static void igb_set_rx_mode(struct net_device *);
125 static void igb_update_phy_info(unsigned long);
126 static void igb_watchdog(unsigned long);
127 static void igb_watchdog_task(struct work_struct *);
128 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
129 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
130 struct rtnl_link_stats64 *stats);
131 static int igb_change_mtu(struct net_device *, int);
132 static int igb_set_mac(struct net_device *, void *);
133 static void igb_set_uta(struct igb_adapter *adapter);
134 static irqreturn_t igb_intr(int irq, void *);
135 static irqreturn_t igb_intr_msi(int irq, void *);
136 static irqreturn_t igb_msix_other(int irq, void *);
137 static irqreturn_t igb_msix_ring(int irq, void *);
138 #ifdef CONFIG_IGB_DCA
139 static void igb_update_dca(struct igb_q_vector *);
140 static void igb_setup_dca(struct igb_adapter *);
141 #endif /* CONFIG_IGB_DCA */
142 static int igb_poll(struct napi_struct *, int);
143 static bool igb_clean_tx_irq(struct igb_q_vector *);
144 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
145 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
146 static void igb_tx_timeout(struct net_device *);
147 static void igb_reset_task(struct work_struct *);
148 static void igb_vlan_mode(struct net_device *netdev, u32 features);
149 static void igb_vlan_rx_add_vid(struct net_device *, u16);
150 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
151 static void igb_restore_vlan(struct igb_adapter *);
152 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
153 static void igb_ping_all_vfs(struct igb_adapter *);
154 static void igb_msg_task(struct igb_adapter *);
155 static void igb_vmm_control(struct igb_adapter *);
156 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
157 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
158 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
159 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
160 int vf, u16 vlan, u8 qos);
161 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
162 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
163 struct ifla_vf_info *ivi);
164 static void igb_check_vf_rate_limit(struct igb_adapter *);
165
166 #ifdef CONFIG_PM
167 static int igb_suspend(struct pci_dev *, pm_message_t);
168 static int igb_resume(struct pci_dev *);
169 #endif
170 static void igb_shutdown(struct pci_dev *);
171 #ifdef CONFIG_IGB_DCA
172 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
173 static struct notifier_block dca_notifier = {
174 .notifier_call = igb_notify_dca,
175 .next = NULL,
176 .priority = 0
177 };
178 #endif
179 #ifdef CONFIG_NET_POLL_CONTROLLER
180 /* for netdump / net console */
181 static void igb_netpoll(struct net_device *);
182 #endif
183 #ifdef CONFIG_PCI_IOV
184 static unsigned int max_vfs = 0;
185 module_param(max_vfs, uint, 0);
186 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
187 "per physical function");
188 #endif /* CONFIG_PCI_IOV */
189
190 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
191 pci_channel_state_t);
192 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
193 static void igb_io_resume(struct pci_dev *);
194
195 static struct pci_error_handlers igb_err_handler = {
196 .error_detected = igb_io_error_detected,
197 .slot_reset = igb_io_slot_reset,
198 .resume = igb_io_resume,
199 };
200
201
202 static struct pci_driver igb_driver = {
203 .name = igb_driver_name,
204 .id_table = igb_pci_tbl,
205 .probe = igb_probe,
206 .remove = __devexit_p(igb_remove),
207 #ifdef CONFIG_PM
208 /* Power Management Hooks */
209 .suspend = igb_suspend,
210 .resume = igb_resume,
211 #endif
212 .shutdown = igb_shutdown,
213 .err_handler = &igb_err_handler
214 };
215
216 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
217 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
218 MODULE_LICENSE("GPL");
219 MODULE_VERSION(DRV_VERSION);
220
221 struct igb_reg_info {
222 u32 ofs;
223 char *name;
224 };
225
226 static const struct igb_reg_info igb_reg_info_tbl[] = {
227
228 /* General Registers */
229 {E1000_CTRL, "CTRL"},
230 {E1000_STATUS, "STATUS"},
231 {E1000_CTRL_EXT, "CTRL_EXT"},
232
233 /* Interrupt Registers */
234 {E1000_ICR, "ICR"},
235
236 /* RX Registers */
237 {E1000_RCTL, "RCTL"},
238 {E1000_RDLEN(0), "RDLEN"},
239 {E1000_RDH(0), "RDH"},
240 {E1000_RDT(0), "RDT"},
241 {E1000_RXDCTL(0), "RXDCTL"},
242 {E1000_RDBAL(0), "RDBAL"},
243 {E1000_RDBAH(0), "RDBAH"},
244
245 /* TX Registers */
246 {E1000_TCTL, "TCTL"},
247 {E1000_TDBAL(0), "TDBAL"},
248 {E1000_TDBAH(0), "TDBAH"},
249 {E1000_TDLEN(0), "TDLEN"},
250 {E1000_TDH(0), "TDH"},
251 {E1000_TDT(0), "TDT"},
252 {E1000_TXDCTL(0), "TXDCTL"},
253 {E1000_TDFH, "TDFH"},
254 {E1000_TDFT, "TDFT"},
255 {E1000_TDFHS, "TDFHS"},
256 {E1000_TDFPC, "TDFPC"},
257
258 /* List Terminator */
259 {}
260 };
261
262 /*
263 * igb_regdump - register printout routine
264 */
265 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
266 {
267 int n = 0;
268 char rname[16];
269 u32 regs[8];
270
271 switch (reginfo->ofs) {
272 case E1000_RDLEN(0):
273 for (n = 0; n < 4; n++)
274 regs[n] = rd32(E1000_RDLEN(n));
275 break;
276 case E1000_RDH(0):
277 for (n = 0; n < 4; n++)
278 regs[n] = rd32(E1000_RDH(n));
279 break;
280 case E1000_RDT(0):
281 for (n = 0; n < 4; n++)
282 regs[n] = rd32(E1000_RDT(n));
283 break;
284 case E1000_RXDCTL(0):
285 for (n = 0; n < 4; n++)
286 regs[n] = rd32(E1000_RXDCTL(n));
287 break;
288 case E1000_RDBAL(0):
289 for (n = 0; n < 4; n++)
290 regs[n] = rd32(E1000_RDBAL(n));
291 break;
292 case E1000_RDBAH(0):
293 for (n = 0; n < 4; n++)
294 regs[n] = rd32(E1000_RDBAH(n));
295 break;
296 case E1000_TDBAL(0):
297 for (n = 0; n < 4; n++)
298 regs[n] = rd32(E1000_RDBAL(n));
299 break;
300 case E1000_TDBAH(0):
301 for (n = 0; n < 4; n++)
302 regs[n] = rd32(E1000_TDBAH(n));
303 break;
304 case E1000_TDLEN(0):
305 for (n = 0; n < 4; n++)
306 regs[n] = rd32(E1000_TDLEN(n));
307 break;
308 case E1000_TDH(0):
309 for (n = 0; n < 4; n++)
310 regs[n] = rd32(E1000_TDH(n));
311 break;
312 case E1000_TDT(0):
313 for (n = 0; n < 4; n++)
314 regs[n] = rd32(E1000_TDT(n));
315 break;
316 case E1000_TXDCTL(0):
317 for (n = 0; n < 4; n++)
318 regs[n] = rd32(E1000_TXDCTL(n));
319 break;
320 default:
321 printk(KERN_INFO "%-15s %08x\n",
322 reginfo->name, rd32(reginfo->ofs));
323 return;
324 }
325
326 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
327 printk(KERN_INFO "%-15s ", rname);
328 for (n = 0; n < 4; n++)
329 printk(KERN_CONT "%08x ", regs[n]);
330 printk(KERN_CONT "\n");
331 }
332
333 /*
334 * igb_dump - Print registers, tx-rings and rx-rings
335 */
336 static void igb_dump(struct igb_adapter *adapter)
337 {
338 struct net_device *netdev = adapter->netdev;
339 struct e1000_hw *hw = &adapter->hw;
340 struct igb_reg_info *reginfo;
341 int n = 0;
342 struct igb_ring *tx_ring;
343 union e1000_adv_tx_desc *tx_desc;
344 struct my_u0 { u64 a; u64 b; } *u0;
345 struct igb_ring *rx_ring;
346 union e1000_adv_rx_desc *rx_desc;
347 u32 staterr;
348 int i = 0;
349
350 if (!netif_msg_hw(adapter))
351 return;
352
353 /* Print netdevice Info */
354 if (netdev) {
355 dev_info(&adapter->pdev->dev, "Net device Info\n");
356 printk(KERN_INFO "Device Name state "
357 "trans_start last_rx\n");
358 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
359 netdev->name,
360 netdev->state,
361 netdev->trans_start,
362 netdev->last_rx);
363 }
364
365 /* Print Registers */
366 dev_info(&adapter->pdev->dev, "Register Dump\n");
367 printk(KERN_INFO " Register Name Value\n");
368 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
369 reginfo->name; reginfo++) {
370 igb_regdump(hw, reginfo);
371 }
372
373 /* Print TX Ring Summary */
374 if (!netdev || !netif_running(netdev))
375 goto exit;
376
377 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
378 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]"
379 " leng ntw timestamp\n");
380 for (n = 0; n < adapter->num_tx_queues; n++) {
381 struct igb_tx_buffer *buffer_info;
382 tx_ring = adapter->tx_ring[n];
383 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
384 printk(KERN_INFO " %5d %5X %5X %016llX %04X %p %016llX\n",
385 n, tx_ring->next_to_use, tx_ring->next_to_clean,
386 (u64)buffer_info->dma,
387 buffer_info->length,
388 buffer_info->next_to_watch,
389 (u64)buffer_info->time_stamp);
390 }
391
392 /* Print TX Rings */
393 if (!netif_msg_tx_done(adapter))
394 goto rx_ring_summary;
395
396 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
397
398 /* Transmit Descriptor Formats
399 *
400 * Advanced Transmit Descriptor
401 * +--------------------------------------------------------------+
402 * 0 | Buffer Address [63:0] |
403 * +--------------------------------------------------------------+
404 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
405 * +--------------------------------------------------------------+
406 * 63 46 45 40 39 38 36 35 32 31 24 15 0
407 */
408
409 for (n = 0; n < adapter->num_tx_queues; n++) {
410 tx_ring = adapter->tx_ring[n];
411 printk(KERN_INFO "------------------------------------\n");
412 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
413 printk(KERN_INFO "------------------------------------\n");
414 printk(KERN_INFO "T [desc] [address 63:0 ] "
415 "[PlPOCIStDDM Ln] [bi->dma ] "
416 "leng ntw timestamp bi->skb\n");
417
418 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
419 struct igb_tx_buffer *buffer_info;
420 tx_desc = IGB_TX_DESC(tx_ring, i);
421 buffer_info = &tx_ring->tx_buffer_info[i];
422 u0 = (struct my_u0 *)tx_desc;
423 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
424 " %04X %p %016llX %p", i,
425 le64_to_cpu(u0->a),
426 le64_to_cpu(u0->b),
427 (u64)buffer_info->dma,
428 buffer_info->length,
429 buffer_info->next_to_watch,
430 (u64)buffer_info->time_stamp,
431 buffer_info->skb);
432 if (i == tx_ring->next_to_use &&
433 i == tx_ring->next_to_clean)
434 printk(KERN_CONT " NTC/U\n");
435 else if (i == tx_ring->next_to_use)
436 printk(KERN_CONT " NTU\n");
437 else if (i == tx_ring->next_to_clean)
438 printk(KERN_CONT " NTC\n");
439 else
440 printk(KERN_CONT "\n");
441
442 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
443 print_hex_dump(KERN_INFO, "",
444 DUMP_PREFIX_ADDRESS,
445 16, 1, phys_to_virt(buffer_info->dma),
446 buffer_info->length, true);
447 }
448 }
449
450 /* Print RX Rings Summary */
451 rx_ring_summary:
452 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
453 printk(KERN_INFO "Queue [NTU] [NTC]\n");
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
456 printk(KERN_INFO " %5d %5X %5X\n", n,
457 rx_ring->next_to_use, rx_ring->next_to_clean);
458 }
459
460 /* Print RX Rings */
461 if (!netif_msg_rx_status(adapter))
462 goto exit;
463
464 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
465
466 /* Advanced Receive Descriptor (Read) Format
467 * 63 1 0
468 * +-----------------------------------------------------+
469 * 0 | Packet Buffer Address [63:1] |A0/NSE|
470 * +----------------------------------------------+------+
471 * 8 | Header Buffer Address [63:1] | DD |
472 * +-----------------------------------------------------+
473 *
474 *
475 * Advanced Receive Descriptor (Write-Back) Format
476 *
477 * 63 48 47 32 31 30 21 20 17 16 4 3 0
478 * +------------------------------------------------------+
479 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
480 * | Checksum Ident | | | | Type | Type |
481 * +------------------------------------------------------+
482 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
483 * +------------------------------------------------------+
484 * 63 48 47 32 31 20 19 0
485 */
486
487 for (n = 0; n < adapter->num_rx_queues; n++) {
488 rx_ring = adapter->rx_ring[n];
489 printk(KERN_INFO "------------------------------------\n");
490 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
491 printk(KERN_INFO "------------------------------------\n");
492 printk(KERN_INFO "R [desc] [ PktBuf A0] "
493 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
494 "<-- Adv Rx Read format\n");
495 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
496 "[vl er S cks ln] ---------------- [bi->skb] "
497 "<-- Adv Rx Write-Back format\n");
498
499 for (i = 0; i < rx_ring->count; i++) {
500 struct igb_rx_buffer *buffer_info;
501 buffer_info = &rx_ring->rx_buffer_info[i];
502 rx_desc = IGB_RX_DESC(rx_ring, i);
503 u0 = (struct my_u0 *)rx_desc;
504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
505 if (staterr & E1000_RXD_STAT_DD) {
506 /* Descriptor Done */
507 printk(KERN_INFO "RWB[0x%03X] %016llX "
508 "%016llX ---------------- %p", i,
509 le64_to_cpu(u0->a),
510 le64_to_cpu(u0->b),
511 buffer_info->skb);
512 } else {
513 printk(KERN_INFO "R [0x%03X] %016llX "
514 "%016llX %016llX %p", i,
515 le64_to_cpu(u0->a),
516 le64_to_cpu(u0->b),
517 (u64)buffer_info->dma,
518 buffer_info->skb);
519
520 if (netif_msg_pktdata(adapter)) {
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS,
523 16, 1,
524 phys_to_virt(buffer_info->dma),
525 IGB_RX_HDR_LEN, true);
526 print_hex_dump(KERN_INFO, "",
527 DUMP_PREFIX_ADDRESS,
528 16, 1,
529 phys_to_virt(
530 buffer_info->page_dma +
531 buffer_info->page_offset),
532 PAGE_SIZE/2, true);
533 }
534 }
535
536 if (i == rx_ring->next_to_use)
537 printk(KERN_CONT " NTU\n");
538 else if (i == rx_ring->next_to_clean)
539 printk(KERN_CONT " NTC\n");
540 else
541 printk(KERN_CONT "\n");
542
543 }
544 }
545
546 exit:
547 return;
548 }
549
550
551 /**
552 * igb_read_clock - read raw cycle counter (to be used by time counter)
553 */
554 static cycle_t igb_read_clock(const struct cyclecounter *tc)
555 {
556 struct igb_adapter *adapter =
557 container_of(tc, struct igb_adapter, cycles);
558 struct e1000_hw *hw = &adapter->hw;
559 u64 stamp = 0;
560 int shift = 0;
561
562 /*
563 * The timestamp latches on lowest register read. For the 82580
564 * the lowest register is SYSTIMR instead of SYSTIML. However we never
565 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
566 */
567 if (hw->mac.type == e1000_82580) {
568 stamp = rd32(E1000_SYSTIMR) >> 8;
569 shift = IGB_82580_TSYNC_SHIFT;
570 }
571
572 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
573 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
574 return stamp;
575 }
576
577 /**
578 * igb_get_hw_dev - return device
579 * used by hardware layer to print debugging information
580 **/
581 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
582 {
583 struct igb_adapter *adapter = hw->back;
584 return adapter->netdev;
585 }
586
587 /**
588 * igb_init_module - Driver Registration Routine
589 *
590 * igb_init_module is the first routine called when the driver is
591 * loaded. All it does is register with the PCI subsystem.
592 **/
593 static int __init igb_init_module(void)
594 {
595 int ret;
596 printk(KERN_INFO "%s - version %s\n",
597 igb_driver_string, igb_driver_version);
598
599 printk(KERN_INFO "%s\n", igb_copyright);
600
601 #ifdef CONFIG_IGB_DCA
602 dca_register_notify(&dca_notifier);
603 #endif
604 ret = pci_register_driver(&igb_driver);
605 return ret;
606 }
607
608 module_init(igb_init_module);
609
610 /**
611 * igb_exit_module - Driver Exit Cleanup Routine
612 *
613 * igb_exit_module is called just before the driver is removed
614 * from memory.
615 **/
616 static void __exit igb_exit_module(void)
617 {
618 #ifdef CONFIG_IGB_DCA
619 dca_unregister_notify(&dca_notifier);
620 #endif
621 pci_unregister_driver(&igb_driver);
622 }
623
624 module_exit(igb_exit_module);
625
626 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
627 /**
628 * igb_cache_ring_register - Descriptor ring to register mapping
629 * @adapter: board private structure to initialize
630 *
631 * Once we know the feature-set enabled for the device, we'll cache
632 * the register offset the descriptor ring is assigned to.
633 **/
634 static void igb_cache_ring_register(struct igb_adapter *adapter)
635 {
636 int i = 0, j = 0;
637 u32 rbase_offset = adapter->vfs_allocated_count;
638
639 switch (adapter->hw.mac.type) {
640 case e1000_82576:
641 /* The queues are allocated for virtualization such that VF 0
642 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
643 * In order to avoid collision we start at the first free queue
644 * and continue consuming queues in the same sequence
645 */
646 if (adapter->vfs_allocated_count) {
647 for (; i < adapter->rss_queues; i++)
648 adapter->rx_ring[i]->reg_idx = rbase_offset +
649 Q_IDX_82576(i);
650 }
651 case e1000_82575:
652 case e1000_82580:
653 case e1000_i350:
654 default:
655 for (; i < adapter->num_rx_queues; i++)
656 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
657 for (; j < adapter->num_tx_queues; j++)
658 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
659 break;
660 }
661 }
662
663 static void igb_free_queues(struct igb_adapter *adapter)
664 {
665 int i;
666
667 for (i = 0; i < adapter->num_tx_queues; i++) {
668 kfree(adapter->tx_ring[i]);
669 adapter->tx_ring[i] = NULL;
670 }
671 for (i = 0; i < adapter->num_rx_queues; i++) {
672 kfree(adapter->rx_ring[i]);
673 adapter->rx_ring[i] = NULL;
674 }
675 adapter->num_rx_queues = 0;
676 adapter->num_tx_queues = 0;
677 }
678
679 /**
680 * igb_alloc_queues - Allocate memory for all rings
681 * @adapter: board private structure to initialize
682 *
683 * We allocate one ring per queue at run-time since we don't know the
684 * number of queues at compile-time.
685 **/
686 static int igb_alloc_queues(struct igb_adapter *adapter)
687 {
688 struct igb_ring *ring;
689 int i;
690
691 for (i = 0; i < adapter->num_tx_queues; i++) {
692 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
693 if (!ring)
694 goto err;
695 ring->count = adapter->tx_ring_count;
696 ring->queue_index = i;
697 ring->dev = &adapter->pdev->dev;
698 ring->netdev = adapter->netdev;
699 /* For 82575, context index must be unique per ring. */
700 if (adapter->hw.mac.type == e1000_82575)
701 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
702 adapter->tx_ring[i] = ring;
703 }
704
705 for (i = 0; i < adapter->num_rx_queues; i++) {
706 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
707 if (!ring)
708 goto err;
709 ring->count = adapter->rx_ring_count;
710 ring->queue_index = i;
711 ring->dev = &adapter->pdev->dev;
712 ring->netdev = adapter->netdev;
713 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
714 /* set flag indicating ring supports SCTP checksum offload */
715 if (adapter->hw.mac.type >= e1000_82576)
716 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
717 adapter->rx_ring[i] = ring;
718 }
719
720 igb_cache_ring_register(adapter);
721
722 return 0;
723
724 err:
725 igb_free_queues(adapter);
726
727 return -ENOMEM;
728 }
729
730 #define IGB_N0_QUEUE -1
731 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
732 {
733 u32 msixbm = 0;
734 struct igb_adapter *adapter = q_vector->adapter;
735 struct e1000_hw *hw = &adapter->hw;
736 u32 ivar, index;
737 int rx_queue = IGB_N0_QUEUE;
738 int tx_queue = IGB_N0_QUEUE;
739
740 if (q_vector->rx_ring)
741 rx_queue = q_vector->rx_ring->reg_idx;
742 if (q_vector->tx_ring)
743 tx_queue = q_vector->tx_ring->reg_idx;
744
745 switch (hw->mac.type) {
746 case e1000_82575:
747 /* The 82575 assigns vectors using a bitmask, which matches the
748 bitmask for the EICR/EIMS/EIMC registers. To assign one
749 or more queues to a vector, we write the appropriate bits
750 into the MSIXBM register for that vector. */
751 if (rx_queue > IGB_N0_QUEUE)
752 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
753 if (tx_queue > IGB_N0_QUEUE)
754 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
755 if (!adapter->msix_entries && msix_vector == 0)
756 msixbm |= E1000_EIMS_OTHER;
757 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
758 q_vector->eims_value = msixbm;
759 break;
760 case e1000_82576:
761 /* 82576 uses a table-based method for assigning vectors.
762 Each queue has a single entry in the table to which we write
763 a vector number along with a "valid" bit. Sadly, the layout
764 of the table is somewhat counterintuitive. */
765 if (rx_queue > IGB_N0_QUEUE) {
766 index = (rx_queue & 0x7);
767 ivar = array_rd32(E1000_IVAR0, index);
768 if (rx_queue < 8) {
769 /* vector goes into low byte of register */
770 ivar = ivar & 0xFFFFFF00;
771 ivar |= msix_vector | E1000_IVAR_VALID;
772 } else {
773 /* vector goes into third byte of register */
774 ivar = ivar & 0xFF00FFFF;
775 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
776 }
777 array_wr32(E1000_IVAR0, index, ivar);
778 }
779 if (tx_queue > IGB_N0_QUEUE) {
780 index = (tx_queue & 0x7);
781 ivar = array_rd32(E1000_IVAR0, index);
782 if (tx_queue < 8) {
783 /* vector goes into second byte of register */
784 ivar = ivar & 0xFFFF00FF;
785 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
786 } else {
787 /* vector goes into high byte of register */
788 ivar = ivar & 0x00FFFFFF;
789 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
790 }
791 array_wr32(E1000_IVAR0, index, ivar);
792 }
793 q_vector->eims_value = 1 << msix_vector;
794 break;
795 case e1000_82580:
796 case e1000_i350:
797 /* 82580 uses the same table-based approach as 82576 but has fewer
798 entries as a result we carry over for queues greater than 4. */
799 if (rx_queue > IGB_N0_QUEUE) {
800 index = (rx_queue >> 1);
801 ivar = array_rd32(E1000_IVAR0, index);
802 if (rx_queue & 0x1) {
803 /* vector goes into third byte of register */
804 ivar = ivar & 0xFF00FFFF;
805 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
806 } else {
807 /* vector goes into low byte of register */
808 ivar = ivar & 0xFFFFFF00;
809 ivar |= msix_vector | E1000_IVAR_VALID;
810 }
811 array_wr32(E1000_IVAR0, index, ivar);
812 }
813 if (tx_queue > IGB_N0_QUEUE) {
814 index = (tx_queue >> 1);
815 ivar = array_rd32(E1000_IVAR0, index);
816 if (tx_queue & 0x1) {
817 /* vector goes into high byte of register */
818 ivar = ivar & 0x00FFFFFF;
819 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
820 } else {
821 /* vector goes into second byte of register */
822 ivar = ivar & 0xFFFF00FF;
823 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
824 }
825 array_wr32(E1000_IVAR0, index, ivar);
826 }
827 q_vector->eims_value = 1 << msix_vector;
828 break;
829 default:
830 BUG();
831 break;
832 }
833
834 /* add q_vector eims value to global eims_enable_mask */
835 adapter->eims_enable_mask |= q_vector->eims_value;
836
837 /* configure q_vector to set itr on first interrupt */
838 q_vector->set_itr = 1;
839 }
840
841 /**
842 * igb_configure_msix - Configure MSI-X hardware
843 *
844 * igb_configure_msix sets up the hardware to properly
845 * generate MSI-X interrupts.
846 **/
847 static void igb_configure_msix(struct igb_adapter *adapter)
848 {
849 u32 tmp;
850 int i, vector = 0;
851 struct e1000_hw *hw = &adapter->hw;
852
853 adapter->eims_enable_mask = 0;
854
855 /* set vector for other causes, i.e. link changes */
856 switch (hw->mac.type) {
857 case e1000_82575:
858 tmp = rd32(E1000_CTRL_EXT);
859 /* enable MSI-X PBA support*/
860 tmp |= E1000_CTRL_EXT_PBA_CLR;
861
862 /* Auto-Mask interrupts upon ICR read. */
863 tmp |= E1000_CTRL_EXT_EIAME;
864 tmp |= E1000_CTRL_EXT_IRCA;
865
866 wr32(E1000_CTRL_EXT, tmp);
867
868 /* enable msix_other interrupt */
869 array_wr32(E1000_MSIXBM(0), vector++,
870 E1000_EIMS_OTHER);
871 adapter->eims_other = E1000_EIMS_OTHER;
872
873 break;
874
875 case e1000_82576:
876 case e1000_82580:
877 case e1000_i350:
878 /* Turn on MSI-X capability first, or our settings
879 * won't stick. And it will take days to debug. */
880 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
881 E1000_GPIE_PBA | E1000_GPIE_EIAME |
882 E1000_GPIE_NSICR);
883
884 /* enable msix_other interrupt */
885 adapter->eims_other = 1 << vector;
886 tmp = (vector++ | E1000_IVAR_VALID) << 8;
887
888 wr32(E1000_IVAR_MISC, tmp);
889 break;
890 default:
891 /* do nothing, since nothing else supports MSI-X */
892 break;
893 } /* switch (hw->mac.type) */
894
895 adapter->eims_enable_mask |= adapter->eims_other;
896
897 for (i = 0; i < adapter->num_q_vectors; i++)
898 igb_assign_vector(adapter->q_vector[i], vector++);
899
900 wrfl();
901 }
902
903 /**
904 * igb_request_msix - Initialize MSI-X interrupts
905 *
906 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
907 * kernel.
908 **/
909 static int igb_request_msix(struct igb_adapter *adapter)
910 {
911 struct net_device *netdev = adapter->netdev;
912 struct e1000_hw *hw = &adapter->hw;
913 int i, err = 0, vector = 0;
914
915 err = request_irq(adapter->msix_entries[vector].vector,
916 igb_msix_other, 0, netdev->name, adapter);
917 if (err)
918 goto out;
919 vector++;
920
921 for (i = 0; i < adapter->num_q_vectors; i++) {
922 struct igb_q_vector *q_vector = adapter->q_vector[i];
923
924 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
925
926 if (q_vector->rx_ring && q_vector->tx_ring)
927 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
928 q_vector->rx_ring->queue_index);
929 else if (q_vector->tx_ring)
930 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
931 q_vector->tx_ring->queue_index);
932 else if (q_vector->rx_ring)
933 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
934 q_vector->rx_ring->queue_index);
935 else
936 sprintf(q_vector->name, "%s-unused", netdev->name);
937
938 err = request_irq(adapter->msix_entries[vector].vector,
939 igb_msix_ring, 0, q_vector->name,
940 q_vector);
941 if (err)
942 goto out;
943 vector++;
944 }
945
946 igb_configure_msix(adapter);
947 return 0;
948 out:
949 return err;
950 }
951
952 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
953 {
954 if (adapter->msix_entries) {
955 pci_disable_msix(adapter->pdev);
956 kfree(adapter->msix_entries);
957 adapter->msix_entries = NULL;
958 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
959 pci_disable_msi(adapter->pdev);
960 }
961 }
962
963 /**
964 * igb_free_q_vectors - Free memory allocated for interrupt vectors
965 * @adapter: board private structure to initialize
966 *
967 * This function frees the memory allocated to the q_vectors. In addition if
968 * NAPI is enabled it will delete any references to the NAPI struct prior
969 * to freeing the q_vector.
970 **/
971 static void igb_free_q_vectors(struct igb_adapter *adapter)
972 {
973 int v_idx;
974
975 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
976 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
977 adapter->q_vector[v_idx] = NULL;
978 if (!q_vector)
979 continue;
980 netif_napi_del(&q_vector->napi);
981 kfree(q_vector);
982 }
983 adapter->num_q_vectors = 0;
984 }
985
986 /**
987 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
988 *
989 * This function resets the device so that it has 0 rx queues, tx queues, and
990 * MSI-X interrupts allocated.
991 */
992 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
993 {
994 igb_free_queues(adapter);
995 igb_free_q_vectors(adapter);
996 igb_reset_interrupt_capability(adapter);
997 }
998
999 /**
1000 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1001 *
1002 * Attempt to configure interrupts using the best available
1003 * capabilities of the hardware and kernel.
1004 **/
1005 static int igb_set_interrupt_capability(struct igb_adapter *adapter)
1006 {
1007 int err;
1008 int numvecs, i;
1009
1010 /* Number of supported queues. */
1011 adapter->num_rx_queues = adapter->rss_queues;
1012 if (adapter->vfs_allocated_count)
1013 adapter->num_tx_queues = 1;
1014 else
1015 adapter->num_tx_queues = adapter->rss_queues;
1016
1017 /* start with one vector for every rx queue */
1018 numvecs = adapter->num_rx_queues;
1019
1020 /* if tx handler is separate add 1 for every tx queue */
1021 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1022 numvecs += adapter->num_tx_queues;
1023
1024 /* store the number of vectors reserved for queues */
1025 adapter->num_q_vectors = numvecs;
1026
1027 /* add 1 vector for link status interrupts */
1028 numvecs++;
1029 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1030 GFP_KERNEL);
1031 if (!adapter->msix_entries)
1032 goto msi_only;
1033
1034 for (i = 0; i < numvecs; i++)
1035 adapter->msix_entries[i].entry = i;
1036
1037 err = pci_enable_msix(adapter->pdev,
1038 adapter->msix_entries,
1039 numvecs);
1040 if (err == 0)
1041 goto out;
1042
1043 igb_reset_interrupt_capability(adapter);
1044
1045 /* If we can't do MSI-X, try MSI */
1046 msi_only:
1047 #ifdef CONFIG_PCI_IOV
1048 /* disable SR-IOV for non MSI-X configurations */
1049 if (adapter->vf_data) {
1050 struct e1000_hw *hw = &adapter->hw;
1051 /* disable iov and allow time for transactions to clear */
1052 pci_disable_sriov(adapter->pdev);
1053 msleep(500);
1054
1055 kfree(adapter->vf_data);
1056 adapter->vf_data = NULL;
1057 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1058 wrfl();
1059 msleep(100);
1060 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1061 }
1062 #endif
1063 adapter->vfs_allocated_count = 0;
1064 adapter->rss_queues = 1;
1065 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1066 adapter->num_rx_queues = 1;
1067 adapter->num_tx_queues = 1;
1068 adapter->num_q_vectors = 1;
1069 if (!pci_enable_msi(adapter->pdev))
1070 adapter->flags |= IGB_FLAG_HAS_MSI;
1071 out:
1072 /* Notify the stack of the (possibly) reduced queue counts. */
1073 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
1074 return netif_set_real_num_rx_queues(adapter->netdev,
1075 adapter->num_rx_queues);
1076 }
1077
1078 /**
1079 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1080 * @adapter: board private structure to initialize
1081 *
1082 * We allocate one q_vector per queue interrupt. If allocation fails we
1083 * return -ENOMEM.
1084 **/
1085 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1086 {
1087 struct igb_q_vector *q_vector;
1088 struct e1000_hw *hw = &adapter->hw;
1089 int v_idx;
1090
1091 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1092 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
1093 if (!q_vector)
1094 goto err_out;
1095 q_vector->adapter = adapter;
1096 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1097 q_vector->itr_val = IGB_START_ITR;
1098 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1099 adapter->q_vector[v_idx] = q_vector;
1100 }
1101 return 0;
1102
1103 err_out:
1104 igb_free_q_vectors(adapter);
1105 return -ENOMEM;
1106 }
1107
1108 static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1109 int ring_idx, int v_idx)
1110 {
1111 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1112
1113 q_vector->rx_ring = adapter->rx_ring[ring_idx];
1114 q_vector->rx_ring->q_vector = q_vector;
1115 q_vector->itr_val = adapter->rx_itr_setting;
1116 if (q_vector->itr_val && q_vector->itr_val <= 3)
1117 q_vector->itr_val = IGB_START_ITR;
1118 }
1119
1120 static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1121 int ring_idx, int v_idx)
1122 {
1123 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1124
1125 q_vector->tx_ring = adapter->tx_ring[ring_idx];
1126 q_vector->tx_ring->q_vector = q_vector;
1127 q_vector->itr_val = adapter->tx_itr_setting;
1128 q_vector->tx_work_limit = adapter->tx_work_limit;
1129 if (q_vector->itr_val && q_vector->itr_val <= 3)
1130 q_vector->itr_val = IGB_START_ITR;
1131 }
1132
1133 /**
1134 * igb_map_ring_to_vector - maps allocated queues to vectors
1135 *
1136 * This function maps the recently allocated queues to vectors.
1137 **/
1138 static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1139 {
1140 int i;
1141 int v_idx = 0;
1142
1143 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1144 (adapter->num_q_vectors < adapter->num_tx_queues))
1145 return -ENOMEM;
1146
1147 if (adapter->num_q_vectors >=
1148 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1149 for (i = 0; i < adapter->num_rx_queues; i++)
1150 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1151 for (i = 0; i < adapter->num_tx_queues; i++)
1152 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1153 } else {
1154 for (i = 0; i < adapter->num_rx_queues; i++) {
1155 if (i < adapter->num_tx_queues)
1156 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1157 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1158 }
1159 for (; i < adapter->num_tx_queues; i++)
1160 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1161 }
1162 return 0;
1163 }
1164
1165 /**
1166 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1167 *
1168 * This function initializes the interrupts and allocates all of the queues.
1169 **/
1170 static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1171 {
1172 struct pci_dev *pdev = adapter->pdev;
1173 int err;
1174
1175 err = igb_set_interrupt_capability(adapter);
1176 if (err)
1177 return err;
1178
1179 err = igb_alloc_q_vectors(adapter);
1180 if (err) {
1181 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1182 goto err_alloc_q_vectors;
1183 }
1184
1185 err = igb_alloc_queues(adapter);
1186 if (err) {
1187 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1188 goto err_alloc_queues;
1189 }
1190
1191 err = igb_map_ring_to_vector(adapter);
1192 if (err) {
1193 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1194 goto err_map_queues;
1195 }
1196
1197
1198 return 0;
1199 err_map_queues:
1200 igb_free_queues(adapter);
1201 err_alloc_queues:
1202 igb_free_q_vectors(adapter);
1203 err_alloc_q_vectors:
1204 igb_reset_interrupt_capability(adapter);
1205 return err;
1206 }
1207
1208 /**
1209 * igb_request_irq - initialize interrupts
1210 *
1211 * Attempts to configure interrupts using the best available
1212 * capabilities of the hardware and kernel.
1213 **/
1214 static int igb_request_irq(struct igb_adapter *adapter)
1215 {
1216 struct net_device *netdev = adapter->netdev;
1217 struct pci_dev *pdev = adapter->pdev;
1218 int err = 0;
1219
1220 if (adapter->msix_entries) {
1221 err = igb_request_msix(adapter);
1222 if (!err)
1223 goto request_done;
1224 /* fall back to MSI */
1225 igb_clear_interrupt_scheme(adapter);
1226 if (!pci_enable_msi(adapter->pdev))
1227 adapter->flags |= IGB_FLAG_HAS_MSI;
1228 igb_free_all_tx_resources(adapter);
1229 igb_free_all_rx_resources(adapter);
1230 adapter->num_tx_queues = 1;
1231 adapter->num_rx_queues = 1;
1232 adapter->num_q_vectors = 1;
1233 err = igb_alloc_q_vectors(adapter);
1234 if (err) {
1235 dev_err(&pdev->dev,
1236 "Unable to allocate memory for vectors\n");
1237 goto request_done;
1238 }
1239 err = igb_alloc_queues(adapter);
1240 if (err) {
1241 dev_err(&pdev->dev,
1242 "Unable to allocate memory for queues\n");
1243 igb_free_q_vectors(adapter);
1244 goto request_done;
1245 }
1246 igb_setup_all_tx_resources(adapter);
1247 igb_setup_all_rx_resources(adapter);
1248 } else {
1249 igb_assign_vector(adapter->q_vector[0], 0);
1250 }
1251
1252 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1253 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
1254 netdev->name, adapter);
1255 if (!err)
1256 goto request_done;
1257
1258 /* fall back to legacy interrupts */
1259 igb_reset_interrupt_capability(adapter);
1260 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1261 }
1262
1263 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
1264 netdev->name, adapter);
1265
1266 if (err)
1267 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
1268 err);
1269
1270 request_done:
1271 return err;
1272 }
1273
1274 static void igb_free_irq(struct igb_adapter *adapter)
1275 {
1276 if (adapter->msix_entries) {
1277 int vector = 0, i;
1278
1279 free_irq(adapter->msix_entries[vector++].vector, adapter);
1280
1281 for (i = 0; i < adapter->num_q_vectors; i++) {
1282 struct igb_q_vector *q_vector = adapter->q_vector[i];
1283 free_irq(adapter->msix_entries[vector++].vector,
1284 q_vector);
1285 }
1286 } else {
1287 free_irq(adapter->pdev->irq, adapter);
1288 }
1289 }
1290
1291 /**
1292 * igb_irq_disable - Mask off interrupt generation on the NIC
1293 * @adapter: board private structure
1294 **/
1295 static void igb_irq_disable(struct igb_adapter *adapter)
1296 {
1297 struct e1000_hw *hw = &adapter->hw;
1298
1299 /*
1300 * we need to be careful when disabling interrupts. The VFs are also
1301 * mapped into these registers and so clearing the bits can cause
1302 * issues on the VF drivers so we only need to clear what we set
1303 */
1304 if (adapter->msix_entries) {
1305 u32 regval = rd32(E1000_EIAM);
1306 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1307 wr32(E1000_EIMC, adapter->eims_enable_mask);
1308 regval = rd32(E1000_EIAC);
1309 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1310 }
1311
1312 wr32(E1000_IAM, 0);
1313 wr32(E1000_IMC, ~0);
1314 wrfl();
1315 if (adapter->msix_entries) {
1316 int i;
1317 for (i = 0; i < adapter->num_q_vectors; i++)
1318 synchronize_irq(adapter->msix_entries[i].vector);
1319 } else {
1320 synchronize_irq(adapter->pdev->irq);
1321 }
1322 }
1323
1324 /**
1325 * igb_irq_enable - Enable default interrupt generation settings
1326 * @adapter: board private structure
1327 **/
1328 static void igb_irq_enable(struct igb_adapter *adapter)
1329 {
1330 struct e1000_hw *hw = &adapter->hw;
1331
1332 if (adapter->msix_entries) {
1333 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
1334 u32 regval = rd32(E1000_EIAC);
1335 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1336 regval = rd32(E1000_EIAM);
1337 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1338 wr32(E1000_EIMS, adapter->eims_enable_mask);
1339 if (adapter->vfs_allocated_count) {
1340 wr32(E1000_MBVFIMR, 0xFF);
1341 ims |= E1000_IMS_VMMB;
1342 }
1343 if (adapter->hw.mac.type == e1000_82580)
1344 ims |= E1000_IMS_DRSTA;
1345
1346 wr32(E1000_IMS, ims);
1347 } else {
1348 wr32(E1000_IMS, IMS_ENABLE_MASK |
1349 E1000_IMS_DRSTA);
1350 wr32(E1000_IAM, IMS_ENABLE_MASK |
1351 E1000_IMS_DRSTA);
1352 }
1353 }
1354
1355 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1356 {
1357 struct e1000_hw *hw = &adapter->hw;
1358 u16 vid = adapter->hw.mng_cookie.vlan_id;
1359 u16 old_vid = adapter->mng_vlan_id;
1360
1361 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1362 /* add VID to filter table */
1363 igb_vfta_set(hw, vid, true);
1364 adapter->mng_vlan_id = vid;
1365 } else {
1366 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1367 }
1368
1369 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1370 (vid != old_vid) &&
1371 !test_bit(old_vid, adapter->active_vlans)) {
1372 /* remove VID from filter table */
1373 igb_vfta_set(hw, old_vid, false);
1374 }
1375 }
1376
1377 /**
1378 * igb_release_hw_control - release control of the h/w to f/w
1379 * @adapter: address of board private structure
1380 *
1381 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1382 * For ASF and Pass Through versions of f/w this means that the
1383 * driver is no longer loaded.
1384 *
1385 **/
1386 static void igb_release_hw_control(struct igb_adapter *adapter)
1387 {
1388 struct e1000_hw *hw = &adapter->hw;
1389 u32 ctrl_ext;
1390
1391 /* Let firmware take over control of h/w */
1392 ctrl_ext = rd32(E1000_CTRL_EXT);
1393 wr32(E1000_CTRL_EXT,
1394 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1395 }
1396
1397 /**
1398 * igb_get_hw_control - get control of the h/w from f/w
1399 * @adapter: address of board private structure
1400 *
1401 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1402 * For ASF and Pass Through versions of f/w this means that
1403 * the driver is loaded.
1404 *
1405 **/
1406 static void igb_get_hw_control(struct igb_adapter *adapter)
1407 {
1408 struct e1000_hw *hw = &adapter->hw;
1409 u32 ctrl_ext;
1410
1411 /* Let firmware know the driver has taken over */
1412 ctrl_ext = rd32(E1000_CTRL_EXT);
1413 wr32(E1000_CTRL_EXT,
1414 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1415 }
1416
1417 /**
1418 * igb_configure - configure the hardware for RX and TX
1419 * @adapter: private board structure
1420 **/
1421 static void igb_configure(struct igb_adapter *adapter)
1422 {
1423 struct net_device *netdev = adapter->netdev;
1424 int i;
1425
1426 igb_get_hw_control(adapter);
1427 igb_set_rx_mode(netdev);
1428
1429 igb_restore_vlan(adapter);
1430
1431 igb_setup_tctl(adapter);
1432 igb_setup_mrqc(adapter);
1433 igb_setup_rctl(adapter);
1434
1435 igb_configure_tx(adapter);
1436 igb_configure_rx(adapter);
1437
1438 igb_rx_fifo_flush_82575(&adapter->hw);
1439
1440 /* call igb_desc_unused which always leaves
1441 * at least 1 descriptor unused to make sure
1442 * next_to_use != next_to_clean */
1443 for (i = 0; i < adapter->num_rx_queues; i++) {
1444 struct igb_ring *ring = adapter->rx_ring[i];
1445 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1446 }
1447 }
1448
1449 /**
1450 * igb_power_up_link - Power up the phy/serdes link
1451 * @adapter: address of board private structure
1452 **/
1453 void igb_power_up_link(struct igb_adapter *adapter)
1454 {
1455 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1456 igb_power_up_phy_copper(&adapter->hw);
1457 else
1458 igb_power_up_serdes_link_82575(&adapter->hw);
1459 }
1460
1461 /**
1462 * igb_power_down_link - Power down the phy/serdes link
1463 * @adapter: address of board private structure
1464 */
1465 static void igb_power_down_link(struct igb_adapter *adapter)
1466 {
1467 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1468 igb_power_down_phy_copper_82575(&adapter->hw);
1469 else
1470 igb_shutdown_serdes_link_82575(&adapter->hw);
1471 }
1472
1473 /**
1474 * igb_up - Open the interface and prepare it to handle traffic
1475 * @adapter: board private structure
1476 **/
1477 int igb_up(struct igb_adapter *adapter)
1478 {
1479 struct e1000_hw *hw = &adapter->hw;
1480 int i;
1481
1482 /* hardware has been reset, we need to reload some things */
1483 igb_configure(adapter);
1484
1485 clear_bit(__IGB_DOWN, &adapter->state);
1486
1487 for (i = 0; i < adapter->num_q_vectors; i++) {
1488 struct igb_q_vector *q_vector = adapter->q_vector[i];
1489 napi_enable(&q_vector->napi);
1490 }
1491 if (adapter->msix_entries)
1492 igb_configure_msix(adapter);
1493 else
1494 igb_assign_vector(adapter->q_vector[0], 0);
1495
1496 /* Clear any pending interrupts. */
1497 rd32(E1000_ICR);
1498 igb_irq_enable(adapter);
1499
1500 /* notify VFs that reset has been completed */
1501 if (adapter->vfs_allocated_count) {
1502 u32 reg_data = rd32(E1000_CTRL_EXT);
1503 reg_data |= E1000_CTRL_EXT_PFRSTD;
1504 wr32(E1000_CTRL_EXT, reg_data);
1505 }
1506
1507 netif_tx_start_all_queues(adapter->netdev);
1508
1509 /* start the watchdog. */
1510 hw->mac.get_link_status = 1;
1511 schedule_work(&adapter->watchdog_task);
1512
1513 return 0;
1514 }
1515
1516 void igb_down(struct igb_adapter *adapter)
1517 {
1518 struct net_device *netdev = adapter->netdev;
1519 struct e1000_hw *hw = &adapter->hw;
1520 u32 tctl, rctl;
1521 int i;
1522
1523 /* signal that we're down so the interrupt handler does not
1524 * reschedule our watchdog timer */
1525 set_bit(__IGB_DOWN, &adapter->state);
1526
1527 /* disable receives in the hardware */
1528 rctl = rd32(E1000_RCTL);
1529 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1530 /* flush and sleep below */
1531
1532 netif_tx_stop_all_queues(netdev);
1533
1534 /* disable transmits in the hardware */
1535 tctl = rd32(E1000_TCTL);
1536 tctl &= ~E1000_TCTL_EN;
1537 wr32(E1000_TCTL, tctl);
1538 /* flush both disables and wait for them to finish */
1539 wrfl();
1540 msleep(10);
1541
1542 for (i = 0; i < adapter->num_q_vectors; i++) {
1543 struct igb_q_vector *q_vector = adapter->q_vector[i];
1544 napi_disable(&q_vector->napi);
1545 }
1546
1547 igb_irq_disable(adapter);
1548
1549 del_timer_sync(&adapter->watchdog_timer);
1550 del_timer_sync(&adapter->phy_info_timer);
1551
1552 netif_carrier_off(netdev);
1553
1554 /* record the stats before reset*/
1555 spin_lock(&adapter->stats64_lock);
1556 igb_update_stats(adapter, &adapter->stats64);
1557 spin_unlock(&adapter->stats64_lock);
1558
1559 adapter->link_speed = 0;
1560 adapter->link_duplex = 0;
1561
1562 if (!pci_channel_offline(adapter->pdev))
1563 igb_reset(adapter);
1564 igb_clean_all_tx_rings(adapter);
1565 igb_clean_all_rx_rings(adapter);
1566 #ifdef CONFIG_IGB_DCA
1567
1568 /* since we reset the hardware DCA settings were cleared */
1569 igb_setup_dca(adapter);
1570 #endif
1571 }
1572
1573 void igb_reinit_locked(struct igb_adapter *adapter)
1574 {
1575 WARN_ON(in_interrupt());
1576 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1577 msleep(1);
1578 igb_down(adapter);
1579 igb_up(adapter);
1580 clear_bit(__IGB_RESETTING, &adapter->state);
1581 }
1582
1583 void igb_reset(struct igb_adapter *adapter)
1584 {
1585 struct pci_dev *pdev = adapter->pdev;
1586 struct e1000_hw *hw = &adapter->hw;
1587 struct e1000_mac_info *mac = &hw->mac;
1588 struct e1000_fc_info *fc = &hw->fc;
1589 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1590 u16 hwm;
1591
1592 /* Repartition Pba for greater than 9k mtu
1593 * To take effect CTRL.RST is required.
1594 */
1595 switch (mac->type) {
1596 case e1000_i350:
1597 case e1000_82580:
1598 pba = rd32(E1000_RXPBS);
1599 pba = igb_rxpbs_adjust_82580(pba);
1600 break;
1601 case e1000_82576:
1602 pba = rd32(E1000_RXPBS);
1603 pba &= E1000_RXPBS_SIZE_MASK_82576;
1604 break;
1605 case e1000_82575:
1606 default:
1607 pba = E1000_PBA_34K;
1608 break;
1609 }
1610
1611 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1612 (mac->type < e1000_82576)) {
1613 /* adjust PBA for jumbo frames */
1614 wr32(E1000_PBA, pba);
1615
1616 /* To maintain wire speed transmits, the Tx FIFO should be
1617 * large enough to accommodate two full transmit packets,
1618 * rounded up to the next 1KB and expressed in KB. Likewise,
1619 * the Rx FIFO should be large enough to accommodate at least
1620 * one full receive packet and is similarly rounded up and
1621 * expressed in KB. */
1622 pba = rd32(E1000_PBA);
1623 /* upper 16 bits has Tx packet buffer allocation size in KB */
1624 tx_space = pba >> 16;
1625 /* lower 16 bits has Rx packet buffer allocation size in KB */
1626 pba &= 0xffff;
1627 /* the tx fifo also stores 16 bytes of information about the tx
1628 * but don't include ethernet FCS because hardware appends it */
1629 min_tx_space = (adapter->max_frame_size +
1630 sizeof(union e1000_adv_tx_desc) -
1631 ETH_FCS_LEN) * 2;
1632 min_tx_space = ALIGN(min_tx_space, 1024);
1633 min_tx_space >>= 10;
1634 /* software strips receive CRC, so leave room for it */
1635 min_rx_space = adapter->max_frame_size;
1636 min_rx_space = ALIGN(min_rx_space, 1024);
1637 min_rx_space >>= 10;
1638
1639 /* If current Tx allocation is less than the min Tx FIFO size,
1640 * and the min Tx FIFO size is less than the current Rx FIFO
1641 * allocation, take space away from current Rx allocation */
1642 if (tx_space < min_tx_space &&
1643 ((min_tx_space - tx_space) < pba)) {
1644 pba = pba - (min_tx_space - tx_space);
1645
1646 /* if short on rx space, rx wins and must trump tx
1647 * adjustment */
1648 if (pba < min_rx_space)
1649 pba = min_rx_space;
1650 }
1651 wr32(E1000_PBA, pba);
1652 }
1653
1654 /* flow control settings */
1655 /* The high water mark must be low enough to fit one full frame
1656 * (or the size used for early receive) above it in the Rx FIFO.
1657 * Set it to the lower of:
1658 * - 90% of the Rx FIFO size, or
1659 * - the full Rx FIFO size minus one full frame */
1660 hwm = min(((pba << 10) * 9 / 10),
1661 ((pba << 10) - 2 * adapter->max_frame_size));
1662
1663 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1664 fc->low_water = fc->high_water - 16;
1665 fc->pause_time = 0xFFFF;
1666 fc->send_xon = 1;
1667 fc->current_mode = fc->requested_mode;
1668
1669 /* disable receive for all VFs and wait one second */
1670 if (adapter->vfs_allocated_count) {
1671 int i;
1672 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1673 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1674
1675 /* ping all the active vfs to let them know we are going down */
1676 igb_ping_all_vfs(adapter);
1677
1678 /* disable transmits and receives */
1679 wr32(E1000_VFRE, 0);
1680 wr32(E1000_VFTE, 0);
1681 }
1682
1683 /* Allow time for pending master requests to run */
1684 hw->mac.ops.reset_hw(hw);
1685 wr32(E1000_WUC, 0);
1686
1687 if (hw->mac.ops.init_hw(hw))
1688 dev_err(&pdev->dev, "Hardware Error\n");
1689 if (hw->mac.type > e1000_82580) {
1690 if (adapter->flags & IGB_FLAG_DMAC) {
1691 u32 reg;
1692
1693 /*
1694 * DMA Coalescing high water mark needs to be higher
1695 * than * the * Rx threshold. The Rx threshold is
1696 * currently * pba - 6, so we * should use a high water
1697 * mark of pba * - 4. */
1698 hwm = (pba - 4) << 10;
1699
1700 reg = (((pba-6) << E1000_DMACR_DMACTHR_SHIFT)
1701 & E1000_DMACR_DMACTHR_MASK);
1702
1703 /* transition to L0x or L1 if available..*/
1704 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1705
1706 /* watchdog timer= +-1000 usec in 32usec intervals */
1707 reg |= (1000 >> 5);
1708 wr32(E1000_DMACR, reg);
1709
1710 /* no lower threshold to disable coalescing(smart fifb)
1711 * -UTRESH=0*/
1712 wr32(E1000_DMCRTRH, 0);
1713
1714 /* set hwm to PBA - 2 * max frame size */
1715 wr32(E1000_FCRTC, hwm);
1716
1717 /*
1718 * This sets the time to wait before requesting tran-
1719 * sition to * low power state to number of usecs needed
1720 * to receive 1 512 * byte frame at gigabit line rate
1721 */
1722 reg = rd32(E1000_DMCTLX);
1723 reg |= IGB_DMCTLX_DCFLUSH_DIS;
1724
1725 /* Delay 255 usec before entering Lx state. */
1726 reg |= 0xFF;
1727 wr32(E1000_DMCTLX, reg);
1728
1729 /* free space in Tx packet buffer to wake from DMAC */
1730 wr32(E1000_DMCTXTH,
1731 (IGB_MIN_TXPBSIZE -
1732 (IGB_TX_BUF_4096 + adapter->max_frame_size))
1733 >> 6);
1734
1735 /* make low power state decision controlled by DMAC */
1736 reg = rd32(E1000_PCIEMISC);
1737 reg |= E1000_PCIEMISC_LX_DECISION;
1738 wr32(E1000_PCIEMISC, reg);
1739 } /* end if IGB_FLAG_DMAC set */
1740 }
1741 if (hw->mac.type == e1000_82580) {
1742 u32 reg = rd32(E1000_PCIEMISC);
1743 wr32(E1000_PCIEMISC,
1744 reg & ~E1000_PCIEMISC_LX_DECISION);
1745 }
1746 if (!netif_running(adapter->netdev))
1747 igb_power_down_link(adapter);
1748
1749 igb_update_mng_vlan(adapter);
1750
1751 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1752 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1753
1754 igb_get_phy_info(hw);
1755 }
1756
1757 static u32 igb_fix_features(struct net_device *netdev, u32 features)
1758 {
1759 /*
1760 * Since there is no support for separate rx/tx vlan accel
1761 * enable/disable make sure tx flag is always in same state as rx.
1762 */
1763 if (features & NETIF_F_HW_VLAN_RX)
1764 features |= NETIF_F_HW_VLAN_TX;
1765 else
1766 features &= ~NETIF_F_HW_VLAN_TX;
1767
1768 return features;
1769 }
1770
1771 static int igb_set_features(struct net_device *netdev, u32 features)
1772 {
1773 struct igb_adapter *adapter = netdev_priv(netdev);
1774 int i;
1775 u32 changed = netdev->features ^ features;
1776
1777 for (i = 0; i < adapter->num_rx_queues; i++) {
1778 if (features & NETIF_F_RXCSUM)
1779 adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM;
1780 else
1781 adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM;
1782 }
1783
1784 if (changed & NETIF_F_HW_VLAN_RX)
1785 igb_vlan_mode(netdev, features);
1786
1787 return 0;
1788 }
1789
1790 static const struct net_device_ops igb_netdev_ops = {
1791 .ndo_open = igb_open,
1792 .ndo_stop = igb_close,
1793 .ndo_start_xmit = igb_xmit_frame,
1794 .ndo_get_stats64 = igb_get_stats64,
1795 .ndo_set_rx_mode = igb_set_rx_mode,
1796 .ndo_set_mac_address = igb_set_mac,
1797 .ndo_change_mtu = igb_change_mtu,
1798 .ndo_do_ioctl = igb_ioctl,
1799 .ndo_tx_timeout = igb_tx_timeout,
1800 .ndo_validate_addr = eth_validate_addr,
1801 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1802 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1803 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1804 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1805 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1806 .ndo_get_vf_config = igb_ndo_get_vf_config,
1807 #ifdef CONFIG_NET_POLL_CONTROLLER
1808 .ndo_poll_controller = igb_netpoll,
1809 #endif
1810 .ndo_fix_features = igb_fix_features,
1811 .ndo_set_features = igb_set_features,
1812 };
1813
1814 /**
1815 * igb_probe - Device Initialization Routine
1816 * @pdev: PCI device information struct
1817 * @ent: entry in igb_pci_tbl
1818 *
1819 * Returns 0 on success, negative on failure
1820 *
1821 * igb_probe initializes an adapter identified by a pci_dev structure.
1822 * The OS initialization, configuring of the adapter private structure,
1823 * and a hardware reset occur.
1824 **/
1825 static int __devinit igb_probe(struct pci_dev *pdev,
1826 const struct pci_device_id *ent)
1827 {
1828 struct net_device *netdev;
1829 struct igb_adapter *adapter;
1830 struct e1000_hw *hw;
1831 u16 eeprom_data = 0;
1832 s32 ret_val;
1833 static int global_quad_port_a; /* global quad port a indication */
1834 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1835 unsigned long mmio_start, mmio_len;
1836 int err, pci_using_dac;
1837 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1838 u8 part_str[E1000_PBANUM_LENGTH];
1839
1840 /* Catch broken hardware that put the wrong VF device ID in
1841 * the PCIe SR-IOV capability.
1842 */
1843 if (pdev->is_virtfn) {
1844 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1845 pci_name(pdev), pdev->vendor, pdev->device);
1846 return -EINVAL;
1847 }
1848
1849 err = pci_enable_device_mem(pdev);
1850 if (err)
1851 return err;
1852
1853 pci_using_dac = 0;
1854 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1855 if (!err) {
1856 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1857 if (!err)
1858 pci_using_dac = 1;
1859 } else {
1860 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1861 if (err) {
1862 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1863 if (err) {
1864 dev_err(&pdev->dev, "No usable DMA "
1865 "configuration, aborting\n");
1866 goto err_dma;
1867 }
1868 }
1869 }
1870
1871 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1872 IORESOURCE_MEM),
1873 igb_driver_name);
1874 if (err)
1875 goto err_pci_reg;
1876
1877 pci_enable_pcie_error_reporting(pdev);
1878
1879 pci_set_master(pdev);
1880 pci_save_state(pdev);
1881
1882 err = -ENOMEM;
1883 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1884 IGB_MAX_TX_QUEUES);
1885 if (!netdev)
1886 goto err_alloc_etherdev;
1887
1888 SET_NETDEV_DEV(netdev, &pdev->dev);
1889
1890 pci_set_drvdata(pdev, netdev);
1891 adapter = netdev_priv(netdev);
1892 adapter->netdev = netdev;
1893 adapter->pdev = pdev;
1894 hw = &adapter->hw;
1895 hw->back = adapter;
1896 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1897
1898 mmio_start = pci_resource_start(pdev, 0);
1899 mmio_len = pci_resource_len(pdev, 0);
1900
1901 err = -EIO;
1902 hw->hw_addr = ioremap(mmio_start, mmio_len);
1903 if (!hw->hw_addr)
1904 goto err_ioremap;
1905
1906 netdev->netdev_ops = &igb_netdev_ops;
1907 igb_set_ethtool_ops(netdev);
1908 netdev->watchdog_timeo = 5 * HZ;
1909
1910 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1911
1912 netdev->mem_start = mmio_start;
1913 netdev->mem_end = mmio_start + mmio_len;
1914
1915 /* PCI config space info */
1916 hw->vendor_id = pdev->vendor;
1917 hw->device_id = pdev->device;
1918 hw->revision_id = pdev->revision;
1919 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1920 hw->subsystem_device_id = pdev->subsystem_device;
1921
1922 /* Copy the default MAC, PHY and NVM function pointers */
1923 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1924 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1925 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1926 /* Initialize skew-specific constants */
1927 err = ei->get_invariants(hw);
1928 if (err)
1929 goto err_sw_init;
1930
1931 /* setup the private structure */
1932 err = igb_sw_init(adapter);
1933 if (err)
1934 goto err_sw_init;
1935
1936 igb_get_bus_info_pcie(hw);
1937
1938 hw->phy.autoneg_wait_to_complete = false;
1939
1940 /* Copper options */
1941 if (hw->phy.media_type == e1000_media_type_copper) {
1942 hw->phy.mdix = AUTO_ALL_MODES;
1943 hw->phy.disable_polarity_correction = false;
1944 hw->phy.ms_type = e1000_ms_hw_default;
1945 }
1946
1947 if (igb_check_reset_block(hw))
1948 dev_info(&pdev->dev,
1949 "PHY reset is blocked due to SOL/IDER session.\n");
1950
1951 netdev->hw_features = NETIF_F_SG |
1952 NETIF_F_IP_CSUM |
1953 NETIF_F_IPV6_CSUM |
1954 NETIF_F_TSO |
1955 NETIF_F_TSO6 |
1956 NETIF_F_RXCSUM |
1957 NETIF_F_HW_VLAN_RX;
1958
1959 netdev->features = netdev->hw_features |
1960 NETIF_F_HW_VLAN_TX |
1961 NETIF_F_HW_VLAN_FILTER;
1962
1963 netdev->vlan_features |= NETIF_F_TSO;
1964 netdev->vlan_features |= NETIF_F_TSO6;
1965 netdev->vlan_features |= NETIF_F_IP_CSUM;
1966 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1967 netdev->vlan_features |= NETIF_F_SG;
1968
1969 if (pci_using_dac) {
1970 netdev->features |= NETIF_F_HIGHDMA;
1971 netdev->vlan_features |= NETIF_F_HIGHDMA;
1972 }
1973
1974 if (hw->mac.type >= e1000_82576) {
1975 netdev->hw_features |= NETIF_F_SCTP_CSUM;
1976 netdev->features |= NETIF_F_SCTP_CSUM;
1977 }
1978
1979 netdev->priv_flags |= IFF_UNICAST_FLT;
1980
1981 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
1982
1983 /* before reading the NVM, reset the controller to put the device in a
1984 * known good starting state */
1985 hw->mac.ops.reset_hw(hw);
1986
1987 /* make sure the NVM is good */
1988 if (hw->nvm.ops.validate(hw) < 0) {
1989 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1990 err = -EIO;
1991 goto err_eeprom;
1992 }
1993
1994 /* copy the MAC address out of the NVM */
1995 if (hw->mac.ops.read_mac_addr(hw))
1996 dev_err(&pdev->dev, "NVM Read Error\n");
1997
1998 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1999 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2000
2001 if (!is_valid_ether_addr(netdev->perm_addr)) {
2002 dev_err(&pdev->dev, "Invalid MAC Address\n");
2003 err = -EIO;
2004 goto err_eeprom;
2005 }
2006
2007 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2008 (unsigned long) adapter);
2009 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2010 (unsigned long) adapter);
2011
2012 INIT_WORK(&adapter->reset_task, igb_reset_task);
2013 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2014
2015 /* Initialize link properties that are user-changeable */
2016 adapter->fc_autoneg = true;
2017 hw->mac.autoneg = true;
2018 hw->phy.autoneg_advertised = 0x2f;
2019
2020 hw->fc.requested_mode = e1000_fc_default;
2021 hw->fc.current_mode = e1000_fc_default;
2022
2023 igb_validate_mdi_setting(hw);
2024
2025 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
2026 * enable the ACPI Magic Packet filter
2027 */
2028
2029 if (hw->bus.func == 0)
2030 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
2031 else if (hw->mac.type >= e1000_82580)
2032 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2033 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2034 &eeprom_data);
2035 else if (hw->bus.func == 1)
2036 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2037
2038 if (eeprom_data & eeprom_apme_mask)
2039 adapter->eeprom_wol |= E1000_WUFC_MAG;
2040
2041 /* now that we have the eeprom settings, apply the special cases where
2042 * the eeprom may be wrong or the board simply won't support wake on
2043 * lan on a particular port */
2044 switch (pdev->device) {
2045 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2046 adapter->eeprom_wol = 0;
2047 break;
2048 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2049 case E1000_DEV_ID_82576_FIBER:
2050 case E1000_DEV_ID_82576_SERDES:
2051 /* Wake events only supported on port A for dual fiber
2052 * regardless of eeprom setting */
2053 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2054 adapter->eeprom_wol = 0;
2055 break;
2056 case E1000_DEV_ID_82576_QUAD_COPPER:
2057 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2058 /* if quad port adapter, disable WoL on all but port A */
2059 if (global_quad_port_a != 0)
2060 adapter->eeprom_wol = 0;
2061 else
2062 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2063 /* Reset for multiple quad port adapters */
2064 if (++global_quad_port_a == 4)
2065 global_quad_port_a = 0;
2066 break;
2067 }
2068
2069 /* initialize the wol settings based on the eeprom settings */
2070 adapter->wol = adapter->eeprom_wol;
2071 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2072
2073 /* reset the hardware with the new settings */
2074 igb_reset(adapter);
2075
2076 /* let the f/w know that the h/w is now under the control of the
2077 * driver. */
2078 igb_get_hw_control(adapter);
2079
2080 strcpy(netdev->name, "eth%d");
2081 err = register_netdev(netdev);
2082 if (err)
2083 goto err_register;
2084
2085 igb_vlan_mode(netdev, netdev->features);
2086
2087 /* carrier off reporting is important to ethtool even BEFORE open */
2088 netif_carrier_off(netdev);
2089
2090 #ifdef CONFIG_IGB_DCA
2091 if (dca_add_requester(&pdev->dev) == 0) {
2092 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2093 dev_info(&pdev->dev, "DCA enabled\n");
2094 igb_setup_dca(adapter);
2095 }
2096
2097 #endif
2098 /* do hw tstamp init after resetting */
2099 igb_init_hw_timer(adapter);
2100
2101 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2102 /* print bus type/speed/width info */
2103 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2104 netdev->name,
2105 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2106 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2107 "unknown"),
2108 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2109 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2110 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2111 "unknown"),
2112 netdev->dev_addr);
2113
2114 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2115 if (ret_val)
2116 strcpy(part_str, "Unknown");
2117 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2118 dev_info(&pdev->dev,
2119 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2120 adapter->msix_entries ? "MSI-X" :
2121 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2122 adapter->num_rx_queues, adapter->num_tx_queues);
2123 switch (hw->mac.type) {
2124 case e1000_i350:
2125 igb_set_eee_i350(hw);
2126 break;
2127 default:
2128 break;
2129 }
2130 return 0;
2131
2132 err_register:
2133 igb_release_hw_control(adapter);
2134 err_eeprom:
2135 if (!igb_check_reset_block(hw))
2136 igb_reset_phy(hw);
2137
2138 if (hw->flash_address)
2139 iounmap(hw->flash_address);
2140 err_sw_init:
2141 igb_clear_interrupt_scheme(adapter);
2142 iounmap(hw->hw_addr);
2143 err_ioremap:
2144 free_netdev(netdev);
2145 err_alloc_etherdev:
2146 pci_release_selected_regions(pdev,
2147 pci_select_bars(pdev, IORESOURCE_MEM));
2148 err_pci_reg:
2149 err_dma:
2150 pci_disable_device(pdev);
2151 return err;
2152 }
2153
2154 /**
2155 * igb_remove - Device Removal Routine
2156 * @pdev: PCI device information struct
2157 *
2158 * igb_remove is called by the PCI subsystem to alert the driver
2159 * that it should release a PCI device. The could be caused by a
2160 * Hot-Plug event, or because the driver is going to be removed from
2161 * memory.
2162 **/
2163 static void __devexit igb_remove(struct pci_dev *pdev)
2164 {
2165 struct net_device *netdev = pci_get_drvdata(pdev);
2166 struct igb_adapter *adapter = netdev_priv(netdev);
2167 struct e1000_hw *hw = &adapter->hw;
2168
2169 /*
2170 * The watchdog timer may be rescheduled, so explicitly
2171 * disable watchdog from being rescheduled.
2172 */
2173 set_bit(__IGB_DOWN, &adapter->state);
2174 del_timer_sync(&adapter->watchdog_timer);
2175 del_timer_sync(&adapter->phy_info_timer);
2176
2177 cancel_work_sync(&adapter->reset_task);
2178 cancel_work_sync(&adapter->watchdog_task);
2179
2180 #ifdef CONFIG_IGB_DCA
2181 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2182 dev_info(&pdev->dev, "DCA disabled\n");
2183 dca_remove_requester(&pdev->dev);
2184 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2185 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2186 }
2187 #endif
2188
2189 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2190 * would have already happened in close and is redundant. */
2191 igb_release_hw_control(adapter);
2192
2193 unregister_netdev(netdev);
2194
2195 igb_clear_interrupt_scheme(adapter);
2196
2197 #ifdef CONFIG_PCI_IOV
2198 /* reclaim resources allocated to VFs */
2199 if (adapter->vf_data) {
2200 /* disable iov and allow time for transactions to clear */
2201 pci_disable_sriov(pdev);
2202 msleep(500);
2203
2204 kfree(adapter->vf_data);
2205 adapter->vf_data = NULL;
2206 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2207 wrfl();
2208 msleep(100);
2209 dev_info(&pdev->dev, "IOV Disabled\n");
2210 }
2211 #endif
2212
2213 iounmap(hw->hw_addr);
2214 if (hw->flash_address)
2215 iounmap(hw->flash_address);
2216 pci_release_selected_regions(pdev,
2217 pci_select_bars(pdev, IORESOURCE_MEM));
2218
2219 free_netdev(netdev);
2220
2221 pci_disable_pcie_error_reporting(pdev);
2222
2223 pci_disable_device(pdev);
2224 }
2225
2226 /**
2227 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2228 * @adapter: board private structure to initialize
2229 *
2230 * This function initializes the vf specific data storage and then attempts to
2231 * allocate the VFs. The reason for ordering it this way is because it is much
2232 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2233 * the memory for the VFs.
2234 **/
2235 static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2236 {
2237 #ifdef CONFIG_PCI_IOV
2238 struct pci_dev *pdev = adapter->pdev;
2239
2240 if (adapter->vfs_allocated_count) {
2241 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2242 sizeof(struct vf_data_storage),
2243 GFP_KERNEL);
2244 /* if allocation failed then we do not support SR-IOV */
2245 if (!adapter->vf_data) {
2246 adapter->vfs_allocated_count = 0;
2247 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2248 "Data Storage\n");
2249 }
2250 }
2251
2252 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
2253 kfree(adapter->vf_data);
2254 adapter->vf_data = NULL;
2255 #endif /* CONFIG_PCI_IOV */
2256 adapter->vfs_allocated_count = 0;
2257 #ifdef CONFIG_PCI_IOV
2258 } else {
2259 unsigned char mac_addr[ETH_ALEN];
2260 int i;
2261 dev_info(&pdev->dev, "%d vfs allocated\n",
2262 adapter->vfs_allocated_count);
2263 for (i = 0; i < adapter->vfs_allocated_count; i++) {
2264 random_ether_addr(mac_addr);
2265 igb_set_vf_mac(adapter, i, mac_addr);
2266 }
2267 /* DMA Coalescing is not supported in IOV mode. */
2268 if (adapter->flags & IGB_FLAG_DMAC)
2269 adapter->flags &= ~IGB_FLAG_DMAC;
2270 }
2271 #endif /* CONFIG_PCI_IOV */
2272 }
2273
2274
2275 /**
2276 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
2277 * @adapter: board private structure to initialize
2278 *
2279 * igb_init_hw_timer initializes the function pointer and values for the hw
2280 * timer found in hardware.
2281 **/
2282 static void igb_init_hw_timer(struct igb_adapter *adapter)
2283 {
2284 struct e1000_hw *hw = &adapter->hw;
2285
2286 switch (hw->mac.type) {
2287 case e1000_i350:
2288 case e1000_82580:
2289 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2290 adapter->cycles.read = igb_read_clock;
2291 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2292 adapter->cycles.mult = 1;
2293 /*
2294 * The 82580 timesync updates the system timer every 8ns by 8ns
2295 * and the value cannot be shifted. Instead we need to shift
2296 * the registers to generate a 64bit timer value. As a result
2297 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
2298 * 24 in order to generate a larger value for synchronization.
2299 */
2300 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
2301 /* disable system timer temporarily by setting bit 31 */
2302 wr32(E1000_TSAUXC, 0x80000000);
2303 wrfl();
2304
2305 /* Set registers so that rollover occurs soon to test this. */
2306 wr32(E1000_SYSTIMR, 0x00000000);
2307 wr32(E1000_SYSTIML, 0x80000000);
2308 wr32(E1000_SYSTIMH, 0x000000FF);
2309 wrfl();
2310
2311 /* enable system timer by clearing bit 31 */
2312 wr32(E1000_TSAUXC, 0x0);
2313 wrfl();
2314
2315 timecounter_init(&adapter->clock,
2316 &adapter->cycles,
2317 ktime_to_ns(ktime_get_real()));
2318 /*
2319 * Synchronize our NIC clock against system wall clock. NIC
2320 * time stamp reading requires ~3us per sample, each sample
2321 * was pretty stable even under load => only require 10
2322 * samples for each offset comparison.
2323 */
2324 memset(&adapter->compare, 0, sizeof(adapter->compare));
2325 adapter->compare.source = &adapter->clock;
2326 adapter->compare.target = ktime_get_real;
2327 adapter->compare.num_samples = 10;
2328 timecompare_update(&adapter->compare, 0);
2329 break;
2330 case e1000_82576:
2331 /*
2332 * Initialize hardware timer: we keep it running just in case
2333 * that some program needs it later on.
2334 */
2335 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2336 adapter->cycles.read = igb_read_clock;
2337 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2338 adapter->cycles.mult = 1;
2339 /**
2340 * Scale the NIC clock cycle by a large factor so that
2341 * relatively small clock corrections can be added or
2342 * subtracted at each clock tick. The drawbacks of a large
2343 * factor are a) that the clock register overflows more quickly
2344 * (not such a big deal) and b) that the increment per tick has
2345 * to fit into 24 bits. As a result we need to use a shift of
2346 * 19 so we can fit a value of 16 into the TIMINCA register.
2347 */
2348 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
2349 wr32(E1000_TIMINCA,
2350 (1 << E1000_TIMINCA_16NS_SHIFT) |
2351 (16 << IGB_82576_TSYNC_SHIFT));
2352
2353 /* Set registers so that rollover occurs soon to test this. */
2354 wr32(E1000_SYSTIML, 0x00000000);
2355 wr32(E1000_SYSTIMH, 0xFF800000);
2356 wrfl();
2357
2358 timecounter_init(&adapter->clock,
2359 &adapter->cycles,
2360 ktime_to_ns(ktime_get_real()));
2361 /*
2362 * Synchronize our NIC clock against system wall clock. NIC
2363 * time stamp reading requires ~3us per sample, each sample
2364 * was pretty stable even under load => only require 10
2365 * samples for each offset comparison.
2366 */
2367 memset(&adapter->compare, 0, sizeof(adapter->compare));
2368 adapter->compare.source = &adapter->clock;
2369 adapter->compare.target = ktime_get_real;
2370 adapter->compare.num_samples = 10;
2371 timecompare_update(&adapter->compare, 0);
2372 break;
2373 case e1000_82575:
2374 /* 82575 does not support timesync */
2375 default:
2376 break;
2377 }
2378
2379 }
2380
2381 /**
2382 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2383 * @adapter: board private structure to initialize
2384 *
2385 * igb_sw_init initializes the Adapter private data structure.
2386 * Fields are initialized based on PCI device information and
2387 * OS network device settings (MTU size).
2388 **/
2389 static int __devinit igb_sw_init(struct igb_adapter *adapter)
2390 {
2391 struct e1000_hw *hw = &adapter->hw;
2392 struct net_device *netdev = adapter->netdev;
2393 struct pci_dev *pdev = adapter->pdev;
2394
2395 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2396
2397 /* set default ring sizes */
2398 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2399 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2400
2401 /* set default ITR values */
2402 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2403 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2404
2405 /* set default work limits */
2406 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2407
2408 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2409 VLAN_HLEN;
2410 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2411
2412 spin_lock_init(&adapter->stats64_lock);
2413 #ifdef CONFIG_PCI_IOV
2414 switch (hw->mac.type) {
2415 case e1000_82576:
2416 case e1000_i350:
2417 if (max_vfs > 7) {
2418 dev_warn(&pdev->dev,
2419 "Maximum of 7 VFs per PF, using max\n");
2420 adapter->vfs_allocated_count = 7;
2421 } else
2422 adapter->vfs_allocated_count = max_vfs;
2423 break;
2424 default:
2425 break;
2426 }
2427 #endif /* CONFIG_PCI_IOV */
2428 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
2429 /* i350 cannot do RSS and SR-IOV at the same time */
2430 if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count)
2431 adapter->rss_queues = 1;
2432
2433 /*
2434 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2435 * then we should combine the queues into a queue pair in order to
2436 * conserve interrupts due to limited supply
2437 */
2438 if ((adapter->rss_queues > 4) ||
2439 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2440 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2441
2442 /* This call may decrease the number of queues */
2443 if (igb_init_interrupt_scheme(adapter)) {
2444 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2445 return -ENOMEM;
2446 }
2447
2448 igb_probe_vfs(adapter);
2449
2450 /* Explicitly disable IRQ since the NIC can be in any state. */
2451 igb_irq_disable(adapter);
2452
2453 if (hw->mac.type == e1000_i350)
2454 adapter->flags &= ~IGB_FLAG_DMAC;
2455
2456 set_bit(__IGB_DOWN, &adapter->state);
2457 return 0;
2458 }
2459
2460 /**
2461 * igb_open - Called when a network interface is made active
2462 * @netdev: network interface device structure
2463 *
2464 * Returns 0 on success, negative value on failure
2465 *
2466 * The open entry point is called when a network interface is made
2467 * active by the system (IFF_UP). At this point all resources needed
2468 * for transmit and receive operations are allocated, the interrupt
2469 * handler is registered with the OS, the watchdog timer is started,
2470 * and the stack is notified that the interface is ready.
2471 **/
2472 static int igb_open(struct net_device *netdev)
2473 {
2474 struct igb_adapter *adapter = netdev_priv(netdev);
2475 struct e1000_hw *hw = &adapter->hw;
2476 int err;
2477 int i;
2478
2479 /* disallow open during test */
2480 if (test_bit(__IGB_TESTING, &adapter->state))
2481 return -EBUSY;
2482
2483 netif_carrier_off(netdev);
2484
2485 /* allocate transmit descriptors */
2486 err = igb_setup_all_tx_resources(adapter);
2487 if (err)
2488 goto err_setup_tx;
2489
2490 /* allocate receive descriptors */
2491 err = igb_setup_all_rx_resources(adapter);
2492 if (err)
2493 goto err_setup_rx;
2494
2495 igb_power_up_link(adapter);
2496
2497 /* before we allocate an interrupt, we must be ready to handle it.
2498 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2499 * as soon as we call pci_request_irq, so we have to setup our
2500 * clean_rx handler before we do so. */
2501 igb_configure(adapter);
2502
2503 err = igb_request_irq(adapter);
2504 if (err)
2505 goto err_req_irq;
2506
2507 /* From here on the code is the same as igb_up() */
2508 clear_bit(__IGB_DOWN, &adapter->state);
2509
2510 for (i = 0; i < adapter->num_q_vectors; i++) {
2511 struct igb_q_vector *q_vector = adapter->q_vector[i];
2512 napi_enable(&q_vector->napi);
2513 }
2514
2515 /* Clear any pending interrupts. */
2516 rd32(E1000_ICR);
2517
2518 igb_irq_enable(adapter);
2519
2520 /* notify VFs that reset has been completed */
2521 if (adapter->vfs_allocated_count) {
2522 u32 reg_data = rd32(E1000_CTRL_EXT);
2523 reg_data |= E1000_CTRL_EXT_PFRSTD;
2524 wr32(E1000_CTRL_EXT, reg_data);
2525 }
2526
2527 netif_tx_start_all_queues(netdev);
2528
2529 /* start the watchdog. */
2530 hw->mac.get_link_status = 1;
2531 schedule_work(&adapter->watchdog_task);
2532
2533 return 0;
2534
2535 err_req_irq:
2536 igb_release_hw_control(adapter);
2537 igb_power_down_link(adapter);
2538 igb_free_all_rx_resources(adapter);
2539 err_setup_rx:
2540 igb_free_all_tx_resources(adapter);
2541 err_setup_tx:
2542 igb_reset(adapter);
2543
2544 return err;
2545 }
2546
2547 /**
2548 * igb_close - Disables a network interface
2549 * @netdev: network interface device structure
2550 *
2551 * Returns 0, this is not allowed to fail
2552 *
2553 * The close entry point is called when an interface is de-activated
2554 * by the OS. The hardware is still under the driver's control, but
2555 * needs to be disabled. A global MAC reset is issued to stop the
2556 * hardware, and all transmit and receive resources are freed.
2557 **/
2558 static int igb_close(struct net_device *netdev)
2559 {
2560 struct igb_adapter *adapter = netdev_priv(netdev);
2561
2562 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2563 igb_down(adapter);
2564
2565 igb_free_irq(adapter);
2566
2567 igb_free_all_tx_resources(adapter);
2568 igb_free_all_rx_resources(adapter);
2569
2570 return 0;
2571 }
2572
2573 /**
2574 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2575 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2576 *
2577 * Return 0 on success, negative on failure
2578 **/
2579 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2580 {
2581 struct device *dev = tx_ring->dev;
2582 int size;
2583
2584 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2585 tx_ring->tx_buffer_info = vzalloc(size);
2586 if (!tx_ring->tx_buffer_info)
2587 goto err;
2588
2589 /* round up to nearest 4K */
2590 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2591 tx_ring->size = ALIGN(tx_ring->size, 4096);
2592
2593 tx_ring->desc = dma_alloc_coherent(dev,
2594 tx_ring->size,
2595 &tx_ring->dma,
2596 GFP_KERNEL);
2597
2598 if (!tx_ring->desc)
2599 goto err;
2600
2601 tx_ring->next_to_use = 0;
2602 tx_ring->next_to_clean = 0;
2603 return 0;
2604
2605 err:
2606 vfree(tx_ring->tx_buffer_info);
2607 dev_err(dev,
2608 "Unable to allocate memory for the transmit descriptor ring\n");
2609 return -ENOMEM;
2610 }
2611
2612 /**
2613 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2614 * (Descriptors) for all queues
2615 * @adapter: board private structure
2616 *
2617 * Return 0 on success, negative on failure
2618 **/
2619 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2620 {
2621 struct pci_dev *pdev = adapter->pdev;
2622 int i, err = 0;
2623
2624 for (i = 0; i < adapter->num_tx_queues; i++) {
2625 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2626 if (err) {
2627 dev_err(&pdev->dev,
2628 "Allocation for Tx Queue %u failed\n", i);
2629 for (i--; i >= 0; i--)
2630 igb_free_tx_resources(adapter->tx_ring[i]);
2631 break;
2632 }
2633 }
2634
2635 return err;
2636 }
2637
2638 /**
2639 * igb_setup_tctl - configure the transmit control registers
2640 * @adapter: Board private structure
2641 **/
2642 void igb_setup_tctl(struct igb_adapter *adapter)
2643 {
2644 struct e1000_hw *hw = &adapter->hw;
2645 u32 tctl;
2646
2647 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2648 wr32(E1000_TXDCTL(0), 0);
2649
2650 /* Program the Transmit Control Register */
2651 tctl = rd32(E1000_TCTL);
2652 tctl &= ~E1000_TCTL_CT;
2653 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2654 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2655
2656 igb_config_collision_dist(hw);
2657
2658 /* Enable transmits */
2659 tctl |= E1000_TCTL_EN;
2660
2661 wr32(E1000_TCTL, tctl);
2662 }
2663
2664 /**
2665 * igb_configure_tx_ring - Configure transmit ring after Reset
2666 * @adapter: board private structure
2667 * @ring: tx ring to configure
2668 *
2669 * Configure a transmit ring after a reset.
2670 **/
2671 void igb_configure_tx_ring(struct igb_adapter *adapter,
2672 struct igb_ring *ring)
2673 {
2674 struct e1000_hw *hw = &adapter->hw;
2675 u32 txdctl = 0;
2676 u64 tdba = ring->dma;
2677 int reg_idx = ring->reg_idx;
2678
2679 /* disable the queue */
2680 wr32(E1000_TXDCTL(reg_idx), 0);
2681 wrfl();
2682 mdelay(10);
2683
2684 wr32(E1000_TDLEN(reg_idx),
2685 ring->count * sizeof(union e1000_adv_tx_desc));
2686 wr32(E1000_TDBAL(reg_idx),
2687 tdba & 0x00000000ffffffffULL);
2688 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2689
2690 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2691 wr32(E1000_TDH(reg_idx), 0);
2692 writel(0, ring->tail);
2693
2694 txdctl |= IGB_TX_PTHRESH;
2695 txdctl |= IGB_TX_HTHRESH << 8;
2696 txdctl |= IGB_TX_WTHRESH << 16;
2697
2698 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2699 wr32(E1000_TXDCTL(reg_idx), txdctl);
2700 }
2701
2702 /**
2703 * igb_configure_tx - Configure transmit Unit after Reset
2704 * @adapter: board private structure
2705 *
2706 * Configure the Tx unit of the MAC after a reset.
2707 **/
2708 static void igb_configure_tx(struct igb_adapter *adapter)
2709 {
2710 int i;
2711
2712 for (i = 0; i < adapter->num_tx_queues; i++)
2713 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2714 }
2715
2716 /**
2717 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2718 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2719 *
2720 * Returns 0 on success, negative on failure
2721 **/
2722 int igb_setup_rx_resources(struct igb_ring *rx_ring)
2723 {
2724 struct device *dev = rx_ring->dev;
2725 int size, desc_len;
2726
2727 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
2728 rx_ring->rx_buffer_info = vzalloc(size);
2729 if (!rx_ring->rx_buffer_info)
2730 goto err;
2731
2732 desc_len = sizeof(union e1000_adv_rx_desc);
2733
2734 /* Round up to nearest 4K */
2735 rx_ring->size = rx_ring->count * desc_len;
2736 rx_ring->size = ALIGN(rx_ring->size, 4096);
2737
2738 rx_ring->desc = dma_alloc_coherent(dev,
2739 rx_ring->size,
2740 &rx_ring->dma,
2741 GFP_KERNEL);
2742
2743 if (!rx_ring->desc)
2744 goto err;
2745
2746 rx_ring->next_to_clean = 0;
2747 rx_ring->next_to_use = 0;
2748
2749 return 0;
2750
2751 err:
2752 vfree(rx_ring->rx_buffer_info);
2753 rx_ring->rx_buffer_info = NULL;
2754 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2755 " ring\n");
2756 return -ENOMEM;
2757 }
2758
2759 /**
2760 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2761 * (Descriptors) for all queues
2762 * @adapter: board private structure
2763 *
2764 * Return 0 on success, negative on failure
2765 **/
2766 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2767 {
2768 struct pci_dev *pdev = adapter->pdev;
2769 int i, err = 0;
2770
2771 for (i = 0; i < adapter->num_rx_queues; i++) {
2772 err = igb_setup_rx_resources(adapter->rx_ring[i]);
2773 if (err) {
2774 dev_err(&pdev->dev,
2775 "Allocation for Rx Queue %u failed\n", i);
2776 for (i--; i >= 0; i--)
2777 igb_free_rx_resources(adapter->rx_ring[i]);
2778 break;
2779 }
2780 }
2781
2782 return err;
2783 }
2784
2785 /**
2786 * igb_setup_mrqc - configure the multiple receive queue control registers
2787 * @adapter: Board private structure
2788 **/
2789 static void igb_setup_mrqc(struct igb_adapter *adapter)
2790 {
2791 struct e1000_hw *hw = &adapter->hw;
2792 u32 mrqc, rxcsum;
2793 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2794 union e1000_reta {
2795 u32 dword;
2796 u8 bytes[4];
2797 } reta;
2798 static const u8 rsshash[40] = {
2799 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2800 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2801 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2802 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2803
2804 /* Fill out hash function seeds */
2805 for (j = 0; j < 10; j++) {
2806 u32 rsskey = rsshash[(j * 4)];
2807 rsskey |= rsshash[(j * 4) + 1] << 8;
2808 rsskey |= rsshash[(j * 4) + 2] << 16;
2809 rsskey |= rsshash[(j * 4) + 3] << 24;
2810 array_wr32(E1000_RSSRK(0), j, rsskey);
2811 }
2812
2813 num_rx_queues = adapter->rss_queues;
2814
2815 if (adapter->vfs_allocated_count) {
2816 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2817 switch (hw->mac.type) {
2818 case e1000_i350:
2819 case e1000_82580:
2820 num_rx_queues = 1;
2821 shift = 0;
2822 break;
2823 case e1000_82576:
2824 shift = 3;
2825 num_rx_queues = 2;
2826 break;
2827 case e1000_82575:
2828 shift = 2;
2829 shift2 = 6;
2830 default:
2831 break;
2832 }
2833 } else {
2834 if (hw->mac.type == e1000_82575)
2835 shift = 6;
2836 }
2837
2838 for (j = 0; j < (32 * 4); j++) {
2839 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2840 if (shift2)
2841 reta.bytes[j & 3] |= num_rx_queues << shift2;
2842 if ((j & 3) == 3)
2843 wr32(E1000_RETA(j >> 2), reta.dword);
2844 }
2845
2846 /*
2847 * Disable raw packet checksumming so that RSS hash is placed in
2848 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2849 * offloads as they are enabled by default
2850 */
2851 rxcsum = rd32(E1000_RXCSUM);
2852 rxcsum |= E1000_RXCSUM_PCSD;
2853
2854 if (adapter->hw.mac.type >= e1000_82576)
2855 /* Enable Receive Checksum Offload for SCTP */
2856 rxcsum |= E1000_RXCSUM_CRCOFL;
2857
2858 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2859 wr32(E1000_RXCSUM, rxcsum);
2860
2861 /* If VMDq is enabled then we set the appropriate mode for that, else
2862 * we default to RSS so that an RSS hash is calculated per packet even
2863 * if we are only using one queue */
2864 if (adapter->vfs_allocated_count) {
2865 if (hw->mac.type > e1000_82575) {
2866 /* Set the default pool for the PF's first queue */
2867 u32 vtctl = rd32(E1000_VT_CTL);
2868 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2869 E1000_VT_CTL_DISABLE_DEF_POOL);
2870 vtctl |= adapter->vfs_allocated_count <<
2871 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2872 wr32(E1000_VT_CTL, vtctl);
2873 }
2874 if (adapter->rss_queues > 1)
2875 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2876 else
2877 mrqc = E1000_MRQC_ENABLE_VMDQ;
2878 } else {
2879 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2880 }
2881 igb_vmm_control(adapter);
2882
2883 /*
2884 * Generate RSS hash based on TCP port numbers and/or
2885 * IPv4/v6 src and dst addresses since UDP cannot be
2886 * hashed reliably due to IP fragmentation
2887 */
2888 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2889 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2890 E1000_MRQC_RSS_FIELD_IPV6 |
2891 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2892 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2893
2894 wr32(E1000_MRQC, mrqc);
2895 }
2896
2897 /**
2898 * igb_setup_rctl - configure the receive control registers
2899 * @adapter: Board private structure
2900 **/
2901 void igb_setup_rctl(struct igb_adapter *adapter)
2902 {
2903 struct e1000_hw *hw = &adapter->hw;
2904 u32 rctl;
2905
2906 rctl = rd32(E1000_RCTL);
2907
2908 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2909 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2910
2911 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2912 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2913
2914 /*
2915 * enable stripping of CRC. It's unlikely this will break BMC
2916 * redirection as it did with e1000. Newer features require
2917 * that the HW strips the CRC.
2918 */
2919 rctl |= E1000_RCTL_SECRC;
2920
2921 /* disable store bad packets and clear size bits. */
2922 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2923
2924 /* enable LPE to prevent packets larger than max_frame_size */
2925 rctl |= E1000_RCTL_LPE;
2926
2927 /* disable queue 0 to prevent tail write w/o re-config */
2928 wr32(E1000_RXDCTL(0), 0);
2929
2930 /* Attention!!! For SR-IOV PF driver operations you must enable
2931 * queue drop for all VF and PF queues to prevent head of line blocking
2932 * if an un-trusted VF does not provide descriptors to hardware.
2933 */
2934 if (adapter->vfs_allocated_count) {
2935 /* set all queue drop enable bits */
2936 wr32(E1000_QDE, ALL_QUEUES);
2937 }
2938
2939 wr32(E1000_RCTL, rctl);
2940 }
2941
2942 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2943 int vfn)
2944 {
2945 struct e1000_hw *hw = &adapter->hw;
2946 u32 vmolr;
2947
2948 /* if it isn't the PF check to see if VFs are enabled and
2949 * increase the size to support vlan tags */
2950 if (vfn < adapter->vfs_allocated_count &&
2951 adapter->vf_data[vfn].vlans_enabled)
2952 size += VLAN_TAG_SIZE;
2953
2954 vmolr = rd32(E1000_VMOLR(vfn));
2955 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2956 vmolr |= size | E1000_VMOLR_LPE;
2957 wr32(E1000_VMOLR(vfn), vmolr);
2958
2959 return 0;
2960 }
2961
2962 /**
2963 * igb_rlpml_set - set maximum receive packet size
2964 * @adapter: board private structure
2965 *
2966 * Configure maximum receivable packet size.
2967 **/
2968 static void igb_rlpml_set(struct igb_adapter *adapter)
2969 {
2970 u32 max_frame_size = adapter->max_frame_size;
2971 struct e1000_hw *hw = &adapter->hw;
2972 u16 pf_id = adapter->vfs_allocated_count;
2973
2974 if (pf_id) {
2975 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2976 /*
2977 * If we're in VMDQ or SR-IOV mode, then set global RLPML
2978 * to our max jumbo frame size, in case we need to enable
2979 * jumbo frames on one of the rings later.
2980 * This will not pass over-length frames into the default
2981 * queue because it's gated by the VMOLR.RLPML.
2982 */
2983 max_frame_size = MAX_JUMBO_FRAME_SIZE;
2984 }
2985
2986 wr32(E1000_RLPML, max_frame_size);
2987 }
2988
2989 static inline void igb_set_vmolr(struct igb_adapter *adapter,
2990 int vfn, bool aupe)
2991 {
2992 struct e1000_hw *hw = &adapter->hw;
2993 u32 vmolr;
2994
2995 /*
2996 * This register exists only on 82576 and newer so if we are older then
2997 * we should exit and do nothing
2998 */
2999 if (hw->mac.type < e1000_82576)
3000 return;
3001
3002 vmolr = rd32(E1000_VMOLR(vfn));
3003 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3004 if (aupe)
3005 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3006 else
3007 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3008
3009 /* clear all bits that might not be set */
3010 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3011
3012 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3013 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3014 /*
3015 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3016 * multicast packets
3017 */
3018 if (vfn <= adapter->vfs_allocated_count)
3019 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3020
3021 wr32(E1000_VMOLR(vfn), vmolr);
3022 }
3023
3024 /**
3025 * igb_configure_rx_ring - Configure a receive ring after Reset
3026 * @adapter: board private structure
3027 * @ring: receive ring to be configured
3028 *
3029 * Configure the Rx unit of the MAC after a reset.
3030 **/
3031 void igb_configure_rx_ring(struct igb_adapter *adapter,
3032 struct igb_ring *ring)
3033 {
3034 struct e1000_hw *hw = &adapter->hw;
3035 u64 rdba = ring->dma;
3036 int reg_idx = ring->reg_idx;
3037 u32 srrctl = 0, rxdctl = 0;
3038
3039 /* disable the queue */
3040 wr32(E1000_RXDCTL(reg_idx), 0);
3041
3042 /* Set DMA base address registers */
3043 wr32(E1000_RDBAL(reg_idx),
3044 rdba & 0x00000000ffffffffULL);
3045 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3046 wr32(E1000_RDLEN(reg_idx),
3047 ring->count * sizeof(union e1000_adv_rx_desc));
3048
3049 /* initialize head and tail */
3050 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3051 wr32(E1000_RDH(reg_idx), 0);
3052 writel(0, ring->tail);
3053
3054 /* set descriptor configuration */
3055 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3056 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3057 srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3058 #else
3059 srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3060 #endif
3061 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3062 if (hw->mac.type == e1000_82580)
3063 srrctl |= E1000_SRRCTL_TIMESTAMP;
3064 /* Only set Drop Enable if we are supporting multiple queues */
3065 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3066 srrctl |= E1000_SRRCTL_DROP_EN;
3067
3068 wr32(E1000_SRRCTL(reg_idx), srrctl);
3069
3070 /* set filtering for VMDQ pools */
3071 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3072
3073 rxdctl |= IGB_RX_PTHRESH;
3074 rxdctl |= IGB_RX_HTHRESH << 8;
3075 rxdctl |= IGB_RX_WTHRESH << 16;
3076
3077 /* enable receive descriptor fetching */
3078 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3079 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3080 }
3081
3082 /**
3083 * igb_configure_rx - Configure receive Unit after Reset
3084 * @adapter: board private structure
3085 *
3086 * Configure the Rx unit of the MAC after a reset.
3087 **/
3088 static void igb_configure_rx(struct igb_adapter *adapter)
3089 {
3090 int i;
3091
3092 /* set UTA to appropriate mode */
3093 igb_set_uta(adapter);
3094
3095 /* set the correct pool for the PF default MAC address in entry 0 */
3096 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3097 adapter->vfs_allocated_count);
3098
3099 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3100 * the Base and Length of the Rx Descriptor Ring */
3101 for (i = 0; i < adapter->num_rx_queues; i++)
3102 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3103 }
3104
3105 /**
3106 * igb_free_tx_resources - Free Tx Resources per Queue
3107 * @tx_ring: Tx descriptor ring for a specific queue
3108 *
3109 * Free all transmit software resources
3110 **/
3111 void igb_free_tx_resources(struct igb_ring *tx_ring)
3112 {
3113 igb_clean_tx_ring(tx_ring);
3114
3115 vfree(tx_ring->tx_buffer_info);
3116 tx_ring->tx_buffer_info = NULL;
3117
3118 /* if not set, then don't free */
3119 if (!tx_ring->desc)
3120 return;
3121
3122 dma_free_coherent(tx_ring->dev, tx_ring->size,
3123 tx_ring->desc, tx_ring->dma);
3124
3125 tx_ring->desc = NULL;
3126 }
3127
3128 /**
3129 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3130 * @adapter: board private structure
3131 *
3132 * Free all transmit software resources
3133 **/
3134 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3135 {
3136 int i;
3137
3138 for (i = 0; i < adapter->num_tx_queues; i++)
3139 igb_free_tx_resources(adapter->tx_ring[i]);
3140 }
3141
3142 void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
3143 struct igb_tx_buffer *buffer_info)
3144 {
3145 if (buffer_info->dma) {
3146 if (buffer_info->mapped_as_page)
3147 dma_unmap_page(tx_ring->dev,
3148 buffer_info->dma,
3149 buffer_info->length,
3150 DMA_TO_DEVICE);
3151 else
3152 dma_unmap_single(tx_ring->dev,
3153 buffer_info->dma,
3154 buffer_info->length,
3155 DMA_TO_DEVICE);
3156 buffer_info->dma = 0;
3157 }
3158 if (buffer_info->skb) {
3159 dev_kfree_skb_any(buffer_info->skb);
3160 buffer_info->skb = NULL;
3161 }
3162 buffer_info->time_stamp = 0;
3163 buffer_info->length = 0;
3164 buffer_info->next_to_watch = NULL;
3165 buffer_info->mapped_as_page = false;
3166 }
3167
3168 /**
3169 * igb_clean_tx_ring - Free Tx Buffers
3170 * @tx_ring: ring to be cleaned
3171 **/
3172 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3173 {
3174 struct igb_tx_buffer *buffer_info;
3175 unsigned long size;
3176 unsigned int i;
3177
3178 if (!tx_ring->tx_buffer_info)
3179 return;
3180 /* Free all the Tx ring sk_buffs */
3181
3182 for (i = 0; i < tx_ring->count; i++) {
3183 buffer_info = &tx_ring->tx_buffer_info[i];
3184 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3185 }
3186
3187 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3188 memset(tx_ring->tx_buffer_info, 0, size);
3189
3190 /* Zero out the descriptor ring */
3191 memset(tx_ring->desc, 0, tx_ring->size);
3192
3193 tx_ring->next_to_use = 0;
3194 tx_ring->next_to_clean = 0;
3195 }
3196
3197 /**
3198 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3199 * @adapter: board private structure
3200 **/
3201 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3202 {
3203 int i;
3204
3205 for (i = 0; i < adapter->num_tx_queues; i++)
3206 igb_clean_tx_ring(adapter->tx_ring[i]);
3207 }
3208
3209 /**
3210 * igb_free_rx_resources - Free Rx Resources
3211 * @rx_ring: ring to clean the resources from
3212 *
3213 * Free all receive software resources
3214 **/
3215 void igb_free_rx_resources(struct igb_ring *rx_ring)
3216 {
3217 igb_clean_rx_ring(rx_ring);
3218
3219 vfree(rx_ring->rx_buffer_info);
3220 rx_ring->rx_buffer_info = NULL;
3221
3222 /* if not set, then don't free */
3223 if (!rx_ring->desc)
3224 return;
3225
3226 dma_free_coherent(rx_ring->dev, rx_ring->size,
3227 rx_ring->desc, rx_ring->dma);
3228
3229 rx_ring->desc = NULL;
3230 }
3231
3232 /**
3233 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3234 * @adapter: board private structure
3235 *
3236 * Free all receive software resources
3237 **/
3238 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3239 {
3240 int i;
3241
3242 for (i = 0; i < adapter->num_rx_queues; i++)
3243 igb_free_rx_resources(adapter->rx_ring[i]);
3244 }
3245
3246 /**
3247 * igb_clean_rx_ring - Free Rx Buffers per Queue
3248 * @rx_ring: ring to free buffers from
3249 **/
3250 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3251 {
3252 unsigned long size;
3253 u16 i;
3254
3255 if (!rx_ring->rx_buffer_info)
3256 return;
3257
3258 /* Free all the Rx ring sk_buffs */
3259 for (i = 0; i < rx_ring->count; i++) {
3260 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3261 if (buffer_info->dma) {
3262 dma_unmap_single(rx_ring->dev,
3263 buffer_info->dma,
3264 IGB_RX_HDR_LEN,
3265 DMA_FROM_DEVICE);
3266 buffer_info->dma = 0;
3267 }
3268
3269 if (buffer_info->skb) {
3270 dev_kfree_skb(buffer_info->skb);
3271 buffer_info->skb = NULL;
3272 }
3273 if (buffer_info->page_dma) {
3274 dma_unmap_page(rx_ring->dev,
3275 buffer_info->page_dma,
3276 PAGE_SIZE / 2,
3277 DMA_FROM_DEVICE);
3278 buffer_info->page_dma = 0;
3279 }
3280 if (buffer_info->page) {
3281 put_page(buffer_info->page);
3282 buffer_info->page = NULL;
3283 buffer_info->page_offset = 0;
3284 }
3285 }
3286
3287 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3288 memset(rx_ring->rx_buffer_info, 0, size);
3289
3290 /* Zero out the descriptor ring */
3291 memset(rx_ring->desc, 0, rx_ring->size);
3292
3293 rx_ring->next_to_clean = 0;
3294 rx_ring->next_to_use = 0;
3295 }
3296
3297 /**
3298 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3299 * @adapter: board private structure
3300 **/
3301 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3302 {
3303 int i;
3304
3305 for (i = 0; i < adapter->num_rx_queues; i++)
3306 igb_clean_rx_ring(adapter->rx_ring[i]);
3307 }
3308
3309 /**
3310 * igb_set_mac - Change the Ethernet Address of the NIC
3311 * @netdev: network interface device structure
3312 * @p: pointer to an address structure
3313 *
3314 * Returns 0 on success, negative on failure
3315 **/
3316 static int igb_set_mac(struct net_device *netdev, void *p)
3317 {
3318 struct igb_adapter *adapter = netdev_priv(netdev);
3319 struct e1000_hw *hw = &adapter->hw;
3320 struct sockaddr *addr = p;
3321
3322 if (!is_valid_ether_addr(addr->sa_data))
3323 return -EADDRNOTAVAIL;
3324
3325 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3326 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3327
3328 /* set the correct pool for the new PF MAC address in entry 0 */
3329 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3330 adapter->vfs_allocated_count);
3331
3332 return 0;
3333 }
3334
3335 /**
3336 * igb_write_mc_addr_list - write multicast addresses to MTA
3337 * @netdev: network interface device structure
3338 *
3339 * Writes multicast address list to the MTA hash table.
3340 * Returns: -ENOMEM on failure
3341 * 0 on no addresses written
3342 * X on writing X addresses to MTA
3343 **/
3344 static int igb_write_mc_addr_list(struct net_device *netdev)
3345 {
3346 struct igb_adapter *adapter = netdev_priv(netdev);
3347 struct e1000_hw *hw = &adapter->hw;
3348 struct netdev_hw_addr *ha;
3349 u8 *mta_list;
3350 int i;
3351
3352 if (netdev_mc_empty(netdev)) {
3353 /* nothing to program, so clear mc list */
3354 igb_update_mc_addr_list(hw, NULL, 0);
3355 igb_restore_vf_multicasts(adapter);
3356 return 0;
3357 }
3358
3359 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3360 if (!mta_list)
3361 return -ENOMEM;
3362
3363 /* The shared function expects a packed array of only addresses. */
3364 i = 0;
3365 netdev_for_each_mc_addr(ha, netdev)
3366 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3367
3368 igb_update_mc_addr_list(hw, mta_list, i);
3369 kfree(mta_list);
3370
3371 return netdev_mc_count(netdev);
3372 }
3373
3374 /**
3375 * igb_write_uc_addr_list - write unicast addresses to RAR table
3376 * @netdev: network interface device structure
3377 *
3378 * Writes unicast address list to the RAR table.
3379 * Returns: -ENOMEM on failure/insufficient address space
3380 * 0 on no addresses written
3381 * X on writing X addresses to the RAR table
3382 **/
3383 static int igb_write_uc_addr_list(struct net_device *netdev)
3384 {
3385 struct igb_adapter *adapter = netdev_priv(netdev);
3386 struct e1000_hw *hw = &adapter->hw;
3387 unsigned int vfn = adapter->vfs_allocated_count;
3388 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3389 int count = 0;
3390
3391 /* return ENOMEM indicating insufficient memory for addresses */
3392 if (netdev_uc_count(netdev) > rar_entries)
3393 return -ENOMEM;
3394
3395 if (!netdev_uc_empty(netdev) && rar_entries) {
3396 struct netdev_hw_addr *ha;
3397
3398 netdev_for_each_uc_addr(ha, netdev) {
3399 if (!rar_entries)
3400 break;
3401 igb_rar_set_qsel(adapter, ha->addr,
3402 rar_entries--,
3403 vfn);
3404 count++;
3405 }
3406 }
3407 /* write the addresses in reverse order to avoid write combining */
3408 for (; rar_entries > 0 ; rar_entries--) {
3409 wr32(E1000_RAH(rar_entries), 0);
3410 wr32(E1000_RAL(rar_entries), 0);
3411 }
3412 wrfl();
3413
3414 return count;
3415 }
3416
3417 /**
3418 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3419 * @netdev: network interface device structure
3420 *
3421 * The set_rx_mode entry point is called whenever the unicast or multicast
3422 * address lists or the network interface flags are updated. This routine is
3423 * responsible for configuring the hardware for proper unicast, multicast,
3424 * promiscuous mode, and all-multi behavior.
3425 **/
3426 static void igb_set_rx_mode(struct net_device *netdev)
3427 {
3428 struct igb_adapter *adapter = netdev_priv(netdev);
3429 struct e1000_hw *hw = &adapter->hw;
3430 unsigned int vfn = adapter->vfs_allocated_count;
3431 u32 rctl, vmolr = 0;
3432 int count;
3433
3434 /* Check for Promiscuous and All Multicast modes */
3435 rctl = rd32(E1000_RCTL);
3436
3437 /* clear the effected bits */
3438 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3439
3440 if (netdev->flags & IFF_PROMISC) {
3441 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3442 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3443 } else {
3444 if (netdev->flags & IFF_ALLMULTI) {
3445 rctl |= E1000_RCTL_MPE;
3446 vmolr |= E1000_VMOLR_MPME;
3447 } else {
3448 /*
3449 * Write addresses to the MTA, if the attempt fails
3450 * then we should just turn on promiscuous mode so
3451 * that we can at least receive multicast traffic
3452 */
3453 count = igb_write_mc_addr_list(netdev);
3454 if (count < 0) {
3455 rctl |= E1000_RCTL_MPE;
3456 vmolr |= E1000_VMOLR_MPME;
3457 } else if (count) {
3458 vmolr |= E1000_VMOLR_ROMPE;
3459 }
3460 }
3461 /*
3462 * Write addresses to available RAR registers, if there is not
3463 * sufficient space to store all the addresses then enable
3464 * unicast promiscuous mode
3465 */
3466 count = igb_write_uc_addr_list(netdev);
3467 if (count < 0) {
3468 rctl |= E1000_RCTL_UPE;
3469 vmolr |= E1000_VMOLR_ROPE;
3470 }
3471 rctl |= E1000_RCTL_VFE;
3472 }
3473 wr32(E1000_RCTL, rctl);
3474
3475 /*
3476 * In order to support SR-IOV and eventually VMDq it is necessary to set
3477 * the VMOLR to enable the appropriate modes. Without this workaround
3478 * we will have issues with VLAN tag stripping not being done for frames
3479 * that are only arriving because we are the default pool
3480 */
3481 if (hw->mac.type < e1000_82576)
3482 return;
3483
3484 vmolr |= rd32(E1000_VMOLR(vfn)) &
3485 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3486 wr32(E1000_VMOLR(vfn), vmolr);
3487 igb_restore_vf_multicasts(adapter);
3488 }
3489
3490 static void igb_check_wvbr(struct igb_adapter *adapter)
3491 {
3492 struct e1000_hw *hw = &adapter->hw;
3493 u32 wvbr = 0;
3494
3495 switch (hw->mac.type) {
3496 case e1000_82576:
3497 case e1000_i350:
3498 if (!(wvbr = rd32(E1000_WVBR)))
3499 return;
3500 break;
3501 default:
3502 break;
3503 }
3504
3505 adapter->wvbr |= wvbr;
3506 }
3507
3508 #define IGB_STAGGERED_QUEUE_OFFSET 8
3509
3510 static void igb_spoof_check(struct igb_adapter *adapter)
3511 {
3512 int j;
3513
3514 if (!adapter->wvbr)
3515 return;
3516
3517 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3518 if (adapter->wvbr & (1 << j) ||
3519 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3520 dev_warn(&adapter->pdev->dev,
3521 "Spoof event(s) detected on VF %d\n", j);
3522 adapter->wvbr &=
3523 ~((1 << j) |
3524 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3525 }
3526 }
3527 }
3528
3529 /* Need to wait a few seconds after link up to get diagnostic information from
3530 * the phy */
3531 static void igb_update_phy_info(unsigned long data)
3532 {
3533 struct igb_adapter *adapter = (struct igb_adapter *) data;
3534 igb_get_phy_info(&adapter->hw);
3535 }
3536
3537 /**
3538 * igb_has_link - check shared code for link and determine up/down
3539 * @adapter: pointer to driver private info
3540 **/
3541 bool igb_has_link(struct igb_adapter *adapter)
3542 {
3543 struct e1000_hw *hw = &adapter->hw;
3544 bool link_active = false;
3545 s32 ret_val = 0;
3546
3547 /* get_link_status is set on LSC (link status) interrupt or
3548 * rx sequence error interrupt. get_link_status will stay
3549 * false until the e1000_check_for_link establishes link
3550 * for copper adapters ONLY
3551 */
3552 switch (hw->phy.media_type) {
3553 case e1000_media_type_copper:
3554 if (hw->mac.get_link_status) {
3555 ret_val = hw->mac.ops.check_for_link(hw);
3556 link_active = !hw->mac.get_link_status;
3557 } else {
3558 link_active = true;
3559 }
3560 break;
3561 case e1000_media_type_internal_serdes:
3562 ret_val = hw->mac.ops.check_for_link(hw);
3563 link_active = hw->mac.serdes_has_link;
3564 break;
3565 default:
3566 case e1000_media_type_unknown:
3567 break;
3568 }
3569
3570 return link_active;
3571 }
3572
3573 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3574 {
3575 bool ret = false;
3576 u32 ctrl_ext, thstat;
3577
3578 /* check for thermal sensor event on i350, copper only */
3579 if (hw->mac.type == e1000_i350) {
3580 thstat = rd32(E1000_THSTAT);
3581 ctrl_ext = rd32(E1000_CTRL_EXT);
3582
3583 if ((hw->phy.media_type == e1000_media_type_copper) &&
3584 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3585 ret = !!(thstat & event);
3586 }
3587 }
3588
3589 return ret;
3590 }
3591
3592 /**
3593 * igb_watchdog - Timer Call-back
3594 * @data: pointer to adapter cast into an unsigned long
3595 **/
3596 static void igb_watchdog(unsigned long data)
3597 {
3598 struct igb_adapter *adapter = (struct igb_adapter *)data;
3599 /* Do the rest outside of interrupt context */
3600 schedule_work(&adapter->watchdog_task);
3601 }
3602
3603 static void igb_watchdog_task(struct work_struct *work)
3604 {
3605 struct igb_adapter *adapter = container_of(work,
3606 struct igb_adapter,
3607 watchdog_task);
3608 struct e1000_hw *hw = &adapter->hw;
3609 struct net_device *netdev = adapter->netdev;
3610 u32 link;
3611 int i;
3612
3613 link = igb_has_link(adapter);
3614 if (link) {
3615 if (!netif_carrier_ok(netdev)) {
3616 u32 ctrl;
3617 hw->mac.ops.get_speed_and_duplex(hw,
3618 &adapter->link_speed,
3619 &adapter->link_duplex);
3620
3621 ctrl = rd32(E1000_CTRL);
3622 /* Links status message must follow this format */
3623 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
3624 "Flow Control: %s\n",
3625 netdev->name,
3626 adapter->link_speed,
3627 adapter->link_duplex == FULL_DUPLEX ?
3628 "Full Duplex" : "Half Duplex",
3629 ((ctrl & E1000_CTRL_TFCE) &&
3630 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3631 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3632 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
3633
3634 /* check for thermal sensor event */
3635 if (igb_thermal_sensor_event(hw, E1000_THSTAT_LINK_THROTTLE)) {
3636 printk(KERN_INFO "igb: %s The network adapter "
3637 "link speed was downshifted "
3638 "because it overheated.\n",
3639 netdev->name);
3640 }
3641
3642 /* adjust timeout factor according to speed/duplex */
3643 adapter->tx_timeout_factor = 1;
3644 switch (adapter->link_speed) {
3645 case SPEED_10:
3646 adapter->tx_timeout_factor = 14;
3647 break;
3648 case SPEED_100:
3649 /* maybe add some timeout factor ? */
3650 break;
3651 }
3652
3653 netif_carrier_on(netdev);
3654
3655 igb_ping_all_vfs(adapter);
3656 igb_check_vf_rate_limit(adapter);
3657
3658 /* link state has changed, schedule phy info update */
3659 if (!test_bit(__IGB_DOWN, &adapter->state))
3660 mod_timer(&adapter->phy_info_timer,
3661 round_jiffies(jiffies + 2 * HZ));
3662 }
3663 } else {
3664 if (netif_carrier_ok(netdev)) {
3665 adapter->link_speed = 0;
3666 adapter->link_duplex = 0;
3667
3668 /* check for thermal sensor event */
3669 if (igb_thermal_sensor_event(hw, E1000_THSTAT_PWR_DOWN)) {
3670 printk(KERN_ERR "igb: %s The network adapter "
3671 "was stopped because it "
3672 "overheated.\n",
3673 netdev->name);
3674 }
3675
3676 /* Links status message must follow this format */
3677 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3678 netdev->name);
3679 netif_carrier_off(netdev);
3680
3681 igb_ping_all_vfs(adapter);
3682
3683 /* link state has changed, schedule phy info update */
3684 if (!test_bit(__IGB_DOWN, &adapter->state))
3685 mod_timer(&adapter->phy_info_timer,
3686 round_jiffies(jiffies + 2 * HZ));
3687 }
3688 }
3689
3690 spin_lock(&adapter->stats64_lock);
3691 igb_update_stats(adapter, &adapter->stats64);
3692 spin_unlock(&adapter->stats64_lock);
3693
3694 for (i = 0; i < adapter->num_tx_queues; i++) {
3695 struct igb_ring *tx_ring = adapter->tx_ring[i];
3696 if (!netif_carrier_ok(netdev)) {
3697 /* We've lost link, so the controller stops DMA,
3698 * but we've got queued Tx work that's never going
3699 * to get done, so reset controller to flush Tx.
3700 * (Do the reset outside of interrupt context). */
3701 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3702 adapter->tx_timeout_count++;
3703 schedule_work(&adapter->reset_task);
3704 /* return immediately since reset is imminent */
3705 return;
3706 }
3707 }
3708
3709 /* Force detection of hung controller every watchdog period */
3710 tx_ring->detect_tx_hung = true;
3711 }
3712
3713 /* Cause software interrupt to ensure rx ring is cleaned */
3714 if (adapter->msix_entries) {
3715 u32 eics = 0;
3716 for (i = 0; i < adapter->num_q_vectors; i++) {
3717 struct igb_q_vector *q_vector = adapter->q_vector[i];
3718 eics |= q_vector->eims_value;
3719 }
3720 wr32(E1000_EICS, eics);
3721 } else {
3722 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3723 }
3724
3725 igb_spoof_check(adapter);
3726
3727 /* Reset the timer */
3728 if (!test_bit(__IGB_DOWN, &adapter->state))
3729 mod_timer(&adapter->watchdog_timer,
3730 round_jiffies(jiffies + 2 * HZ));
3731 }
3732
3733 enum latency_range {
3734 lowest_latency = 0,
3735 low_latency = 1,
3736 bulk_latency = 2,
3737 latency_invalid = 255
3738 };
3739
3740 /**
3741 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3742 *
3743 * Stores a new ITR value based on strictly on packet size. This
3744 * algorithm is less sophisticated than that used in igb_update_itr,
3745 * due to the difficulty of synchronizing statistics across multiple
3746 * receive rings. The divisors and thresholds used by this function
3747 * were determined based on theoretical maximum wire speed and testing
3748 * data, in order to minimize response time while increasing bulk
3749 * throughput.
3750 * This functionality is controlled by the InterruptThrottleRate module
3751 * parameter (see igb_param.c)
3752 * NOTE: This function is called only when operating in a multiqueue
3753 * receive environment.
3754 * @q_vector: pointer to q_vector
3755 **/
3756 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3757 {
3758 int new_val = q_vector->itr_val;
3759 int avg_wire_size = 0;
3760 struct igb_adapter *adapter = q_vector->adapter;
3761 struct igb_ring *ring;
3762 unsigned int packets;
3763
3764 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3765 * ints/sec - ITR timer value of 120 ticks.
3766 */
3767 if (adapter->link_speed != SPEED_1000) {
3768 new_val = 976;
3769 goto set_itr_val;
3770 }
3771
3772 ring = q_vector->rx_ring;
3773 if (ring) {
3774 packets = ACCESS_ONCE(ring->total_packets);
3775
3776 if (packets)
3777 avg_wire_size = ring->total_bytes / packets;
3778 }
3779
3780 ring = q_vector->tx_ring;
3781 if (ring) {
3782 packets = ACCESS_ONCE(ring->total_packets);
3783
3784 if (packets)
3785 avg_wire_size = max_t(u32, avg_wire_size,
3786 ring->total_bytes / packets);
3787 }
3788
3789 /* if avg_wire_size isn't set no work was done */
3790 if (!avg_wire_size)
3791 goto clear_counts;
3792
3793 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3794 avg_wire_size += 24;
3795
3796 /* Don't starve jumbo frames */
3797 avg_wire_size = min(avg_wire_size, 3000);
3798
3799 /* Give a little boost to mid-size frames */
3800 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3801 new_val = avg_wire_size / 3;
3802 else
3803 new_val = avg_wire_size / 2;
3804
3805 /* when in itr mode 3 do not exceed 20K ints/sec */
3806 if (adapter->rx_itr_setting == 3 && new_val < 196)
3807 new_val = 196;
3808
3809 set_itr_val:
3810 if (new_val != q_vector->itr_val) {
3811 q_vector->itr_val = new_val;
3812 q_vector->set_itr = 1;
3813 }
3814 clear_counts:
3815 if (q_vector->rx_ring) {
3816 q_vector->rx_ring->total_bytes = 0;
3817 q_vector->rx_ring->total_packets = 0;
3818 }
3819 if (q_vector->tx_ring) {
3820 q_vector->tx_ring->total_bytes = 0;
3821 q_vector->tx_ring->total_packets = 0;
3822 }
3823 }
3824
3825 /**
3826 * igb_update_itr - update the dynamic ITR value based on statistics
3827 * Stores a new ITR value based on packets and byte
3828 * counts during the last interrupt. The advantage of per interrupt
3829 * computation is faster updates and more accurate ITR for the current
3830 * traffic pattern. Constants in this function were computed
3831 * based on theoretical maximum wire speed and thresholds were set based
3832 * on testing data as well as attempting to minimize response time
3833 * while increasing bulk throughput.
3834 * this functionality is controlled by the InterruptThrottleRate module
3835 * parameter (see igb_param.c)
3836 * NOTE: These calculations are only valid when operating in a single-
3837 * queue environment.
3838 * @adapter: pointer to adapter
3839 * @itr_setting: current q_vector->itr_val
3840 * @packets: the number of packets during this measurement interval
3841 * @bytes: the number of bytes during this measurement interval
3842 **/
3843 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3844 int packets, int bytes)
3845 {
3846 unsigned int retval = itr_setting;
3847
3848 if (packets == 0)
3849 goto update_itr_done;
3850
3851 switch (itr_setting) {
3852 case lowest_latency:
3853 /* handle TSO and jumbo frames */
3854 if (bytes/packets > 8000)
3855 retval = bulk_latency;
3856 else if ((packets < 5) && (bytes > 512))
3857 retval = low_latency;
3858 break;
3859 case low_latency: /* 50 usec aka 20000 ints/s */
3860 if (bytes > 10000) {
3861 /* this if handles the TSO accounting */
3862 if (bytes/packets > 8000) {
3863 retval = bulk_latency;
3864 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3865 retval = bulk_latency;
3866 } else if ((packets > 35)) {
3867 retval = lowest_latency;
3868 }
3869 } else if (bytes/packets > 2000) {
3870 retval = bulk_latency;
3871 } else if (packets <= 2 && bytes < 512) {
3872 retval = lowest_latency;
3873 }
3874 break;
3875 case bulk_latency: /* 250 usec aka 4000 ints/s */
3876 if (bytes > 25000) {
3877 if (packets > 35)
3878 retval = low_latency;
3879 } else if (bytes < 1500) {
3880 retval = low_latency;
3881 }
3882 break;
3883 }
3884
3885 update_itr_done:
3886 return retval;
3887 }
3888
3889 static void igb_set_itr(struct igb_adapter *adapter)
3890 {
3891 struct igb_q_vector *q_vector = adapter->q_vector[0];
3892 u16 current_itr;
3893 u32 new_itr = q_vector->itr_val;
3894
3895 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3896 if (adapter->link_speed != SPEED_1000) {
3897 current_itr = 0;
3898 new_itr = 4000;
3899 goto set_itr_now;
3900 }
3901
3902 adapter->rx_itr = igb_update_itr(adapter,
3903 adapter->rx_itr,
3904 q_vector->rx_ring->total_packets,
3905 q_vector->rx_ring->total_bytes);
3906
3907 adapter->tx_itr = igb_update_itr(adapter,
3908 adapter->tx_itr,
3909 q_vector->tx_ring->total_packets,
3910 q_vector->tx_ring->total_bytes);
3911 current_itr = max(adapter->rx_itr, adapter->tx_itr);
3912
3913 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3914 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
3915 current_itr = low_latency;
3916
3917 switch (current_itr) {
3918 /* counts and packets in update_itr are dependent on these numbers */
3919 case lowest_latency:
3920 new_itr = 56; /* aka 70,000 ints/sec */
3921 break;
3922 case low_latency:
3923 new_itr = 196; /* aka 20,000 ints/sec */
3924 break;
3925 case bulk_latency:
3926 new_itr = 980; /* aka 4,000 ints/sec */
3927 break;
3928 default:
3929 break;
3930 }
3931
3932 set_itr_now:
3933 q_vector->rx_ring->total_bytes = 0;
3934 q_vector->rx_ring->total_packets = 0;
3935 q_vector->tx_ring->total_bytes = 0;
3936 q_vector->tx_ring->total_packets = 0;
3937
3938 if (new_itr != q_vector->itr_val) {
3939 /* this attempts to bias the interrupt rate towards Bulk
3940 * by adding intermediate steps when interrupt rate is
3941 * increasing */
3942 new_itr = new_itr > q_vector->itr_val ?
3943 max((new_itr * q_vector->itr_val) /
3944 (new_itr + (q_vector->itr_val >> 2)),
3945 new_itr) :
3946 new_itr;
3947 /* Don't write the value here; it resets the adapter's
3948 * internal timer, and causes us to delay far longer than
3949 * we should between interrupts. Instead, we write the ITR
3950 * value at the beginning of the next interrupt so the timing
3951 * ends up being correct.
3952 */
3953 q_vector->itr_val = new_itr;
3954 q_vector->set_itr = 1;
3955 }
3956 }
3957
3958 #define IGB_TX_FLAGS_CSUM 0x00000001
3959 #define IGB_TX_FLAGS_VLAN 0x00000002
3960 #define IGB_TX_FLAGS_TSO 0x00000004
3961 #define IGB_TX_FLAGS_IPV4 0x00000008
3962 #define IGB_TX_FLAGS_TSTAMP 0x00000010
3963 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3964 #define IGB_TX_FLAGS_VLAN_SHIFT 16
3965
3966 void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3967 u32 type_tucmd, u32 mss_l4len_idx)
3968 {
3969 struct e1000_adv_tx_context_desc *context_desc;
3970 u16 i = tx_ring->next_to_use;
3971
3972 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3973
3974 i++;
3975 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3976
3977 /* set bits to identify this as an advanced context descriptor */
3978 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
3979
3980 /* For 82575, context index must be unique per ring. */
3981 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3982 mss_l4len_idx |= tx_ring->reg_idx << 4;
3983
3984 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3985 context_desc->seqnum_seed = 0;
3986 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
3987 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3988 }
3989
3990 static inline int igb_tso(struct igb_ring *tx_ring,
3991 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3992 {
3993 int err;
3994 u32 vlan_macip_lens, type_tucmd;
3995 u32 mss_l4len_idx, l4len;
3996
3997 if (!skb_is_gso(skb))
3998 return 0;
3999
4000 if (skb_header_cloned(skb)) {
4001 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4002 if (err)
4003 return err;
4004 }
4005
4006 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4007 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4008
4009 if (skb->protocol == htons(ETH_P_IP)) {
4010 struct iphdr *iph = ip_hdr(skb);
4011 iph->tot_len = 0;
4012 iph->check = 0;
4013 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4014 iph->daddr, 0,
4015 IPPROTO_TCP,
4016 0);
4017 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4018 } else if (skb_is_gso_v6(skb)) {
4019 ipv6_hdr(skb)->payload_len = 0;
4020 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4021 &ipv6_hdr(skb)->daddr,
4022 0, IPPROTO_TCP, 0);
4023 }
4024
4025 l4len = tcp_hdrlen(skb);
4026 *hdr_len = skb_transport_offset(skb) + l4len;
4027
4028 /* MSS L4LEN IDX */
4029 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4030 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4031
4032 /* VLAN MACLEN IPLEN */
4033 vlan_macip_lens = skb_network_header_len(skb);
4034 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4035 vlan_macip_lens |= tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4036
4037 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4038
4039 return 1;
4040 }
4041
4042 static inline bool igb_tx_csum(struct igb_ring *tx_ring,
4043 struct sk_buff *skb, u32 tx_flags)
4044 {
4045 u32 vlan_macip_lens = 0;
4046 u32 mss_l4len_idx = 0;
4047 u32 type_tucmd = 0;
4048
4049 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4050 if (!(tx_flags & IGB_TX_FLAGS_VLAN))
4051 return false;
4052 } else {
4053 u8 l4_hdr = 0;
4054 switch (skb->protocol) {
4055 case __constant_htons(ETH_P_IP):
4056 vlan_macip_lens |= skb_network_header_len(skb);
4057 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4058 l4_hdr = ip_hdr(skb)->protocol;
4059 break;
4060 case __constant_htons(ETH_P_IPV6):
4061 vlan_macip_lens |= skb_network_header_len(skb);
4062 l4_hdr = ipv6_hdr(skb)->nexthdr;
4063 break;
4064 default:
4065 if (unlikely(net_ratelimit())) {
4066 dev_warn(tx_ring->dev,
4067 "partial checksum but proto=%x!\n",
4068 skb->protocol);
4069 }
4070 break;
4071 }
4072
4073 switch (l4_hdr) {
4074 case IPPROTO_TCP:
4075 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4076 mss_l4len_idx = tcp_hdrlen(skb) <<
4077 E1000_ADVTXD_L4LEN_SHIFT;
4078 break;
4079 case IPPROTO_SCTP:
4080 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4081 mss_l4len_idx = sizeof(struct sctphdr) <<
4082 E1000_ADVTXD_L4LEN_SHIFT;
4083 break;
4084 case IPPROTO_UDP:
4085 mss_l4len_idx = sizeof(struct udphdr) <<
4086 E1000_ADVTXD_L4LEN_SHIFT;
4087 break;
4088 default:
4089 if (unlikely(net_ratelimit())) {
4090 dev_warn(tx_ring->dev,
4091 "partial checksum but l4 proto=%x!\n",
4092 l4_hdr);
4093 }
4094 break;
4095 }
4096 }
4097
4098 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4099 vlan_macip_lens |= tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4100
4101 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4102
4103 return (skb->ip_summed == CHECKSUM_PARTIAL);
4104 }
4105
4106 #define IGB_MAX_TXD_PWR 16
4107 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
4108
4109 static inline int igb_tx_map(struct igb_ring *tx_ring, struct sk_buff *skb,
4110 struct igb_tx_buffer *first)
4111 {
4112 struct igb_tx_buffer *buffer_info;
4113 struct device *dev = tx_ring->dev;
4114 unsigned int hlen = skb_headlen(skb);
4115 unsigned int count = 0, i;
4116 unsigned int f;
4117 u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
4118
4119 i = tx_ring->next_to_use;
4120
4121 buffer_info = &tx_ring->tx_buffer_info[i];
4122 BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD);
4123 buffer_info->length = hlen;
4124 buffer_info->dma = dma_map_single(dev, skb->data, hlen,
4125 DMA_TO_DEVICE);
4126 if (dma_mapping_error(dev, buffer_info->dma))
4127 goto dma_error;
4128
4129 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
4130 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f];
4131 unsigned int len = frag->size;
4132
4133 count++;
4134 i++;
4135 if (i == tx_ring->count)
4136 i = 0;
4137
4138 buffer_info = &tx_ring->tx_buffer_info[i];
4139 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
4140 buffer_info->length = len;
4141 buffer_info->mapped_as_page = true;
4142 buffer_info->dma = skb_frag_dma_map(dev, frag, 0, len,
4143 DMA_TO_DEVICE);
4144 if (dma_mapping_error(dev, buffer_info->dma))
4145 goto dma_error;
4146
4147 }
4148
4149 buffer_info->skb = skb;
4150 buffer_info->tx_flags = skb_shinfo(skb)->tx_flags;
4151 /* multiply data chunks by size of headers */
4152 buffer_info->bytecount = ((gso_segs - 1) * hlen) + skb->len;
4153 buffer_info->gso_segs = gso_segs;
4154
4155 /* set the timestamp */
4156 first->time_stamp = jiffies;
4157
4158 /* set next_to_watch value indicating a packet is present */
4159 first->next_to_watch = IGB_TX_DESC(tx_ring, i);
4160
4161 return ++count;
4162
4163 dma_error:
4164 dev_err(dev, "TX DMA map failed\n");
4165
4166 /* clear timestamp and dma mappings for failed buffer_info mapping */
4167 buffer_info->dma = 0;
4168 buffer_info->time_stamp = 0;
4169 buffer_info->length = 0;
4170 buffer_info->mapped_as_page = false;
4171
4172 /* clear timestamp and dma mappings for remaining portion of packet */
4173 while (count--) {
4174 if (i == 0)
4175 i = tx_ring->count;
4176 i--;
4177 buffer_info = &tx_ring->tx_buffer_info[i];
4178 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
4179 }
4180
4181 return 0;
4182 }
4183
4184 static inline void igb_tx_queue(struct igb_ring *tx_ring,
4185 u32 tx_flags, int count, u32 paylen,
4186 u8 hdr_len)
4187 {
4188 union e1000_adv_tx_desc *tx_desc;
4189 struct igb_tx_buffer *buffer_info;
4190 u32 olinfo_status = 0, cmd_type_len;
4191 unsigned int i = tx_ring->next_to_use;
4192
4193 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
4194 E1000_ADVTXD_DCMD_DEXT);
4195
4196 if (tx_flags & IGB_TX_FLAGS_VLAN)
4197 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
4198
4199 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
4200 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
4201
4202 if (tx_flags & IGB_TX_FLAGS_TSO) {
4203 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
4204
4205 /* insert tcp checksum */
4206 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4207
4208 /* insert ip checksum */
4209 if (tx_flags & IGB_TX_FLAGS_IPV4)
4210 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4211
4212 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
4213 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4214 }
4215
4216 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
4217 (tx_flags & (IGB_TX_FLAGS_CSUM |
4218 IGB_TX_FLAGS_TSO |
4219 IGB_TX_FLAGS_VLAN)))
4220 olinfo_status |= tx_ring->reg_idx << 4;
4221
4222 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
4223
4224 do {
4225 buffer_info = &tx_ring->tx_buffer_info[i];
4226 tx_desc = IGB_TX_DESC(tx_ring, i);
4227 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
4228 tx_desc->read.cmd_type_len =
4229 cpu_to_le32(cmd_type_len | buffer_info->length);
4230 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4231 count--;
4232 i++;
4233 if (i == tx_ring->count)
4234 i = 0;
4235 } while (count > 0);
4236
4237 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
4238 /* Force memory writes to complete before letting h/w
4239 * know there are new descriptors to fetch. (Only
4240 * applicable for weak-ordered memory model archs,
4241 * such as IA-64). */
4242 wmb();
4243
4244 tx_ring->next_to_use = i;
4245 writel(i, tx_ring->tail);
4246 /* we need this if more than one processor can write to our tail
4247 * at a time, it syncronizes IO on IA64/Altix systems */
4248 mmiowb();
4249 }
4250
4251 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
4252 {
4253 struct net_device *netdev = tx_ring->netdev;
4254
4255 netif_stop_subqueue(netdev, tx_ring->queue_index);
4256
4257 /* Herbert's original patch had:
4258 * smp_mb__after_netif_stop_queue();
4259 * but since that doesn't exist yet, just open code it. */
4260 smp_mb();
4261
4262 /* We need to check again in a case another CPU has just
4263 * made room available. */
4264 if (igb_desc_unused(tx_ring) < size)
4265 return -EBUSY;
4266
4267 /* A reprieve! */
4268 netif_wake_subqueue(netdev, tx_ring->queue_index);
4269
4270 u64_stats_update_begin(&tx_ring->tx_syncp2);
4271 tx_ring->tx_stats.restart_queue2++;
4272 u64_stats_update_end(&tx_ring->tx_syncp2);
4273
4274 return 0;
4275 }
4276
4277 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
4278 {
4279 if (igb_desc_unused(tx_ring) >= size)
4280 return 0;
4281 return __igb_maybe_stop_tx(tx_ring, size);
4282 }
4283
4284 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4285 struct igb_ring *tx_ring)
4286 {
4287 struct igb_tx_buffer *first;
4288 int tso, count;
4289 u32 tx_flags = 0;
4290 u8 hdr_len = 0;
4291
4292 /* need: 1 descriptor per page,
4293 * + 2 desc gap to keep tail from touching head,
4294 * + 1 desc for skb->data,
4295 * + 1 desc for context descriptor,
4296 * otherwise try next time */
4297 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
4298 /* this is a hard error */
4299 return NETDEV_TX_BUSY;
4300 }
4301
4302 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4303 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4304 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4305 }
4306
4307 if (vlan_tx_tag_present(skb)) {
4308 tx_flags |= IGB_TX_FLAGS_VLAN;
4309 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4310 }
4311
4312 if (skb->protocol == htons(ETH_P_IP))
4313 tx_flags |= IGB_TX_FLAGS_IPV4;
4314
4315 /* record the location of the first descriptor for this packet */
4316 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4317
4318 tso = igb_tso(tx_ring, skb, tx_flags, &hdr_len);
4319
4320 if (tso < 0)
4321 goto out_drop;
4322 else if (tso)
4323 tx_flags |= IGB_TX_FLAGS_TSO;
4324 else if (igb_tx_csum(tx_ring, skb, tx_flags) &&
4325 (skb->ip_summed == CHECKSUM_PARTIAL))
4326 tx_flags |= IGB_TX_FLAGS_CSUM;
4327
4328 /*
4329 * count reflects descriptors mapped, if 0 or less then mapping error
4330 * has occurred and we need to rewind the descriptor queue
4331 */
4332 count = igb_tx_map(tx_ring, skb, first);
4333 if (!count) {
4334 dev_kfree_skb_any(skb);
4335 first->time_stamp = 0;
4336 tx_ring->next_to_use = first - tx_ring->tx_buffer_info;
4337 return NETDEV_TX_OK;
4338 }
4339
4340 igb_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
4341
4342 /* Make sure there is space in the ring for the next send. */
4343 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
4344
4345 return NETDEV_TX_OK;
4346
4347 out_drop:
4348 dev_kfree_skb_any(skb);
4349 return NETDEV_TX_OK;
4350 }
4351
4352 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4353 struct sk_buff *skb)
4354 {
4355 unsigned int r_idx = skb->queue_mapping;
4356
4357 if (r_idx >= adapter->num_tx_queues)
4358 r_idx = r_idx % adapter->num_tx_queues;
4359
4360 return adapter->tx_ring[r_idx];
4361 }
4362
4363 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4364 struct net_device *netdev)
4365 {
4366 struct igb_adapter *adapter = netdev_priv(netdev);
4367
4368 if (test_bit(__IGB_DOWN, &adapter->state)) {
4369 dev_kfree_skb_any(skb);
4370 return NETDEV_TX_OK;
4371 }
4372
4373 if (skb->len <= 0) {
4374 dev_kfree_skb_any(skb);
4375 return NETDEV_TX_OK;
4376 }
4377
4378 /*
4379 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4380 * in order to meet this minimum size requirement.
4381 */
4382 if (skb->len < 17) {
4383 if (skb_padto(skb, 17))
4384 return NETDEV_TX_OK;
4385 skb->len = 17;
4386 }
4387
4388 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4389 }
4390
4391 /**
4392 * igb_tx_timeout - Respond to a Tx Hang
4393 * @netdev: network interface device structure
4394 **/
4395 static void igb_tx_timeout(struct net_device *netdev)
4396 {
4397 struct igb_adapter *adapter = netdev_priv(netdev);
4398 struct e1000_hw *hw = &adapter->hw;
4399
4400 /* Do the reset outside of interrupt context */
4401 adapter->tx_timeout_count++;
4402
4403 if (hw->mac.type == e1000_82580)
4404 hw->dev_spec._82575.global_device_reset = true;
4405
4406 schedule_work(&adapter->reset_task);
4407 wr32(E1000_EICS,
4408 (adapter->eims_enable_mask & ~adapter->eims_other));
4409 }
4410
4411 static void igb_reset_task(struct work_struct *work)
4412 {
4413 struct igb_adapter *adapter;
4414 adapter = container_of(work, struct igb_adapter, reset_task);
4415
4416 igb_dump(adapter);
4417 netdev_err(adapter->netdev, "Reset adapter\n");
4418 igb_reinit_locked(adapter);
4419 }
4420
4421 /**
4422 * igb_get_stats64 - Get System Network Statistics
4423 * @netdev: network interface device structure
4424 * @stats: rtnl_link_stats64 pointer
4425 *
4426 **/
4427 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4428 struct rtnl_link_stats64 *stats)
4429 {
4430 struct igb_adapter *adapter = netdev_priv(netdev);
4431
4432 spin_lock(&adapter->stats64_lock);
4433 igb_update_stats(adapter, &adapter->stats64);
4434 memcpy(stats, &adapter->stats64, sizeof(*stats));
4435 spin_unlock(&adapter->stats64_lock);
4436
4437 return stats;
4438 }
4439
4440 /**
4441 * igb_change_mtu - Change the Maximum Transfer Unit
4442 * @netdev: network interface device structure
4443 * @new_mtu: new value for maximum frame size
4444 *
4445 * Returns 0 on success, negative on failure
4446 **/
4447 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4448 {
4449 struct igb_adapter *adapter = netdev_priv(netdev);
4450 struct pci_dev *pdev = adapter->pdev;
4451 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4452
4453 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4454 dev_err(&pdev->dev, "Invalid MTU setting\n");
4455 return -EINVAL;
4456 }
4457
4458 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4459 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4460 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4461 return -EINVAL;
4462 }
4463
4464 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4465 msleep(1);
4466
4467 /* igb_down has a dependency on max_frame_size */
4468 adapter->max_frame_size = max_frame;
4469
4470 if (netif_running(netdev))
4471 igb_down(adapter);
4472
4473 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4474 netdev->mtu, new_mtu);
4475 netdev->mtu = new_mtu;
4476
4477 if (netif_running(netdev))
4478 igb_up(adapter);
4479 else
4480 igb_reset(adapter);
4481
4482 clear_bit(__IGB_RESETTING, &adapter->state);
4483
4484 return 0;
4485 }
4486
4487 /**
4488 * igb_update_stats - Update the board statistics counters
4489 * @adapter: board private structure
4490 **/
4491
4492 void igb_update_stats(struct igb_adapter *adapter,
4493 struct rtnl_link_stats64 *net_stats)
4494 {
4495 struct e1000_hw *hw = &adapter->hw;
4496 struct pci_dev *pdev = adapter->pdev;
4497 u32 reg, mpc;
4498 u16 phy_tmp;
4499 int i;
4500 u64 bytes, packets;
4501 unsigned int start;
4502 u64 _bytes, _packets;
4503
4504 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4505
4506 /*
4507 * Prevent stats update while adapter is being reset, or if the pci
4508 * connection is down.
4509 */
4510 if (adapter->link_speed == 0)
4511 return;
4512 if (pci_channel_offline(pdev))
4513 return;
4514
4515 bytes = 0;
4516 packets = 0;
4517 for (i = 0; i < adapter->num_rx_queues; i++) {
4518 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
4519 struct igb_ring *ring = adapter->rx_ring[i];
4520
4521 ring->rx_stats.drops += rqdpc_tmp;
4522 net_stats->rx_fifo_errors += rqdpc_tmp;
4523
4524 do {
4525 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4526 _bytes = ring->rx_stats.bytes;
4527 _packets = ring->rx_stats.packets;
4528 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4529 bytes += _bytes;
4530 packets += _packets;
4531 }
4532
4533 net_stats->rx_bytes = bytes;
4534 net_stats->rx_packets = packets;
4535
4536 bytes = 0;
4537 packets = 0;
4538 for (i = 0; i < adapter->num_tx_queues; i++) {
4539 struct igb_ring *ring = adapter->tx_ring[i];
4540 do {
4541 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4542 _bytes = ring->tx_stats.bytes;
4543 _packets = ring->tx_stats.packets;
4544 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4545 bytes += _bytes;
4546 packets += _packets;
4547 }
4548 net_stats->tx_bytes = bytes;
4549 net_stats->tx_packets = packets;
4550
4551 /* read stats registers */
4552 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4553 adapter->stats.gprc += rd32(E1000_GPRC);
4554 adapter->stats.gorc += rd32(E1000_GORCL);
4555 rd32(E1000_GORCH); /* clear GORCL */
4556 adapter->stats.bprc += rd32(E1000_BPRC);
4557 adapter->stats.mprc += rd32(E1000_MPRC);
4558 adapter->stats.roc += rd32(E1000_ROC);
4559
4560 adapter->stats.prc64 += rd32(E1000_PRC64);
4561 adapter->stats.prc127 += rd32(E1000_PRC127);
4562 adapter->stats.prc255 += rd32(E1000_PRC255);
4563 adapter->stats.prc511 += rd32(E1000_PRC511);
4564 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4565 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4566 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4567 adapter->stats.sec += rd32(E1000_SEC);
4568
4569 mpc = rd32(E1000_MPC);
4570 adapter->stats.mpc += mpc;
4571 net_stats->rx_fifo_errors += mpc;
4572 adapter->stats.scc += rd32(E1000_SCC);
4573 adapter->stats.ecol += rd32(E1000_ECOL);
4574 adapter->stats.mcc += rd32(E1000_MCC);
4575 adapter->stats.latecol += rd32(E1000_LATECOL);
4576 adapter->stats.dc += rd32(E1000_DC);
4577 adapter->stats.rlec += rd32(E1000_RLEC);
4578 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4579 adapter->stats.xontxc += rd32(E1000_XONTXC);
4580 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4581 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4582 adapter->stats.fcruc += rd32(E1000_FCRUC);
4583 adapter->stats.gptc += rd32(E1000_GPTC);
4584 adapter->stats.gotc += rd32(E1000_GOTCL);
4585 rd32(E1000_GOTCH); /* clear GOTCL */
4586 adapter->stats.rnbc += rd32(E1000_RNBC);
4587 adapter->stats.ruc += rd32(E1000_RUC);
4588 adapter->stats.rfc += rd32(E1000_RFC);
4589 adapter->stats.rjc += rd32(E1000_RJC);
4590 adapter->stats.tor += rd32(E1000_TORH);
4591 adapter->stats.tot += rd32(E1000_TOTH);
4592 adapter->stats.tpr += rd32(E1000_TPR);
4593
4594 adapter->stats.ptc64 += rd32(E1000_PTC64);
4595 adapter->stats.ptc127 += rd32(E1000_PTC127);
4596 adapter->stats.ptc255 += rd32(E1000_PTC255);
4597 adapter->stats.ptc511 += rd32(E1000_PTC511);
4598 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4599 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4600
4601 adapter->stats.mptc += rd32(E1000_MPTC);
4602 adapter->stats.bptc += rd32(E1000_BPTC);
4603
4604 adapter->stats.tpt += rd32(E1000_TPT);
4605 adapter->stats.colc += rd32(E1000_COLC);
4606
4607 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4608 /* read internal phy specific stats */
4609 reg = rd32(E1000_CTRL_EXT);
4610 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4611 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4612 adapter->stats.tncrs += rd32(E1000_TNCRS);
4613 }
4614
4615 adapter->stats.tsctc += rd32(E1000_TSCTC);
4616 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4617
4618 adapter->stats.iac += rd32(E1000_IAC);
4619 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4620 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4621 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4622 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4623 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4624 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4625 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4626 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4627
4628 /* Fill out the OS statistics structure */
4629 net_stats->multicast = adapter->stats.mprc;
4630 net_stats->collisions = adapter->stats.colc;
4631
4632 /* Rx Errors */
4633
4634 /* RLEC on some newer hardware can be incorrect so build
4635 * our own version based on RUC and ROC */
4636 net_stats->rx_errors = adapter->stats.rxerrc +
4637 adapter->stats.crcerrs + adapter->stats.algnerrc +
4638 adapter->stats.ruc + adapter->stats.roc +
4639 adapter->stats.cexterr;
4640 net_stats->rx_length_errors = adapter->stats.ruc +
4641 adapter->stats.roc;
4642 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4643 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4644 net_stats->rx_missed_errors = adapter->stats.mpc;
4645
4646 /* Tx Errors */
4647 net_stats->tx_errors = adapter->stats.ecol +
4648 adapter->stats.latecol;
4649 net_stats->tx_aborted_errors = adapter->stats.ecol;
4650 net_stats->tx_window_errors = adapter->stats.latecol;
4651 net_stats->tx_carrier_errors = adapter->stats.tncrs;
4652
4653 /* Tx Dropped needs to be maintained elsewhere */
4654
4655 /* Phy Stats */
4656 if (hw->phy.media_type == e1000_media_type_copper) {
4657 if ((adapter->link_speed == SPEED_1000) &&
4658 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4659 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4660 adapter->phy_stats.idle_errors += phy_tmp;
4661 }
4662 }
4663
4664 /* Management Stats */
4665 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4666 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4667 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4668
4669 /* OS2BMC Stats */
4670 reg = rd32(E1000_MANC);
4671 if (reg & E1000_MANC_EN_BMC2OS) {
4672 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4673 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4674 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4675 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4676 }
4677 }
4678
4679 static irqreturn_t igb_msix_other(int irq, void *data)
4680 {
4681 struct igb_adapter *adapter = data;
4682 struct e1000_hw *hw = &adapter->hw;
4683 u32 icr = rd32(E1000_ICR);
4684 /* reading ICR causes bit 31 of EICR to be cleared */
4685
4686 if (icr & E1000_ICR_DRSTA)
4687 schedule_work(&adapter->reset_task);
4688
4689 if (icr & E1000_ICR_DOUTSYNC) {
4690 /* HW is reporting DMA is out of sync */
4691 adapter->stats.doosync++;
4692 /* The DMA Out of Sync is also indication of a spoof event
4693 * in IOV mode. Check the Wrong VM Behavior register to
4694 * see if it is really a spoof event. */
4695 igb_check_wvbr(adapter);
4696 }
4697
4698 /* Check for a mailbox event */
4699 if (icr & E1000_ICR_VMMB)
4700 igb_msg_task(adapter);
4701
4702 if (icr & E1000_ICR_LSC) {
4703 hw->mac.get_link_status = 1;
4704 /* guard against interrupt when we're going down */
4705 if (!test_bit(__IGB_DOWN, &adapter->state))
4706 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4707 }
4708
4709 if (adapter->vfs_allocated_count)
4710 wr32(E1000_IMS, E1000_IMS_LSC |
4711 E1000_IMS_VMMB |
4712 E1000_IMS_DOUTSYNC);
4713 else
4714 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
4715 wr32(E1000_EIMS, adapter->eims_other);
4716
4717 return IRQ_HANDLED;
4718 }
4719
4720 static void igb_write_itr(struct igb_q_vector *q_vector)
4721 {
4722 struct igb_adapter *adapter = q_vector->adapter;
4723 u32 itr_val = q_vector->itr_val & 0x7FFC;
4724
4725 if (!q_vector->set_itr)
4726 return;
4727
4728 if (!itr_val)
4729 itr_val = 0x4;
4730
4731 if (adapter->hw.mac.type == e1000_82575)
4732 itr_val |= itr_val << 16;
4733 else
4734 itr_val |= 0x8000000;
4735
4736 writel(itr_val, q_vector->itr_register);
4737 q_vector->set_itr = 0;
4738 }
4739
4740 static irqreturn_t igb_msix_ring(int irq, void *data)
4741 {
4742 struct igb_q_vector *q_vector = data;
4743
4744 /* Write the ITR value calculated from the previous interrupt. */
4745 igb_write_itr(q_vector);
4746
4747 napi_schedule(&q_vector->napi);
4748
4749 return IRQ_HANDLED;
4750 }
4751
4752 #ifdef CONFIG_IGB_DCA
4753 static void igb_update_dca(struct igb_q_vector *q_vector)
4754 {
4755 struct igb_adapter *adapter = q_vector->adapter;
4756 struct e1000_hw *hw = &adapter->hw;
4757 int cpu = get_cpu();
4758
4759 if (q_vector->cpu == cpu)
4760 goto out_no_update;
4761
4762 if (q_vector->tx_ring) {
4763 int q = q_vector->tx_ring->reg_idx;
4764 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4765 if (hw->mac.type == e1000_82575) {
4766 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4767 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
4768 } else {
4769 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4770 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4771 E1000_DCA_TXCTRL_CPUID_SHIFT;
4772 }
4773 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4774 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4775 }
4776 if (q_vector->rx_ring) {
4777 int q = q_vector->rx_ring->reg_idx;
4778 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4779 if (hw->mac.type == e1000_82575) {
4780 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
4781 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
4782 } else {
4783 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4784 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4785 E1000_DCA_RXCTRL_CPUID_SHIFT;
4786 }
4787 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4788 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4789 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4790 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
4791 }
4792 q_vector->cpu = cpu;
4793 out_no_update:
4794 put_cpu();
4795 }
4796
4797 static void igb_setup_dca(struct igb_adapter *adapter)
4798 {
4799 struct e1000_hw *hw = &adapter->hw;
4800 int i;
4801
4802 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
4803 return;
4804
4805 /* Always use CB2 mode, difference is masked in the CB driver. */
4806 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4807
4808 for (i = 0; i < adapter->num_q_vectors; i++) {
4809 adapter->q_vector[i]->cpu = -1;
4810 igb_update_dca(adapter->q_vector[i]);
4811 }
4812 }
4813
4814 static int __igb_notify_dca(struct device *dev, void *data)
4815 {
4816 struct net_device *netdev = dev_get_drvdata(dev);
4817 struct igb_adapter *adapter = netdev_priv(netdev);
4818 struct pci_dev *pdev = adapter->pdev;
4819 struct e1000_hw *hw = &adapter->hw;
4820 unsigned long event = *(unsigned long *)data;
4821
4822 switch (event) {
4823 case DCA_PROVIDER_ADD:
4824 /* if already enabled, don't do it again */
4825 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4826 break;
4827 if (dca_add_requester(dev) == 0) {
4828 adapter->flags |= IGB_FLAG_DCA_ENABLED;
4829 dev_info(&pdev->dev, "DCA enabled\n");
4830 igb_setup_dca(adapter);
4831 break;
4832 }
4833 /* Fall Through since DCA is disabled. */
4834 case DCA_PROVIDER_REMOVE:
4835 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
4836 /* without this a class_device is left
4837 * hanging around in the sysfs model */
4838 dca_remove_requester(dev);
4839 dev_info(&pdev->dev, "DCA disabled\n");
4840 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
4841 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
4842 }
4843 break;
4844 }
4845
4846 return 0;
4847 }
4848
4849 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4850 void *p)
4851 {
4852 int ret_val;
4853
4854 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4855 __igb_notify_dca);
4856
4857 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4858 }
4859 #endif /* CONFIG_IGB_DCA */
4860
4861 static void igb_ping_all_vfs(struct igb_adapter *adapter)
4862 {
4863 struct e1000_hw *hw = &adapter->hw;
4864 u32 ping;
4865 int i;
4866
4867 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4868 ping = E1000_PF_CONTROL_MSG;
4869 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4870 ping |= E1000_VT_MSGTYPE_CTS;
4871 igb_write_mbx(hw, &ping, 1, i);
4872 }
4873 }
4874
4875 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4876 {
4877 struct e1000_hw *hw = &adapter->hw;
4878 u32 vmolr = rd32(E1000_VMOLR(vf));
4879 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4880
4881 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
4882 IGB_VF_FLAG_MULTI_PROMISC);
4883 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4884
4885 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4886 vmolr |= E1000_VMOLR_MPME;
4887 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
4888 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4889 } else {
4890 /*
4891 * if we have hashes and we are clearing a multicast promisc
4892 * flag we need to write the hashes to the MTA as this step
4893 * was previously skipped
4894 */
4895 if (vf_data->num_vf_mc_hashes > 30) {
4896 vmolr |= E1000_VMOLR_MPME;
4897 } else if (vf_data->num_vf_mc_hashes) {
4898 int j;
4899 vmolr |= E1000_VMOLR_ROMPE;
4900 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4901 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4902 }
4903 }
4904
4905 wr32(E1000_VMOLR(vf), vmolr);
4906
4907 /* there are flags left unprocessed, likely not supported */
4908 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4909 return -EINVAL;
4910
4911 return 0;
4912
4913 }
4914
4915 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4916 u32 *msgbuf, u32 vf)
4917 {
4918 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4919 u16 *hash_list = (u16 *)&msgbuf[1];
4920 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4921 int i;
4922
4923 /* salt away the number of multicast addresses assigned
4924 * to this VF for later use to restore when the PF multi cast
4925 * list changes
4926 */
4927 vf_data->num_vf_mc_hashes = n;
4928
4929 /* only up to 30 hash values supported */
4930 if (n > 30)
4931 n = 30;
4932
4933 /* store the hashes for later use */
4934 for (i = 0; i < n; i++)
4935 vf_data->vf_mc_hashes[i] = hash_list[i];
4936
4937 /* Flush and reset the mta with the new values */
4938 igb_set_rx_mode(adapter->netdev);
4939
4940 return 0;
4941 }
4942
4943 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4944 {
4945 struct e1000_hw *hw = &adapter->hw;
4946 struct vf_data_storage *vf_data;
4947 int i, j;
4948
4949 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4950 u32 vmolr = rd32(E1000_VMOLR(i));
4951 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4952
4953 vf_data = &adapter->vf_data[i];
4954
4955 if ((vf_data->num_vf_mc_hashes > 30) ||
4956 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4957 vmolr |= E1000_VMOLR_MPME;
4958 } else if (vf_data->num_vf_mc_hashes) {
4959 vmolr |= E1000_VMOLR_ROMPE;
4960 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4961 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4962 }
4963 wr32(E1000_VMOLR(i), vmolr);
4964 }
4965 }
4966
4967 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4968 {
4969 struct e1000_hw *hw = &adapter->hw;
4970 u32 pool_mask, reg, vid;
4971 int i;
4972
4973 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4974
4975 /* Find the vlan filter for this id */
4976 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4977 reg = rd32(E1000_VLVF(i));
4978
4979 /* remove the vf from the pool */
4980 reg &= ~pool_mask;
4981
4982 /* if pool is empty then remove entry from vfta */
4983 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4984 (reg & E1000_VLVF_VLANID_ENABLE)) {
4985 reg = 0;
4986 vid = reg & E1000_VLVF_VLANID_MASK;
4987 igb_vfta_set(hw, vid, false);
4988 }
4989
4990 wr32(E1000_VLVF(i), reg);
4991 }
4992
4993 adapter->vf_data[vf].vlans_enabled = 0;
4994 }
4995
4996 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4997 {
4998 struct e1000_hw *hw = &adapter->hw;
4999 u32 reg, i;
5000
5001 /* The vlvf table only exists on 82576 hardware and newer */
5002 if (hw->mac.type < e1000_82576)
5003 return -1;
5004
5005 /* we only need to do this if VMDq is enabled */
5006 if (!adapter->vfs_allocated_count)
5007 return -1;
5008
5009 /* Find the vlan filter for this id */
5010 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5011 reg = rd32(E1000_VLVF(i));
5012 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5013 vid == (reg & E1000_VLVF_VLANID_MASK))
5014 break;
5015 }
5016
5017 if (add) {
5018 if (i == E1000_VLVF_ARRAY_SIZE) {
5019 /* Did not find a matching VLAN ID entry that was
5020 * enabled. Search for a free filter entry, i.e.
5021 * one without the enable bit set
5022 */
5023 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5024 reg = rd32(E1000_VLVF(i));
5025 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5026 break;
5027 }
5028 }
5029 if (i < E1000_VLVF_ARRAY_SIZE) {
5030 /* Found an enabled/available entry */
5031 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5032
5033 /* if !enabled we need to set this up in vfta */
5034 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5035 /* add VID to filter table */
5036 igb_vfta_set(hw, vid, true);
5037 reg |= E1000_VLVF_VLANID_ENABLE;
5038 }
5039 reg &= ~E1000_VLVF_VLANID_MASK;
5040 reg |= vid;
5041 wr32(E1000_VLVF(i), reg);
5042
5043 /* do not modify RLPML for PF devices */
5044 if (vf >= adapter->vfs_allocated_count)
5045 return 0;
5046
5047 if (!adapter->vf_data[vf].vlans_enabled) {
5048 u32 size;
5049 reg = rd32(E1000_VMOLR(vf));
5050 size = reg & E1000_VMOLR_RLPML_MASK;
5051 size += 4;
5052 reg &= ~E1000_VMOLR_RLPML_MASK;
5053 reg |= size;
5054 wr32(E1000_VMOLR(vf), reg);
5055 }
5056
5057 adapter->vf_data[vf].vlans_enabled++;
5058 return 0;
5059 }
5060 } else {
5061 if (i < E1000_VLVF_ARRAY_SIZE) {
5062 /* remove vf from the pool */
5063 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5064 /* if pool is empty then remove entry from vfta */
5065 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5066 reg = 0;
5067 igb_vfta_set(hw, vid, false);
5068 }
5069 wr32(E1000_VLVF(i), reg);
5070
5071 /* do not modify RLPML for PF devices */
5072 if (vf >= adapter->vfs_allocated_count)
5073 return 0;
5074
5075 adapter->vf_data[vf].vlans_enabled--;
5076 if (!adapter->vf_data[vf].vlans_enabled) {
5077 u32 size;
5078 reg = rd32(E1000_VMOLR(vf));
5079 size = reg & E1000_VMOLR_RLPML_MASK;
5080 size -= 4;
5081 reg &= ~E1000_VMOLR_RLPML_MASK;
5082 reg |= size;
5083 wr32(E1000_VMOLR(vf), reg);
5084 }
5085 }
5086 }
5087 return 0;
5088 }
5089
5090 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5091 {
5092 struct e1000_hw *hw = &adapter->hw;
5093
5094 if (vid)
5095 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5096 else
5097 wr32(E1000_VMVIR(vf), 0);
5098 }
5099
5100 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5101 int vf, u16 vlan, u8 qos)
5102 {
5103 int err = 0;
5104 struct igb_adapter *adapter = netdev_priv(netdev);
5105
5106 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5107 return -EINVAL;
5108 if (vlan || qos) {
5109 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5110 if (err)
5111 goto out;
5112 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5113 igb_set_vmolr(adapter, vf, !vlan);
5114 adapter->vf_data[vf].pf_vlan = vlan;
5115 adapter->vf_data[vf].pf_qos = qos;
5116 dev_info(&adapter->pdev->dev,
5117 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5118 if (test_bit(__IGB_DOWN, &adapter->state)) {
5119 dev_warn(&adapter->pdev->dev,
5120 "The VF VLAN has been set,"
5121 " but the PF device is not up.\n");
5122 dev_warn(&adapter->pdev->dev,
5123 "Bring the PF device up before"
5124 " attempting to use the VF device.\n");
5125 }
5126 } else {
5127 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5128 false, vf);
5129 igb_set_vmvir(adapter, vlan, vf);
5130 igb_set_vmolr(adapter, vf, true);
5131 adapter->vf_data[vf].pf_vlan = 0;
5132 adapter->vf_data[vf].pf_qos = 0;
5133 }
5134 out:
5135 return err;
5136 }
5137
5138 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5139 {
5140 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5141 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5142
5143 return igb_vlvf_set(adapter, vid, add, vf);
5144 }
5145
5146 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5147 {
5148 /* clear flags - except flag that indicates PF has set the MAC */
5149 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5150 adapter->vf_data[vf].last_nack = jiffies;
5151
5152 /* reset offloads to defaults */
5153 igb_set_vmolr(adapter, vf, true);
5154
5155 /* reset vlans for device */
5156 igb_clear_vf_vfta(adapter, vf);
5157 if (adapter->vf_data[vf].pf_vlan)
5158 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5159 adapter->vf_data[vf].pf_vlan,
5160 adapter->vf_data[vf].pf_qos);
5161 else
5162 igb_clear_vf_vfta(adapter, vf);
5163
5164 /* reset multicast table array for vf */
5165 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5166
5167 /* Flush and reset the mta with the new values */
5168 igb_set_rx_mode(adapter->netdev);
5169 }
5170
5171 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5172 {
5173 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5174
5175 /* generate a new mac address as we were hotplug removed/added */
5176 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5177 random_ether_addr(vf_mac);
5178
5179 /* process remaining reset events */
5180 igb_vf_reset(adapter, vf);
5181 }
5182
5183 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5184 {
5185 struct e1000_hw *hw = &adapter->hw;
5186 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5187 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5188 u32 reg, msgbuf[3];
5189 u8 *addr = (u8 *)(&msgbuf[1]);
5190
5191 /* process all the same items cleared in a function level reset */
5192 igb_vf_reset(adapter, vf);
5193
5194 /* set vf mac address */
5195 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5196
5197 /* enable transmit and receive for vf */
5198 reg = rd32(E1000_VFTE);
5199 wr32(E1000_VFTE, reg | (1 << vf));
5200 reg = rd32(E1000_VFRE);
5201 wr32(E1000_VFRE, reg | (1 << vf));
5202
5203 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5204
5205 /* reply to reset with ack and vf mac address */
5206 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5207 memcpy(addr, vf_mac, 6);
5208 igb_write_mbx(hw, msgbuf, 3, vf);
5209 }
5210
5211 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5212 {
5213 /*
5214 * The VF MAC Address is stored in a packed array of bytes
5215 * starting at the second 32 bit word of the msg array
5216 */
5217 unsigned char *addr = (char *)&msg[1];
5218 int err = -1;
5219
5220 if (is_valid_ether_addr(addr))
5221 err = igb_set_vf_mac(adapter, vf, addr);
5222
5223 return err;
5224 }
5225
5226 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5227 {
5228 struct e1000_hw *hw = &adapter->hw;
5229 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5230 u32 msg = E1000_VT_MSGTYPE_NACK;
5231
5232 /* if device isn't clear to send it shouldn't be reading either */
5233 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5234 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5235 igb_write_mbx(hw, &msg, 1, vf);
5236 vf_data->last_nack = jiffies;
5237 }
5238 }
5239
5240 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5241 {
5242 struct pci_dev *pdev = adapter->pdev;
5243 u32 msgbuf[E1000_VFMAILBOX_SIZE];
5244 struct e1000_hw *hw = &adapter->hw;
5245 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5246 s32 retval;
5247
5248 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5249
5250 if (retval) {
5251 /* if receive failed revoke VF CTS stats and restart init */
5252 dev_err(&pdev->dev, "Error receiving message from VF\n");
5253 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5254 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5255 return;
5256 goto out;
5257 }
5258
5259 /* this is a message we already processed, do nothing */
5260 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5261 return;
5262
5263 /*
5264 * until the vf completes a reset it should not be
5265 * allowed to start any configuration.
5266 */
5267
5268 if (msgbuf[0] == E1000_VF_RESET) {
5269 igb_vf_reset_msg(adapter, vf);
5270 return;
5271 }
5272
5273 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5274 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5275 return;
5276 retval = -1;
5277 goto out;
5278 }
5279
5280 switch ((msgbuf[0] & 0xFFFF)) {
5281 case E1000_VF_SET_MAC_ADDR:
5282 retval = -EINVAL;
5283 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5284 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5285 else
5286 dev_warn(&pdev->dev,
5287 "VF %d attempted to override administratively "
5288 "set MAC address\nReload the VF driver to "
5289 "resume operations\n", vf);
5290 break;
5291 case E1000_VF_SET_PROMISC:
5292 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5293 break;
5294 case E1000_VF_SET_MULTICAST:
5295 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5296 break;
5297 case E1000_VF_SET_LPE:
5298 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5299 break;
5300 case E1000_VF_SET_VLAN:
5301 retval = -1;
5302 if (vf_data->pf_vlan)
5303 dev_warn(&pdev->dev,
5304 "VF %d attempted to override administratively "
5305 "set VLAN tag\nReload the VF driver to "
5306 "resume operations\n", vf);
5307 else
5308 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5309 break;
5310 default:
5311 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5312 retval = -1;
5313 break;
5314 }
5315
5316 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5317 out:
5318 /* notify the VF of the results of what it sent us */
5319 if (retval)
5320 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5321 else
5322 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5323
5324 igb_write_mbx(hw, msgbuf, 1, vf);
5325 }
5326
5327 static void igb_msg_task(struct igb_adapter *adapter)
5328 {
5329 struct e1000_hw *hw = &adapter->hw;
5330 u32 vf;
5331
5332 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5333 /* process any reset requests */
5334 if (!igb_check_for_rst(hw, vf))
5335 igb_vf_reset_event(adapter, vf);
5336
5337 /* process any messages pending */
5338 if (!igb_check_for_msg(hw, vf))
5339 igb_rcv_msg_from_vf(adapter, vf);
5340
5341 /* process any acks */
5342 if (!igb_check_for_ack(hw, vf))
5343 igb_rcv_ack_from_vf(adapter, vf);
5344 }
5345 }
5346
5347 /**
5348 * igb_set_uta - Set unicast filter table address
5349 * @adapter: board private structure
5350 *
5351 * The unicast table address is a register array of 32-bit registers.
5352 * The table is meant to be used in a way similar to how the MTA is used
5353 * however due to certain limitations in the hardware it is necessary to
5354 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5355 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
5356 **/
5357 static void igb_set_uta(struct igb_adapter *adapter)
5358 {
5359 struct e1000_hw *hw = &adapter->hw;
5360 int i;
5361
5362 /* The UTA table only exists on 82576 hardware and newer */
5363 if (hw->mac.type < e1000_82576)
5364 return;
5365
5366 /* we only need to do this if VMDq is enabled */
5367 if (!adapter->vfs_allocated_count)
5368 return;
5369
5370 for (i = 0; i < hw->mac.uta_reg_count; i++)
5371 array_wr32(E1000_UTA, i, ~0);
5372 }
5373
5374 /**
5375 * igb_intr_msi - Interrupt Handler
5376 * @irq: interrupt number
5377 * @data: pointer to a network interface device structure
5378 **/
5379 static irqreturn_t igb_intr_msi(int irq, void *data)
5380 {
5381 struct igb_adapter *adapter = data;
5382 struct igb_q_vector *q_vector = adapter->q_vector[0];
5383 struct e1000_hw *hw = &adapter->hw;
5384 /* read ICR disables interrupts using IAM */
5385 u32 icr = rd32(E1000_ICR);
5386
5387 igb_write_itr(q_vector);
5388
5389 if (icr & E1000_ICR_DRSTA)
5390 schedule_work(&adapter->reset_task);
5391
5392 if (icr & E1000_ICR_DOUTSYNC) {
5393 /* HW is reporting DMA is out of sync */
5394 adapter->stats.doosync++;
5395 }
5396
5397 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5398 hw->mac.get_link_status = 1;
5399 if (!test_bit(__IGB_DOWN, &adapter->state))
5400 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5401 }
5402
5403 napi_schedule(&q_vector->napi);
5404
5405 return IRQ_HANDLED;
5406 }
5407
5408 /**
5409 * igb_intr - Legacy Interrupt Handler
5410 * @irq: interrupt number
5411 * @data: pointer to a network interface device structure
5412 **/
5413 static irqreturn_t igb_intr(int irq, void *data)
5414 {
5415 struct igb_adapter *adapter = data;
5416 struct igb_q_vector *q_vector = adapter->q_vector[0];
5417 struct e1000_hw *hw = &adapter->hw;
5418 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5419 * need for the IMC write */
5420 u32 icr = rd32(E1000_ICR);
5421 if (!icr)
5422 return IRQ_NONE; /* Not our interrupt */
5423
5424 igb_write_itr(q_vector);
5425
5426 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5427 * not set, then the adapter didn't send an interrupt */
5428 if (!(icr & E1000_ICR_INT_ASSERTED))
5429 return IRQ_NONE;
5430
5431 if (icr & E1000_ICR_DRSTA)
5432 schedule_work(&adapter->reset_task);
5433
5434 if (icr & E1000_ICR_DOUTSYNC) {
5435 /* HW is reporting DMA is out of sync */
5436 adapter->stats.doosync++;
5437 }
5438
5439 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5440 hw->mac.get_link_status = 1;
5441 /* guard against interrupt when we're going down */
5442 if (!test_bit(__IGB_DOWN, &adapter->state))
5443 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5444 }
5445
5446 napi_schedule(&q_vector->napi);
5447
5448 return IRQ_HANDLED;
5449 }
5450
5451 static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5452 {
5453 struct igb_adapter *adapter = q_vector->adapter;
5454 struct e1000_hw *hw = &adapter->hw;
5455
5456 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
5457 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
5458 if (!adapter->msix_entries)
5459 igb_set_itr(adapter);
5460 else
5461 igb_update_ring_itr(q_vector);
5462 }
5463
5464 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5465 if (adapter->msix_entries)
5466 wr32(E1000_EIMS, q_vector->eims_value);
5467 else
5468 igb_irq_enable(adapter);
5469 }
5470 }
5471
5472 /**
5473 * igb_poll - NAPI Rx polling callback
5474 * @napi: napi polling structure
5475 * @budget: count of how many packets we should handle
5476 **/
5477 static int igb_poll(struct napi_struct *napi, int budget)
5478 {
5479 struct igb_q_vector *q_vector = container_of(napi,
5480 struct igb_q_vector,
5481 napi);
5482 bool clean_complete = true;
5483
5484 #ifdef CONFIG_IGB_DCA
5485 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5486 igb_update_dca(q_vector);
5487 #endif
5488 if (q_vector->tx_ring)
5489 clean_complete = igb_clean_tx_irq(q_vector);
5490
5491 if (q_vector->rx_ring)
5492 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5493
5494 /* If all work not completed, return budget and keep polling */
5495 if (!clean_complete)
5496 return budget;
5497
5498 /* If not enough Rx work done, exit the polling mode */
5499 napi_complete(napi);
5500 igb_ring_irq_enable(q_vector);
5501
5502 return 0;
5503 }
5504
5505 /**
5506 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
5507 * @adapter: board private structure
5508 * @shhwtstamps: timestamp structure to update
5509 * @regval: unsigned 64bit system time value.
5510 *
5511 * We need to convert the system time value stored in the RX/TXSTMP registers
5512 * into a hwtstamp which can be used by the upper level timestamping functions
5513 */
5514 static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
5515 struct skb_shared_hwtstamps *shhwtstamps,
5516 u64 regval)
5517 {
5518 u64 ns;
5519
5520 /*
5521 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
5522 * 24 to match clock shift we setup earlier.
5523 */
5524 if (adapter->hw.mac.type == e1000_82580)
5525 regval <<= IGB_82580_TSYNC_SHIFT;
5526
5527 ns = timecounter_cyc2time(&adapter->clock, regval);
5528 timecompare_update(&adapter->compare, ns);
5529 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
5530 shhwtstamps->hwtstamp = ns_to_ktime(ns);
5531 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
5532 }
5533
5534 /**
5535 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5536 * @q_vector: pointer to q_vector containing needed info
5537 * @buffer: pointer to igb_tx_buffer structure
5538 *
5539 * If we were asked to do hardware stamping and such a time stamp is
5540 * available, then it must have been for this skb here because we only
5541 * allow only one such packet into the queue.
5542 */
5543 static void igb_tx_hwtstamp(struct igb_q_vector *q_vector,
5544 struct igb_tx_buffer *buffer_info)
5545 {
5546 struct igb_adapter *adapter = q_vector->adapter;
5547 struct e1000_hw *hw = &adapter->hw;
5548 struct skb_shared_hwtstamps shhwtstamps;
5549 u64 regval;
5550
5551 /* if skb does not support hw timestamp or TX stamp not valid exit */
5552 if (likely(!(buffer_info->tx_flags & SKBTX_HW_TSTAMP)) ||
5553 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5554 return;
5555
5556 regval = rd32(E1000_TXSTMPL);
5557 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5558
5559 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
5560 skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
5561 }
5562
5563 /**
5564 * igb_clean_tx_irq - Reclaim resources after transmit completes
5565 * @q_vector: pointer to q_vector containing needed info
5566 * returns true if ring is completely cleaned
5567 **/
5568 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5569 {
5570 struct igb_adapter *adapter = q_vector->adapter;
5571 struct igb_ring *tx_ring = q_vector->tx_ring;
5572 struct igb_tx_buffer *tx_buffer;
5573 union e1000_adv_tx_desc *tx_desc, *eop_desc;
5574 unsigned int total_bytes = 0, total_packets = 0;
5575 unsigned int budget = q_vector->tx_work_limit;
5576 unsigned int i = tx_ring->next_to_clean;
5577
5578 if (test_bit(__IGB_DOWN, &adapter->state))
5579 return true;
5580
5581 tx_buffer = &tx_ring->tx_buffer_info[i];
5582 tx_desc = IGB_TX_DESC(tx_ring, i);
5583 i -= tx_ring->count;
5584
5585 for (; budget; budget--) {
5586 eop_desc = tx_buffer->next_to_watch;
5587
5588 /* prevent any other reads prior to eop_desc */
5589 rmb();
5590
5591 /* if next_to_watch is not set then there is no work pending */
5592 if (!eop_desc)
5593 break;
5594
5595 /* if DD is not set pending work has not been completed */
5596 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5597 break;
5598
5599 /* clear next_to_watch to prevent false hangs */
5600 tx_buffer->next_to_watch = NULL;
5601
5602 do {
5603 tx_desc->wb.status = 0;
5604 if (likely(tx_desc == eop_desc)) {
5605 eop_desc = NULL;
5606
5607 total_bytes += tx_buffer->bytecount;
5608 total_packets += tx_buffer->gso_segs;
5609 igb_tx_hwtstamp(q_vector, tx_buffer);
5610 }
5611
5612 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5613
5614 tx_buffer++;
5615 tx_desc++;
5616 i++;
5617 if (unlikely(!i)) {
5618 i -= tx_ring->count;
5619 tx_buffer = tx_ring->tx_buffer_info;
5620 tx_desc = IGB_TX_DESC(tx_ring, 0);
5621 }
5622 } while (eop_desc);
5623 }
5624
5625 i += tx_ring->count;
5626 tx_ring->next_to_clean = i;
5627 u64_stats_update_begin(&tx_ring->tx_syncp);
5628 tx_ring->tx_stats.bytes += total_bytes;
5629 tx_ring->tx_stats.packets += total_packets;
5630 u64_stats_update_end(&tx_ring->tx_syncp);
5631 tx_ring->total_bytes += total_bytes;
5632 tx_ring->total_packets += total_packets;
5633
5634 if (tx_ring->detect_tx_hung) {
5635 struct e1000_hw *hw = &adapter->hw;
5636
5637 eop_desc = tx_buffer->next_to_watch;
5638
5639 /* Detect a transmit hang in hardware, this serializes the
5640 * check with the clearing of time_stamp and movement of i */
5641 tx_ring->detect_tx_hung = false;
5642 if (eop_desc &&
5643 time_after(jiffies, tx_buffer->time_stamp +
5644 (adapter->tx_timeout_factor * HZ)) &&
5645 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5646
5647 /* detected Tx unit hang */
5648 dev_err(tx_ring->dev,
5649 "Detected Tx Unit Hang\n"
5650 " Tx Queue <%d>\n"
5651 " TDH <%x>\n"
5652 " TDT <%x>\n"
5653 " next_to_use <%x>\n"
5654 " next_to_clean <%x>\n"
5655 "buffer_info[next_to_clean]\n"
5656 " time_stamp <%lx>\n"
5657 " next_to_watch <%p>\n"
5658 " jiffies <%lx>\n"
5659 " desc.status <%x>\n",
5660 tx_ring->queue_index,
5661 rd32(E1000_TDH(tx_ring->reg_idx)),
5662 readl(tx_ring->tail),
5663 tx_ring->next_to_use,
5664 tx_ring->next_to_clean,
5665 tx_buffer->time_stamp,
5666 eop_desc,
5667 jiffies,
5668 eop_desc->wb.status);
5669 netif_stop_subqueue(tx_ring->netdev,
5670 tx_ring->queue_index);
5671
5672 /* we are about to reset, no point in enabling stuff */
5673 return true;
5674 }
5675 }
5676
5677 if (unlikely(total_packets &&
5678 netif_carrier_ok(tx_ring->netdev) &&
5679 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5680 /* Make sure that anybody stopping the queue after this
5681 * sees the new next_to_clean.
5682 */
5683 smp_mb();
5684 if (__netif_subqueue_stopped(tx_ring->netdev,
5685 tx_ring->queue_index) &&
5686 !(test_bit(__IGB_DOWN, &adapter->state))) {
5687 netif_wake_subqueue(tx_ring->netdev,
5688 tx_ring->queue_index);
5689
5690 u64_stats_update_begin(&tx_ring->tx_syncp);
5691 tx_ring->tx_stats.restart_queue++;
5692 u64_stats_update_end(&tx_ring->tx_syncp);
5693 }
5694 }
5695
5696 return !!budget;
5697 }
5698
5699 static inline void igb_rx_checksum(struct igb_ring *ring,
5700 u32 status_err, struct sk_buff *skb)
5701 {
5702 skb_checksum_none_assert(skb);
5703
5704 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
5705 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5706 (status_err & E1000_RXD_STAT_IXSM))
5707 return;
5708
5709 /* TCP/UDP checksum error bit is set */
5710 if (status_err &
5711 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
5712 /*
5713 * work around errata with sctp packets where the TCPE aka
5714 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5715 * packets, (aka let the stack check the crc32c)
5716 */
5717 if ((skb->len == 60) &&
5718 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) {
5719 u64_stats_update_begin(&ring->rx_syncp);
5720 ring->rx_stats.csum_err++;
5721 u64_stats_update_end(&ring->rx_syncp);
5722 }
5723 /* let the stack verify checksum errors */
5724 return;
5725 }
5726 /* It must be a TCP or UDP packet with a valid checksum */
5727 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5728 skb->ip_summed = CHECKSUM_UNNECESSARY;
5729
5730 dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err);
5731 }
5732
5733 static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
5734 struct sk_buff *skb)
5735 {
5736 struct igb_adapter *adapter = q_vector->adapter;
5737 struct e1000_hw *hw = &adapter->hw;
5738 u64 regval;
5739
5740 /*
5741 * If this bit is set, then the RX registers contain the time stamp. No
5742 * other packet will be time stamped until we read these registers, so
5743 * read the registers to make them available again. Because only one
5744 * packet can be time stamped at a time, we know that the register
5745 * values must belong to this one here and therefore we don't need to
5746 * compare any of the additional attributes stored for it.
5747 *
5748 * If nothing went wrong, then it should have a shared tx_flags that we
5749 * can turn into a skb_shared_hwtstamps.
5750 */
5751 if (staterr & E1000_RXDADV_STAT_TSIP) {
5752 u32 *stamp = (u32 *)skb->data;
5753 regval = le32_to_cpu(*(stamp + 2));
5754 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5755 skb_pull(skb, IGB_TS_HDR_LEN);
5756 } else {
5757 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5758 return;
5759
5760 regval = rd32(E1000_RXSTMPL);
5761 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5762 }
5763
5764 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5765 }
5766 static inline u16 igb_get_hlen(union e1000_adv_rx_desc *rx_desc)
5767 {
5768 /* HW will not DMA in data larger than the given buffer, even if it
5769 * parses the (NFS, of course) header to be larger. In that case, it
5770 * fills the header buffer and spills the rest into the page.
5771 */
5772 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5773 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
5774 if (hlen > IGB_RX_HDR_LEN)
5775 hlen = IGB_RX_HDR_LEN;
5776 return hlen;
5777 }
5778
5779 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget)
5780 {
5781 struct igb_ring *rx_ring = q_vector->rx_ring;
5782 union e1000_adv_rx_desc *rx_desc;
5783 const int current_node = numa_node_id();
5784 unsigned int total_bytes = 0, total_packets = 0;
5785 u32 staterr;
5786 u16 cleaned_count = igb_desc_unused(rx_ring);
5787 u16 i = rx_ring->next_to_clean;
5788
5789 rx_desc = IGB_RX_DESC(rx_ring, i);
5790 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5791
5792 while (staterr & E1000_RXD_STAT_DD) {
5793 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
5794 struct sk_buff *skb = buffer_info->skb;
5795 union e1000_adv_rx_desc *next_rxd;
5796
5797 buffer_info->skb = NULL;
5798 prefetch(skb->data);
5799
5800 i++;
5801 if (i == rx_ring->count)
5802 i = 0;
5803
5804 next_rxd = IGB_RX_DESC(rx_ring, i);
5805 prefetch(next_rxd);
5806
5807 /*
5808 * This memory barrier is needed to keep us from reading
5809 * any other fields out of the rx_desc until we know the
5810 * RXD_STAT_DD bit is set
5811 */
5812 rmb();
5813
5814 if (!skb_is_nonlinear(skb)) {
5815 __skb_put(skb, igb_get_hlen(rx_desc));
5816 dma_unmap_single(rx_ring->dev, buffer_info->dma,
5817 IGB_RX_HDR_LEN,
5818 DMA_FROM_DEVICE);
5819 buffer_info->dma = 0;
5820 }
5821
5822 if (rx_desc->wb.upper.length) {
5823 u16 length = le16_to_cpu(rx_desc->wb.upper.length);
5824
5825 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
5826 buffer_info->page,
5827 buffer_info->page_offset,
5828 length);
5829
5830 skb->len += length;
5831 skb->data_len += length;
5832 skb->truesize += length;
5833
5834 if ((page_count(buffer_info->page) != 1) ||
5835 (page_to_nid(buffer_info->page) != current_node))
5836 buffer_info->page = NULL;
5837 else
5838 get_page(buffer_info->page);
5839
5840 dma_unmap_page(rx_ring->dev, buffer_info->page_dma,
5841 PAGE_SIZE / 2, DMA_FROM_DEVICE);
5842 buffer_info->page_dma = 0;
5843 }
5844
5845 if (!(staterr & E1000_RXD_STAT_EOP)) {
5846 struct igb_rx_buffer *next_buffer;
5847 next_buffer = &rx_ring->rx_buffer_info[i];
5848 buffer_info->skb = next_buffer->skb;
5849 buffer_info->dma = next_buffer->dma;
5850 next_buffer->skb = skb;
5851 next_buffer->dma = 0;
5852 goto next_desc;
5853 }
5854
5855 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5856 dev_kfree_skb_any(skb);
5857 goto next_desc;
5858 }
5859
5860 if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS))
5861 igb_rx_hwtstamp(q_vector, staterr, skb);
5862 total_bytes += skb->len;
5863 total_packets++;
5864
5865 igb_rx_checksum(rx_ring, staterr, skb);
5866
5867 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
5868
5869 if (staterr & E1000_RXD_STAT_VP) {
5870 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
5871
5872 __vlan_hwaccel_put_tag(skb, vid);
5873 }
5874 napi_gro_receive(&q_vector->napi, skb);
5875
5876 budget--;
5877 next_desc:
5878 if (!budget)
5879 break;
5880
5881 cleaned_count++;
5882 /* return some buffers to hardware, one at a time is too slow */
5883 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
5884 igb_alloc_rx_buffers(rx_ring, cleaned_count);
5885 cleaned_count = 0;
5886 }
5887
5888 /* use prefetched values */
5889 rx_desc = next_rxd;
5890 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5891 }
5892
5893 rx_ring->next_to_clean = i;
5894 u64_stats_update_begin(&rx_ring->rx_syncp);
5895 rx_ring->rx_stats.packets += total_packets;
5896 rx_ring->rx_stats.bytes += total_bytes;
5897 u64_stats_update_end(&rx_ring->rx_syncp);
5898 rx_ring->total_packets += total_packets;
5899 rx_ring->total_bytes += total_bytes;
5900
5901 if (cleaned_count)
5902 igb_alloc_rx_buffers(rx_ring, cleaned_count);
5903
5904 return !!budget;
5905 }
5906
5907 static bool igb_alloc_mapped_skb(struct igb_ring *rx_ring,
5908 struct igb_rx_buffer *bi)
5909 {
5910 struct sk_buff *skb = bi->skb;
5911 dma_addr_t dma = bi->dma;
5912
5913 if (dma)
5914 return true;
5915
5916 if (likely(!skb)) {
5917 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5918 IGB_RX_HDR_LEN);
5919 bi->skb = skb;
5920 if (!skb) {
5921 rx_ring->rx_stats.alloc_failed++;
5922 return false;
5923 }
5924
5925 /* initialize skb for ring */
5926 skb_record_rx_queue(skb, rx_ring->queue_index);
5927 }
5928
5929 dma = dma_map_single(rx_ring->dev, skb->data,
5930 IGB_RX_HDR_LEN, DMA_FROM_DEVICE);
5931
5932 if (dma_mapping_error(rx_ring->dev, dma)) {
5933 rx_ring->rx_stats.alloc_failed++;
5934 return false;
5935 }
5936
5937 bi->dma = dma;
5938 return true;
5939 }
5940
5941 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
5942 struct igb_rx_buffer *bi)
5943 {
5944 struct page *page = bi->page;
5945 dma_addr_t page_dma = bi->page_dma;
5946 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
5947
5948 if (page_dma)
5949 return true;
5950
5951 if (!page) {
5952 page = netdev_alloc_page(rx_ring->netdev);
5953 bi->page = page;
5954 if (unlikely(!page)) {
5955 rx_ring->rx_stats.alloc_failed++;
5956 return false;
5957 }
5958 }
5959
5960 page_dma = dma_map_page(rx_ring->dev, page,
5961 page_offset, PAGE_SIZE / 2,
5962 DMA_FROM_DEVICE);
5963
5964 if (dma_mapping_error(rx_ring->dev, page_dma)) {
5965 rx_ring->rx_stats.alloc_failed++;
5966 return false;
5967 }
5968
5969 bi->page_dma = page_dma;
5970 bi->page_offset = page_offset;
5971 return true;
5972 }
5973
5974 /**
5975 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
5976 * @adapter: address of board private structure
5977 **/
5978 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
5979 {
5980 union e1000_adv_rx_desc *rx_desc;
5981 struct igb_rx_buffer *bi;
5982 u16 i = rx_ring->next_to_use;
5983
5984 rx_desc = IGB_RX_DESC(rx_ring, i);
5985 bi = &rx_ring->rx_buffer_info[i];
5986 i -= rx_ring->count;
5987
5988 while (cleaned_count--) {
5989 if (!igb_alloc_mapped_skb(rx_ring, bi))
5990 break;
5991
5992 /* Refresh the desc even if buffer_addrs didn't change
5993 * because each write-back erases this info. */
5994 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
5995
5996 if (!igb_alloc_mapped_page(rx_ring, bi))
5997 break;
5998
5999 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
6000
6001 rx_desc++;
6002 bi++;
6003 i++;
6004 if (unlikely(!i)) {
6005 rx_desc = IGB_RX_DESC(rx_ring, 0);
6006 bi = rx_ring->rx_buffer_info;
6007 i -= rx_ring->count;
6008 }
6009
6010 /* clear the hdr_addr for the next_to_use descriptor */
6011 rx_desc->read.hdr_addr = 0;
6012 }
6013
6014 i += rx_ring->count;
6015
6016 if (rx_ring->next_to_use != i) {
6017 rx_ring->next_to_use = i;
6018
6019 /* Force memory writes to complete before letting h/w
6020 * know there are new descriptors to fetch. (Only
6021 * applicable for weak-ordered memory model archs,
6022 * such as IA-64). */
6023 wmb();
6024 writel(i, rx_ring->tail);
6025 }
6026 }
6027
6028 /**
6029 * igb_mii_ioctl -
6030 * @netdev:
6031 * @ifreq:
6032 * @cmd:
6033 **/
6034 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6035 {
6036 struct igb_adapter *adapter = netdev_priv(netdev);
6037 struct mii_ioctl_data *data = if_mii(ifr);
6038
6039 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6040 return -EOPNOTSUPP;
6041
6042 switch (cmd) {
6043 case SIOCGMIIPHY:
6044 data->phy_id = adapter->hw.phy.addr;
6045 break;
6046 case SIOCGMIIREG:
6047 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6048 &data->val_out))
6049 return -EIO;
6050 break;
6051 case SIOCSMIIREG:
6052 default:
6053 return -EOPNOTSUPP;
6054 }
6055 return 0;
6056 }
6057
6058 /**
6059 * igb_hwtstamp_ioctl - control hardware time stamping
6060 * @netdev:
6061 * @ifreq:
6062 * @cmd:
6063 *
6064 * Outgoing time stamping can be enabled and disabled. Play nice and
6065 * disable it when requested, although it shouldn't case any overhead
6066 * when no packet needs it. At most one packet in the queue may be
6067 * marked for time stamping, otherwise it would be impossible to tell
6068 * for sure to which packet the hardware time stamp belongs.
6069 *
6070 * Incoming time stamping has to be configured via the hardware
6071 * filters. Not all combinations are supported, in particular event
6072 * type has to be specified. Matching the kind of event packet is
6073 * not supported, with the exception of "all V2 events regardless of
6074 * level 2 or 4".
6075 *
6076 **/
6077 static int igb_hwtstamp_ioctl(struct net_device *netdev,
6078 struct ifreq *ifr, int cmd)
6079 {
6080 struct igb_adapter *adapter = netdev_priv(netdev);
6081 struct e1000_hw *hw = &adapter->hw;
6082 struct hwtstamp_config config;
6083 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
6084 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6085 u32 tsync_rx_cfg = 0;
6086 bool is_l4 = false;
6087 bool is_l2 = false;
6088 u32 regval;
6089
6090 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6091 return -EFAULT;
6092
6093 /* reserved for future extensions */
6094 if (config.flags)
6095 return -EINVAL;
6096
6097 switch (config.tx_type) {
6098 case HWTSTAMP_TX_OFF:
6099 tsync_tx_ctl = 0;
6100 case HWTSTAMP_TX_ON:
6101 break;
6102 default:
6103 return -ERANGE;
6104 }
6105
6106 switch (config.rx_filter) {
6107 case HWTSTAMP_FILTER_NONE:
6108 tsync_rx_ctl = 0;
6109 break;
6110 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6111 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6112 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6113 case HWTSTAMP_FILTER_ALL:
6114 /*
6115 * register TSYNCRXCFG must be set, therefore it is not
6116 * possible to time stamp both Sync and Delay_Req messages
6117 * => fall back to time stamping all packets
6118 */
6119 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6120 config.rx_filter = HWTSTAMP_FILTER_ALL;
6121 break;
6122 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6123 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
6124 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
6125 is_l4 = true;
6126 break;
6127 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6128 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
6129 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
6130 is_l4 = true;
6131 break;
6132 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6133 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6134 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
6135 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
6136 is_l2 = true;
6137 is_l4 = true;
6138 config.rx_filter = HWTSTAMP_FILTER_SOME;
6139 break;
6140 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6141 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6142 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
6143 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
6144 is_l2 = true;
6145 is_l4 = true;
6146 config.rx_filter = HWTSTAMP_FILTER_SOME;
6147 break;
6148 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6149 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6150 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6151 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
6152 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
6153 is_l2 = true;
6154 break;
6155 default:
6156 return -ERANGE;
6157 }
6158
6159 if (hw->mac.type == e1000_82575) {
6160 if (tsync_rx_ctl | tsync_tx_ctl)
6161 return -EINVAL;
6162 return 0;
6163 }
6164
6165 /*
6166 * Per-packet timestamping only works if all packets are
6167 * timestamped, so enable timestamping in all packets as
6168 * long as one rx filter was configured.
6169 */
6170 if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
6171 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6172 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6173 }
6174
6175 /* enable/disable TX */
6176 regval = rd32(E1000_TSYNCTXCTL);
6177 regval &= ~E1000_TSYNCTXCTL_ENABLED;
6178 regval |= tsync_tx_ctl;
6179 wr32(E1000_TSYNCTXCTL, regval);
6180
6181 /* enable/disable RX */
6182 regval = rd32(E1000_TSYNCRXCTL);
6183 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
6184 regval |= tsync_rx_ctl;
6185 wr32(E1000_TSYNCRXCTL, regval);
6186
6187 /* define which PTP packets are time stamped */
6188 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
6189
6190 /* define ethertype filter for timestamped packets */
6191 if (is_l2)
6192 wr32(E1000_ETQF(3),
6193 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
6194 E1000_ETQF_1588 | /* enable timestamping */
6195 ETH_P_1588)); /* 1588 eth protocol type */
6196 else
6197 wr32(E1000_ETQF(3), 0);
6198
6199 #define PTP_PORT 319
6200 /* L4 Queue Filter[3]: filter by destination port and protocol */
6201 if (is_l4) {
6202 u32 ftqf = (IPPROTO_UDP /* UDP */
6203 | E1000_FTQF_VF_BP /* VF not compared */
6204 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
6205 | E1000_FTQF_MASK); /* mask all inputs */
6206 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
6207
6208 wr32(E1000_IMIR(3), htons(PTP_PORT));
6209 wr32(E1000_IMIREXT(3),
6210 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
6211 if (hw->mac.type == e1000_82576) {
6212 /* enable source port check */
6213 wr32(E1000_SPQF(3), htons(PTP_PORT));
6214 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
6215 }
6216 wr32(E1000_FTQF(3), ftqf);
6217 } else {
6218 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
6219 }
6220 wrfl();
6221
6222 adapter->hwtstamp_config = config;
6223
6224 /* clear TX/RX time stamp registers, just to be sure */
6225 regval = rd32(E1000_TXSTMPH);
6226 regval = rd32(E1000_RXSTMPH);
6227
6228 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
6229 -EFAULT : 0;
6230 }
6231
6232 /**
6233 * igb_ioctl -
6234 * @netdev:
6235 * @ifreq:
6236 * @cmd:
6237 **/
6238 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6239 {
6240 switch (cmd) {
6241 case SIOCGMIIPHY:
6242 case SIOCGMIIREG:
6243 case SIOCSMIIREG:
6244 return igb_mii_ioctl(netdev, ifr, cmd);
6245 case SIOCSHWTSTAMP:
6246 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
6247 default:
6248 return -EOPNOTSUPP;
6249 }
6250 }
6251
6252 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6253 {
6254 struct igb_adapter *adapter = hw->back;
6255 u16 cap_offset;
6256
6257 cap_offset = adapter->pdev->pcie_cap;
6258 if (!cap_offset)
6259 return -E1000_ERR_CONFIG;
6260
6261 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
6262
6263 return 0;
6264 }
6265
6266 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6267 {
6268 struct igb_adapter *adapter = hw->back;
6269 u16 cap_offset;
6270
6271 cap_offset = adapter->pdev->pcie_cap;
6272 if (!cap_offset)
6273 return -E1000_ERR_CONFIG;
6274
6275 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6276
6277 return 0;
6278 }
6279
6280 static void igb_vlan_mode(struct net_device *netdev, u32 features)
6281 {
6282 struct igb_adapter *adapter = netdev_priv(netdev);
6283 struct e1000_hw *hw = &adapter->hw;
6284 u32 ctrl, rctl;
6285
6286 igb_irq_disable(adapter);
6287
6288 if (features & NETIF_F_HW_VLAN_RX) {
6289 /* enable VLAN tag insert/strip */
6290 ctrl = rd32(E1000_CTRL);
6291 ctrl |= E1000_CTRL_VME;
6292 wr32(E1000_CTRL, ctrl);
6293
6294 /* Disable CFI check */
6295 rctl = rd32(E1000_RCTL);
6296 rctl &= ~E1000_RCTL_CFIEN;
6297 wr32(E1000_RCTL, rctl);
6298 } else {
6299 /* disable VLAN tag insert/strip */
6300 ctrl = rd32(E1000_CTRL);
6301 ctrl &= ~E1000_CTRL_VME;
6302 wr32(E1000_CTRL, ctrl);
6303 }
6304
6305 igb_rlpml_set(adapter);
6306
6307 if (!test_bit(__IGB_DOWN, &adapter->state))
6308 igb_irq_enable(adapter);
6309 }
6310
6311 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6312 {
6313 struct igb_adapter *adapter = netdev_priv(netdev);
6314 struct e1000_hw *hw = &adapter->hw;
6315 int pf_id = adapter->vfs_allocated_count;
6316
6317 /* attempt to add filter to vlvf array */
6318 igb_vlvf_set(adapter, vid, true, pf_id);
6319
6320 /* add the filter since PF can receive vlans w/o entry in vlvf */
6321 igb_vfta_set(hw, vid, true);
6322
6323 set_bit(vid, adapter->active_vlans);
6324 }
6325
6326 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6327 {
6328 struct igb_adapter *adapter = netdev_priv(netdev);
6329 struct e1000_hw *hw = &adapter->hw;
6330 int pf_id = adapter->vfs_allocated_count;
6331 s32 err;
6332
6333 igb_irq_disable(adapter);
6334
6335 if (!test_bit(__IGB_DOWN, &adapter->state))
6336 igb_irq_enable(adapter);
6337
6338 /* remove vlan from VLVF table array */
6339 err = igb_vlvf_set(adapter, vid, false, pf_id);
6340
6341 /* if vid was not present in VLVF just remove it from table */
6342 if (err)
6343 igb_vfta_set(hw, vid, false);
6344
6345 clear_bit(vid, adapter->active_vlans);
6346 }
6347
6348 static void igb_restore_vlan(struct igb_adapter *adapter)
6349 {
6350 u16 vid;
6351
6352 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6353 igb_vlan_rx_add_vid(adapter->netdev, vid);
6354 }
6355
6356 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6357 {
6358 struct pci_dev *pdev = adapter->pdev;
6359 struct e1000_mac_info *mac = &adapter->hw.mac;
6360
6361 mac->autoneg = 0;
6362
6363 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6364 * for the switch() below to work */
6365 if ((spd & 1) || (dplx & ~1))
6366 goto err_inval;
6367
6368 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6369 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6370 spd != SPEED_1000 &&
6371 dplx != DUPLEX_FULL)
6372 goto err_inval;
6373
6374 switch (spd + dplx) {
6375 case SPEED_10 + DUPLEX_HALF:
6376 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6377 break;
6378 case SPEED_10 + DUPLEX_FULL:
6379 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6380 break;
6381 case SPEED_100 + DUPLEX_HALF:
6382 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6383 break;
6384 case SPEED_100 + DUPLEX_FULL:
6385 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6386 break;
6387 case SPEED_1000 + DUPLEX_FULL:
6388 mac->autoneg = 1;
6389 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6390 break;
6391 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6392 default:
6393 goto err_inval;
6394 }
6395 return 0;
6396
6397 err_inval:
6398 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6399 return -EINVAL;
6400 }
6401
6402 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
6403 {
6404 struct net_device *netdev = pci_get_drvdata(pdev);
6405 struct igb_adapter *adapter = netdev_priv(netdev);
6406 struct e1000_hw *hw = &adapter->hw;
6407 u32 ctrl, rctl, status;
6408 u32 wufc = adapter->wol;
6409 #ifdef CONFIG_PM
6410 int retval = 0;
6411 #endif
6412
6413 netif_device_detach(netdev);
6414
6415 if (netif_running(netdev))
6416 igb_close(netdev);
6417
6418 igb_clear_interrupt_scheme(adapter);
6419
6420 #ifdef CONFIG_PM
6421 retval = pci_save_state(pdev);
6422 if (retval)
6423 return retval;
6424 #endif
6425
6426 status = rd32(E1000_STATUS);
6427 if (status & E1000_STATUS_LU)
6428 wufc &= ~E1000_WUFC_LNKC;
6429
6430 if (wufc) {
6431 igb_setup_rctl(adapter);
6432 igb_set_rx_mode(netdev);
6433
6434 /* turn on all-multi mode if wake on multicast is enabled */
6435 if (wufc & E1000_WUFC_MC) {
6436 rctl = rd32(E1000_RCTL);
6437 rctl |= E1000_RCTL_MPE;
6438 wr32(E1000_RCTL, rctl);
6439 }
6440
6441 ctrl = rd32(E1000_CTRL);
6442 /* advertise wake from D3Cold */
6443 #define E1000_CTRL_ADVD3WUC 0x00100000
6444 /* phy power management enable */
6445 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6446 ctrl |= E1000_CTRL_ADVD3WUC;
6447 wr32(E1000_CTRL, ctrl);
6448
6449 /* Allow time for pending master requests to run */
6450 igb_disable_pcie_master(hw);
6451
6452 wr32(E1000_WUC, E1000_WUC_PME_EN);
6453 wr32(E1000_WUFC, wufc);
6454 } else {
6455 wr32(E1000_WUC, 0);
6456 wr32(E1000_WUFC, 0);
6457 }
6458
6459 *enable_wake = wufc || adapter->en_mng_pt;
6460 if (!*enable_wake)
6461 igb_power_down_link(adapter);
6462 else
6463 igb_power_up_link(adapter);
6464
6465 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6466 * would have already happened in close and is redundant. */
6467 igb_release_hw_control(adapter);
6468
6469 pci_disable_device(pdev);
6470
6471 return 0;
6472 }
6473
6474 #ifdef CONFIG_PM
6475 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
6476 {
6477 int retval;
6478 bool wake;
6479
6480 retval = __igb_shutdown(pdev, &wake);
6481 if (retval)
6482 return retval;
6483
6484 if (wake) {
6485 pci_prepare_to_sleep(pdev);
6486 } else {
6487 pci_wake_from_d3(pdev, false);
6488 pci_set_power_state(pdev, PCI_D3hot);
6489 }
6490
6491 return 0;
6492 }
6493
6494 static int igb_resume(struct pci_dev *pdev)
6495 {
6496 struct net_device *netdev = pci_get_drvdata(pdev);
6497 struct igb_adapter *adapter = netdev_priv(netdev);
6498 struct e1000_hw *hw = &adapter->hw;
6499 u32 err;
6500
6501 pci_set_power_state(pdev, PCI_D0);
6502 pci_restore_state(pdev);
6503 pci_save_state(pdev);
6504
6505 err = pci_enable_device_mem(pdev);
6506 if (err) {
6507 dev_err(&pdev->dev,
6508 "igb: Cannot enable PCI device from suspend\n");
6509 return err;
6510 }
6511 pci_set_master(pdev);
6512
6513 pci_enable_wake(pdev, PCI_D3hot, 0);
6514 pci_enable_wake(pdev, PCI_D3cold, 0);
6515
6516 if (igb_init_interrupt_scheme(adapter)) {
6517 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6518 return -ENOMEM;
6519 }
6520
6521 igb_reset(adapter);
6522
6523 /* let the f/w know that the h/w is now under the control of the
6524 * driver. */
6525 igb_get_hw_control(adapter);
6526
6527 wr32(E1000_WUS, ~0);
6528
6529 if (netif_running(netdev)) {
6530 err = igb_open(netdev);
6531 if (err)
6532 return err;
6533 }
6534
6535 netif_device_attach(netdev);
6536
6537 return 0;
6538 }
6539 #endif
6540
6541 static void igb_shutdown(struct pci_dev *pdev)
6542 {
6543 bool wake;
6544
6545 __igb_shutdown(pdev, &wake);
6546
6547 if (system_state == SYSTEM_POWER_OFF) {
6548 pci_wake_from_d3(pdev, wake);
6549 pci_set_power_state(pdev, PCI_D3hot);
6550 }
6551 }
6552
6553 #ifdef CONFIG_NET_POLL_CONTROLLER
6554 /*
6555 * Polling 'interrupt' - used by things like netconsole to send skbs
6556 * without having to re-enable interrupts. It's not called while
6557 * the interrupt routine is executing.
6558 */
6559 static void igb_netpoll(struct net_device *netdev)
6560 {
6561 struct igb_adapter *adapter = netdev_priv(netdev);
6562 struct e1000_hw *hw = &adapter->hw;
6563 int i;
6564
6565 if (!adapter->msix_entries) {
6566 struct igb_q_vector *q_vector = adapter->q_vector[0];
6567 igb_irq_disable(adapter);
6568 napi_schedule(&q_vector->napi);
6569 return;
6570 }
6571
6572 for (i = 0; i < adapter->num_q_vectors; i++) {
6573 struct igb_q_vector *q_vector = adapter->q_vector[i];
6574 wr32(E1000_EIMC, q_vector->eims_value);
6575 napi_schedule(&q_vector->napi);
6576 }
6577 }
6578 #endif /* CONFIG_NET_POLL_CONTROLLER */
6579
6580 /**
6581 * igb_io_error_detected - called when PCI error is detected
6582 * @pdev: Pointer to PCI device
6583 * @state: The current pci connection state
6584 *
6585 * This function is called after a PCI bus error affecting
6586 * this device has been detected.
6587 */
6588 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6589 pci_channel_state_t state)
6590 {
6591 struct net_device *netdev = pci_get_drvdata(pdev);
6592 struct igb_adapter *adapter = netdev_priv(netdev);
6593
6594 netif_device_detach(netdev);
6595
6596 if (state == pci_channel_io_perm_failure)
6597 return PCI_ERS_RESULT_DISCONNECT;
6598
6599 if (netif_running(netdev))
6600 igb_down(adapter);
6601 pci_disable_device(pdev);
6602
6603 /* Request a slot slot reset. */
6604 return PCI_ERS_RESULT_NEED_RESET;
6605 }
6606
6607 /**
6608 * igb_io_slot_reset - called after the pci bus has been reset.
6609 * @pdev: Pointer to PCI device
6610 *
6611 * Restart the card from scratch, as if from a cold-boot. Implementation
6612 * resembles the first-half of the igb_resume routine.
6613 */
6614 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6615 {
6616 struct net_device *netdev = pci_get_drvdata(pdev);
6617 struct igb_adapter *adapter = netdev_priv(netdev);
6618 struct e1000_hw *hw = &adapter->hw;
6619 pci_ers_result_t result;
6620 int err;
6621
6622 if (pci_enable_device_mem(pdev)) {
6623 dev_err(&pdev->dev,
6624 "Cannot re-enable PCI device after reset.\n");
6625 result = PCI_ERS_RESULT_DISCONNECT;
6626 } else {
6627 pci_set_master(pdev);
6628 pci_restore_state(pdev);
6629 pci_save_state(pdev);
6630
6631 pci_enable_wake(pdev, PCI_D3hot, 0);
6632 pci_enable_wake(pdev, PCI_D3cold, 0);
6633
6634 igb_reset(adapter);
6635 wr32(E1000_WUS, ~0);
6636 result = PCI_ERS_RESULT_RECOVERED;
6637 }
6638
6639 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6640 if (err) {
6641 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6642 "failed 0x%0x\n", err);
6643 /* non-fatal, continue */
6644 }
6645
6646 return result;
6647 }
6648
6649 /**
6650 * igb_io_resume - called when traffic can start flowing again.
6651 * @pdev: Pointer to PCI device
6652 *
6653 * This callback is called when the error recovery driver tells us that
6654 * its OK to resume normal operation. Implementation resembles the
6655 * second-half of the igb_resume routine.
6656 */
6657 static void igb_io_resume(struct pci_dev *pdev)
6658 {
6659 struct net_device *netdev = pci_get_drvdata(pdev);
6660 struct igb_adapter *adapter = netdev_priv(netdev);
6661
6662 if (netif_running(netdev)) {
6663 if (igb_up(adapter)) {
6664 dev_err(&pdev->dev, "igb_up failed after reset\n");
6665 return;
6666 }
6667 }
6668
6669 netif_device_attach(netdev);
6670
6671 /* let the f/w know that the h/w is now under the control of the
6672 * driver. */
6673 igb_get_hw_control(adapter);
6674 }
6675
6676 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6677 u8 qsel)
6678 {
6679 u32 rar_low, rar_high;
6680 struct e1000_hw *hw = &adapter->hw;
6681
6682 /* HW expects these in little endian so we reverse the byte order
6683 * from network order (big endian) to little endian
6684 */
6685 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6686 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6687 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6688
6689 /* Indicate to hardware the Address is Valid. */
6690 rar_high |= E1000_RAH_AV;
6691
6692 if (hw->mac.type == e1000_82575)
6693 rar_high |= E1000_RAH_POOL_1 * qsel;
6694 else
6695 rar_high |= E1000_RAH_POOL_1 << qsel;
6696
6697 wr32(E1000_RAL(index), rar_low);
6698 wrfl();
6699 wr32(E1000_RAH(index), rar_high);
6700 wrfl();
6701 }
6702
6703 static int igb_set_vf_mac(struct igb_adapter *adapter,
6704 int vf, unsigned char *mac_addr)
6705 {
6706 struct e1000_hw *hw = &adapter->hw;
6707 /* VF MAC addresses start at end of receive addresses and moves
6708 * torwards the first, as a result a collision should not be possible */
6709 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6710
6711 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
6712
6713 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
6714
6715 return 0;
6716 }
6717
6718 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6719 {
6720 struct igb_adapter *adapter = netdev_priv(netdev);
6721 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6722 return -EINVAL;
6723 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6724 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6725 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6726 " change effective.");
6727 if (test_bit(__IGB_DOWN, &adapter->state)) {
6728 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6729 " but the PF device is not up.\n");
6730 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6731 " attempting to use the VF device.\n");
6732 }
6733 return igb_set_vf_mac(adapter, vf, mac);
6734 }
6735
6736 static int igb_link_mbps(int internal_link_speed)
6737 {
6738 switch (internal_link_speed) {
6739 case SPEED_100:
6740 return 100;
6741 case SPEED_1000:
6742 return 1000;
6743 default:
6744 return 0;
6745 }
6746 }
6747
6748 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
6749 int link_speed)
6750 {
6751 int rf_dec, rf_int;
6752 u32 bcnrc_val;
6753
6754 if (tx_rate != 0) {
6755 /* Calculate the rate factor values to set */
6756 rf_int = link_speed / tx_rate;
6757 rf_dec = (link_speed - (rf_int * tx_rate));
6758 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
6759
6760 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
6761 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
6762 E1000_RTTBCNRC_RF_INT_MASK);
6763 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
6764 } else {
6765 bcnrc_val = 0;
6766 }
6767
6768 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
6769 wr32(E1000_RTTBCNRC, bcnrc_val);
6770 }
6771
6772 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
6773 {
6774 int actual_link_speed, i;
6775 bool reset_rate = false;
6776
6777 /* VF TX rate limit was not set or not supported */
6778 if ((adapter->vf_rate_link_speed == 0) ||
6779 (adapter->hw.mac.type != e1000_82576))
6780 return;
6781
6782 actual_link_speed = igb_link_mbps(adapter->link_speed);
6783 if (actual_link_speed != adapter->vf_rate_link_speed) {
6784 reset_rate = true;
6785 adapter->vf_rate_link_speed = 0;
6786 dev_info(&adapter->pdev->dev,
6787 "Link speed has been changed. VF Transmit "
6788 "rate is disabled\n");
6789 }
6790
6791 for (i = 0; i < adapter->vfs_allocated_count; i++) {
6792 if (reset_rate)
6793 adapter->vf_data[i].tx_rate = 0;
6794
6795 igb_set_vf_rate_limit(&adapter->hw, i,
6796 adapter->vf_data[i].tx_rate,
6797 actual_link_speed);
6798 }
6799 }
6800
6801 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6802 {
6803 struct igb_adapter *adapter = netdev_priv(netdev);
6804 struct e1000_hw *hw = &adapter->hw;
6805 int actual_link_speed;
6806
6807 if (hw->mac.type != e1000_82576)
6808 return -EOPNOTSUPP;
6809
6810 actual_link_speed = igb_link_mbps(adapter->link_speed);
6811 if ((vf >= adapter->vfs_allocated_count) ||
6812 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
6813 (tx_rate < 0) || (tx_rate > actual_link_speed))
6814 return -EINVAL;
6815
6816 adapter->vf_rate_link_speed = actual_link_speed;
6817 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
6818 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
6819
6820 return 0;
6821 }
6822
6823 static int igb_ndo_get_vf_config(struct net_device *netdev,
6824 int vf, struct ifla_vf_info *ivi)
6825 {
6826 struct igb_adapter *adapter = netdev_priv(netdev);
6827 if (vf >= adapter->vfs_allocated_count)
6828 return -EINVAL;
6829 ivi->vf = vf;
6830 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
6831 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
6832 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6833 ivi->qos = adapter->vf_data[vf].pf_qos;
6834 return 0;
6835 }
6836
6837 static void igb_vmm_control(struct igb_adapter *adapter)
6838 {
6839 struct e1000_hw *hw = &adapter->hw;
6840 u32 reg;
6841
6842 switch (hw->mac.type) {
6843 case e1000_82575:
6844 default:
6845 /* replication is not supported for 82575 */
6846 return;
6847 case e1000_82576:
6848 /* notify HW that the MAC is adding vlan tags */
6849 reg = rd32(E1000_DTXCTL);
6850 reg |= E1000_DTXCTL_VLAN_ADDED;
6851 wr32(E1000_DTXCTL, reg);
6852 case e1000_82580:
6853 /* enable replication vlan tag stripping */
6854 reg = rd32(E1000_RPLOLR);
6855 reg |= E1000_RPLOLR_STRVLAN;
6856 wr32(E1000_RPLOLR, reg);
6857 case e1000_i350:
6858 /* none of the above registers are supported by i350 */
6859 break;
6860 }
6861
6862 if (adapter->vfs_allocated_count) {
6863 igb_vmdq_set_loopback_pf(hw, true);
6864 igb_vmdq_set_replication_pf(hw, true);
6865 igb_vmdq_set_anti_spoofing_pf(hw, true,
6866 adapter->vfs_allocated_count);
6867 } else {
6868 igb_vmdq_set_loopback_pf(hw, false);
6869 igb_vmdq_set_replication_pf(hw, false);
6870 }
6871 }
6872
6873 /* igb_main.c */
Linux kernel - Deliverables
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