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igb: Fix sparse warning about passing __beXX into leXX_to_cpup
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
57 #include "igb.h"
58
59 #define MAJ 5
60 #define MIN 3
61 #define BUILD 0
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71 static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73 };
74
75 static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 int igb_open(struct net_device *);
126 int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter, bool set);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static int igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 static int igb_disable_sriov(struct pci_dev *dev);
183 static int igb_pci_disable_sriov(struct pci_dev *dev);
184 #endif
185
186 #ifdef CONFIG_PM
187 #ifdef CONFIG_PM_SLEEP
188 static int igb_suspend(struct device *);
189 #endif
190 static int igb_resume(struct device *);
191 static int igb_runtime_suspend(struct device *dev);
192 static int igb_runtime_resume(struct device *dev);
193 static int igb_runtime_idle(struct device *dev);
194 static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198 };
199 #endif
200 static void igb_shutdown(struct pci_dev *);
201 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
202 #ifdef CONFIG_IGB_DCA
203 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204 static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208 };
209 #endif
210 #ifdef CONFIG_NET_POLL_CONTROLLER
211 /* for netdump / net console */
212 static void igb_netpoll(struct net_device *);
213 #endif
214 #ifdef CONFIG_PCI_IOV
215 static unsigned int max_vfs;
216 module_param(max_vfs, uint, 0);
217 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
218 #endif /* CONFIG_PCI_IOV */
219
220 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223 static void igb_io_resume(struct pci_dev *);
224
225 static const struct pci_error_handlers igb_err_handler = {
226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229 };
230
231 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
232
233 static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
237 .remove = igb_remove,
238 #ifdef CONFIG_PM
239 .driver.pm = &igb_pm_ops,
240 #endif
241 .shutdown = igb_shutdown,
242 .sriov_configure = igb_pci_sriov_configure,
243 .err_handler = &igb_err_handler
244 };
245
246 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248 MODULE_LICENSE("GPL");
249 MODULE_VERSION(DRV_VERSION);
250
251 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252 static int debug = -1;
253 module_param(debug, int, 0);
254 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
256 struct igb_reg_info {
257 u32 ofs;
258 char *name;
259 };
260
261 static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295 };
296
297 /* igb_regdump - register printout routine */
298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299 {
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
361 }
362
363 /* igb_dump - Print registers, Tx-rings and Rx-rings */
364 static void igb_dump(struct igb_adapter *adapter)
365 {
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
375 u16 i, n;
376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
383 pr_info("Device Name state trans_start last_rx\n");
384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
390 pr_info(" Register Name Value\n");
391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
402 for (n = 0; n < adapter->num_tx_queues; n++) {
403 struct igb_tx_buffer *buffer_info;
404 tx_ring = adapter->tx_ring[n];
405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
439 const char *next_desc;
440 struct igb_tx_buffer *buffer_info;
441 tx_desc = IGB_TX_DESC(tx_ring, i);
442 buffer_info = &tx_ring->tx_buffer_info[i];
443 u0 = (struct my_u0 *)tx_desc;
444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
456 le64_to_cpu(u0->b),
457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
461 buffer_info->skb, next_desc);
462
463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
466 16, 1, buffer_info->skb->data,
467 dma_unmap_len(buffer_info, len),
468 true);
469 }
470 }
471
472 /* Print RX Rings Summary */
473 rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
475 pr_info("Queue [NTU] [NTC]\n");
476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
516
517 for (i = 0; i < rx_ring->count; i++) {
518 const char *next_desc;
519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
521 rx_desc = IGB_RX_DESC(rx_ring, i);
522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
538 next_desc);
539 } else {
540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
545 next_desc);
546
547 if (netif_msg_pktdata(adapter) &&
548 buffer_info->dma && buffer_info->page) {
549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
554 IGB_RX_BUFSZ, true);
555 }
556 }
557 }
558 }
559
560 exit:
561 return;
562 }
563
564 /**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
570 **/
571 static int igb_get_i2c_data(void *data)
572 {
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
577 return !!(i2cctl & E1000_I2C_DATA_IN);
578 }
579
580 /**
581 * igb_set_i2c_data - Sets the I2C data bit
582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
586 **/
587 static void igb_set_i2c_data(void *data, int state)
588 {
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603 }
604
605 /**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
611 **/
612 static void igb_set_i2c_clk(void *data, int state)
613 {
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627 }
628
629 /**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
634 **/
635 static int igb_get_i2c_clk(void *data)
636 {
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
641 return !!(i2cctl & E1000_I2C_CLK_IN);
642 }
643
644 static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651 };
652
653 /**
654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
658 **/
659 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
660 {
661 struct igb_adapter *adapter = hw->back;
662 return adapter->netdev;
663 }
664
665 /**
666 * igb_init_module - Driver Registration Routine
667 *
668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
670 **/
671 static int __init igb_init_module(void)
672 {
673 int ret;
674
675 pr_info("%s - version %s\n",
676 igb_driver_string, igb_driver_version);
677 pr_info("%s\n", igb_copyright);
678
679 #ifdef CONFIG_IGB_DCA
680 dca_register_notify(&dca_notifier);
681 #endif
682 ret = pci_register_driver(&igb_driver);
683 return ret;
684 }
685
686 module_init(igb_init_module);
687
688 /**
689 * igb_exit_module - Driver Exit Cleanup Routine
690 *
691 * igb_exit_module is called just before the driver is removed
692 * from memory.
693 **/
694 static void __exit igb_exit_module(void)
695 {
696 #ifdef CONFIG_IGB_DCA
697 dca_unregister_notify(&dca_notifier);
698 #endif
699 pci_unregister_driver(&igb_driver);
700 }
701
702 module_exit(igb_exit_module);
703
704 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705 /**
706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
708 *
709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
711 **/
712 static void igb_cache_ring_register(struct igb_adapter *adapter)
713 {
714 int i = 0, j = 0;
715 u32 rbase_offset = adapter->vfs_allocated_count;
716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
724 if (adapter->vfs_allocated_count) {
725 for (; i < adapter->rss_queues; i++)
726 adapter->rx_ring[i]->reg_idx = rbase_offset +
727 Q_IDX_82576(i);
728 }
729 /* Fall through */
730 case e1000_82575:
731 case e1000_82580:
732 case e1000_i350:
733 case e1000_i354:
734 case e1000_i210:
735 case e1000_i211:
736 /* Fall through */
737 default:
738 for (; i < adapter->num_rx_queues; i++)
739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
740 for (; j < adapter->num_tx_queues; j++)
741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
742 break;
743 }
744 }
745
746 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747 {
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766 }
767
768 /**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782 {
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792 }
793
794 #define IGB_N0_QUEUE -1
795 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
796 {
797 struct igb_adapter *adapter = q_vector->adapter;
798 struct e1000_hw *hw = &adapter->hw;
799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
801 u32 msixbm = 0;
802
803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
807
808 switch (hw->mac.type) {
809 case e1000_82575:
810 /* The 82575 assigns vectors using a bitmask, which matches the
811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
815 if (rx_queue > IGB_N0_QUEUE)
816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
817 if (tx_queue > IGB_N0_QUEUE)
818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
820 msixbm |= E1000_EIMS_OTHER;
821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
822 q_vector->eims_value = msixbm;
823 break;
824 case e1000_82576:
825 /* 82576 uses a table that essentially consists of 2 columns
826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
838 q_vector->eims_value = 1 << msix_vector;
839 break;
840 case e1000_82580:
841 case e1000_i350:
842 case e1000_i354:
843 case e1000_i210:
844 case e1000_i211:
845 /* On 82580 and newer adapters the scheme is similar to 82576
846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
859 q_vector->eims_value = 1 << msix_vector;
860 break;
861 default:
862 BUG();
863 break;
864 }
865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
871 }
872
873 /**
874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
876 *
877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
879 **/
880 static void igb_configure_msix(struct igb_adapter *adapter)
881 {
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
887
888 /* set vector for other causes, i.e. link changes */
889 switch (hw->mac.type) {
890 case e1000_82575:
891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
900
901 /* enable msix_other interrupt */
902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
903 adapter->eims_other = E1000_EIMS_OTHER;
904
905 break;
906
907 case e1000_82576:
908 case e1000_82580:
909 case e1000_i350:
910 case e1000_i354:
911 case e1000_i210:
912 case e1000_i211:
913 /* Turn on MSI-X capability first, or our settings
914 * won't stick. And it will take days to debug.
915 */
916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
923
924 wr32(E1000_IVAR_MISC, tmp);
925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
935
936 wrfl();
937 }
938
939 /**
940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
942 *
943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
945 **/
946 static int igb_request_msix(struct igb_adapter *adapter)
947 {
948 struct net_device *netdev = adapter->netdev;
949 int i, err = 0, vector = 0, free_vector = 0;
950
951 err = request_irq(adapter->msix_entries[vector].vector,
952 igb_msix_other, 0, netdev->name, adapter);
953 if (err)
954 goto err_out;
955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
959 vector++;
960
961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
962
963 if (q_vector->rx.ring && q_vector->tx.ring)
964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
971 q_vector->rx.ring->queue_index);
972 else
973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
975 err = request_irq(adapter->msix_entries[vector].vector,
976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
978 if (err)
979 goto err_free;
980 }
981
982 igb_configure_msix(adapter);
983 return 0;
984
985 err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994 err_out:
995 return err;
996 }
997
998 /**
999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
1002 *
1003 * This function frees the memory allocated to the q_vector.
1004 **/
1005 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006 {
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
1016 }
1017
1018 /**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027 {
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1041
1042 netif_napi_del(&q_vector->napi);
1043
1044 }
1045
1046 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047 {
1048 int v_idx = adapter->num_q_vectors;
1049
1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1051 pci_disable_msix(adapter->pdev);
1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1053 pci_disable_msi(adapter->pdev);
1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
1057 }
1058
1059 /**
1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
1062 *
1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
1066 **/
1067 static void igb_free_q_vectors(struct igb_adapter *adapter)
1068 {
1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
1073 adapter->num_q_vectors = 0;
1074
1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
1077 igb_free_q_vector(adapter, v_idx);
1078 }
1079 }
1080
1081 /**
1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
1084 *
1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
1087 */
1088 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089 {
1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092 }
1093
1094 /**
1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
1098 *
1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
1101 **/
1102 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1103 {
1104 int err;
1105 int numvecs, i;
1106
1107 if (!msix)
1108 goto msi_only;
1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
1110
1111 /* Number of supported queues. */
1112 adapter->num_rx_queues = adapter->rss_queues;
1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
1117
1118 /* start with one vector for every Rx queue */
1119 numvecs = adapter->num_rx_queues;
1120
1121 /* if Tx handler is separate add 1 for every Tx queue */
1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
1138 return;
1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143 msi_only:
1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1145 #ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1156 wrfl();
1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160 #endif
1161 adapter->vfs_allocated_count = 0;
1162 adapter->rss_queues = 1;
1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1164 adapter->num_rx_queues = 1;
1165 adapter->num_tx_queues = 1;
1166 adapter->num_q_vectors = 1;
1167 if (!pci_enable_msi(adapter->pdev))
1168 adapter->flags |= IGB_FLAG_HAS_MSI;
1169 }
1170
1171 static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173 {
1174 head->ring = ring;
1175 head->count++;
1176 }
1177
1178 /**
1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
1187 *
1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1189 **/
1190 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
1194 {
1195 struct igb_q_vector *q_vector;
1196 struct igb_ring *ring;
1197 int ring_count, size;
1198
1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
1208 q_vector = adapter->q_vector[v_idx];
1209 if (!q_vector) {
1210 q_vector = kzalloc(size, GFP_KERNEL);
1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
1215 memset(q_vector, 0, size);
1216 }
1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
1276 }
1277
1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
1282
1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
1285
1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
1288
1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1292
1293 /* On i350, i354, i210, and i211, loopback VLAN packets
1294 * have the tag byte-swapped.
1295 */
1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1298
1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
1303 u64_stats_init(&ring->rx_syncp);
1304
1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
1310 }
1311
1312
1313 /**
1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
1316 *
1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
1319 **/
1320 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1321 {
1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
1327
1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
1332
1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
1339 }
1340 }
1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1345
1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
1359 return 0;
1360
1361 err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
1370 }
1371
1372 /**
1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
1376 *
1377 * This function initializes the interrupts and allocates all of the queues.
1378 **/
1379 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1380 {
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
1384 igb_set_interrupt_capability(adapter, msix);
1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
1392 igb_cache_ring_register(adapter);
1393
1394 return 0;
1395
1396 err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399 }
1400
1401 /**
1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
1404 *
1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
1407 **/
1408 static int igb_request_irq(struct igb_adapter *adapter)
1409 {
1410 struct net_device *netdev = adapter->netdev;
1411 struct pci_dev *pdev = adapter->pdev;
1412 int err = 0;
1413
1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1415 err = igb_request_msix(adapter);
1416 if (!err)
1417 goto request_done;
1418 /* fall back to MSI */
1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
1421
1422 igb_clear_interrupt_scheme(adapter);
1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
1425 goto request_done;
1426
1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
1429 igb_configure(adapter);
1430 }
1431
1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
1436 netdev->name, adapter);
1437 if (!err)
1438 goto request_done;
1439
1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1443 }
1444
1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1446 netdev->name, adapter);
1447
1448 if (err)
1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1450 err);
1451
1452 request_done:
1453 return err;
1454 }
1455
1456 static void igb_free_irq(struct igb_adapter *adapter)
1457 {
1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1459 int vector = 0, i;
1460
1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
1462
1463 for (i = 0; i < adapter->num_q_vectors; i++)
1464 free_irq(adapter->msix_entries[vector++].vector,
1465 adapter->q_vector[i]);
1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
1468 }
1469 }
1470
1471 /**
1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
1474 **/
1475 static void igb_irq_disable(struct igb_adapter *adapter)
1476 {
1477 struct e1000_hw *hw = &adapter->hw;
1478
1479 /* we need to be careful when disabling interrupts. The VFs are also
1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1484 u32 regval = rd32(E1000_EIAM);
1485
1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1490 }
1491
1492 wr32(E1000_IAM, 0);
1493 wr32(E1000_IMC, ~0);
1494 wrfl();
1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1496 int i;
1497
1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
1503 }
1504
1505 /**
1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
1508 **/
1509 static void igb_irq_enable(struct igb_adapter *adapter)
1510 {
1511 struct e1000_hw *hw = &adapter->hw;
1512
1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1515 u32 regval = rd32(E1000_EIAC);
1516
1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
1521 if (adapter->vfs_allocated_count) {
1522 wr32(E1000_MBVFIMR, 0xFF);
1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
1526 } else {
1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
1531 }
1532 }
1533
1534 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535 {
1536 struct e1000_hw *hw = &adapter->hw;
1537 u16 pf_id = adapter->vfs_allocated_count;
1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
1543 igb_vfta_set(hw, vid, pf_id, true, true);
1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
1551 !test_bit(old_vid, adapter->active_vlans)) {
1552 /* remove VID from filter table */
1553 igb_vfta_set(hw, vid, pf_id, false, true);
1554 }
1555 }
1556
1557 /**
1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
1560 *
1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
1564 **/
1565 static void igb_release_hw_control(struct igb_adapter *adapter)
1566 {
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574 }
1575
1576 /**
1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
1579 *
1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
1583 **/
1584 static void igb_get_hw_control(struct igb_adapter *adapter)
1585 {
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593 }
1594
1595 /**
1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
1598 **/
1599 static void igb_configure(struct igb_adapter *adapter)
1600 {
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
1605 igb_set_rx_mode(netdev);
1606
1607 igb_restore_vlan(adapter);
1608
1609 igb_setup_tctl(adapter);
1610 igb_setup_mrqc(adapter);
1611 igb_setup_rctl(adapter);
1612
1613 igb_configure_tx(adapter);
1614 igb_configure_rx(adapter);
1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
1618 /* call igb_desc_unused which always leaves
1619 * at least 1 descriptor unused to make sure
1620 * next_to_use != next_to_clean
1621 */
1622 for (i = 0; i < adapter->num_rx_queues; i++) {
1623 struct igb_ring *ring = adapter->rx_ring[i];
1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1625 }
1626 }
1627
1628 /**
1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
1631 **/
1632 void igb_power_up_link(struct igb_adapter *adapter)
1633 {
1634 igb_reset_phy(&adapter->hw);
1635
1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
1640
1641 igb_setup_link(&adapter->hw);
1642 }
1643
1644 /**
1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
1647 */
1648 static void igb_power_down_link(struct igb_adapter *adapter)
1649 {
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654 }
1655
1656 /**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660 static void igb_check_swap_media(struct igb_adapter *adapter)
1661 {
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721 }
1722
1723 /**
1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
1726 **/
1727 int igb_up(struct igb_adapter *adapter)
1728 {
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1741 igb_configure_msix(adapter);
1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
1752
1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
1757 netif_tx_start_all_queues(adapter->netdev);
1758
1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
1767 return 0;
1768 }
1769
1770 void igb_down(struct igb_adapter *adapter)
1771 {
1772 struct net_device *netdev = adapter->netdev;
1773 struct e1000_hw *hw = &adapter->hw;
1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
1778 * reschedule our watchdog timer
1779 */
1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
1787 netif_carrier_off(netdev);
1788 netif_tx_stop_all_queues(netdev);
1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
1796 usleep_range(10000, 11000);
1797
1798 igb_irq_disable(adapter);
1799
1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
1802 for (i = 0; i < adapter->num_q_vectors; i++) {
1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
1807 }
1808
1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
1812 /* record the stats before reset*/
1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
1816
1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
1822
1823 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1824 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1825
1826 igb_clean_all_tx_rings(adapter);
1827 igb_clean_all_rx_rings(adapter);
1828 #ifdef CONFIG_IGB_DCA
1829
1830 /* since we reset the hardware DCA settings were cleared */
1831 igb_setup_dca(adapter);
1832 #endif
1833 }
1834
1835 void igb_reinit_locked(struct igb_adapter *adapter)
1836 {
1837 WARN_ON(in_interrupt());
1838 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1839 usleep_range(1000, 2000);
1840 igb_down(adapter);
1841 igb_up(adapter);
1842 clear_bit(__IGB_RESETTING, &adapter->state);
1843 }
1844
1845 /** igb_enable_mas - Media Autosense re-enable after swap
1846 *
1847 * @adapter: adapter struct
1848 **/
1849 static void igb_enable_mas(struct igb_adapter *adapter)
1850 {
1851 struct e1000_hw *hw = &adapter->hw;
1852 u32 connsw = rd32(E1000_CONNSW);
1853
1854 /* configure for SerDes media detect */
1855 if ((hw->phy.media_type == e1000_media_type_copper) &&
1856 (!(connsw & E1000_CONNSW_SERDESD))) {
1857 connsw |= E1000_CONNSW_ENRGSRC;
1858 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1859 wr32(E1000_CONNSW, connsw);
1860 wrfl();
1861 }
1862 }
1863
1864 void igb_reset(struct igb_adapter *adapter)
1865 {
1866 struct pci_dev *pdev = adapter->pdev;
1867 struct e1000_hw *hw = &adapter->hw;
1868 struct e1000_mac_info *mac = &hw->mac;
1869 struct e1000_fc_info *fc = &hw->fc;
1870 u32 pba, hwm;
1871
1872 /* Repartition Pba for greater than 9k mtu
1873 * To take effect CTRL.RST is required.
1874 */
1875 switch (mac->type) {
1876 case e1000_i350:
1877 case e1000_i354:
1878 case e1000_82580:
1879 pba = rd32(E1000_RXPBS);
1880 pba = igb_rxpbs_adjust_82580(pba);
1881 break;
1882 case e1000_82576:
1883 pba = rd32(E1000_RXPBS);
1884 pba &= E1000_RXPBS_SIZE_MASK_82576;
1885 break;
1886 case e1000_82575:
1887 case e1000_i210:
1888 case e1000_i211:
1889 default:
1890 pba = E1000_PBA_34K;
1891 break;
1892 }
1893
1894 if (mac->type == e1000_82575) {
1895 u32 min_rx_space, min_tx_space, needed_tx_space;
1896
1897 /* write Rx PBA so that hardware can report correct Tx PBA */
1898 wr32(E1000_PBA, pba);
1899
1900 /* To maintain wire speed transmits, the Tx FIFO should be
1901 * large enough to accommodate two full transmit packets,
1902 * rounded up to the next 1KB and expressed in KB. Likewise,
1903 * the Rx FIFO should be large enough to accommodate at least
1904 * one full receive packet and is similarly rounded up and
1905 * expressed in KB.
1906 */
1907 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1908
1909 /* The Tx FIFO also stores 16 bytes of information about the Tx
1910 * but don't include Ethernet FCS because hardware appends it.
1911 * We only need to round down to the nearest 512 byte block
1912 * count since the value we care about is 2 frames, not 1.
1913 */
1914 min_tx_space = adapter->max_frame_size;
1915 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1916 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1917
1918 /* upper 16 bits has Tx packet buffer allocation size in KB */
1919 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
1920
1921 /* If current Tx allocation is less than the min Tx FIFO size,
1922 * and the min Tx FIFO size is less than the current Rx FIFO
1923 * allocation, take space away from current Rx allocation.
1924 */
1925 if (needed_tx_space < pba) {
1926 pba -= needed_tx_space;
1927
1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
1934
1935 /* adjust PBA for jumbo frames */
1936 wr32(E1000_PBA, pba);
1937 }
1938
1939 /* flow control settings
1940 * The high water mark must be low enough to fit one full frame
1941 * after transmitting the pause frame. As such we must have enough
1942 * space to allow for us to complete our current transmit and then
1943 * receive the frame that is in progress from the link partner.
1944 * Set it to:
1945 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
1946 */
1947 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
1948
1949 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1950 fc->low_water = fc->high_water - 16;
1951 fc->pause_time = 0xFFFF;
1952 fc->send_xon = 1;
1953 fc->current_mode = fc->requested_mode;
1954
1955 /* disable receive for all VFs and wait one second */
1956 if (adapter->vfs_allocated_count) {
1957 int i;
1958
1959 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1960 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1961
1962 /* ping all the active vfs to let them know we are going down */
1963 igb_ping_all_vfs(adapter);
1964
1965 /* disable transmits and receives */
1966 wr32(E1000_VFRE, 0);
1967 wr32(E1000_VFTE, 0);
1968 }
1969
1970 /* Allow time for pending master requests to run */
1971 hw->mac.ops.reset_hw(hw);
1972 wr32(E1000_WUC, 0);
1973
1974 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1975 /* need to resetup here after media swap */
1976 adapter->ei.get_invariants(hw);
1977 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1978 }
1979 if ((mac->type == e1000_82575) &&
1980 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1981 igb_enable_mas(adapter);
1982 }
1983 if (hw->mac.ops.init_hw(hw))
1984 dev_err(&pdev->dev, "Hardware Error\n");
1985
1986 /* Flow control settings reset on hardware reset, so guarantee flow
1987 * control is off when forcing speed.
1988 */
1989 if (!hw->mac.autoneg)
1990 igb_force_mac_fc(hw);
1991
1992 igb_init_dmac(adapter, pba);
1993 #ifdef CONFIG_IGB_HWMON
1994 /* Re-initialize the thermal sensor on i350 devices. */
1995 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1996 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1997 /* If present, re-initialize the external thermal sensor
1998 * interface.
1999 */
2000 if (adapter->ets)
2001 mac->ops.init_thermal_sensor_thresh(hw);
2002 }
2003 }
2004 #endif
2005 /* Re-establish EEE setting */
2006 if (hw->phy.media_type == e1000_media_type_copper) {
2007 switch (mac->type) {
2008 case e1000_i350:
2009 case e1000_i210:
2010 case e1000_i211:
2011 igb_set_eee_i350(hw, true, true);
2012 break;
2013 case e1000_i354:
2014 igb_set_eee_i354(hw, true, true);
2015 break;
2016 default:
2017 break;
2018 }
2019 }
2020 if (!netif_running(adapter->netdev))
2021 igb_power_down_link(adapter);
2022
2023 igb_update_mng_vlan(adapter);
2024
2025 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2026 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2027
2028 /* Re-enable PTP, where applicable. */
2029 igb_ptp_reset(adapter);
2030
2031 igb_get_phy_info(hw);
2032 }
2033
2034 static netdev_features_t igb_fix_features(struct net_device *netdev,
2035 netdev_features_t features)
2036 {
2037 /* Since there is no support for separate Rx/Tx vlan accel
2038 * enable/disable make sure Tx flag is always in same state as Rx.
2039 */
2040 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2041 features |= NETIF_F_HW_VLAN_CTAG_TX;
2042 else
2043 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2044
2045 return features;
2046 }
2047
2048 static int igb_set_features(struct net_device *netdev,
2049 netdev_features_t features)
2050 {
2051 netdev_features_t changed = netdev->features ^ features;
2052 struct igb_adapter *adapter = netdev_priv(netdev);
2053
2054 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2055 igb_vlan_mode(netdev, features);
2056
2057 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2058 return 0;
2059
2060 netdev->features = features;
2061
2062 if (netif_running(netdev))
2063 igb_reinit_locked(adapter);
2064 else
2065 igb_reset(adapter);
2066
2067 return 0;
2068 }
2069
2070 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2071 struct net_device *dev,
2072 const unsigned char *addr, u16 vid,
2073 u16 flags)
2074 {
2075 /* guarantee we can provide a unique filter for the unicast address */
2076 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2077 struct igb_adapter *adapter = netdev_priv(dev);
2078 struct e1000_hw *hw = &adapter->hw;
2079 int vfn = adapter->vfs_allocated_count;
2080 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2081
2082 if (netdev_uc_count(dev) >= rar_entries)
2083 return -ENOMEM;
2084 }
2085
2086 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2087 }
2088
2089 static const struct net_device_ops igb_netdev_ops = {
2090 .ndo_open = igb_open,
2091 .ndo_stop = igb_close,
2092 .ndo_start_xmit = igb_xmit_frame,
2093 .ndo_get_stats64 = igb_get_stats64,
2094 .ndo_set_rx_mode = igb_set_rx_mode,
2095 .ndo_set_mac_address = igb_set_mac,
2096 .ndo_change_mtu = igb_change_mtu,
2097 .ndo_do_ioctl = igb_ioctl,
2098 .ndo_tx_timeout = igb_tx_timeout,
2099 .ndo_validate_addr = eth_validate_addr,
2100 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2101 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2102 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2103 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2104 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2105 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2106 .ndo_get_vf_config = igb_ndo_get_vf_config,
2107 #ifdef CONFIG_NET_POLL_CONTROLLER
2108 .ndo_poll_controller = igb_netpoll,
2109 #endif
2110 .ndo_fix_features = igb_fix_features,
2111 .ndo_set_features = igb_set_features,
2112 .ndo_fdb_add = igb_ndo_fdb_add,
2113 .ndo_features_check = passthru_features_check,
2114 };
2115
2116 /**
2117 * igb_set_fw_version - Configure version string for ethtool
2118 * @adapter: adapter struct
2119 **/
2120 void igb_set_fw_version(struct igb_adapter *adapter)
2121 {
2122 struct e1000_hw *hw = &adapter->hw;
2123 struct e1000_fw_version fw;
2124
2125 igb_get_fw_version(hw, &fw);
2126
2127 switch (hw->mac.type) {
2128 case e1000_i210:
2129 case e1000_i211:
2130 if (!(igb_get_flash_presence_i210(hw))) {
2131 snprintf(adapter->fw_version,
2132 sizeof(adapter->fw_version),
2133 "%2d.%2d-%d",
2134 fw.invm_major, fw.invm_minor,
2135 fw.invm_img_type);
2136 break;
2137 }
2138 /* fall through */
2139 default:
2140 /* if option is rom valid, display its version too */
2141 if (fw.or_valid) {
2142 snprintf(adapter->fw_version,
2143 sizeof(adapter->fw_version),
2144 "%d.%d, 0x%08x, %d.%d.%d",
2145 fw.eep_major, fw.eep_minor, fw.etrack_id,
2146 fw.or_major, fw.or_build, fw.or_patch);
2147 /* no option rom */
2148 } else if (fw.etrack_id != 0X0000) {
2149 snprintf(adapter->fw_version,
2150 sizeof(adapter->fw_version),
2151 "%d.%d, 0x%08x",
2152 fw.eep_major, fw.eep_minor, fw.etrack_id);
2153 } else {
2154 snprintf(adapter->fw_version,
2155 sizeof(adapter->fw_version),
2156 "%d.%d.%d",
2157 fw.eep_major, fw.eep_minor, fw.eep_build);
2158 }
2159 break;
2160 }
2161 }
2162
2163 /**
2164 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2165 *
2166 * @adapter: adapter struct
2167 **/
2168 static void igb_init_mas(struct igb_adapter *adapter)
2169 {
2170 struct e1000_hw *hw = &adapter->hw;
2171 u16 eeprom_data;
2172
2173 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2174 switch (hw->bus.func) {
2175 case E1000_FUNC_0:
2176 if (eeprom_data & IGB_MAS_ENABLE_0) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 case E1000_FUNC_1:
2184 if (eeprom_data & IGB_MAS_ENABLE_1) {
2185 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2186 netdev_info(adapter->netdev,
2187 "MAS: Enabling Media Autosense for port %d\n",
2188 hw->bus.func);
2189 }
2190 break;
2191 case E1000_FUNC_2:
2192 if (eeprom_data & IGB_MAS_ENABLE_2) {
2193 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2194 netdev_info(adapter->netdev,
2195 "MAS: Enabling Media Autosense for port %d\n",
2196 hw->bus.func);
2197 }
2198 break;
2199 case E1000_FUNC_3:
2200 if (eeprom_data & IGB_MAS_ENABLE_3) {
2201 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2202 netdev_info(adapter->netdev,
2203 "MAS: Enabling Media Autosense for port %d\n",
2204 hw->bus.func);
2205 }
2206 break;
2207 default:
2208 /* Shouldn't get here */
2209 netdev_err(adapter->netdev,
2210 "MAS: Invalid port configuration, returning\n");
2211 break;
2212 }
2213 }
2214
2215 /**
2216 * igb_init_i2c - Init I2C interface
2217 * @adapter: pointer to adapter structure
2218 **/
2219 static s32 igb_init_i2c(struct igb_adapter *adapter)
2220 {
2221 s32 status = 0;
2222
2223 /* I2C interface supported on i350 devices */
2224 if (adapter->hw.mac.type != e1000_i350)
2225 return 0;
2226
2227 /* Initialize the i2c bus which is controlled by the registers.
2228 * This bus will use the i2c_algo_bit structue that implements
2229 * the protocol through toggling of the 4 bits in the register.
2230 */
2231 adapter->i2c_adap.owner = THIS_MODULE;
2232 adapter->i2c_algo = igb_i2c_algo;
2233 adapter->i2c_algo.data = adapter;
2234 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2235 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2236 strlcpy(adapter->i2c_adap.name, "igb BB",
2237 sizeof(adapter->i2c_adap.name));
2238 status = i2c_bit_add_bus(&adapter->i2c_adap);
2239 return status;
2240 }
2241
2242 /**
2243 * igb_probe - Device Initialization Routine
2244 * @pdev: PCI device information struct
2245 * @ent: entry in igb_pci_tbl
2246 *
2247 * Returns 0 on success, negative on failure
2248 *
2249 * igb_probe initializes an adapter identified by a pci_dev structure.
2250 * The OS initialization, configuring of the adapter private structure,
2251 * and a hardware reset occur.
2252 **/
2253 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2254 {
2255 struct net_device *netdev;
2256 struct igb_adapter *adapter;
2257 struct e1000_hw *hw;
2258 u16 eeprom_data = 0;
2259 s32 ret_val;
2260 static int global_quad_port_a; /* global quad port a indication */
2261 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2262 int err, pci_using_dac;
2263 u8 part_str[E1000_PBANUM_LENGTH];
2264
2265 /* Catch broken hardware that put the wrong VF device ID in
2266 * the PCIe SR-IOV capability.
2267 */
2268 if (pdev->is_virtfn) {
2269 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2270 pci_name(pdev), pdev->vendor, pdev->device);
2271 return -EINVAL;
2272 }
2273
2274 err = pci_enable_device_mem(pdev);
2275 if (err)
2276 return err;
2277
2278 pci_using_dac = 0;
2279 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2280 if (!err) {
2281 pci_using_dac = 1;
2282 } else {
2283 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2284 if (err) {
2285 dev_err(&pdev->dev,
2286 "No usable DMA configuration, aborting\n");
2287 goto err_dma;
2288 }
2289 }
2290
2291 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2292 IORESOURCE_MEM),
2293 igb_driver_name);
2294 if (err)
2295 goto err_pci_reg;
2296
2297 pci_enable_pcie_error_reporting(pdev);
2298
2299 pci_set_master(pdev);
2300 pci_save_state(pdev);
2301
2302 err = -ENOMEM;
2303 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2304 IGB_MAX_TX_QUEUES);
2305 if (!netdev)
2306 goto err_alloc_etherdev;
2307
2308 SET_NETDEV_DEV(netdev, &pdev->dev);
2309
2310 pci_set_drvdata(pdev, netdev);
2311 adapter = netdev_priv(netdev);
2312 adapter->netdev = netdev;
2313 adapter->pdev = pdev;
2314 hw = &adapter->hw;
2315 hw->back = adapter;
2316 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2317
2318 err = -EIO;
2319 adapter->io_addr = pci_iomap(pdev, 0, 0);
2320 if (!adapter->io_addr)
2321 goto err_ioremap;
2322 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2323 hw->hw_addr = adapter->io_addr;
2324
2325 netdev->netdev_ops = &igb_netdev_ops;
2326 igb_set_ethtool_ops(netdev);
2327 netdev->watchdog_timeo = 5 * HZ;
2328
2329 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2330
2331 netdev->mem_start = pci_resource_start(pdev, 0);
2332 netdev->mem_end = pci_resource_end(pdev, 0);
2333
2334 /* PCI config space info */
2335 hw->vendor_id = pdev->vendor;
2336 hw->device_id = pdev->device;
2337 hw->revision_id = pdev->revision;
2338 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2339 hw->subsystem_device_id = pdev->subsystem_device;
2340
2341 /* Copy the default MAC, PHY and NVM function pointers */
2342 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2343 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2344 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2345 /* Initialize skew-specific constants */
2346 err = ei->get_invariants(hw);
2347 if (err)
2348 goto err_sw_init;
2349
2350 /* setup the private structure */
2351 err = igb_sw_init(adapter);
2352 if (err)
2353 goto err_sw_init;
2354
2355 igb_get_bus_info_pcie(hw);
2356
2357 hw->phy.autoneg_wait_to_complete = false;
2358
2359 /* Copper options */
2360 if (hw->phy.media_type == e1000_media_type_copper) {
2361 hw->phy.mdix = AUTO_ALL_MODES;
2362 hw->phy.disable_polarity_correction = false;
2363 hw->phy.ms_type = e1000_ms_hw_default;
2364 }
2365
2366 if (igb_check_reset_block(hw))
2367 dev_info(&pdev->dev,
2368 "PHY reset is blocked due to SOL/IDER session.\n");
2369
2370 /* features is initialized to 0 in allocation, it might have bits
2371 * set by igb_sw_init so we should use an or instead of an
2372 * assignment.
2373 */
2374 netdev->features |= NETIF_F_SG |
2375 NETIF_F_TSO |
2376 NETIF_F_TSO6 |
2377 NETIF_F_RXHASH |
2378 NETIF_F_RXCSUM |
2379 NETIF_F_HW_CSUM |
2380 NETIF_F_HW_VLAN_CTAG_RX |
2381 NETIF_F_HW_VLAN_CTAG_TX;
2382
2383 if (hw->mac.type >= e1000_82576)
2384 netdev->features |= NETIF_F_SCTP_CRC;
2385
2386 /* copy netdev features into list of user selectable features */
2387 netdev->hw_features |= netdev->features;
2388 netdev->hw_features |= NETIF_F_RXALL;
2389
2390 if (hw->mac.type >= e1000_i350)
2391 netdev->hw_features |= NETIF_F_NTUPLE;
2392
2393 /* set this bit last since it cannot be part of hw_features */
2394 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2395
2396 netdev->vlan_features |= NETIF_F_SG |
2397 NETIF_F_TSO |
2398 NETIF_F_TSO6 |
2399 NETIF_F_HW_CSUM |
2400 NETIF_F_SCTP_CRC;
2401
2402 netdev->mpls_features |= NETIF_F_HW_CSUM;
2403 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
2404
2405 netdev->priv_flags |= IFF_SUPP_NOFCS;
2406
2407 if (pci_using_dac) {
2408 netdev->features |= NETIF_F_HIGHDMA;
2409 netdev->vlan_features |= NETIF_F_HIGHDMA;
2410 }
2411
2412 netdev->priv_flags |= IFF_UNICAST_FLT;
2413
2414 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2415
2416 /* before reading the NVM, reset the controller to put the device in a
2417 * known good starting state
2418 */
2419 hw->mac.ops.reset_hw(hw);
2420
2421 /* make sure the NVM is good , i211/i210 parts can have special NVM
2422 * that doesn't contain a checksum
2423 */
2424 switch (hw->mac.type) {
2425 case e1000_i210:
2426 case e1000_i211:
2427 if (igb_get_flash_presence_i210(hw)) {
2428 if (hw->nvm.ops.validate(hw) < 0) {
2429 dev_err(&pdev->dev,
2430 "The NVM Checksum Is Not Valid\n");
2431 err = -EIO;
2432 goto err_eeprom;
2433 }
2434 }
2435 break;
2436 default:
2437 if (hw->nvm.ops.validate(hw) < 0) {
2438 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2439 err = -EIO;
2440 goto err_eeprom;
2441 }
2442 break;
2443 }
2444
2445 /* copy the MAC address out of the NVM */
2446 if (hw->mac.ops.read_mac_addr(hw))
2447 dev_err(&pdev->dev, "NVM Read Error\n");
2448
2449 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2450
2451 if (!is_valid_ether_addr(netdev->dev_addr)) {
2452 dev_err(&pdev->dev, "Invalid MAC Address\n");
2453 err = -EIO;
2454 goto err_eeprom;
2455 }
2456
2457 /* get firmware version for ethtool -i */
2458 igb_set_fw_version(adapter);
2459
2460 /* configure RXPBSIZE and TXPBSIZE */
2461 if (hw->mac.type == e1000_i210) {
2462 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2463 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2464 }
2465
2466 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2467 (unsigned long) adapter);
2468 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2469 (unsigned long) adapter);
2470
2471 INIT_WORK(&adapter->reset_task, igb_reset_task);
2472 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2473
2474 /* Initialize link properties that are user-changeable */
2475 adapter->fc_autoneg = true;
2476 hw->mac.autoneg = true;
2477 hw->phy.autoneg_advertised = 0x2f;
2478
2479 hw->fc.requested_mode = e1000_fc_default;
2480 hw->fc.current_mode = e1000_fc_default;
2481
2482 igb_validate_mdi_setting(hw);
2483
2484 /* By default, support wake on port A */
2485 if (hw->bus.func == 0)
2486 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2487
2488 /* Check the NVM for wake support on non-port A ports */
2489 if (hw->mac.type >= e1000_82580)
2490 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2491 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2492 &eeprom_data);
2493 else if (hw->bus.func == 1)
2494 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2495
2496 if (eeprom_data & IGB_EEPROM_APME)
2497 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2498
2499 /* now that we have the eeprom settings, apply the special cases where
2500 * the eeprom may be wrong or the board simply won't support wake on
2501 * lan on a particular port
2502 */
2503 switch (pdev->device) {
2504 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2505 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2506 break;
2507 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2508 case E1000_DEV_ID_82576_FIBER:
2509 case E1000_DEV_ID_82576_SERDES:
2510 /* Wake events only supported on port A for dual fiber
2511 * regardless of eeprom setting
2512 */
2513 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2514 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2515 break;
2516 case E1000_DEV_ID_82576_QUAD_COPPER:
2517 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2518 /* if quad port adapter, disable WoL on all but port A */
2519 if (global_quad_port_a != 0)
2520 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2521 else
2522 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2523 /* Reset for multiple quad port adapters */
2524 if (++global_quad_port_a == 4)
2525 global_quad_port_a = 0;
2526 break;
2527 default:
2528 /* If the device can't wake, don't set software support */
2529 if (!device_can_wakeup(&adapter->pdev->dev))
2530 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2531 }
2532
2533 /* initialize the wol settings based on the eeprom settings */
2534 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2535 adapter->wol |= E1000_WUFC_MAG;
2536
2537 /* Some vendors want WoL disabled by default, but still supported */
2538 if ((hw->mac.type == e1000_i350) &&
2539 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2540 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2541 adapter->wol = 0;
2542 }
2543
2544 /* Some vendors want the ability to Use the EEPROM setting as
2545 * enable/disable only, and not for capability
2546 */
2547 if (((hw->mac.type == e1000_i350) ||
2548 (hw->mac.type == e1000_i354)) &&
2549 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
2550 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2551 adapter->wol = 0;
2552 }
2553 if (hw->mac.type == e1000_i350) {
2554 if (((pdev->subsystem_device == 0x5001) ||
2555 (pdev->subsystem_device == 0x5002)) &&
2556 (hw->bus.func == 0)) {
2557 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2558 adapter->wol = 0;
2559 }
2560 if (pdev->subsystem_device == 0x1F52)
2561 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2562 }
2563
2564 device_set_wakeup_enable(&adapter->pdev->dev,
2565 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2566
2567 /* reset the hardware with the new settings */
2568 igb_reset(adapter);
2569
2570 /* Init the I2C interface */
2571 err = igb_init_i2c(adapter);
2572 if (err) {
2573 dev_err(&pdev->dev, "failed to init i2c interface\n");
2574 goto err_eeprom;
2575 }
2576
2577 /* let the f/w know that the h/w is now under the control of the
2578 * driver.
2579 */
2580 igb_get_hw_control(adapter);
2581
2582 strcpy(netdev->name, "eth%d");
2583 err = register_netdev(netdev);
2584 if (err)
2585 goto err_register;
2586
2587 /* carrier off reporting is important to ethtool even BEFORE open */
2588 netif_carrier_off(netdev);
2589
2590 #ifdef CONFIG_IGB_DCA
2591 if (dca_add_requester(&pdev->dev) == 0) {
2592 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2593 dev_info(&pdev->dev, "DCA enabled\n");
2594 igb_setup_dca(adapter);
2595 }
2596
2597 #endif
2598 #ifdef CONFIG_IGB_HWMON
2599 /* Initialize the thermal sensor on i350 devices. */
2600 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2601 u16 ets_word;
2602
2603 /* Read the NVM to determine if this i350 device supports an
2604 * external thermal sensor.
2605 */
2606 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2607 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2608 adapter->ets = true;
2609 else
2610 adapter->ets = false;
2611 if (igb_sysfs_init(adapter))
2612 dev_err(&pdev->dev,
2613 "failed to allocate sysfs resources\n");
2614 } else {
2615 adapter->ets = false;
2616 }
2617 #endif
2618 /* Check if Media Autosense is enabled */
2619 adapter->ei = *ei;
2620 if (hw->dev_spec._82575.mas_capable)
2621 igb_init_mas(adapter);
2622
2623 /* do hw tstamp init after resetting */
2624 igb_ptp_init(adapter);
2625
2626 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2627 /* print bus type/speed/width info, not applicable to i354 */
2628 if (hw->mac.type != e1000_i354) {
2629 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2630 netdev->name,
2631 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2632 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2633 "unknown"),
2634 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2635 "Width x4" :
2636 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2637 "Width x2" :
2638 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2639 "Width x1" : "unknown"), netdev->dev_addr);
2640 }
2641
2642 if ((hw->mac.type >= e1000_i210 ||
2643 igb_get_flash_presence_i210(hw))) {
2644 ret_val = igb_read_part_string(hw, part_str,
2645 E1000_PBANUM_LENGTH);
2646 } else {
2647 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2648 }
2649
2650 if (ret_val)
2651 strcpy(part_str, "Unknown");
2652 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2653 dev_info(&pdev->dev,
2654 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2655 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2656 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2657 adapter->num_rx_queues, adapter->num_tx_queues);
2658 if (hw->phy.media_type == e1000_media_type_copper) {
2659 switch (hw->mac.type) {
2660 case e1000_i350:
2661 case e1000_i210:
2662 case e1000_i211:
2663 /* Enable EEE for internal copper PHY devices */
2664 err = igb_set_eee_i350(hw, true, true);
2665 if ((!err) &&
2666 (!hw->dev_spec._82575.eee_disable)) {
2667 adapter->eee_advert =
2668 MDIO_EEE_100TX | MDIO_EEE_1000T;
2669 adapter->flags |= IGB_FLAG_EEE;
2670 }
2671 break;
2672 case e1000_i354:
2673 if ((rd32(E1000_CTRL_EXT) &
2674 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2675 err = igb_set_eee_i354(hw, true, true);
2676 if ((!err) &&
2677 (!hw->dev_spec._82575.eee_disable)) {
2678 adapter->eee_advert =
2679 MDIO_EEE_100TX | MDIO_EEE_1000T;
2680 adapter->flags |= IGB_FLAG_EEE;
2681 }
2682 }
2683 break;
2684 default:
2685 break;
2686 }
2687 }
2688 pm_runtime_put_noidle(&pdev->dev);
2689 return 0;
2690
2691 err_register:
2692 igb_release_hw_control(adapter);
2693 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2694 err_eeprom:
2695 if (!igb_check_reset_block(hw))
2696 igb_reset_phy(hw);
2697
2698 if (hw->flash_address)
2699 iounmap(hw->flash_address);
2700 err_sw_init:
2701 kfree(adapter->shadow_vfta);
2702 igb_clear_interrupt_scheme(adapter);
2703 #ifdef CONFIG_PCI_IOV
2704 igb_disable_sriov(pdev);
2705 #endif
2706 pci_iounmap(pdev, adapter->io_addr);
2707 err_ioremap:
2708 free_netdev(netdev);
2709 err_alloc_etherdev:
2710 pci_release_selected_regions(pdev,
2711 pci_select_bars(pdev, IORESOURCE_MEM));
2712 err_pci_reg:
2713 err_dma:
2714 pci_disable_device(pdev);
2715 return err;
2716 }
2717
2718 #ifdef CONFIG_PCI_IOV
2719 static int igb_disable_sriov(struct pci_dev *pdev)
2720 {
2721 struct net_device *netdev = pci_get_drvdata(pdev);
2722 struct igb_adapter *adapter = netdev_priv(netdev);
2723 struct e1000_hw *hw = &adapter->hw;
2724
2725 /* reclaim resources allocated to VFs */
2726 if (adapter->vf_data) {
2727 /* disable iov and allow time for transactions to clear */
2728 if (pci_vfs_assigned(pdev)) {
2729 dev_warn(&pdev->dev,
2730 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2731 return -EPERM;
2732 } else {
2733 pci_disable_sriov(pdev);
2734 msleep(500);
2735 }
2736
2737 kfree(adapter->vf_data);
2738 adapter->vf_data = NULL;
2739 adapter->vfs_allocated_count = 0;
2740 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2741 wrfl();
2742 msleep(100);
2743 dev_info(&pdev->dev, "IOV Disabled\n");
2744
2745 /* Re-enable DMA Coalescing flag since IOV is turned off */
2746 adapter->flags |= IGB_FLAG_DMAC;
2747 }
2748
2749 return 0;
2750 }
2751
2752 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2753 {
2754 struct net_device *netdev = pci_get_drvdata(pdev);
2755 struct igb_adapter *adapter = netdev_priv(netdev);
2756 int old_vfs = pci_num_vf(pdev);
2757 int err = 0;
2758 int i;
2759
2760 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2761 err = -EPERM;
2762 goto out;
2763 }
2764 if (!num_vfs)
2765 goto out;
2766
2767 if (old_vfs) {
2768 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2769 old_vfs, max_vfs);
2770 adapter->vfs_allocated_count = old_vfs;
2771 } else
2772 adapter->vfs_allocated_count = num_vfs;
2773
2774 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2775 sizeof(struct vf_data_storage), GFP_KERNEL);
2776
2777 /* if allocation failed then we do not support SR-IOV */
2778 if (!adapter->vf_data) {
2779 adapter->vfs_allocated_count = 0;
2780 dev_err(&pdev->dev,
2781 "Unable to allocate memory for VF Data Storage\n");
2782 err = -ENOMEM;
2783 goto out;
2784 }
2785
2786 /* only call pci_enable_sriov() if no VFs are allocated already */
2787 if (!old_vfs) {
2788 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2789 if (err)
2790 goto err_out;
2791 }
2792 dev_info(&pdev->dev, "%d VFs allocated\n",
2793 adapter->vfs_allocated_count);
2794 for (i = 0; i < adapter->vfs_allocated_count; i++)
2795 igb_vf_configure(adapter, i);
2796
2797 /* DMA Coalescing is not supported in IOV mode. */
2798 adapter->flags &= ~IGB_FLAG_DMAC;
2799 goto out;
2800
2801 err_out:
2802 kfree(adapter->vf_data);
2803 adapter->vf_data = NULL;
2804 adapter->vfs_allocated_count = 0;
2805 out:
2806 return err;
2807 }
2808
2809 #endif
2810 /**
2811 * igb_remove_i2c - Cleanup I2C interface
2812 * @adapter: pointer to adapter structure
2813 **/
2814 static void igb_remove_i2c(struct igb_adapter *adapter)
2815 {
2816 /* free the adapter bus structure */
2817 i2c_del_adapter(&adapter->i2c_adap);
2818 }
2819
2820 /**
2821 * igb_remove - Device Removal Routine
2822 * @pdev: PCI device information struct
2823 *
2824 * igb_remove is called by the PCI subsystem to alert the driver
2825 * that it should release a PCI device. The could be caused by a
2826 * Hot-Plug event, or because the driver is going to be removed from
2827 * memory.
2828 **/
2829 static void igb_remove(struct pci_dev *pdev)
2830 {
2831 struct net_device *netdev = pci_get_drvdata(pdev);
2832 struct igb_adapter *adapter = netdev_priv(netdev);
2833 struct e1000_hw *hw = &adapter->hw;
2834
2835 pm_runtime_get_noresume(&pdev->dev);
2836 #ifdef CONFIG_IGB_HWMON
2837 igb_sysfs_exit(adapter);
2838 #endif
2839 igb_remove_i2c(adapter);
2840 igb_ptp_stop(adapter);
2841 /* The watchdog timer may be rescheduled, so explicitly
2842 * disable watchdog from being rescheduled.
2843 */
2844 set_bit(__IGB_DOWN, &adapter->state);
2845 del_timer_sync(&adapter->watchdog_timer);
2846 del_timer_sync(&adapter->phy_info_timer);
2847
2848 cancel_work_sync(&adapter->reset_task);
2849 cancel_work_sync(&adapter->watchdog_task);
2850
2851 #ifdef CONFIG_IGB_DCA
2852 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2853 dev_info(&pdev->dev, "DCA disabled\n");
2854 dca_remove_requester(&pdev->dev);
2855 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2856 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2857 }
2858 #endif
2859
2860 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2861 * would have already happened in close and is redundant.
2862 */
2863 igb_release_hw_control(adapter);
2864
2865 #ifdef CONFIG_PCI_IOV
2866 igb_disable_sriov(pdev);
2867 #endif
2868
2869 unregister_netdev(netdev);
2870
2871 igb_clear_interrupt_scheme(adapter);
2872
2873 pci_iounmap(pdev, adapter->io_addr);
2874 if (hw->flash_address)
2875 iounmap(hw->flash_address);
2876 pci_release_selected_regions(pdev,
2877 pci_select_bars(pdev, IORESOURCE_MEM));
2878
2879 kfree(adapter->shadow_vfta);
2880 free_netdev(netdev);
2881
2882 pci_disable_pcie_error_reporting(pdev);
2883
2884 pci_disable_device(pdev);
2885 }
2886
2887 /**
2888 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2889 * @adapter: board private structure to initialize
2890 *
2891 * This function initializes the vf specific data storage and then attempts to
2892 * allocate the VFs. The reason for ordering it this way is because it is much
2893 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2894 * the memory for the VFs.
2895 **/
2896 static void igb_probe_vfs(struct igb_adapter *adapter)
2897 {
2898 #ifdef CONFIG_PCI_IOV
2899 struct pci_dev *pdev = adapter->pdev;
2900 struct e1000_hw *hw = &adapter->hw;
2901
2902 /* Virtualization features not supported on i210 family. */
2903 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2904 return;
2905
2906 /* Of the below we really only want the effect of getting
2907 * IGB_FLAG_HAS_MSIX set (if available), without which
2908 * igb_enable_sriov() has no effect.
2909 */
2910 igb_set_interrupt_capability(adapter, true);
2911 igb_reset_interrupt_capability(adapter);
2912
2913 pci_sriov_set_totalvfs(pdev, 7);
2914 igb_enable_sriov(pdev, max_vfs);
2915
2916 #endif /* CONFIG_PCI_IOV */
2917 }
2918
2919 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2920 {
2921 struct e1000_hw *hw = &adapter->hw;
2922 u32 max_rss_queues;
2923
2924 /* Determine the maximum number of RSS queues supported. */
2925 switch (hw->mac.type) {
2926 case e1000_i211:
2927 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2928 break;
2929 case e1000_82575:
2930 case e1000_i210:
2931 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2932 break;
2933 case e1000_i350:
2934 /* I350 cannot do RSS and SR-IOV at the same time */
2935 if (!!adapter->vfs_allocated_count) {
2936 max_rss_queues = 1;
2937 break;
2938 }
2939 /* fall through */
2940 case e1000_82576:
2941 if (!!adapter->vfs_allocated_count) {
2942 max_rss_queues = 2;
2943 break;
2944 }
2945 /* fall through */
2946 case e1000_82580:
2947 case e1000_i354:
2948 default:
2949 max_rss_queues = IGB_MAX_RX_QUEUES;
2950 break;
2951 }
2952
2953 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2954
2955 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2956 }
2957
2958 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2959 const u32 max_rss_queues)
2960 {
2961 struct e1000_hw *hw = &adapter->hw;
2962
2963 /* Determine if we need to pair queues. */
2964 switch (hw->mac.type) {
2965 case e1000_82575:
2966 case e1000_i211:
2967 /* Device supports enough interrupts without queue pairing. */
2968 break;
2969 case e1000_82576:
2970 case e1000_82580:
2971 case e1000_i350:
2972 case e1000_i354:
2973 case e1000_i210:
2974 default:
2975 /* If rss_queues > half of max_rss_queues, pair the queues in
2976 * order to conserve interrupts due to limited supply.
2977 */
2978 if (adapter->rss_queues > (max_rss_queues / 2))
2979 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2980 else
2981 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
2982 break;
2983 }
2984 }
2985
2986 /**
2987 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2988 * @adapter: board private structure to initialize
2989 *
2990 * igb_sw_init initializes the Adapter private data structure.
2991 * Fields are initialized based on PCI device information and
2992 * OS network device settings (MTU size).
2993 **/
2994 static int igb_sw_init(struct igb_adapter *adapter)
2995 {
2996 struct e1000_hw *hw = &adapter->hw;
2997 struct net_device *netdev = adapter->netdev;
2998 struct pci_dev *pdev = adapter->pdev;
2999
3000 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3001
3002 /* set default ring sizes */
3003 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3004 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3005
3006 /* set default ITR values */
3007 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3008 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3009
3010 /* set default work limits */
3011 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3012
3013 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3014 VLAN_HLEN;
3015 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3016
3017 spin_lock_init(&adapter->stats64_lock);
3018 #ifdef CONFIG_PCI_IOV
3019 switch (hw->mac.type) {
3020 case e1000_82576:
3021 case e1000_i350:
3022 if (max_vfs > 7) {
3023 dev_warn(&pdev->dev,
3024 "Maximum of 7 VFs per PF, using max\n");
3025 max_vfs = adapter->vfs_allocated_count = 7;
3026 } else
3027 adapter->vfs_allocated_count = max_vfs;
3028 if (adapter->vfs_allocated_count)
3029 dev_warn(&pdev->dev,
3030 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3031 break;
3032 default:
3033 break;
3034 }
3035 #endif /* CONFIG_PCI_IOV */
3036
3037 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3038 adapter->flags |= IGB_FLAG_HAS_MSIX;
3039
3040 igb_probe_vfs(adapter);
3041
3042 igb_init_queue_configuration(adapter);
3043
3044 /* Setup and initialize a copy of the hw vlan table array */
3045 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3046 GFP_ATOMIC);
3047
3048 /* This call may decrease the number of queues */
3049 if (igb_init_interrupt_scheme(adapter, true)) {
3050 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3051 return -ENOMEM;
3052 }
3053
3054 /* Explicitly disable IRQ since the NIC can be in any state. */
3055 igb_irq_disable(adapter);
3056
3057 if (hw->mac.type >= e1000_i350)
3058 adapter->flags &= ~IGB_FLAG_DMAC;
3059
3060 set_bit(__IGB_DOWN, &adapter->state);
3061 return 0;
3062 }
3063
3064 /**
3065 * igb_open - Called when a network interface is made active
3066 * @netdev: network interface device structure
3067 *
3068 * Returns 0 on success, negative value on failure
3069 *
3070 * The open entry point is called when a network interface is made
3071 * active by the system (IFF_UP). At this point all resources needed
3072 * for transmit and receive operations are allocated, the interrupt
3073 * handler is registered with the OS, the watchdog timer is started,
3074 * and the stack is notified that the interface is ready.
3075 **/
3076 static int __igb_open(struct net_device *netdev, bool resuming)
3077 {
3078 struct igb_adapter *adapter = netdev_priv(netdev);
3079 struct e1000_hw *hw = &adapter->hw;
3080 struct pci_dev *pdev = adapter->pdev;
3081 int err;
3082 int i;
3083
3084 /* disallow open during test */
3085 if (test_bit(__IGB_TESTING, &adapter->state)) {
3086 WARN_ON(resuming);
3087 return -EBUSY;
3088 }
3089
3090 if (!resuming)
3091 pm_runtime_get_sync(&pdev->dev);
3092
3093 netif_carrier_off(netdev);
3094
3095 /* allocate transmit descriptors */
3096 err = igb_setup_all_tx_resources(adapter);
3097 if (err)
3098 goto err_setup_tx;
3099
3100 /* allocate receive descriptors */
3101 err = igb_setup_all_rx_resources(adapter);
3102 if (err)
3103 goto err_setup_rx;
3104
3105 igb_power_up_link(adapter);
3106
3107 /* before we allocate an interrupt, we must be ready to handle it.
3108 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3109 * as soon as we call pci_request_irq, so we have to setup our
3110 * clean_rx handler before we do so.
3111 */
3112 igb_configure(adapter);
3113
3114 err = igb_request_irq(adapter);
3115 if (err)
3116 goto err_req_irq;
3117
3118 /* Notify the stack of the actual queue counts. */
3119 err = netif_set_real_num_tx_queues(adapter->netdev,
3120 adapter->num_tx_queues);
3121 if (err)
3122 goto err_set_queues;
3123
3124 err = netif_set_real_num_rx_queues(adapter->netdev,
3125 adapter->num_rx_queues);
3126 if (err)
3127 goto err_set_queues;
3128
3129 /* From here on the code is the same as igb_up() */
3130 clear_bit(__IGB_DOWN, &adapter->state);
3131
3132 for (i = 0; i < adapter->num_q_vectors; i++)
3133 napi_enable(&(adapter->q_vector[i]->napi));
3134
3135 /* Clear any pending interrupts. */
3136 rd32(E1000_ICR);
3137
3138 igb_irq_enable(adapter);
3139
3140 /* notify VFs that reset has been completed */
3141 if (adapter->vfs_allocated_count) {
3142 u32 reg_data = rd32(E1000_CTRL_EXT);
3143
3144 reg_data |= E1000_CTRL_EXT_PFRSTD;
3145 wr32(E1000_CTRL_EXT, reg_data);
3146 }
3147
3148 netif_tx_start_all_queues(netdev);
3149
3150 if (!resuming)
3151 pm_runtime_put(&pdev->dev);
3152
3153 /* start the watchdog. */
3154 hw->mac.get_link_status = 1;
3155 schedule_work(&adapter->watchdog_task);
3156
3157 return 0;
3158
3159 err_set_queues:
3160 igb_free_irq(adapter);
3161 err_req_irq:
3162 igb_release_hw_control(adapter);
3163 igb_power_down_link(adapter);
3164 igb_free_all_rx_resources(adapter);
3165 err_setup_rx:
3166 igb_free_all_tx_resources(adapter);
3167 err_setup_tx:
3168 igb_reset(adapter);
3169 if (!resuming)
3170 pm_runtime_put(&pdev->dev);
3171
3172 return err;
3173 }
3174
3175 int igb_open(struct net_device *netdev)
3176 {
3177 return __igb_open(netdev, false);
3178 }
3179
3180 /**
3181 * igb_close - Disables a network interface
3182 * @netdev: network interface device structure
3183 *
3184 * Returns 0, this is not allowed to fail
3185 *
3186 * The close entry point is called when an interface is de-activated
3187 * by the OS. The hardware is still under the driver's control, but
3188 * needs to be disabled. A global MAC reset is issued to stop the
3189 * hardware, and all transmit and receive resources are freed.
3190 **/
3191 static int __igb_close(struct net_device *netdev, bool suspending)
3192 {
3193 struct igb_adapter *adapter = netdev_priv(netdev);
3194 struct pci_dev *pdev = adapter->pdev;
3195
3196 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3197
3198 if (!suspending)
3199 pm_runtime_get_sync(&pdev->dev);
3200
3201 igb_down(adapter);
3202 igb_free_irq(adapter);
3203
3204 igb_free_all_tx_resources(adapter);
3205 igb_free_all_rx_resources(adapter);
3206
3207 if (!suspending)
3208 pm_runtime_put_sync(&pdev->dev);
3209 return 0;
3210 }
3211
3212 int igb_close(struct net_device *netdev)
3213 {
3214 return __igb_close(netdev, false);
3215 }
3216
3217 /**
3218 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3219 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3220 *
3221 * Return 0 on success, negative on failure
3222 **/
3223 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3224 {
3225 struct device *dev = tx_ring->dev;
3226 int size;
3227
3228 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3229
3230 tx_ring->tx_buffer_info = vzalloc(size);
3231 if (!tx_ring->tx_buffer_info)
3232 goto err;
3233
3234 /* round up to nearest 4K */
3235 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3236 tx_ring->size = ALIGN(tx_ring->size, 4096);
3237
3238 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3239 &tx_ring->dma, GFP_KERNEL);
3240 if (!tx_ring->desc)
3241 goto err;
3242
3243 tx_ring->next_to_use = 0;
3244 tx_ring->next_to_clean = 0;
3245
3246 return 0;
3247
3248 err:
3249 vfree(tx_ring->tx_buffer_info);
3250 tx_ring->tx_buffer_info = NULL;
3251 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3252 return -ENOMEM;
3253 }
3254
3255 /**
3256 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3257 * (Descriptors) for all queues
3258 * @adapter: board private structure
3259 *
3260 * Return 0 on success, negative on failure
3261 **/
3262 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3263 {
3264 struct pci_dev *pdev = adapter->pdev;
3265 int i, err = 0;
3266
3267 for (i = 0; i < adapter->num_tx_queues; i++) {
3268 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3269 if (err) {
3270 dev_err(&pdev->dev,
3271 "Allocation for Tx Queue %u failed\n", i);
3272 for (i--; i >= 0; i--)
3273 igb_free_tx_resources(adapter->tx_ring[i]);
3274 break;
3275 }
3276 }
3277
3278 return err;
3279 }
3280
3281 /**
3282 * igb_setup_tctl - configure the transmit control registers
3283 * @adapter: Board private structure
3284 **/
3285 void igb_setup_tctl(struct igb_adapter *adapter)
3286 {
3287 struct e1000_hw *hw = &adapter->hw;
3288 u32 tctl;
3289
3290 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3291 wr32(E1000_TXDCTL(0), 0);
3292
3293 /* Program the Transmit Control Register */
3294 tctl = rd32(E1000_TCTL);
3295 tctl &= ~E1000_TCTL_CT;
3296 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3297 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3298
3299 igb_config_collision_dist(hw);
3300
3301 /* Enable transmits */
3302 tctl |= E1000_TCTL_EN;
3303
3304 wr32(E1000_TCTL, tctl);
3305 }
3306
3307 /**
3308 * igb_configure_tx_ring - Configure transmit ring after Reset
3309 * @adapter: board private structure
3310 * @ring: tx ring to configure
3311 *
3312 * Configure a transmit ring after a reset.
3313 **/
3314 void igb_configure_tx_ring(struct igb_adapter *adapter,
3315 struct igb_ring *ring)
3316 {
3317 struct e1000_hw *hw = &adapter->hw;
3318 u32 txdctl = 0;
3319 u64 tdba = ring->dma;
3320 int reg_idx = ring->reg_idx;
3321
3322 /* disable the queue */
3323 wr32(E1000_TXDCTL(reg_idx), 0);
3324 wrfl();
3325 mdelay(10);
3326
3327 wr32(E1000_TDLEN(reg_idx),
3328 ring->count * sizeof(union e1000_adv_tx_desc));
3329 wr32(E1000_TDBAL(reg_idx),
3330 tdba & 0x00000000ffffffffULL);
3331 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3332
3333 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3334 wr32(E1000_TDH(reg_idx), 0);
3335 writel(0, ring->tail);
3336
3337 txdctl |= IGB_TX_PTHRESH;
3338 txdctl |= IGB_TX_HTHRESH << 8;
3339 txdctl |= IGB_TX_WTHRESH << 16;
3340
3341 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3342 wr32(E1000_TXDCTL(reg_idx), txdctl);
3343 }
3344
3345 /**
3346 * igb_configure_tx - Configure transmit Unit after Reset
3347 * @adapter: board private structure
3348 *
3349 * Configure the Tx unit of the MAC after a reset.
3350 **/
3351 static void igb_configure_tx(struct igb_adapter *adapter)
3352 {
3353 int i;
3354
3355 for (i = 0; i < adapter->num_tx_queues; i++)
3356 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3357 }
3358
3359 /**
3360 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3361 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3362 *
3363 * Returns 0 on success, negative on failure
3364 **/
3365 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3366 {
3367 struct device *dev = rx_ring->dev;
3368 int size;
3369
3370 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3371
3372 rx_ring->rx_buffer_info = vzalloc(size);
3373 if (!rx_ring->rx_buffer_info)
3374 goto err;
3375
3376 /* Round up to nearest 4K */
3377 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3378 rx_ring->size = ALIGN(rx_ring->size, 4096);
3379
3380 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3381 &rx_ring->dma, GFP_KERNEL);
3382 if (!rx_ring->desc)
3383 goto err;
3384
3385 rx_ring->next_to_alloc = 0;
3386 rx_ring->next_to_clean = 0;
3387 rx_ring->next_to_use = 0;
3388
3389 return 0;
3390
3391 err:
3392 vfree(rx_ring->rx_buffer_info);
3393 rx_ring->rx_buffer_info = NULL;
3394 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3395 return -ENOMEM;
3396 }
3397
3398 /**
3399 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3400 * (Descriptors) for all queues
3401 * @adapter: board private structure
3402 *
3403 * Return 0 on success, negative on failure
3404 **/
3405 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3406 {
3407 struct pci_dev *pdev = adapter->pdev;
3408 int i, err = 0;
3409
3410 for (i = 0; i < adapter->num_rx_queues; i++) {
3411 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3412 if (err) {
3413 dev_err(&pdev->dev,
3414 "Allocation for Rx Queue %u failed\n", i);
3415 for (i--; i >= 0; i--)
3416 igb_free_rx_resources(adapter->rx_ring[i]);
3417 break;
3418 }
3419 }
3420
3421 return err;
3422 }
3423
3424 /**
3425 * igb_setup_mrqc - configure the multiple receive queue control registers
3426 * @adapter: Board private structure
3427 **/
3428 static void igb_setup_mrqc(struct igb_adapter *adapter)
3429 {
3430 struct e1000_hw *hw = &adapter->hw;
3431 u32 mrqc, rxcsum;
3432 u32 j, num_rx_queues;
3433 u32 rss_key[10];
3434
3435 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3436 for (j = 0; j < 10; j++)
3437 wr32(E1000_RSSRK(j), rss_key[j]);
3438
3439 num_rx_queues = adapter->rss_queues;
3440
3441 switch (hw->mac.type) {
3442 case e1000_82576:
3443 /* 82576 supports 2 RSS queues for SR-IOV */
3444 if (adapter->vfs_allocated_count)
3445 num_rx_queues = 2;
3446 break;
3447 default:
3448 break;
3449 }
3450
3451 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3452 for (j = 0; j < IGB_RETA_SIZE; j++)
3453 adapter->rss_indir_tbl[j] =
3454 (j * num_rx_queues) / IGB_RETA_SIZE;
3455 adapter->rss_indir_tbl_init = num_rx_queues;
3456 }
3457 igb_write_rss_indir_tbl(adapter);
3458
3459 /* Disable raw packet checksumming so that RSS hash is placed in
3460 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3461 * offloads as they are enabled by default
3462 */
3463 rxcsum = rd32(E1000_RXCSUM);
3464 rxcsum |= E1000_RXCSUM_PCSD;
3465
3466 if (adapter->hw.mac.type >= e1000_82576)
3467 /* Enable Receive Checksum Offload for SCTP */
3468 rxcsum |= E1000_RXCSUM_CRCOFL;
3469
3470 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3471 wr32(E1000_RXCSUM, rxcsum);
3472
3473 /* Generate RSS hash based on packet types, TCP/UDP
3474 * port numbers and/or IPv4/v6 src and dst addresses
3475 */
3476 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3477 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3478 E1000_MRQC_RSS_FIELD_IPV6 |
3479 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3480 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3481
3482 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3483 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3484 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3485 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3486
3487 /* If VMDq is enabled then we set the appropriate mode for that, else
3488 * we default to RSS so that an RSS hash is calculated per packet even
3489 * if we are only using one queue
3490 */
3491 if (adapter->vfs_allocated_count) {
3492 if (hw->mac.type > e1000_82575) {
3493 /* Set the default pool for the PF's first queue */
3494 u32 vtctl = rd32(E1000_VT_CTL);
3495
3496 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3497 E1000_VT_CTL_DISABLE_DEF_POOL);
3498 vtctl |= adapter->vfs_allocated_count <<
3499 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3500 wr32(E1000_VT_CTL, vtctl);
3501 }
3502 if (adapter->rss_queues > 1)
3503 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
3504 else
3505 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3506 } else {
3507 if (hw->mac.type != e1000_i211)
3508 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
3509 }
3510 igb_vmm_control(adapter);
3511
3512 wr32(E1000_MRQC, mrqc);
3513 }
3514
3515 /**
3516 * igb_setup_rctl - configure the receive control registers
3517 * @adapter: Board private structure
3518 **/
3519 void igb_setup_rctl(struct igb_adapter *adapter)
3520 {
3521 struct e1000_hw *hw = &adapter->hw;
3522 u32 rctl;
3523
3524 rctl = rd32(E1000_RCTL);
3525
3526 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3527 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3528
3529 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3530 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3531
3532 /* enable stripping of CRC. It's unlikely this will break BMC
3533 * redirection as it did with e1000. Newer features require
3534 * that the HW strips the CRC.
3535 */
3536 rctl |= E1000_RCTL_SECRC;
3537
3538 /* disable store bad packets and clear size bits. */
3539 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3540
3541 /* enable LPE to allow for reception of jumbo frames */
3542 rctl |= E1000_RCTL_LPE;
3543
3544 /* disable queue 0 to prevent tail write w/o re-config */
3545 wr32(E1000_RXDCTL(0), 0);
3546
3547 /* Attention!!! For SR-IOV PF driver operations you must enable
3548 * queue drop for all VF and PF queues to prevent head of line blocking
3549 * if an un-trusted VF does not provide descriptors to hardware.
3550 */
3551 if (adapter->vfs_allocated_count) {
3552 /* set all queue drop enable bits */
3553 wr32(E1000_QDE, ALL_QUEUES);
3554 }
3555
3556 /* This is useful for sniffing bad packets. */
3557 if (adapter->netdev->features & NETIF_F_RXALL) {
3558 /* UPE and MPE will be handled by normal PROMISC logic
3559 * in e1000e_set_rx_mode
3560 */
3561 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3562 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3563 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3564
3565 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
3566 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3567 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3568 * and that breaks VLANs.
3569 */
3570 }
3571
3572 wr32(E1000_RCTL, rctl);
3573 }
3574
3575 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3576 int vfn)
3577 {
3578 struct e1000_hw *hw = &adapter->hw;
3579 u32 vmolr;
3580
3581 if (size > MAX_JUMBO_FRAME_SIZE)
3582 size = MAX_JUMBO_FRAME_SIZE;
3583
3584 vmolr = rd32(E1000_VMOLR(vfn));
3585 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3586 vmolr |= size | E1000_VMOLR_LPE;
3587 wr32(E1000_VMOLR(vfn), vmolr);
3588
3589 return 0;
3590 }
3591
3592 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
3593 int vfn, bool enable)
3594 {
3595 struct e1000_hw *hw = &adapter->hw;
3596 u32 val, reg;
3597
3598 if (hw->mac.type < e1000_82576)
3599 return;
3600
3601 if (hw->mac.type == e1000_i350)
3602 reg = E1000_DVMOLR(vfn);
3603 else
3604 reg = E1000_VMOLR(vfn);
3605
3606 val = rd32(reg);
3607 if (enable)
3608 val |= E1000_VMOLR_STRVLAN;
3609 else
3610 val &= ~(E1000_VMOLR_STRVLAN);
3611 wr32(reg, val);
3612 }
3613
3614 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3615 int vfn, bool aupe)
3616 {
3617 struct e1000_hw *hw = &adapter->hw;
3618 u32 vmolr;
3619
3620 /* This register exists only on 82576 and newer so if we are older then
3621 * we should exit and do nothing
3622 */
3623 if (hw->mac.type < e1000_82576)
3624 return;
3625
3626 vmolr = rd32(E1000_VMOLR(vfn));
3627 if (aupe)
3628 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3629 else
3630 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3631
3632 /* clear all bits that might not be set */
3633 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3634
3635 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3636 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3637 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3638 * multicast packets
3639 */
3640 if (vfn <= adapter->vfs_allocated_count)
3641 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3642
3643 wr32(E1000_VMOLR(vfn), vmolr);
3644 }
3645
3646 /**
3647 * igb_configure_rx_ring - Configure a receive ring after Reset
3648 * @adapter: board private structure
3649 * @ring: receive ring to be configured
3650 *
3651 * Configure the Rx unit of the MAC after a reset.
3652 **/
3653 void igb_configure_rx_ring(struct igb_adapter *adapter,
3654 struct igb_ring *ring)
3655 {
3656 struct e1000_hw *hw = &adapter->hw;
3657 u64 rdba = ring->dma;
3658 int reg_idx = ring->reg_idx;
3659 u32 srrctl = 0, rxdctl = 0;
3660
3661 /* disable the queue */
3662 wr32(E1000_RXDCTL(reg_idx), 0);
3663
3664 /* Set DMA base address registers */
3665 wr32(E1000_RDBAL(reg_idx),
3666 rdba & 0x00000000ffffffffULL);
3667 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3668 wr32(E1000_RDLEN(reg_idx),
3669 ring->count * sizeof(union e1000_adv_rx_desc));
3670
3671 /* initialize head and tail */
3672 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3673 wr32(E1000_RDH(reg_idx), 0);
3674 writel(0, ring->tail);
3675
3676 /* set descriptor configuration */
3677 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3678 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3679 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3680 if (hw->mac.type >= e1000_82580)
3681 srrctl |= E1000_SRRCTL_TIMESTAMP;
3682 /* Only set Drop Enable if we are supporting multiple queues */
3683 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3684 srrctl |= E1000_SRRCTL_DROP_EN;
3685
3686 wr32(E1000_SRRCTL(reg_idx), srrctl);
3687
3688 /* set filtering for VMDQ pools */
3689 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3690
3691 rxdctl |= IGB_RX_PTHRESH;
3692 rxdctl |= IGB_RX_HTHRESH << 8;
3693 rxdctl |= IGB_RX_WTHRESH << 16;
3694
3695 /* enable receive descriptor fetching */
3696 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3697 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3698 }
3699
3700 /**
3701 * igb_configure_rx - Configure receive Unit after Reset
3702 * @adapter: board private structure
3703 *
3704 * Configure the Rx unit of the MAC after a reset.
3705 **/
3706 static void igb_configure_rx(struct igb_adapter *adapter)
3707 {
3708 int i;
3709
3710 /* set the correct pool for the PF default MAC address in entry 0 */
3711 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3712 adapter->vfs_allocated_count);
3713
3714 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3715 * the Base and Length of the Rx Descriptor Ring
3716 */
3717 for (i = 0; i < adapter->num_rx_queues; i++)
3718 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3719 }
3720
3721 /**
3722 * igb_free_tx_resources - Free Tx Resources per Queue
3723 * @tx_ring: Tx descriptor ring for a specific queue
3724 *
3725 * Free all transmit software resources
3726 **/
3727 void igb_free_tx_resources(struct igb_ring *tx_ring)
3728 {
3729 igb_clean_tx_ring(tx_ring);
3730
3731 vfree(tx_ring->tx_buffer_info);
3732 tx_ring->tx_buffer_info = NULL;
3733
3734 /* if not set, then don't free */
3735 if (!tx_ring->desc)
3736 return;
3737
3738 dma_free_coherent(tx_ring->dev, tx_ring->size,
3739 tx_ring->desc, tx_ring->dma);
3740
3741 tx_ring->desc = NULL;
3742 }
3743
3744 /**
3745 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3746 * @adapter: board private structure
3747 *
3748 * Free all transmit software resources
3749 **/
3750 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3751 {
3752 int i;
3753
3754 for (i = 0; i < adapter->num_tx_queues; i++)
3755 if (adapter->tx_ring[i])
3756 igb_free_tx_resources(adapter->tx_ring[i]);
3757 }
3758
3759 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3760 struct igb_tx_buffer *tx_buffer)
3761 {
3762 if (tx_buffer->skb) {
3763 dev_kfree_skb_any(tx_buffer->skb);
3764 if (dma_unmap_len(tx_buffer, len))
3765 dma_unmap_single(ring->dev,
3766 dma_unmap_addr(tx_buffer, dma),
3767 dma_unmap_len(tx_buffer, len),
3768 DMA_TO_DEVICE);
3769 } else if (dma_unmap_len(tx_buffer, len)) {
3770 dma_unmap_page(ring->dev,
3771 dma_unmap_addr(tx_buffer, dma),
3772 dma_unmap_len(tx_buffer, len),
3773 DMA_TO_DEVICE);
3774 }
3775 tx_buffer->next_to_watch = NULL;
3776 tx_buffer->skb = NULL;
3777 dma_unmap_len_set(tx_buffer, len, 0);
3778 /* buffer_info must be completely set up in the transmit path */
3779 }
3780
3781 /**
3782 * igb_clean_tx_ring - Free Tx Buffers
3783 * @tx_ring: ring to be cleaned
3784 **/
3785 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3786 {
3787 struct igb_tx_buffer *buffer_info;
3788 unsigned long size;
3789 u16 i;
3790
3791 if (!tx_ring->tx_buffer_info)
3792 return;
3793 /* Free all the Tx ring sk_buffs */
3794
3795 for (i = 0; i < tx_ring->count; i++) {
3796 buffer_info = &tx_ring->tx_buffer_info[i];
3797 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3798 }
3799
3800 netdev_tx_reset_queue(txring_txq(tx_ring));
3801
3802 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3803 memset(tx_ring->tx_buffer_info, 0, size);
3804
3805 /* Zero out the descriptor ring */
3806 memset(tx_ring->desc, 0, tx_ring->size);
3807
3808 tx_ring->next_to_use = 0;
3809 tx_ring->next_to_clean = 0;
3810 }
3811
3812 /**
3813 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3814 * @adapter: board private structure
3815 **/
3816 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3817 {
3818 int i;
3819
3820 for (i = 0; i < adapter->num_tx_queues; i++)
3821 if (adapter->tx_ring[i])
3822 igb_clean_tx_ring(adapter->tx_ring[i]);
3823 }
3824
3825 /**
3826 * igb_free_rx_resources - Free Rx Resources
3827 * @rx_ring: ring to clean the resources from
3828 *
3829 * Free all receive software resources
3830 **/
3831 void igb_free_rx_resources(struct igb_ring *rx_ring)
3832 {
3833 igb_clean_rx_ring(rx_ring);
3834
3835 vfree(rx_ring->rx_buffer_info);
3836 rx_ring->rx_buffer_info = NULL;
3837
3838 /* if not set, then don't free */
3839 if (!rx_ring->desc)
3840 return;
3841
3842 dma_free_coherent(rx_ring->dev, rx_ring->size,
3843 rx_ring->desc, rx_ring->dma);
3844
3845 rx_ring->desc = NULL;
3846 }
3847
3848 /**
3849 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3850 * @adapter: board private structure
3851 *
3852 * Free all receive software resources
3853 **/
3854 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3855 {
3856 int i;
3857
3858 for (i = 0; i < adapter->num_rx_queues; i++)
3859 if (adapter->rx_ring[i])
3860 igb_free_rx_resources(adapter->rx_ring[i]);
3861 }
3862
3863 /**
3864 * igb_clean_rx_ring - Free Rx Buffers per Queue
3865 * @rx_ring: ring to free buffers from
3866 **/
3867 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3868 {
3869 unsigned long size;
3870 u16 i;
3871
3872 if (rx_ring->skb)
3873 dev_kfree_skb(rx_ring->skb);
3874 rx_ring->skb = NULL;
3875
3876 if (!rx_ring->rx_buffer_info)
3877 return;
3878
3879 /* Free all the Rx ring sk_buffs */
3880 for (i = 0; i < rx_ring->count; i++) {
3881 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3882
3883 if (!buffer_info->page)
3884 continue;
3885
3886 dma_unmap_page(rx_ring->dev,
3887 buffer_info->dma,
3888 PAGE_SIZE,
3889 DMA_FROM_DEVICE);
3890 __free_page(buffer_info->page);
3891
3892 buffer_info->page = NULL;
3893 }
3894
3895 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3896 memset(rx_ring->rx_buffer_info, 0, size);
3897
3898 /* Zero out the descriptor ring */
3899 memset(rx_ring->desc, 0, rx_ring->size);
3900
3901 rx_ring->next_to_alloc = 0;
3902 rx_ring->next_to_clean = 0;
3903 rx_ring->next_to_use = 0;
3904 }
3905
3906 /**
3907 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3908 * @adapter: board private structure
3909 **/
3910 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3911 {
3912 int i;
3913
3914 for (i = 0; i < adapter->num_rx_queues; i++)
3915 if (adapter->rx_ring[i])
3916 igb_clean_rx_ring(adapter->rx_ring[i]);
3917 }
3918
3919 /**
3920 * igb_set_mac - Change the Ethernet Address of the NIC
3921 * @netdev: network interface device structure
3922 * @p: pointer to an address structure
3923 *
3924 * Returns 0 on success, negative on failure
3925 **/
3926 static int igb_set_mac(struct net_device *netdev, void *p)
3927 {
3928 struct igb_adapter *adapter = netdev_priv(netdev);
3929 struct e1000_hw *hw = &adapter->hw;
3930 struct sockaddr *addr = p;
3931
3932 if (!is_valid_ether_addr(addr->sa_data))
3933 return -EADDRNOTAVAIL;
3934
3935 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3936 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3937
3938 /* set the correct pool for the new PF MAC address in entry 0 */
3939 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3940 adapter->vfs_allocated_count);
3941
3942 return 0;
3943 }
3944
3945 /**
3946 * igb_write_mc_addr_list - write multicast addresses to MTA
3947 * @netdev: network interface device structure
3948 *
3949 * Writes multicast address list to the MTA hash table.
3950 * Returns: -ENOMEM on failure
3951 * 0 on no addresses written
3952 * X on writing X addresses to MTA
3953 **/
3954 static int igb_write_mc_addr_list(struct net_device *netdev)
3955 {
3956 struct igb_adapter *adapter = netdev_priv(netdev);
3957 struct e1000_hw *hw = &adapter->hw;
3958 struct netdev_hw_addr *ha;
3959 u8 *mta_list;
3960 int i;
3961
3962 if (netdev_mc_empty(netdev)) {
3963 /* nothing to program, so clear mc list */
3964 igb_update_mc_addr_list(hw, NULL, 0);
3965 igb_restore_vf_multicasts(adapter);
3966 return 0;
3967 }
3968
3969 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3970 if (!mta_list)
3971 return -ENOMEM;
3972
3973 /* The shared function expects a packed array of only addresses. */
3974 i = 0;
3975 netdev_for_each_mc_addr(ha, netdev)
3976 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3977
3978 igb_update_mc_addr_list(hw, mta_list, i);
3979 kfree(mta_list);
3980
3981 return netdev_mc_count(netdev);
3982 }
3983
3984 /**
3985 * igb_write_uc_addr_list - write unicast addresses to RAR table
3986 * @netdev: network interface device structure
3987 *
3988 * Writes unicast address list to the RAR table.
3989 * Returns: -ENOMEM on failure/insufficient address space
3990 * 0 on no addresses written
3991 * X on writing X addresses to the RAR table
3992 **/
3993 static int igb_write_uc_addr_list(struct net_device *netdev)
3994 {
3995 struct igb_adapter *adapter = netdev_priv(netdev);
3996 struct e1000_hw *hw = &adapter->hw;
3997 unsigned int vfn = adapter->vfs_allocated_count;
3998 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3999 int count = 0;
4000
4001 /* return ENOMEM indicating insufficient memory for addresses */
4002 if (netdev_uc_count(netdev) > rar_entries)
4003 return -ENOMEM;
4004
4005 if (!netdev_uc_empty(netdev) && rar_entries) {
4006 struct netdev_hw_addr *ha;
4007
4008 netdev_for_each_uc_addr(ha, netdev) {
4009 if (!rar_entries)
4010 break;
4011 igb_rar_set_qsel(adapter, ha->addr,
4012 rar_entries--,
4013 vfn);
4014 count++;
4015 }
4016 }
4017 /* write the addresses in reverse order to avoid write combining */
4018 for (; rar_entries > 0 ; rar_entries--) {
4019 wr32(E1000_RAH(rar_entries), 0);
4020 wr32(E1000_RAL(rar_entries), 0);
4021 }
4022 wrfl();
4023
4024 return count;
4025 }
4026
4027 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4028 {
4029 struct e1000_hw *hw = &adapter->hw;
4030 u32 i, pf_id;
4031
4032 switch (hw->mac.type) {
4033 case e1000_i210:
4034 case e1000_i211:
4035 case e1000_i350:
4036 /* VLAN filtering needed for VLAN prio filter */
4037 if (adapter->netdev->features & NETIF_F_NTUPLE)
4038 break;
4039 /* fall through */
4040 case e1000_82576:
4041 case e1000_82580:
4042 case e1000_i354:
4043 /* VLAN filtering needed for pool filtering */
4044 if (adapter->vfs_allocated_count)
4045 break;
4046 /* fall through */
4047 default:
4048 return 1;
4049 }
4050
4051 /* We are already in VLAN promisc, nothing to do */
4052 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4053 return 0;
4054
4055 if (!adapter->vfs_allocated_count)
4056 goto set_vfta;
4057
4058 /* Add PF to all active pools */
4059 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4060
4061 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4062 u32 vlvf = rd32(E1000_VLVF(i));
4063
4064 vlvf |= 1 << pf_id;
4065 wr32(E1000_VLVF(i), vlvf);
4066 }
4067
4068 set_vfta:
4069 /* Set all bits in the VLAN filter table array */
4070 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4071 hw->mac.ops.write_vfta(hw, i, ~0U);
4072
4073 /* Set flag so we don't redo unnecessary work */
4074 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4075
4076 return 0;
4077 }
4078
4079 #define VFTA_BLOCK_SIZE 8
4080 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4081 {
4082 struct e1000_hw *hw = &adapter->hw;
4083 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4084 u32 vid_start = vfta_offset * 32;
4085 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4086 u32 i, vid, word, bits, pf_id;
4087
4088 /* guarantee that we don't scrub out management VLAN */
4089 vid = adapter->mng_vlan_id;
4090 if (vid >= vid_start && vid < vid_end)
4091 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4092
4093 if (!adapter->vfs_allocated_count)
4094 goto set_vfta;
4095
4096 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4097
4098 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4099 u32 vlvf = rd32(E1000_VLVF(i));
4100
4101 /* pull VLAN ID from VLVF */
4102 vid = vlvf & VLAN_VID_MASK;
4103
4104 /* only concern ourselves with a certain range */
4105 if (vid < vid_start || vid >= vid_end)
4106 continue;
4107
4108 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4109 /* record VLAN ID in VFTA */
4110 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4111
4112 /* if PF is part of this then continue */
4113 if (test_bit(vid, adapter->active_vlans))
4114 continue;
4115 }
4116
4117 /* remove PF from the pool */
4118 bits = ~(1 << pf_id);
4119 bits &= rd32(E1000_VLVF(i));
4120 wr32(E1000_VLVF(i), bits);
4121 }
4122
4123 set_vfta:
4124 /* extract values from active_vlans and write back to VFTA */
4125 for (i = VFTA_BLOCK_SIZE; i--;) {
4126 vid = (vfta_offset + i) * 32;
4127 word = vid / BITS_PER_LONG;
4128 bits = vid % BITS_PER_LONG;
4129
4130 vfta[i] |= adapter->active_vlans[word] >> bits;
4131
4132 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4133 }
4134 }
4135
4136 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4137 {
4138 u32 i;
4139
4140 /* We are not in VLAN promisc, nothing to do */
4141 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4142 return;
4143
4144 /* Set flag so we don't redo unnecessary work */
4145 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4146
4147 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4148 igb_scrub_vfta(adapter, i);
4149 }
4150
4151 /**
4152 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4153 * @netdev: network interface device structure
4154 *
4155 * The set_rx_mode entry point is called whenever the unicast or multicast
4156 * address lists or the network interface flags are updated. This routine is
4157 * responsible for configuring the hardware for proper unicast, multicast,
4158 * promiscuous mode, and all-multi behavior.
4159 **/
4160 static void igb_set_rx_mode(struct net_device *netdev)
4161 {
4162 struct igb_adapter *adapter = netdev_priv(netdev);
4163 struct e1000_hw *hw = &adapter->hw;
4164 unsigned int vfn = adapter->vfs_allocated_count;
4165 u32 rctl = 0, vmolr = 0;
4166 int count;
4167
4168 /* Check for Promiscuous and All Multicast modes */
4169 if (netdev->flags & IFF_PROMISC) {
4170 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
4171 vmolr |= E1000_VMOLR_MPME;
4172
4173 /* enable use of UTA filter to force packets to default pool */
4174 if (hw->mac.type == e1000_82576)
4175 vmolr |= E1000_VMOLR_ROPE;
4176 } else {
4177 if (netdev->flags & IFF_ALLMULTI) {
4178 rctl |= E1000_RCTL_MPE;
4179 vmolr |= E1000_VMOLR_MPME;
4180 } else {
4181 /* Write addresses to the MTA, if the attempt fails
4182 * then we should just turn on promiscuous mode so
4183 * that we can at least receive multicast traffic
4184 */
4185 count = igb_write_mc_addr_list(netdev);
4186 if (count < 0) {
4187 rctl |= E1000_RCTL_MPE;
4188 vmolr |= E1000_VMOLR_MPME;
4189 } else if (count) {
4190 vmolr |= E1000_VMOLR_ROMPE;
4191 }
4192 }
4193 }
4194
4195 /* Write addresses to available RAR registers, if there is not
4196 * sufficient space to store all the addresses then enable
4197 * unicast promiscuous mode
4198 */
4199 count = igb_write_uc_addr_list(netdev);
4200 if (count < 0) {
4201 rctl |= E1000_RCTL_UPE;
4202 vmolr |= E1000_VMOLR_ROPE;
4203 }
4204
4205 /* enable VLAN filtering by default */
4206 rctl |= E1000_RCTL_VFE;
4207
4208 /* disable VLAN filtering for modes that require it */
4209 if ((netdev->flags & IFF_PROMISC) ||
4210 (netdev->features & NETIF_F_RXALL)) {
4211 /* if we fail to set all rules then just clear VFE */
4212 if (igb_vlan_promisc_enable(adapter))
4213 rctl &= ~E1000_RCTL_VFE;
4214 } else {
4215 igb_vlan_promisc_disable(adapter);
4216 }
4217
4218 /* update state of unicast, multicast, and VLAN filtering modes */
4219 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4220 E1000_RCTL_VFE);
4221 wr32(E1000_RCTL, rctl);
4222
4223 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4224 * the VMOLR to enable the appropriate modes. Without this workaround
4225 * we will have issues with VLAN tag stripping not being done for frames
4226 * that are only arriving because we are the default pool
4227 */
4228 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4229 return;
4230
4231 /* set UTA to appropriate mode */
4232 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4233
4234 vmolr |= rd32(E1000_VMOLR(vfn)) &
4235 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4236
4237 /* enable Rx jumbo frames, no need for restriction */
4238 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4239 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4240
4241 wr32(E1000_VMOLR(vfn), vmolr);
4242 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4243
4244 igb_restore_vf_multicasts(adapter);
4245 }
4246
4247 static void igb_check_wvbr(struct igb_adapter *adapter)
4248 {
4249 struct e1000_hw *hw = &adapter->hw;
4250 u32 wvbr = 0;
4251
4252 switch (hw->mac.type) {
4253 case e1000_82576:
4254 case e1000_i350:
4255 wvbr = rd32(E1000_WVBR);
4256 if (!wvbr)
4257 return;
4258 break;
4259 default:
4260 break;
4261 }
4262
4263 adapter->wvbr |= wvbr;
4264 }
4265
4266 #define IGB_STAGGERED_QUEUE_OFFSET 8
4267
4268 static void igb_spoof_check(struct igb_adapter *adapter)
4269 {
4270 int j;
4271
4272 if (!adapter->wvbr)
4273 return;
4274
4275 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4276 if (adapter->wvbr & (1 << j) ||
4277 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4278 dev_warn(&adapter->pdev->dev,
4279 "Spoof event(s) detected on VF %d\n", j);
4280 adapter->wvbr &=
4281 ~((1 << j) |
4282 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4283 }
4284 }
4285 }
4286
4287 /* Need to wait a few seconds after link up to get diagnostic information from
4288 * the phy
4289 */
4290 static void igb_update_phy_info(unsigned long data)
4291 {
4292 struct igb_adapter *adapter = (struct igb_adapter *) data;
4293 igb_get_phy_info(&adapter->hw);
4294 }
4295
4296 /**
4297 * igb_has_link - check shared code for link and determine up/down
4298 * @adapter: pointer to driver private info
4299 **/
4300 bool igb_has_link(struct igb_adapter *adapter)
4301 {
4302 struct e1000_hw *hw = &adapter->hw;
4303 bool link_active = false;
4304
4305 /* get_link_status is set on LSC (link status) interrupt or
4306 * rx sequence error interrupt. get_link_status will stay
4307 * false until the e1000_check_for_link establishes link
4308 * for copper adapters ONLY
4309 */
4310 switch (hw->phy.media_type) {
4311 case e1000_media_type_copper:
4312 if (!hw->mac.get_link_status)
4313 return true;
4314 case e1000_media_type_internal_serdes:
4315 hw->mac.ops.check_for_link(hw);
4316 link_active = !hw->mac.get_link_status;
4317 break;
4318 default:
4319 case e1000_media_type_unknown:
4320 break;
4321 }
4322
4323 if (((hw->mac.type == e1000_i210) ||
4324 (hw->mac.type == e1000_i211)) &&
4325 (hw->phy.id == I210_I_PHY_ID)) {
4326 if (!netif_carrier_ok(adapter->netdev)) {
4327 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4328 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4329 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4330 adapter->link_check_timeout = jiffies;
4331 }
4332 }
4333
4334 return link_active;
4335 }
4336
4337 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4338 {
4339 bool ret = false;
4340 u32 ctrl_ext, thstat;
4341
4342 /* check for thermal sensor event on i350 copper only */
4343 if (hw->mac.type == e1000_i350) {
4344 thstat = rd32(E1000_THSTAT);
4345 ctrl_ext = rd32(E1000_CTRL_EXT);
4346
4347 if ((hw->phy.media_type == e1000_media_type_copper) &&
4348 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4349 ret = !!(thstat & event);
4350 }
4351
4352 return ret;
4353 }
4354
4355 /**
4356 * igb_check_lvmmc - check for malformed packets received
4357 * and indicated in LVMMC register
4358 * @adapter: pointer to adapter
4359 **/
4360 static void igb_check_lvmmc(struct igb_adapter *adapter)
4361 {
4362 struct e1000_hw *hw = &adapter->hw;
4363 u32 lvmmc;
4364
4365 lvmmc = rd32(E1000_LVMMC);
4366 if (lvmmc) {
4367 if (unlikely(net_ratelimit())) {
4368 netdev_warn(adapter->netdev,
4369 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4370 lvmmc);
4371 }
4372 }
4373 }
4374
4375 /**
4376 * igb_watchdog - Timer Call-back
4377 * @data: pointer to adapter cast into an unsigned long
4378 **/
4379 static void igb_watchdog(unsigned long data)
4380 {
4381 struct igb_adapter *adapter = (struct igb_adapter *)data;
4382 /* Do the rest outside of interrupt context */
4383 schedule_work(&adapter->watchdog_task);
4384 }
4385
4386 static void igb_watchdog_task(struct work_struct *work)
4387 {
4388 struct igb_adapter *adapter = container_of(work,
4389 struct igb_adapter,
4390 watchdog_task);
4391 struct e1000_hw *hw = &adapter->hw;
4392 struct e1000_phy_info *phy = &hw->phy;
4393 struct net_device *netdev = adapter->netdev;
4394 u32 link;
4395 int i;
4396 u32 connsw;
4397 u16 phy_data, retry_count = 20;
4398
4399 link = igb_has_link(adapter);
4400
4401 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4402 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4403 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4404 else
4405 link = false;
4406 }
4407
4408 /* Force link down if we have fiber to swap to */
4409 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4410 if (hw->phy.media_type == e1000_media_type_copper) {
4411 connsw = rd32(E1000_CONNSW);
4412 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4413 link = 0;
4414 }
4415 }
4416 if (link) {
4417 /* Perform a reset if the media type changed. */
4418 if (hw->dev_spec._82575.media_changed) {
4419 hw->dev_spec._82575.media_changed = false;
4420 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4421 igb_reset(adapter);
4422 }
4423 /* Cancel scheduled suspend requests. */
4424 pm_runtime_resume(netdev->dev.parent);
4425
4426 if (!netif_carrier_ok(netdev)) {
4427 u32 ctrl;
4428
4429 hw->mac.ops.get_speed_and_duplex(hw,
4430 &adapter->link_speed,
4431 &adapter->link_duplex);
4432
4433 ctrl = rd32(E1000_CTRL);
4434 /* Links status message must follow this format */
4435 netdev_info(netdev,
4436 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4437 netdev->name,
4438 adapter->link_speed,
4439 adapter->link_duplex == FULL_DUPLEX ?
4440 "Full" : "Half",
4441 (ctrl & E1000_CTRL_TFCE) &&
4442 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4443 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4444 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4445
4446 /* disable EEE if enabled */
4447 if ((adapter->flags & IGB_FLAG_EEE) &&
4448 (adapter->link_duplex == HALF_DUPLEX)) {
4449 dev_info(&adapter->pdev->dev,
4450 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4451 adapter->hw.dev_spec._82575.eee_disable = true;
4452 adapter->flags &= ~IGB_FLAG_EEE;
4453 }
4454
4455 /* check if SmartSpeed worked */
4456 igb_check_downshift(hw);
4457 if (phy->speed_downgraded)
4458 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4459
4460 /* check for thermal sensor event */
4461 if (igb_thermal_sensor_event(hw,
4462 E1000_THSTAT_LINK_THROTTLE))
4463 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4464
4465 /* adjust timeout factor according to speed/duplex */
4466 adapter->tx_timeout_factor = 1;
4467 switch (adapter->link_speed) {
4468 case SPEED_10:
4469 adapter->tx_timeout_factor = 14;
4470 break;
4471 case SPEED_100:
4472 /* maybe add some timeout factor ? */
4473 break;
4474 }
4475
4476 if (adapter->link_speed != SPEED_1000)
4477 goto no_wait;
4478
4479 /* wait for Remote receiver status OK */
4480 retry_read_status:
4481 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
4482 &phy_data)) {
4483 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4484 retry_count) {
4485 msleep(100);
4486 retry_count--;
4487 goto retry_read_status;
4488 } else if (!retry_count) {
4489 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
4490 }
4491 } else {
4492 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
4493 }
4494 no_wait:
4495 netif_carrier_on(netdev);
4496
4497 igb_ping_all_vfs(adapter);
4498 igb_check_vf_rate_limit(adapter);
4499
4500 /* link state has changed, schedule phy info update */
4501 if (!test_bit(__IGB_DOWN, &adapter->state))
4502 mod_timer(&adapter->phy_info_timer,
4503 round_jiffies(jiffies + 2 * HZ));
4504 }
4505 } else {
4506 if (netif_carrier_ok(netdev)) {
4507 adapter->link_speed = 0;
4508 adapter->link_duplex = 0;
4509
4510 /* check for thermal sensor event */
4511 if (igb_thermal_sensor_event(hw,
4512 E1000_THSTAT_PWR_DOWN)) {
4513 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4514 }
4515
4516 /* Links status message must follow this format */
4517 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4518 netdev->name);
4519 netif_carrier_off(netdev);
4520
4521 igb_ping_all_vfs(adapter);
4522
4523 /* link state has changed, schedule phy info update */
4524 if (!test_bit(__IGB_DOWN, &adapter->state))
4525 mod_timer(&adapter->phy_info_timer,
4526 round_jiffies(jiffies + 2 * HZ));
4527
4528 /* link is down, time to check for alternate media */
4529 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4530 igb_check_swap_media(adapter);
4531 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4532 schedule_work(&adapter->reset_task);
4533 /* return immediately */
4534 return;
4535 }
4536 }
4537 pm_schedule_suspend(netdev->dev.parent,
4538 MSEC_PER_SEC * 5);
4539
4540 /* also check for alternate media here */
4541 } else if (!netif_carrier_ok(netdev) &&
4542 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4543 igb_check_swap_media(adapter);
4544 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4545 schedule_work(&adapter->reset_task);
4546 /* return immediately */
4547 return;
4548 }
4549 }
4550 }
4551
4552 spin_lock(&adapter->stats64_lock);
4553 igb_update_stats(adapter, &adapter->stats64);
4554 spin_unlock(&adapter->stats64_lock);
4555
4556 for (i = 0; i < adapter->num_tx_queues; i++) {
4557 struct igb_ring *tx_ring = adapter->tx_ring[i];
4558 if (!netif_carrier_ok(netdev)) {
4559 /* We've lost link, so the controller stops DMA,
4560 * but we've got queued Tx work that's never going
4561 * to get done, so reset controller to flush Tx.
4562 * (Do the reset outside of interrupt context).
4563 */
4564 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4565 adapter->tx_timeout_count++;
4566 schedule_work(&adapter->reset_task);
4567 /* return immediately since reset is imminent */
4568 return;
4569 }
4570 }
4571
4572 /* Force detection of hung controller every watchdog period */
4573 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4574 }
4575
4576 /* Cause software interrupt to ensure Rx ring is cleaned */
4577 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4578 u32 eics = 0;
4579
4580 for (i = 0; i < adapter->num_q_vectors; i++)
4581 eics |= adapter->q_vector[i]->eims_value;
4582 wr32(E1000_EICS, eics);
4583 } else {
4584 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4585 }
4586
4587 igb_spoof_check(adapter);
4588 igb_ptp_rx_hang(adapter);
4589
4590 /* Check LVMMC register on i350/i354 only */
4591 if ((adapter->hw.mac.type == e1000_i350) ||
4592 (adapter->hw.mac.type == e1000_i354))
4593 igb_check_lvmmc(adapter);
4594
4595 /* Reset the timer */
4596 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4597 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4598 mod_timer(&adapter->watchdog_timer,
4599 round_jiffies(jiffies + HZ));
4600 else
4601 mod_timer(&adapter->watchdog_timer,
4602 round_jiffies(jiffies + 2 * HZ));
4603 }
4604 }
4605
4606 enum latency_range {
4607 lowest_latency = 0,
4608 low_latency = 1,
4609 bulk_latency = 2,
4610 latency_invalid = 255
4611 };
4612
4613 /**
4614 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4615 * @q_vector: pointer to q_vector
4616 *
4617 * Stores a new ITR value based on strictly on packet size. This
4618 * algorithm is less sophisticated than that used in igb_update_itr,
4619 * due to the difficulty of synchronizing statistics across multiple
4620 * receive rings. The divisors and thresholds used by this function
4621 * were determined based on theoretical maximum wire speed and testing
4622 * data, in order to minimize response time while increasing bulk
4623 * throughput.
4624 * This functionality is controlled by ethtool's coalescing settings.
4625 * NOTE: This function is called only when operating in a multiqueue
4626 * receive environment.
4627 **/
4628 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4629 {
4630 int new_val = q_vector->itr_val;
4631 int avg_wire_size = 0;
4632 struct igb_adapter *adapter = q_vector->adapter;
4633 unsigned int packets;
4634
4635 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4636 * ints/sec - ITR timer value of 120 ticks.
4637 */
4638 if (adapter->link_speed != SPEED_1000) {
4639 new_val = IGB_4K_ITR;
4640 goto set_itr_val;
4641 }
4642
4643 packets = q_vector->rx.total_packets;
4644 if (packets)
4645 avg_wire_size = q_vector->rx.total_bytes / packets;
4646
4647 packets = q_vector->tx.total_packets;
4648 if (packets)
4649 avg_wire_size = max_t(u32, avg_wire_size,
4650 q_vector->tx.total_bytes / packets);
4651
4652 /* if avg_wire_size isn't set no work was done */
4653 if (!avg_wire_size)
4654 goto clear_counts;
4655
4656 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4657 avg_wire_size += 24;
4658
4659 /* Don't starve jumbo frames */
4660 avg_wire_size = min(avg_wire_size, 3000);
4661
4662 /* Give a little boost to mid-size frames */
4663 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4664 new_val = avg_wire_size / 3;
4665 else
4666 new_val = avg_wire_size / 2;
4667
4668 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4669 if (new_val < IGB_20K_ITR &&
4670 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4671 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4672 new_val = IGB_20K_ITR;
4673
4674 set_itr_val:
4675 if (new_val != q_vector->itr_val) {
4676 q_vector->itr_val = new_val;
4677 q_vector->set_itr = 1;
4678 }
4679 clear_counts:
4680 q_vector->rx.total_bytes = 0;
4681 q_vector->rx.total_packets = 0;
4682 q_vector->tx.total_bytes = 0;
4683 q_vector->tx.total_packets = 0;
4684 }
4685
4686 /**
4687 * igb_update_itr - update the dynamic ITR value based on statistics
4688 * @q_vector: pointer to q_vector
4689 * @ring_container: ring info to update the itr for
4690 *
4691 * Stores a new ITR value based on packets and byte
4692 * counts during the last interrupt. The advantage of per interrupt
4693 * computation is faster updates and more accurate ITR for the current
4694 * traffic pattern. Constants in this function were computed
4695 * based on theoretical maximum wire speed and thresholds were set based
4696 * on testing data as well as attempting to minimize response time
4697 * while increasing bulk throughput.
4698 * This functionality is controlled by ethtool's coalescing settings.
4699 * NOTE: These calculations are only valid when operating in a single-
4700 * queue environment.
4701 **/
4702 static void igb_update_itr(struct igb_q_vector *q_vector,
4703 struct igb_ring_container *ring_container)
4704 {
4705 unsigned int packets = ring_container->total_packets;
4706 unsigned int bytes = ring_container->total_bytes;
4707 u8 itrval = ring_container->itr;
4708
4709 /* no packets, exit with status unchanged */
4710 if (packets == 0)
4711 return;
4712
4713 switch (itrval) {
4714 case lowest_latency:
4715 /* handle TSO and jumbo frames */
4716 if (bytes/packets > 8000)
4717 itrval = bulk_latency;
4718 else if ((packets < 5) && (bytes > 512))
4719 itrval = low_latency;
4720 break;
4721 case low_latency: /* 50 usec aka 20000 ints/s */
4722 if (bytes > 10000) {
4723 /* this if handles the TSO accounting */
4724 if (bytes/packets > 8000)
4725 itrval = bulk_latency;
4726 else if ((packets < 10) || ((bytes/packets) > 1200))
4727 itrval = bulk_latency;
4728 else if ((packets > 35))
4729 itrval = lowest_latency;
4730 } else if (bytes/packets > 2000) {
4731 itrval = bulk_latency;
4732 } else if (packets <= 2 && bytes < 512) {
4733 itrval = lowest_latency;
4734 }
4735 break;
4736 case bulk_latency: /* 250 usec aka 4000 ints/s */
4737 if (bytes > 25000) {
4738 if (packets > 35)
4739 itrval = low_latency;
4740 } else if (bytes < 1500) {
4741 itrval = low_latency;
4742 }
4743 break;
4744 }
4745
4746 /* clear work counters since we have the values we need */
4747 ring_container->total_bytes = 0;
4748 ring_container->total_packets = 0;
4749
4750 /* write updated itr to ring container */
4751 ring_container->itr = itrval;
4752 }
4753
4754 static void igb_set_itr(struct igb_q_vector *q_vector)
4755 {
4756 struct igb_adapter *adapter = q_vector->adapter;
4757 u32 new_itr = q_vector->itr_val;
4758 u8 current_itr = 0;
4759
4760 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4761 if (adapter->link_speed != SPEED_1000) {
4762 current_itr = 0;
4763 new_itr = IGB_4K_ITR;
4764 goto set_itr_now;
4765 }
4766
4767 igb_update_itr(q_vector, &q_vector->tx);
4768 igb_update_itr(q_vector, &q_vector->rx);
4769
4770 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4771
4772 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4773 if (current_itr == lowest_latency &&
4774 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4775 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4776 current_itr = low_latency;
4777
4778 switch (current_itr) {
4779 /* counts and packets in update_itr are dependent on these numbers */
4780 case lowest_latency:
4781 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4782 break;
4783 case low_latency:
4784 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4785 break;
4786 case bulk_latency:
4787 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4788 break;
4789 default:
4790 break;
4791 }
4792
4793 set_itr_now:
4794 if (new_itr != q_vector->itr_val) {
4795 /* this attempts to bias the interrupt rate towards Bulk
4796 * by adding intermediate steps when interrupt rate is
4797 * increasing
4798 */
4799 new_itr = new_itr > q_vector->itr_val ?
4800 max((new_itr * q_vector->itr_val) /
4801 (new_itr + (q_vector->itr_val >> 2)),
4802 new_itr) : new_itr;
4803 /* Don't write the value here; it resets the adapter's
4804 * internal timer, and causes us to delay far longer than
4805 * we should between interrupts. Instead, we write the ITR
4806 * value at the beginning of the next interrupt so the timing
4807 * ends up being correct.
4808 */
4809 q_vector->itr_val = new_itr;
4810 q_vector->set_itr = 1;
4811 }
4812 }
4813
4814 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4815 u32 type_tucmd, u32 mss_l4len_idx)
4816 {
4817 struct e1000_adv_tx_context_desc *context_desc;
4818 u16 i = tx_ring->next_to_use;
4819
4820 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4821
4822 i++;
4823 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4824
4825 /* set bits to identify this as an advanced context descriptor */
4826 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4827
4828 /* For 82575, context index must be unique per ring. */
4829 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4830 mss_l4len_idx |= tx_ring->reg_idx << 4;
4831
4832 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4833 context_desc->seqnum_seed = 0;
4834 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4835 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4836 }
4837
4838 static int igb_tso(struct igb_ring *tx_ring,
4839 struct igb_tx_buffer *first,
4840 u8 *hdr_len)
4841 {
4842 struct sk_buff *skb = first->skb;
4843 u32 vlan_macip_lens, type_tucmd;
4844 u32 mss_l4len_idx, l4len;
4845 int err;
4846
4847 if (skb->ip_summed != CHECKSUM_PARTIAL)
4848 return 0;
4849
4850 if (!skb_is_gso(skb))
4851 return 0;
4852
4853 err = skb_cow_head(skb, 0);
4854 if (err < 0)
4855 return err;
4856
4857 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4858 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4859
4860 if (first->protocol == htons(ETH_P_IP)) {
4861 struct iphdr *iph = ip_hdr(skb);
4862 iph->tot_len = 0;
4863 iph->check = 0;
4864 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4865 iph->daddr, 0,
4866 IPPROTO_TCP,
4867 0);
4868 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4869 first->tx_flags |= IGB_TX_FLAGS_TSO |
4870 IGB_TX_FLAGS_CSUM |
4871 IGB_TX_FLAGS_IPV4;
4872 } else if (skb_is_gso_v6(skb)) {
4873 ipv6_hdr(skb)->payload_len = 0;
4874 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4875 &ipv6_hdr(skb)->daddr,
4876 0, IPPROTO_TCP, 0);
4877 first->tx_flags |= IGB_TX_FLAGS_TSO |
4878 IGB_TX_FLAGS_CSUM;
4879 }
4880
4881 /* compute header lengths */
4882 l4len = tcp_hdrlen(skb);
4883 *hdr_len = skb_transport_offset(skb) + l4len;
4884
4885 /* update gso size and bytecount with header size */
4886 first->gso_segs = skb_shinfo(skb)->gso_segs;
4887 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4888
4889 /* MSS L4LEN IDX */
4890 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4891 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4892
4893 /* VLAN MACLEN IPLEN */
4894 vlan_macip_lens = skb_network_header_len(skb);
4895 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4896 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4897
4898 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4899
4900 return 1;
4901 }
4902
4903 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
4904 {
4905 unsigned int offset = 0;
4906
4907 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
4908
4909 return offset == skb_checksum_start_offset(skb);
4910 }
4911
4912 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4913 {
4914 struct sk_buff *skb = first->skb;
4915 u32 vlan_macip_lens = 0;
4916 u32 type_tucmd = 0;
4917
4918 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4919 csum_failed:
4920 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4921 return;
4922 goto no_csum;
4923 }
4924
4925 switch (skb->csum_offset) {
4926 case offsetof(struct tcphdr, check):
4927 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4928 /* fall through */
4929 case offsetof(struct udphdr, check):
4930 break;
4931 case offsetof(struct sctphdr, checksum):
4932 /* validate that this is actually an SCTP request */
4933 if (((first->protocol == htons(ETH_P_IP)) &&
4934 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
4935 ((first->protocol == htons(ETH_P_IPV6)) &&
4936 igb_ipv6_csum_is_sctp(skb))) {
4937 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
4938 break;
4939 }
4940 default:
4941 skb_checksum_help(skb);
4942 goto csum_failed;
4943 }
4944
4945 /* update TX checksum flag */
4946 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4947 vlan_macip_lens = skb_checksum_start_offset(skb) -
4948 skb_network_offset(skb);
4949 no_csum:
4950 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4951 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4952
4953 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0);
4954 }
4955
4956 #define IGB_SET_FLAG(_input, _flag, _result) \
4957 ((_flag <= _result) ? \
4958 ((u32)(_input & _flag) * (_result / _flag)) : \
4959 ((u32)(_input & _flag) / (_flag / _result)))
4960
4961 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4962 {
4963 /* set type for advanced descriptor with frame checksum insertion */
4964 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4965 E1000_ADVTXD_DCMD_DEXT |
4966 E1000_ADVTXD_DCMD_IFCS;
4967
4968 /* set HW vlan bit if vlan is present */
4969 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4970 (E1000_ADVTXD_DCMD_VLE));
4971
4972 /* set segmentation bits for TSO */
4973 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4974 (E1000_ADVTXD_DCMD_TSE));
4975
4976 /* set timestamp bit if present */
4977 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4978 (E1000_ADVTXD_MAC_TSTAMP));
4979
4980 /* insert frame checksum */
4981 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4982
4983 return cmd_type;
4984 }
4985
4986 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4987 union e1000_adv_tx_desc *tx_desc,
4988 u32 tx_flags, unsigned int paylen)
4989 {
4990 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4991
4992 /* 82575 requires a unique index per ring */
4993 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4994 olinfo_status |= tx_ring->reg_idx << 4;
4995
4996 /* insert L4 checksum */
4997 olinfo_status |= IGB_SET_FLAG(tx_flags,
4998 IGB_TX_FLAGS_CSUM,
4999 (E1000_TXD_POPTS_TXSM << 8));
5000
5001 /* insert IPv4 checksum */
5002 olinfo_status |= IGB_SET_FLAG(tx_flags,
5003 IGB_TX_FLAGS_IPV4,
5004 (E1000_TXD_POPTS_IXSM << 8));
5005
5006 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5007 }
5008
5009 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5010 {
5011 struct net_device *netdev = tx_ring->netdev;
5012
5013 netif_stop_subqueue(netdev, tx_ring->queue_index);
5014
5015 /* Herbert's original patch had:
5016 * smp_mb__after_netif_stop_queue();
5017 * but since that doesn't exist yet, just open code it.
5018 */
5019 smp_mb();
5020
5021 /* We need to check again in a case another CPU has just
5022 * made room available.
5023 */
5024 if (igb_desc_unused(tx_ring) < size)
5025 return -EBUSY;
5026
5027 /* A reprieve! */
5028 netif_wake_subqueue(netdev, tx_ring->queue_index);
5029
5030 u64_stats_update_begin(&tx_ring->tx_syncp2);
5031 tx_ring->tx_stats.restart_queue2++;
5032 u64_stats_update_end(&tx_ring->tx_syncp2);
5033
5034 return 0;
5035 }
5036
5037 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5038 {
5039 if (igb_desc_unused(tx_ring) >= size)
5040 return 0;
5041 return __igb_maybe_stop_tx(tx_ring, size);
5042 }
5043
5044 static void igb_tx_map(struct igb_ring *tx_ring,
5045 struct igb_tx_buffer *first,
5046 const u8 hdr_len)
5047 {
5048 struct sk_buff *skb = first->skb;
5049 struct igb_tx_buffer *tx_buffer;
5050 union e1000_adv_tx_desc *tx_desc;
5051 struct skb_frag_struct *frag;
5052 dma_addr_t dma;
5053 unsigned int data_len, size;
5054 u32 tx_flags = first->tx_flags;
5055 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
5056 u16 i = tx_ring->next_to_use;
5057
5058 tx_desc = IGB_TX_DESC(tx_ring, i);
5059
5060 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5061
5062 size = skb_headlen(skb);
5063 data_len = skb->data_len;
5064
5065 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5066
5067 tx_buffer = first;
5068
5069 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5070 if (dma_mapping_error(tx_ring->dev, dma))
5071 goto dma_error;
5072
5073 /* record length, and DMA address */
5074 dma_unmap_len_set(tx_buffer, len, size);
5075 dma_unmap_addr_set(tx_buffer, dma, dma);
5076
5077 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5078
5079 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5080 tx_desc->read.cmd_type_len =
5081 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
5082
5083 i++;
5084 tx_desc++;
5085 if (i == tx_ring->count) {
5086 tx_desc = IGB_TX_DESC(tx_ring, 0);
5087 i = 0;
5088 }
5089 tx_desc->read.olinfo_status = 0;
5090
5091 dma += IGB_MAX_DATA_PER_TXD;
5092 size -= IGB_MAX_DATA_PER_TXD;
5093
5094 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5095 }
5096
5097 if (likely(!data_len))
5098 break;
5099
5100 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
5101
5102 i++;
5103 tx_desc++;
5104 if (i == tx_ring->count) {
5105 tx_desc = IGB_TX_DESC(tx_ring, 0);
5106 i = 0;
5107 }
5108 tx_desc->read.olinfo_status = 0;
5109
5110 size = skb_frag_size(frag);
5111 data_len -= size;
5112
5113 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
5114 size, DMA_TO_DEVICE);
5115
5116 tx_buffer = &tx_ring->tx_buffer_info[i];
5117 }
5118
5119 /* write last descriptor with RS and EOP bits */
5120 cmd_type |= size | IGB_TXD_DCMD;
5121 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
5122
5123 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5124
5125 /* set the timestamp */
5126 first->time_stamp = jiffies;
5127
5128 /* Force memory writes to complete before letting h/w know there
5129 * are new descriptors to fetch. (Only applicable for weak-ordered
5130 * memory model archs, such as IA-64).
5131 *
5132 * We also need this memory barrier to make certain all of the
5133 * status bits have been updated before next_to_watch is written.
5134 */
5135 wmb();
5136
5137 /* set next_to_watch value indicating a packet is present */
5138 first->next_to_watch = tx_desc;
5139
5140 i++;
5141 if (i == tx_ring->count)
5142 i = 0;
5143
5144 tx_ring->next_to_use = i;
5145
5146 /* Make sure there is space in the ring for the next send. */
5147 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5148
5149 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
5150 writel(i, tx_ring->tail);
5151
5152 /* we need this if more than one processor can write to our tail
5153 * at a time, it synchronizes IO on IA64/Altix systems
5154 */
5155 mmiowb();
5156 }
5157 return;
5158
5159 dma_error:
5160 dev_err(tx_ring->dev, "TX DMA map failed\n");
5161
5162 /* clear dma mappings for failed tx_buffer_info map */
5163 for (;;) {
5164 tx_buffer = &tx_ring->tx_buffer_info[i];
5165 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5166 if (tx_buffer == first)
5167 break;
5168 if (i == 0)
5169 i = tx_ring->count;
5170 i--;
5171 }
5172
5173 tx_ring->next_to_use = i;
5174 }
5175
5176 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5177 struct igb_ring *tx_ring)
5178 {
5179 struct igb_tx_buffer *first;
5180 int tso;
5181 u32 tx_flags = 0;
5182 unsigned short f;
5183 u16 count = TXD_USE_COUNT(skb_headlen(skb));
5184 __be16 protocol = vlan_get_protocol(skb);
5185 u8 hdr_len = 0;
5186
5187 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5188 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
5189 * + 2 desc gap to keep tail from touching head,
5190 * + 1 desc for context descriptor,
5191 * otherwise try next time
5192 */
5193 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5194 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5195
5196 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5197 /* this is a hard error */
5198 return NETDEV_TX_BUSY;
5199 }
5200
5201 /* record the location of the first descriptor for this packet */
5202 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5203 first->skb = skb;
5204 first->bytecount = skb->len;
5205 first->gso_segs = 1;
5206
5207 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5208 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5209
5210 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5211 &adapter->state)) {
5212 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5213 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5214
5215 adapter->ptp_tx_skb = skb_get(skb);
5216 adapter->ptp_tx_start = jiffies;
5217 if (adapter->hw.mac.type == e1000_82576)
5218 schedule_work(&adapter->ptp_tx_work);
5219 }
5220 }
5221
5222 skb_tx_timestamp(skb);
5223
5224 if (skb_vlan_tag_present(skb)) {
5225 tx_flags |= IGB_TX_FLAGS_VLAN;
5226 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5227 }
5228
5229 /* record initial flags and protocol */
5230 first->tx_flags = tx_flags;
5231 first->protocol = protocol;
5232
5233 tso = igb_tso(tx_ring, first, &hdr_len);
5234 if (tso < 0)
5235 goto out_drop;
5236 else if (!tso)
5237 igb_tx_csum(tx_ring, first);
5238
5239 igb_tx_map(tx_ring, first, hdr_len);
5240
5241 return NETDEV_TX_OK;
5242
5243 out_drop:
5244 igb_unmap_and_free_tx_resource(tx_ring, first);
5245
5246 return NETDEV_TX_OK;
5247 }
5248
5249 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5250 struct sk_buff *skb)
5251 {
5252 unsigned int r_idx = skb->queue_mapping;
5253
5254 if (r_idx >= adapter->num_tx_queues)
5255 r_idx = r_idx % adapter->num_tx_queues;
5256
5257 return adapter->tx_ring[r_idx];
5258 }
5259
5260 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5261 struct net_device *netdev)
5262 {
5263 struct igb_adapter *adapter = netdev_priv(netdev);
5264
5265 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5266 * in order to meet this minimum size requirement.
5267 */
5268 if (skb_put_padto(skb, 17))
5269 return NETDEV_TX_OK;
5270
5271 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5272 }
5273
5274 /**
5275 * igb_tx_timeout - Respond to a Tx Hang
5276 * @netdev: network interface device structure
5277 **/
5278 static void igb_tx_timeout(struct net_device *netdev)
5279 {
5280 struct igb_adapter *adapter = netdev_priv(netdev);
5281 struct e1000_hw *hw = &adapter->hw;
5282
5283 /* Do the reset outside of interrupt context */
5284 adapter->tx_timeout_count++;
5285
5286 if (hw->mac.type >= e1000_82580)
5287 hw->dev_spec._82575.global_device_reset = true;
5288
5289 schedule_work(&adapter->reset_task);
5290 wr32(E1000_EICS,
5291 (adapter->eims_enable_mask & ~adapter->eims_other));
5292 }
5293
5294 static void igb_reset_task(struct work_struct *work)
5295 {
5296 struct igb_adapter *adapter;
5297 adapter = container_of(work, struct igb_adapter, reset_task);
5298
5299 igb_dump(adapter);
5300 netdev_err(adapter->netdev, "Reset adapter\n");
5301 igb_reinit_locked(adapter);
5302 }
5303
5304 /**
5305 * igb_get_stats64 - Get System Network Statistics
5306 * @netdev: network interface device structure
5307 * @stats: rtnl_link_stats64 pointer
5308 **/
5309 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5310 struct rtnl_link_stats64 *stats)
5311 {
5312 struct igb_adapter *adapter = netdev_priv(netdev);
5313
5314 spin_lock(&adapter->stats64_lock);
5315 igb_update_stats(adapter, &adapter->stats64);
5316 memcpy(stats, &adapter->stats64, sizeof(*stats));
5317 spin_unlock(&adapter->stats64_lock);
5318
5319 return stats;
5320 }
5321
5322 /**
5323 * igb_change_mtu - Change the Maximum Transfer Unit
5324 * @netdev: network interface device structure
5325 * @new_mtu: new value for maximum frame size
5326 *
5327 * Returns 0 on success, negative on failure
5328 **/
5329 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5330 {
5331 struct igb_adapter *adapter = netdev_priv(netdev);
5332 struct pci_dev *pdev = adapter->pdev;
5333 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5334
5335 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5336 dev_err(&pdev->dev, "Invalid MTU setting\n");
5337 return -EINVAL;
5338 }
5339
5340 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5341 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5342 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5343 return -EINVAL;
5344 }
5345
5346 /* adjust max frame to be at least the size of a standard frame */
5347 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5348 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5349
5350 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5351 usleep_range(1000, 2000);
5352
5353 /* igb_down has a dependency on max_frame_size */
5354 adapter->max_frame_size = max_frame;
5355
5356 if (netif_running(netdev))
5357 igb_down(adapter);
5358
5359 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5360 netdev->mtu, new_mtu);
5361 netdev->mtu = new_mtu;
5362
5363 if (netif_running(netdev))
5364 igb_up(adapter);
5365 else
5366 igb_reset(adapter);
5367
5368 clear_bit(__IGB_RESETTING, &adapter->state);
5369
5370 return 0;
5371 }
5372
5373 /**
5374 * igb_update_stats - Update the board statistics counters
5375 * @adapter: board private structure
5376 **/
5377 void igb_update_stats(struct igb_adapter *adapter,
5378 struct rtnl_link_stats64 *net_stats)
5379 {
5380 struct e1000_hw *hw = &adapter->hw;
5381 struct pci_dev *pdev = adapter->pdev;
5382 u32 reg, mpc;
5383 int i;
5384 u64 bytes, packets;
5385 unsigned int start;
5386 u64 _bytes, _packets;
5387
5388 /* Prevent stats update while adapter is being reset, or if the pci
5389 * connection is down.
5390 */
5391 if (adapter->link_speed == 0)
5392 return;
5393 if (pci_channel_offline(pdev))
5394 return;
5395
5396 bytes = 0;
5397 packets = 0;
5398
5399 rcu_read_lock();
5400 for (i = 0; i < adapter->num_rx_queues; i++) {
5401 struct igb_ring *ring = adapter->rx_ring[i];
5402 u32 rqdpc = rd32(E1000_RQDPC(i));
5403 if (hw->mac.type >= e1000_i210)
5404 wr32(E1000_RQDPC(i), 0);
5405
5406 if (rqdpc) {
5407 ring->rx_stats.drops += rqdpc;
5408 net_stats->rx_fifo_errors += rqdpc;
5409 }
5410
5411 do {
5412 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5413 _bytes = ring->rx_stats.bytes;
5414 _packets = ring->rx_stats.packets;
5415 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5416 bytes += _bytes;
5417 packets += _packets;
5418 }
5419
5420 net_stats->rx_bytes = bytes;
5421 net_stats->rx_packets = packets;
5422
5423 bytes = 0;
5424 packets = 0;
5425 for (i = 0; i < adapter->num_tx_queues; i++) {
5426 struct igb_ring *ring = adapter->tx_ring[i];
5427 do {
5428 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5429 _bytes = ring->tx_stats.bytes;
5430 _packets = ring->tx_stats.packets;
5431 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5432 bytes += _bytes;
5433 packets += _packets;
5434 }
5435 net_stats->tx_bytes = bytes;
5436 net_stats->tx_packets = packets;
5437 rcu_read_unlock();
5438
5439 /* read stats registers */
5440 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5441 adapter->stats.gprc += rd32(E1000_GPRC);
5442 adapter->stats.gorc += rd32(E1000_GORCL);
5443 rd32(E1000_GORCH); /* clear GORCL */
5444 adapter->stats.bprc += rd32(E1000_BPRC);
5445 adapter->stats.mprc += rd32(E1000_MPRC);
5446 adapter->stats.roc += rd32(E1000_ROC);
5447
5448 adapter->stats.prc64 += rd32(E1000_PRC64);
5449 adapter->stats.prc127 += rd32(E1000_PRC127);
5450 adapter->stats.prc255 += rd32(E1000_PRC255);
5451 adapter->stats.prc511 += rd32(E1000_PRC511);
5452 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5453 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5454 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5455 adapter->stats.sec += rd32(E1000_SEC);
5456
5457 mpc = rd32(E1000_MPC);
5458 adapter->stats.mpc += mpc;
5459 net_stats->rx_fifo_errors += mpc;
5460 adapter->stats.scc += rd32(E1000_SCC);
5461 adapter->stats.ecol += rd32(E1000_ECOL);
5462 adapter->stats.mcc += rd32(E1000_MCC);
5463 adapter->stats.latecol += rd32(E1000_LATECOL);
5464 adapter->stats.dc += rd32(E1000_DC);
5465 adapter->stats.rlec += rd32(E1000_RLEC);
5466 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5467 adapter->stats.xontxc += rd32(E1000_XONTXC);
5468 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5469 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5470 adapter->stats.fcruc += rd32(E1000_FCRUC);
5471 adapter->stats.gptc += rd32(E1000_GPTC);
5472 adapter->stats.gotc += rd32(E1000_GOTCL);
5473 rd32(E1000_GOTCH); /* clear GOTCL */
5474 adapter->stats.rnbc += rd32(E1000_RNBC);
5475 adapter->stats.ruc += rd32(E1000_RUC);
5476 adapter->stats.rfc += rd32(E1000_RFC);
5477 adapter->stats.rjc += rd32(E1000_RJC);
5478 adapter->stats.tor += rd32(E1000_TORH);
5479 adapter->stats.tot += rd32(E1000_TOTH);
5480 adapter->stats.tpr += rd32(E1000_TPR);
5481
5482 adapter->stats.ptc64 += rd32(E1000_PTC64);
5483 adapter->stats.ptc127 += rd32(E1000_PTC127);
5484 adapter->stats.ptc255 += rd32(E1000_PTC255);
5485 adapter->stats.ptc511 += rd32(E1000_PTC511);
5486 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5487 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5488
5489 adapter->stats.mptc += rd32(E1000_MPTC);
5490 adapter->stats.bptc += rd32(E1000_BPTC);
5491
5492 adapter->stats.tpt += rd32(E1000_TPT);
5493 adapter->stats.colc += rd32(E1000_COLC);
5494
5495 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5496 /* read internal phy specific stats */
5497 reg = rd32(E1000_CTRL_EXT);
5498 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5499 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5500
5501 /* this stat has invalid values on i210/i211 */
5502 if ((hw->mac.type != e1000_i210) &&
5503 (hw->mac.type != e1000_i211))
5504 adapter->stats.tncrs += rd32(E1000_TNCRS);
5505 }
5506
5507 adapter->stats.tsctc += rd32(E1000_TSCTC);
5508 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5509
5510 adapter->stats.iac += rd32(E1000_IAC);
5511 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5512 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5513 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5514 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5515 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5516 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5517 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5518 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5519
5520 /* Fill out the OS statistics structure */
5521 net_stats->multicast = adapter->stats.mprc;
5522 net_stats->collisions = adapter->stats.colc;
5523
5524 /* Rx Errors */
5525
5526 /* RLEC on some newer hardware can be incorrect so build
5527 * our own version based on RUC and ROC
5528 */
5529 net_stats->rx_errors = adapter->stats.rxerrc +
5530 adapter->stats.crcerrs + adapter->stats.algnerrc +
5531 adapter->stats.ruc + adapter->stats.roc +
5532 adapter->stats.cexterr;
5533 net_stats->rx_length_errors = adapter->stats.ruc +
5534 adapter->stats.roc;
5535 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5536 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5537 net_stats->rx_missed_errors = adapter->stats.mpc;
5538
5539 /* Tx Errors */
5540 net_stats->tx_errors = adapter->stats.ecol +
5541 adapter->stats.latecol;
5542 net_stats->tx_aborted_errors = adapter->stats.ecol;
5543 net_stats->tx_window_errors = adapter->stats.latecol;
5544 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5545
5546 /* Tx Dropped needs to be maintained elsewhere */
5547
5548 /* Management Stats */
5549 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5550 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5551 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5552
5553 /* OS2BMC Stats */
5554 reg = rd32(E1000_MANC);
5555 if (reg & E1000_MANC_EN_BMC2OS) {
5556 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5557 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5558 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5559 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5560 }
5561 }
5562
5563 static void igb_tsync_interrupt(struct igb_adapter *adapter)
5564 {
5565 struct e1000_hw *hw = &adapter->hw;
5566 struct ptp_clock_event event;
5567 struct timespec64 ts;
5568 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5569
5570 if (tsicr & TSINTR_SYS_WRAP) {
5571 event.type = PTP_CLOCK_PPS;
5572 if (adapter->ptp_caps.pps)
5573 ptp_clock_event(adapter->ptp_clock, &event);
5574 else
5575 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5576 ack |= TSINTR_SYS_WRAP;
5577 }
5578
5579 if (tsicr & E1000_TSICR_TXTS) {
5580 /* retrieve hardware timestamp */
5581 schedule_work(&adapter->ptp_tx_work);
5582 ack |= E1000_TSICR_TXTS;
5583 }
5584
5585 if (tsicr & TSINTR_TT0) {
5586 spin_lock(&adapter->tmreg_lock);
5587 ts = timespec64_add(adapter->perout[0].start,
5588 adapter->perout[0].period);
5589 /* u32 conversion of tv_sec is safe until y2106 */
5590 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5591 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
5592 tsauxc = rd32(E1000_TSAUXC);
5593 tsauxc |= TSAUXC_EN_TT0;
5594 wr32(E1000_TSAUXC, tsauxc);
5595 adapter->perout[0].start = ts;
5596 spin_unlock(&adapter->tmreg_lock);
5597 ack |= TSINTR_TT0;
5598 }
5599
5600 if (tsicr & TSINTR_TT1) {
5601 spin_lock(&adapter->tmreg_lock);
5602 ts = timespec64_add(adapter->perout[1].start,
5603 adapter->perout[1].period);
5604 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5605 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
5606 tsauxc = rd32(E1000_TSAUXC);
5607 tsauxc |= TSAUXC_EN_TT1;
5608 wr32(E1000_TSAUXC, tsauxc);
5609 adapter->perout[1].start = ts;
5610 spin_unlock(&adapter->tmreg_lock);
5611 ack |= TSINTR_TT1;
5612 }
5613
5614 if (tsicr & TSINTR_AUTT0) {
5615 nsec = rd32(E1000_AUXSTMPL0);
5616 sec = rd32(E1000_AUXSTMPH0);
5617 event.type = PTP_CLOCK_EXTTS;
5618 event.index = 0;
5619 event.timestamp = sec * 1000000000ULL + nsec;
5620 ptp_clock_event(adapter->ptp_clock, &event);
5621 ack |= TSINTR_AUTT0;
5622 }
5623
5624 if (tsicr & TSINTR_AUTT1) {
5625 nsec = rd32(E1000_AUXSTMPL1);
5626 sec = rd32(E1000_AUXSTMPH1);
5627 event.type = PTP_CLOCK_EXTTS;
5628 event.index = 1;
5629 event.timestamp = sec * 1000000000ULL + nsec;
5630 ptp_clock_event(adapter->ptp_clock, &event);
5631 ack |= TSINTR_AUTT1;
5632 }
5633
5634 /* acknowledge the interrupts */
5635 wr32(E1000_TSICR, ack);
5636 }
5637
5638 static irqreturn_t igb_msix_other(int irq, void *data)
5639 {
5640 struct igb_adapter *adapter = data;
5641 struct e1000_hw *hw = &adapter->hw;
5642 u32 icr = rd32(E1000_ICR);
5643 /* reading ICR causes bit 31 of EICR to be cleared */
5644
5645 if (icr & E1000_ICR_DRSTA)
5646 schedule_work(&adapter->reset_task);
5647
5648 if (icr & E1000_ICR_DOUTSYNC) {
5649 /* HW is reporting DMA is out of sync */
5650 adapter->stats.doosync++;
5651 /* The DMA Out of Sync is also indication of a spoof event
5652 * in IOV mode. Check the Wrong VM Behavior register to
5653 * see if it is really a spoof event.
5654 */
5655 igb_check_wvbr(adapter);
5656 }
5657
5658 /* Check for a mailbox event */
5659 if (icr & E1000_ICR_VMMB)
5660 igb_msg_task(adapter);
5661
5662 if (icr & E1000_ICR_LSC) {
5663 hw->mac.get_link_status = 1;
5664 /* guard against interrupt when we're going down */
5665 if (!test_bit(__IGB_DOWN, &adapter->state))
5666 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5667 }
5668
5669 if (icr & E1000_ICR_TS)
5670 igb_tsync_interrupt(adapter);
5671
5672 wr32(E1000_EIMS, adapter->eims_other);
5673
5674 return IRQ_HANDLED;
5675 }
5676
5677 static void igb_write_itr(struct igb_q_vector *q_vector)
5678 {
5679 struct igb_adapter *adapter = q_vector->adapter;
5680 u32 itr_val = q_vector->itr_val & 0x7FFC;
5681
5682 if (!q_vector->set_itr)
5683 return;
5684
5685 if (!itr_val)
5686 itr_val = 0x4;
5687
5688 if (adapter->hw.mac.type == e1000_82575)
5689 itr_val |= itr_val << 16;
5690 else
5691 itr_val |= E1000_EITR_CNT_IGNR;
5692
5693 writel(itr_val, q_vector->itr_register);
5694 q_vector->set_itr = 0;
5695 }
5696
5697 static irqreturn_t igb_msix_ring(int irq, void *data)
5698 {
5699 struct igb_q_vector *q_vector = data;
5700
5701 /* Write the ITR value calculated from the previous interrupt. */
5702 igb_write_itr(q_vector);
5703
5704 napi_schedule(&q_vector->napi);
5705
5706 return IRQ_HANDLED;
5707 }
5708
5709 #ifdef CONFIG_IGB_DCA
5710 static void igb_update_tx_dca(struct igb_adapter *adapter,
5711 struct igb_ring *tx_ring,
5712 int cpu)
5713 {
5714 struct e1000_hw *hw = &adapter->hw;
5715 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5716
5717 if (hw->mac.type != e1000_82575)
5718 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5719
5720 /* We can enable relaxed ordering for reads, but not writes when
5721 * DCA is enabled. This is due to a known issue in some chipsets
5722 * which will cause the DCA tag to be cleared.
5723 */
5724 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5725 E1000_DCA_TXCTRL_DATA_RRO_EN |
5726 E1000_DCA_TXCTRL_DESC_DCA_EN;
5727
5728 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5729 }
5730
5731 static void igb_update_rx_dca(struct igb_adapter *adapter,
5732 struct igb_ring *rx_ring,
5733 int cpu)
5734 {
5735 struct e1000_hw *hw = &adapter->hw;
5736 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5737
5738 if (hw->mac.type != e1000_82575)
5739 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5740
5741 /* We can enable relaxed ordering for reads, but not writes when
5742 * DCA is enabled. This is due to a known issue in some chipsets
5743 * which will cause the DCA tag to be cleared.
5744 */
5745 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5746 E1000_DCA_RXCTRL_DESC_DCA_EN;
5747
5748 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5749 }
5750
5751 static void igb_update_dca(struct igb_q_vector *q_vector)
5752 {
5753 struct igb_adapter *adapter = q_vector->adapter;
5754 int cpu = get_cpu();
5755
5756 if (q_vector->cpu == cpu)
5757 goto out_no_update;
5758
5759 if (q_vector->tx.ring)
5760 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5761
5762 if (q_vector->rx.ring)
5763 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5764
5765 q_vector->cpu = cpu;
5766 out_no_update:
5767 put_cpu();
5768 }
5769
5770 static void igb_setup_dca(struct igb_adapter *adapter)
5771 {
5772 struct e1000_hw *hw = &adapter->hw;
5773 int i;
5774
5775 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5776 return;
5777
5778 /* Always use CB2 mode, difference is masked in the CB driver. */
5779 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5780
5781 for (i = 0; i < adapter->num_q_vectors; i++) {
5782 adapter->q_vector[i]->cpu = -1;
5783 igb_update_dca(adapter->q_vector[i]);
5784 }
5785 }
5786
5787 static int __igb_notify_dca(struct device *dev, void *data)
5788 {
5789 struct net_device *netdev = dev_get_drvdata(dev);
5790 struct igb_adapter *adapter = netdev_priv(netdev);
5791 struct pci_dev *pdev = adapter->pdev;
5792 struct e1000_hw *hw = &adapter->hw;
5793 unsigned long event = *(unsigned long *)data;
5794
5795 switch (event) {
5796 case DCA_PROVIDER_ADD:
5797 /* if already enabled, don't do it again */
5798 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5799 break;
5800 if (dca_add_requester(dev) == 0) {
5801 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5802 dev_info(&pdev->dev, "DCA enabled\n");
5803 igb_setup_dca(adapter);
5804 break;
5805 }
5806 /* Fall Through since DCA is disabled. */
5807 case DCA_PROVIDER_REMOVE:
5808 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5809 /* without this a class_device is left
5810 * hanging around in the sysfs model
5811 */
5812 dca_remove_requester(dev);
5813 dev_info(&pdev->dev, "DCA disabled\n");
5814 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5815 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5816 }
5817 break;
5818 }
5819
5820 return 0;
5821 }
5822
5823 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5824 void *p)
5825 {
5826 int ret_val;
5827
5828 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5829 __igb_notify_dca);
5830
5831 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5832 }
5833 #endif /* CONFIG_IGB_DCA */
5834
5835 #ifdef CONFIG_PCI_IOV
5836 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5837 {
5838 unsigned char mac_addr[ETH_ALEN];
5839
5840 eth_zero_addr(mac_addr);
5841 igb_set_vf_mac(adapter, vf, mac_addr);
5842
5843 /* By default spoof check is enabled for all VFs */
5844 adapter->vf_data[vf].spoofchk_enabled = true;
5845
5846 return 0;
5847 }
5848
5849 #endif
5850 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5851 {
5852 struct e1000_hw *hw = &adapter->hw;
5853 u32 ping;
5854 int i;
5855
5856 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5857 ping = E1000_PF_CONTROL_MSG;
5858 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5859 ping |= E1000_VT_MSGTYPE_CTS;
5860 igb_write_mbx(hw, &ping, 1, i);
5861 }
5862 }
5863
5864 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5865 {
5866 struct e1000_hw *hw = &adapter->hw;
5867 u32 vmolr = rd32(E1000_VMOLR(vf));
5868 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5869
5870 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5871 IGB_VF_FLAG_MULTI_PROMISC);
5872 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5873
5874 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5875 vmolr |= E1000_VMOLR_MPME;
5876 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5877 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5878 } else {
5879 /* if we have hashes and we are clearing a multicast promisc
5880 * flag we need to write the hashes to the MTA as this step
5881 * was previously skipped
5882 */
5883 if (vf_data->num_vf_mc_hashes > 30) {
5884 vmolr |= E1000_VMOLR_MPME;
5885 } else if (vf_data->num_vf_mc_hashes) {
5886 int j;
5887
5888 vmolr |= E1000_VMOLR_ROMPE;
5889 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5890 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5891 }
5892 }
5893
5894 wr32(E1000_VMOLR(vf), vmolr);
5895
5896 /* there are flags left unprocessed, likely not supported */
5897 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5898 return -EINVAL;
5899
5900 return 0;
5901 }
5902
5903 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5904 u32 *msgbuf, u32 vf)
5905 {
5906 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5907 u16 *hash_list = (u16 *)&msgbuf[1];
5908 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5909 int i;
5910
5911 /* salt away the number of multicast addresses assigned
5912 * to this VF for later use to restore when the PF multi cast
5913 * list changes
5914 */
5915 vf_data->num_vf_mc_hashes = n;
5916
5917 /* only up to 30 hash values supported */
5918 if (n > 30)
5919 n = 30;
5920
5921 /* store the hashes for later use */
5922 for (i = 0; i < n; i++)
5923 vf_data->vf_mc_hashes[i] = hash_list[i];
5924
5925 /* Flush and reset the mta with the new values */
5926 igb_set_rx_mode(adapter->netdev);
5927
5928 return 0;
5929 }
5930
5931 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5932 {
5933 struct e1000_hw *hw = &adapter->hw;
5934 struct vf_data_storage *vf_data;
5935 int i, j;
5936
5937 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5938 u32 vmolr = rd32(E1000_VMOLR(i));
5939
5940 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5941
5942 vf_data = &adapter->vf_data[i];
5943
5944 if ((vf_data->num_vf_mc_hashes > 30) ||
5945 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5946 vmolr |= E1000_VMOLR_MPME;
5947 } else if (vf_data->num_vf_mc_hashes) {
5948 vmolr |= E1000_VMOLR_ROMPE;
5949 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5950 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5951 }
5952 wr32(E1000_VMOLR(i), vmolr);
5953 }
5954 }
5955
5956 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5957 {
5958 struct e1000_hw *hw = &adapter->hw;
5959 u32 pool_mask, vlvf_mask, i;
5960
5961 /* create mask for VF and other pools */
5962 pool_mask = E1000_VLVF_POOLSEL_MASK;
5963 vlvf_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5964
5965 /* drop PF from pool bits */
5966 pool_mask &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT +
5967 adapter->vfs_allocated_count));
5968
5969 /* Find the vlan filter for this id */
5970 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
5971 u32 vlvf = rd32(E1000_VLVF(i));
5972 u32 vfta_mask, vid, vfta;
5973
5974 /* remove the vf from the pool */
5975 if (!(vlvf & vlvf_mask))
5976 continue;
5977
5978 /* clear out bit from VLVF */
5979 vlvf ^= vlvf_mask;
5980
5981 /* if other pools are present, just remove ourselves */
5982 if (vlvf & pool_mask)
5983 goto update_vlvfb;
5984
5985 /* if PF is present, leave VFTA */
5986 if (vlvf & E1000_VLVF_POOLSEL_MASK)
5987 goto update_vlvf;
5988
5989 vid = vlvf & E1000_VLVF_VLANID_MASK;
5990 vfta_mask = 1 << (vid % 32);
5991
5992 /* clear bit from VFTA */
5993 vfta = adapter->shadow_vfta[vid / 32];
5994 if (vfta & vfta_mask)
5995 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
5996 update_vlvf:
5997 /* clear pool selection enable */
5998 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5999 vlvf &= E1000_VLVF_POOLSEL_MASK;
6000 else
6001 vlvf = 0;
6002 update_vlvfb:
6003 /* clear pool bits */
6004 wr32(E1000_VLVF(i), vlvf);
6005 }
6006 }
6007
6008 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6009 {
6010 u32 vlvf;
6011 int idx;
6012
6013 /* short cut the special case */
6014 if (vlan == 0)
6015 return 0;
6016
6017 /* Search for the VLAN id in the VLVF entries */
6018 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6019 vlvf = rd32(E1000_VLVF(idx));
6020 if ((vlvf & VLAN_VID_MASK) == vlan)
6021 break;
6022 }
6023
6024 return idx;
6025 }
6026
6027 void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6028 {
6029 struct e1000_hw *hw = &adapter->hw;
6030 u32 bits, pf_id;
6031 int idx;
6032
6033 idx = igb_find_vlvf_entry(hw, vid);
6034 if (!idx)
6035 return;
6036
6037 /* See if any other pools are set for this VLAN filter
6038 * entry other than the PF.
6039 */
6040 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6041 bits = ~(1 << pf_id) & E1000_VLVF_POOLSEL_MASK;
6042 bits &= rd32(E1000_VLVF(idx));
6043
6044 /* Disable the filter so this falls into the default pool. */
6045 if (!bits) {
6046 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6047 wr32(E1000_VLVF(idx), 1 << pf_id);
6048 else
6049 wr32(E1000_VLVF(idx), 0);
6050 }
6051 }
6052
6053 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6054 bool add, u32 vf)
6055 {
6056 int pf_id = adapter->vfs_allocated_count;
6057 struct e1000_hw *hw = &adapter->hw;
6058 int err;
6059
6060 /* If VLAN overlaps with one the PF is currently monitoring make
6061 * sure that we are able to allocate a VLVF entry. This may be
6062 * redundant but it guarantees PF will maintain visibility to
6063 * the VLAN.
6064 */
6065 if (add && test_bit(vid, adapter->active_vlans)) {
6066 err = igb_vfta_set(hw, vid, pf_id, true, false);
6067 if (err)
6068 return err;
6069 }
6070
6071 err = igb_vfta_set(hw, vid, vf, add, false);
6072
6073 if (add && !err)
6074 return err;
6075
6076 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6077 * we may need to drop the PF pool bit in order to allow us to free
6078 * up the VLVF resources.
6079 */
6080 if (test_bit(vid, adapter->active_vlans) ||
6081 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6082 igb_update_pf_vlvf(adapter, vid);
6083
6084 return err;
6085 }
6086
6087 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6088 {
6089 struct e1000_hw *hw = &adapter->hw;
6090
6091 if (vid)
6092 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6093 else
6094 wr32(E1000_VMVIR(vf), 0);
6095 }
6096
6097 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6098 u16 vlan, u8 qos)
6099 {
6100 int err;
6101
6102 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6103 if (err)
6104 return err;
6105
6106 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6107 igb_set_vmolr(adapter, vf, !vlan);
6108
6109 /* revoke access to previous VLAN */
6110 if (vlan != adapter->vf_data[vf].pf_vlan)
6111 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6112 false, vf);
6113
6114 adapter->vf_data[vf].pf_vlan = vlan;
6115 adapter->vf_data[vf].pf_qos = qos;
6116 igb_set_vf_vlan_strip(adapter, vf, true);
6117 dev_info(&adapter->pdev->dev,
6118 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6119 if (test_bit(__IGB_DOWN, &adapter->state)) {
6120 dev_warn(&adapter->pdev->dev,
6121 "The VF VLAN has been set, but the PF device is not up.\n");
6122 dev_warn(&adapter->pdev->dev,
6123 "Bring the PF device up before attempting to use the VF device.\n");
6124 }
6125
6126 return err;
6127 }
6128
6129 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6130 {
6131 /* Restore tagless access via VLAN 0 */
6132 igb_set_vf_vlan(adapter, 0, true, vf);
6133
6134 igb_set_vmvir(adapter, 0, vf);
6135 igb_set_vmolr(adapter, vf, true);
6136
6137 /* Remove any PF assigned VLAN */
6138 if (adapter->vf_data[vf].pf_vlan)
6139 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6140 false, vf);
6141
6142 adapter->vf_data[vf].pf_vlan = 0;
6143 adapter->vf_data[vf].pf_qos = 0;
6144 igb_set_vf_vlan_strip(adapter, vf, false);
6145
6146 return 0;
6147 }
6148
6149 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6150 int vf, u16 vlan, u8 qos)
6151 {
6152 struct igb_adapter *adapter = netdev_priv(netdev);
6153
6154 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6155 return -EINVAL;
6156
6157 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6158 igb_disable_port_vlan(adapter, vf);
6159 }
6160
6161 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6162 {
6163 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6164 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6165 int ret;
6166
6167 if (adapter->vf_data[vf].pf_vlan)
6168 return -1;
6169
6170 /* VLAN 0 is a special case, don't allow it to be removed */
6171 if (!vid && !add)
6172 return 0;
6173
6174 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
6175 if (!ret)
6176 igb_set_vf_vlan_strip(adapter, vf, !!vid);
6177 return ret;
6178 }
6179
6180 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6181 {
6182 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6183
6184 /* clear flags - except flag that indicates PF has set the MAC */
6185 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6186 vf_data->last_nack = jiffies;
6187
6188 /* reset vlans for device */
6189 igb_clear_vf_vfta(adapter, vf);
6190 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6191 igb_set_vmvir(adapter, vf_data->pf_vlan |
6192 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6193 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
6194 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
6195
6196 /* reset multicast table array for vf */
6197 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6198
6199 /* Flush and reset the mta with the new values */
6200 igb_set_rx_mode(adapter->netdev);
6201 }
6202
6203 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6204 {
6205 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6206
6207 /* clear mac address as we were hotplug removed/added */
6208 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6209 eth_zero_addr(vf_mac);
6210
6211 /* process remaining reset events */
6212 igb_vf_reset(adapter, vf);
6213 }
6214
6215 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6216 {
6217 struct e1000_hw *hw = &adapter->hw;
6218 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6219 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6220 u32 reg, msgbuf[3];
6221 u8 *addr = (u8 *)(&msgbuf[1]);
6222
6223 /* process all the same items cleared in a function level reset */
6224 igb_vf_reset(adapter, vf);
6225
6226 /* set vf mac address */
6227 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6228
6229 /* enable transmit and receive for vf */
6230 reg = rd32(E1000_VFTE);
6231 wr32(E1000_VFTE, reg | (1 << vf));
6232 reg = rd32(E1000_VFRE);
6233 wr32(E1000_VFRE, reg | (1 << vf));
6234
6235 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6236
6237 /* reply to reset with ack and vf mac address */
6238 if (!is_zero_ether_addr(vf_mac)) {
6239 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6240 memcpy(addr, vf_mac, ETH_ALEN);
6241 } else {
6242 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6243 }
6244 igb_write_mbx(hw, msgbuf, 3, vf);
6245 }
6246
6247 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6248 {
6249 /* The VF MAC Address is stored in a packed array of bytes
6250 * starting at the second 32 bit word of the msg array
6251 */
6252 unsigned char *addr = (char *)&msg[1];
6253 int err = -1;
6254
6255 if (is_valid_ether_addr(addr))
6256 err = igb_set_vf_mac(adapter, vf, addr);
6257
6258 return err;
6259 }
6260
6261 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6262 {
6263 struct e1000_hw *hw = &adapter->hw;
6264 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6265 u32 msg = E1000_VT_MSGTYPE_NACK;
6266
6267 /* if device isn't clear to send it shouldn't be reading either */
6268 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6269 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6270 igb_write_mbx(hw, &msg, 1, vf);
6271 vf_data->last_nack = jiffies;
6272 }
6273 }
6274
6275 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6276 {
6277 struct pci_dev *pdev = adapter->pdev;
6278 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6279 struct e1000_hw *hw = &adapter->hw;
6280 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6281 s32 retval;
6282
6283 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6284
6285 if (retval) {
6286 /* if receive failed revoke VF CTS stats and restart init */
6287 dev_err(&pdev->dev, "Error receiving message from VF\n");
6288 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6289 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6290 return;
6291 goto out;
6292 }
6293
6294 /* this is a message we already processed, do nothing */
6295 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6296 return;
6297
6298 /* until the vf completes a reset it should not be
6299 * allowed to start any configuration.
6300 */
6301 if (msgbuf[0] == E1000_VF_RESET) {
6302 igb_vf_reset_msg(adapter, vf);
6303 return;
6304 }
6305
6306 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6307 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6308 return;
6309 retval = -1;
6310 goto out;
6311 }
6312
6313 switch ((msgbuf[0] & 0xFFFF)) {
6314 case E1000_VF_SET_MAC_ADDR:
6315 retval = -EINVAL;
6316 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6317 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6318 else
6319 dev_warn(&pdev->dev,
6320 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6321 vf);
6322 break;
6323 case E1000_VF_SET_PROMISC:
6324 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6325 break;
6326 case E1000_VF_SET_MULTICAST:
6327 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6328 break;
6329 case E1000_VF_SET_LPE:
6330 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6331 break;
6332 case E1000_VF_SET_VLAN:
6333 retval = -1;
6334 if (vf_data->pf_vlan)
6335 dev_warn(&pdev->dev,
6336 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6337 vf);
6338 else
6339 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
6340 break;
6341 default:
6342 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6343 retval = -1;
6344 break;
6345 }
6346
6347 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6348 out:
6349 /* notify the VF of the results of what it sent us */
6350 if (retval)
6351 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6352 else
6353 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6354
6355 igb_write_mbx(hw, msgbuf, 1, vf);
6356 }
6357
6358 static void igb_msg_task(struct igb_adapter *adapter)
6359 {
6360 struct e1000_hw *hw = &adapter->hw;
6361 u32 vf;
6362
6363 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6364 /* process any reset requests */
6365 if (!igb_check_for_rst(hw, vf))
6366 igb_vf_reset_event(adapter, vf);
6367
6368 /* process any messages pending */
6369 if (!igb_check_for_msg(hw, vf))
6370 igb_rcv_msg_from_vf(adapter, vf);
6371
6372 /* process any acks */
6373 if (!igb_check_for_ack(hw, vf))
6374 igb_rcv_ack_from_vf(adapter, vf);
6375 }
6376 }
6377
6378 /**
6379 * igb_set_uta - Set unicast filter table address
6380 * @adapter: board private structure
6381 * @set: boolean indicating if we are setting or clearing bits
6382 *
6383 * The unicast table address is a register array of 32-bit registers.
6384 * The table is meant to be used in a way similar to how the MTA is used
6385 * however due to certain limitations in the hardware it is necessary to
6386 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6387 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6388 **/
6389 static void igb_set_uta(struct igb_adapter *adapter, bool set)
6390 {
6391 struct e1000_hw *hw = &adapter->hw;
6392 u32 uta = set ? ~0 : 0;
6393 int i;
6394
6395 /* we only need to do this if VMDq is enabled */
6396 if (!adapter->vfs_allocated_count)
6397 return;
6398
6399 for (i = hw->mac.uta_reg_count; i--;)
6400 array_wr32(E1000_UTA, i, uta);
6401 }
6402
6403 /**
6404 * igb_intr_msi - Interrupt Handler
6405 * @irq: interrupt number
6406 * @data: pointer to a network interface device structure
6407 **/
6408 static irqreturn_t igb_intr_msi(int irq, void *data)
6409 {
6410 struct igb_adapter *adapter = data;
6411 struct igb_q_vector *q_vector = adapter->q_vector[0];
6412 struct e1000_hw *hw = &adapter->hw;
6413 /* read ICR disables interrupts using IAM */
6414 u32 icr = rd32(E1000_ICR);
6415
6416 igb_write_itr(q_vector);
6417
6418 if (icr & E1000_ICR_DRSTA)
6419 schedule_work(&adapter->reset_task);
6420
6421 if (icr & E1000_ICR_DOUTSYNC) {
6422 /* HW is reporting DMA is out of sync */
6423 adapter->stats.doosync++;
6424 }
6425
6426 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6427 hw->mac.get_link_status = 1;
6428 if (!test_bit(__IGB_DOWN, &adapter->state))
6429 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6430 }
6431
6432 if (icr & E1000_ICR_TS)
6433 igb_tsync_interrupt(adapter);
6434
6435 napi_schedule(&q_vector->napi);
6436
6437 return IRQ_HANDLED;
6438 }
6439
6440 /**
6441 * igb_intr - Legacy Interrupt Handler
6442 * @irq: interrupt number
6443 * @data: pointer to a network interface device structure
6444 **/
6445 static irqreturn_t igb_intr(int irq, void *data)
6446 {
6447 struct igb_adapter *adapter = data;
6448 struct igb_q_vector *q_vector = adapter->q_vector[0];
6449 struct e1000_hw *hw = &adapter->hw;
6450 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6451 * need for the IMC write
6452 */
6453 u32 icr = rd32(E1000_ICR);
6454
6455 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6456 * not set, then the adapter didn't send an interrupt
6457 */
6458 if (!(icr & E1000_ICR_INT_ASSERTED))
6459 return IRQ_NONE;
6460
6461 igb_write_itr(q_vector);
6462
6463 if (icr & E1000_ICR_DRSTA)
6464 schedule_work(&adapter->reset_task);
6465
6466 if (icr & E1000_ICR_DOUTSYNC) {
6467 /* HW is reporting DMA is out of sync */
6468 adapter->stats.doosync++;
6469 }
6470
6471 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6472 hw->mac.get_link_status = 1;
6473 /* guard against interrupt when we're going down */
6474 if (!test_bit(__IGB_DOWN, &adapter->state))
6475 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6476 }
6477
6478 if (icr & E1000_ICR_TS)
6479 igb_tsync_interrupt(adapter);
6480
6481 napi_schedule(&q_vector->napi);
6482
6483 return IRQ_HANDLED;
6484 }
6485
6486 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6487 {
6488 struct igb_adapter *adapter = q_vector->adapter;
6489 struct e1000_hw *hw = &adapter->hw;
6490
6491 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6492 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6493 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6494 igb_set_itr(q_vector);
6495 else
6496 igb_update_ring_itr(q_vector);
6497 }
6498
6499 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6500 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6501 wr32(E1000_EIMS, q_vector->eims_value);
6502 else
6503 igb_irq_enable(adapter);
6504 }
6505 }
6506
6507 /**
6508 * igb_poll - NAPI Rx polling callback
6509 * @napi: napi polling structure
6510 * @budget: count of how many packets we should handle
6511 **/
6512 static int igb_poll(struct napi_struct *napi, int budget)
6513 {
6514 struct igb_q_vector *q_vector = container_of(napi,
6515 struct igb_q_vector,
6516 napi);
6517 bool clean_complete = true;
6518 int work_done = 0;
6519
6520 #ifdef CONFIG_IGB_DCA
6521 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6522 igb_update_dca(q_vector);
6523 #endif
6524 if (q_vector->tx.ring)
6525 clean_complete = igb_clean_tx_irq(q_vector);
6526
6527 if (q_vector->rx.ring) {
6528 int cleaned = igb_clean_rx_irq(q_vector, budget);
6529
6530 work_done += cleaned;
6531 clean_complete &= (cleaned < budget);
6532 }
6533
6534 /* If all work not completed, return budget and keep polling */
6535 if (!clean_complete)
6536 return budget;
6537
6538 /* If not enough Rx work done, exit the polling mode */
6539 napi_complete_done(napi, work_done);
6540 igb_ring_irq_enable(q_vector);
6541
6542 return 0;
6543 }
6544
6545 /**
6546 * igb_clean_tx_irq - Reclaim resources after transmit completes
6547 * @q_vector: pointer to q_vector containing needed info
6548 *
6549 * returns true if ring is completely cleaned
6550 **/
6551 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6552 {
6553 struct igb_adapter *adapter = q_vector->adapter;
6554 struct igb_ring *tx_ring = q_vector->tx.ring;
6555 struct igb_tx_buffer *tx_buffer;
6556 union e1000_adv_tx_desc *tx_desc;
6557 unsigned int total_bytes = 0, total_packets = 0;
6558 unsigned int budget = q_vector->tx.work_limit;
6559 unsigned int i = tx_ring->next_to_clean;
6560
6561 if (test_bit(__IGB_DOWN, &adapter->state))
6562 return true;
6563
6564 tx_buffer = &tx_ring->tx_buffer_info[i];
6565 tx_desc = IGB_TX_DESC(tx_ring, i);
6566 i -= tx_ring->count;
6567
6568 do {
6569 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6570
6571 /* if next_to_watch is not set then there is no work pending */
6572 if (!eop_desc)
6573 break;
6574
6575 /* prevent any other reads prior to eop_desc */
6576 read_barrier_depends();
6577
6578 /* if DD is not set pending work has not been completed */
6579 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6580 break;
6581
6582 /* clear next_to_watch to prevent false hangs */
6583 tx_buffer->next_to_watch = NULL;
6584
6585 /* update the statistics for this packet */
6586 total_bytes += tx_buffer->bytecount;
6587 total_packets += tx_buffer->gso_segs;
6588
6589 /* free the skb */
6590 dev_consume_skb_any(tx_buffer->skb);
6591
6592 /* unmap skb header data */
6593 dma_unmap_single(tx_ring->dev,
6594 dma_unmap_addr(tx_buffer, dma),
6595 dma_unmap_len(tx_buffer, len),
6596 DMA_TO_DEVICE);
6597
6598 /* clear tx_buffer data */
6599 tx_buffer->skb = NULL;
6600 dma_unmap_len_set(tx_buffer, len, 0);
6601
6602 /* clear last DMA location and unmap remaining buffers */
6603 while (tx_desc != eop_desc) {
6604 tx_buffer++;
6605 tx_desc++;
6606 i++;
6607 if (unlikely(!i)) {
6608 i -= tx_ring->count;
6609 tx_buffer = tx_ring->tx_buffer_info;
6610 tx_desc = IGB_TX_DESC(tx_ring, 0);
6611 }
6612
6613 /* unmap any remaining paged data */
6614 if (dma_unmap_len(tx_buffer, len)) {
6615 dma_unmap_page(tx_ring->dev,
6616 dma_unmap_addr(tx_buffer, dma),
6617 dma_unmap_len(tx_buffer, len),
6618 DMA_TO_DEVICE);
6619 dma_unmap_len_set(tx_buffer, len, 0);
6620 }
6621 }
6622
6623 /* move us one more past the eop_desc for start of next pkt */
6624 tx_buffer++;
6625 tx_desc++;
6626 i++;
6627 if (unlikely(!i)) {
6628 i -= tx_ring->count;
6629 tx_buffer = tx_ring->tx_buffer_info;
6630 tx_desc = IGB_TX_DESC(tx_ring, 0);
6631 }
6632
6633 /* issue prefetch for next Tx descriptor */
6634 prefetch(tx_desc);
6635
6636 /* update budget accounting */
6637 budget--;
6638 } while (likely(budget));
6639
6640 netdev_tx_completed_queue(txring_txq(tx_ring),
6641 total_packets, total_bytes);
6642 i += tx_ring->count;
6643 tx_ring->next_to_clean = i;
6644 u64_stats_update_begin(&tx_ring->tx_syncp);
6645 tx_ring->tx_stats.bytes += total_bytes;
6646 tx_ring->tx_stats.packets += total_packets;
6647 u64_stats_update_end(&tx_ring->tx_syncp);
6648 q_vector->tx.total_bytes += total_bytes;
6649 q_vector->tx.total_packets += total_packets;
6650
6651 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6652 struct e1000_hw *hw = &adapter->hw;
6653
6654 /* Detect a transmit hang in hardware, this serializes the
6655 * check with the clearing of time_stamp and movement of i
6656 */
6657 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6658 if (tx_buffer->next_to_watch &&
6659 time_after(jiffies, tx_buffer->time_stamp +
6660 (adapter->tx_timeout_factor * HZ)) &&
6661 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6662
6663 /* detected Tx unit hang */
6664 dev_err(tx_ring->dev,
6665 "Detected Tx Unit Hang\n"
6666 " Tx Queue <%d>\n"
6667 " TDH <%x>\n"
6668 " TDT <%x>\n"
6669 " next_to_use <%x>\n"
6670 " next_to_clean <%x>\n"
6671 "buffer_info[next_to_clean]\n"
6672 " time_stamp <%lx>\n"
6673 " next_to_watch <%p>\n"
6674 " jiffies <%lx>\n"
6675 " desc.status <%x>\n",
6676 tx_ring->queue_index,
6677 rd32(E1000_TDH(tx_ring->reg_idx)),
6678 readl(tx_ring->tail),
6679 tx_ring->next_to_use,
6680 tx_ring->next_to_clean,
6681 tx_buffer->time_stamp,
6682 tx_buffer->next_to_watch,
6683 jiffies,
6684 tx_buffer->next_to_watch->wb.status);
6685 netif_stop_subqueue(tx_ring->netdev,
6686 tx_ring->queue_index);
6687
6688 /* we are about to reset, no point in enabling stuff */
6689 return true;
6690 }
6691 }
6692
6693 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6694 if (unlikely(total_packets &&
6695 netif_carrier_ok(tx_ring->netdev) &&
6696 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6697 /* Make sure that anybody stopping the queue after this
6698 * sees the new next_to_clean.
6699 */
6700 smp_mb();
6701 if (__netif_subqueue_stopped(tx_ring->netdev,
6702 tx_ring->queue_index) &&
6703 !(test_bit(__IGB_DOWN, &adapter->state))) {
6704 netif_wake_subqueue(tx_ring->netdev,
6705 tx_ring->queue_index);
6706
6707 u64_stats_update_begin(&tx_ring->tx_syncp);
6708 tx_ring->tx_stats.restart_queue++;
6709 u64_stats_update_end(&tx_ring->tx_syncp);
6710 }
6711 }
6712
6713 return !!budget;
6714 }
6715
6716 /**
6717 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6718 * @rx_ring: rx descriptor ring to store buffers on
6719 * @old_buff: donor buffer to have page reused
6720 *
6721 * Synchronizes page for reuse by the adapter
6722 **/
6723 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6724 struct igb_rx_buffer *old_buff)
6725 {
6726 struct igb_rx_buffer *new_buff;
6727 u16 nta = rx_ring->next_to_alloc;
6728
6729 new_buff = &rx_ring->rx_buffer_info[nta];
6730
6731 /* update, and store next to alloc */
6732 nta++;
6733 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6734
6735 /* transfer page from old buffer to new buffer */
6736 *new_buff = *old_buff;
6737
6738 /* sync the buffer for use by the device */
6739 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6740 old_buff->page_offset,
6741 IGB_RX_BUFSZ,
6742 DMA_FROM_DEVICE);
6743 }
6744
6745 static inline bool igb_page_is_reserved(struct page *page)
6746 {
6747 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
6748 }
6749
6750 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6751 struct page *page,
6752 unsigned int truesize)
6753 {
6754 /* avoid re-using remote pages */
6755 if (unlikely(igb_page_is_reserved(page)))
6756 return false;
6757
6758 #if (PAGE_SIZE < 8192)
6759 /* if we are only owner of page we can reuse it */
6760 if (unlikely(page_count(page) != 1))
6761 return false;
6762
6763 /* flip page offset to other buffer */
6764 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6765 #else
6766 /* move offset up to the next cache line */
6767 rx_buffer->page_offset += truesize;
6768
6769 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6770 return false;
6771 #endif
6772
6773 /* Even if we own the page, we are not allowed to use atomic_set()
6774 * This would break get_page_unless_zero() users.
6775 */
6776 page_ref_inc(page);
6777
6778 return true;
6779 }
6780
6781 /**
6782 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6783 * @rx_ring: rx descriptor ring to transact packets on
6784 * @rx_buffer: buffer containing page to add
6785 * @rx_desc: descriptor containing length of buffer written by hardware
6786 * @skb: sk_buff to place the data into
6787 *
6788 * This function will add the data contained in rx_buffer->page to the skb.
6789 * This is done either through a direct copy if the data in the buffer is
6790 * less than the skb header size, otherwise it will just attach the page as
6791 * a frag to the skb.
6792 *
6793 * The function will then update the page offset if necessary and return
6794 * true if the buffer can be reused by the adapter.
6795 **/
6796 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6797 struct igb_rx_buffer *rx_buffer,
6798 union e1000_adv_rx_desc *rx_desc,
6799 struct sk_buff *skb)
6800 {
6801 struct page *page = rx_buffer->page;
6802 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6803 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6804 #if (PAGE_SIZE < 8192)
6805 unsigned int truesize = IGB_RX_BUFSZ;
6806 #else
6807 unsigned int truesize = SKB_DATA_ALIGN(size);
6808 #endif
6809 unsigned int pull_len;
6810
6811 if (unlikely(skb_is_nonlinear(skb)))
6812 goto add_tail_frag;
6813
6814 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6815 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6816 va += IGB_TS_HDR_LEN;
6817 size -= IGB_TS_HDR_LEN;
6818 }
6819
6820 if (likely(size <= IGB_RX_HDR_LEN)) {
6821 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6822
6823 /* page is not reserved, we can reuse buffer as-is */
6824 if (likely(!igb_page_is_reserved(page)))
6825 return true;
6826
6827 /* this page cannot be reused so discard it */
6828 __free_page(page);
6829 return false;
6830 }
6831
6832 /* we need the header to contain the greater of either ETH_HLEN or
6833 * 60 bytes if the skb->len is less than 60 for skb_pad.
6834 */
6835 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6836
6837 /* align pull length to size of long to optimize memcpy performance */
6838 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6839
6840 /* update all of the pointers */
6841 va += pull_len;
6842 size -= pull_len;
6843
6844 add_tail_frag:
6845 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6846 (unsigned long)va & ~PAGE_MASK, size, truesize);
6847
6848 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6849 }
6850
6851 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6852 union e1000_adv_rx_desc *rx_desc,
6853 struct sk_buff *skb)
6854 {
6855 struct igb_rx_buffer *rx_buffer;
6856 struct page *page;
6857
6858 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6859 page = rx_buffer->page;
6860 prefetchw(page);
6861
6862 if (likely(!skb)) {
6863 void *page_addr = page_address(page) +
6864 rx_buffer->page_offset;
6865
6866 /* prefetch first cache line of first page */
6867 prefetch(page_addr);
6868 #if L1_CACHE_BYTES < 128
6869 prefetch(page_addr + L1_CACHE_BYTES);
6870 #endif
6871
6872 /* allocate a skb to store the frags */
6873 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6874 if (unlikely(!skb)) {
6875 rx_ring->rx_stats.alloc_failed++;
6876 return NULL;
6877 }
6878
6879 /* we will be copying header into skb->data in
6880 * pskb_may_pull so it is in our interest to prefetch
6881 * it now to avoid a possible cache miss
6882 */
6883 prefetchw(skb->data);
6884 }
6885
6886 /* we are reusing so sync this buffer for CPU use */
6887 dma_sync_single_range_for_cpu(rx_ring->dev,
6888 rx_buffer->dma,
6889 rx_buffer->page_offset,
6890 IGB_RX_BUFSZ,
6891 DMA_FROM_DEVICE);
6892
6893 /* pull page into skb */
6894 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6895 /* hand second half of page back to the ring */
6896 igb_reuse_rx_page(rx_ring, rx_buffer);
6897 } else {
6898 /* we are not reusing the buffer so unmap it */
6899 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6900 PAGE_SIZE, DMA_FROM_DEVICE);
6901 }
6902
6903 /* clear contents of rx_buffer */
6904 rx_buffer->page = NULL;
6905
6906 return skb;
6907 }
6908
6909 static inline void igb_rx_checksum(struct igb_ring *ring,
6910 union e1000_adv_rx_desc *rx_desc,
6911 struct sk_buff *skb)
6912 {
6913 skb_checksum_none_assert(skb);
6914
6915 /* Ignore Checksum bit is set */
6916 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6917 return;
6918
6919 /* Rx checksum disabled via ethtool */
6920 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6921 return;
6922
6923 /* TCP/UDP checksum error bit is set */
6924 if (igb_test_staterr(rx_desc,
6925 E1000_RXDEXT_STATERR_TCPE |
6926 E1000_RXDEXT_STATERR_IPE)) {
6927 /* work around errata with sctp packets where the TCPE aka
6928 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6929 * packets, (aka let the stack check the crc32c)
6930 */
6931 if (!((skb->len == 60) &&
6932 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6933 u64_stats_update_begin(&ring->rx_syncp);
6934 ring->rx_stats.csum_err++;
6935 u64_stats_update_end(&ring->rx_syncp);
6936 }
6937 /* let the stack verify checksum errors */
6938 return;
6939 }
6940 /* It must be a TCP or UDP packet with a valid checksum */
6941 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6942 E1000_RXD_STAT_UDPCS))
6943 skb->ip_summed = CHECKSUM_UNNECESSARY;
6944
6945 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6946 le32_to_cpu(rx_desc->wb.upper.status_error));
6947 }
6948
6949 static inline void igb_rx_hash(struct igb_ring *ring,
6950 union e1000_adv_rx_desc *rx_desc,
6951 struct sk_buff *skb)
6952 {
6953 if (ring->netdev->features & NETIF_F_RXHASH)
6954 skb_set_hash(skb,
6955 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6956 PKT_HASH_TYPE_L3);
6957 }
6958
6959 /**
6960 * igb_is_non_eop - process handling of non-EOP buffers
6961 * @rx_ring: Rx ring being processed
6962 * @rx_desc: Rx descriptor for current buffer
6963 * @skb: current socket buffer containing buffer in progress
6964 *
6965 * This function updates next to clean. If the buffer is an EOP buffer
6966 * this function exits returning false, otherwise it will place the
6967 * sk_buff in the next buffer to be chained and return true indicating
6968 * that this is in fact a non-EOP buffer.
6969 **/
6970 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6971 union e1000_adv_rx_desc *rx_desc)
6972 {
6973 u32 ntc = rx_ring->next_to_clean + 1;
6974
6975 /* fetch, update, and store next to clean */
6976 ntc = (ntc < rx_ring->count) ? ntc : 0;
6977 rx_ring->next_to_clean = ntc;
6978
6979 prefetch(IGB_RX_DESC(rx_ring, ntc));
6980
6981 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6982 return false;
6983
6984 return true;
6985 }
6986
6987 /**
6988 * igb_cleanup_headers - Correct corrupted or empty headers
6989 * @rx_ring: rx descriptor ring packet is being transacted on
6990 * @rx_desc: pointer to the EOP Rx descriptor
6991 * @skb: pointer to current skb being fixed
6992 *
6993 * Address the case where we are pulling data in on pages only
6994 * and as such no data is present in the skb header.
6995 *
6996 * In addition if skb is not at least 60 bytes we need to pad it so that
6997 * it is large enough to qualify as a valid Ethernet frame.
6998 *
6999 * Returns true if an error was encountered and skb was freed.
7000 **/
7001 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
7002 union e1000_adv_rx_desc *rx_desc,
7003 struct sk_buff *skb)
7004 {
7005 if (unlikely((igb_test_staterr(rx_desc,
7006 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
7007 struct net_device *netdev = rx_ring->netdev;
7008 if (!(netdev->features & NETIF_F_RXALL)) {
7009 dev_kfree_skb_any(skb);
7010 return true;
7011 }
7012 }
7013
7014 /* if eth_skb_pad returns an error the skb was freed */
7015 if (eth_skb_pad(skb))
7016 return true;
7017
7018 return false;
7019 }
7020
7021 /**
7022 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
7023 * @rx_ring: rx descriptor ring packet is being transacted on
7024 * @rx_desc: pointer to the EOP Rx descriptor
7025 * @skb: pointer to current skb being populated
7026 *
7027 * This function checks the ring, descriptor, and packet information in
7028 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
7029 * other fields within the skb.
7030 **/
7031 static void igb_process_skb_fields(struct igb_ring *rx_ring,
7032 union e1000_adv_rx_desc *rx_desc,
7033 struct sk_buff *skb)
7034 {
7035 struct net_device *dev = rx_ring->netdev;
7036
7037 igb_rx_hash(rx_ring, rx_desc, skb);
7038
7039 igb_rx_checksum(rx_ring, rx_desc, skb);
7040
7041 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7042 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7043 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
7044
7045 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
7046 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7047 u16 vid;
7048
7049 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7050 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7051 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7052 else
7053 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7054
7055 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
7056 }
7057
7058 skb_record_rx_queue(skb, rx_ring->queue_index);
7059
7060 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7061 }
7062
7063 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
7064 {
7065 struct igb_ring *rx_ring = q_vector->rx.ring;
7066 struct sk_buff *skb = rx_ring->skb;
7067 unsigned int total_bytes = 0, total_packets = 0;
7068 u16 cleaned_count = igb_desc_unused(rx_ring);
7069
7070 while (likely(total_packets < budget)) {
7071 union e1000_adv_rx_desc *rx_desc;
7072
7073 /* return some buffers to hardware, one at a time is too slow */
7074 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7075 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7076 cleaned_count = 0;
7077 }
7078
7079 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
7080
7081 if (!rx_desc->wb.upper.status_error)
7082 break;
7083
7084 /* This memory barrier is needed to keep us from reading
7085 * any other fields out of the rx_desc until we know the
7086 * descriptor has been written back
7087 */
7088 dma_rmb();
7089
7090 /* retrieve a buffer from the ring */
7091 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
7092
7093 /* exit if we failed to retrieve a buffer */
7094 if (!skb)
7095 break;
7096
7097 cleaned_count++;
7098
7099 /* fetch next buffer in frame if non-eop */
7100 if (igb_is_non_eop(rx_ring, rx_desc))
7101 continue;
7102
7103 /* verify the packet layout is correct */
7104 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7105 skb = NULL;
7106 continue;
7107 }
7108
7109 /* probably a little skewed due to removing CRC */
7110 total_bytes += skb->len;
7111
7112 /* populate checksum, timestamp, VLAN, and protocol */
7113 igb_process_skb_fields(rx_ring, rx_desc, skb);
7114
7115 napi_gro_receive(&q_vector->napi, skb);
7116
7117 /* reset skb pointer */
7118 skb = NULL;
7119
7120 /* update budget accounting */
7121 total_packets++;
7122 }
7123
7124 /* place incomplete frames back on ring for completion */
7125 rx_ring->skb = skb;
7126
7127 u64_stats_update_begin(&rx_ring->rx_syncp);
7128 rx_ring->rx_stats.packets += total_packets;
7129 rx_ring->rx_stats.bytes += total_bytes;
7130 u64_stats_update_end(&rx_ring->rx_syncp);
7131 q_vector->rx.total_packets += total_packets;
7132 q_vector->rx.total_bytes += total_bytes;
7133
7134 if (cleaned_count)
7135 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7136
7137 return total_packets;
7138 }
7139
7140 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
7141 struct igb_rx_buffer *bi)
7142 {
7143 struct page *page = bi->page;
7144 dma_addr_t dma;
7145
7146 /* since we are recycling buffers we should seldom need to alloc */
7147 if (likely(page))
7148 return true;
7149
7150 /* alloc new page for storage */
7151 page = dev_alloc_page();
7152 if (unlikely(!page)) {
7153 rx_ring->rx_stats.alloc_failed++;
7154 return false;
7155 }
7156
7157 /* map page for use */
7158 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7159
7160 /* if mapping failed free memory back to system since
7161 * there isn't much point in holding memory we can't use
7162 */
7163 if (dma_mapping_error(rx_ring->dev, dma)) {
7164 __free_page(page);
7165
7166 rx_ring->rx_stats.alloc_failed++;
7167 return false;
7168 }
7169
7170 bi->dma = dma;
7171 bi->page = page;
7172 bi->page_offset = 0;
7173
7174 return true;
7175 }
7176
7177 /**
7178 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7179 * @adapter: address of board private structure
7180 **/
7181 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7182 {
7183 union e1000_adv_rx_desc *rx_desc;
7184 struct igb_rx_buffer *bi;
7185 u16 i = rx_ring->next_to_use;
7186
7187 /* nothing to do */
7188 if (!cleaned_count)
7189 return;
7190
7191 rx_desc = IGB_RX_DESC(rx_ring, i);
7192 bi = &rx_ring->rx_buffer_info[i];
7193 i -= rx_ring->count;
7194
7195 do {
7196 if (!igb_alloc_mapped_page(rx_ring, bi))
7197 break;
7198
7199 /* Refresh the desc even if buffer_addrs didn't change
7200 * because each write-back erases this info.
7201 */
7202 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7203
7204 rx_desc++;
7205 bi++;
7206 i++;
7207 if (unlikely(!i)) {
7208 rx_desc = IGB_RX_DESC(rx_ring, 0);
7209 bi = rx_ring->rx_buffer_info;
7210 i -= rx_ring->count;
7211 }
7212
7213 /* clear the status bits for the next_to_use descriptor */
7214 rx_desc->wb.upper.status_error = 0;
7215
7216 cleaned_count--;
7217 } while (cleaned_count);
7218
7219 i += rx_ring->count;
7220
7221 if (rx_ring->next_to_use != i) {
7222 /* record the next descriptor to use */
7223 rx_ring->next_to_use = i;
7224
7225 /* update next to alloc since we have filled the ring */
7226 rx_ring->next_to_alloc = i;
7227
7228 /* Force memory writes to complete before letting h/w
7229 * know there are new descriptors to fetch. (Only
7230 * applicable for weak-ordered memory model archs,
7231 * such as IA-64).
7232 */
7233 wmb();
7234 writel(i, rx_ring->tail);
7235 }
7236 }
7237
7238 /**
7239 * igb_mii_ioctl -
7240 * @netdev:
7241 * @ifreq:
7242 * @cmd:
7243 **/
7244 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7245 {
7246 struct igb_adapter *adapter = netdev_priv(netdev);
7247 struct mii_ioctl_data *data = if_mii(ifr);
7248
7249 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7250 return -EOPNOTSUPP;
7251
7252 switch (cmd) {
7253 case SIOCGMIIPHY:
7254 data->phy_id = adapter->hw.phy.addr;
7255 break;
7256 case SIOCGMIIREG:
7257 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7258 &data->val_out))
7259 return -EIO;
7260 break;
7261 case SIOCSMIIREG:
7262 default:
7263 return -EOPNOTSUPP;
7264 }
7265 return 0;
7266 }
7267
7268 /**
7269 * igb_ioctl -
7270 * @netdev:
7271 * @ifreq:
7272 * @cmd:
7273 **/
7274 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7275 {
7276 switch (cmd) {
7277 case SIOCGMIIPHY:
7278 case SIOCGMIIREG:
7279 case SIOCSMIIREG:
7280 return igb_mii_ioctl(netdev, ifr, cmd);
7281 case SIOCGHWTSTAMP:
7282 return igb_ptp_get_ts_config(netdev, ifr);
7283 case SIOCSHWTSTAMP:
7284 return igb_ptp_set_ts_config(netdev, ifr);
7285 default:
7286 return -EOPNOTSUPP;
7287 }
7288 }
7289
7290 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7291 {
7292 struct igb_adapter *adapter = hw->back;
7293
7294 pci_read_config_word(adapter->pdev, reg, value);
7295 }
7296
7297 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7298 {
7299 struct igb_adapter *adapter = hw->back;
7300
7301 pci_write_config_word(adapter->pdev, reg, *value);
7302 }
7303
7304 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7305 {
7306 struct igb_adapter *adapter = hw->back;
7307
7308 if (pcie_capability_read_word(adapter->pdev, reg, value))
7309 return -E1000_ERR_CONFIG;
7310
7311 return 0;
7312 }
7313
7314 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7315 {
7316 struct igb_adapter *adapter = hw->back;
7317
7318 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7319 return -E1000_ERR_CONFIG;
7320
7321 return 0;
7322 }
7323
7324 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7325 {
7326 struct igb_adapter *adapter = netdev_priv(netdev);
7327 struct e1000_hw *hw = &adapter->hw;
7328 u32 ctrl, rctl;
7329 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7330
7331 if (enable) {
7332 /* enable VLAN tag insert/strip */
7333 ctrl = rd32(E1000_CTRL);
7334 ctrl |= E1000_CTRL_VME;
7335 wr32(E1000_CTRL, ctrl);
7336
7337 /* Disable CFI check */
7338 rctl = rd32(E1000_RCTL);
7339 rctl &= ~E1000_RCTL_CFIEN;
7340 wr32(E1000_RCTL, rctl);
7341 } else {
7342 /* disable VLAN tag insert/strip */
7343 ctrl = rd32(E1000_CTRL);
7344 ctrl &= ~E1000_CTRL_VME;
7345 wr32(E1000_CTRL, ctrl);
7346 }
7347
7348 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
7349 }
7350
7351 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7352 __be16 proto, u16 vid)
7353 {
7354 struct igb_adapter *adapter = netdev_priv(netdev);
7355 struct e1000_hw *hw = &adapter->hw;
7356 int pf_id = adapter->vfs_allocated_count;
7357
7358 /* add the filter since PF can receive vlans w/o entry in vlvf */
7359 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7360 igb_vfta_set(hw, vid, pf_id, true, !!vid);
7361
7362 set_bit(vid, adapter->active_vlans);
7363
7364 return 0;
7365 }
7366
7367 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7368 __be16 proto, u16 vid)
7369 {
7370 struct igb_adapter *adapter = netdev_priv(netdev);
7371 int pf_id = adapter->vfs_allocated_count;
7372 struct e1000_hw *hw = &adapter->hw;
7373
7374 /* remove VID from filter table */
7375 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7376 igb_vfta_set(hw, vid, pf_id, false, true);
7377
7378 clear_bit(vid, adapter->active_vlans);
7379
7380 return 0;
7381 }
7382
7383 static void igb_restore_vlan(struct igb_adapter *adapter)
7384 {
7385 u16 vid = 1;
7386
7387 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7388 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
7389
7390 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
7391 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7392 }
7393
7394 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7395 {
7396 struct pci_dev *pdev = adapter->pdev;
7397 struct e1000_mac_info *mac = &adapter->hw.mac;
7398
7399 mac->autoneg = 0;
7400
7401 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7402 * for the switch() below to work
7403 */
7404 if ((spd & 1) || (dplx & ~1))
7405 goto err_inval;
7406
7407 /* Fiber NIC's only allow 1000 gbps Full duplex
7408 * and 100Mbps Full duplex for 100baseFx sfp
7409 */
7410 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7411 switch (spd + dplx) {
7412 case SPEED_10 + DUPLEX_HALF:
7413 case SPEED_10 + DUPLEX_FULL:
7414 case SPEED_100 + DUPLEX_HALF:
7415 goto err_inval;
7416 default:
7417 break;
7418 }
7419 }
7420
7421 switch (spd + dplx) {
7422 case SPEED_10 + DUPLEX_HALF:
7423 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7424 break;
7425 case SPEED_10 + DUPLEX_FULL:
7426 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7427 break;
7428 case SPEED_100 + DUPLEX_HALF:
7429 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7430 break;
7431 case SPEED_100 + DUPLEX_FULL:
7432 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7433 break;
7434 case SPEED_1000 + DUPLEX_FULL:
7435 mac->autoneg = 1;
7436 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7437 break;
7438 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7439 default:
7440 goto err_inval;
7441 }
7442
7443 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7444 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7445
7446 return 0;
7447
7448 err_inval:
7449 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7450 return -EINVAL;
7451 }
7452
7453 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7454 bool runtime)
7455 {
7456 struct net_device *netdev = pci_get_drvdata(pdev);
7457 struct igb_adapter *adapter = netdev_priv(netdev);
7458 struct e1000_hw *hw = &adapter->hw;
7459 u32 ctrl, rctl, status;
7460 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7461 #ifdef CONFIG_PM
7462 int retval = 0;
7463 #endif
7464
7465 netif_device_detach(netdev);
7466
7467 if (netif_running(netdev))
7468 __igb_close(netdev, true);
7469
7470 igb_clear_interrupt_scheme(adapter);
7471
7472 #ifdef CONFIG_PM
7473 retval = pci_save_state(pdev);
7474 if (retval)
7475 return retval;
7476 #endif
7477
7478 status = rd32(E1000_STATUS);
7479 if (status & E1000_STATUS_LU)
7480 wufc &= ~E1000_WUFC_LNKC;
7481
7482 if (wufc) {
7483 igb_setup_rctl(adapter);
7484 igb_set_rx_mode(netdev);
7485
7486 /* turn on all-multi mode if wake on multicast is enabled */
7487 if (wufc & E1000_WUFC_MC) {
7488 rctl = rd32(E1000_RCTL);
7489 rctl |= E1000_RCTL_MPE;
7490 wr32(E1000_RCTL, rctl);
7491 }
7492
7493 ctrl = rd32(E1000_CTRL);
7494 /* advertise wake from D3Cold */
7495 #define E1000_CTRL_ADVD3WUC 0x00100000
7496 /* phy power management enable */
7497 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7498 ctrl |= E1000_CTRL_ADVD3WUC;
7499 wr32(E1000_CTRL, ctrl);
7500
7501 /* Allow time for pending master requests to run */
7502 igb_disable_pcie_master(hw);
7503
7504 wr32(E1000_WUC, E1000_WUC_PME_EN);
7505 wr32(E1000_WUFC, wufc);
7506 } else {
7507 wr32(E1000_WUC, 0);
7508 wr32(E1000_WUFC, 0);
7509 }
7510
7511 *enable_wake = wufc || adapter->en_mng_pt;
7512 if (!*enable_wake)
7513 igb_power_down_link(adapter);
7514 else
7515 igb_power_up_link(adapter);
7516
7517 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7518 * would have already happened in close and is redundant.
7519 */
7520 igb_release_hw_control(adapter);
7521
7522 pci_disable_device(pdev);
7523
7524 return 0;
7525 }
7526
7527 #ifdef CONFIG_PM
7528 #ifdef CONFIG_PM_SLEEP
7529 static int igb_suspend(struct device *dev)
7530 {
7531 int retval;
7532 bool wake;
7533 struct pci_dev *pdev = to_pci_dev(dev);
7534
7535 retval = __igb_shutdown(pdev, &wake, 0);
7536 if (retval)
7537 return retval;
7538
7539 if (wake) {
7540 pci_prepare_to_sleep(pdev);
7541 } else {
7542 pci_wake_from_d3(pdev, false);
7543 pci_set_power_state(pdev, PCI_D3hot);
7544 }
7545
7546 return 0;
7547 }
7548 #endif /* CONFIG_PM_SLEEP */
7549
7550 static int igb_resume(struct device *dev)
7551 {
7552 struct pci_dev *pdev = to_pci_dev(dev);
7553 struct net_device *netdev = pci_get_drvdata(pdev);
7554 struct igb_adapter *adapter = netdev_priv(netdev);
7555 struct e1000_hw *hw = &adapter->hw;
7556 u32 err;
7557
7558 pci_set_power_state(pdev, PCI_D0);
7559 pci_restore_state(pdev);
7560 pci_save_state(pdev);
7561
7562 if (!pci_device_is_present(pdev))
7563 return -ENODEV;
7564 err = pci_enable_device_mem(pdev);
7565 if (err) {
7566 dev_err(&pdev->dev,
7567 "igb: Cannot enable PCI device from suspend\n");
7568 return err;
7569 }
7570 pci_set_master(pdev);
7571
7572 pci_enable_wake(pdev, PCI_D3hot, 0);
7573 pci_enable_wake(pdev, PCI_D3cold, 0);
7574
7575 if (igb_init_interrupt_scheme(adapter, true)) {
7576 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7577 rtnl_unlock();
7578 return -ENOMEM;
7579 }
7580
7581 igb_reset(adapter);
7582
7583 /* let the f/w know that the h/w is now under the control of the
7584 * driver.
7585 */
7586 igb_get_hw_control(adapter);
7587
7588 wr32(E1000_WUS, ~0);
7589
7590 if (netdev->flags & IFF_UP) {
7591 rtnl_lock();
7592 err = __igb_open(netdev, true);
7593 rtnl_unlock();
7594 if (err)
7595 return err;
7596 }
7597
7598 netif_device_attach(netdev);
7599 return 0;
7600 }
7601
7602 static int igb_runtime_idle(struct device *dev)
7603 {
7604 struct pci_dev *pdev = to_pci_dev(dev);
7605 struct net_device *netdev = pci_get_drvdata(pdev);
7606 struct igb_adapter *adapter = netdev_priv(netdev);
7607
7608 if (!igb_has_link(adapter))
7609 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7610
7611 return -EBUSY;
7612 }
7613
7614 static int igb_runtime_suspend(struct device *dev)
7615 {
7616 struct pci_dev *pdev = to_pci_dev(dev);
7617 int retval;
7618 bool wake;
7619
7620 retval = __igb_shutdown(pdev, &wake, 1);
7621 if (retval)
7622 return retval;
7623
7624 if (wake) {
7625 pci_prepare_to_sleep(pdev);
7626 } else {
7627 pci_wake_from_d3(pdev, false);
7628 pci_set_power_state(pdev, PCI_D3hot);
7629 }
7630
7631 return 0;
7632 }
7633
7634 static int igb_runtime_resume(struct device *dev)
7635 {
7636 return igb_resume(dev);
7637 }
7638 #endif /* CONFIG_PM */
7639
7640 static void igb_shutdown(struct pci_dev *pdev)
7641 {
7642 bool wake;
7643
7644 __igb_shutdown(pdev, &wake, 0);
7645
7646 if (system_state == SYSTEM_POWER_OFF) {
7647 pci_wake_from_d3(pdev, wake);
7648 pci_set_power_state(pdev, PCI_D3hot);
7649 }
7650 }
7651
7652 #ifdef CONFIG_PCI_IOV
7653 static int igb_sriov_reinit(struct pci_dev *dev)
7654 {
7655 struct net_device *netdev = pci_get_drvdata(dev);
7656 struct igb_adapter *adapter = netdev_priv(netdev);
7657 struct pci_dev *pdev = adapter->pdev;
7658
7659 rtnl_lock();
7660
7661 if (netif_running(netdev))
7662 igb_close(netdev);
7663 else
7664 igb_reset(adapter);
7665
7666 igb_clear_interrupt_scheme(adapter);
7667
7668 igb_init_queue_configuration(adapter);
7669
7670 if (igb_init_interrupt_scheme(adapter, true)) {
7671 rtnl_unlock();
7672 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7673 return -ENOMEM;
7674 }
7675
7676 if (netif_running(netdev))
7677 igb_open(netdev);
7678
7679 rtnl_unlock();
7680
7681 return 0;
7682 }
7683
7684 static int igb_pci_disable_sriov(struct pci_dev *dev)
7685 {
7686 int err = igb_disable_sriov(dev);
7687
7688 if (!err)
7689 err = igb_sriov_reinit(dev);
7690
7691 return err;
7692 }
7693
7694 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7695 {
7696 int err = igb_enable_sriov(dev, num_vfs);
7697
7698 if (err)
7699 goto out;
7700
7701 err = igb_sriov_reinit(dev);
7702 if (!err)
7703 return num_vfs;
7704
7705 out:
7706 return err;
7707 }
7708
7709 #endif
7710 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7711 {
7712 #ifdef CONFIG_PCI_IOV
7713 if (num_vfs == 0)
7714 return igb_pci_disable_sriov(dev);
7715 else
7716 return igb_pci_enable_sriov(dev, num_vfs);
7717 #endif
7718 return 0;
7719 }
7720
7721 #ifdef CONFIG_NET_POLL_CONTROLLER
7722 /* Polling 'interrupt' - used by things like netconsole to send skbs
7723 * without having to re-enable interrupts. It's not called while
7724 * the interrupt routine is executing.
7725 */
7726 static void igb_netpoll(struct net_device *netdev)
7727 {
7728 struct igb_adapter *adapter = netdev_priv(netdev);
7729 struct e1000_hw *hw = &adapter->hw;
7730 struct igb_q_vector *q_vector;
7731 int i;
7732
7733 for (i = 0; i < adapter->num_q_vectors; i++) {
7734 q_vector = adapter->q_vector[i];
7735 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7736 wr32(E1000_EIMC, q_vector->eims_value);
7737 else
7738 igb_irq_disable(adapter);
7739 napi_schedule(&q_vector->napi);
7740 }
7741 }
7742 #endif /* CONFIG_NET_POLL_CONTROLLER */
7743
7744 /**
7745 * igb_io_error_detected - called when PCI error is detected
7746 * @pdev: Pointer to PCI device
7747 * @state: The current pci connection state
7748 *
7749 * This function is called after a PCI bus error affecting
7750 * this device has been detected.
7751 **/
7752 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7753 pci_channel_state_t state)
7754 {
7755 struct net_device *netdev = pci_get_drvdata(pdev);
7756 struct igb_adapter *adapter = netdev_priv(netdev);
7757
7758 netif_device_detach(netdev);
7759
7760 if (state == pci_channel_io_perm_failure)
7761 return PCI_ERS_RESULT_DISCONNECT;
7762
7763 if (netif_running(netdev))
7764 igb_down(adapter);
7765 pci_disable_device(pdev);
7766
7767 /* Request a slot slot reset. */
7768 return PCI_ERS_RESULT_NEED_RESET;
7769 }
7770
7771 /**
7772 * igb_io_slot_reset - called after the pci bus has been reset.
7773 * @pdev: Pointer to PCI device
7774 *
7775 * Restart the card from scratch, as if from a cold-boot. Implementation
7776 * resembles the first-half of the igb_resume routine.
7777 **/
7778 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7779 {
7780 struct net_device *netdev = pci_get_drvdata(pdev);
7781 struct igb_adapter *adapter = netdev_priv(netdev);
7782 struct e1000_hw *hw = &adapter->hw;
7783 pci_ers_result_t result;
7784 int err;
7785
7786 if (pci_enable_device_mem(pdev)) {
7787 dev_err(&pdev->dev,
7788 "Cannot re-enable PCI device after reset.\n");
7789 result = PCI_ERS_RESULT_DISCONNECT;
7790 } else {
7791 pci_set_master(pdev);
7792 pci_restore_state(pdev);
7793 pci_save_state(pdev);
7794
7795 pci_enable_wake(pdev, PCI_D3hot, 0);
7796 pci_enable_wake(pdev, PCI_D3cold, 0);
7797
7798 igb_reset(adapter);
7799 wr32(E1000_WUS, ~0);
7800 result = PCI_ERS_RESULT_RECOVERED;
7801 }
7802
7803 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7804 if (err) {
7805 dev_err(&pdev->dev,
7806 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7807 err);
7808 /* non-fatal, continue */
7809 }
7810
7811 return result;
7812 }
7813
7814 /**
7815 * igb_io_resume - called when traffic can start flowing again.
7816 * @pdev: Pointer to PCI device
7817 *
7818 * This callback is called when the error recovery driver tells us that
7819 * its OK to resume normal operation. Implementation resembles the
7820 * second-half of the igb_resume routine.
7821 */
7822 static void igb_io_resume(struct pci_dev *pdev)
7823 {
7824 struct net_device *netdev = pci_get_drvdata(pdev);
7825 struct igb_adapter *adapter = netdev_priv(netdev);
7826
7827 if (netif_running(netdev)) {
7828 if (igb_up(adapter)) {
7829 dev_err(&pdev->dev, "igb_up failed after reset\n");
7830 return;
7831 }
7832 }
7833
7834 netif_device_attach(netdev);
7835
7836 /* let the f/w know that the h/w is now under the control of the
7837 * driver.
7838 */
7839 igb_get_hw_control(adapter);
7840 }
7841
7842 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7843 u8 qsel)
7844 {
7845 struct e1000_hw *hw = &adapter->hw;
7846 u32 rar_low, rar_high;
7847
7848 /* HW expects these to be in network order when they are plugged
7849 * into the registers which are little endian. In order to guarantee
7850 * that ordering we need to do an leXX_to_cpup here in order to be
7851 * ready for the byteswap that occurs with writel
7852 */
7853 rar_low = le32_to_cpup((__le32 *)(addr));
7854 rar_high = le16_to_cpup((__le16 *)(addr + 4));
7855
7856 /* Indicate to hardware the Address is Valid. */
7857 rar_high |= E1000_RAH_AV;
7858
7859 if (hw->mac.type == e1000_82575)
7860 rar_high |= E1000_RAH_POOL_1 * qsel;
7861 else
7862 rar_high |= E1000_RAH_POOL_1 << qsel;
7863
7864 wr32(E1000_RAL(index), rar_low);
7865 wrfl();
7866 wr32(E1000_RAH(index), rar_high);
7867 wrfl();
7868 }
7869
7870 static int igb_set_vf_mac(struct igb_adapter *adapter,
7871 int vf, unsigned char *mac_addr)
7872 {
7873 struct e1000_hw *hw = &adapter->hw;
7874 /* VF MAC addresses start at end of receive addresses and moves
7875 * towards the first, as a result a collision should not be possible
7876 */
7877 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7878
7879 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7880
7881 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7882
7883 return 0;
7884 }
7885
7886 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7887 {
7888 struct igb_adapter *adapter = netdev_priv(netdev);
7889 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7890 return -EINVAL;
7891 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7892 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7893 dev_info(&adapter->pdev->dev,
7894 "Reload the VF driver to make this change effective.");
7895 if (test_bit(__IGB_DOWN, &adapter->state)) {
7896 dev_warn(&adapter->pdev->dev,
7897 "The VF MAC address has been set, but the PF device is not up.\n");
7898 dev_warn(&adapter->pdev->dev,
7899 "Bring the PF device up before attempting to use the VF device.\n");
7900 }
7901 return igb_set_vf_mac(adapter, vf, mac);
7902 }
7903
7904 static int igb_link_mbps(int internal_link_speed)
7905 {
7906 switch (internal_link_speed) {
7907 case SPEED_100:
7908 return 100;
7909 case SPEED_1000:
7910 return 1000;
7911 default:
7912 return 0;
7913 }
7914 }
7915
7916 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7917 int link_speed)
7918 {
7919 int rf_dec, rf_int;
7920 u32 bcnrc_val;
7921
7922 if (tx_rate != 0) {
7923 /* Calculate the rate factor values to set */
7924 rf_int = link_speed / tx_rate;
7925 rf_dec = (link_speed - (rf_int * tx_rate));
7926 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7927 tx_rate;
7928
7929 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7930 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7931 E1000_RTTBCNRC_RF_INT_MASK);
7932 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7933 } else {
7934 bcnrc_val = 0;
7935 }
7936
7937 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7938 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7939 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7940 */
7941 wr32(E1000_RTTBCNRM, 0x14);
7942 wr32(E1000_RTTBCNRC, bcnrc_val);
7943 }
7944
7945 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7946 {
7947 int actual_link_speed, i;
7948 bool reset_rate = false;
7949
7950 /* VF TX rate limit was not set or not supported */
7951 if ((adapter->vf_rate_link_speed == 0) ||
7952 (adapter->hw.mac.type != e1000_82576))
7953 return;
7954
7955 actual_link_speed = igb_link_mbps(adapter->link_speed);
7956 if (actual_link_speed != adapter->vf_rate_link_speed) {
7957 reset_rate = true;
7958 adapter->vf_rate_link_speed = 0;
7959 dev_info(&adapter->pdev->dev,
7960 "Link speed has been changed. VF Transmit rate is disabled\n");
7961 }
7962
7963 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7964 if (reset_rate)
7965 adapter->vf_data[i].tx_rate = 0;
7966
7967 igb_set_vf_rate_limit(&adapter->hw, i,
7968 adapter->vf_data[i].tx_rate,
7969 actual_link_speed);
7970 }
7971 }
7972
7973 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7974 int min_tx_rate, int max_tx_rate)
7975 {
7976 struct igb_adapter *adapter = netdev_priv(netdev);
7977 struct e1000_hw *hw = &adapter->hw;
7978 int actual_link_speed;
7979
7980 if (hw->mac.type != e1000_82576)
7981 return -EOPNOTSUPP;
7982
7983 if (min_tx_rate)
7984 return -EINVAL;
7985
7986 actual_link_speed = igb_link_mbps(adapter->link_speed);
7987 if ((vf >= adapter->vfs_allocated_count) ||
7988 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7989 (max_tx_rate < 0) ||
7990 (max_tx_rate > actual_link_speed))
7991 return -EINVAL;
7992
7993 adapter->vf_rate_link_speed = actual_link_speed;
7994 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7995 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7996
7997 return 0;
7998 }
7999
8000 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
8001 bool setting)
8002 {
8003 struct igb_adapter *adapter = netdev_priv(netdev);
8004 struct e1000_hw *hw = &adapter->hw;
8005 u32 reg_val, reg_offset;
8006
8007 if (!adapter->vfs_allocated_count)
8008 return -EOPNOTSUPP;
8009
8010 if (vf >= adapter->vfs_allocated_count)
8011 return -EINVAL;
8012
8013 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
8014 reg_val = rd32(reg_offset);
8015 if (setting)
8016 reg_val |= ((1 << vf) |
8017 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
8018 else
8019 reg_val &= ~((1 << vf) |
8020 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
8021 wr32(reg_offset, reg_val);
8022
8023 adapter->vf_data[vf].spoofchk_enabled = setting;
8024 return 0;
8025 }
8026
8027 static int igb_ndo_get_vf_config(struct net_device *netdev,
8028 int vf, struct ifla_vf_info *ivi)
8029 {
8030 struct igb_adapter *adapter = netdev_priv(netdev);
8031 if (vf >= adapter->vfs_allocated_count)
8032 return -EINVAL;
8033 ivi->vf = vf;
8034 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
8035 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8036 ivi->min_tx_rate = 0;
8037 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8038 ivi->qos = adapter->vf_data[vf].pf_qos;
8039 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8040 return 0;
8041 }
8042
8043 static void igb_vmm_control(struct igb_adapter *adapter)
8044 {
8045 struct e1000_hw *hw = &adapter->hw;
8046 u32 reg;
8047
8048 switch (hw->mac.type) {
8049 case e1000_82575:
8050 case e1000_i210:
8051 case e1000_i211:
8052 case e1000_i354:
8053 default:
8054 /* replication is not supported for 82575 */
8055 return;
8056 case e1000_82576:
8057 /* notify HW that the MAC is adding vlan tags */
8058 reg = rd32(E1000_DTXCTL);
8059 reg |= E1000_DTXCTL_VLAN_ADDED;
8060 wr32(E1000_DTXCTL, reg);
8061 /* Fall through */
8062 case e1000_82580:
8063 /* enable replication vlan tag stripping */
8064 reg = rd32(E1000_RPLOLR);
8065 reg |= E1000_RPLOLR_STRVLAN;
8066 wr32(E1000_RPLOLR, reg);
8067 /* Fall through */
8068 case e1000_i350:
8069 /* none of the above registers are supported by i350 */
8070 break;
8071 }
8072
8073 if (adapter->vfs_allocated_count) {
8074 igb_vmdq_set_loopback_pf(hw, true);
8075 igb_vmdq_set_replication_pf(hw, true);
8076 igb_vmdq_set_anti_spoofing_pf(hw, true,
8077 adapter->vfs_allocated_count);
8078 } else {
8079 igb_vmdq_set_loopback_pf(hw, false);
8080 igb_vmdq_set_replication_pf(hw, false);
8081 }
8082 }
8083
8084 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8085 {
8086 struct e1000_hw *hw = &adapter->hw;
8087 u32 dmac_thr;
8088 u16 hwm;
8089
8090 if (hw->mac.type > e1000_82580) {
8091 if (adapter->flags & IGB_FLAG_DMAC) {
8092 u32 reg;
8093
8094 /* force threshold to 0. */
8095 wr32(E1000_DMCTXTH, 0);
8096
8097 /* DMA Coalescing high water mark needs to be greater
8098 * than the Rx threshold. Set hwm to PBA - max frame
8099 * size in 16B units, capping it at PBA - 6KB.
8100 */
8101 hwm = 64 * (pba - 6);
8102 reg = rd32(E1000_FCRTC);
8103 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8104 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8105 & E1000_FCRTC_RTH_COAL_MASK);
8106 wr32(E1000_FCRTC, reg);
8107
8108 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
8109 * frame size, capping it at PBA - 10KB.
8110 */
8111 dmac_thr = pba - 10;
8112 reg = rd32(E1000_DMACR);
8113 reg &= ~E1000_DMACR_DMACTHR_MASK;
8114 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8115 & E1000_DMACR_DMACTHR_MASK);
8116
8117 /* transition to L0x or L1 if available..*/
8118 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8119
8120 /* watchdog timer= +-1000 usec in 32usec intervals */
8121 reg |= (1000 >> 5);
8122
8123 /* Disable BMC-to-OS Watchdog Enable */
8124 if (hw->mac.type != e1000_i354)
8125 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8126
8127 wr32(E1000_DMACR, reg);
8128
8129 /* no lower threshold to disable
8130 * coalescing(smart fifb)-UTRESH=0
8131 */
8132 wr32(E1000_DMCRTRH, 0);
8133
8134 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8135
8136 wr32(E1000_DMCTLX, reg);
8137
8138 /* free space in tx packet buffer to wake from
8139 * DMA coal
8140 */
8141 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8142 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8143
8144 /* make low power state decision controlled
8145 * by DMA coal
8146 */
8147 reg = rd32(E1000_PCIEMISC);
8148 reg &= ~E1000_PCIEMISC_LX_DECISION;
8149 wr32(E1000_PCIEMISC, reg);
8150 } /* endif adapter->dmac is not disabled */
8151 } else if (hw->mac.type == e1000_82580) {
8152 u32 reg = rd32(E1000_PCIEMISC);
8153
8154 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8155 wr32(E1000_DMACR, 0);
8156 }
8157 }
8158
8159 /**
8160 * igb_read_i2c_byte - Reads 8 bit word over I2C
8161 * @hw: pointer to hardware structure
8162 * @byte_offset: byte offset to read
8163 * @dev_addr: device address
8164 * @data: value read
8165 *
8166 * Performs byte read operation over I2C interface at
8167 * a specified device address.
8168 **/
8169 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8170 u8 dev_addr, u8 *data)
8171 {
8172 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8173 struct i2c_client *this_client = adapter->i2c_client;
8174 s32 status;
8175 u16 swfw_mask = 0;
8176
8177 if (!this_client)
8178 return E1000_ERR_I2C;
8179
8180 swfw_mask = E1000_SWFW_PHY0_SM;
8181
8182 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8183 return E1000_ERR_SWFW_SYNC;
8184
8185 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8186 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8187
8188 if (status < 0)
8189 return E1000_ERR_I2C;
8190 else {
8191 *data = status;
8192 return 0;
8193 }
8194 }
8195
8196 /**
8197 * igb_write_i2c_byte - Writes 8 bit word over I2C
8198 * @hw: pointer to hardware structure
8199 * @byte_offset: byte offset to write
8200 * @dev_addr: device address
8201 * @data: value to write
8202 *
8203 * Performs byte write operation over I2C interface at
8204 * a specified device address.
8205 **/
8206 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8207 u8 dev_addr, u8 data)
8208 {
8209 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8210 struct i2c_client *this_client = adapter->i2c_client;
8211 s32 status;
8212 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8213
8214 if (!this_client)
8215 return E1000_ERR_I2C;
8216
8217 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8218 return E1000_ERR_SWFW_SYNC;
8219 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8220 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8221
8222 if (status)
8223 return E1000_ERR_I2C;
8224 else
8225 return 0;
8226
8227 }
8228
8229 int igb_reinit_queues(struct igb_adapter *adapter)
8230 {
8231 struct net_device *netdev = adapter->netdev;
8232 struct pci_dev *pdev = adapter->pdev;
8233 int err = 0;
8234
8235 if (netif_running(netdev))
8236 igb_close(netdev);
8237
8238 igb_reset_interrupt_capability(adapter);
8239
8240 if (igb_init_interrupt_scheme(adapter, true)) {
8241 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8242 return -ENOMEM;
8243 }
8244
8245 if (netif_running(netdev))
8246 err = igb_open(netdev);
8247
8248 return err;
8249 }
8250 /* igb_main.c */
Linux kernel - Deliverables
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