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Merge branches 'pci/demodularize-hosts' and 'pci/host-request-windows' into next
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #include <linux/etherdevice.h>
54 #ifdef CONFIG_IGB_DCA
55 #include <linux/dca.h>
56 #endif
57 #include <linux/i2c.h>
58 #include "igb.h"
59
60 #define MAJ 5
61 #define MIN 3
62 #define BUILD 0
63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
64 __stringify(BUILD) "-k"
65 char igb_driver_name[] = "igb";
66 char igb_driver_version[] = DRV_VERSION;
67 static const char igb_driver_string[] =
68 "Intel(R) Gigabit Ethernet Network Driver";
69 static const char igb_copyright[] =
70 "Copyright (c) 2007-2014 Intel Corporation.";
71
72 static const struct e1000_info *igb_info_tbl[] = {
73 [board_82575] = &e1000_82575_info,
74 };
75
76 static const struct pci_device_id igb_pci_tbl[] = {
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
112 /* required last entry */
113 {0, }
114 };
115
116 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
117
118 static int igb_setup_all_tx_resources(struct igb_adapter *);
119 static int igb_setup_all_rx_resources(struct igb_adapter *);
120 static void igb_free_all_tx_resources(struct igb_adapter *);
121 static void igb_free_all_rx_resources(struct igb_adapter *);
122 static void igb_setup_mrqc(struct igb_adapter *);
123 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
124 static void igb_remove(struct pci_dev *pdev);
125 static int igb_sw_init(struct igb_adapter *);
126 int igb_open(struct net_device *);
127 int igb_close(struct net_device *);
128 static void igb_configure(struct igb_adapter *);
129 static void igb_configure_tx(struct igb_adapter *);
130 static void igb_configure_rx(struct igb_adapter *);
131 static void igb_clean_all_tx_rings(struct igb_adapter *);
132 static void igb_clean_all_rx_rings(struct igb_adapter *);
133 static void igb_clean_tx_ring(struct igb_ring *);
134 static void igb_clean_rx_ring(struct igb_ring *);
135 static void igb_set_rx_mode(struct net_device *);
136 static void igb_update_phy_info(unsigned long);
137 static void igb_watchdog(unsigned long);
138 static void igb_watchdog_task(struct work_struct *);
139 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
140 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
141 struct rtnl_link_stats64 *stats);
142 static int igb_change_mtu(struct net_device *, int);
143 static int igb_set_mac(struct net_device *, void *);
144 static void igb_set_uta(struct igb_adapter *adapter, bool set);
145 static irqreturn_t igb_intr(int irq, void *);
146 static irqreturn_t igb_intr_msi(int irq, void *);
147 static irqreturn_t igb_msix_other(int irq, void *);
148 static irqreturn_t igb_msix_ring(int irq, void *);
149 #ifdef CONFIG_IGB_DCA
150 static void igb_update_dca(struct igb_q_vector *);
151 static void igb_setup_dca(struct igb_adapter *);
152 #endif /* CONFIG_IGB_DCA */
153 static int igb_poll(struct napi_struct *, int);
154 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
155 static int igb_clean_rx_irq(struct igb_q_vector *, int);
156 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
157 static void igb_tx_timeout(struct net_device *);
158 static void igb_reset_task(struct work_struct *);
159 static void igb_vlan_mode(struct net_device *netdev,
160 netdev_features_t features);
161 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
162 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
163 static void igb_restore_vlan(struct igb_adapter *);
164 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
165 static void igb_ping_all_vfs(struct igb_adapter *);
166 static void igb_msg_task(struct igb_adapter *);
167 static void igb_vmm_control(struct igb_adapter *);
168 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
169 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
170 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
171 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
172 int vf, u16 vlan, u8 qos);
173 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
174 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
175 bool setting);
176 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
177 struct ifla_vf_info *ivi);
178 static void igb_check_vf_rate_limit(struct igb_adapter *);
179
180 #ifdef CONFIG_PCI_IOV
181 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
182 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
183 static int igb_disable_sriov(struct pci_dev *dev);
184 static int igb_pci_disable_sriov(struct pci_dev *dev);
185 #endif
186
187 #ifdef CONFIG_PM
188 #ifdef CONFIG_PM_SLEEP
189 static int igb_suspend(struct device *);
190 #endif
191 static int igb_resume(struct device *);
192 static int igb_runtime_suspend(struct device *dev);
193 static int igb_runtime_resume(struct device *dev);
194 static int igb_runtime_idle(struct device *dev);
195 static const struct dev_pm_ops igb_pm_ops = {
196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
198 igb_runtime_idle)
199 };
200 #endif
201 static void igb_shutdown(struct pci_dev *);
202 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
203 #ifdef CONFIG_IGB_DCA
204 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
205 static struct notifier_block dca_notifier = {
206 .notifier_call = igb_notify_dca,
207 .next = NULL,
208 .priority = 0
209 };
210 #endif
211 #ifdef CONFIG_NET_POLL_CONTROLLER
212 /* for netdump / net console */
213 static void igb_netpoll(struct net_device *);
214 #endif
215 #ifdef CONFIG_PCI_IOV
216 static unsigned int max_vfs;
217 module_param(max_vfs, uint, 0);
218 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
219 #endif /* CONFIG_PCI_IOV */
220
221 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
222 pci_channel_state_t);
223 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
224 static void igb_io_resume(struct pci_dev *);
225
226 static const struct pci_error_handlers igb_err_handler = {
227 .error_detected = igb_io_error_detected,
228 .slot_reset = igb_io_slot_reset,
229 .resume = igb_io_resume,
230 };
231
232 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
233
234 static struct pci_driver igb_driver = {
235 .name = igb_driver_name,
236 .id_table = igb_pci_tbl,
237 .probe = igb_probe,
238 .remove = igb_remove,
239 #ifdef CONFIG_PM
240 .driver.pm = &igb_pm_ops,
241 #endif
242 .shutdown = igb_shutdown,
243 .sriov_configure = igb_pci_sriov_configure,
244 .err_handler = &igb_err_handler
245 };
246
247 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
248 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
249 MODULE_LICENSE("GPL");
250 MODULE_VERSION(DRV_VERSION);
251
252 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
253 static int debug = -1;
254 module_param(debug, int, 0);
255 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
256
257 struct igb_reg_info {
258 u32 ofs;
259 char *name;
260 };
261
262 static const struct igb_reg_info igb_reg_info_tbl[] = {
263
264 /* General Registers */
265 {E1000_CTRL, "CTRL"},
266 {E1000_STATUS, "STATUS"},
267 {E1000_CTRL_EXT, "CTRL_EXT"},
268
269 /* Interrupt Registers */
270 {E1000_ICR, "ICR"},
271
272 /* RX Registers */
273 {E1000_RCTL, "RCTL"},
274 {E1000_RDLEN(0), "RDLEN"},
275 {E1000_RDH(0), "RDH"},
276 {E1000_RDT(0), "RDT"},
277 {E1000_RXDCTL(0), "RXDCTL"},
278 {E1000_RDBAL(0), "RDBAL"},
279 {E1000_RDBAH(0), "RDBAH"},
280
281 /* TX Registers */
282 {E1000_TCTL, "TCTL"},
283 {E1000_TDBAL(0), "TDBAL"},
284 {E1000_TDBAH(0), "TDBAH"},
285 {E1000_TDLEN(0), "TDLEN"},
286 {E1000_TDH(0), "TDH"},
287 {E1000_TDT(0), "TDT"},
288 {E1000_TXDCTL(0), "TXDCTL"},
289 {E1000_TDFH, "TDFH"},
290 {E1000_TDFT, "TDFT"},
291 {E1000_TDFHS, "TDFHS"},
292 {E1000_TDFPC, "TDFPC"},
293
294 /* List Terminator */
295 {}
296 };
297
298 /* igb_regdump - register printout routine */
299 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
300 {
301 int n = 0;
302 char rname[16];
303 u32 regs[8];
304
305 switch (reginfo->ofs) {
306 case E1000_RDLEN(0):
307 for (n = 0; n < 4; n++)
308 regs[n] = rd32(E1000_RDLEN(n));
309 break;
310 case E1000_RDH(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDH(n));
313 break;
314 case E1000_RDT(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDT(n));
317 break;
318 case E1000_RXDCTL(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RXDCTL(n));
321 break;
322 case E1000_RDBAL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RDBAL(n));
325 break;
326 case E1000_RDBAH(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAH(n));
329 break;
330 case E1000_TDBAL(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAL(n));
333 break;
334 case E1000_TDBAH(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_TDBAH(n));
337 break;
338 case E1000_TDLEN(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDLEN(n));
341 break;
342 case E1000_TDH(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDH(n));
345 break;
346 case E1000_TDT(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDT(n));
349 break;
350 case E1000_TXDCTL(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TXDCTL(n));
353 break;
354 default:
355 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
356 return;
357 }
358
359 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
360 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
361 regs[2], regs[3]);
362 }
363
364 /* igb_dump - Print registers, Tx-rings and Rx-rings */
365 static void igb_dump(struct igb_adapter *adapter)
366 {
367 struct net_device *netdev = adapter->netdev;
368 struct e1000_hw *hw = &adapter->hw;
369 struct igb_reg_info *reginfo;
370 struct igb_ring *tx_ring;
371 union e1000_adv_tx_desc *tx_desc;
372 struct my_u0 { u64 a; u64 b; } *u0;
373 struct igb_ring *rx_ring;
374 union e1000_adv_rx_desc *rx_desc;
375 u32 staterr;
376 u16 i, n;
377
378 if (!netif_msg_hw(adapter))
379 return;
380
381 /* Print netdevice Info */
382 if (netdev) {
383 dev_info(&adapter->pdev->dev, "Net device Info\n");
384 pr_info("Device Name state trans_start last_rx\n");
385 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
386 netdev->state, dev_trans_start(netdev), netdev->last_rx);
387 }
388
389 /* Print Registers */
390 dev_info(&adapter->pdev->dev, "Register Dump\n");
391 pr_info(" Register Name Value\n");
392 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
393 reginfo->name; reginfo++) {
394 igb_regdump(hw, reginfo);
395 }
396
397 /* Print TX Ring Summary */
398 if (!netdev || !netif_running(netdev))
399 goto exit;
400
401 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
402 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
403 for (n = 0; n < adapter->num_tx_queues; n++) {
404 struct igb_tx_buffer *buffer_info;
405 tx_ring = adapter->tx_ring[n];
406 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
407 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
408 n, tx_ring->next_to_use, tx_ring->next_to_clean,
409 (u64)dma_unmap_addr(buffer_info, dma),
410 dma_unmap_len(buffer_info, len),
411 buffer_info->next_to_watch,
412 (u64)buffer_info->time_stamp);
413 }
414
415 /* Print TX Rings */
416 if (!netif_msg_tx_done(adapter))
417 goto rx_ring_summary;
418
419 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
420
421 /* Transmit Descriptor Formats
422 *
423 * Advanced Transmit Descriptor
424 * +--------------------------------------------------------------+
425 * 0 | Buffer Address [63:0] |
426 * +--------------------------------------------------------------+
427 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
428 * +--------------------------------------------------------------+
429 * 63 46 45 40 39 38 36 35 32 31 24 15 0
430 */
431
432 for (n = 0; n < adapter->num_tx_queues; n++) {
433 tx_ring = adapter->tx_ring[n];
434 pr_info("------------------------------------\n");
435 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
436 pr_info("------------------------------------\n");
437 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
440 const char *next_desc;
441 struct igb_tx_buffer *buffer_info;
442 tx_desc = IGB_TX_DESC(tx_ring, i);
443 buffer_info = &tx_ring->tx_buffer_info[i];
444 u0 = (struct my_u0 *)tx_desc;
445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
455 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
456 i, le64_to_cpu(u0->a),
457 le64_to_cpu(u0->b),
458 (u64)dma_unmap_addr(buffer_info, dma),
459 dma_unmap_len(buffer_info, len),
460 buffer_info->next_to_watch,
461 (u64)buffer_info->time_stamp,
462 buffer_info->skb, next_desc);
463
464 if (netif_msg_pktdata(adapter) && buffer_info->skb)
465 print_hex_dump(KERN_INFO, "",
466 DUMP_PREFIX_ADDRESS,
467 16, 1, buffer_info->skb->data,
468 dma_unmap_len(buffer_info, len),
469 true);
470 }
471 }
472
473 /* Print RX Rings Summary */
474 rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
476 pr_info("Queue [NTU] [NTC]\n");
477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
516 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
517
518 for (i = 0; i < rx_ring->count; i++) {
519 const char *next_desc;
520 struct igb_rx_buffer *buffer_info;
521 buffer_info = &rx_ring->rx_buffer_info[i];
522 rx_desc = IGB_RX_DESC(rx_ring, i);
523 u0 = (struct my_u0 *)rx_desc;
524 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
525
526 if (i == rx_ring->next_to_use)
527 next_desc = " NTU";
528 else if (i == rx_ring->next_to_clean)
529 next_desc = " NTC";
530 else
531 next_desc = "";
532
533 if (staterr & E1000_RXD_STAT_DD) {
534 /* Descriptor Done */
535 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
536 "RWB", i,
537 le64_to_cpu(u0->a),
538 le64_to_cpu(u0->b),
539 next_desc);
540 } else {
541 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
542 "R ", i,
543 le64_to_cpu(u0->a),
544 le64_to_cpu(u0->b),
545 (u64)buffer_info->dma,
546 next_desc);
547
548 if (netif_msg_pktdata(adapter) &&
549 buffer_info->dma && buffer_info->page) {
550 print_hex_dump(KERN_INFO, "",
551 DUMP_PREFIX_ADDRESS,
552 16, 1,
553 page_address(buffer_info->page) +
554 buffer_info->page_offset,
555 IGB_RX_BUFSZ, true);
556 }
557 }
558 }
559 }
560
561 exit:
562 return;
563 }
564
565 /**
566 * igb_get_i2c_data - Reads the I2C SDA data bit
567 * @hw: pointer to hardware structure
568 * @i2cctl: Current value of I2CCTL register
569 *
570 * Returns the I2C data bit value
571 **/
572 static int igb_get_i2c_data(void *data)
573 {
574 struct igb_adapter *adapter = (struct igb_adapter *)data;
575 struct e1000_hw *hw = &adapter->hw;
576 s32 i2cctl = rd32(E1000_I2CPARAMS);
577
578 return !!(i2cctl & E1000_I2C_DATA_IN);
579 }
580
581 /**
582 * igb_set_i2c_data - Sets the I2C data bit
583 * @data: pointer to hardware structure
584 * @state: I2C data value (0 or 1) to set
585 *
586 * Sets the I2C data bit
587 **/
588 static void igb_set_i2c_data(void *data, int state)
589 {
590 struct igb_adapter *adapter = (struct igb_adapter *)data;
591 struct e1000_hw *hw = &adapter->hw;
592 s32 i2cctl = rd32(E1000_I2CPARAMS);
593
594 if (state)
595 i2cctl |= E1000_I2C_DATA_OUT;
596 else
597 i2cctl &= ~E1000_I2C_DATA_OUT;
598
599 i2cctl &= ~E1000_I2C_DATA_OE_N;
600 i2cctl |= E1000_I2C_CLK_OE_N;
601 wr32(E1000_I2CPARAMS, i2cctl);
602 wrfl();
603
604 }
605
606 /**
607 * igb_set_i2c_clk - Sets the I2C SCL clock
608 * @data: pointer to hardware structure
609 * @state: state to set clock
610 *
611 * Sets the I2C clock line to state
612 **/
613 static void igb_set_i2c_clk(void *data, int state)
614 {
615 struct igb_adapter *adapter = (struct igb_adapter *)data;
616 struct e1000_hw *hw = &adapter->hw;
617 s32 i2cctl = rd32(E1000_I2CPARAMS);
618
619 if (state) {
620 i2cctl |= E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 } else {
623 i2cctl &= ~E1000_I2C_CLK_OUT;
624 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 }
626 wr32(E1000_I2CPARAMS, i2cctl);
627 wrfl();
628 }
629
630 /**
631 * igb_get_i2c_clk - Gets the I2C SCL clock state
632 * @data: pointer to hardware structure
633 *
634 * Gets the I2C clock state
635 **/
636 static int igb_get_i2c_clk(void *data)
637 {
638 struct igb_adapter *adapter = (struct igb_adapter *)data;
639 struct e1000_hw *hw = &adapter->hw;
640 s32 i2cctl = rd32(E1000_I2CPARAMS);
641
642 return !!(i2cctl & E1000_I2C_CLK_IN);
643 }
644
645 static const struct i2c_algo_bit_data igb_i2c_algo = {
646 .setsda = igb_set_i2c_data,
647 .setscl = igb_set_i2c_clk,
648 .getsda = igb_get_i2c_data,
649 .getscl = igb_get_i2c_clk,
650 .udelay = 5,
651 .timeout = 20,
652 };
653
654 /**
655 * igb_get_hw_dev - return device
656 * @hw: pointer to hardware structure
657 *
658 * used by hardware layer to print debugging information
659 **/
660 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
661 {
662 struct igb_adapter *adapter = hw->back;
663 return adapter->netdev;
664 }
665
666 /**
667 * igb_init_module - Driver Registration Routine
668 *
669 * igb_init_module is the first routine called when the driver is
670 * loaded. All it does is register with the PCI subsystem.
671 **/
672 static int __init igb_init_module(void)
673 {
674 int ret;
675
676 pr_info("%s - version %s\n",
677 igb_driver_string, igb_driver_version);
678 pr_info("%s\n", igb_copyright);
679
680 #ifdef CONFIG_IGB_DCA
681 dca_register_notify(&dca_notifier);
682 #endif
683 ret = pci_register_driver(&igb_driver);
684 return ret;
685 }
686
687 module_init(igb_init_module);
688
689 /**
690 * igb_exit_module - Driver Exit Cleanup Routine
691 *
692 * igb_exit_module is called just before the driver is removed
693 * from memory.
694 **/
695 static void __exit igb_exit_module(void)
696 {
697 #ifdef CONFIG_IGB_DCA
698 dca_unregister_notify(&dca_notifier);
699 #endif
700 pci_unregister_driver(&igb_driver);
701 }
702
703 module_exit(igb_exit_module);
704
705 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706 /**
707 * igb_cache_ring_register - Descriptor ring to register mapping
708 * @adapter: board private structure to initialize
709 *
710 * Once we know the feature-set enabled for the device, we'll cache
711 * the register offset the descriptor ring is assigned to.
712 **/
713 static void igb_cache_ring_register(struct igb_adapter *adapter)
714 {
715 int i = 0, j = 0;
716 u32 rbase_offset = adapter->vfs_allocated_count;
717
718 switch (adapter->hw.mac.type) {
719 case e1000_82576:
720 /* The queues are allocated for virtualization such that VF 0
721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
722 * In order to avoid collision we start at the first free queue
723 * and continue consuming queues in the same sequence
724 */
725 if (adapter->vfs_allocated_count) {
726 for (; i < adapter->rss_queues; i++)
727 adapter->rx_ring[i]->reg_idx = rbase_offset +
728 Q_IDX_82576(i);
729 }
730 /* Fall through */
731 case e1000_82575:
732 case e1000_82580:
733 case e1000_i350:
734 case e1000_i354:
735 case e1000_i210:
736 case e1000_i211:
737 /* Fall through */
738 default:
739 for (; i < adapter->num_rx_queues; i++)
740 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
741 for (; j < adapter->num_tx_queues; j++)
742 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
743 break;
744 }
745 }
746
747 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
748 {
749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
751 u32 value = 0;
752
753 if (E1000_REMOVED(hw_addr))
754 return ~value;
755
756 value = readl(&hw_addr[reg]);
757
758 /* reads should not return all F's */
759 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
760 struct net_device *netdev = igb->netdev;
761 hw->hw_addr = NULL;
762 netif_device_detach(netdev);
763 netdev_err(netdev, "PCIe link lost, device now detached\n");
764 }
765
766 return value;
767 }
768
769 /**
770 * igb_write_ivar - configure ivar for given MSI-X vector
771 * @hw: pointer to the HW structure
772 * @msix_vector: vector number we are allocating to a given ring
773 * @index: row index of IVAR register to write within IVAR table
774 * @offset: column offset of in IVAR, should be multiple of 8
775 *
776 * This function is intended to handle the writing of the IVAR register
777 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
778 * each containing an cause allocation for an Rx and Tx ring, and a
779 * variable number of rows depending on the number of queues supported.
780 **/
781 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
782 int index, int offset)
783 {
784 u32 ivar = array_rd32(E1000_IVAR0, index);
785
786 /* clear any bits that are currently set */
787 ivar &= ~((u32)0xFF << offset);
788
789 /* write vector and valid bit */
790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
791
792 array_wr32(E1000_IVAR0, index, ivar);
793 }
794
795 #define IGB_N0_QUEUE -1
796 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
797 {
798 struct igb_adapter *adapter = q_vector->adapter;
799 struct e1000_hw *hw = &adapter->hw;
800 int rx_queue = IGB_N0_QUEUE;
801 int tx_queue = IGB_N0_QUEUE;
802 u32 msixbm = 0;
803
804 if (q_vector->rx.ring)
805 rx_queue = q_vector->rx.ring->reg_idx;
806 if (q_vector->tx.ring)
807 tx_queue = q_vector->tx.ring->reg_idx;
808
809 switch (hw->mac.type) {
810 case e1000_82575:
811 /* The 82575 assigns vectors using a bitmask, which matches the
812 * bitmask for the EICR/EIMS/EIMC registers. To assign one
813 * or more queues to a vector, we write the appropriate bits
814 * into the MSIXBM register for that vector.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
818 if (tx_queue > IGB_N0_QUEUE)
819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
821 msixbm |= E1000_EIMS_OTHER;
822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
823 q_vector->eims_value = msixbm;
824 break;
825 case e1000_82576:
826 /* 82576 uses a table that essentially consists of 2 columns
827 * with 8 rows. The ordering is column-major so we use the
828 * lower 3 bits as the row index, and the 4th bit as the
829 * column offset.
830 */
831 if (rx_queue > IGB_N0_QUEUE)
832 igb_write_ivar(hw, msix_vector,
833 rx_queue & 0x7,
834 (rx_queue & 0x8) << 1);
835 if (tx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 tx_queue & 0x7,
838 ((tx_queue & 0x8) << 1) + 8);
839 q_vector->eims_value = BIT(msix_vector);
840 break;
841 case e1000_82580:
842 case e1000_i350:
843 case e1000_i354:
844 case e1000_i210:
845 case e1000_i211:
846 /* On 82580 and newer adapters the scheme is similar to 82576
847 * however instead of ordering column-major we have things
848 * ordered row-major. So we traverse the table by using
849 * bit 0 as the column offset, and the remaining bits as the
850 * row index.
851 */
852 if (rx_queue > IGB_N0_QUEUE)
853 igb_write_ivar(hw, msix_vector,
854 rx_queue >> 1,
855 (rx_queue & 0x1) << 4);
856 if (tx_queue > IGB_N0_QUEUE)
857 igb_write_ivar(hw, msix_vector,
858 tx_queue >> 1,
859 ((tx_queue & 0x1) << 4) + 8);
860 q_vector->eims_value = BIT(msix_vector);
861 break;
862 default:
863 BUG();
864 break;
865 }
866
867 /* add q_vector eims value to global eims_enable_mask */
868 adapter->eims_enable_mask |= q_vector->eims_value;
869
870 /* configure q_vector to set itr on first interrupt */
871 q_vector->set_itr = 1;
872 }
873
874 /**
875 * igb_configure_msix - Configure MSI-X hardware
876 * @adapter: board private structure to initialize
877 *
878 * igb_configure_msix sets up the hardware to properly
879 * generate MSI-X interrupts.
880 **/
881 static void igb_configure_msix(struct igb_adapter *adapter)
882 {
883 u32 tmp;
884 int i, vector = 0;
885 struct e1000_hw *hw = &adapter->hw;
886
887 adapter->eims_enable_mask = 0;
888
889 /* set vector for other causes, i.e. link changes */
890 switch (hw->mac.type) {
891 case e1000_82575:
892 tmp = rd32(E1000_CTRL_EXT);
893 /* enable MSI-X PBA support*/
894 tmp |= E1000_CTRL_EXT_PBA_CLR;
895
896 /* Auto-Mask interrupts upon ICR read. */
897 tmp |= E1000_CTRL_EXT_EIAME;
898 tmp |= E1000_CTRL_EXT_IRCA;
899
900 wr32(E1000_CTRL_EXT, tmp);
901
902 /* enable msix_other interrupt */
903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
904 adapter->eims_other = E1000_EIMS_OTHER;
905
906 break;
907
908 case e1000_82576:
909 case e1000_82580:
910 case e1000_i350:
911 case e1000_i354:
912 case e1000_i210:
913 case e1000_i211:
914 /* Turn on MSI-X capability first, or our settings
915 * won't stick. And it will take days to debug.
916 */
917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
918 E1000_GPIE_PBA | E1000_GPIE_EIAME |
919 E1000_GPIE_NSICR);
920
921 /* enable msix_other interrupt */
922 adapter->eims_other = BIT(vector);
923 tmp = (vector++ | E1000_IVAR_VALID) << 8;
924
925 wr32(E1000_IVAR_MISC, tmp);
926 break;
927 default:
928 /* do nothing, since nothing else supports MSI-X */
929 break;
930 } /* switch (hw->mac.type) */
931
932 adapter->eims_enable_mask |= adapter->eims_other;
933
934 for (i = 0; i < adapter->num_q_vectors; i++)
935 igb_assign_vector(adapter->q_vector[i], vector++);
936
937 wrfl();
938 }
939
940 /**
941 * igb_request_msix - Initialize MSI-X interrupts
942 * @adapter: board private structure to initialize
943 *
944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
945 * kernel.
946 **/
947 static int igb_request_msix(struct igb_adapter *adapter)
948 {
949 struct net_device *netdev = adapter->netdev;
950 int i, err = 0, vector = 0, free_vector = 0;
951
952 err = request_irq(adapter->msix_entries[vector].vector,
953 igb_msix_other, 0, netdev->name, adapter);
954 if (err)
955 goto err_out;
956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
960 vector++;
961
962 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
963
964 if (q_vector->rx.ring && q_vector->tx.ring)
965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
972 q_vector->rx.ring->queue_index);
973 else
974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
976 err = request_irq(adapter->msix_entries[vector].vector,
977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
979 if (err)
980 goto err_free;
981 }
982
983 igb_configure_msix(adapter);
984 return 0;
985
986 err_free:
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995 err_out:
996 return err;
997 }
998
999 /**
1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
1003 *
1004 * This function frees the memory allocated to the q_vector.
1005 **/
1006 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007 {
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
1010 adapter->q_vector[v_idx] = NULL;
1011
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
1015 if (q_vector)
1016 kfree_rcu(q_vector, rcu);
1017 }
1018
1019 /**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028 {
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1042
1043 netif_napi_del(&q_vector->napi);
1044
1045 }
1046
1047 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048 {
1049 int v_idx = adapter->num_q_vectors;
1050
1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1052 pci_disable_msix(adapter->pdev);
1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1054 pci_disable_msi(adapter->pdev);
1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
1058 }
1059
1060 /**
1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
1063 *
1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
1067 **/
1068 static void igb_free_q_vectors(struct igb_adapter *adapter)
1069 {
1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
1074 adapter->num_q_vectors = 0;
1075
1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
1078 igb_free_q_vector(adapter, v_idx);
1079 }
1080 }
1081
1082 /**
1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
1085 *
1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
1088 */
1089 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090 {
1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093 }
1094
1095 /**
1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
1099 *
1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
1102 **/
1103 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1104 {
1105 int err;
1106 int numvecs, i;
1107
1108 if (!msix)
1109 goto msi_only;
1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
1111
1112 /* Number of supported queues. */
1113 adapter->num_rx_queues = adapter->rss_queues;
1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
1118
1119 /* start with one vector for every Rx queue */
1120 numvecs = adapter->num_rx_queues;
1121
1122 /* if Tx handler is separate add 1 for every Tx queue */
1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
1139 return;
1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144 msi_only:
1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1146 #ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1157 wrfl();
1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161 #endif
1162 adapter->vfs_allocated_count = 0;
1163 adapter->rss_queues = 1;
1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1165 adapter->num_rx_queues = 1;
1166 adapter->num_tx_queues = 1;
1167 adapter->num_q_vectors = 1;
1168 if (!pci_enable_msi(adapter->pdev))
1169 adapter->flags |= IGB_FLAG_HAS_MSI;
1170 }
1171
1172 static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174 {
1175 head->ring = ring;
1176 head->count++;
1177 }
1178
1179 /**
1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
1188 *
1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1190 **/
1191 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
1195 {
1196 struct igb_q_vector *q_vector;
1197 struct igb_ring *ring;
1198 int ring_count, size;
1199
1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
1209 q_vector = adapter->q_vector[v_idx];
1210 if (!q_vector) {
1211 q_vector = kzalloc(size, GFP_KERNEL);
1212 } else if (size > ksize(q_vector)) {
1213 kfree_rcu(q_vector, rcu);
1214 q_vector = kzalloc(size, GFP_KERNEL);
1215 } else {
1216 memset(q_vector, 0, size);
1217 }
1218 if (!q_vector)
1219 return -ENOMEM;
1220
1221 /* initialize NAPI */
1222 netif_napi_add(adapter->netdev, &q_vector->napi,
1223 igb_poll, 64);
1224
1225 /* tie q_vector and adapter together */
1226 adapter->q_vector[v_idx] = q_vector;
1227 q_vector->adapter = adapter;
1228
1229 /* initialize work limits */
1230 q_vector->tx.work_limit = adapter->tx_work_limit;
1231
1232 /* initialize ITR configuration */
1233 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1234 q_vector->itr_val = IGB_START_ITR;
1235
1236 /* initialize pointer to rings */
1237 ring = q_vector->ring;
1238
1239 /* intialize ITR */
1240 if (rxr_count) {
1241 /* rx or rx/tx vector */
1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 q_vector->itr_val = adapter->rx_itr_setting;
1244 } else {
1245 /* tx only vector */
1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 q_vector->itr_val = adapter->tx_itr_setting;
1248 }
1249
1250 if (txr_count) {
1251 /* assign generic ring traits */
1252 ring->dev = &adapter->pdev->dev;
1253 ring->netdev = adapter->netdev;
1254
1255 /* configure backlink on ring */
1256 ring->q_vector = q_vector;
1257
1258 /* update q_vector Tx values */
1259 igb_add_ring(ring, &q_vector->tx);
1260
1261 /* For 82575, context index must be unique per ring. */
1262 if (adapter->hw.mac.type == e1000_82575)
1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1264
1265 /* apply Tx specific ring traits */
1266 ring->count = adapter->tx_ring_count;
1267 ring->queue_index = txr_idx;
1268
1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1271
1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1274
1275 /* push pointer to next ring */
1276 ring++;
1277 }
1278
1279 if (rxr_count) {
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
1283
1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
1286
1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
1289
1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1293
1294 /* On i350, i354, i210, and i211, loopback VLAN packets
1295 * have the tag byte-swapped.
1296 */
1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1299
1300 /* apply Rx specific ring traits */
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1303
1304 u64_stats_init(&ring->rx_syncp);
1305
1306 /* assign ring to adapter */
1307 adapter->rx_ring[rxr_idx] = ring;
1308 }
1309
1310 return 0;
1311 }
1312
1313
1314 /**
1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316 * @adapter: board private structure to initialize
1317 *
1318 * We allocate one q_vector per queue interrupt. If allocation fails we
1319 * return -ENOMEM.
1320 **/
1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1322 {
1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327 int err;
1328
1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332 0, 0, 1, rxr_idx);
1333
1334 if (err)
1335 goto err_out;
1336
1337 /* update counts and index */
1338 rxr_remaining--;
1339 rxr_idx++;
1340 }
1341 }
1342
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1346
1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1349
1350 if (err)
1351 goto err_out;
1352
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1356 rxr_idx++;
1357 txr_idx++;
1358 }
1359
1360 return 0;
1361
1362 err_out:
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1366
1367 while (v_idx--)
1368 igb_free_q_vector(adapter, v_idx);
1369
1370 return -ENOMEM;
1371 }
1372
1373 /**
1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
1377 *
1378 * This function initializes the interrupts and allocates all of the queues.
1379 **/
1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1381 {
1382 struct pci_dev *pdev = adapter->pdev;
1383 int err;
1384
1385 igb_set_interrupt_capability(adapter, msix);
1386
1387 err = igb_alloc_q_vectors(adapter);
1388 if (err) {
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1391 }
1392
1393 igb_cache_ring_register(adapter);
1394
1395 return 0;
1396
1397 err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1399 return err;
1400 }
1401
1402 /**
1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
1405 *
1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
1408 **/
1409 static int igb_request_irq(struct igb_adapter *adapter)
1410 {
1411 struct net_device *netdev = adapter->netdev;
1412 struct pci_dev *pdev = adapter->pdev;
1413 int err = 0;
1414
1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416 err = igb_request_msix(adapter);
1417 if (!err)
1418 goto request_done;
1419 /* fall back to MSI */
1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
1422
1423 igb_clear_interrupt_scheme(adapter);
1424 err = igb_init_interrupt_scheme(adapter, false);
1425 if (err)
1426 goto request_done;
1427
1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
1430 igb_configure(adapter);
1431 }
1432
1433 igb_assign_vector(adapter->q_vector[0], 0);
1434
1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
1437 netdev->name, adapter);
1438 if (!err)
1439 goto request_done;
1440
1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1444 }
1445
1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447 netdev->name, adapter);
1448
1449 if (err)
1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1451 err);
1452
1453 request_done:
1454 return err;
1455 }
1456
1457 static void igb_free_irq(struct igb_adapter *adapter)
1458 {
1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1460 int vector = 0, i;
1461
1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
1463
1464 for (i = 0; i < adapter->num_q_vectors; i++)
1465 free_irq(adapter->msix_entries[vector++].vector,
1466 adapter->q_vector[i]);
1467 } else {
1468 free_irq(adapter->pdev->irq, adapter);
1469 }
1470 }
1471
1472 /**
1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
1475 **/
1476 static void igb_irq_disable(struct igb_adapter *adapter)
1477 {
1478 struct e1000_hw *hw = &adapter->hw;
1479
1480 /* we need to be careful when disabling interrupts. The VFs are also
1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1483 */
1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485 u32 regval = rd32(E1000_EIAM);
1486
1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1491 }
1492
1493 wr32(E1000_IAM, 0);
1494 wr32(E1000_IMC, ~0);
1495 wrfl();
1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1497 int i;
1498
1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1501 } else {
1502 synchronize_irq(adapter->pdev->irq);
1503 }
1504 }
1505
1506 /**
1507 * igb_irq_enable - Enable default interrupt generation settings
1508 * @adapter: board private structure
1509 **/
1510 static void igb_irq_enable(struct igb_adapter *adapter)
1511 {
1512 struct e1000_hw *hw = &adapter->hw;
1513
1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516 u32 regval = rd32(E1000_EIAC);
1517
1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
1522 if (adapter->vfs_allocated_count) {
1523 wr32(E1000_MBVFIMR, 0xFF);
1524 ims |= E1000_IMS_VMMB;
1525 }
1526 wr32(E1000_IMS, ims);
1527 } else {
1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529 E1000_IMS_DRSTA);
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531 E1000_IMS_DRSTA);
1532 }
1533 }
1534
1535 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536 {
1537 struct e1000_hw *hw = &adapter->hw;
1538 u16 pf_id = adapter->vfs_allocated_count;
1539 u16 vid = adapter->hw.mng_cookie.vlan_id;
1540 u16 old_vid = adapter->mng_vlan_id;
1541
1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1543 /* add VID to filter table */
1544 igb_vfta_set(hw, vid, pf_id, true, true);
1545 adapter->mng_vlan_id = vid;
1546 } else {
1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1548 }
1549
1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1551 (vid != old_vid) &&
1552 !test_bit(old_vid, adapter->active_vlans)) {
1553 /* remove VID from filter table */
1554 igb_vfta_set(hw, vid, pf_id, false, true);
1555 }
1556 }
1557
1558 /**
1559 * igb_release_hw_control - release control of the h/w to f/w
1560 * @adapter: address of board private structure
1561 *
1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1563 * For ASF and Pass Through versions of f/w this means that the
1564 * driver is no longer loaded.
1565 **/
1566 static void igb_release_hw_control(struct igb_adapter *adapter)
1567 {
1568 struct e1000_hw *hw = &adapter->hw;
1569 u32 ctrl_ext;
1570
1571 /* Let firmware take over control of h/w */
1572 ctrl_ext = rd32(E1000_CTRL_EXT);
1573 wr32(E1000_CTRL_EXT,
1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1575 }
1576
1577 /**
1578 * igb_get_hw_control - get control of the h/w from f/w
1579 * @adapter: address of board private structure
1580 *
1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1582 * For ASF and Pass Through versions of f/w this means that
1583 * the driver is loaded.
1584 **/
1585 static void igb_get_hw_control(struct igb_adapter *adapter)
1586 {
1587 struct e1000_hw *hw = &adapter->hw;
1588 u32 ctrl_ext;
1589
1590 /* Let firmware know the driver has taken over */
1591 ctrl_ext = rd32(E1000_CTRL_EXT);
1592 wr32(E1000_CTRL_EXT,
1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1594 }
1595
1596 /**
1597 * igb_configure - configure the hardware for RX and TX
1598 * @adapter: private board structure
1599 **/
1600 static void igb_configure(struct igb_adapter *adapter)
1601 {
1602 struct net_device *netdev = adapter->netdev;
1603 int i;
1604
1605 igb_get_hw_control(adapter);
1606 igb_set_rx_mode(netdev);
1607
1608 igb_restore_vlan(adapter);
1609
1610 igb_setup_tctl(adapter);
1611 igb_setup_mrqc(adapter);
1612 igb_setup_rctl(adapter);
1613
1614 igb_configure_tx(adapter);
1615 igb_configure_rx(adapter);
1616
1617 igb_rx_fifo_flush_82575(&adapter->hw);
1618
1619 /* call igb_desc_unused which always leaves
1620 * at least 1 descriptor unused to make sure
1621 * next_to_use != next_to_clean
1622 */
1623 for (i = 0; i < adapter->num_rx_queues; i++) {
1624 struct igb_ring *ring = adapter->rx_ring[i];
1625 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1626 }
1627 }
1628
1629 /**
1630 * igb_power_up_link - Power up the phy/serdes link
1631 * @adapter: address of board private structure
1632 **/
1633 void igb_power_up_link(struct igb_adapter *adapter)
1634 {
1635 igb_reset_phy(&adapter->hw);
1636
1637 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1638 igb_power_up_phy_copper(&adapter->hw);
1639 else
1640 igb_power_up_serdes_link_82575(&adapter->hw);
1641
1642 igb_setup_link(&adapter->hw);
1643 }
1644
1645 /**
1646 * igb_power_down_link - Power down the phy/serdes link
1647 * @adapter: address of board private structure
1648 */
1649 static void igb_power_down_link(struct igb_adapter *adapter)
1650 {
1651 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1652 igb_power_down_phy_copper_82575(&adapter->hw);
1653 else
1654 igb_shutdown_serdes_link_82575(&adapter->hw);
1655 }
1656
1657 /**
1658 * Detect and switch function for Media Auto Sense
1659 * @adapter: address of the board private structure
1660 **/
1661 static void igb_check_swap_media(struct igb_adapter *adapter)
1662 {
1663 struct e1000_hw *hw = &adapter->hw;
1664 u32 ctrl_ext, connsw;
1665 bool swap_now = false;
1666
1667 ctrl_ext = rd32(E1000_CTRL_EXT);
1668 connsw = rd32(E1000_CONNSW);
1669
1670 /* need to live swap if current media is copper and we have fiber/serdes
1671 * to go to.
1672 */
1673
1674 if ((hw->phy.media_type == e1000_media_type_copper) &&
1675 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1676 swap_now = true;
1677 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1678 /* copper signal takes time to appear */
1679 if (adapter->copper_tries < 4) {
1680 adapter->copper_tries++;
1681 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1682 wr32(E1000_CONNSW, connsw);
1683 return;
1684 } else {
1685 adapter->copper_tries = 0;
1686 if ((connsw & E1000_CONNSW_PHYSD) &&
1687 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1688 swap_now = true;
1689 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1690 wr32(E1000_CONNSW, connsw);
1691 }
1692 }
1693 }
1694
1695 if (!swap_now)
1696 return;
1697
1698 switch (hw->phy.media_type) {
1699 case e1000_media_type_copper:
1700 netdev_info(adapter->netdev,
1701 "MAS: changing media to fiber/serdes\n");
1702 ctrl_ext |=
1703 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1704 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1705 adapter->copper_tries = 0;
1706 break;
1707 case e1000_media_type_internal_serdes:
1708 case e1000_media_type_fiber:
1709 netdev_info(adapter->netdev,
1710 "MAS: changing media to copper\n");
1711 ctrl_ext &=
1712 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1713 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1714 break;
1715 default:
1716 /* shouldn't get here during regular operation */
1717 netdev_err(adapter->netdev,
1718 "AMS: Invalid media type found, returning\n");
1719 break;
1720 }
1721 wr32(E1000_CTRL_EXT, ctrl_ext);
1722 }
1723
1724 /**
1725 * igb_up - Open the interface and prepare it to handle traffic
1726 * @adapter: board private structure
1727 **/
1728 int igb_up(struct igb_adapter *adapter)
1729 {
1730 struct e1000_hw *hw = &adapter->hw;
1731 int i;
1732
1733 /* hardware has been reset, we need to reload some things */
1734 igb_configure(adapter);
1735
1736 clear_bit(__IGB_DOWN, &adapter->state);
1737
1738 for (i = 0; i < adapter->num_q_vectors; i++)
1739 napi_enable(&(adapter->q_vector[i]->napi));
1740
1741 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1742 igb_configure_msix(adapter);
1743 else
1744 igb_assign_vector(adapter->q_vector[0], 0);
1745
1746 /* Clear any pending interrupts. */
1747 rd32(E1000_ICR);
1748 igb_irq_enable(adapter);
1749
1750 /* notify VFs that reset has been completed */
1751 if (adapter->vfs_allocated_count) {
1752 u32 reg_data = rd32(E1000_CTRL_EXT);
1753
1754 reg_data |= E1000_CTRL_EXT_PFRSTD;
1755 wr32(E1000_CTRL_EXT, reg_data);
1756 }
1757
1758 netif_tx_start_all_queues(adapter->netdev);
1759
1760 /* start the watchdog. */
1761 hw->mac.get_link_status = 1;
1762 schedule_work(&adapter->watchdog_task);
1763
1764 if ((adapter->flags & IGB_FLAG_EEE) &&
1765 (!hw->dev_spec._82575.eee_disable))
1766 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1767
1768 return 0;
1769 }
1770
1771 void igb_down(struct igb_adapter *adapter)
1772 {
1773 struct net_device *netdev = adapter->netdev;
1774 struct e1000_hw *hw = &adapter->hw;
1775 u32 tctl, rctl;
1776 int i;
1777
1778 /* signal that we're down so the interrupt handler does not
1779 * reschedule our watchdog timer
1780 */
1781 set_bit(__IGB_DOWN, &adapter->state);
1782
1783 /* disable receives in the hardware */
1784 rctl = rd32(E1000_RCTL);
1785 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1786 /* flush and sleep below */
1787
1788 netif_carrier_off(netdev);
1789 netif_tx_stop_all_queues(netdev);
1790
1791 /* disable transmits in the hardware */
1792 tctl = rd32(E1000_TCTL);
1793 tctl &= ~E1000_TCTL_EN;
1794 wr32(E1000_TCTL, tctl);
1795 /* flush both disables and wait for them to finish */
1796 wrfl();
1797 usleep_range(10000, 11000);
1798
1799 igb_irq_disable(adapter);
1800
1801 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1802
1803 for (i = 0; i < adapter->num_q_vectors; i++) {
1804 if (adapter->q_vector[i]) {
1805 napi_synchronize(&adapter->q_vector[i]->napi);
1806 napi_disable(&adapter->q_vector[i]->napi);
1807 }
1808 }
1809
1810 del_timer_sync(&adapter->watchdog_timer);
1811 del_timer_sync(&adapter->phy_info_timer);
1812
1813 /* record the stats before reset*/
1814 spin_lock(&adapter->stats64_lock);
1815 igb_update_stats(adapter, &adapter->stats64);
1816 spin_unlock(&adapter->stats64_lock);
1817
1818 adapter->link_speed = 0;
1819 adapter->link_duplex = 0;
1820
1821 if (!pci_channel_offline(adapter->pdev))
1822 igb_reset(adapter);
1823
1824 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1825 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1826
1827 igb_clean_all_tx_rings(adapter);
1828 igb_clean_all_rx_rings(adapter);
1829 #ifdef CONFIG_IGB_DCA
1830
1831 /* since we reset the hardware DCA settings were cleared */
1832 igb_setup_dca(adapter);
1833 #endif
1834 }
1835
1836 void igb_reinit_locked(struct igb_adapter *adapter)
1837 {
1838 WARN_ON(in_interrupt());
1839 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1840 usleep_range(1000, 2000);
1841 igb_down(adapter);
1842 igb_up(adapter);
1843 clear_bit(__IGB_RESETTING, &adapter->state);
1844 }
1845
1846 /** igb_enable_mas - Media Autosense re-enable after swap
1847 *
1848 * @adapter: adapter struct
1849 **/
1850 static void igb_enable_mas(struct igb_adapter *adapter)
1851 {
1852 struct e1000_hw *hw = &adapter->hw;
1853 u32 connsw = rd32(E1000_CONNSW);
1854
1855 /* configure for SerDes media detect */
1856 if ((hw->phy.media_type == e1000_media_type_copper) &&
1857 (!(connsw & E1000_CONNSW_SERDESD))) {
1858 connsw |= E1000_CONNSW_ENRGSRC;
1859 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1860 wr32(E1000_CONNSW, connsw);
1861 wrfl();
1862 }
1863 }
1864
1865 void igb_reset(struct igb_adapter *adapter)
1866 {
1867 struct pci_dev *pdev = adapter->pdev;
1868 struct e1000_hw *hw = &adapter->hw;
1869 struct e1000_mac_info *mac = &hw->mac;
1870 struct e1000_fc_info *fc = &hw->fc;
1871 u32 pba, hwm;
1872
1873 /* Repartition Pba for greater than 9k mtu
1874 * To take effect CTRL.RST is required.
1875 */
1876 switch (mac->type) {
1877 case e1000_i350:
1878 case e1000_i354:
1879 case e1000_82580:
1880 pba = rd32(E1000_RXPBS);
1881 pba = igb_rxpbs_adjust_82580(pba);
1882 break;
1883 case e1000_82576:
1884 pba = rd32(E1000_RXPBS);
1885 pba &= E1000_RXPBS_SIZE_MASK_82576;
1886 break;
1887 case e1000_82575:
1888 case e1000_i210:
1889 case e1000_i211:
1890 default:
1891 pba = E1000_PBA_34K;
1892 break;
1893 }
1894
1895 if (mac->type == e1000_82575) {
1896 u32 min_rx_space, min_tx_space, needed_tx_space;
1897
1898 /* write Rx PBA so that hardware can report correct Tx PBA */
1899 wr32(E1000_PBA, pba);
1900
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
1906 * expressed in KB.
1907 */
1908 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1909
1910 /* The Tx FIFO also stores 16 bytes of information about the Tx
1911 * but don't include Ethernet FCS because hardware appends it.
1912 * We only need to round down to the nearest 512 byte block
1913 * count since the value we care about is 2 frames, not 1.
1914 */
1915 min_tx_space = adapter->max_frame_size;
1916 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1917 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1918
1919 /* upper 16 bits has Tx packet buffer allocation size in KB */
1920 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
1921
1922 /* If current Tx allocation is less than the min Tx FIFO size,
1923 * and the min Tx FIFO size is less than the current Rx FIFO
1924 * allocation, take space away from current Rx allocation.
1925 */
1926 if (needed_tx_space < pba) {
1927 pba -= needed_tx_space;
1928
1929 /* if short on Rx space, Rx wins and must trump Tx
1930 * adjustment
1931 */
1932 if (pba < min_rx_space)
1933 pba = min_rx_space;
1934 }
1935
1936 /* adjust PBA for jumbo frames */
1937 wr32(E1000_PBA, pba);
1938 }
1939
1940 /* flow control settings
1941 * The high water mark must be low enough to fit one full frame
1942 * after transmitting the pause frame. As such we must have enough
1943 * space to allow for us to complete our current transmit and then
1944 * receive the frame that is in progress from the link partner.
1945 * Set it to:
1946 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
1947 */
1948 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
1949
1950 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1951 fc->low_water = fc->high_water - 16;
1952 fc->pause_time = 0xFFFF;
1953 fc->send_xon = 1;
1954 fc->current_mode = fc->requested_mode;
1955
1956 /* disable receive for all VFs and wait one second */
1957 if (adapter->vfs_allocated_count) {
1958 int i;
1959
1960 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1961 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1962
1963 /* ping all the active vfs to let them know we are going down */
1964 igb_ping_all_vfs(adapter);
1965
1966 /* disable transmits and receives */
1967 wr32(E1000_VFRE, 0);
1968 wr32(E1000_VFTE, 0);
1969 }
1970
1971 /* Allow time for pending master requests to run */
1972 hw->mac.ops.reset_hw(hw);
1973 wr32(E1000_WUC, 0);
1974
1975 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1976 /* need to resetup here after media swap */
1977 adapter->ei.get_invariants(hw);
1978 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1979 }
1980 if ((mac->type == e1000_82575) &&
1981 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1982 igb_enable_mas(adapter);
1983 }
1984 if (hw->mac.ops.init_hw(hw))
1985 dev_err(&pdev->dev, "Hardware Error\n");
1986
1987 /* Flow control settings reset on hardware reset, so guarantee flow
1988 * control is off when forcing speed.
1989 */
1990 if (!hw->mac.autoneg)
1991 igb_force_mac_fc(hw);
1992
1993 igb_init_dmac(adapter, pba);
1994 #ifdef CONFIG_IGB_HWMON
1995 /* Re-initialize the thermal sensor on i350 devices. */
1996 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1997 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1998 /* If present, re-initialize the external thermal sensor
1999 * interface.
2000 */
2001 if (adapter->ets)
2002 mac->ops.init_thermal_sensor_thresh(hw);
2003 }
2004 }
2005 #endif
2006 /* Re-establish EEE setting */
2007 if (hw->phy.media_type == e1000_media_type_copper) {
2008 switch (mac->type) {
2009 case e1000_i350:
2010 case e1000_i210:
2011 case e1000_i211:
2012 igb_set_eee_i350(hw, true, true);
2013 break;
2014 case e1000_i354:
2015 igb_set_eee_i354(hw, true, true);
2016 break;
2017 default:
2018 break;
2019 }
2020 }
2021 if (!netif_running(adapter->netdev))
2022 igb_power_down_link(adapter);
2023
2024 igb_update_mng_vlan(adapter);
2025
2026 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2027 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2028
2029 /* Re-enable PTP, where applicable. */
2030 igb_ptp_reset(adapter);
2031
2032 igb_get_phy_info(hw);
2033 }
2034
2035 static netdev_features_t igb_fix_features(struct net_device *netdev,
2036 netdev_features_t features)
2037 {
2038 /* Since there is no support for separate Rx/Tx vlan accel
2039 * enable/disable make sure Tx flag is always in same state as Rx.
2040 */
2041 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2042 features |= NETIF_F_HW_VLAN_CTAG_TX;
2043 else
2044 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2045
2046 return features;
2047 }
2048
2049 static int igb_set_features(struct net_device *netdev,
2050 netdev_features_t features)
2051 {
2052 netdev_features_t changed = netdev->features ^ features;
2053 struct igb_adapter *adapter = netdev_priv(netdev);
2054
2055 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2056 igb_vlan_mode(netdev, features);
2057
2058 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2059 return 0;
2060
2061 netdev->features = features;
2062
2063 if (netif_running(netdev))
2064 igb_reinit_locked(adapter);
2065 else
2066 igb_reset(adapter);
2067
2068 return 0;
2069 }
2070
2071 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2072 struct net_device *dev,
2073 const unsigned char *addr, u16 vid,
2074 u16 flags)
2075 {
2076 /* guarantee we can provide a unique filter for the unicast address */
2077 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2078 struct igb_adapter *adapter = netdev_priv(dev);
2079 struct e1000_hw *hw = &adapter->hw;
2080 int vfn = adapter->vfs_allocated_count;
2081 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2082
2083 if (netdev_uc_count(dev) >= rar_entries)
2084 return -ENOMEM;
2085 }
2086
2087 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2088 }
2089
2090 #define IGB_MAX_MAC_HDR_LEN 127
2091 #define IGB_MAX_NETWORK_HDR_LEN 511
2092
2093 static netdev_features_t
2094 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2095 netdev_features_t features)
2096 {
2097 unsigned int network_hdr_len, mac_hdr_len;
2098
2099 /* Make certain the headers can be described by a context descriptor */
2100 mac_hdr_len = skb_network_header(skb) - skb->data;
2101 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2102 return features & ~(NETIF_F_HW_CSUM |
2103 NETIF_F_SCTP_CRC |
2104 NETIF_F_HW_VLAN_CTAG_TX |
2105 NETIF_F_TSO |
2106 NETIF_F_TSO6);
2107
2108 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2109 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2110 return features & ~(NETIF_F_HW_CSUM |
2111 NETIF_F_SCTP_CRC |
2112 NETIF_F_TSO |
2113 NETIF_F_TSO6);
2114
2115 /* We can only support IPV4 TSO in tunnels if we can mangle the
2116 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2117 */
2118 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2119 features &= ~NETIF_F_TSO;
2120
2121 return features;
2122 }
2123
2124 static const struct net_device_ops igb_netdev_ops = {
2125 .ndo_open = igb_open,
2126 .ndo_stop = igb_close,
2127 .ndo_start_xmit = igb_xmit_frame,
2128 .ndo_get_stats64 = igb_get_stats64,
2129 .ndo_set_rx_mode = igb_set_rx_mode,
2130 .ndo_set_mac_address = igb_set_mac,
2131 .ndo_change_mtu = igb_change_mtu,
2132 .ndo_do_ioctl = igb_ioctl,
2133 .ndo_tx_timeout = igb_tx_timeout,
2134 .ndo_validate_addr = eth_validate_addr,
2135 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2136 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2137 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2138 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2139 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2140 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2141 .ndo_get_vf_config = igb_ndo_get_vf_config,
2142 #ifdef CONFIG_NET_POLL_CONTROLLER
2143 .ndo_poll_controller = igb_netpoll,
2144 #endif
2145 .ndo_fix_features = igb_fix_features,
2146 .ndo_set_features = igb_set_features,
2147 .ndo_fdb_add = igb_ndo_fdb_add,
2148 .ndo_features_check = igb_features_check,
2149 };
2150
2151 /**
2152 * igb_set_fw_version - Configure version string for ethtool
2153 * @adapter: adapter struct
2154 **/
2155 void igb_set_fw_version(struct igb_adapter *adapter)
2156 {
2157 struct e1000_hw *hw = &adapter->hw;
2158 struct e1000_fw_version fw;
2159
2160 igb_get_fw_version(hw, &fw);
2161
2162 switch (hw->mac.type) {
2163 case e1000_i210:
2164 case e1000_i211:
2165 if (!(igb_get_flash_presence_i210(hw))) {
2166 snprintf(adapter->fw_version,
2167 sizeof(adapter->fw_version),
2168 "%2d.%2d-%d",
2169 fw.invm_major, fw.invm_minor,
2170 fw.invm_img_type);
2171 break;
2172 }
2173 /* fall through */
2174 default:
2175 /* if option is rom valid, display its version too */
2176 if (fw.or_valid) {
2177 snprintf(adapter->fw_version,
2178 sizeof(adapter->fw_version),
2179 "%d.%d, 0x%08x, %d.%d.%d",
2180 fw.eep_major, fw.eep_minor, fw.etrack_id,
2181 fw.or_major, fw.or_build, fw.or_patch);
2182 /* no option rom */
2183 } else if (fw.etrack_id != 0X0000) {
2184 snprintf(adapter->fw_version,
2185 sizeof(adapter->fw_version),
2186 "%d.%d, 0x%08x",
2187 fw.eep_major, fw.eep_minor, fw.etrack_id);
2188 } else {
2189 snprintf(adapter->fw_version,
2190 sizeof(adapter->fw_version),
2191 "%d.%d.%d",
2192 fw.eep_major, fw.eep_minor, fw.eep_build);
2193 }
2194 break;
2195 }
2196 }
2197
2198 /**
2199 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2200 *
2201 * @adapter: adapter struct
2202 **/
2203 static void igb_init_mas(struct igb_adapter *adapter)
2204 {
2205 struct e1000_hw *hw = &adapter->hw;
2206 u16 eeprom_data;
2207
2208 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2209 switch (hw->bus.func) {
2210 case E1000_FUNC_0:
2211 if (eeprom_data & IGB_MAS_ENABLE_0) {
2212 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2213 netdev_info(adapter->netdev,
2214 "MAS: Enabling Media Autosense for port %d\n",
2215 hw->bus.func);
2216 }
2217 break;
2218 case E1000_FUNC_1:
2219 if (eeprom_data & IGB_MAS_ENABLE_1) {
2220 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2221 netdev_info(adapter->netdev,
2222 "MAS: Enabling Media Autosense for port %d\n",
2223 hw->bus.func);
2224 }
2225 break;
2226 case E1000_FUNC_2:
2227 if (eeprom_data & IGB_MAS_ENABLE_2) {
2228 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2229 netdev_info(adapter->netdev,
2230 "MAS: Enabling Media Autosense for port %d\n",
2231 hw->bus.func);
2232 }
2233 break;
2234 case E1000_FUNC_3:
2235 if (eeprom_data & IGB_MAS_ENABLE_3) {
2236 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2237 netdev_info(adapter->netdev,
2238 "MAS: Enabling Media Autosense for port %d\n",
2239 hw->bus.func);
2240 }
2241 break;
2242 default:
2243 /* Shouldn't get here */
2244 netdev_err(adapter->netdev,
2245 "MAS: Invalid port configuration, returning\n");
2246 break;
2247 }
2248 }
2249
2250 /**
2251 * igb_init_i2c - Init I2C interface
2252 * @adapter: pointer to adapter structure
2253 **/
2254 static s32 igb_init_i2c(struct igb_adapter *adapter)
2255 {
2256 s32 status = 0;
2257
2258 /* I2C interface supported on i350 devices */
2259 if (adapter->hw.mac.type != e1000_i350)
2260 return 0;
2261
2262 /* Initialize the i2c bus which is controlled by the registers.
2263 * This bus will use the i2c_algo_bit structue that implements
2264 * the protocol through toggling of the 4 bits in the register.
2265 */
2266 adapter->i2c_adap.owner = THIS_MODULE;
2267 adapter->i2c_algo = igb_i2c_algo;
2268 adapter->i2c_algo.data = adapter;
2269 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2270 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2271 strlcpy(adapter->i2c_adap.name, "igb BB",
2272 sizeof(adapter->i2c_adap.name));
2273 status = i2c_bit_add_bus(&adapter->i2c_adap);
2274 return status;
2275 }
2276
2277 /**
2278 * igb_probe - Device Initialization Routine
2279 * @pdev: PCI device information struct
2280 * @ent: entry in igb_pci_tbl
2281 *
2282 * Returns 0 on success, negative on failure
2283 *
2284 * igb_probe initializes an adapter identified by a pci_dev structure.
2285 * The OS initialization, configuring of the adapter private structure,
2286 * and a hardware reset occur.
2287 **/
2288 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2289 {
2290 struct net_device *netdev;
2291 struct igb_adapter *adapter;
2292 struct e1000_hw *hw;
2293 u16 eeprom_data = 0;
2294 s32 ret_val;
2295 static int global_quad_port_a; /* global quad port a indication */
2296 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2297 int err, pci_using_dac;
2298 u8 part_str[E1000_PBANUM_LENGTH];
2299
2300 /* Catch broken hardware that put the wrong VF device ID in
2301 * the PCIe SR-IOV capability.
2302 */
2303 if (pdev->is_virtfn) {
2304 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2305 pci_name(pdev), pdev->vendor, pdev->device);
2306 return -EINVAL;
2307 }
2308
2309 err = pci_enable_device_mem(pdev);
2310 if (err)
2311 return err;
2312
2313 pci_using_dac = 0;
2314 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2315 if (!err) {
2316 pci_using_dac = 1;
2317 } else {
2318 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2319 if (err) {
2320 dev_err(&pdev->dev,
2321 "No usable DMA configuration, aborting\n");
2322 goto err_dma;
2323 }
2324 }
2325
2326 err = pci_request_mem_regions(pdev, igb_driver_name);
2327 if (err)
2328 goto err_pci_reg;
2329
2330 pci_enable_pcie_error_reporting(pdev);
2331
2332 pci_set_master(pdev);
2333 pci_save_state(pdev);
2334
2335 err = -ENOMEM;
2336 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2337 IGB_MAX_TX_QUEUES);
2338 if (!netdev)
2339 goto err_alloc_etherdev;
2340
2341 SET_NETDEV_DEV(netdev, &pdev->dev);
2342
2343 pci_set_drvdata(pdev, netdev);
2344 adapter = netdev_priv(netdev);
2345 adapter->netdev = netdev;
2346 adapter->pdev = pdev;
2347 hw = &adapter->hw;
2348 hw->back = adapter;
2349 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2350
2351 err = -EIO;
2352 adapter->io_addr = pci_iomap(pdev, 0, 0);
2353 if (!adapter->io_addr)
2354 goto err_ioremap;
2355 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2356 hw->hw_addr = adapter->io_addr;
2357
2358 netdev->netdev_ops = &igb_netdev_ops;
2359 igb_set_ethtool_ops(netdev);
2360 netdev->watchdog_timeo = 5 * HZ;
2361
2362 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2363
2364 netdev->mem_start = pci_resource_start(pdev, 0);
2365 netdev->mem_end = pci_resource_end(pdev, 0);
2366
2367 /* PCI config space info */
2368 hw->vendor_id = pdev->vendor;
2369 hw->device_id = pdev->device;
2370 hw->revision_id = pdev->revision;
2371 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2372 hw->subsystem_device_id = pdev->subsystem_device;
2373
2374 /* Copy the default MAC, PHY and NVM function pointers */
2375 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2376 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2377 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2378 /* Initialize skew-specific constants */
2379 err = ei->get_invariants(hw);
2380 if (err)
2381 goto err_sw_init;
2382
2383 /* setup the private structure */
2384 err = igb_sw_init(adapter);
2385 if (err)
2386 goto err_sw_init;
2387
2388 igb_get_bus_info_pcie(hw);
2389
2390 hw->phy.autoneg_wait_to_complete = false;
2391
2392 /* Copper options */
2393 if (hw->phy.media_type == e1000_media_type_copper) {
2394 hw->phy.mdix = AUTO_ALL_MODES;
2395 hw->phy.disable_polarity_correction = false;
2396 hw->phy.ms_type = e1000_ms_hw_default;
2397 }
2398
2399 if (igb_check_reset_block(hw))
2400 dev_info(&pdev->dev,
2401 "PHY reset is blocked due to SOL/IDER session.\n");
2402
2403 /* features is initialized to 0 in allocation, it might have bits
2404 * set by igb_sw_init so we should use an or instead of an
2405 * assignment.
2406 */
2407 netdev->features |= NETIF_F_SG |
2408 NETIF_F_TSO |
2409 NETIF_F_TSO6 |
2410 NETIF_F_RXHASH |
2411 NETIF_F_RXCSUM |
2412 NETIF_F_HW_CSUM;
2413
2414 if (hw->mac.type >= e1000_82576)
2415 netdev->features |= NETIF_F_SCTP_CRC;
2416
2417 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
2418 NETIF_F_GSO_GRE_CSUM | \
2419 NETIF_F_GSO_IPXIP4 | \
2420 NETIF_F_GSO_IPXIP6 | \
2421 NETIF_F_GSO_UDP_TUNNEL | \
2422 NETIF_F_GSO_UDP_TUNNEL_CSUM)
2423
2424 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
2425 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
2426
2427 /* copy netdev features into list of user selectable features */
2428 netdev->hw_features |= netdev->features |
2429 NETIF_F_HW_VLAN_CTAG_RX |
2430 NETIF_F_HW_VLAN_CTAG_TX |
2431 NETIF_F_RXALL;
2432
2433 if (hw->mac.type >= e1000_i350)
2434 netdev->hw_features |= NETIF_F_NTUPLE;
2435
2436 if (pci_using_dac)
2437 netdev->features |= NETIF_F_HIGHDMA;
2438
2439 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
2440 netdev->mpls_features |= NETIF_F_HW_CSUM;
2441 netdev->hw_enc_features |= netdev->vlan_features;
2442
2443 /* set this bit last since it cannot be part of vlan_features */
2444 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
2445 NETIF_F_HW_VLAN_CTAG_RX |
2446 NETIF_F_HW_VLAN_CTAG_TX;
2447
2448 netdev->priv_flags |= IFF_SUPP_NOFCS;
2449
2450 netdev->priv_flags |= IFF_UNICAST_FLT;
2451
2452 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2453
2454 /* before reading the NVM, reset the controller to put the device in a
2455 * known good starting state
2456 */
2457 hw->mac.ops.reset_hw(hw);
2458
2459 /* make sure the NVM is good , i211/i210 parts can have special NVM
2460 * that doesn't contain a checksum
2461 */
2462 switch (hw->mac.type) {
2463 case e1000_i210:
2464 case e1000_i211:
2465 if (igb_get_flash_presence_i210(hw)) {
2466 if (hw->nvm.ops.validate(hw) < 0) {
2467 dev_err(&pdev->dev,
2468 "The NVM Checksum Is Not Valid\n");
2469 err = -EIO;
2470 goto err_eeprom;
2471 }
2472 }
2473 break;
2474 default:
2475 if (hw->nvm.ops.validate(hw) < 0) {
2476 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2477 err = -EIO;
2478 goto err_eeprom;
2479 }
2480 break;
2481 }
2482
2483 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
2484 /* copy the MAC address out of the NVM */
2485 if (hw->mac.ops.read_mac_addr(hw))
2486 dev_err(&pdev->dev, "NVM Read Error\n");
2487 }
2488
2489 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2490
2491 if (!is_valid_ether_addr(netdev->dev_addr)) {
2492 dev_err(&pdev->dev, "Invalid MAC Address\n");
2493 err = -EIO;
2494 goto err_eeprom;
2495 }
2496
2497 /* get firmware version for ethtool -i */
2498 igb_set_fw_version(adapter);
2499
2500 /* configure RXPBSIZE and TXPBSIZE */
2501 if (hw->mac.type == e1000_i210) {
2502 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2503 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2504 }
2505
2506 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2507 (unsigned long) adapter);
2508 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2509 (unsigned long) adapter);
2510
2511 INIT_WORK(&adapter->reset_task, igb_reset_task);
2512 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2513
2514 /* Initialize link properties that are user-changeable */
2515 adapter->fc_autoneg = true;
2516 hw->mac.autoneg = true;
2517 hw->phy.autoneg_advertised = 0x2f;
2518
2519 hw->fc.requested_mode = e1000_fc_default;
2520 hw->fc.current_mode = e1000_fc_default;
2521
2522 igb_validate_mdi_setting(hw);
2523
2524 /* By default, support wake on port A */
2525 if (hw->bus.func == 0)
2526 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2527
2528 /* Check the NVM for wake support on non-port A ports */
2529 if (hw->mac.type >= e1000_82580)
2530 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2531 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2532 &eeprom_data);
2533 else if (hw->bus.func == 1)
2534 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2535
2536 if (eeprom_data & IGB_EEPROM_APME)
2537 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2538
2539 /* now that we have the eeprom settings, apply the special cases where
2540 * the eeprom may be wrong or the board simply won't support wake on
2541 * lan on a particular port
2542 */
2543 switch (pdev->device) {
2544 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2545 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2546 break;
2547 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2548 case E1000_DEV_ID_82576_FIBER:
2549 case E1000_DEV_ID_82576_SERDES:
2550 /* Wake events only supported on port A for dual fiber
2551 * regardless of eeprom setting
2552 */
2553 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2554 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2555 break;
2556 case E1000_DEV_ID_82576_QUAD_COPPER:
2557 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2558 /* if quad port adapter, disable WoL on all but port A */
2559 if (global_quad_port_a != 0)
2560 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2561 else
2562 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2563 /* Reset for multiple quad port adapters */
2564 if (++global_quad_port_a == 4)
2565 global_quad_port_a = 0;
2566 break;
2567 default:
2568 /* If the device can't wake, don't set software support */
2569 if (!device_can_wakeup(&adapter->pdev->dev))
2570 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2571 }
2572
2573 /* initialize the wol settings based on the eeprom settings */
2574 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2575 adapter->wol |= E1000_WUFC_MAG;
2576
2577 /* Some vendors want WoL disabled by default, but still supported */
2578 if ((hw->mac.type == e1000_i350) &&
2579 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2580 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2581 adapter->wol = 0;
2582 }
2583
2584 /* Some vendors want the ability to Use the EEPROM setting as
2585 * enable/disable only, and not for capability
2586 */
2587 if (((hw->mac.type == e1000_i350) ||
2588 (hw->mac.type == e1000_i354)) &&
2589 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
2590 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2591 adapter->wol = 0;
2592 }
2593 if (hw->mac.type == e1000_i350) {
2594 if (((pdev->subsystem_device == 0x5001) ||
2595 (pdev->subsystem_device == 0x5002)) &&
2596 (hw->bus.func == 0)) {
2597 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2598 adapter->wol = 0;
2599 }
2600 if (pdev->subsystem_device == 0x1F52)
2601 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2602 }
2603
2604 device_set_wakeup_enable(&adapter->pdev->dev,
2605 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2606
2607 /* reset the hardware with the new settings */
2608 igb_reset(adapter);
2609
2610 /* Init the I2C interface */
2611 err = igb_init_i2c(adapter);
2612 if (err) {
2613 dev_err(&pdev->dev, "failed to init i2c interface\n");
2614 goto err_eeprom;
2615 }
2616
2617 /* let the f/w know that the h/w is now under the control of the
2618 * driver.
2619 */
2620 igb_get_hw_control(adapter);
2621
2622 strcpy(netdev->name, "eth%d");
2623 err = register_netdev(netdev);
2624 if (err)
2625 goto err_register;
2626
2627 /* carrier off reporting is important to ethtool even BEFORE open */
2628 netif_carrier_off(netdev);
2629
2630 #ifdef CONFIG_IGB_DCA
2631 if (dca_add_requester(&pdev->dev) == 0) {
2632 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2633 dev_info(&pdev->dev, "DCA enabled\n");
2634 igb_setup_dca(adapter);
2635 }
2636
2637 #endif
2638 #ifdef CONFIG_IGB_HWMON
2639 /* Initialize the thermal sensor on i350 devices. */
2640 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2641 u16 ets_word;
2642
2643 /* Read the NVM to determine if this i350 device supports an
2644 * external thermal sensor.
2645 */
2646 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2647 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2648 adapter->ets = true;
2649 else
2650 adapter->ets = false;
2651 if (igb_sysfs_init(adapter))
2652 dev_err(&pdev->dev,
2653 "failed to allocate sysfs resources\n");
2654 } else {
2655 adapter->ets = false;
2656 }
2657 #endif
2658 /* Check if Media Autosense is enabled */
2659 adapter->ei = *ei;
2660 if (hw->dev_spec._82575.mas_capable)
2661 igb_init_mas(adapter);
2662
2663 /* do hw tstamp init after resetting */
2664 igb_ptp_init(adapter);
2665
2666 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2667 /* print bus type/speed/width info, not applicable to i354 */
2668 if (hw->mac.type != e1000_i354) {
2669 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2670 netdev->name,
2671 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2672 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2673 "unknown"),
2674 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2675 "Width x4" :
2676 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2677 "Width x2" :
2678 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2679 "Width x1" : "unknown"), netdev->dev_addr);
2680 }
2681
2682 if ((hw->mac.type >= e1000_i210 ||
2683 igb_get_flash_presence_i210(hw))) {
2684 ret_val = igb_read_part_string(hw, part_str,
2685 E1000_PBANUM_LENGTH);
2686 } else {
2687 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2688 }
2689
2690 if (ret_val)
2691 strcpy(part_str, "Unknown");
2692 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2693 dev_info(&pdev->dev,
2694 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2695 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2696 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2697 adapter->num_rx_queues, adapter->num_tx_queues);
2698 if (hw->phy.media_type == e1000_media_type_copper) {
2699 switch (hw->mac.type) {
2700 case e1000_i350:
2701 case e1000_i210:
2702 case e1000_i211:
2703 /* Enable EEE for internal copper PHY devices */
2704 err = igb_set_eee_i350(hw, true, true);
2705 if ((!err) &&
2706 (!hw->dev_spec._82575.eee_disable)) {
2707 adapter->eee_advert =
2708 MDIO_EEE_100TX | MDIO_EEE_1000T;
2709 adapter->flags |= IGB_FLAG_EEE;
2710 }
2711 break;
2712 case e1000_i354:
2713 if ((rd32(E1000_CTRL_EXT) &
2714 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2715 err = igb_set_eee_i354(hw, true, true);
2716 if ((!err) &&
2717 (!hw->dev_spec._82575.eee_disable)) {
2718 adapter->eee_advert =
2719 MDIO_EEE_100TX | MDIO_EEE_1000T;
2720 adapter->flags |= IGB_FLAG_EEE;
2721 }
2722 }
2723 break;
2724 default:
2725 break;
2726 }
2727 }
2728 pm_runtime_put_noidle(&pdev->dev);
2729 return 0;
2730
2731 err_register:
2732 igb_release_hw_control(adapter);
2733 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2734 err_eeprom:
2735 if (!igb_check_reset_block(hw))
2736 igb_reset_phy(hw);
2737
2738 if (hw->flash_address)
2739 iounmap(hw->flash_address);
2740 err_sw_init:
2741 kfree(adapter->shadow_vfta);
2742 igb_clear_interrupt_scheme(adapter);
2743 #ifdef CONFIG_PCI_IOV
2744 igb_disable_sriov(pdev);
2745 #endif
2746 pci_iounmap(pdev, adapter->io_addr);
2747 err_ioremap:
2748 free_netdev(netdev);
2749 err_alloc_etherdev:
2750 pci_release_mem_regions(pdev);
2751 err_pci_reg:
2752 err_dma:
2753 pci_disable_device(pdev);
2754 return err;
2755 }
2756
2757 #ifdef CONFIG_PCI_IOV
2758 static int igb_disable_sriov(struct pci_dev *pdev)
2759 {
2760 struct net_device *netdev = pci_get_drvdata(pdev);
2761 struct igb_adapter *adapter = netdev_priv(netdev);
2762 struct e1000_hw *hw = &adapter->hw;
2763
2764 /* reclaim resources allocated to VFs */
2765 if (adapter->vf_data) {
2766 /* disable iov and allow time for transactions to clear */
2767 if (pci_vfs_assigned(pdev)) {
2768 dev_warn(&pdev->dev,
2769 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2770 return -EPERM;
2771 } else {
2772 pci_disable_sriov(pdev);
2773 msleep(500);
2774 }
2775
2776 kfree(adapter->vf_data);
2777 adapter->vf_data = NULL;
2778 adapter->vfs_allocated_count = 0;
2779 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2780 wrfl();
2781 msleep(100);
2782 dev_info(&pdev->dev, "IOV Disabled\n");
2783
2784 /* Re-enable DMA Coalescing flag since IOV is turned off */
2785 adapter->flags |= IGB_FLAG_DMAC;
2786 }
2787
2788 return 0;
2789 }
2790
2791 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2792 {
2793 struct net_device *netdev = pci_get_drvdata(pdev);
2794 struct igb_adapter *adapter = netdev_priv(netdev);
2795 int old_vfs = pci_num_vf(pdev);
2796 int err = 0;
2797 int i;
2798
2799 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2800 err = -EPERM;
2801 goto out;
2802 }
2803 if (!num_vfs)
2804 goto out;
2805
2806 if (old_vfs) {
2807 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2808 old_vfs, max_vfs);
2809 adapter->vfs_allocated_count = old_vfs;
2810 } else
2811 adapter->vfs_allocated_count = num_vfs;
2812
2813 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2814 sizeof(struct vf_data_storage), GFP_KERNEL);
2815
2816 /* if allocation failed then we do not support SR-IOV */
2817 if (!adapter->vf_data) {
2818 adapter->vfs_allocated_count = 0;
2819 dev_err(&pdev->dev,
2820 "Unable to allocate memory for VF Data Storage\n");
2821 err = -ENOMEM;
2822 goto out;
2823 }
2824
2825 /* only call pci_enable_sriov() if no VFs are allocated already */
2826 if (!old_vfs) {
2827 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2828 if (err)
2829 goto err_out;
2830 }
2831 dev_info(&pdev->dev, "%d VFs allocated\n",
2832 adapter->vfs_allocated_count);
2833 for (i = 0; i < adapter->vfs_allocated_count; i++)
2834 igb_vf_configure(adapter, i);
2835
2836 /* DMA Coalescing is not supported in IOV mode. */
2837 adapter->flags &= ~IGB_FLAG_DMAC;
2838 goto out;
2839
2840 err_out:
2841 kfree(adapter->vf_data);
2842 adapter->vf_data = NULL;
2843 adapter->vfs_allocated_count = 0;
2844 out:
2845 return err;
2846 }
2847
2848 #endif
2849 /**
2850 * igb_remove_i2c - Cleanup I2C interface
2851 * @adapter: pointer to adapter structure
2852 **/
2853 static void igb_remove_i2c(struct igb_adapter *adapter)
2854 {
2855 /* free the adapter bus structure */
2856 i2c_del_adapter(&adapter->i2c_adap);
2857 }
2858
2859 /**
2860 * igb_remove - Device Removal Routine
2861 * @pdev: PCI device information struct
2862 *
2863 * igb_remove is called by the PCI subsystem to alert the driver
2864 * that it should release a PCI device. The could be caused by a
2865 * Hot-Plug event, or because the driver is going to be removed from
2866 * memory.
2867 **/
2868 static void igb_remove(struct pci_dev *pdev)
2869 {
2870 struct net_device *netdev = pci_get_drvdata(pdev);
2871 struct igb_adapter *adapter = netdev_priv(netdev);
2872 struct e1000_hw *hw = &adapter->hw;
2873
2874 pm_runtime_get_noresume(&pdev->dev);
2875 #ifdef CONFIG_IGB_HWMON
2876 igb_sysfs_exit(adapter);
2877 #endif
2878 igb_remove_i2c(adapter);
2879 igb_ptp_stop(adapter);
2880 /* The watchdog timer may be rescheduled, so explicitly
2881 * disable watchdog from being rescheduled.
2882 */
2883 set_bit(__IGB_DOWN, &adapter->state);
2884 del_timer_sync(&adapter->watchdog_timer);
2885 del_timer_sync(&adapter->phy_info_timer);
2886
2887 cancel_work_sync(&adapter->reset_task);
2888 cancel_work_sync(&adapter->watchdog_task);
2889
2890 #ifdef CONFIG_IGB_DCA
2891 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2892 dev_info(&pdev->dev, "DCA disabled\n");
2893 dca_remove_requester(&pdev->dev);
2894 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2895 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2896 }
2897 #endif
2898
2899 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2900 * would have already happened in close and is redundant.
2901 */
2902 igb_release_hw_control(adapter);
2903
2904 #ifdef CONFIG_PCI_IOV
2905 igb_disable_sriov(pdev);
2906 #endif
2907
2908 unregister_netdev(netdev);
2909
2910 igb_clear_interrupt_scheme(adapter);
2911
2912 pci_iounmap(pdev, adapter->io_addr);
2913 if (hw->flash_address)
2914 iounmap(hw->flash_address);
2915 pci_release_mem_regions(pdev);
2916
2917 kfree(adapter->shadow_vfta);
2918 free_netdev(netdev);
2919
2920 pci_disable_pcie_error_reporting(pdev);
2921
2922 pci_disable_device(pdev);
2923 }
2924
2925 /**
2926 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2927 * @adapter: board private structure to initialize
2928 *
2929 * This function initializes the vf specific data storage and then attempts to
2930 * allocate the VFs. The reason for ordering it this way is because it is much
2931 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2932 * the memory for the VFs.
2933 **/
2934 static void igb_probe_vfs(struct igb_adapter *adapter)
2935 {
2936 #ifdef CONFIG_PCI_IOV
2937 struct pci_dev *pdev = adapter->pdev;
2938 struct e1000_hw *hw = &adapter->hw;
2939
2940 /* Virtualization features not supported on i210 family. */
2941 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2942 return;
2943
2944 /* Of the below we really only want the effect of getting
2945 * IGB_FLAG_HAS_MSIX set (if available), without which
2946 * igb_enable_sriov() has no effect.
2947 */
2948 igb_set_interrupt_capability(adapter, true);
2949 igb_reset_interrupt_capability(adapter);
2950
2951 pci_sriov_set_totalvfs(pdev, 7);
2952 igb_enable_sriov(pdev, max_vfs);
2953
2954 #endif /* CONFIG_PCI_IOV */
2955 }
2956
2957 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2958 {
2959 struct e1000_hw *hw = &adapter->hw;
2960 u32 max_rss_queues;
2961
2962 /* Determine the maximum number of RSS queues supported. */
2963 switch (hw->mac.type) {
2964 case e1000_i211:
2965 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2966 break;
2967 case e1000_82575:
2968 case e1000_i210:
2969 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2970 break;
2971 case e1000_i350:
2972 /* I350 cannot do RSS and SR-IOV at the same time */
2973 if (!!adapter->vfs_allocated_count) {
2974 max_rss_queues = 1;
2975 break;
2976 }
2977 /* fall through */
2978 case e1000_82576:
2979 if (!!adapter->vfs_allocated_count) {
2980 max_rss_queues = 2;
2981 break;
2982 }
2983 /* fall through */
2984 case e1000_82580:
2985 case e1000_i354:
2986 default:
2987 max_rss_queues = IGB_MAX_RX_QUEUES;
2988 break;
2989 }
2990
2991 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2992
2993 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2994 }
2995
2996 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2997 const u32 max_rss_queues)
2998 {
2999 struct e1000_hw *hw = &adapter->hw;
3000
3001 /* Determine if we need to pair queues. */
3002 switch (hw->mac.type) {
3003 case e1000_82575:
3004 case e1000_i211:
3005 /* Device supports enough interrupts without queue pairing. */
3006 break;
3007 case e1000_82576:
3008 case e1000_82580:
3009 case e1000_i350:
3010 case e1000_i354:
3011 case e1000_i210:
3012 default:
3013 /* If rss_queues > half of max_rss_queues, pair the queues in
3014 * order to conserve interrupts due to limited supply.
3015 */
3016 if (adapter->rss_queues > (max_rss_queues / 2))
3017 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3018 else
3019 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3020 break;
3021 }
3022 }
3023
3024 /**
3025 * igb_sw_init - Initialize general software structures (struct igb_adapter)
3026 * @adapter: board private structure to initialize
3027 *
3028 * igb_sw_init initializes the Adapter private data structure.
3029 * Fields are initialized based on PCI device information and
3030 * OS network device settings (MTU size).
3031 **/
3032 static int igb_sw_init(struct igb_adapter *adapter)
3033 {
3034 struct e1000_hw *hw = &adapter->hw;
3035 struct net_device *netdev = adapter->netdev;
3036 struct pci_dev *pdev = adapter->pdev;
3037
3038 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3039
3040 /* set default ring sizes */
3041 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3042 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3043
3044 /* set default ITR values */
3045 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3046 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3047
3048 /* set default work limits */
3049 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3050
3051 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3052 VLAN_HLEN;
3053 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3054
3055 spin_lock_init(&adapter->stats64_lock);
3056 #ifdef CONFIG_PCI_IOV
3057 switch (hw->mac.type) {
3058 case e1000_82576:
3059 case e1000_i350:
3060 if (max_vfs > 7) {
3061 dev_warn(&pdev->dev,
3062 "Maximum of 7 VFs per PF, using max\n");
3063 max_vfs = adapter->vfs_allocated_count = 7;
3064 } else
3065 adapter->vfs_allocated_count = max_vfs;
3066 if (adapter->vfs_allocated_count)
3067 dev_warn(&pdev->dev,
3068 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3069 break;
3070 default:
3071 break;
3072 }
3073 #endif /* CONFIG_PCI_IOV */
3074
3075 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3076 adapter->flags |= IGB_FLAG_HAS_MSIX;
3077
3078 igb_probe_vfs(adapter);
3079
3080 igb_init_queue_configuration(adapter);
3081
3082 /* Setup and initialize a copy of the hw vlan table array */
3083 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3084 GFP_ATOMIC);
3085
3086 /* This call may decrease the number of queues */
3087 if (igb_init_interrupt_scheme(adapter, true)) {
3088 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3089 return -ENOMEM;
3090 }
3091
3092 /* Explicitly disable IRQ since the NIC can be in any state. */
3093 igb_irq_disable(adapter);
3094
3095 if (hw->mac.type >= e1000_i350)
3096 adapter->flags &= ~IGB_FLAG_DMAC;
3097
3098 set_bit(__IGB_DOWN, &adapter->state);
3099 return 0;
3100 }
3101
3102 /**
3103 * igb_open - Called when a network interface is made active
3104 * @netdev: network interface device structure
3105 *
3106 * Returns 0 on success, negative value on failure
3107 *
3108 * The open entry point is called when a network interface is made
3109 * active by the system (IFF_UP). At this point all resources needed
3110 * for transmit and receive operations are allocated, the interrupt
3111 * handler is registered with the OS, the watchdog timer is started,
3112 * and the stack is notified that the interface is ready.
3113 **/
3114 static int __igb_open(struct net_device *netdev, bool resuming)
3115 {
3116 struct igb_adapter *adapter = netdev_priv(netdev);
3117 struct e1000_hw *hw = &adapter->hw;
3118 struct pci_dev *pdev = adapter->pdev;
3119 int err;
3120 int i;
3121
3122 /* disallow open during test */
3123 if (test_bit(__IGB_TESTING, &adapter->state)) {
3124 WARN_ON(resuming);
3125 return -EBUSY;
3126 }
3127
3128 if (!resuming)
3129 pm_runtime_get_sync(&pdev->dev);
3130
3131 netif_carrier_off(netdev);
3132
3133 /* allocate transmit descriptors */
3134 err = igb_setup_all_tx_resources(adapter);
3135 if (err)
3136 goto err_setup_tx;
3137
3138 /* allocate receive descriptors */
3139 err = igb_setup_all_rx_resources(adapter);
3140 if (err)
3141 goto err_setup_rx;
3142
3143 igb_power_up_link(adapter);
3144
3145 /* before we allocate an interrupt, we must be ready to handle it.
3146 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3147 * as soon as we call pci_request_irq, so we have to setup our
3148 * clean_rx handler before we do so.
3149 */
3150 igb_configure(adapter);
3151
3152 err = igb_request_irq(adapter);
3153 if (err)
3154 goto err_req_irq;
3155
3156 /* Notify the stack of the actual queue counts. */
3157 err = netif_set_real_num_tx_queues(adapter->netdev,
3158 adapter->num_tx_queues);
3159 if (err)
3160 goto err_set_queues;
3161
3162 err = netif_set_real_num_rx_queues(adapter->netdev,
3163 adapter->num_rx_queues);
3164 if (err)
3165 goto err_set_queues;
3166
3167 /* From here on the code is the same as igb_up() */
3168 clear_bit(__IGB_DOWN, &adapter->state);
3169
3170 for (i = 0; i < adapter->num_q_vectors; i++)
3171 napi_enable(&(adapter->q_vector[i]->napi));
3172
3173 /* Clear any pending interrupts. */
3174 rd32(E1000_ICR);
3175
3176 igb_irq_enable(adapter);
3177
3178 /* notify VFs that reset has been completed */
3179 if (adapter->vfs_allocated_count) {
3180 u32 reg_data = rd32(E1000_CTRL_EXT);
3181
3182 reg_data |= E1000_CTRL_EXT_PFRSTD;
3183 wr32(E1000_CTRL_EXT, reg_data);
3184 }
3185
3186 netif_tx_start_all_queues(netdev);
3187
3188 if (!resuming)
3189 pm_runtime_put(&pdev->dev);
3190
3191 /* start the watchdog. */
3192 hw->mac.get_link_status = 1;
3193 schedule_work(&adapter->watchdog_task);
3194
3195 return 0;
3196
3197 err_set_queues:
3198 igb_free_irq(adapter);
3199 err_req_irq:
3200 igb_release_hw_control(adapter);
3201 igb_power_down_link(adapter);
3202 igb_free_all_rx_resources(adapter);
3203 err_setup_rx:
3204 igb_free_all_tx_resources(adapter);
3205 err_setup_tx:
3206 igb_reset(adapter);
3207 if (!resuming)
3208 pm_runtime_put(&pdev->dev);
3209
3210 return err;
3211 }
3212
3213 int igb_open(struct net_device *netdev)
3214 {
3215 return __igb_open(netdev, false);
3216 }
3217
3218 /**
3219 * igb_close - Disables a network interface
3220 * @netdev: network interface device structure
3221 *
3222 * Returns 0, this is not allowed to fail
3223 *
3224 * The close entry point is called when an interface is de-activated
3225 * by the OS. The hardware is still under the driver's control, but
3226 * needs to be disabled. A global MAC reset is issued to stop the
3227 * hardware, and all transmit and receive resources are freed.
3228 **/
3229 static int __igb_close(struct net_device *netdev, bool suspending)
3230 {
3231 struct igb_adapter *adapter = netdev_priv(netdev);
3232 struct pci_dev *pdev = adapter->pdev;
3233
3234 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3235
3236 if (!suspending)
3237 pm_runtime_get_sync(&pdev->dev);
3238
3239 igb_down(adapter);
3240 igb_free_irq(adapter);
3241
3242 igb_free_all_tx_resources(adapter);
3243 igb_free_all_rx_resources(adapter);
3244
3245 if (!suspending)
3246 pm_runtime_put_sync(&pdev->dev);
3247 return 0;
3248 }
3249
3250 int igb_close(struct net_device *netdev)
3251 {
3252 return __igb_close(netdev, false);
3253 }
3254
3255 /**
3256 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3257 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3258 *
3259 * Return 0 on success, negative on failure
3260 **/
3261 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3262 {
3263 struct device *dev = tx_ring->dev;
3264 int size;
3265
3266 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3267
3268 tx_ring->tx_buffer_info = vzalloc(size);
3269 if (!tx_ring->tx_buffer_info)
3270 goto err;
3271
3272 /* round up to nearest 4K */
3273 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3274 tx_ring->size = ALIGN(tx_ring->size, 4096);
3275
3276 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3277 &tx_ring->dma, GFP_KERNEL);
3278 if (!tx_ring->desc)
3279 goto err;
3280
3281 tx_ring->next_to_use = 0;
3282 tx_ring->next_to_clean = 0;
3283
3284 return 0;
3285
3286 err:
3287 vfree(tx_ring->tx_buffer_info);
3288 tx_ring->tx_buffer_info = NULL;
3289 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3290 return -ENOMEM;
3291 }
3292
3293 /**
3294 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3295 * (Descriptors) for all queues
3296 * @adapter: board private structure
3297 *
3298 * Return 0 on success, negative on failure
3299 **/
3300 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3301 {
3302 struct pci_dev *pdev = adapter->pdev;
3303 int i, err = 0;
3304
3305 for (i = 0; i < adapter->num_tx_queues; i++) {
3306 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3307 if (err) {
3308 dev_err(&pdev->dev,
3309 "Allocation for Tx Queue %u failed\n", i);
3310 for (i--; i >= 0; i--)
3311 igb_free_tx_resources(adapter->tx_ring[i]);
3312 break;
3313 }
3314 }
3315
3316 return err;
3317 }
3318
3319 /**
3320 * igb_setup_tctl - configure the transmit control registers
3321 * @adapter: Board private structure
3322 **/
3323 void igb_setup_tctl(struct igb_adapter *adapter)
3324 {
3325 struct e1000_hw *hw = &adapter->hw;
3326 u32 tctl;
3327
3328 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3329 wr32(E1000_TXDCTL(0), 0);
3330
3331 /* Program the Transmit Control Register */
3332 tctl = rd32(E1000_TCTL);
3333 tctl &= ~E1000_TCTL_CT;
3334 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3335 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3336
3337 igb_config_collision_dist(hw);
3338
3339 /* Enable transmits */
3340 tctl |= E1000_TCTL_EN;
3341
3342 wr32(E1000_TCTL, tctl);
3343 }
3344
3345 /**
3346 * igb_configure_tx_ring - Configure transmit ring after Reset
3347 * @adapter: board private structure
3348 * @ring: tx ring to configure
3349 *
3350 * Configure a transmit ring after a reset.
3351 **/
3352 void igb_configure_tx_ring(struct igb_adapter *adapter,
3353 struct igb_ring *ring)
3354 {
3355 struct e1000_hw *hw = &adapter->hw;
3356 u32 txdctl = 0;
3357 u64 tdba = ring->dma;
3358 int reg_idx = ring->reg_idx;
3359
3360 /* disable the queue */
3361 wr32(E1000_TXDCTL(reg_idx), 0);
3362 wrfl();
3363 mdelay(10);
3364
3365 wr32(E1000_TDLEN(reg_idx),
3366 ring->count * sizeof(union e1000_adv_tx_desc));
3367 wr32(E1000_TDBAL(reg_idx),
3368 tdba & 0x00000000ffffffffULL);
3369 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3370
3371 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3372 wr32(E1000_TDH(reg_idx), 0);
3373 writel(0, ring->tail);
3374
3375 txdctl |= IGB_TX_PTHRESH;
3376 txdctl |= IGB_TX_HTHRESH << 8;
3377 txdctl |= IGB_TX_WTHRESH << 16;
3378
3379 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3380 wr32(E1000_TXDCTL(reg_idx), txdctl);
3381 }
3382
3383 /**
3384 * igb_configure_tx - Configure transmit Unit after Reset
3385 * @adapter: board private structure
3386 *
3387 * Configure the Tx unit of the MAC after a reset.
3388 **/
3389 static void igb_configure_tx(struct igb_adapter *adapter)
3390 {
3391 int i;
3392
3393 for (i = 0; i < adapter->num_tx_queues; i++)
3394 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3395 }
3396
3397 /**
3398 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3399 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3400 *
3401 * Returns 0 on success, negative on failure
3402 **/
3403 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3404 {
3405 struct device *dev = rx_ring->dev;
3406 int size;
3407
3408 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3409
3410 rx_ring->rx_buffer_info = vzalloc(size);
3411 if (!rx_ring->rx_buffer_info)
3412 goto err;
3413
3414 /* Round up to nearest 4K */
3415 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3416 rx_ring->size = ALIGN(rx_ring->size, 4096);
3417
3418 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3419 &rx_ring->dma, GFP_KERNEL);
3420 if (!rx_ring->desc)
3421 goto err;
3422
3423 rx_ring->next_to_alloc = 0;
3424 rx_ring->next_to_clean = 0;
3425 rx_ring->next_to_use = 0;
3426
3427 return 0;
3428
3429 err:
3430 vfree(rx_ring->rx_buffer_info);
3431 rx_ring->rx_buffer_info = NULL;
3432 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3433 return -ENOMEM;
3434 }
3435
3436 /**
3437 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3438 * (Descriptors) for all queues
3439 * @adapter: board private structure
3440 *
3441 * Return 0 on success, negative on failure
3442 **/
3443 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3444 {
3445 struct pci_dev *pdev = adapter->pdev;
3446 int i, err = 0;
3447
3448 for (i = 0; i < adapter->num_rx_queues; i++) {
3449 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3450 if (err) {
3451 dev_err(&pdev->dev,
3452 "Allocation for Rx Queue %u failed\n", i);
3453 for (i--; i >= 0; i--)
3454 igb_free_rx_resources(adapter->rx_ring[i]);
3455 break;
3456 }
3457 }
3458
3459 return err;
3460 }
3461
3462 /**
3463 * igb_setup_mrqc - configure the multiple receive queue control registers
3464 * @adapter: Board private structure
3465 **/
3466 static void igb_setup_mrqc(struct igb_adapter *adapter)
3467 {
3468 struct e1000_hw *hw = &adapter->hw;
3469 u32 mrqc, rxcsum;
3470 u32 j, num_rx_queues;
3471 u32 rss_key[10];
3472
3473 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3474 for (j = 0; j < 10; j++)
3475 wr32(E1000_RSSRK(j), rss_key[j]);
3476
3477 num_rx_queues = adapter->rss_queues;
3478
3479 switch (hw->mac.type) {
3480 case e1000_82576:
3481 /* 82576 supports 2 RSS queues for SR-IOV */
3482 if (adapter->vfs_allocated_count)
3483 num_rx_queues = 2;
3484 break;
3485 default:
3486 break;
3487 }
3488
3489 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3490 for (j = 0; j < IGB_RETA_SIZE; j++)
3491 adapter->rss_indir_tbl[j] =
3492 (j * num_rx_queues) / IGB_RETA_SIZE;
3493 adapter->rss_indir_tbl_init = num_rx_queues;
3494 }
3495 igb_write_rss_indir_tbl(adapter);
3496
3497 /* Disable raw packet checksumming so that RSS hash is placed in
3498 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3499 * offloads as they are enabled by default
3500 */
3501 rxcsum = rd32(E1000_RXCSUM);
3502 rxcsum |= E1000_RXCSUM_PCSD;
3503
3504 if (adapter->hw.mac.type >= e1000_82576)
3505 /* Enable Receive Checksum Offload for SCTP */
3506 rxcsum |= E1000_RXCSUM_CRCOFL;
3507
3508 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3509 wr32(E1000_RXCSUM, rxcsum);
3510
3511 /* Generate RSS hash based on packet types, TCP/UDP
3512 * port numbers and/or IPv4/v6 src and dst addresses
3513 */
3514 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3515 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3516 E1000_MRQC_RSS_FIELD_IPV6 |
3517 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3518 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3519
3520 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3521 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3522 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3523 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3524
3525 /* If VMDq is enabled then we set the appropriate mode for that, else
3526 * we default to RSS so that an RSS hash is calculated per packet even
3527 * if we are only using one queue
3528 */
3529 if (adapter->vfs_allocated_count) {
3530 if (hw->mac.type > e1000_82575) {
3531 /* Set the default pool for the PF's first queue */
3532 u32 vtctl = rd32(E1000_VT_CTL);
3533
3534 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3535 E1000_VT_CTL_DISABLE_DEF_POOL);
3536 vtctl |= adapter->vfs_allocated_count <<
3537 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3538 wr32(E1000_VT_CTL, vtctl);
3539 }
3540 if (adapter->rss_queues > 1)
3541 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
3542 else
3543 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3544 } else {
3545 if (hw->mac.type != e1000_i211)
3546 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
3547 }
3548 igb_vmm_control(adapter);
3549
3550 wr32(E1000_MRQC, mrqc);
3551 }
3552
3553 /**
3554 * igb_setup_rctl - configure the receive control registers
3555 * @adapter: Board private structure
3556 **/
3557 void igb_setup_rctl(struct igb_adapter *adapter)
3558 {
3559 struct e1000_hw *hw = &adapter->hw;
3560 u32 rctl;
3561
3562 rctl = rd32(E1000_RCTL);
3563
3564 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3565 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3566
3567 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3568 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3569
3570 /* enable stripping of CRC. It's unlikely this will break BMC
3571 * redirection as it did with e1000. Newer features require
3572 * that the HW strips the CRC.
3573 */
3574 rctl |= E1000_RCTL_SECRC;
3575
3576 /* disable store bad packets and clear size bits. */
3577 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3578
3579 /* enable LPE to allow for reception of jumbo frames */
3580 rctl |= E1000_RCTL_LPE;
3581
3582 /* disable queue 0 to prevent tail write w/o re-config */
3583 wr32(E1000_RXDCTL(0), 0);
3584
3585 /* Attention!!! For SR-IOV PF driver operations you must enable
3586 * queue drop for all VF and PF queues to prevent head of line blocking
3587 * if an un-trusted VF does not provide descriptors to hardware.
3588 */
3589 if (adapter->vfs_allocated_count) {
3590 /* set all queue drop enable bits */
3591 wr32(E1000_QDE, ALL_QUEUES);
3592 }
3593
3594 /* This is useful for sniffing bad packets. */
3595 if (adapter->netdev->features & NETIF_F_RXALL) {
3596 /* UPE and MPE will be handled by normal PROMISC logic
3597 * in e1000e_set_rx_mode
3598 */
3599 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3600 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3601 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3602
3603 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
3604 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3605 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3606 * and that breaks VLANs.
3607 */
3608 }
3609
3610 wr32(E1000_RCTL, rctl);
3611 }
3612
3613 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3614 int vfn)
3615 {
3616 struct e1000_hw *hw = &adapter->hw;
3617 u32 vmolr;
3618
3619 if (size > MAX_JUMBO_FRAME_SIZE)
3620 size = MAX_JUMBO_FRAME_SIZE;
3621
3622 vmolr = rd32(E1000_VMOLR(vfn));
3623 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3624 vmolr |= size | E1000_VMOLR_LPE;
3625 wr32(E1000_VMOLR(vfn), vmolr);
3626
3627 return 0;
3628 }
3629
3630 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
3631 int vfn, bool enable)
3632 {
3633 struct e1000_hw *hw = &adapter->hw;
3634 u32 val, reg;
3635
3636 if (hw->mac.type < e1000_82576)
3637 return;
3638
3639 if (hw->mac.type == e1000_i350)
3640 reg = E1000_DVMOLR(vfn);
3641 else
3642 reg = E1000_VMOLR(vfn);
3643
3644 val = rd32(reg);
3645 if (enable)
3646 val |= E1000_VMOLR_STRVLAN;
3647 else
3648 val &= ~(E1000_VMOLR_STRVLAN);
3649 wr32(reg, val);
3650 }
3651
3652 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3653 int vfn, bool aupe)
3654 {
3655 struct e1000_hw *hw = &adapter->hw;
3656 u32 vmolr;
3657
3658 /* This register exists only on 82576 and newer so if we are older then
3659 * we should exit and do nothing
3660 */
3661 if (hw->mac.type < e1000_82576)
3662 return;
3663
3664 vmolr = rd32(E1000_VMOLR(vfn));
3665 if (aupe)
3666 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3667 else
3668 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3669
3670 /* clear all bits that might not be set */
3671 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3672
3673 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3674 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3675 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3676 * multicast packets
3677 */
3678 if (vfn <= adapter->vfs_allocated_count)
3679 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3680
3681 wr32(E1000_VMOLR(vfn), vmolr);
3682 }
3683
3684 /**
3685 * igb_configure_rx_ring - Configure a receive ring after Reset
3686 * @adapter: board private structure
3687 * @ring: receive ring to be configured
3688 *
3689 * Configure the Rx unit of the MAC after a reset.
3690 **/
3691 void igb_configure_rx_ring(struct igb_adapter *adapter,
3692 struct igb_ring *ring)
3693 {
3694 struct e1000_hw *hw = &adapter->hw;
3695 u64 rdba = ring->dma;
3696 int reg_idx = ring->reg_idx;
3697 u32 srrctl = 0, rxdctl = 0;
3698
3699 /* disable the queue */
3700 wr32(E1000_RXDCTL(reg_idx), 0);
3701
3702 /* Set DMA base address registers */
3703 wr32(E1000_RDBAL(reg_idx),
3704 rdba & 0x00000000ffffffffULL);
3705 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3706 wr32(E1000_RDLEN(reg_idx),
3707 ring->count * sizeof(union e1000_adv_rx_desc));
3708
3709 /* initialize head and tail */
3710 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3711 wr32(E1000_RDH(reg_idx), 0);
3712 writel(0, ring->tail);
3713
3714 /* set descriptor configuration */
3715 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3716 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3717 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3718 if (hw->mac.type >= e1000_82580)
3719 srrctl |= E1000_SRRCTL_TIMESTAMP;
3720 /* Only set Drop Enable if we are supporting multiple queues */
3721 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3722 srrctl |= E1000_SRRCTL_DROP_EN;
3723
3724 wr32(E1000_SRRCTL(reg_idx), srrctl);
3725
3726 /* set filtering for VMDQ pools */
3727 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3728
3729 rxdctl |= IGB_RX_PTHRESH;
3730 rxdctl |= IGB_RX_HTHRESH << 8;
3731 rxdctl |= IGB_RX_WTHRESH << 16;
3732
3733 /* enable receive descriptor fetching */
3734 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3735 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3736 }
3737
3738 /**
3739 * igb_configure_rx - Configure receive Unit after Reset
3740 * @adapter: board private structure
3741 *
3742 * Configure the Rx unit of the MAC after a reset.
3743 **/
3744 static void igb_configure_rx(struct igb_adapter *adapter)
3745 {
3746 int i;
3747
3748 /* set the correct pool for the PF default MAC address in entry 0 */
3749 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3750 adapter->vfs_allocated_count);
3751
3752 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3753 * the Base and Length of the Rx Descriptor Ring
3754 */
3755 for (i = 0; i < adapter->num_rx_queues; i++)
3756 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3757 }
3758
3759 /**
3760 * igb_free_tx_resources - Free Tx Resources per Queue
3761 * @tx_ring: Tx descriptor ring for a specific queue
3762 *
3763 * Free all transmit software resources
3764 **/
3765 void igb_free_tx_resources(struct igb_ring *tx_ring)
3766 {
3767 igb_clean_tx_ring(tx_ring);
3768
3769 vfree(tx_ring->tx_buffer_info);
3770 tx_ring->tx_buffer_info = NULL;
3771
3772 /* if not set, then don't free */
3773 if (!tx_ring->desc)
3774 return;
3775
3776 dma_free_coherent(tx_ring->dev, tx_ring->size,
3777 tx_ring->desc, tx_ring->dma);
3778
3779 tx_ring->desc = NULL;
3780 }
3781
3782 /**
3783 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3784 * @adapter: board private structure
3785 *
3786 * Free all transmit software resources
3787 **/
3788 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3789 {
3790 int i;
3791
3792 for (i = 0; i < adapter->num_tx_queues; i++)
3793 if (adapter->tx_ring[i])
3794 igb_free_tx_resources(adapter->tx_ring[i]);
3795 }
3796
3797 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3798 struct igb_tx_buffer *tx_buffer)
3799 {
3800 if (tx_buffer->skb) {
3801 dev_kfree_skb_any(tx_buffer->skb);
3802 if (dma_unmap_len(tx_buffer, len))
3803 dma_unmap_single(ring->dev,
3804 dma_unmap_addr(tx_buffer, dma),
3805 dma_unmap_len(tx_buffer, len),
3806 DMA_TO_DEVICE);
3807 } else if (dma_unmap_len(tx_buffer, len)) {
3808 dma_unmap_page(ring->dev,
3809 dma_unmap_addr(tx_buffer, dma),
3810 dma_unmap_len(tx_buffer, len),
3811 DMA_TO_DEVICE);
3812 }
3813 tx_buffer->next_to_watch = NULL;
3814 tx_buffer->skb = NULL;
3815 dma_unmap_len_set(tx_buffer, len, 0);
3816 /* buffer_info must be completely set up in the transmit path */
3817 }
3818
3819 /**
3820 * igb_clean_tx_ring - Free Tx Buffers
3821 * @tx_ring: ring to be cleaned
3822 **/
3823 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3824 {
3825 struct igb_tx_buffer *buffer_info;
3826 unsigned long size;
3827 u16 i;
3828
3829 if (!tx_ring->tx_buffer_info)
3830 return;
3831 /* Free all the Tx ring sk_buffs */
3832
3833 for (i = 0; i < tx_ring->count; i++) {
3834 buffer_info = &tx_ring->tx_buffer_info[i];
3835 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3836 }
3837
3838 netdev_tx_reset_queue(txring_txq(tx_ring));
3839
3840 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3841 memset(tx_ring->tx_buffer_info, 0, size);
3842
3843 /* Zero out the descriptor ring */
3844 memset(tx_ring->desc, 0, tx_ring->size);
3845
3846 tx_ring->next_to_use = 0;
3847 tx_ring->next_to_clean = 0;
3848 }
3849
3850 /**
3851 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3852 * @adapter: board private structure
3853 **/
3854 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3855 {
3856 int i;
3857
3858 for (i = 0; i < adapter->num_tx_queues; i++)
3859 if (adapter->tx_ring[i])
3860 igb_clean_tx_ring(adapter->tx_ring[i]);
3861 }
3862
3863 /**
3864 * igb_free_rx_resources - Free Rx Resources
3865 * @rx_ring: ring to clean the resources from
3866 *
3867 * Free all receive software resources
3868 **/
3869 void igb_free_rx_resources(struct igb_ring *rx_ring)
3870 {
3871 igb_clean_rx_ring(rx_ring);
3872
3873 vfree(rx_ring->rx_buffer_info);
3874 rx_ring->rx_buffer_info = NULL;
3875
3876 /* if not set, then don't free */
3877 if (!rx_ring->desc)
3878 return;
3879
3880 dma_free_coherent(rx_ring->dev, rx_ring->size,
3881 rx_ring->desc, rx_ring->dma);
3882
3883 rx_ring->desc = NULL;
3884 }
3885
3886 /**
3887 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3888 * @adapter: board private structure
3889 *
3890 * Free all receive software resources
3891 **/
3892 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3893 {
3894 int i;
3895
3896 for (i = 0; i < adapter->num_rx_queues; i++)
3897 if (adapter->rx_ring[i])
3898 igb_free_rx_resources(adapter->rx_ring[i]);
3899 }
3900
3901 /**
3902 * igb_clean_rx_ring - Free Rx Buffers per Queue
3903 * @rx_ring: ring to free buffers from
3904 **/
3905 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3906 {
3907 unsigned long size;
3908 u16 i;
3909
3910 if (rx_ring->skb)
3911 dev_kfree_skb(rx_ring->skb);
3912 rx_ring->skb = NULL;
3913
3914 if (!rx_ring->rx_buffer_info)
3915 return;
3916
3917 /* Free all the Rx ring sk_buffs */
3918 for (i = 0; i < rx_ring->count; i++) {
3919 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3920
3921 if (!buffer_info->page)
3922 continue;
3923
3924 dma_unmap_page(rx_ring->dev,
3925 buffer_info->dma,
3926 PAGE_SIZE,
3927 DMA_FROM_DEVICE);
3928 __free_page(buffer_info->page);
3929
3930 buffer_info->page = NULL;
3931 }
3932
3933 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3934 memset(rx_ring->rx_buffer_info, 0, size);
3935
3936 /* Zero out the descriptor ring */
3937 memset(rx_ring->desc, 0, rx_ring->size);
3938
3939 rx_ring->next_to_alloc = 0;
3940 rx_ring->next_to_clean = 0;
3941 rx_ring->next_to_use = 0;
3942 }
3943
3944 /**
3945 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3946 * @adapter: board private structure
3947 **/
3948 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3949 {
3950 int i;
3951
3952 for (i = 0; i < adapter->num_rx_queues; i++)
3953 if (adapter->rx_ring[i])
3954 igb_clean_rx_ring(adapter->rx_ring[i]);
3955 }
3956
3957 /**
3958 * igb_set_mac - Change the Ethernet Address of the NIC
3959 * @netdev: network interface device structure
3960 * @p: pointer to an address structure
3961 *
3962 * Returns 0 on success, negative on failure
3963 **/
3964 static int igb_set_mac(struct net_device *netdev, void *p)
3965 {
3966 struct igb_adapter *adapter = netdev_priv(netdev);
3967 struct e1000_hw *hw = &adapter->hw;
3968 struct sockaddr *addr = p;
3969
3970 if (!is_valid_ether_addr(addr->sa_data))
3971 return -EADDRNOTAVAIL;
3972
3973 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3974 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3975
3976 /* set the correct pool for the new PF MAC address in entry 0 */
3977 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3978 adapter->vfs_allocated_count);
3979
3980 return 0;
3981 }
3982
3983 /**
3984 * igb_write_mc_addr_list - write multicast addresses to MTA
3985 * @netdev: network interface device structure
3986 *
3987 * Writes multicast address list to the MTA hash table.
3988 * Returns: -ENOMEM on failure
3989 * 0 on no addresses written
3990 * X on writing X addresses to MTA
3991 **/
3992 static int igb_write_mc_addr_list(struct net_device *netdev)
3993 {
3994 struct igb_adapter *adapter = netdev_priv(netdev);
3995 struct e1000_hw *hw = &adapter->hw;
3996 struct netdev_hw_addr *ha;
3997 u8 *mta_list;
3998 int i;
3999
4000 if (netdev_mc_empty(netdev)) {
4001 /* nothing to program, so clear mc list */
4002 igb_update_mc_addr_list(hw, NULL, 0);
4003 igb_restore_vf_multicasts(adapter);
4004 return 0;
4005 }
4006
4007 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
4008 if (!mta_list)
4009 return -ENOMEM;
4010
4011 /* The shared function expects a packed array of only addresses. */
4012 i = 0;
4013 netdev_for_each_mc_addr(ha, netdev)
4014 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
4015
4016 igb_update_mc_addr_list(hw, mta_list, i);
4017 kfree(mta_list);
4018
4019 return netdev_mc_count(netdev);
4020 }
4021
4022 /**
4023 * igb_write_uc_addr_list - write unicast addresses to RAR table
4024 * @netdev: network interface device structure
4025 *
4026 * Writes unicast address list to the RAR table.
4027 * Returns: -ENOMEM on failure/insufficient address space
4028 * 0 on no addresses written
4029 * X on writing X addresses to the RAR table
4030 **/
4031 static int igb_write_uc_addr_list(struct net_device *netdev)
4032 {
4033 struct igb_adapter *adapter = netdev_priv(netdev);
4034 struct e1000_hw *hw = &adapter->hw;
4035 unsigned int vfn = adapter->vfs_allocated_count;
4036 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
4037 int count = 0;
4038
4039 /* return ENOMEM indicating insufficient memory for addresses */
4040 if (netdev_uc_count(netdev) > rar_entries)
4041 return -ENOMEM;
4042
4043 if (!netdev_uc_empty(netdev) && rar_entries) {
4044 struct netdev_hw_addr *ha;
4045
4046 netdev_for_each_uc_addr(ha, netdev) {
4047 if (!rar_entries)
4048 break;
4049 igb_rar_set_qsel(adapter, ha->addr,
4050 rar_entries--,
4051 vfn);
4052 count++;
4053 }
4054 }
4055 /* write the addresses in reverse order to avoid write combining */
4056 for (; rar_entries > 0 ; rar_entries--) {
4057 wr32(E1000_RAH(rar_entries), 0);
4058 wr32(E1000_RAL(rar_entries), 0);
4059 }
4060 wrfl();
4061
4062 return count;
4063 }
4064
4065 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4066 {
4067 struct e1000_hw *hw = &adapter->hw;
4068 u32 i, pf_id;
4069
4070 switch (hw->mac.type) {
4071 case e1000_i210:
4072 case e1000_i211:
4073 case e1000_i350:
4074 /* VLAN filtering needed for VLAN prio filter */
4075 if (adapter->netdev->features & NETIF_F_NTUPLE)
4076 break;
4077 /* fall through */
4078 case e1000_82576:
4079 case e1000_82580:
4080 case e1000_i354:
4081 /* VLAN filtering needed for pool filtering */
4082 if (adapter->vfs_allocated_count)
4083 break;
4084 /* fall through */
4085 default:
4086 return 1;
4087 }
4088
4089 /* We are already in VLAN promisc, nothing to do */
4090 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4091 return 0;
4092
4093 if (!adapter->vfs_allocated_count)
4094 goto set_vfta;
4095
4096 /* Add PF to all active pools */
4097 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4098
4099 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4100 u32 vlvf = rd32(E1000_VLVF(i));
4101
4102 vlvf |= BIT(pf_id);
4103 wr32(E1000_VLVF(i), vlvf);
4104 }
4105
4106 set_vfta:
4107 /* Set all bits in the VLAN filter table array */
4108 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4109 hw->mac.ops.write_vfta(hw, i, ~0U);
4110
4111 /* Set flag so we don't redo unnecessary work */
4112 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4113
4114 return 0;
4115 }
4116
4117 #define VFTA_BLOCK_SIZE 8
4118 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4119 {
4120 struct e1000_hw *hw = &adapter->hw;
4121 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4122 u32 vid_start = vfta_offset * 32;
4123 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4124 u32 i, vid, word, bits, pf_id;
4125
4126 /* guarantee that we don't scrub out management VLAN */
4127 vid = adapter->mng_vlan_id;
4128 if (vid >= vid_start && vid < vid_end)
4129 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4130
4131 if (!adapter->vfs_allocated_count)
4132 goto set_vfta;
4133
4134 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4135
4136 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4137 u32 vlvf = rd32(E1000_VLVF(i));
4138
4139 /* pull VLAN ID from VLVF */
4140 vid = vlvf & VLAN_VID_MASK;
4141
4142 /* only concern ourselves with a certain range */
4143 if (vid < vid_start || vid >= vid_end)
4144 continue;
4145
4146 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4147 /* record VLAN ID in VFTA */
4148 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4149
4150 /* if PF is part of this then continue */
4151 if (test_bit(vid, adapter->active_vlans))
4152 continue;
4153 }
4154
4155 /* remove PF from the pool */
4156 bits = ~BIT(pf_id);
4157 bits &= rd32(E1000_VLVF(i));
4158 wr32(E1000_VLVF(i), bits);
4159 }
4160
4161 set_vfta:
4162 /* extract values from active_vlans and write back to VFTA */
4163 for (i = VFTA_BLOCK_SIZE; i--;) {
4164 vid = (vfta_offset + i) * 32;
4165 word = vid / BITS_PER_LONG;
4166 bits = vid % BITS_PER_LONG;
4167
4168 vfta[i] |= adapter->active_vlans[word] >> bits;
4169
4170 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4171 }
4172 }
4173
4174 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4175 {
4176 u32 i;
4177
4178 /* We are not in VLAN promisc, nothing to do */
4179 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4180 return;
4181
4182 /* Set flag so we don't redo unnecessary work */
4183 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4184
4185 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4186 igb_scrub_vfta(adapter, i);
4187 }
4188
4189 /**
4190 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4191 * @netdev: network interface device structure
4192 *
4193 * The set_rx_mode entry point is called whenever the unicast or multicast
4194 * address lists or the network interface flags are updated. This routine is
4195 * responsible for configuring the hardware for proper unicast, multicast,
4196 * promiscuous mode, and all-multi behavior.
4197 **/
4198 static void igb_set_rx_mode(struct net_device *netdev)
4199 {
4200 struct igb_adapter *adapter = netdev_priv(netdev);
4201 struct e1000_hw *hw = &adapter->hw;
4202 unsigned int vfn = adapter->vfs_allocated_count;
4203 u32 rctl = 0, vmolr = 0;
4204 int count;
4205
4206 /* Check for Promiscuous and All Multicast modes */
4207 if (netdev->flags & IFF_PROMISC) {
4208 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
4209 vmolr |= E1000_VMOLR_MPME;
4210
4211 /* enable use of UTA filter to force packets to default pool */
4212 if (hw->mac.type == e1000_82576)
4213 vmolr |= E1000_VMOLR_ROPE;
4214 } else {
4215 if (netdev->flags & IFF_ALLMULTI) {
4216 rctl |= E1000_RCTL_MPE;
4217 vmolr |= E1000_VMOLR_MPME;
4218 } else {
4219 /* Write addresses to the MTA, if the attempt fails
4220 * then we should just turn on promiscuous mode so
4221 * that we can at least receive multicast traffic
4222 */
4223 count = igb_write_mc_addr_list(netdev);
4224 if (count < 0) {
4225 rctl |= E1000_RCTL_MPE;
4226 vmolr |= E1000_VMOLR_MPME;
4227 } else if (count) {
4228 vmolr |= E1000_VMOLR_ROMPE;
4229 }
4230 }
4231 }
4232
4233 /* Write addresses to available RAR registers, if there is not
4234 * sufficient space to store all the addresses then enable
4235 * unicast promiscuous mode
4236 */
4237 count = igb_write_uc_addr_list(netdev);
4238 if (count < 0) {
4239 rctl |= E1000_RCTL_UPE;
4240 vmolr |= E1000_VMOLR_ROPE;
4241 }
4242
4243 /* enable VLAN filtering by default */
4244 rctl |= E1000_RCTL_VFE;
4245
4246 /* disable VLAN filtering for modes that require it */
4247 if ((netdev->flags & IFF_PROMISC) ||
4248 (netdev->features & NETIF_F_RXALL)) {
4249 /* if we fail to set all rules then just clear VFE */
4250 if (igb_vlan_promisc_enable(adapter))
4251 rctl &= ~E1000_RCTL_VFE;
4252 } else {
4253 igb_vlan_promisc_disable(adapter);
4254 }
4255
4256 /* update state of unicast, multicast, and VLAN filtering modes */
4257 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4258 E1000_RCTL_VFE);
4259 wr32(E1000_RCTL, rctl);
4260
4261 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4262 * the VMOLR to enable the appropriate modes. Without this workaround
4263 * we will have issues with VLAN tag stripping not being done for frames
4264 * that are only arriving because we are the default pool
4265 */
4266 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4267 return;
4268
4269 /* set UTA to appropriate mode */
4270 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4271
4272 vmolr |= rd32(E1000_VMOLR(vfn)) &
4273 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4274
4275 /* enable Rx jumbo frames, no need for restriction */
4276 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4277 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4278
4279 wr32(E1000_VMOLR(vfn), vmolr);
4280 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4281
4282 igb_restore_vf_multicasts(adapter);
4283 }
4284
4285 static void igb_check_wvbr(struct igb_adapter *adapter)
4286 {
4287 struct e1000_hw *hw = &adapter->hw;
4288 u32 wvbr = 0;
4289
4290 switch (hw->mac.type) {
4291 case e1000_82576:
4292 case e1000_i350:
4293 wvbr = rd32(E1000_WVBR);
4294 if (!wvbr)
4295 return;
4296 break;
4297 default:
4298 break;
4299 }
4300
4301 adapter->wvbr |= wvbr;
4302 }
4303
4304 #define IGB_STAGGERED_QUEUE_OFFSET 8
4305
4306 static void igb_spoof_check(struct igb_adapter *adapter)
4307 {
4308 int j;
4309
4310 if (!adapter->wvbr)
4311 return;
4312
4313 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4314 if (adapter->wvbr & BIT(j) ||
4315 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
4316 dev_warn(&adapter->pdev->dev,
4317 "Spoof event(s) detected on VF %d\n", j);
4318 adapter->wvbr &=
4319 ~(BIT(j) |
4320 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
4321 }
4322 }
4323 }
4324
4325 /* Need to wait a few seconds after link up to get diagnostic information from
4326 * the phy
4327 */
4328 static void igb_update_phy_info(unsigned long data)
4329 {
4330 struct igb_adapter *adapter = (struct igb_adapter *) data;
4331 igb_get_phy_info(&adapter->hw);
4332 }
4333
4334 /**
4335 * igb_has_link - check shared code for link and determine up/down
4336 * @adapter: pointer to driver private info
4337 **/
4338 bool igb_has_link(struct igb_adapter *adapter)
4339 {
4340 struct e1000_hw *hw = &adapter->hw;
4341 bool link_active = false;
4342
4343 /* get_link_status is set on LSC (link status) interrupt or
4344 * rx sequence error interrupt. get_link_status will stay
4345 * false until the e1000_check_for_link establishes link
4346 * for copper adapters ONLY
4347 */
4348 switch (hw->phy.media_type) {
4349 case e1000_media_type_copper:
4350 if (!hw->mac.get_link_status)
4351 return true;
4352 case e1000_media_type_internal_serdes:
4353 hw->mac.ops.check_for_link(hw);
4354 link_active = !hw->mac.get_link_status;
4355 break;
4356 default:
4357 case e1000_media_type_unknown:
4358 break;
4359 }
4360
4361 if (((hw->mac.type == e1000_i210) ||
4362 (hw->mac.type == e1000_i211)) &&
4363 (hw->phy.id == I210_I_PHY_ID)) {
4364 if (!netif_carrier_ok(adapter->netdev)) {
4365 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4366 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4367 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4368 adapter->link_check_timeout = jiffies;
4369 }
4370 }
4371
4372 return link_active;
4373 }
4374
4375 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4376 {
4377 bool ret = false;
4378 u32 ctrl_ext, thstat;
4379
4380 /* check for thermal sensor event on i350 copper only */
4381 if (hw->mac.type == e1000_i350) {
4382 thstat = rd32(E1000_THSTAT);
4383 ctrl_ext = rd32(E1000_CTRL_EXT);
4384
4385 if ((hw->phy.media_type == e1000_media_type_copper) &&
4386 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4387 ret = !!(thstat & event);
4388 }
4389
4390 return ret;
4391 }
4392
4393 /**
4394 * igb_check_lvmmc - check for malformed packets received
4395 * and indicated in LVMMC register
4396 * @adapter: pointer to adapter
4397 **/
4398 static void igb_check_lvmmc(struct igb_adapter *adapter)
4399 {
4400 struct e1000_hw *hw = &adapter->hw;
4401 u32 lvmmc;
4402
4403 lvmmc = rd32(E1000_LVMMC);
4404 if (lvmmc) {
4405 if (unlikely(net_ratelimit())) {
4406 netdev_warn(adapter->netdev,
4407 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4408 lvmmc);
4409 }
4410 }
4411 }
4412
4413 /**
4414 * igb_watchdog - Timer Call-back
4415 * @data: pointer to adapter cast into an unsigned long
4416 **/
4417 static void igb_watchdog(unsigned long data)
4418 {
4419 struct igb_adapter *adapter = (struct igb_adapter *)data;
4420 /* Do the rest outside of interrupt context */
4421 schedule_work(&adapter->watchdog_task);
4422 }
4423
4424 static void igb_watchdog_task(struct work_struct *work)
4425 {
4426 struct igb_adapter *adapter = container_of(work,
4427 struct igb_adapter,
4428 watchdog_task);
4429 struct e1000_hw *hw = &adapter->hw;
4430 struct e1000_phy_info *phy = &hw->phy;
4431 struct net_device *netdev = adapter->netdev;
4432 u32 link;
4433 int i;
4434 u32 connsw;
4435 u16 phy_data, retry_count = 20;
4436
4437 link = igb_has_link(adapter);
4438
4439 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4440 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4441 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4442 else
4443 link = false;
4444 }
4445
4446 /* Force link down if we have fiber to swap to */
4447 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4448 if (hw->phy.media_type == e1000_media_type_copper) {
4449 connsw = rd32(E1000_CONNSW);
4450 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4451 link = 0;
4452 }
4453 }
4454 if (link) {
4455 /* Perform a reset if the media type changed. */
4456 if (hw->dev_spec._82575.media_changed) {
4457 hw->dev_spec._82575.media_changed = false;
4458 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4459 igb_reset(adapter);
4460 }
4461 /* Cancel scheduled suspend requests. */
4462 pm_runtime_resume(netdev->dev.parent);
4463
4464 if (!netif_carrier_ok(netdev)) {
4465 u32 ctrl;
4466
4467 hw->mac.ops.get_speed_and_duplex(hw,
4468 &adapter->link_speed,
4469 &adapter->link_duplex);
4470
4471 ctrl = rd32(E1000_CTRL);
4472 /* Links status message must follow this format */
4473 netdev_info(netdev,
4474 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4475 netdev->name,
4476 adapter->link_speed,
4477 adapter->link_duplex == FULL_DUPLEX ?
4478 "Full" : "Half",
4479 (ctrl & E1000_CTRL_TFCE) &&
4480 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4481 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4482 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4483
4484 /* disable EEE if enabled */
4485 if ((adapter->flags & IGB_FLAG_EEE) &&
4486 (adapter->link_duplex == HALF_DUPLEX)) {
4487 dev_info(&adapter->pdev->dev,
4488 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4489 adapter->hw.dev_spec._82575.eee_disable = true;
4490 adapter->flags &= ~IGB_FLAG_EEE;
4491 }
4492
4493 /* check if SmartSpeed worked */
4494 igb_check_downshift(hw);
4495 if (phy->speed_downgraded)
4496 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4497
4498 /* check for thermal sensor event */
4499 if (igb_thermal_sensor_event(hw,
4500 E1000_THSTAT_LINK_THROTTLE))
4501 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4502
4503 /* adjust timeout factor according to speed/duplex */
4504 adapter->tx_timeout_factor = 1;
4505 switch (adapter->link_speed) {
4506 case SPEED_10:
4507 adapter->tx_timeout_factor = 14;
4508 break;
4509 case SPEED_100:
4510 /* maybe add some timeout factor ? */
4511 break;
4512 }
4513
4514 if (adapter->link_speed != SPEED_1000)
4515 goto no_wait;
4516
4517 /* wait for Remote receiver status OK */
4518 retry_read_status:
4519 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
4520 &phy_data)) {
4521 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4522 retry_count) {
4523 msleep(100);
4524 retry_count--;
4525 goto retry_read_status;
4526 } else if (!retry_count) {
4527 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
4528 }
4529 } else {
4530 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
4531 }
4532 no_wait:
4533 netif_carrier_on(netdev);
4534
4535 igb_ping_all_vfs(adapter);
4536 igb_check_vf_rate_limit(adapter);
4537
4538 /* link state has changed, schedule phy info update */
4539 if (!test_bit(__IGB_DOWN, &adapter->state))
4540 mod_timer(&adapter->phy_info_timer,
4541 round_jiffies(jiffies + 2 * HZ));
4542 }
4543 } else {
4544 if (netif_carrier_ok(netdev)) {
4545 adapter->link_speed = 0;
4546 adapter->link_duplex = 0;
4547
4548 /* check for thermal sensor event */
4549 if (igb_thermal_sensor_event(hw,
4550 E1000_THSTAT_PWR_DOWN)) {
4551 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4552 }
4553
4554 /* Links status message must follow this format */
4555 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4556 netdev->name);
4557 netif_carrier_off(netdev);
4558
4559 igb_ping_all_vfs(adapter);
4560
4561 /* link state has changed, schedule phy info update */
4562 if (!test_bit(__IGB_DOWN, &adapter->state))
4563 mod_timer(&adapter->phy_info_timer,
4564 round_jiffies(jiffies + 2 * HZ));
4565
4566 /* link is down, time to check for alternate media */
4567 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4568 igb_check_swap_media(adapter);
4569 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4570 schedule_work(&adapter->reset_task);
4571 /* return immediately */
4572 return;
4573 }
4574 }
4575 pm_schedule_suspend(netdev->dev.parent,
4576 MSEC_PER_SEC * 5);
4577
4578 /* also check for alternate media here */
4579 } else if (!netif_carrier_ok(netdev) &&
4580 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4581 igb_check_swap_media(adapter);
4582 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4583 schedule_work(&adapter->reset_task);
4584 /* return immediately */
4585 return;
4586 }
4587 }
4588 }
4589
4590 spin_lock(&adapter->stats64_lock);
4591 igb_update_stats(adapter, &adapter->stats64);
4592 spin_unlock(&adapter->stats64_lock);
4593
4594 for (i = 0; i < adapter->num_tx_queues; i++) {
4595 struct igb_ring *tx_ring = adapter->tx_ring[i];
4596 if (!netif_carrier_ok(netdev)) {
4597 /* We've lost link, so the controller stops DMA,
4598 * but we've got queued Tx work that's never going
4599 * to get done, so reset controller to flush Tx.
4600 * (Do the reset outside of interrupt context).
4601 */
4602 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4603 adapter->tx_timeout_count++;
4604 schedule_work(&adapter->reset_task);
4605 /* return immediately since reset is imminent */
4606 return;
4607 }
4608 }
4609
4610 /* Force detection of hung controller every watchdog period */
4611 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4612 }
4613
4614 /* Cause software interrupt to ensure Rx ring is cleaned */
4615 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4616 u32 eics = 0;
4617
4618 for (i = 0; i < adapter->num_q_vectors; i++)
4619 eics |= adapter->q_vector[i]->eims_value;
4620 wr32(E1000_EICS, eics);
4621 } else {
4622 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4623 }
4624
4625 igb_spoof_check(adapter);
4626 igb_ptp_rx_hang(adapter);
4627
4628 /* Check LVMMC register on i350/i354 only */
4629 if ((adapter->hw.mac.type == e1000_i350) ||
4630 (adapter->hw.mac.type == e1000_i354))
4631 igb_check_lvmmc(adapter);
4632
4633 /* Reset the timer */
4634 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4635 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4636 mod_timer(&adapter->watchdog_timer,
4637 round_jiffies(jiffies + HZ));
4638 else
4639 mod_timer(&adapter->watchdog_timer,
4640 round_jiffies(jiffies + 2 * HZ));
4641 }
4642 }
4643
4644 enum latency_range {
4645 lowest_latency = 0,
4646 low_latency = 1,
4647 bulk_latency = 2,
4648 latency_invalid = 255
4649 };
4650
4651 /**
4652 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4653 * @q_vector: pointer to q_vector
4654 *
4655 * Stores a new ITR value based on strictly on packet size. This
4656 * algorithm is less sophisticated than that used in igb_update_itr,
4657 * due to the difficulty of synchronizing statistics across multiple
4658 * receive rings. The divisors and thresholds used by this function
4659 * were determined based on theoretical maximum wire speed and testing
4660 * data, in order to minimize response time while increasing bulk
4661 * throughput.
4662 * This functionality is controlled by ethtool's coalescing settings.
4663 * NOTE: This function is called only when operating in a multiqueue
4664 * receive environment.
4665 **/
4666 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4667 {
4668 int new_val = q_vector->itr_val;
4669 int avg_wire_size = 0;
4670 struct igb_adapter *adapter = q_vector->adapter;
4671 unsigned int packets;
4672
4673 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4674 * ints/sec - ITR timer value of 120 ticks.
4675 */
4676 if (adapter->link_speed != SPEED_1000) {
4677 new_val = IGB_4K_ITR;
4678 goto set_itr_val;
4679 }
4680
4681 packets = q_vector->rx.total_packets;
4682 if (packets)
4683 avg_wire_size = q_vector->rx.total_bytes / packets;
4684
4685 packets = q_vector->tx.total_packets;
4686 if (packets)
4687 avg_wire_size = max_t(u32, avg_wire_size,
4688 q_vector->tx.total_bytes / packets);
4689
4690 /* if avg_wire_size isn't set no work was done */
4691 if (!avg_wire_size)
4692 goto clear_counts;
4693
4694 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4695 avg_wire_size += 24;
4696
4697 /* Don't starve jumbo frames */
4698 avg_wire_size = min(avg_wire_size, 3000);
4699
4700 /* Give a little boost to mid-size frames */
4701 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4702 new_val = avg_wire_size / 3;
4703 else
4704 new_val = avg_wire_size / 2;
4705
4706 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4707 if (new_val < IGB_20K_ITR &&
4708 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4709 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4710 new_val = IGB_20K_ITR;
4711
4712 set_itr_val:
4713 if (new_val != q_vector->itr_val) {
4714 q_vector->itr_val = new_val;
4715 q_vector->set_itr = 1;
4716 }
4717 clear_counts:
4718 q_vector->rx.total_bytes = 0;
4719 q_vector->rx.total_packets = 0;
4720 q_vector->tx.total_bytes = 0;
4721 q_vector->tx.total_packets = 0;
4722 }
4723
4724 /**
4725 * igb_update_itr - update the dynamic ITR value based on statistics
4726 * @q_vector: pointer to q_vector
4727 * @ring_container: ring info to update the itr for
4728 *
4729 * Stores a new ITR value based on packets and byte
4730 * counts during the last interrupt. The advantage of per interrupt
4731 * computation is faster updates and more accurate ITR for the current
4732 * traffic pattern. Constants in this function were computed
4733 * based on theoretical maximum wire speed and thresholds were set based
4734 * on testing data as well as attempting to minimize response time
4735 * while increasing bulk throughput.
4736 * This functionality is controlled by ethtool's coalescing settings.
4737 * NOTE: These calculations are only valid when operating in a single-
4738 * queue environment.
4739 **/
4740 static void igb_update_itr(struct igb_q_vector *q_vector,
4741 struct igb_ring_container *ring_container)
4742 {
4743 unsigned int packets = ring_container->total_packets;
4744 unsigned int bytes = ring_container->total_bytes;
4745 u8 itrval = ring_container->itr;
4746
4747 /* no packets, exit with status unchanged */
4748 if (packets == 0)
4749 return;
4750
4751 switch (itrval) {
4752 case lowest_latency:
4753 /* handle TSO and jumbo frames */
4754 if (bytes/packets > 8000)
4755 itrval = bulk_latency;
4756 else if ((packets < 5) && (bytes > 512))
4757 itrval = low_latency;
4758 break;
4759 case low_latency: /* 50 usec aka 20000 ints/s */
4760 if (bytes > 10000) {
4761 /* this if handles the TSO accounting */
4762 if (bytes/packets > 8000)
4763 itrval = bulk_latency;
4764 else if ((packets < 10) || ((bytes/packets) > 1200))
4765 itrval = bulk_latency;
4766 else if ((packets > 35))
4767 itrval = lowest_latency;
4768 } else if (bytes/packets > 2000) {
4769 itrval = bulk_latency;
4770 } else if (packets <= 2 && bytes < 512) {
4771 itrval = lowest_latency;
4772 }
4773 break;
4774 case bulk_latency: /* 250 usec aka 4000 ints/s */
4775 if (bytes > 25000) {
4776 if (packets > 35)
4777 itrval = low_latency;
4778 } else if (bytes < 1500) {
4779 itrval = low_latency;
4780 }
4781 break;
4782 }
4783
4784 /* clear work counters since we have the values we need */
4785 ring_container->total_bytes = 0;
4786 ring_container->total_packets = 0;
4787
4788 /* write updated itr to ring container */
4789 ring_container->itr = itrval;
4790 }
4791
4792 static void igb_set_itr(struct igb_q_vector *q_vector)
4793 {
4794 struct igb_adapter *adapter = q_vector->adapter;
4795 u32 new_itr = q_vector->itr_val;
4796 u8 current_itr = 0;
4797
4798 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4799 if (adapter->link_speed != SPEED_1000) {
4800 current_itr = 0;
4801 new_itr = IGB_4K_ITR;
4802 goto set_itr_now;
4803 }
4804
4805 igb_update_itr(q_vector, &q_vector->tx);
4806 igb_update_itr(q_vector, &q_vector->rx);
4807
4808 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4809
4810 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4811 if (current_itr == lowest_latency &&
4812 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4813 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4814 current_itr = low_latency;
4815
4816 switch (current_itr) {
4817 /* counts and packets in update_itr are dependent on these numbers */
4818 case lowest_latency:
4819 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4820 break;
4821 case low_latency:
4822 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4823 break;
4824 case bulk_latency:
4825 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4826 break;
4827 default:
4828 break;
4829 }
4830
4831 set_itr_now:
4832 if (new_itr != q_vector->itr_val) {
4833 /* this attempts to bias the interrupt rate towards Bulk
4834 * by adding intermediate steps when interrupt rate is
4835 * increasing
4836 */
4837 new_itr = new_itr > q_vector->itr_val ?
4838 max((new_itr * q_vector->itr_val) /
4839 (new_itr + (q_vector->itr_val >> 2)),
4840 new_itr) : new_itr;
4841 /* Don't write the value here; it resets the adapter's
4842 * internal timer, and causes us to delay far longer than
4843 * we should between interrupts. Instead, we write the ITR
4844 * value at the beginning of the next interrupt so the timing
4845 * ends up being correct.
4846 */
4847 q_vector->itr_val = new_itr;
4848 q_vector->set_itr = 1;
4849 }
4850 }
4851
4852 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4853 u32 type_tucmd, u32 mss_l4len_idx)
4854 {
4855 struct e1000_adv_tx_context_desc *context_desc;
4856 u16 i = tx_ring->next_to_use;
4857
4858 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4859
4860 i++;
4861 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4862
4863 /* set bits to identify this as an advanced context descriptor */
4864 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4865
4866 /* For 82575, context index must be unique per ring. */
4867 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4868 mss_l4len_idx |= tx_ring->reg_idx << 4;
4869
4870 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4871 context_desc->seqnum_seed = 0;
4872 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4873 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4874 }
4875
4876 static int igb_tso(struct igb_ring *tx_ring,
4877 struct igb_tx_buffer *first,
4878 u8 *hdr_len)
4879 {
4880 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
4881 struct sk_buff *skb = first->skb;
4882 union {
4883 struct iphdr *v4;
4884 struct ipv6hdr *v6;
4885 unsigned char *hdr;
4886 } ip;
4887 union {
4888 struct tcphdr *tcp;
4889 unsigned char *hdr;
4890 } l4;
4891 u32 paylen, l4_offset;
4892 int err;
4893
4894 if (skb->ip_summed != CHECKSUM_PARTIAL)
4895 return 0;
4896
4897 if (!skb_is_gso(skb))
4898 return 0;
4899
4900 err = skb_cow_head(skb, 0);
4901 if (err < 0)
4902 return err;
4903
4904 ip.hdr = skb_network_header(skb);
4905 l4.hdr = skb_checksum_start(skb);
4906
4907 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4908 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4909
4910 /* initialize outer IP header fields */
4911 if (ip.v4->version == 4) {
4912 /* IP header will have to cancel out any data that
4913 * is not a part of the outer IP header
4914 */
4915 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
4916 csum_unfold(l4.tcp->check)));
4917 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4918
4919 ip.v4->tot_len = 0;
4920 first->tx_flags |= IGB_TX_FLAGS_TSO |
4921 IGB_TX_FLAGS_CSUM |
4922 IGB_TX_FLAGS_IPV4;
4923 } else {
4924 ip.v6->payload_len = 0;
4925 first->tx_flags |= IGB_TX_FLAGS_TSO |
4926 IGB_TX_FLAGS_CSUM;
4927 }
4928
4929 /* determine offset of inner transport header */
4930 l4_offset = l4.hdr - skb->data;
4931
4932 /* compute length of segmentation header */
4933 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
4934
4935 /* remove payload length from inner checksum */
4936 paylen = skb->len - l4_offset;
4937 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
4938
4939 /* update gso size and bytecount with header size */
4940 first->gso_segs = skb_shinfo(skb)->gso_segs;
4941 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4942
4943 /* MSS L4LEN IDX */
4944 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
4945 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4946
4947 /* VLAN MACLEN IPLEN */
4948 vlan_macip_lens = l4.hdr - ip.hdr;
4949 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
4950 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4951
4952 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4953
4954 return 1;
4955 }
4956
4957 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
4958 {
4959 unsigned int offset = 0;
4960
4961 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
4962
4963 return offset == skb_checksum_start_offset(skb);
4964 }
4965
4966 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4967 {
4968 struct sk_buff *skb = first->skb;
4969 u32 vlan_macip_lens = 0;
4970 u32 type_tucmd = 0;
4971
4972 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4973 csum_failed:
4974 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4975 return;
4976 goto no_csum;
4977 }
4978
4979 switch (skb->csum_offset) {
4980 case offsetof(struct tcphdr, check):
4981 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4982 /* fall through */
4983 case offsetof(struct udphdr, check):
4984 break;
4985 case offsetof(struct sctphdr, checksum):
4986 /* validate that this is actually an SCTP request */
4987 if (((first->protocol == htons(ETH_P_IP)) &&
4988 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
4989 ((first->protocol == htons(ETH_P_IPV6)) &&
4990 igb_ipv6_csum_is_sctp(skb))) {
4991 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
4992 break;
4993 }
4994 default:
4995 skb_checksum_help(skb);
4996 goto csum_failed;
4997 }
4998
4999 /* update TX checksum flag */
5000 first->tx_flags |= IGB_TX_FLAGS_CSUM;
5001 vlan_macip_lens = skb_checksum_start_offset(skb) -
5002 skb_network_offset(skb);
5003 no_csum:
5004 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
5005 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5006
5007 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0);
5008 }
5009
5010 #define IGB_SET_FLAG(_input, _flag, _result) \
5011 ((_flag <= _result) ? \
5012 ((u32)(_input & _flag) * (_result / _flag)) : \
5013 ((u32)(_input & _flag) / (_flag / _result)))
5014
5015 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
5016 {
5017 /* set type for advanced descriptor with frame checksum insertion */
5018 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
5019 E1000_ADVTXD_DCMD_DEXT |
5020 E1000_ADVTXD_DCMD_IFCS;
5021
5022 /* set HW vlan bit if vlan is present */
5023 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
5024 (E1000_ADVTXD_DCMD_VLE));
5025
5026 /* set segmentation bits for TSO */
5027 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
5028 (E1000_ADVTXD_DCMD_TSE));
5029
5030 /* set timestamp bit if present */
5031 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
5032 (E1000_ADVTXD_MAC_TSTAMP));
5033
5034 /* insert frame checksum */
5035 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
5036
5037 return cmd_type;
5038 }
5039
5040 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
5041 union e1000_adv_tx_desc *tx_desc,
5042 u32 tx_flags, unsigned int paylen)
5043 {
5044 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
5045
5046 /* 82575 requires a unique index per ring */
5047 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5048 olinfo_status |= tx_ring->reg_idx << 4;
5049
5050 /* insert L4 checksum */
5051 olinfo_status |= IGB_SET_FLAG(tx_flags,
5052 IGB_TX_FLAGS_CSUM,
5053 (E1000_TXD_POPTS_TXSM << 8));
5054
5055 /* insert IPv4 checksum */
5056 olinfo_status |= IGB_SET_FLAG(tx_flags,
5057 IGB_TX_FLAGS_IPV4,
5058 (E1000_TXD_POPTS_IXSM << 8));
5059
5060 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5061 }
5062
5063 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5064 {
5065 struct net_device *netdev = tx_ring->netdev;
5066
5067 netif_stop_subqueue(netdev, tx_ring->queue_index);
5068
5069 /* Herbert's original patch had:
5070 * smp_mb__after_netif_stop_queue();
5071 * but since that doesn't exist yet, just open code it.
5072 */
5073 smp_mb();
5074
5075 /* We need to check again in a case another CPU has just
5076 * made room available.
5077 */
5078 if (igb_desc_unused(tx_ring) < size)
5079 return -EBUSY;
5080
5081 /* A reprieve! */
5082 netif_wake_subqueue(netdev, tx_ring->queue_index);
5083
5084 u64_stats_update_begin(&tx_ring->tx_syncp2);
5085 tx_ring->tx_stats.restart_queue2++;
5086 u64_stats_update_end(&tx_ring->tx_syncp2);
5087
5088 return 0;
5089 }
5090
5091 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5092 {
5093 if (igb_desc_unused(tx_ring) >= size)
5094 return 0;
5095 return __igb_maybe_stop_tx(tx_ring, size);
5096 }
5097
5098 static void igb_tx_map(struct igb_ring *tx_ring,
5099 struct igb_tx_buffer *first,
5100 const u8 hdr_len)
5101 {
5102 struct sk_buff *skb = first->skb;
5103 struct igb_tx_buffer *tx_buffer;
5104 union e1000_adv_tx_desc *tx_desc;
5105 struct skb_frag_struct *frag;
5106 dma_addr_t dma;
5107 unsigned int data_len, size;
5108 u32 tx_flags = first->tx_flags;
5109 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
5110 u16 i = tx_ring->next_to_use;
5111
5112 tx_desc = IGB_TX_DESC(tx_ring, i);
5113
5114 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5115
5116 size = skb_headlen(skb);
5117 data_len = skb->data_len;
5118
5119 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5120
5121 tx_buffer = first;
5122
5123 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5124 if (dma_mapping_error(tx_ring->dev, dma))
5125 goto dma_error;
5126
5127 /* record length, and DMA address */
5128 dma_unmap_len_set(tx_buffer, len, size);
5129 dma_unmap_addr_set(tx_buffer, dma, dma);
5130
5131 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5132
5133 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5134 tx_desc->read.cmd_type_len =
5135 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
5136
5137 i++;
5138 tx_desc++;
5139 if (i == tx_ring->count) {
5140 tx_desc = IGB_TX_DESC(tx_ring, 0);
5141 i = 0;
5142 }
5143 tx_desc->read.olinfo_status = 0;
5144
5145 dma += IGB_MAX_DATA_PER_TXD;
5146 size -= IGB_MAX_DATA_PER_TXD;
5147
5148 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5149 }
5150
5151 if (likely(!data_len))
5152 break;
5153
5154 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
5155
5156 i++;
5157 tx_desc++;
5158 if (i == tx_ring->count) {
5159 tx_desc = IGB_TX_DESC(tx_ring, 0);
5160 i = 0;
5161 }
5162 tx_desc->read.olinfo_status = 0;
5163
5164 size = skb_frag_size(frag);
5165 data_len -= size;
5166
5167 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
5168 size, DMA_TO_DEVICE);
5169
5170 tx_buffer = &tx_ring->tx_buffer_info[i];
5171 }
5172
5173 /* write last descriptor with RS and EOP bits */
5174 cmd_type |= size | IGB_TXD_DCMD;
5175 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
5176
5177 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5178
5179 /* set the timestamp */
5180 first->time_stamp = jiffies;
5181
5182 /* Force memory writes to complete before letting h/w know there
5183 * are new descriptors to fetch. (Only applicable for weak-ordered
5184 * memory model archs, such as IA-64).
5185 *
5186 * We also need this memory barrier to make certain all of the
5187 * status bits have been updated before next_to_watch is written.
5188 */
5189 wmb();
5190
5191 /* set next_to_watch value indicating a packet is present */
5192 first->next_to_watch = tx_desc;
5193
5194 i++;
5195 if (i == tx_ring->count)
5196 i = 0;
5197
5198 tx_ring->next_to_use = i;
5199
5200 /* Make sure there is space in the ring for the next send. */
5201 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5202
5203 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
5204 writel(i, tx_ring->tail);
5205
5206 /* we need this if more than one processor can write to our tail
5207 * at a time, it synchronizes IO on IA64/Altix systems
5208 */
5209 mmiowb();
5210 }
5211 return;
5212
5213 dma_error:
5214 dev_err(tx_ring->dev, "TX DMA map failed\n");
5215
5216 /* clear dma mappings for failed tx_buffer_info map */
5217 for (;;) {
5218 tx_buffer = &tx_ring->tx_buffer_info[i];
5219 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5220 if (tx_buffer == first)
5221 break;
5222 if (i == 0)
5223 i = tx_ring->count;
5224 i--;
5225 }
5226
5227 tx_ring->next_to_use = i;
5228 }
5229
5230 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5231 struct igb_ring *tx_ring)
5232 {
5233 struct igb_tx_buffer *first;
5234 int tso;
5235 u32 tx_flags = 0;
5236 unsigned short f;
5237 u16 count = TXD_USE_COUNT(skb_headlen(skb));
5238 __be16 protocol = vlan_get_protocol(skb);
5239 u8 hdr_len = 0;
5240
5241 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5242 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
5243 * + 2 desc gap to keep tail from touching head,
5244 * + 1 desc for context descriptor,
5245 * otherwise try next time
5246 */
5247 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5248 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5249
5250 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5251 /* this is a hard error */
5252 return NETDEV_TX_BUSY;
5253 }
5254
5255 /* record the location of the first descriptor for this packet */
5256 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5257 first->skb = skb;
5258 first->bytecount = skb->len;
5259 first->gso_segs = 1;
5260
5261 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5262 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5263
5264 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5265 &adapter->state)) {
5266 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5267 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5268
5269 adapter->ptp_tx_skb = skb_get(skb);
5270 adapter->ptp_tx_start = jiffies;
5271 if (adapter->hw.mac.type == e1000_82576)
5272 schedule_work(&adapter->ptp_tx_work);
5273 }
5274 }
5275
5276 skb_tx_timestamp(skb);
5277
5278 if (skb_vlan_tag_present(skb)) {
5279 tx_flags |= IGB_TX_FLAGS_VLAN;
5280 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5281 }
5282
5283 /* record initial flags and protocol */
5284 first->tx_flags = tx_flags;
5285 first->protocol = protocol;
5286
5287 tso = igb_tso(tx_ring, first, &hdr_len);
5288 if (tso < 0)
5289 goto out_drop;
5290 else if (!tso)
5291 igb_tx_csum(tx_ring, first);
5292
5293 igb_tx_map(tx_ring, first, hdr_len);
5294
5295 return NETDEV_TX_OK;
5296
5297 out_drop:
5298 igb_unmap_and_free_tx_resource(tx_ring, first);
5299
5300 return NETDEV_TX_OK;
5301 }
5302
5303 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5304 struct sk_buff *skb)
5305 {
5306 unsigned int r_idx = skb->queue_mapping;
5307
5308 if (r_idx >= adapter->num_tx_queues)
5309 r_idx = r_idx % adapter->num_tx_queues;
5310
5311 return adapter->tx_ring[r_idx];
5312 }
5313
5314 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5315 struct net_device *netdev)
5316 {
5317 struct igb_adapter *adapter = netdev_priv(netdev);
5318
5319 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5320 * in order to meet this minimum size requirement.
5321 */
5322 if (skb_put_padto(skb, 17))
5323 return NETDEV_TX_OK;
5324
5325 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5326 }
5327
5328 /**
5329 * igb_tx_timeout - Respond to a Tx Hang
5330 * @netdev: network interface device structure
5331 **/
5332 static void igb_tx_timeout(struct net_device *netdev)
5333 {
5334 struct igb_adapter *adapter = netdev_priv(netdev);
5335 struct e1000_hw *hw = &adapter->hw;
5336
5337 /* Do the reset outside of interrupt context */
5338 adapter->tx_timeout_count++;
5339
5340 if (hw->mac.type >= e1000_82580)
5341 hw->dev_spec._82575.global_device_reset = true;
5342
5343 schedule_work(&adapter->reset_task);
5344 wr32(E1000_EICS,
5345 (adapter->eims_enable_mask & ~adapter->eims_other));
5346 }
5347
5348 static void igb_reset_task(struct work_struct *work)
5349 {
5350 struct igb_adapter *adapter;
5351 adapter = container_of(work, struct igb_adapter, reset_task);
5352
5353 igb_dump(adapter);
5354 netdev_err(adapter->netdev, "Reset adapter\n");
5355 igb_reinit_locked(adapter);
5356 }
5357
5358 /**
5359 * igb_get_stats64 - Get System Network Statistics
5360 * @netdev: network interface device structure
5361 * @stats: rtnl_link_stats64 pointer
5362 **/
5363 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5364 struct rtnl_link_stats64 *stats)
5365 {
5366 struct igb_adapter *adapter = netdev_priv(netdev);
5367
5368 spin_lock(&adapter->stats64_lock);
5369 igb_update_stats(adapter, &adapter->stats64);
5370 memcpy(stats, &adapter->stats64, sizeof(*stats));
5371 spin_unlock(&adapter->stats64_lock);
5372
5373 return stats;
5374 }
5375
5376 /**
5377 * igb_change_mtu - Change the Maximum Transfer Unit
5378 * @netdev: network interface device structure
5379 * @new_mtu: new value for maximum frame size
5380 *
5381 * Returns 0 on success, negative on failure
5382 **/
5383 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5384 {
5385 struct igb_adapter *adapter = netdev_priv(netdev);
5386 struct pci_dev *pdev = adapter->pdev;
5387 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5388
5389 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5390 dev_err(&pdev->dev, "Invalid MTU setting\n");
5391 return -EINVAL;
5392 }
5393
5394 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5395 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5396 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5397 return -EINVAL;
5398 }
5399
5400 /* adjust max frame to be at least the size of a standard frame */
5401 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5402 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5403
5404 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5405 usleep_range(1000, 2000);
5406
5407 /* igb_down has a dependency on max_frame_size */
5408 adapter->max_frame_size = max_frame;
5409
5410 if (netif_running(netdev))
5411 igb_down(adapter);
5412
5413 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5414 netdev->mtu, new_mtu);
5415 netdev->mtu = new_mtu;
5416
5417 if (netif_running(netdev))
5418 igb_up(adapter);
5419 else
5420 igb_reset(adapter);
5421
5422 clear_bit(__IGB_RESETTING, &adapter->state);
5423
5424 return 0;
5425 }
5426
5427 /**
5428 * igb_update_stats - Update the board statistics counters
5429 * @adapter: board private structure
5430 **/
5431 void igb_update_stats(struct igb_adapter *adapter,
5432 struct rtnl_link_stats64 *net_stats)
5433 {
5434 struct e1000_hw *hw = &adapter->hw;
5435 struct pci_dev *pdev = adapter->pdev;
5436 u32 reg, mpc;
5437 int i;
5438 u64 bytes, packets;
5439 unsigned int start;
5440 u64 _bytes, _packets;
5441
5442 /* Prevent stats update while adapter is being reset, or if the pci
5443 * connection is down.
5444 */
5445 if (adapter->link_speed == 0)
5446 return;
5447 if (pci_channel_offline(pdev))
5448 return;
5449
5450 bytes = 0;
5451 packets = 0;
5452
5453 rcu_read_lock();
5454 for (i = 0; i < adapter->num_rx_queues; i++) {
5455 struct igb_ring *ring = adapter->rx_ring[i];
5456 u32 rqdpc = rd32(E1000_RQDPC(i));
5457 if (hw->mac.type >= e1000_i210)
5458 wr32(E1000_RQDPC(i), 0);
5459
5460 if (rqdpc) {
5461 ring->rx_stats.drops += rqdpc;
5462 net_stats->rx_fifo_errors += rqdpc;
5463 }
5464
5465 do {
5466 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5467 _bytes = ring->rx_stats.bytes;
5468 _packets = ring->rx_stats.packets;
5469 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5470 bytes += _bytes;
5471 packets += _packets;
5472 }
5473
5474 net_stats->rx_bytes = bytes;
5475 net_stats->rx_packets = packets;
5476
5477 bytes = 0;
5478 packets = 0;
5479 for (i = 0; i < adapter->num_tx_queues; i++) {
5480 struct igb_ring *ring = adapter->tx_ring[i];
5481 do {
5482 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5483 _bytes = ring->tx_stats.bytes;
5484 _packets = ring->tx_stats.packets;
5485 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5486 bytes += _bytes;
5487 packets += _packets;
5488 }
5489 net_stats->tx_bytes = bytes;
5490 net_stats->tx_packets = packets;
5491 rcu_read_unlock();
5492
5493 /* read stats registers */
5494 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5495 adapter->stats.gprc += rd32(E1000_GPRC);
5496 adapter->stats.gorc += rd32(E1000_GORCL);
5497 rd32(E1000_GORCH); /* clear GORCL */
5498 adapter->stats.bprc += rd32(E1000_BPRC);
5499 adapter->stats.mprc += rd32(E1000_MPRC);
5500 adapter->stats.roc += rd32(E1000_ROC);
5501
5502 adapter->stats.prc64 += rd32(E1000_PRC64);
5503 adapter->stats.prc127 += rd32(E1000_PRC127);
5504 adapter->stats.prc255 += rd32(E1000_PRC255);
5505 adapter->stats.prc511 += rd32(E1000_PRC511);
5506 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5507 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5508 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5509 adapter->stats.sec += rd32(E1000_SEC);
5510
5511 mpc = rd32(E1000_MPC);
5512 adapter->stats.mpc += mpc;
5513 net_stats->rx_fifo_errors += mpc;
5514 adapter->stats.scc += rd32(E1000_SCC);
5515 adapter->stats.ecol += rd32(E1000_ECOL);
5516 adapter->stats.mcc += rd32(E1000_MCC);
5517 adapter->stats.latecol += rd32(E1000_LATECOL);
5518 adapter->stats.dc += rd32(E1000_DC);
5519 adapter->stats.rlec += rd32(E1000_RLEC);
5520 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5521 adapter->stats.xontxc += rd32(E1000_XONTXC);
5522 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5523 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5524 adapter->stats.fcruc += rd32(E1000_FCRUC);
5525 adapter->stats.gptc += rd32(E1000_GPTC);
5526 adapter->stats.gotc += rd32(E1000_GOTCL);
5527 rd32(E1000_GOTCH); /* clear GOTCL */
5528 adapter->stats.rnbc += rd32(E1000_RNBC);
5529 adapter->stats.ruc += rd32(E1000_RUC);
5530 adapter->stats.rfc += rd32(E1000_RFC);
5531 adapter->stats.rjc += rd32(E1000_RJC);
5532 adapter->stats.tor += rd32(E1000_TORH);
5533 adapter->stats.tot += rd32(E1000_TOTH);
5534 adapter->stats.tpr += rd32(E1000_TPR);
5535
5536 adapter->stats.ptc64 += rd32(E1000_PTC64);
5537 adapter->stats.ptc127 += rd32(E1000_PTC127);
5538 adapter->stats.ptc255 += rd32(E1000_PTC255);
5539 adapter->stats.ptc511 += rd32(E1000_PTC511);
5540 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5541 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5542
5543 adapter->stats.mptc += rd32(E1000_MPTC);
5544 adapter->stats.bptc += rd32(E1000_BPTC);
5545
5546 adapter->stats.tpt += rd32(E1000_TPT);
5547 adapter->stats.colc += rd32(E1000_COLC);
5548
5549 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5550 /* read internal phy specific stats */
5551 reg = rd32(E1000_CTRL_EXT);
5552 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5553 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5554
5555 /* this stat has invalid values on i210/i211 */
5556 if ((hw->mac.type != e1000_i210) &&
5557 (hw->mac.type != e1000_i211))
5558 adapter->stats.tncrs += rd32(E1000_TNCRS);
5559 }
5560
5561 adapter->stats.tsctc += rd32(E1000_TSCTC);
5562 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5563
5564 adapter->stats.iac += rd32(E1000_IAC);
5565 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5566 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5567 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5568 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5569 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5570 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5571 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5572 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5573
5574 /* Fill out the OS statistics structure */
5575 net_stats->multicast = adapter->stats.mprc;
5576 net_stats->collisions = adapter->stats.colc;
5577
5578 /* Rx Errors */
5579
5580 /* RLEC on some newer hardware can be incorrect so build
5581 * our own version based on RUC and ROC
5582 */
5583 net_stats->rx_errors = adapter->stats.rxerrc +
5584 adapter->stats.crcerrs + adapter->stats.algnerrc +
5585 adapter->stats.ruc + adapter->stats.roc +
5586 adapter->stats.cexterr;
5587 net_stats->rx_length_errors = adapter->stats.ruc +
5588 adapter->stats.roc;
5589 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5590 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5591 net_stats->rx_missed_errors = adapter->stats.mpc;
5592
5593 /* Tx Errors */
5594 net_stats->tx_errors = adapter->stats.ecol +
5595 adapter->stats.latecol;
5596 net_stats->tx_aborted_errors = adapter->stats.ecol;
5597 net_stats->tx_window_errors = adapter->stats.latecol;
5598 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5599
5600 /* Tx Dropped needs to be maintained elsewhere */
5601
5602 /* Management Stats */
5603 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5604 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5605 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5606
5607 /* OS2BMC Stats */
5608 reg = rd32(E1000_MANC);
5609 if (reg & E1000_MANC_EN_BMC2OS) {
5610 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5611 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5612 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5613 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5614 }
5615 }
5616
5617 static void igb_tsync_interrupt(struct igb_adapter *adapter)
5618 {
5619 struct e1000_hw *hw = &adapter->hw;
5620 struct ptp_clock_event event;
5621 struct timespec64 ts;
5622 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
5623
5624 if (tsicr & TSINTR_SYS_WRAP) {
5625 event.type = PTP_CLOCK_PPS;
5626 if (adapter->ptp_caps.pps)
5627 ptp_clock_event(adapter->ptp_clock, &event);
5628 else
5629 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5630 ack |= TSINTR_SYS_WRAP;
5631 }
5632
5633 if (tsicr & E1000_TSICR_TXTS) {
5634 /* retrieve hardware timestamp */
5635 schedule_work(&adapter->ptp_tx_work);
5636 ack |= E1000_TSICR_TXTS;
5637 }
5638
5639 if (tsicr & TSINTR_TT0) {
5640 spin_lock(&adapter->tmreg_lock);
5641 ts = timespec64_add(adapter->perout[0].start,
5642 adapter->perout[0].period);
5643 /* u32 conversion of tv_sec is safe until y2106 */
5644 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5645 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
5646 tsauxc = rd32(E1000_TSAUXC);
5647 tsauxc |= TSAUXC_EN_TT0;
5648 wr32(E1000_TSAUXC, tsauxc);
5649 adapter->perout[0].start = ts;
5650 spin_unlock(&adapter->tmreg_lock);
5651 ack |= TSINTR_TT0;
5652 }
5653
5654 if (tsicr & TSINTR_TT1) {
5655 spin_lock(&adapter->tmreg_lock);
5656 ts = timespec64_add(adapter->perout[1].start,
5657 adapter->perout[1].period);
5658 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5659 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
5660 tsauxc = rd32(E1000_TSAUXC);
5661 tsauxc |= TSAUXC_EN_TT1;
5662 wr32(E1000_TSAUXC, tsauxc);
5663 adapter->perout[1].start = ts;
5664 spin_unlock(&adapter->tmreg_lock);
5665 ack |= TSINTR_TT1;
5666 }
5667
5668 if (tsicr & TSINTR_AUTT0) {
5669 nsec = rd32(E1000_AUXSTMPL0);
5670 sec = rd32(E1000_AUXSTMPH0);
5671 event.type = PTP_CLOCK_EXTTS;
5672 event.index = 0;
5673 event.timestamp = sec * 1000000000ULL + nsec;
5674 ptp_clock_event(adapter->ptp_clock, &event);
5675 ack |= TSINTR_AUTT0;
5676 }
5677
5678 if (tsicr & TSINTR_AUTT1) {
5679 nsec = rd32(E1000_AUXSTMPL1);
5680 sec = rd32(E1000_AUXSTMPH1);
5681 event.type = PTP_CLOCK_EXTTS;
5682 event.index = 1;
5683 event.timestamp = sec * 1000000000ULL + nsec;
5684 ptp_clock_event(adapter->ptp_clock, &event);
5685 ack |= TSINTR_AUTT1;
5686 }
5687
5688 /* acknowledge the interrupts */
5689 wr32(E1000_TSICR, ack);
5690 }
5691
5692 static irqreturn_t igb_msix_other(int irq, void *data)
5693 {
5694 struct igb_adapter *adapter = data;
5695 struct e1000_hw *hw = &adapter->hw;
5696 u32 icr = rd32(E1000_ICR);
5697 /* reading ICR causes bit 31 of EICR to be cleared */
5698
5699 if (icr & E1000_ICR_DRSTA)
5700 schedule_work(&adapter->reset_task);
5701
5702 if (icr & E1000_ICR_DOUTSYNC) {
5703 /* HW is reporting DMA is out of sync */
5704 adapter->stats.doosync++;
5705 /* The DMA Out of Sync is also indication of a spoof event
5706 * in IOV mode. Check the Wrong VM Behavior register to
5707 * see if it is really a spoof event.
5708 */
5709 igb_check_wvbr(adapter);
5710 }
5711
5712 /* Check for a mailbox event */
5713 if (icr & E1000_ICR_VMMB)
5714 igb_msg_task(adapter);
5715
5716 if (icr & E1000_ICR_LSC) {
5717 hw->mac.get_link_status = 1;
5718 /* guard against interrupt when we're going down */
5719 if (!test_bit(__IGB_DOWN, &adapter->state))
5720 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5721 }
5722
5723 if (icr & E1000_ICR_TS)
5724 igb_tsync_interrupt(adapter);
5725
5726 wr32(E1000_EIMS, adapter->eims_other);
5727
5728 return IRQ_HANDLED;
5729 }
5730
5731 static void igb_write_itr(struct igb_q_vector *q_vector)
5732 {
5733 struct igb_adapter *adapter = q_vector->adapter;
5734 u32 itr_val = q_vector->itr_val & 0x7FFC;
5735
5736 if (!q_vector->set_itr)
5737 return;
5738
5739 if (!itr_val)
5740 itr_val = 0x4;
5741
5742 if (adapter->hw.mac.type == e1000_82575)
5743 itr_val |= itr_val << 16;
5744 else
5745 itr_val |= E1000_EITR_CNT_IGNR;
5746
5747 writel(itr_val, q_vector->itr_register);
5748 q_vector->set_itr = 0;
5749 }
5750
5751 static irqreturn_t igb_msix_ring(int irq, void *data)
5752 {
5753 struct igb_q_vector *q_vector = data;
5754
5755 /* Write the ITR value calculated from the previous interrupt. */
5756 igb_write_itr(q_vector);
5757
5758 napi_schedule(&q_vector->napi);
5759
5760 return IRQ_HANDLED;
5761 }
5762
5763 #ifdef CONFIG_IGB_DCA
5764 static void igb_update_tx_dca(struct igb_adapter *adapter,
5765 struct igb_ring *tx_ring,
5766 int cpu)
5767 {
5768 struct e1000_hw *hw = &adapter->hw;
5769 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5770
5771 if (hw->mac.type != e1000_82575)
5772 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5773
5774 /* We can enable relaxed ordering for reads, but not writes when
5775 * DCA is enabled. This is due to a known issue in some chipsets
5776 * which will cause the DCA tag to be cleared.
5777 */
5778 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5779 E1000_DCA_TXCTRL_DATA_RRO_EN |
5780 E1000_DCA_TXCTRL_DESC_DCA_EN;
5781
5782 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5783 }
5784
5785 static void igb_update_rx_dca(struct igb_adapter *adapter,
5786 struct igb_ring *rx_ring,
5787 int cpu)
5788 {
5789 struct e1000_hw *hw = &adapter->hw;
5790 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5791
5792 if (hw->mac.type != e1000_82575)
5793 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5794
5795 /* We can enable relaxed ordering for reads, but not writes when
5796 * DCA is enabled. This is due to a known issue in some chipsets
5797 * which will cause the DCA tag to be cleared.
5798 */
5799 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5800 E1000_DCA_RXCTRL_DESC_DCA_EN;
5801
5802 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5803 }
5804
5805 static void igb_update_dca(struct igb_q_vector *q_vector)
5806 {
5807 struct igb_adapter *adapter = q_vector->adapter;
5808 int cpu = get_cpu();
5809
5810 if (q_vector->cpu == cpu)
5811 goto out_no_update;
5812
5813 if (q_vector->tx.ring)
5814 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5815
5816 if (q_vector->rx.ring)
5817 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5818
5819 q_vector->cpu = cpu;
5820 out_no_update:
5821 put_cpu();
5822 }
5823
5824 static void igb_setup_dca(struct igb_adapter *adapter)
5825 {
5826 struct e1000_hw *hw = &adapter->hw;
5827 int i;
5828
5829 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5830 return;
5831
5832 /* Always use CB2 mode, difference is masked in the CB driver. */
5833 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5834
5835 for (i = 0; i < adapter->num_q_vectors; i++) {
5836 adapter->q_vector[i]->cpu = -1;
5837 igb_update_dca(adapter->q_vector[i]);
5838 }
5839 }
5840
5841 static int __igb_notify_dca(struct device *dev, void *data)
5842 {
5843 struct net_device *netdev = dev_get_drvdata(dev);
5844 struct igb_adapter *adapter = netdev_priv(netdev);
5845 struct pci_dev *pdev = adapter->pdev;
5846 struct e1000_hw *hw = &adapter->hw;
5847 unsigned long event = *(unsigned long *)data;
5848
5849 switch (event) {
5850 case DCA_PROVIDER_ADD:
5851 /* if already enabled, don't do it again */
5852 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5853 break;
5854 if (dca_add_requester(dev) == 0) {
5855 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5856 dev_info(&pdev->dev, "DCA enabled\n");
5857 igb_setup_dca(adapter);
5858 break;
5859 }
5860 /* Fall Through since DCA is disabled. */
5861 case DCA_PROVIDER_REMOVE:
5862 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5863 /* without this a class_device is left
5864 * hanging around in the sysfs model
5865 */
5866 dca_remove_requester(dev);
5867 dev_info(&pdev->dev, "DCA disabled\n");
5868 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5869 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5870 }
5871 break;
5872 }
5873
5874 return 0;
5875 }
5876
5877 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5878 void *p)
5879 {
5880 int ret_val;
5881
5882 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5883 __igb_notify_dca);
5884
5885 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5886 }
5887 #endif /* CONFIG_IGB_DCA */
5888
5889 #ifdef CONFIG_PCI_IOV
5890 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5891 {
5892 unsigned char mac_addr[ETH_ALEN];
5893
5894 eth_zero_addr(mac_addr);
5895 igb_set_vf_mac(adapter, vf, mac_addr);
5896
5897 /* By default spoof check is enabled for all VFs */
5898 adapter->vf_data[vf].spoofchk_enabled = true;
5899
5900 return 0;
5901 }
5902
5903 #endif
5904 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5905 {
5906 struct e1000_hw *hw = &adapter->hw;
5907 u32 ping;
5908 int i;
5909
5910 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5911 ping = E1000_PF_CONTROL_MSG;
5912 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5913 ping |= E1000_VT_MSGTYPE_CTS;
5914 igb_write_mbx(hw, &ping, 1, i);
5915 }
5916 }
5917
5918 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5919 {
5920 struct e1000_hw *hw = &adapter->hw;
5921 u32 vmolr = rd32(E1000_VMOLR(vf));
5922 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5923
5924 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5925 IGB_VF_FLAG_MULTI_PROMISC);
5926 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5927
5928 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5929 vmolr |= E1000_VMOLR_MPME;
5930 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5931 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5932 } else {
5933 /* if we have hashes and we are clearing a multicast promisc
5934 * flag we need to write the hashes to the MTA as this step
5935 * was previously skipped
5936 */
5937 if (vf_data->num_vf_mc_hashes > 30) {
5938 vmolr |= E1000_VMOLR_MPME;
5939 } else if (vf_data->num_vf_mc_hashes) {
5940 int j;
5941
5942 vmolr |= E1000_VMOLR_ROMPE;
5943 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5944 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5945 }
5946 }
5947
5948 wr32(E1000_VMOLR(vf), vmolr);
5949
5950 /* there are flags left unprocessed, likely not supported */
5951 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5952 return -EINVAL;
5953
5954 return 0;
5955 }
5956
5957 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5958 u32 *msgbuf, u32 vf)
5959 {
5960 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5961 u16 *hash_list = (u16 *)&msgbuf[1];
5962 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5963 int i;
5964
5965 /* salt away the number of multicast addresses assigned
5966 * to this VF for later use to restore when the PF multi cast
5967 * list changes
5968 */
5969 vf_data->num_vf_mc_hashes = n;
5970
5971 /* only up to 30 hash values supported */
5972 if (n > 30)
5973 n = 30;
5974
5975 /* store the hashes for later use */
5976 for (i = 0; i < n; i++)
5977 vf_data->vf_mc_hashes[i] = hash_list[i];
5978
5979 /* Flush and reset the mta with the new values */
5980 igb_set_rx_mode(adapter->netdev);
5981
5982 return 0;
5983 }
5984
5985 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5986 {
5987 struct e1000_hw *hw = &adapter->hw;
5988 struct vf_data_storage *vf_data;
5989 int i, j;
5990
5991 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5992 u32 vmolr = rd32(E1000_VMOLR(i));
5993
5994 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5995
5996 vf_data = &adapter->vf_data[i];
5997
5998 if ((vf_data->num_vf_mc_hashes > 30) ||
5999 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
6000 vmolr |= E1000_VMOLR_MPME;
6001 } else if (vf_data->num_vf_mc_hashes) {
6002 vmolr |= E1000_VMOLR_ROMPE;
6003 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6004 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6005 }
6006 wr32(E1000_VMOLR(i), vmolr);
6007 }
6008 }
6009
6010 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
6011 {
6012 struct e1000_hw *hw = &adapter->hw;
6013 u32 pool_mask, vlvf_mask, i;
6014
6015 /* create mask for VF and other pools */
6016 pool_mask = E1000_VLVF_POOLSEL_MASK;
6017 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
6018
6019 /* drop PF from pool bits */
6020 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
6021 adapter->vfs_allocated_count);
6022
6023 /* Find the vlan filter for this id */
6024 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
6025 u32 vlvf = rd32(E1000_VLVF(i));
6026 u32 vfta_mask, vid, vfta;
6027
6028 /* remove the vf from the pool */
6029 if (!(vlvf & vlvf_mask))
6030 continue;
6031
6032 /* clear out bit from VLVF */
6033 vlvf ^= vlvf_mask;
6034
6035 /* if other pools are present, just remove ourselves */
6036 if (vlvf & pool_mask)
6037 goto update_vlvfb;
6038
6039 /* if PF is present, leave VFTA */
6040 if (vlvf & E1000_VLVF_POOLSEL_MASK)
6041 goto update_vlvf;
6042
6043 vid = vlvf & E1000_VLVF_VLANID_MASK;
6044 vfta_mask = BIT(vid % 32);
6045
6046 /* clear bit from VFTA */
6047 vfta = adapter->shadow_vfta[vid / 32];
6048 if (vfta & vfta_mask)
6049 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
6050 update_vlvf:
6051 /* clear pool selection enable */
6052 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6053 vlvf &= E1000_VLVF_POOLSEL_MASK;
6054 else
6055 vlvf = 0;
6056 update_vlvfb:
6057 /* clear pool bits */
6058 wr32(E1000_VLVF(i), vlvf);
6059 }
6060 }
6061
6062 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6063 {
6064 u32 vlvf;
6065 int idx;
6066
6067 /* short cut the special case */
6068 if (vlan == 0)
6069 return 0;
6070
6071 /* Search for the VLAN id in the VLVF entries */
6072 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6073 vlvf = rd32(E1000_VLVF(idx));
6074 if ((vlvf & VLAN_VID_MASK) == vlan)
6075 break;
6076 }
6077
6078 return idx;
6079 }
6080
6081 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6082 {
6083 struct e1000_hw *hw = &adapter->hw;
6084 u32 bits, pf_id;
6085 int idx;
6086
6087 idx = igb_find_vlvf_entry(hw, vid);
6088 if (!idx)
6089 return;
6090
6091 /* See if any other pools are set for this VLAN filter
6092 * entry other than the PF.
6093 */
6094 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6095 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
6096 bits &= rd32(E1000_VLVF(idx));
6097
6098 /* Disable the filter so this falls into the default pool. */
6099 if (!bits) {
6100 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6101 wr32(E1000_VLVF(idx), BIT(pf_id));
6102 else
6103 wr32(E1000_VLVF(idx), 0);
6104 }
6105 }
6106
6107 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6108 bool add, u32 vf)
6109 {
6110 int pf_id = adapter->vfs_allocated_count;
6111 struct e1000_hw *hw = &adapter->hw;
6112 int err;
6113
6114 /* If VLAN overlaps with one the PF is currently monitoring make
6115 * sure that we are able to allocate a VLVF entry. This may be
6116 * redundant but it guarantees PF will maintain visibility to
6117 * the VLAN.
6118 */
6119 if (add && test_bit(vid, adapter->active_vlans)) {
6120 err = igb_vfta_set(hw, vid, pf_id, true, false);
6121 if (err)
6122 return err;
6123 }
6124
6125 err = igb_vfta_set(hw, vid, vf, add, false);
6126
6127 if (add && !err)
6128 return err;
6129
6130 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6131 * we may need to drop the PF pool bit in order to allow us to free
6132 * up the VLVF resources.
6133 */
6134 if (test_bit(vid, adapter->active_vlans) ||
6135 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6136 igb_update_pf_vlvf(adapter, vid);
6137
6138 return err;
6139 }
6140
6141 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6142 {
6143 struct e1000_hw *hw = &adapter->hw;
6144
6145 if (vid)
6146 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6147 else
6148 wr32(E1000_VMVIR(vf), 0);
6149 }
6150
6151 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6152 u16 vlan, u8 qos)
6153 {
6154 int err;
6155
6156 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6157 if (err)
6158 return err;
6159
6160 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6161 igb_set_vmolr(adapter, vf, !vlan);
6162
6163 /* revoke access to previous VLAN */
6164 if (vlan != adapter->vf_data[vf].pf_vlan)
6165 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6166 false, vf);
6167
6168 adapter->vf_data[vf].pf_vlan = vlan;
6169 adapter->vf_data[vf].pf_qos = qos;
6170 igb_set_vf_vlan_strip(adapter, vf, true);
6171 dev_info(&adapter->pdev->dev,
6172 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6173 if (test_bit(__IGB_DOWN, &adapter->state)) {
6174 dev_warn(&adapter->pdev->dev,
6175 "The VF VLAN has been set, but the PF device is not up.\n");
6176 dev_warn(&adapter->pdev->dev,
6177 "Bring the PF device up before attempting to use the VF device.\n");
6178 }
6179
6180 return err;
6181 }
6182
6183 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6184 {
6185 /* Restore tagless access via VLAN 0 */
6186 igb_set_vf_vlan(adapter, 0, true, vf);
6187
6188 igb_set_vmvir(adapter, 0, vf);
6189 igb_set_vmolr(adapter, vf, true);
6190
6191 /* Remove any PF assigned VLAN */
6192 if (adapter->vf_data[vf].pf_vlan)
6193 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6194 false, vf);
6195
6196 adapter->vf_data[vf].pf_vlan = 0;
6197 adapter->vf_data[vf].pf_qos = 0;
6198 igb_set_vf_vlan_strip(adapter, vf, false);
6199
6200 return 0;
6201 }
6202
6203 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6204 int vf, u16 vlan, u8 qos)
6205 {
6206 struct igb_adapter *adapter = netdev_priv(netdev);
6207
6208 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6209 return -EINVAL;
6210
6211 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6212 igb_disable_port_vlan(adapter, vf);
6213 }
6214
6215 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6216 {
6217 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6218 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6219 int ret;
6220
6221 if (adapter->vf_data[vf].pf_vlan)
6222 return -1;
6223
6224 /* VLAN 0 is a special case, don't allow it to be removed */
6225 if (!vid && !add)
6226 return 0;
6227
6228 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
6229 if (!ret)
6230 igb_set_vf_vlan_strip(adapter, vf, !!vid);
6231 return ret;
6232 }
6233
6234 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6235 {
6236 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6237
6238 /* clear flags - except flag that indicates PF has set the MAC */
6239 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6240 vf_data->last_nack = jiffies;
6241
6242 /* reset vlans for device */
6243 igb_clear_vf_vfta(adapter, vf);
6244 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6245 igb_set_vmvir(adapter, vf_data->pf_vlan |
6246 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6247 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
6248 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
6249
6250 /* reset multicast table array for vf */
6251 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6252
6253 /* Flush and reset the mta with the new values */
6254 igb_set_rx_mode(adapter->netdev);
6255 }
6256
6257 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6258 {
6259 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6260
6261 /* clear mac address as we were hotplug removed/added */
6262 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6263 eth_zero_addr(vf_mac);
6264
6265 /* process remaining reset events */
6266 igb_vf_reset(adapter, vf);
6267 }
6268
6269 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6270 {
6271 struct e1000_hw *hw = &adapter->hw;
6272 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6273 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6274 u32 reg, msgbuf[3];
6275 u8 *addr = (u8 *)(&msgbuf[1]);
6276
6277 /* process all the same items cleared in a function level reset */
6278 igb_vf_reset(adapter, vf);
6279
6280 /* set vf mac address */
6281 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6282
6283 /* enable transmit and receive for vf */
6284 reg = rd32(E1000_VFTE);
6285 wr32(E1000_VFTE, reg | BIT(vf));
6286 reg = rd32(E1000_VFRE);
6287 wr32(E1000_VFRE, reg | BIT(vf));
6288
6289 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6290
6291 /* reply to reset with ack and vf mac address */
6292 if (!is_zero_ether_addr(vf_mac)) {
6293 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6294 memcpy(addr, vf_mac, ETH_ALEN);
6295 } else {
6296 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6297 }
6298 igb_write_mbx(hw, msgbuf, 3, vf);
6299 }
6300
6301 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6302 {
6303 /* The VF MAC Address is stored in a packed array of bytes
6304 * starting at the second 32 bit word of the msg array
6305 */
6306 unsigned char *addr = (char *)&msg[1];
6307 int err = -1;
6308
6309 if (is_valid_ether_addr(addr))
6310 err = igb_set_vf_mac(adapter, vf, addr);
6311
6312 return err;
6313 }
6314
6315 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6316 {
6317 struct e1000_hw *hw = &adapter->hw;
6318 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6319 u32 msg = E1000_VT_MSGTYPE_NACK;
6320
6321 /* if device isn't clear to send it shouldn't be reading either */
6322 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6323 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6324 igb_write_mbx(hw, &msg, 1, vf);
6325 vf_data->last_nack = jiffies;
6326 }
6327 }
6328
6329 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6330 {
6331 struct pci_dev *pdev = adapter->pdev;
6332 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6333 struct e1000_hw *hw = &adapter->hw;
6334 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6335 s32 retval;
6336
6337 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6338
6339 if (retval) {
6340 /* if receive failed revoke VF CTS stats and restart init */
6341 dev_err(&pdev->dev, "Error receiving message from VF\n");
6342 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6343 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6344 return;
6345 goto out;
6346 }
6347
6348 /* this is a message we already processed, do nothing */
6349 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6350 return;
6351
6352 /* until the vf completes a reset it should not be
6353 * allowed to start any configuration.
6354 */
6355 if (msgbuf[0] == E1000_VF_RESET) {
6356 igb_vf_reset_msg(adapter, vf);
6357 return;
6358 }
6359
6360 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6361 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6362 return;
6363 retval = -1;
6364 goto out;
6365 }
6366
6367 switch ((msgbuf[0] & 0xFFFF)) {
6368 case E1000_VF_SET_MAC_ADDR:
6369 retval = -EINVAL;
6370 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6371 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6372 else
6373 dev_warn(&pdev->dev,
6374 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6375 vf);
6376 break;
6377 case E1000_VF_SET_PROMISC:
6378 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6379 break;
6380 case E1000_VF_SET_MULTICAST:
6381 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6382 break;
6383 case E1000_VF_SET_LPE:
6384 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6385 break;
6386 case E1000_VF_SET_VLAN:
6387 retval = -1;
6388 if (vf_data->pf_vlan)
6389 dev_warn(&pdev->dev,
6390 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6391 vf);
6392 else
6393 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
6394 break;
6395 default:
6396 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6397 retval = -1;
6398 break;
6399 }
6400
6401 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6402 out:
6403 /* notify the VF of the results of what it sent us */
6404 if (retval)
6405 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6406 else
6407 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6408
6409 igb_write_mbx(hw, msgbuf, 1, vf);
6410 }
6411
6412 static void igb_msg_task(struct igb_adapter *adapter)
6413 {
6414 struct e1000_hw *hw = &adapter->hw;
6415 u32 vf;
6416
6417 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6418 /* process any reset requests */
6419 if (!igb_check_for_rst(hw, vf))
6420 igb_vf_reset_event(adapter, vf);
6421
6422 /* process any messages pending */
6423 if (!igb_check_for_msg(hw, vf))
6424 igb_rcv_msg_from_vf(adapter, vf);
6425
6426 /* process any acks */
6427 if (!igb_check_for_ack(hw, vf))
6428 igb_rcv_ack_from_vf(adapter, vf);
6429 }
6430 }
6431
6432 /**
6433 * igb_set_uta - Set unicast filter table address
6434 * @adapter: board private structure
6435 * @set: boolean indicating if we are setting or clearing bits
6436 *
6437 * The unicast table address is a register array of 32-bit registers.
6438 * The table is meant to be used in a way similar to how the MTA is used
6439 * however due to certain limitations in the hardware it is necessary to
6440 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6441 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6442 **/
6443 static void igb_set_uta(struct igb_adapter *adapter, bool set)
6444 {
6445 struct e1000_hw *hw = &adapter->hw;
6446 u32 uta = set ? ~0 : 0;
6447 int i;
6448
6449 /* we only need to do this if VMDq is enabled */
6450 if (!adapter->vfs_allocated_count)
6451 return;
6452
6453 for (i = hw->mac.uta_reg_count; i--;)
6454 array_wr32(E1000_UTA, i, uta);
6455 }
6456
6457 /**
6458 * igb_intr_msi - Interrupt Handler
6459 * @irq: interrupt number
6460 * @data: pointer to a network interface device structure
6461 **/
6462 static irqreturn_t igb_intr_msi(int irq, void *data)
6463 {
6464 struct igb_adapter *adapter = data;
6465 struct igb_q_vector *q_vector = adapter->q_vector[0];
6466 struct e1000_hw *hw = &adapter->hw;
6467 /* read ICR disables interrupts using IAM */
6468 u32 icr = rd32(E1000_ICR);
6469
6470 igb_write_itr(q_vector);
6471
6472 if (icr & E1000_ICR_DRSTA)
6473 schedule_work(&adapter->reset_task);
6474
6475 if (icr & E1000_ICR_DOUTSYNC) {
6476 /* HW is reporting DMA is out of sync */
6477 adapter->stats.doosync++;
6478 }
6479
6480 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6481 hw->mac.get_link_status = 1;
6482 if (!test_bit(__IGB_DOWN, &adapter->state))
6483 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6484 }
6485
6486 if (icr & E1000_ICR_TS)
6487 igb_tsync_interrupt(adapter);
6488
6489 napi_schedule(&q_vector->napi);
6490
6491 return IRQ_HANDLED;
6492 }
6493
6494 /**
6495 * igb_intr - Legacy Interrupt Handler
6496 * @irq: interrupt number
6497 * @data: pointer to a network interface device structure
6498 **/
6499 static irqreturn_t igb_intr(int irq, void *data)
6500 {
6501 struct igb_adapter *adapter = data;
6502 struct igb_q_vector *q_vector = adapter->q_vector[0];
6503 struct e1000_hw *hw = &adapter->hw;
6504 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6505 * need for the IMC write
6506 */
6507 u32 icr = rd32(E1000_ICR);
6508
6509 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6510 * not set, then the adapter didn't send an interrupt
6511 */
6512 if (!(icr & E1000_ICR_INT_ASSERTED))
6513 return IRQ_NONE;
6514
6515 igb_write_itr(q_vector);
6516
6517 if (icr & E1000_ICR_DRSTA)
6518 schedule_work(&adapter->reset_task);
6519
6520 if (icr & E1000_ICR_DOUTSYNC) {
6521 /* HW is reporting DMA is out of sync */
6522 adapter->stats.doosync++;
6523 }
6524
6525 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6526 hw->mac.get_link_status = 1;
6527 /* guard against interrupt when we're going down */
6528 if (!test_bit(__IGB_DOWN, &adapter->state))
6529 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6530 }
6531
6532 if (icr & E1000_ICR_TS)
6533 igb_tsync_interrupt(adapter);
6534
6535 napi_schedule(&q_vector->napi);
6536
6537 return IRQ_HANDLED;
6538 }
6539
6540 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6541 {
6542 struct igb_adapter *adapter = q_vector->adapter;
6543 struct e1000_hw *hw = &adapter->hw;
6544
6545 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6546 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6547 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6548 igb_set_itr(q_vector);
6549 else
6550 igb_update_ring_itr(q_vector);
6551 }
6552
6553 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6554 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6555 wr32(E1000_EIMS, q_vector->eims_value);
6556 else
6557 igb_irq_enable(adapter);
6558 }
6559 }
6560
6561 /**
6562 * igb_poll - NAPI Rx polling callback
6563 * @napi: napi polling structure
6564 * @budget: count of how many packets we should handle
6565 **/
6566 static int igb_poll(struct napi_struct *napi, int budget)
6567 {
6568 struct igb_q_vector *q_vector = container_of(napi,
6569 struct igb_q_vector,
6570 napi);
6571 bool clean_complete = true;
6572 int work_done = 0;
6573
6574 #ifdef CONFIG_IGB_DCA
6575 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6576 igb_update_dca(q_vector);
6577 #endif
6578 if (q_vector->tx.ring)
6579 clean_complete = igb_clean_tx_irq(q_vector, budget);
6580
6581 if (q_vector->rx.ring) {
6582 int cleaned = igb_clean_rx_irq(q_vector, budget);
6583
6584 work_done += cleaned;
6585 if (cleaned >= budget)
6586 clean_complete = false;
6587 }
6588
6589 /* If all work not completed, return budget and keep polling */
6590 if (!clean_complete)
6591 return budget;
6592
6593 /* If not enough Rx work done, exit the polling mode */
6594 napi_complete_done(napi, work_done);
6595 igb_ring_irq_enable(q_vector);
6596
6597 return 0;
6598 }
6599
6600 /**
6601 * igb_clean_tx_irq - Reclaim resources after transmit completes
6602 * @q_vector: pointer to q_vector containing needed info
6603 * @napi_budget: Used to determine if we are in netpoll
6604 *
6605 * returns true if ring is completely cleaned
6606 **/
6607 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
6608 {
6609 struct igb_adapter *adapter = q_vector->adapter;
6610 struct igb_ring *tx_ring = q_vector->tx.ring;
6611 struct igb_tx_buffer *tx_buffer;
6612 union e1000_adv_tx_desc *tx_desc;
6613 unsigned int total_bytes = 0, total_packets = 0;
6614 unsigned int budget = q_vector->tx.work_limit;
6615 unsigned int i = tx_ring->next_to_clean;
6616
6617 if (test_bit(__IGB_DOWN, &adapter->state))
6618 return true;
6619
6620 tx_buffer = &tx_ring->tx_buffer_info[i];
6621 tx_desc = IGB_TX_DESC(tx_ring, i);
6622 i -= tx_ring->count;
6623
6624 do {
6625 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6626
6627 /* if next_to_watch is not set then there is no work pending */
6628 if (!eop_desc)
6629 break;
6630
6631 /* prevent any other reads prior to eop_desc */
6632 read_barrier_depends();
6633
6634 /* if DD is not set pending work has not been completed */
6635 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6636 break;
6637
6638 /* clear next_to_watch to prevent false hangs */
6639 tx_buffer->next_to_watch = NULL;
6640
6641 /* update the statistics for this packet */
6642 total_bytes += tx_buffer->bytecount;
6643 total_packets += tx_buffer->gso_segs;
6644
6645 /* free the skb */
6646 napi_consume_skb(tx_buffer->skb, napi_budget);
6647
6648 /* unmap skb header data */
6649 dma_unmap_single(tx_ring->dev,
6650 dma_unmap_addr(tx_buffer, dma),
6651 dma_unmap_len(tx_buffer, len),
6652 DMA_TO_DEVICE);
6653
6654 /* clear tx_buffer data */
6655 tx_buffer->skb = NULL;
6656 dma_unmap_len_set(tx_buffer, len, 0);
6657
6658 /* clear last DMA location and unmap remaining buffers */
6659 while (tx_desc != eop_desc) {
6660 tx_buffer++;
6661 tx_desc++;
6662 i++;
6663 if (unlikely(!i)) {
6664 i -= tx_ring->count;
6665 tx_buffer = tx_ring->tx_buffer_info;
6666 tx_desc = IGB_TX_DESC(tx_ring, 0);
6667 }
6668
6669 /* unmap any remaining paged data */
6670 if (dma_unmap_len(tx_buffer, len)) {
6671 dma_unmap_page(tx_ring->dev,
6672 dma_unmap_addr(tx_buffer, dma),
6673 dma_unmap_len(tx_buffer, len),
6674 DMA_TO_DEVICE);
6675 dma_unmap_len_set(tx_buffer, len, 0);
6676 }
6677 }
6678
6679 /* move us one more past the eop_desc for start of next pkt */
6680 tx_buffer++;
6681 tx_desc++;
6682 i++;
6683 if (unlikely(!i)) {
6684 i -= tx_ring->count;
6685 tx_buffer = tx_ring->tx_buffer_info;
6686 tx_desc = IGB_TX_DESC(tx_ring, 0);
6687 }
6688
6689 /* issue prefetch for next Tx descriptor */
6690 prefetch(tx_desc);
6691
6692 /* update budget accounting */
6693 budget--;
6694 } while (likely(budget));
6695
6696 netdev_tx_completed_queue(txring_txq(tx_ring),
6697 total_packets, total_bytes);
6698 i += tx_ring->count;
6699 tx_ring->next_to_clean = i;
6700 u64_stats_update_begin(&tx_ring->tx_syncp);
6701 tx_ring->tx_stats.bytes += total_bytes;
6702 tx_ring->tx_stats.packets += total_packets;
6703 u64_stats_update_end(&tx_ring->tx_syncp);
6704 q_vector->tx.total_bytes += total_bytes;
6705 q_vector->tx.total_packets += total_packets;
6706
6707 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6708 struct e1000_hw *hw = &adapter->hw;
6709
6710 /* Detect a transmit hang in hardware, this serializes the
6711 * check with the clearing of time_stamp and movement of i
6712 */
6713 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6714 if (tx_buffer->next_to_watch &&
6715 time_after(jiffies, tx_buffer->time_stamp +
6716 (adapter->tx_timeout_factor * HZ)) &&
6717 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6718
6719 /* detected Tx unit hang */
6720 dev_err(tx_ring->dev,
6721 "Detected Tx Unit Hang\n"
6722 " Tx Queue <%d>\n"
6723 " TDH <%x>\n"
6724 " TDT <%x>\n"
6725 " next_to_use <%x>\n"
6726 " next_to_clean <%x>\n"
6727 "buffer_info[next_to_clean]\n"
6728 " time_stamp <%lx>\n"
6729 " next_to_watch <%p>\n"
6730 " jiffies <%lx>\n"
6731 " desc.status <%x>\n",
6732 tx_ring->queue_index,
6733 rd32(E1000_TDH(tx_ring->reg_idx)),
6734 readl(tx_ring->tail),
6735 tx_ring->next_to_use,
6736 tx_ring->next_to_clean,
6737 tx_buffer->time_stamp,
6738 tx_buffer->next_to_watch,
6739 jiffies,
6740 tx_buffer->next_to_watch->wb.status);
6741 netif_stop_subqueue(tx_ring->netdev,
6742 tx_ring->queue_index);
6743
6744 /* we are about to reset, no point in enabling stuff */
6745 return true;
6746 }
6747 }
6748
6749 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6750 if (unlikely(total_packets &&
6751 netif_carrier_ok(tx_ring->netdev) &&
6752 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6753 /* Make sure that anybody stopping the queue after this
6754 * sees the new next_to_clean.
6755 */
6756 smp_mb();
6757 if (__netif_subqueue_stopped(tx_ring->netdev,
6758 tx_ring->queue_index) &&
6759 !(test_bit(__IGB_DOWN, &adapter->state))) {
6760 netif_wake_subqueue(tx_ring->netdev,
6761 tx_ring->queue_index);
6762
6763 u64_stats_update_begin(&tx_ring->tx_syncp);
6764 tx_ring->tx_stats.restart_queue++;
6765 u64_stats_update_end(&tx_ring->tx_syncp);
6766 }
6767 }
6768
6769 return !!budget;
6770 }
6771
6772 /**
6773 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6774 * @rx_ring: rx descriptor ring to store buffers on
6775 * @old_buff: donor buffer to have page reused
6776 *
6777 * Synchronizes page for reuse by the adapter
6778 **/
6779 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6780 struct igb_rx_buffer *old_buff)
6781 {
6782 struct igb_rx_buffer *new_buff;
6783 u16 nta = rx_ring->next_to_alloc;
6784
6785 new_buff = &rx_ring->rx_buffer_info[nta];
6786
6787 /* update, and store next to alloc */
6788 nta++;
6789 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6790
6791 /* transfer page from old buffer to new buffer */
6792 *new_buff = *old_buff;
6793
6794 /* sync the buffer for use by the device */
6795 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6796 old_buff->page_offset,
6797 IGB_RX_BUFSZ,
6798 DMA_FROM_DEVICE);
6799 }
6800
6801 static inline bool igb_page_is_reserved(struct page *page)
6802 {
6803 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
6804 }
6805
6806 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6807 struct page *page,
6808 unsigned int truesize)
6809 {
6810 /* avoid re-using remote pages */
6811 if (unlikely(igb_page_is_reserved(page)))
6812 return false;
6813
6814 #if (PAGE_SIZE < 8192)
6815 /* if we are only owner of page we can reuse it */
6816 if (unlikely(page_count(page) != 1))
6817 return false;
6818
6819 /* flip page offset to other buffer */
6820 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6821 #else
6822 /* move offset up to the next cache line */
6823 rx_buffer->page_offset += truesize;
6824
6825 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6826 return false;
6827 #endif
6828
6829 /* Even if we own the page, we are not allowed to use atomic_set()
6830 * This would break get_page_unless_zero() users.
6831 */
6832 page_ref_inc(page);
6833
6834 return true;
6835 }
6836
6837 /**
6838 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6839 * @rx_ring: rx descriptor ring to transact packets on
6840 * @rx_buffer: buffer containing page to add
6841 * @rx_desc: descriptor containing length of buffer written by hardware
6842 * @skb: sk_buff to place the data into
6843 *
6844 * This function will add the data contained in rx_buffer->page to the skb.
6845 * This is done either through a direct copy if the data in the buffer is
6846 * less than the skb header size, otherwise it will just attach the page as
6847 * a frag to the skb.
6848 *
6849 * The function will then update the page offset if necessary and return
6850 * true if the buffer can be reused by the adapter.
6851 **/
6852 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6853 struct igb_rx_buffer *rx_buffer,
6854 union e1000_adv_rx_desc *rx_desc,
6855 struct sk_buff *skb)
6856 {
6857 struct page *page = rx_buffer->page;
6858 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6859 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6860 #if (PAGE_SIZE < 8192)
6861 unsigned int truesize = IGB_RX_BUFSZ;
6862 #else
6863 unsigned int truesize = SKB_DATA_ALIGN(size);
6864 #endif
6865 unsigned int pull_len;
6866
6867 if (unlikely(skb_is_nonlinear(skb)))
6868 goto add_tail_frag;
6869
6870 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6871 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6872 va += IGB_TS_HDR_LEN;
6873 size -= IGB_TS_HDR_LEN;
6874 }
6875
6876 if (likely(size <= IGB_RX_HDR_LEN)) {
6877 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6878
6879 /* page is not reserved, we can reuse buffer as-is */
6880 if (likely(!igb_page_is_reserved(page)))
6881 return true;
6882
6883 /* this page cannot be reused so discard it */
6884 __free_page(page);
6885 return false;
6886 }
6887
6888 /* we need the header to contain the greater of either ETH_HLEN or
6889 * 60 bytes if the skb->len is less than 60 for skb_pad.
6890 */
6891 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6892
6893 /* align pull length to size of long to optimize memcpy performance */
6894 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6895
6896 /* update all of the pointers */
6897 va += pull_len;
6898 size -= pull_len;
6899
6900 add_tail_frag:
6901 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6902 (unsigned long)va & ~PAGE_MASK, size, truesize);
6903
6904 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6905 }
6906
6907 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6908 union e1000_adv_rx_desc *rx_desc,
6909 struct sk_buff *skb)
6910 {
6911 struct igb_rx_buffer *rx_buffer;
6912 struct page *page;
6913
6914 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6915 page = rx_buffer->page;
6916 prefetchw(page);
6917
6918 if (likely(!skb)) {
6919 void *page_addr = page_address(page) +
6920 rx_buffer->page_offset;
6921
6922 /* prefetch first cache line of first page */
6923 prefetch(page_addr);
6924 #if L1_CACHE_BYTES < 128
6925 prefetch(page_addr + L1_CACHE_BYTES);
6926 #endif
6927
6928 /* allocate a skb to store the frags */
6929 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6930 if (unlikely(!skb)) {
6931 rx_ring->rx_stats.alloc_failed++;
6932 return NULL;
6933 }
6934
6935 /* we will be copying header into skb->data in
6936 * pskb_may_pull so it is in our interest to prefetch
6937 * it now to avoid a possible cache miss
6938 */
6939 prefetchw(skb->data);
6940 }
6941
6942 /* we are reusing so sync this buffer for CPU use */
6943 dma_sync_single_range_for_cpu(rx_ring->dev,
6944 rx_buffer->dma,
6945 rx_buffer->page_offset,
6946 IGB_RX_BUFSZ,
6947 DMA_FROM_DEVICE);
6948
6949 /* pull page into skb */
6950 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6951 /* hand second half of page back to the ring */
6952 igb_reuse_rx_page(rx_ring, rx_buffer);
6953 } else {
6954 /* we are not reusing the buffer so unmap it */
6955 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6956 PAGE_SIZE, DMA_FROM_DEVICE);
6957 }
6958
6959 /* clear contents of rx_buffer */
6960 rx_buffer->page = NULL;
6961
6962 return skb;
6963 }
6964
6965 static inline void igb_rx_checksum(struct igb_ring *ring,
6966 union e1000_adv_rx_desc *rx_desc,
6967 struct sk_buff *skb)
6968 {
6969 skb_checksum_none_assert(skb);
6970
6971 /* Ignore Checksum bit is set */
6972 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6973 return;
6974
6975 /* Rx checksum disabled via ethtool */
6976 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6977 return;
6978
6979 /* TCP/UDP checksum error bit is set */
6980 if (igb_test_staterr(rx_desc,
6981 E1000_RXDEXT_STATERR_TCPE |
6982 E1000_RXDEXT_STATERR_IPE)) {
6983 /* work around errata with sctp packets where the TCPE aka
6984 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6985 * packets, (aka let the stack check the crc32c)
6986 */
6987 if (!((skb->len == 60) &&
6988 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6989 u64_stats_update_begin(&ring->rx_syncp);
6990 ring->rx_stats.csum_err++;
6991 u64_stats_update_end(&ring->rx_syncp);
6992 }
6993 /* let the stack verify checksum errors */
6994 return;
6995 }
6996 /* It must be a TCP or UDP packet with a valid checksum */
6997 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6998 E1000_RXD_STAT_UDPCS))
6999 skb->ip_summed = CHECKSUM_UNNECESSARY;
7000
7001 dev_dbg(ring->dev, "cksum success: bits %08X\n",
7002 le32_to_cpu(rx_desc->wb.upper.status_error));
7003 }
7004
7005 static inline void igb_rx_hash(struct igb_ring *ring,
7006 union e1000_adv_rx_desc *rx_desc,
7007 struct sk_buff *skb)
7008 {
7009 if (ring->netdev->features & NETIF_F_RXHASH)
7010 skb_set_hash(skb,
7011 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
7012 PKT_HASH_TYPE_L3);
7013 }
7014
7015 /**
7016 * igb_is_non_eop - process handling of non-EOP buffers
7017 * @rx_ring: Rx ring being processed
7018 * @rx_desc: Rx descriptor for current buffer
7019 * @skb: current socket buffer containing buffer in progress
7020 *
7021 * This function updates next to clean. If the buffer is an EOP buffer
7022 * this function exits returning false, otherwise it will place the
7023 * sk_buff in the next buffer to be chained and return true indicating
7024 * that this is in fact a non-EOP buffer.
7025 **/
7026 static bool igb_is_non_eop(struct igb_ring *rx_ring,
7027 union e1000_adv_rx_desc *rx_desc)
7028 {
7029 u32 ntc = rx_ring->next_to_clean + 1;
7030
7031 /* fetch, update, and store next to clean */
7032 ntc = (ntc < rx_ring->count) ? ntc : 0;
7033 rx_ring->next_to_clean = ntc;
7034
7035 prefetch(IGB_RX_DESC(rx_ring, ntc));
7036
7037 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
7038 return false;
7039
7040 return true;
7041 }
7042
7043 /**
7044 * igb_cleanup_headers - Correct corrupted or empty headers
7045 * @rx_ring: rx descriptor ring packet is being transacted on
7046 * @rx_desc: pointer to the EOP Rx descriptor
7047 * @skb: pointer to current skb being fixed
7048 *
7049 * Address the case where we are pulling data in on pages only
7050 * and as such no data is present in the skb header.
7051 *
7052 * In addition if skb is not at least 60 bytes we need to pad it so that
7053 * it is large enough to qualify as a valid Ethernet frame.
7054 *
7055 * Returns true if an error was encountered and skb was freed.
7056 **/
7057 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
7058 union e1000_adv_rx_desc *rx_desc,
7059 struct sk_buff *skb)
7060 {
7061 if (unlikely((igb_test_staterr(rx_desc,
7062 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
7063 struct net_device *netdev = rx_ring->netdev;
7064 if (!(netdev->features & NETIF_F_RXALL)) {
7065 dev_kfree_skb_any(skb);
7066 return true;
7067 }
7068 }
7069
7070 /* if eth_skb_pad returns an error the skb was freed */
7071 if (eth_skb_pad(skb))
7072 return true;
7073
7074 return false;
7075 }
7076
7077 /**
7078 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
7079 * @rx_ring: rx descriptor ring packet is being transacted on
7080 * @rx_desc: pointer to the EOP Rx descriptor
7081 * @skb: pointer to current skb being populated
7082 *
7083 * This function checks the ring, descriptor, and packet information in
7084 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
7085 * other fields within the skb.
7086 **/
7087 static void igb_process_skb_fields(struct igb_ring *rx_ring,
7088 union e1000_adv_rx_desc *rx_desc,
7089 struct sk_buff *skb)
7090 {
7091 struct net_device *dev = rx_ring->netdev;
7092
7093 igb_rx_hash(rx_ring, rx_desc, skb);
7094
7095 igb_rx_checksum(rx_ring, rx_desc, skb);
7096
7097 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7098 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7099 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
7100
7101 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
7102 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7103 u16 vid;
7104
7105 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7106 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7107 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7108 else
7109 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7110
7111 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
7112 }
7113
7114 skb_record_rx_queue(skb, rx_ring->queue_index);
7115
7116 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7117 }
7118
7119 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
7120 {
7121 struct igb_ring *rx_ring = q_vector->rx.ring;
7122 struct sk_buff *skb = rx_ring->skb;
7123 unsigned int total_bytes = 0, total_packets = 0;
7124 u16 cleaned_count = igb_desc_unused(rx_ring);
7125
7126 while (likely(total_packets < budget)) {
7127 union e1000_adv_rx_desc *rx_desc;
7128
7129 /* return some buffers to hardware, one at a time is too slow */
7130 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7131 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7132 cleaned_count = 0;
7133 }
7134
7135 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
7136
7137 if (!rx_desc->wb.upper.status_error)
7138 break;
7139
7140 /* This memory barrier is needed to keep us from reading
7141 * any other fields out of the rx_desc until we know the
7142 * descriptor has been written back
7143 */
7144 dma_rmb();
7145
7146 /* retrieve a buffer from the ring */
7147 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
7148
7149 /* exit if we failed to retrieve a buffer */
7150 if (!skb)
7151 break;
7152
7153 cleaned_count++;
7154
7155 /* fetch next buffer in frame if non-eop */
7156 if (igb_is_non_eop(rx_ring, rx_desc))
7157 continue;
7158
7159 /* verify the packet layout is correct */
7160 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7161 skb = NULL;
7162 continue;
7163 }
7164
7165 /* probably a little skewed due to removing CRC */
7166 total_bytes += skb->len;
7167
7168 /* populate checksum, timestamp, VLAN, and protocol */
7169 igb_process_skb_fields(rx_ring, rx_desc, skb);
7170
7171 napi_gro_receive(&q_vector->napi, skb);
7172
7173 /* reset skb pointer */
7174 skb = NULL;
7175
7176 /* update budget accounting */
7177 total_packets++;
7178 }
7179
7180 /* place incomplete frames back on ring for completion */
7181 rx_ring->skb = skb;
7182
7183 u64_stats_update_begin(&rx_ring->rx_syncp);
7184 rx_ring->rx_stats.packets += total_packets;
7185 rx_ring->rx_stats.bytes += total_bytes;
7186 u64_stats_update_end(&rx_ring->rx_syncp);
7187 q_vector->rx.total_packets += total_packets;
7188 q_vector->rx.total_bytes += total_bytes;
7189
7190 if (cleaned_count)
7191 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7192
7193 return total_packets;
7194 }
7195
7196 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
7197 struct igb_rx_buffer *bi)
7198 {
7199 struct page *page = bi->page;
7200 dma_addr_t dma;
7201
7202 /* since we are recycling buffers we should seldom need to alloc */
7203 if (likely(page))
7204 return true;
7205
7206 /* alloc new page for storage */
7207 page = dev_alloc_page();
7208 if (unlikely(!page)) {
7209 rx_ring->rx_stats.alloc_failed++;
7210 return false;
7211 }
7212
7213 /* map page for use */
7214 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
7215
7216 /* if mapping failed free memory back to system since
7217 * there isn't much point in holding memory we can't use
7218 */
7219 if (dma_mapping_error(rx_ring->dev, dma)) {
7220 __free_page(page);
7221
7222 rx_ring->rx_stats.alloc_failed++;
7223 return false;
7224 }
7225
7226 bi->dma = dma;
7227 bi->page = page;
7228 bi->page_offset = 0;
7229
7230 return true;
7231 }
7232
7233 /**
7234 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7235 * @adapter: address of board private structure
7236 **/
7237 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7238 {
7239 union e1000_adv_rx_desc *rx_desc;
7240 struct igb_rx_buffer *bi;
7241 u16 i = rx_ring->next_to_use;
7242
7243 /* nothing to do */
7244 if (!cleaned_count)
7245 return;
7246
7247 rx_desc = IGB_RX_DESC(rx_ring, i);
7248 bi = &rx_ring->rx_buffer_info[i];
7249 i -= rx_ring->count;
7250
7251 do {
7252 if (!igb_alloc_mapped_page(rx_ring, bi))
7253 break;
7254
7255 /* Refresh the desc even if buffer_addrs didn't change
7256 * because each write-back erases this info.
7257 */
7258 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7259
7260 rx_desc++;
7261 bi++;
7262 i++;
7263 if (unlikely(!i)) {
7264 rx_desc = IGB_RX_DESC(rx_ring, 0);
7265 bi = rx_ring->rx_buffer_info;
7266 i -= rx_ring->count;
7267 }
7268
7269 /* clear the status bits for the next_to_use descriptor */
7270 rx_desc->wb.upper.status_error = 0;
7271
7272 cleaned_count--;
7273 } while (cleaned_count);
7274
7275 i += rx_ring->count;
7276
7277 if (rx_ring->next_to_use != i) {
7278 /* record the next descriptor to use */
7279 rx_ring->next_to_use = i;
7280
7281 /* update next to alloc since we have filled the ring */
7282 rx_ring->next_to_alloc = i;
7283
7284 /* Force memory writes to complete before letting h/w
7285 * know there are new descriptors to fetch. (Only
7286 * applicable for weak-ordered memory model archs,
7287 * such as IA-64).
7288 */
7289 wmb();
7290 writel(i, rx_ring->tail);
7291 }
7292 }
7293
7294 /**
7295 * igb_mii_ioctl -
7296 * @netdev:
7297 * @ifreq:
7298 * @cmd:
7299 **/
7300 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7301 {
7302 struct igb_adapter *adapter = netdev_priv(netdev);
7303 struct mii_ioctl_data *data = if_mii(ifr);
7304
7305 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7306 return -EOPNOTSUPP;
7307
7308 switch (cmd) {
7309 case SIOCGMIIPHY:
7310 data->phy_id = adapter->hw.phy.addr;
7311 break;
7312 case SIOCGMIIREG:
7313 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7314 &data->val_out))
7315 return -EIO;
7316 break;
7317 case SIOCSMIIREG:
7318 default:
7319 return -EOPNOTSUPP;
7320 }
7321 return 0;
7322 }
7323
7324 /**
7325 * igb_ioctl -
7326 * @netdev:
7327 * @ifreq:
7328 * @cmd:
7329 **/
7330 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7331 {
7332 switch (cmd) {
7333 case SIOCGMIIPHY:
7334 case SIOCGMIIREG:
7335 case SIOCSMIIREG:
7336 return igb_mii_ioctl(netdev, ifr, cmd);
7337 case SIOCGHWTSTAMP:
7338 return igb_ptp_get_ts_config(netdev, ifr);
7339 case SIOCSHWTSTAMP:
7340 return igb_ptp_set_ts_config(netdev, ifr);
7341 default:
7342 return -EOPNOTSUPP;
7343 }
7344 }
7345
7346 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7347 {
7348 struct igb_adapter *adapter = hw->back;
7349
7350 pci_read_config_word(adapter->pdev, reg, value);
7351 }
7352
7353 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7354 {
7355 struct igb_adapter *adapter = hw->back;
7356
7357 pci_write_config_word(adapter->pdev, reg, *value);
7358 }
7359
7360 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7361 {
7362 struct igb_adapter *adapter = hw->back;
7363
7364 if (pcie_capability_read_word(adapter->pdev, reg, value))
7365 return -E1000_ERR_CONFIG;
7366
7367 return 0;
7368 }
7369
7370 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7371 {
7372 struct igb_adapter *adapter = hw->back;
7373
7374 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7375 return -E1000_ERR_CONFIG;
7376
7377 return 0;
7378 }
7379
7380 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7381 {
7382 struct igb_adapter *adapter = netdev_priv(netdev);
7383 struct e1000_hw *hw = &adapter->hw;
7384 u32 ctrl, rctl;
7385 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7386
7387 if (enable) {
7388 /* enable VLAN tag insert/strip */
7389 ctrl = rd32(E1000_CTRL);
7390 ctrl |= E1000_CTRL_VME;
7391 wr32(E1000_CTRL, ctrl);
7392
7393 /* Disable CFI check */
7394 rctl = rd32(E1000_RCTL);
7395 rctl &= ~E1000_RCTL_CFIEN;
7396 wr32(E1000_RCTL, rctl);
7397 } else {
7398 /* disable VLAN tag insert/strip */
7399 ctrl = rd32(E1000_CTRL);
7400 ctrl &= ~E1000_CTRL_VME;
7401 wr32(E1000_CTRL, ctrl);
7402 }
7403
7404 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
7405 }
7406
7407 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7408 __be16 proto, u16 vid)
7409 {
7410 struct igb_adapter *adapter = netdev_priv(netdev);
7411 struct e1000_hw *hw = &adapter->hw;
7412 int pf_id = adapter->vfs_allocated_count;
7413
7414 /* add the filter since PF can receive vlans w/o entry in vlvf */
7415 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7416 igb_vfta_set(hw, vid, pf_id, true, !!vid);
7417
7418 set_bit(vid, adapter->active_vlans);
7419
7420 return 0;
7421 }
7422
7423 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7424 __be16 proto, u16 vid)
7425 {
7426 struct igb_adapter *adapter = netdev_priv(netdev);
7427 int pf_id = adapter->vfs_allocated_count;
7428 struct e1000_hw *hw = &adapter->hw;
7429
7430 /* remove VID from filter table */
7431 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7432 igb_vfta_set(hw, vid, pf_id, false, true);
7433
7434 clear_bit(vid, adapter->active_vlans);
7435
7436 return 0;
7437 }
7438
7439 static void igb_restore_vlan(struct igb_adapter *adapter)
7440 {
7441 u16 vid = 1;
7442
7443 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7444 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
7445
7446 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
7447 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7448 }
7449
7450 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7451 {
7452 struct pci_dev *pdev = adapter->pdev;
7453 struct e1000_mac_info *mac = &adapter->hw.mac;
7454
7455 mac->autoneg = 0;
7456
7457 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7458 * for the switch() below to work
7459 */
7460 if ((spd & 1) || (dplx & ~1))
7461 goto err_inval;
7462
7463 /* Fiber NIC's only allow 1000 gbps Full duplex
7464 * and 100Mbps Full duplex for 100baseFx sfp
7465 */
7466 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7467 switch (spd + dplx) {
7468 case SPEED_10 + DUPLEX_HALF:
7469 case SPEED_10 + DUPLEX_FULL:
7470 case SPEED_100 + DUPLEX_HALF:
7471 goto err_inval;
7472 default:
7473 break;
7474 }
7475 }
7476
7477 switch (spd + dplx) {
7478 case SPEED_10 + DUPLEX_HALF:
7479 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7480 break;
7481 case SPEED_10 + DUPLEX_FULL:
7482 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7483 break;
7484 case SPEED_100 + DUPLEX_HALF:
7485 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7486 break;
7487 case SPEED_100 + DUPLEX_FULL:
7488 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7489 break;
7490 case SPEED_1000 + DUPLEX_FULL:
7491 mac->autoneg = 1;
7492 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7493 break;
7494 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7495 default:
7496 goto err_inval;
7497 }
7498
7499 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7500 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7501
7502 return 0;
7503
7504 err_inval:
7505 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7506 return -EINVAL;
7507 }
7508
7509 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7510 bool runtime)
7511 {
7512 struct net_device *netdev = pci_get_drvdata(pdev);
7513 struct igb_adapter *adapter = netdev_priv(netdev);
7514 struct e1000_hw *hw = &adapter->hw;
7515 u32 ctrl, rctl, status;
7516 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7517 #ifdef CONFIG_PM
7518 int retval = 0;
7519 #endif
7520
7521 netif_device_detach(netdev);
7522
7523 if (netif_running(netdev))
7524 __igb_close(netdev, true);
7525
7526 igb_clear_interrupt_scheme(adapter);
7527
7528 #ifdef CONFIG_PM
7529 retval = pci_save_state(pdev);
7530 if (retval)
7531 return retval;
7532 #endif
7533
7534 status = rd32(E1000_STATUS);
7535 if (status & E1000_STATUS_LU)
7536 wufc &= ~E1000_WUFC_LNKC;
7537
7538 if (wufc) {
7539 igb_setup_rctl(adapter);
7540 igb_set_rx_mode(netdev);
7541
7542 /* turn on all-multi mode if wake on multicast is enabled */
7543 if (wufc & E1000_WUFC_MC) {
7544 rctl = rd32(E1000_RCTL);
7545 rctl |= E1000_RCTL_MPE;
7546 wr32(E1000_RCTL, rctl);
7547 }
7548
7549 ctrl = rd32(E1000_CTRL);
7550 /* advertise wake from D3Cold */
7551 #define E1000_CTRL_ADVD3WUC 0x00100000
7552 /* phy power management enable */
7553 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7554 ctrl |= E1000_CTRL_ADVD3WUC;
7555 wr32(E1000_CTRL, ctrl);
7556
7557 /* Allow time for pending master requests to run */
7558 igb_disable_pcie_master(hw);
7559
7560 wr32(E1000_WUC, E1000_WUC_PME_EN);
7561 wr32(E1000_WUFC, wufc);
7562 } else {
7563 wr32(E1000_WUC, 0);
7564 wr32(E1000_WUFC, 0);
7565 }
7566
7567 *enable_wake = wufc || adapter->en_mng_pt;
7568 if (!*enable_wake)
7569 igb_power_down_link(adapter);
7570 else
7571 igb_power_up_link(adapter);
7572
7573 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7574 * would have already happened in close and is redundant.
7575 */
7576 igb_release_hw_control(adapter);
7577
7578 pci_disable_device(pdev);
7579
7580 return 0;
7581 }
7582
7583 #ifdef CONFIG_PM
7584 #ifdef CONFIG_PM_SLEEP
7585 static int igb_suspend(struct device *dev)
7586 {
7587 int retval;
7588 bool wake;
7589 struct pci_dev *pdev = to_pci_dev(dev);
7590
7591 retval = __igb_shutdown(pdev, &wake, 0);
7592 if (retval)
7593 return retval;
7594
7595 if (wake) {
7596 pci_prepare_to_sleep(pdev);
7597 } else {
7598 pci_wake_from_d3(pdev, false);
7599 pci_set_power_state(pdev, PCI_D3hot);
7600 }
7601
7602 return 0;
7603 }
7604 #endif /* CONFIG_PM_SLEEP */
7605
7606 static int igb_resume(struct device *dev)
7607 {
7608 struct pci_dev *pdev = to_pci_dev(dev);
7609 struct net_device *netdev = pci_get_drvdata(pdev);
7610 struct igb_adapter *adapter = netdev_priv(netdev);
7611 struct e1000_hw *hw = &adapter->hw;
7612 u32 err;
7613
7614 pci_set_power_state(pdev, PCI_D0);
7615 pci_restore_state(pdev);
7616 pci_save_state(pdev);
7617
7618 if (!pci_device_is_present(pdev))
7619 return -ENODEV;
7620 err = pci_enable_device_mem(pdev);
7621 if (err) {
7622 dev_err(&pdev->dev,
7623 "igb: Cannot enable PCI device from suspend\n");
7624 return err;
7625 }
7626 pci_set_master(pdev);
7627
7628 pci_enable_wake(pdev, PCI_D3hot, 0);
7629 pci_enable_wake(pdev, PCI_D3cold, 0);
7630
7631 if (igb_init_interrupt_scheme(adapter, true)) {
7632 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7633 return -ENOMEM;
7634 }
7635
7636 igb_reset(adapter);
7637
7638 /* let the f/w know that the h/w is now under the control of the
7639 * driver.
7640 */
7641 igb_get_hw_control(adapter);
7642
7643 wr32(E1000_WUS, ~0);
7644
7645 if (netdev->flags & IFF_UP) {
7646 rtnl_lock();
7647 err = __igb_open(netdev, true);
7648 rtnl_unlock();
7649 if (err)
7650 return err;
7651 }
7652
7653 netif_device_attach(netdev);
7654 return 0;
7655 }
7656
7657 static int igb_runtime_idle(struct device *dev)
7658 {
7659 struct pci_dev *pdev = to_pci_dev(dev);
7660 struct net_device *netdev = pci_get_drvdata(pdev);
7661 struct igb_adapter *adapter = netdev_priv(netdev);
7662
7663 if (!igb_has_link(adapter))
7664 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7665
7666 return -EBUSY;
7667 }
7668
7669 static int igb_runtime_suspend(struct device *dev)
7670 {
7671 struct pci_dev *pdev = to_pci_dev(dev);
7672 int retval;
7673 bool wake;
7674
7675 retval = __igb_shutdown(pdev, &wake, 1);
7676 if (retval)
7677 return retval;
7678
7679 if (wake) {
7680 pci_prepare_to_sleep(pdev);
7681 } else {
7682 pci_wake_from_d3(pdev, false);
7683 pci_set_power_state(pdev, PCI_D3hot);
7684 }
7685
7686 return 0;
7687 }
7688
7689 static int igb_runtime_resume(struct device *dev)
7690 {
7691 return igb_resume(dev);
7692 }
7693 #endif /* CONFIG_PM */
7694
7695 static void igb_shutdown(struct pci_dev *pdev)
7696 {
7697 bool wake;
7698
7699 __igb_shutdown(pdev, &wake, 0);
7700
7701 if (system_state == SYSTEM_POWER_OFF) {
7702 pci_wake_from_d3(pdev, wake);
7703 pci_set_power_state(pdev, PCI_D3hot);
7704 }
7705 }
7706
7707 #ifdef CONFIG_PCI_IOV
7708 static int igb_sriov_reinit(struct pci_dev *dev)
7709 {
7710 struct net_device *netdev = pci_get_drvdata(dev);
7711 struct igb_adapter *adapter = netdev_priv(netdev);
7712 struct pci_dev *pdev = adapter->pdev;
7713
7714 rtnl_lock();
7715
7716 if (netif_running(netdev))
7717 igb_close(netdev);
7718 else
7719 igb_reset(adapter);
7720
7721 igb_clear_interrupt_scheme(adapter);
7722
7723 igb_init_queue_configuration(adapter);
7724
7725 if (igb_init_interrupt_scheme(adapter, true)) {
7726 rtnl_unlock();
7727 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7728 return -ENOMEM;
7729 }
7730
7731 if (netif_running(netdev))
7732 igb_open(netdev);
7733
7734 rtnl_unlock();
7735
7736 return 0;
7737 }
7738
7739 static int igb_pci_disable_sriov(struct pci_dev *dev)
7740 {
7741 int err = igb_disable_sriov(dev);
7742
7743 if (!err)
7744 err = igb_sriov_reinit(dev);
7745
7746 return err;
7747 }
7748
7749 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7750 {
7751 int err = igb_enable_sriov(dev, num_vfs);
7752
7753 if (err)
7754 goto out;
7755
7756 err = igb_sriov_reinit(dev);
7757 if (!err)
7758 return num_vfs;
7759
7760 out:
7761 return err;
7762 }
7763
7764 #endif
7765 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7766 {
7767 #ifdef CONFIG_PCI_IOV
7768 if (num_vfs == 0)
7769 return igb_pci_disable_sriov(dev);
7770 else
7771 return igb_pci_enable_sriov(dev, num_vfs);
7772 #endif
7773 return 0;
7774 }
7775
7776 #ifdef CONFIG_NET_POLL_CONTROLLER
7777 /* Polling 'interrupt' - used by things like netconsole to send skbs
7778 * without having to re-enable interrupts. It's not called while
7779 * the interrupt routine is executing.
7780 */
7781 static void igb_netpoll(struct net_device *netdev)
7782 {
7783 struct igb_adapter *adapter = netdev_priv(netdev);
7784 struct e1000_hw *hw = &adapter->hw;
7785 struct igb_q_vector *q_vector;
7786 int i;
7787
7788 for (i = 0; i < adapter->num_q_vectors; i++) {
7789 q_vector = adapter->q_vector[i];
7790 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7791 wr32(E1000_EIMC, q_vector->eims_value);
7792 else
7793 igb_irq_disable(adapter);
7794 napi_schedule(&q_vector->napi);
7795 }
7796 }
7797 #endif /* CONFIG_NET_POLL_CONTROLLER */
7798
7799 /**
7800 * igb_io_error_detected - called when PCI error is detected
7801 * @pdev: Pointer to PCI device
7802 * @state: The current pci connection state
7803 *
7804 * This function is called after a PCI bus error affecting
7805 * this device has been detected.
7806 **/
7807 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7808 pci_channel_state_t state)
7809 {
7810 struct net_device *netdev = pci_get_drvdata(pdev);
7811 struct igb_adapter *adapter = netdev_priv(netdev);
7812
7813 netif_device_detach(netdev);
7814
7815 if (state == pci_channel_io_perm_failure)
7816 return PCI_ERS_RESULT_DISCONNECT;
7817
7818 if (netif_running(netdev))
7819 igb_down(adapter);
7820 pci_disable_device(pdev);
7821
7822 /* Request a slot slot reset. */
7823 return PCI_ERS_RESULT_NEED_RESET;
7824 }
7825
7826 /**
7827 * igb_io_slot_reset - called after the pci bus has been reset.
7828 * @pdev: Pointer to PCI device
7829 *
7830 * Restart the card from scratch, as if from a cold-boot. Implementation
7831 * resembles the first-half of the igb_resume routine.
7832 **/
7833 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7834 {
7835 struct net_device *netdev = pci_get_drvdata(pdev);
7836 struct igb_adapter *adapter = netdev_priv(netdev);
7837 struct e1000_hw *hw = &adapter->hw;
7838 pci_ers_result_t result;
7839 int err;
7840
7841 if (pci_enable_device_mem(pdev)) {
7842 dev_err(&pdev->dev,
7843 "Cannot re-enable PCI device after reset.\n");
7844 result = PCI_ERS_RESULT_DISCONNECT;
7845 } else {
7846 pci_set_master(pdev);
7847 pci_restore_state(pdev);
7848 pci_save_state(pdev);
7849
7850 pci_enable_wake(pdev, PCI_D3hot, 0);
7851 pci_enable_wake(pdev, PCI_D3cold, 0);
7852
7853 igb_reset(adapter);
7854 wr32(E1000_WUS, ~0);
7855 result = PCI_ERS_RESULT_RECOVERED;
7856 }
7857
7858 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7859 if (err) {
7860 dev_err(&pdev->dev,
7861 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7862 err);
7863 /* non-fatal, continue */
7864 }
7865
7866 return result;
7867 }
7868
7869 /**
7870 * igb_io_resume - called when traffic can start flowing again.
7871 * @pdev: Pointer to PCI device
7872 *
7873 * This callback is called when the error recovery driver tells us that
7874 * its OK to resume normal operation. Implementation resembles the
7875 * second-half of the igb_resume routine.
7876 */
7877 static void igb_io_resume(struct pci_dev *pdev)
7878 {
7879 struct net_device *netdev = pci_get_drvdata(pdev);
7880 struct igb_adapter *adapter = netdev_priv(netdev);
7881
7882 if (netif_running(netdev)) {
7883 if (igb_up(adapter)) {
7884 dev_err(&pdev->dev, "igb_up failed after reset\n");
7885 return;
7886 }
7887 }
7888
7889 netif_device_attach(netdev);
7890
7891 /* let the f/w know that the h/w is now under the control of the
7892 * driver.
7893 */
7894 igb_get_hw_control(adapter);
7895 }
7896
7897 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7898 u8 qsel)
7899 {
7900 struct e1000_hw *hw = &adapter->hw;
7901 u32 rar_low, rar_high;
7902
7903 /* HW expects these to be in network order when they are plugged
7904 * into the registers which are little endian. In order to guarantee
7905 * that ordering we need to do an leXX_to_cpup here in order to be
7906 * ready for the byteswap that occurs with writel
7907 */
7908 rar_low = le32_to_cpup((__le32 *)(addr));
7909 rar_high = le16_to_cpup((__le16 *)(addr + 4));
7910
7911 /* Indicate to hardware the Address is Valid. */
7912 rar_high |= E1000_RAH_AV;
7913
7914 if (hw->mac.type == e1000_82575)
7915 rar_high |= E1000_RAH_POOL_1 * qsel;
7916 else
7917 rar_high |= E1000_RAH_POOL_1 << qsel;
7918
7919 wr32(E1000_RAL(index), rar_low);
7920 wrfl();
7921 wr32(E1000_RAH(index), rar_high);
7922 wrfl();
7923 }
7924
7925 static int igb_set_vf_mac(struct igb_adapter *adapter,
7926 int vf, unsigned char *mac_addr)
7927 {
7928 struct e1000_hw *hw = &adapter->hw;
7929 /* VF MAC addresses start at end of receive addresses and moves
7930 * towards the first, as a result a collision should not be possible
7931 */
7932 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7933
7934 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7935
7936 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7937
7938 return 0;
7939 }
7940
7941 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7942 {
7943 struct igb_adapter *adapter = netdev_priv(netdev);
7944 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7945 return -EINVAL;
7946 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7947 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7948 dev_info(&adapter->pdev->dev,
7949 "Reload the VF driver to make this change effective.");
7950 if (test_bit(__IGB_DOWN, &adapter->state)) {
7951 dev_warn(&adapter->pdev->dev,
7952 "The VF MAC address has been set, but the PF device is not up.\n");
7953 dev_warn(&adapter->pdev->dev,
7954 "Bring the PF device up before attempting to use the VF device.\n");
7955 }
7956 return igb_set_vf_mac(adapter, vf, mac);
7957 }
7958
7959 static int igb_link_mbps(int internal_link_speed)
7960 {
7961 switch (internal_link_speed) {
7962 case SPEED_100:
7963 return 100;
7964 case SPEED_1000:
7965 return 1000;
7966 default:
7967 return 0;
7968 }
7969 }
7970
7971 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7972 int link_speed)
7973 {
7974 int rf_dec, rf_int;
7975 u32 bcnrc_val;
7976
7977 if (tx_rate != 0) {
7978 /* Calculate the rate factor values to set */
7979 rf_int = link_speed / tx_rate;
7980 rf_dec = (link_speed - (rf_int * tx_rate));
7981 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
7982 tx_rate;
7983
7984 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7985 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7986 E1000_RTTBCNRC_RF_INT_MASK);
7987 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7988 } else {
7989 bcnrc_val = 0;
7990 }
7991
7992 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7993 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7994 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7995 */
7996 wr32(E1000_RTTBCNRM, 0x14);
7997 wr32(E1000_RTTBCNRC, bcnrc_val);
7998 }
7999
8000 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
8001 {
8002 int actual_link_speed, i;
8003 bool reset_rate = false;
8004
8005 /* VF TX rate limit was not set or not supported */
8006 if ((adapter->vf_rate_link_speed == 0) ||
8007 (adapter->hw.mac.type != e1000_82576))
8008 return;
8009
8010 actual_link_speed = igb_link_mbps(adapter->link_speed);
8011 if (actual_link_speed != adapter->vf_rate_link_speed) {
8012 reset_rate = true;
8013 adapter->vf_rate_link_speed = 0;
8014 dev_info(&adapter->pdev->dev,
8015 "Link speed has been changed. VF Transmit rate is disabled\n");
8016 }
8017
8018 for (i = 0; i < adapter->vfs_allocated_count; i++) {
8019 if (reset_rate)
8020 adapter->vf_data[i].tx_rate = 0;
8021
8022 igb_set_vf_rate_limit(&adapter->hw, i,
8023 adapter->vf_data[i].tx_rate,
8024 actual_link_speed);
8025 }
8026 }
8027
8028 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
8029 int min_tx_rate, int max_tx_rate)
8030 {
8031 struct igb_adapter *adapter = netdev_priv(netdev);
8032 struct e1000_hw *hw = &adapter->hw;
8033 int actual_link_speed;
8034
8035 if (hw->mac.type != e1000_82576)
8036 return -EOPNOTSUPP;
8037
8038 if (min_tx_rate)
8039 return -EINVAL;
8040
8041 actual_link_speed = igb_link_mbps(adapter->link_speed);
8042 if ((vf >= adapter->vfs_allocated_count) ||
8043 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
8044 (max_tx_rate < 0) ||
8045 (max_tx_rate > actual_link_speed))
8046 return -EINVAL;
8047
8048 adapter->vf_rate_link_speed = actual_link_speed;
8049 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
8050 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
8051
8052 return 0;
8053 }
8054
8055 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
8056 bool setting)
8057 {
8058 struct igb_adapter *adapter = netdev_priv(netdev);
8059 struct e1000_hw *hw = &adapter->hw;
8060 u32 reg_val, reg_offset;
8061
8062 if (!adapter->vfs_allocated_count)
8063 return -EOPNOTSUPP;
8064
8065 if (vf >= adapter->vfs_allocated_count)
8066 return -EINVAL;
8067
8068 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
8069 reg_val = rd32(reg_offset);
8070 if (setting)
8071 reg_val |= (BIT(vf) |
8072 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
8073 else
8074 reg_val &= ~(BIT(vf) |
8075 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
8076 wr32(reg_offset, reg_val);
8077
8078 adapter->vf_data[vf].spoofchk_enabled = setting;
8079 return 0;
8080 }
8081
8082 static int igb_ndo_get_vf_config(struct net_device *netdev,
8083 int vf, struct ifla_vf_info *ivi)
8084 {
8085 struct igb_adapter *adapter = netdev_priv(netdev);
8086 if (vf >= adapter->vfs_allocated_count)
8087 return -EINVAL;
8088 ivi->vf = vf;
8089 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
8090 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8091 ivi->min_tx_rate = 0;
8092 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8093 ivi->qos = adapter->vf_data[vf].pf_qos;
8094 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8095 return 0;
8096 }
8097
8098 static void igb_vmm_control(struct igb_adapter *adapter)
8099 {
8100 struct e1000_hw *hw = &adapter->hw;
8101 u32 reg;
8102
8103 switch (hw->mac.type) {
8104 case e1000_82575:
8105 case e1000_i210:
8106 case e1000_i211:
8107 case e1000_i354:
8108 default:
8109 /* replication is not supported for 82575 */
8110 return;
8111 case e1000_82576:
8112 /* notify HW that the MAC is adding vlan tags */
8113 reg = rd32(E1000_DTXCTL);
8114 reg |= E1000_DTXCTL_VLAN_ADDED;
8115 wr32(E1000_DTXCTL, reg);
8116 /* Fall through */
8117 case e1000_82580:
8118 /* enable replication vlan tag stripping */
8119 reg = rd32(E1000_RPLOLR);
8120 reg |= E1000_RPLOLR_STRVLAN;
8121 wr32(E1000_RPLOLR, reg);
8122 /* Fall through */
8123 case e1000_i350:
8124 /* none of the above registers are supported by i350 */
8125 break;
8126 }
8127
8128 if (adapter->vfs_allocated_count) {
8129 igb_vmdq_set_loopback_pf(hw, true);
8130 igb_vmdq_set_replication_pf(hw, true);
8131 igb_vmdq_set_anti_spoofing_pf(hw, true,
8132 adapter->vfs_allocated_count);
8133 } else {
8134 igb_vmdq_set_loopback_pf(hw, false);
8135 igb_vmdq_set_replication_pf(hw, false);
8136 }
8137 }
8138
8139 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8140 {
8141 struct e1000_hw *hw = &adapter->hw;
8142 u32 dmac_thr;
8143 u16 hwm;
8144
8145 if (hw->mac.type > e1000_82580) {
8146 if (adapter->flags & IGB_FLAG_DMAC) {
8147 u32 reg;
8148
8149 /* force threshold to 0. */
8150 wr32(E1000_DMCTXTH, 0);
8151
8152 /* DMA Coalescing high water mark needs to be greater
8153 * than the Rx threshold. Set hwm to PBA - max frame
8154 * size in 16B units, capping it at PBA - 6KB.
8155 */
8156 hwm = 64 * (pba - 6);
8157 reg = rd32(E1000_FCRTC);
8158 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8159 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8160 & E1000_FCRTC_RTH_COAL_MASK);
8161 wr32(E1000_FCRTC, reg);
8162
8163 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
8164 * frame size, capping it at PBA - 10KB.
8165 */
8166 dmac_thr = pba - 10;
8167 reg = rd32(E1000_DMACR);
8168 reg &= ~E1000_DMACR_DMACTHR_MASK;
8169 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8170 & E1000_DMACR_DMACTHR_MASK);
8171
8172 /* transition to L0x or L1 if available..*/
8173 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8174
8175 /* watchdog timer= +-1000 usec in 32usec intervals */
8176 reg |= (1000 >> 5);
8177
8178 /* Disable BMC-to-OS Watchdog Enable */
8179 if (hw->mac.type != e1000_i354)
8180 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8181
8182 wr32(E1000_DMACR, reg);
8183
8184 /* no lower threshold to disable
8185 * coalescing(smart fifb)-UTRESH=0
8186 */
8187 wr32(E1000_DMCRTRH, 0);
8188
8189 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8190
8191 wr32(E1000_DMCTLX, reg);
8192
8193 /* free space in tx packet buffer to wake from
8194 * DMA coal
8195 */
8196 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8197 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8198
8199 /* make low power state decision controlled
8200 * by DMA coal
8201 */
8202 reg = rd32(E1000_PCIEMISC);
8203 reg &= ~E1000_PCIEMISC_LX_DECISION;
8204 wr32(E1000_PCIEMISC, reg);
8205 } /* endif adapter->dmac is not disabled */
8206 } else if (hw->mac.type == e1000_82580) {
8207 u32 reg = rd32(E1000_PCIEMISC);
8208
8209 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8210 wr32(E1000_DMACR, 0);
8211 }
8212 }
8213
8214 /**
8215 * igb_read_i2c_byte - Reads 8 bit word over I2C
8216 * @hw: pointer to hardware structure
8217 * @byte_offset: byte offset to read
8218 * @dev_addr: device address
8219 * @data: value read
8220 *
8221 * Performs byte read operation over I2C interface at
8222 * a specified device address.
8223 **/
8224 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8225 u8 dev_addr, u8 *data)
8226 {
8227 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8228 struct i2c_client *this_client = adapter->i2c_client;
8229 s32 status;
8230 u16 swfw_mask = 0;
8231
8232 if (!this_client)
8233 return E1000_ERR_I2C;
8234
8235 swfw_mask = E1000_SWFW_PHY0_SM;
8236
8237 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8238 return E1000_ERR_SWFW_SYNC;
8239
8240 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8241 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8242
8243 if (status < 0)
8244 return E1000_ERR_I2C;
8245 else {
8246 *data = status;
8247 return 0;
8248 }
8249 }
8250
8251 /**
8252 * igb_write_i2c_byte - Writes 8 bit word over I2C
8253 * @hw: pointer to hardware structure
8254 * @byte_offset: byte offset to write
8255 * @dev_addr: device address
8256 * @data: value to write
8257 *
8258 * Performs byte write operation over I2C interface at
8259 * a specified device address.
8260 **/
8261 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8262 u8 dev_addr, u8 data)
8263 {
8264 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8265 struct i2c_client *this_client = adapter->i2c_client;
8266 s32 status;
8267 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8268
8269 if (!this_client)
8270 return E1000_ERR_I2C;
8271
8272 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8273 return E1000_ERR_SWFW_SYNC;
8274 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8275 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8276
8277 if (status)
8278 return E1000_ERR_I2C;
8279 else
8280 return 0;
8281
8282 }
8283
8284 int igb_reinit_queues(struct igb_adapter *adapter)
8285 {
8286 struct net_device *netdev = adapter->netdev;
8287 struct pci_dev *pdev = adapter->pdev;
8288 int err = 0;
8289
8290 if (netif_running(netdev))
8291 igb_close(netdev);
8292
8293 igb_reset_interrupt_capability(adapter);
8294
8295 if (igb_init_interrupt_scheme(adapter, true)) {
8296 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8297 return -ENOMEM;
8298 }
8299
8300 if (netif_running(netdev))
8301 err = igb_open(netdev);
8302
8303 return err;
8304 }
8305 /* igb_main.c */
Linux kernel - Deliverables
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