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r8169: Use dma_rmb() and dma_wmb() for DescOwn checks
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
57 #include "igb.h"
58
59 #define MAJ 5
60 #define MIN 2
61 #define BUILD 15
62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
63 __stringify(BUILD) "-k"
64 char igb_driver_name[] = "igb";
65 char igb_driver_version[] = DRV_VERSION;
66 static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
68 static const char igb_copyright[] =
69 "Copyright (c) 2007-2014 Intel Corporation.";
70
71 static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73 };
74
75 static const struct pci_device_id igb_pci_tbl[] = {
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113 };
114
115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117 static int igb_setup_all_tx_resources(struct igb_adapter *);
118 static int igb_setup_all_rx_resources(struct igb_adapter *);
119 static void igb_free_all_tx_resources(struct igb_adapter *);
120 static void igb_free_all_rx_resources(struct igb_adapter *);
121 static void igb_setup_mrqc(struct igb_adapter *);
122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
123 static void igb_remove(struct pci_dev *pdev);
124 static int igb_sw_init(struct igb_adapter *);
125 static int igb_open(struct net_device *);
126 static int igb_close(struct net_device *);
127 static void igb_configure(struct igb_adapter *);
128 static void igb_configure_tx(struct igb_adapter *);
129 static void igb_configure_rx(struct igb_adapter *);
130 static void igb_clean_all_tx_rings(struct igb_adapter *);
131 static void igb_clean_all_rx_rings(struct igb_adapter *);
132 static void igb_clean_tx_ring(struct igb_ring *);
133 static void igb_clean_rx_ring(struct igb_ring *);
134 static void igb_set_rx_mode(struct net_device *);
135 static void igb_update_phy_info(unsigned long);
136 static void igb_watchdog(unsigned long);
137 static void igb_watchdog_task(struct work_struct *);
138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
141 static int igb_change_mtu(struct net_device *, int);
142 static int igb_set_mac(struct net_device *, void *);
143 static void igb_set_uta(struct igb_adapter *adapter);
144 static irqreturn_t igb_intr(int irq, void *);
145 static irqreturn_t igb_intr_msi(int irq, void *);
146 static irqreturn_t igb_msix_other(int irq, void *);
147 static irqreturn_t igb_msix_ring(int irq, void *);
148 #ifdef CONFIG_IGB_DCA
149 static void igb_update_dca(struct igb_q_vector *);
150 static void igb_setup_dca(struct igb_adapter *);
151 #endif /* CONFIG_IGB_DCA */
152 static int igb_poll(struct napi_struct *, int);
153 static bool igb_clean_tx_irq(struct igb_q_vector *);
154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156 static void igb_tx_timeout(struct net_device *);
157 static void igb_reset_task(struct work_struct *);
158 static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
162 static void igb_restore_vlan(struct igb_adapter *);
163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
164 static void igb_ping_all_vfs(struct igb_adapter *);
165 static void igb_msg_task(struct igb_adapter *);
166 static void igb_vmm_control(struct igb_adapter *);
167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
177 static void igb_check_vf_rate_limit(struct igb_adapter *);
178
179 #ifdef CONFIG_PCI_IOV
180 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
182 #endif
183
184 #ifdef CONFIG_PM
185 #ifdef CONFIG_PM_SLEEP
186 static int igb_suspend(struct device *);
187 #endif
188 static int igb_resume(struct device *);
189 static int igb_runtime_suspend(struct device *dev);
190 static int igb_runtime_resume(struct device *dev);
191 static int igb_runtime_idle(struct device *dev);
192 static const struct dev_pm_ops igb_pm_ops = {
193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
195 igb_runtime_idle)
196 };
197 #endif
198 static void igb_shutdown(struct pci_dev *);
199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
200 #ifdef CONFIG_IGB_DCA
201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202 static struct notifier_block dca_notifier = {
203 .notifier_call = igb_notify_dca,
204 .next = NULL,
205 .priority = 0
206 };
207 #endif
208 #ifdef CONFIG_NET_POLL_CONTROLLER
209 /* for netdump / net console */
210 static void igb_netpoll(struct net_device *);
211 #endif
212 #ifdef CONFIG_PCI_IOV
213 static unsigned int max_vfs;
214 module_param(max_vfs, uint, 0);
215 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
216 #endif /* CONFIG_PCI_IOV */
217
218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221 static void igb_io_resume(struct pci_dev *);
222
223 static const struct pci_error_handlers igb_err_handler = {
224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227 };
228
229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
230
231 static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
235 .remove = igb_remove,
236 #ifdef CONFIG_PM
237 .driver.pm = &igb_pm_ops,
238 #endif
239 .shutdown = igb_shutdown,
240 .sriov_configure = igb_pci_sriov_configure,
241 .err_handler = &igb_err_handler
242 };
243
244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246 MODULE_LICENSE("GPL");
247 MODULE_VERSION(DRV_VERSION);
248
249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250 static int debug = -1;
251 module_param(debug, int, 0);
252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
254 struct igb_reg_info {
255 u32 ofs;
256 char *name;
257 };
258
259 static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293 };
294
295 /* igb_regdump - register printout routine */
296 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297 {
298 int n = 0;
299 char rname[16];
300 u32 regs[8];
301
302 switch (reginfo->ofs) {
303 case E1000_RDLEN(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_RDLEN(n));
306 break;
307 case E1000_RDH(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDH(n));
310 break;
311 case E1000_RDT(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDT(n));
314 break;
315 case E1000_RXDCTL(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RXDCTL(n));
318 break;
319 case E1000_RDBAL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RDBAL(n));
322 break;
323 case E1000_RDBAH(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAH(n));
326 break;
327 case E1000_TDBAL(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAL(n));
330 break;
331 case E1000_TDBAH(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_TDBAH(n));
334 break;
335 case E1000_TDLEN(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDLEN(n));
338 break;
339 case E1000_TDH(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDH(n));
342 break;
343 case E1000_TDT(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDT(n));
346 break;
347 case E1000_TXDCTL(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TXDCTL(n));
350 break;
351 default:
352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
353 return;
354 }
355
356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 regs[2], regs[3]);
359 }
360
361 /* igb_dump - Print registers, Tx-rings and Rx-rings */
362 static void igb_dump(struct igb_adapter *adapter)
363 {
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
373 u16 i, n;
374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
381 pr_info("Device Name state trans_start last_rx\n");
382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
388 pr_info(" Register Name Value\n");
389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
400 for (n = 0; n < adapter->num_tx_queues; n++) {
401 struct igb_tx_buffer *buffer_info;
402 tx_ring = adapter->tx_ring[n];
403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
435
436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
437 const char *next_desc;
438 struct igb_tx_buffer *buffer_info;
439 tx_desc = IGB_TX_DESC(tx_ring, i);
440 buffer_info = &tx_ring->tx_buffer_info[i];
441 u0 = (struct my_u0 *)tx_desc;
442 if (i == tx_ring->next_to_use &&
443 i == tx_ring->next_to_clean)
444 next_desc = " NTC/U";
445 else if (i == tx_ring->next_to_use)
446 next_desc = " NTU";
447 else if (i == tx_ring->next_to_clean)
448 next_desc = " NTC";
449 else
450 next_desc = "";
451
452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
453 i, le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(buffer_info, dma),
456 dma_unmap_len(buffer_info, len),
457 buffer_info->next_to_watch,
458 (u64)buffer_info->time_stamp,
459 buffer_info->skb, next_desc);
460
461 if (netif_msg_pktdata(adapter) && buffer_info->skb)
462 print_hex_dump(KERN_INFO, "",
463 DUMP_PREFIX_ADDRESS,
464 16, 1, buffer_info->skb->data,
465 dma_unmap_len(buffer_info, len),
466 true);
467 }
468 }
469
470 /* Print RX Rings Summary */
471 rx_ring_summary:
472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
473 pr_info("Queue [NTU] [NTC]\n");
474 for (n = 0; n < adapter->num_rx_queues; n++) {
475 rx_ring = adapter->rx_ring[n];
476 pr_info(" %5d %5X %5X\n",
477 n, rx_ring->next_to_use, rx_ring->next_to_clean);
478 }
479
480 /* Print RX Rings */
481 if (!netif_msg_rx_status(adapter))
482 goto exit;
483
484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
485
486 /* Advanced Receive Descriptor (Read) Format
487 * 63 1 0
488 * +-----------------------------------------------------+
489 * 0 | Packet Buffer Address [63:1] |A0/NSE|
490 * +----------------------------------------------+------+
491 * 8 | Header Buffer Address [63:1] | DD |
492 * +-----------------------------------------------------+
493 *
494 *
495 * Advanced Receive Descriptor (Write-Back) Format
496 *
497 * 63 48 47 32 31 30 21 20 17 16 4 3 0
498 * +------------------------------------------------------+
499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
500 * | Checksum Ident | | | | Type | Type |
501 * +------------------------------------------------------+
502 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 * +------------------------------------------------------+
504 * 63 48 47 32 31 20 19 0
505 */
506
507 for (n = 0; n < adapter->num_rx_queues; n++) {
508 rx_ring = adapter->rx_ring[n];
509 pr_info("------------------------------------\n");
510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
511 pr_info("------------------------------------\n");
512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
514
515 for (i = 0; i < rx_ring->count; i++) {
516 const char *next_desc;
517 struct igb_rx_buffer *buffer_info;
518 buffer_info = &rx_ring->rx_buffer_info[i];
519 rx_desc = IGB_RX_DESC(rx_ring, i);
520 u0 = (struct my_u0 *)rx_desc;
521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
522
523 if (i == rx_ring->next_to_use)
524 next_desc = " NTU";
525 else if (i == rx_ring->next_to_clean)
526 next_desc = " NTC";
527 else
528 next_desc = "";
529
530 if (staterr & E1000_RXD_STAT_DD) {
531 /* Descriptor Done */
532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
533 "RWB", i,
534 le64_to_cpu(u0->a),
535 le64_to_cpu(u0->b),
536 next_desc);
537 } else {
538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
539 "R ", i,
540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
542 (u64)buffer_info->dma,
543 next_desc);
544
545 if (netif_msg_pktdata(adapter) &&
546 buffer_info->dma && buffer_info->page) {
547 print_hex_dump(KERN_INFO, "",
548 DUMP_PREFIX_ADDRESS,
549 16, 1,
550 page_address(buffer_info->page) +
551 buffer_info->page_offset,
552 IGB_RX_BUFSZ, true);
553 }
554 }
555 }
556 }
557
558 exit:
559 return;
560 }
561
562 /**
563 * igb_get_i2c_data - Reads the I2C SDA data bit
564 * @hw: pointer to hardware structure
565 * @i2cctl: Current value of I2CCTL register
566 *
567 * Returns the I2C data bit value
568 **/
569 static int igb_get_i2c_data(void *data)
570 {
571 struct igb_adapter *adapter = (struct igb_adapter *)data;
572 struct e1000_hw *hw = &adapter->hw;
573 s32 i2cctl = rd32(E1000_I2CPARAMS);
574
575 return !!(i2cctl & E1000_I2C_DATA_IN);
576 }
577
578 /**
579 * igb_set_i2c_data - Sets the I2C data bit
580 * @data: pointer to hardware structure
581 * @state: I2C data value (0 or 1) to set
582 *
583 * Sets the I2C data bit
584 **/
585 static void igb_set_i2c_data(void *data, int state)
586 {
587 struct igb_adapter *adapter = (struct igb_adapter *)data;
588 struct e1000_hw *hw = &adapter->hw;
589 s32 i2cctl = rd32(E1000_I2CPARAMS);
590
591 if (state)
592 i2cctl |= E1000_I2C_DATA_OUT;
593 else
594 i2cctl &= ~E1000_I2C_DATA_OUT;
595
596 i2cctl &= ~E1000_I2C_DATA_OE_N;
597 i2cctl |= E1000_I2C_CLK_OE_N;
598 wr32(E1000_I2CPARAMS, i2cctl);
599 wrfl();
600
601 }
602
603 /**
604 * igb_set_i2c_clk - Sets the I2C SCL clock
605 * @data: pointer to hardware structure
606 * @state: state to set clock
607 *
608 * Sets the I2C clock line to state
609 **/
610 static void igb_set_i2c_clk(void *data, int state)
611 {
612 struct igb_adapter *adapter = (struct igb_adapter *)data;
613 struct e1000_hw *hw = &adapter->hw;
614 s32 i2cctl = rd32(E1000_I2CPARAMS);
615
616 if (state) {
617 i2cctl |= E1000_I2C_CLK_OUT;
618 i2cctl &= ~E1000_I2C_CLK_OE_N;
619 } else {
620 i2cctl &= ~E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 }
623 wr32(E1000_I2CPARAMS, i2cctl);
624 wrfl();
625 }
626
627 /**
628 * igb_get_i2c_clk - Gets the I2C SCL clock state
629 * @data: pointer to hardware structure
630 *
631 * Gets the I2C clock state
632 **/
633 static int igb_get_i2c_clk(void *data)
634 {
635 struct igb_adapter *adapter = (struct igb_adapter *)data;
636 struct e1000_hw *hw = &adapter->hw;
637 s32 i2cctl = rd32(E1000_I2CPARAMS);
638
639 return !!(i2cctl & E1000_I2C_CLK_IN);
640 }
641
642 static const struct i2c_algo_bit_data igb_i2c_algo = {
643 .setsda = igb_set_i2c_data,
644 .setscl = igb_set_i2c_clk,
645 .getsda = igb_get_i2c_data,
646 .getscl = igb_get_i2c_clk,
647 .udelay = 5,
648 .timeout = 20,
649 };
650
651 /**
652 * igb_get_hw_dev - return device
653 * @hw: pointer to hardware structure
654 *
655 * used by hardware layer to print debugging information
656 **/
657 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
658 {
659 struct igb_adapter *adapter = hw->back;
660 return adapter->netdev;
661 }
662
663 /**
664 * igb_init_module - Driver Registration Routine
665 *
666 * igb_init_module is the first routine called when the driver is
667 * loaded. All it does is register with the PCI subsystem.
668 **/
669 static int __init igb_init_module(void)
670 {
671 int ret;
672
673 pr_info("%s - version %s\n",
674 igb_driver_string, igb_driver_version);
675 pr_info("%s\n", igb_copyright);
676
677 #ifdef CONFIG_IGB_DCA
678 dca_register_notify(&dca_notifier);
679 #endif
680 ret = pci_register_driver(&igb_driver);
681 return ret;
682 }
683
684 module_init(igb_init_module);
685
686 /**
687 * igb_exit_module - Driver Exit Cleanup Routine
688 *
689 * igb_exit_module is called just before the driver is removed
690 * from memory.
691 **/
692 static void __exit igb_exit_module(void)
693 {
694 #ifdef CONFIG_IGB_DCA
695 dca_unregister_notify(&dca_notifier);
696 #endif
697 pci_unregister_driver(&igb_driver);
698 }
699
700 module_exit(igb_exit_module);
701
702 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703 /**
704 * igb_cache_ring_register - Descriptor ring to register mapping
705 * @adapter: board private structure to initialize
706 *
707 * Once we know the feature-set enabled for the device, we'll cache
708 * the register offset the descriptor ring is assigned to.
709 **/
710 static void igb_cache_ring_register(struct igb_adapter *adapter)
711 {
712 int i = 0, j = 0;
713 u32 rbase_offset = adapter->vfs_allocated_count;
714
715 switch (adapter->hw.mac.type) {
716 case e1000_82576:
717 /* The queues are allocated for virtualization such that VF 0
718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 * In order to avoid collision we start at the first free queue
720 * and continue consuming queues in the same sequence
721 */
722 if (adapter->vfs_allocated_count) {
723 for (; i < adapter->rss_queues; i++)
724 adapter->rx_ring[i]->reg_idx = rbase_offset +
725 Q_IDX_82576(i);
726 }
727 /* Fall through */
728 case e1000_82575:
729 case e1000_82580:
730 case e1000_i350:
731 case e1000_i354:
732 case e1000_i210:
733 case e1000_i211:
734 /* Fall through */
735 default:
736 for (; i < adapter->num_rx_queues; i++)
737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
738 for (; j < adapter->num_tx_queues; j++)
739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
740 break;
741 }
742 }
743
744 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
745 {
746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
748 u32 value = 0;
749
750 if (E1000_REMOVED(hw_addr))
751 return ~value;
752
753 value = readl(&hw_addr[reg]);
754
755 /* reads should not return all F's */
756 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
757 struct net_device *netdev = igb->netdev;
758 hw->hw_addr = NULL;
759 netif_device_detach(netdev);
760 netdev_err(netdev, "PCIe link lost, device now detached\n");
761 }
762
763 return value;
764 }
765
766 /**
767 * igb_write_ivar - configure ivar for given MSI-X vector
768 * @hw: pointer to the HW structure
769 * @msix_vector: vector number we are allocating to a given ring
770 * @index: row index of IVAR register to write within IVAR table
771 * @offset: column offset of in IVAR, should be multiple of 8
772 *
773 * This function is intended to handle the writing of the IVAR register
774 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
775 * each containing an cause allocation for an Rx and Tx ring, and a
776 * variable number of rows depending on the number of queues supported.
777 **/
778 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
779 int index, int offset)
780 {
781 u32 ivar = array_rd32(E1000_IVAR0, index);
782
783 /* clear any bits that are currently set */
784 ivar &= ~((u32)0xFF << offset);
785
786 /* write vector and valid bit */
787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
788
789 array_wr32(E1000_IVAR0, index, ivar);
790 }
791
792 #define IGB_N0_QUEUE -1
793 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
794 {
795 struct igb_adapter *adapter = q_vector->adapter;
796 struct e1000_hw *hw = &adapter->hw;
797 int rx_queue = IGB_N0_QUEUE;
798 int tx_queue = IGB_N0_QUEUE;
799 u32 msixbm = 0;
800
801 if (q_vector->rx.ring)
802 rx_queue = q_vector->rx.ring->reg_idx;
803 if (q_vector->tx.ring)
804 tx_queue = q_vector->tx.ring->reg_idx;
805
806 switch (hw->mac.type) {
807 case e1000_82575:
808 /* The 82575 assigns vectors using a bitmask, which matches the
809 * bitmask for the EICR/EIMS/EIMC registers. To assign one
810 * or more queues to a vector, we write the appropriate bits
811 * into the MSIXBM register for that vector.
812 */
813 if (rx_queue > IGB_N0_QUEUE)
814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
815 if (tx_queue > IGB_N0_QUEUE)
816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
818 msixbm |= E1000_EIMS_OTHER;
819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
820 q_vector->eims_value = msixbm;
821 break;
822 case e1000_82576:
823 /* 82576 uses a table that essentially consists of 2 columns
824 * with 8 rows. The ordering is column-major so we use the
825 * lower 3 bits as the row index, and the 4th bit as the
826 * column offset.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue & 0x7,
831 (rx_queue & 0x8) << 1);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue & 0x7,
835 ((tx_queue & 0x8) << 1) + 8);
836 q_vector->eims_value = 1 << msix_vector;
837 break;
838 case e1000_82580:
839 case e1000_i350:
840 case e1000_i354:
841 case e1000_i210:
842 case e1000_i211:
843 /* On 82580 and newer adapters the scheme is similar to 82576
844 * however instead of ordering column-major we have things
845 * ordered row-major. So we traverse the table by using
846 * bit 0 as the column offset, and the remaining bits as the
847 * row index.
848 */
849 if (rx_queue > IGB_N0_QUEUE)
850 igb_write_ivar(hw, msix_vector,
851 rx_queue >> 1,
852 (rx_queue & 0x1) << 4);
853 if (tx_queue > IGB_N0_QUEUE)
854 igb_write_ivar(hw, msix_vector,
855 tx_queue >> 1,
856 ((tx_queue & 0x1) << 4) + 8);
857 q_vector->eims_value = 1 << msix_vector;
858 break;
859 default:
860 BUG();
861 break;
862 }
863
864 /* add q_vector eims value to global eims_enable_mask */
865 adapter->eims_enable_mask |= q_vector->eims_value;
866
867 /* configure q_vector to set itr on first interrupt */
868 q_vector->set_itr = 1;
869 }
870
871 /**
872 * igb_configure_msix - Configure MSI-X hardware
873 * @adapter: board private structure to initialize
874 *
875 * igb_configure_msix sets up the hardware to properly
876 * generate MSI-X interrupts.
877 **/
878 static void igb_configure_msix(struct igb_adapter *adapter)
879 {
880 u32 tmp;
881 int i, vector = 0;
882 struct e1000_hw *hw = &adapter->hw;
883
884 adapter->eims_enable_mask = 0;
885
886 /* set vector for other causes, i.e. link changes */
887 switch (hw->mac.type) {
888 case e1000_82575:
889 tmp = rd32(E1000_CTRL_EXT);
890 /* enable MSI-X PBA support*/
891 tmp |= E1000_CTRL_EXT_PBA_CLR;
892
893 /* Auto-Mask interrupts upon ICR read. */
894 tmp |= E1000_CTRL_EXT_EIAME;
895 tmp |= E1000_CTRL_EXT_IRCA;
896
897 wr32(E1000_CTRL_EXT, tmp);
898
899 /* enable msix_other interrupt */
900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
901 adapter->eims_other = E1000_EIMS_OTHER;
902
903 break;
904
905 case e1000_82576:
906 case e1000_82580:
907 case e1000_i350:
908 case e1000_i354:
909 case e1000_i210:
910 case e1000_i211:
911 /* Turn on MSI-X capability first, or our settings
912 * won't stick. And it will take days to debug.
913 */
914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
915 E1000_GPIE_PBA | E1000_GPIE_EIAME |
916 E1000_GPIE_NSICR);
917
918 /* enable msix_other interrupt */
919 adapter->eims_other = 1 << vector;
920 tmp = (vector++ | E1000_IVAR_VALID) << 8;
921
922 wr32(E1000_IVAR_MISC, tmp);
923 break;
924 default:
925 /* do nothing, since nothing else supports MSI-X */
926 break;
927 } /* switch (hw->mac.type) */
928
929 adapter->eims_enable_mask |= adapter->eims_other;
930
931 for (i = 0; i < adapter->num_q_vectors; i++)
932 igb_assign_vector(adapter->q_vector[i], vector++);
933
934 wrfl();
935 }
936
937 /**
938 * igb_request_msix - Initialize MSI-X interrupts
939 * @adapter: board private structure to initialize
940 *
941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
942 * kernel.
943 **/
944 static int igb_request_msix(struct igb_adapter *adapter)
945 {
946 struct net_device *netdev = adapter->netdev;
947 struct e1000_hw *hw = &adapter->hw;
948 int i, err = 0, vector = 0, free_vector = 0;
949
950 err = request_irq(adapter->msix_entries[vector].vector,
951 igb_msix_other, 0, netdev->name, adapter);
952 if (err)
953 goto err_out;
954
955 for (i = 0; i < adapter->num_q_vectors; i++) {
956 struct igb_q_vector *q_vector = adapter->q_vector[i];
957
958 vector++;
959
960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
961
962 if (q_vector->rx.ring && q_vector->tx.ring)
963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
964 q_vector->rx.ring->queue_index);
965 else if (q_vector->tx.ring)
966 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
967 q_vector->tx.ring->queue_index);
968 else if (q_vector->rx.ring)
969 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
970 q_vector->rx.ring->queue_index);
971 else
972 sprintf(q_vector->name, "%s-unused", netdev->name);
973
974 err = request_irq(adapter->msix_entries[vector].vector,
975 igb_msix_ring, 0, q_vector->name,
976 q_vector);
977 if (err)
978 goto err_free;
979 }
980
981 igb_configure_msix(adapter);
982 return 0;
983
984 err_free:
985 /* free already assigned IRQs */
986 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
987
988 vector--;
989 for (i = 0; i < vector; i++) {
990 free_irq(adapter->msix_entries[free_vector++].vector,
991 adapter->q_vector[i]);
992 }
993 err_out:
994 return err;
995 }
996
997 /**
998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
1001 *
1002 * This function frees the memory allocated to the q_vector.
1003 **/
1004 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005 {
1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007
1008 adapter->q_vector[v_idx] = NULL;
1009
1010 /* igb_get_stats64() might access the rings on this vector,
1011 * we must wait a grace period before freeing it.
1012 */
1013 if (q_vector)
1014 kfree_rcu(q_vector, rcu);
1015 }
1016
1017 /**
1018 * igb_reset_q_vector - Reset config for interrupt vector
1019 * @adapter: board private structure to initialize
1020 * @v_idx: Index of vector to be reset
1021 *
1022 * If NAPI is enabled it will delete any references to the
1023 * NAPI struct. This is preparation for igb_free_q_vector.
1024 **/
1025 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1026 {
1027 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1028
1029 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1030 * allocated. So, q_vector is NULL so we should stop here.
1031 */
1032 if (!q_vector)
1033 return;
1034
1035 if (q_vector->tx.ring)
1036 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1037
1038 if (q_vector->rx.ring)
1039 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1040
1041 netif_napi_del(&q_vector->napi);
1042
1043 }
1044
1045 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1046 {
1047 int v_idx = adapter->num_q_vectors;
1048
1049 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1050 pci_disable_msix(adapter->pdev);
1051 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1052 pci_disable_msi(adapter->pdev);
1053
1054 while (v_idx--)
1055 igb_reset_q_vector(adapter, v_idx);
1056 }
1057
1058 /**
1059 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1060 * @adapter: board private structure to initialize
1061 *
1062 * This function frees the memory allocated to the q_vectors. In addition if
1063 * NAPI is enabled it will delete any references to the NAPI struct prior
1064 * to freeing the q_vector.
1065 **/
1066 static void igb_free_q_vectors(struct igb_adapter *adapter)
1067 {
1068 int v_idx = adapter->num_q_vectors;
1069
1070 adapter->num_tx_queues = 0;
1071 adapter->num_rx_queues = 0;
1072 adapter->num_q_vectors = 0;
1073
1074 while (v_idx--) {
1075 igb_reset_q_vector(adapter, v_idx);
1076 igb_free_q_vector(adapter, v_idx);
1077 }
1078 }
1079
1080 /**
1081 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1082 * @adapter: board private structure to initialize
1083 *
1084 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1085 * MSI-X interrupts allocated.
1086 */
1087 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1088 {
1089 igb_free_q_vectors(adapter);
1090 igb_reset_interrupt_capability(adapter);
1091 }
1092
1093 /**
1094 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1095 * @adapter: board private structure to initialize
1096 * @msix: boolean value of MSIX capability
1097 *
1098 * Attempt to configure interrupts using the best available
1099 * capabilities of the hardware and kernel.
1100 **/
1101 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1102 {
1103 int err;
1104 int numvecs, i;
1105
1106 if (!msix)
1107 goto msi_only;
1108 adapter->flags |= IGB_FLAG_HAS_MSIX;
1109
1110 /* Number of supported queues. */
1111 adapter->num_rx_queues = adapter->rss_queues;
1112 if (adapter->vfs_allocated_count)
1113 adapter->num_tx_queues = 1;
1114 else
1115 adapter->num_tx_queues = adapter->rss_queues;
1116
1117 /* start with one vector for every Rx queue */
1118 numvecs = adapter->num_rx_queues;
1119
1120 /* if Tx handler is separate add 1 for every Tx queue */
1121 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1122 numvecs += adapter->num_tx_queues;
1123
1124 /* store the number of vectors reserved for queues */
1125 adapter->num_q_vectors = numvecs;
1126
1127 /* add 1 vector for link status interrupts */
1128 numvecs++;
1129 for (i = 0; i < numvecs; i++)
1130 adapter->msix_entries[i].entry = i;
1131
1132 err = pci_enable_msix_range(adapter->pdev,
1133 adapter->msix_entries,
1134 numvecs,
1135 numvecs);
1136 if (err > 0)
1137 return;
1138
1139 igb_reset_interrupt_capability(adapter);
1140
1141 /* If we can't do MSI-X, try MSI */
1142 msi_only:
1143 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1144 #ifdef CONFIG_PCI_IOV
1145 /* disable SR-IOV for non MSI-X configurations */
1146 if (adapter->vf_data) {
1147 struct e1000_hw *hw = &adapter->hw;
1148 /* disable iov and allow time for transactions to clear */
1149 pci_disable_sriov(adapter->pdev);
1150 msleep(500);
1151
1152 kfree(adapter->vf_data);
1153 adapter->vf_data = NULL;
1154 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1155 wrfl();
1156 msleep(100);
1157 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1158 }
1159 #endif
1160 adapter->vfs_allocated_count = 0;
1161 adapter->rss_queues = 1;
1162 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1163 adapter->num_rx_queues = 1;
1164 adapter->num_tx_queues = 1;
1165 adapter->num_q_vectors = 1;
1166 if (!pci_enable_msi(adapter->pdev))
1167 adapter->flags |= IGB_FLAG_HAS_MSI;
1168 }
1169
1170 static void igb_add_ring(struct igb_ring *ring,
1171 struct igb_ring_container *head)
1172 {
1173 head->ring = ring;
1174 head->count++;
1175 }
1176
1177 /**
1178 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1179 * @adapter: board private structure to initialize
1180 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1181 * @v_idx: index of vector in adapter struct
1182 * @txr_count: total number of Tx rings to allocate
1183 * @txr_idx: index of first Tx ring to allocate
1184 * @rxr_count: total number of Rx rings to allocate
1185 * @rxr_idx: index of first Rx ring to allocate
1186 *
1187 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1188 **/
1189 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1190 int v_count, int v_idx,
1191 int txr_count, int txr_idx,
1192 int rxr_count, int rxr_idx)
1193 {
1194 struct igb_q_vector *q_vector;
1195 struct igb_ring *ring;
1196 int ring_count, size;
1197
1198 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1199 if (txr_count > 1 || rxr_count > 1)
1200 return -ENOMEM;
1201
1202 ring_count = txr_count + rxr_count;
1203 size = sizeof(struct igb_q_vector) +
1204 (sizeof(struct igb_ring) * ring_count);
1205
1206 /* allocate q_vector and rings */
1207 q_vector = adapter->q_vector[v_idx];
1208 if (!q_vector)
1209 q_vector = kzalloc(size, GFP_KERNEL);
1210 if (!q_vector)
1211 return -ENOMEM;
1212
1213 /* initialize NAPI */
1214 netif_napi_add(adapter->netdev, &q_vector->napi,
1215 igb_poll, 64);
1216
1217 /* tie q_vector and adapter together */
1218 adapter->q_vector[v_idx] = q_vector;
1219 q_vector->adapter = adapter;
1220
1221 /* initialize work limits */
1222 q_vector->tx.work_limit = adapter->tx_work_limit;
1223
1224 /* initialize ITR configuration */
1225 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1226 q_vector->itr_val = IGB_START_ITR;
1227
1228 /* initialize pointer to rings */
1229 ring = q_vector->ring;
1230
1231 /* intialize ITR */
1232 if (rxr_count) {
1233 /* rx or rx/tx vector */
1234 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1235 q_vector->itr_val = adapter->rx_itr_setting;
1236 } else {
1237 /* tx only vector */
1238 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1239 q_vector->itr_val = adapter->tx_itr_setting;
1240 }
1241
1242 if (txr_count) {
1243 /* assign generic ring traits */
1244 ring->dev = &adapter->pdev->dev;
1245 ring->netdev = adapter->netdev;
1246
1247 /* configure backlink on ring */
1248 ring->q_vector = q_vector;
1249
1250 /* update q_vector Tx values */
1251 igb_add_ring(ring, &q_vector->tx);
1252
1253 /* For 82575, context index must be unique per ring. */
1254 if (adapter->hw.mac.type == e1000_82575)
1255 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1256
1257 /* apply Tx specific ring traits */
1258 ring->count = adapter->tx_ring_count;
1259 ring->queue_index = txr_idx;
1260
1261 u64_stats_init(&ring->tx_syncp);
1262 u64_stats_init(&ring->tx_syncp2);
1263
1264 /* assign ring to adapter */
1265 adapter->tx_ring[txr_idx] = ring;
1266
1267 /* push pointer to next ring */
1268 ring++;
1269 }
1270
1271 if (rxr_count) {
1272 /* assign generic ring traits */
1273 ring->dev = &adapter->pdev->dev;
1274 ring->netdev = adapter->netdev;
1275
1276 /* configure backlink on ring */
1277 ring->q_vector = q_vector;
1278
1279 /* update q_vector Rx values */
1280 igb_add_ring(ring, &q_vector->rx);
1281
1282 /* set flag indicating ring supports SCTP checksum offload */
1283 if (adapter->hw.mac.type >= e1000_82576)
1284 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1285
1286 /* On i350, i354, i210, and i211, loopback VLAN packets
1287 * have the tag byte-swapped.
1288 */
1289 if (adapter->hw.mac.type >= e1000_i350)
1290 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1291
1292 /* apply Rx specific ring traits */
1293 ring->count = adapter->rx_ring_count;
1294 ring->queue_index = rxr_idx;
1295
1296 u64_stats_init(&ring->rx_syncp);
1297
1298 /* assign ring to adapter */
1299 adapter->rx_ring[rxr_idx] = ring;
1300 }
1301
1302 return 0;
1303 }
1304
1305
1306 /**
1307 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1308 * @adapter: board private structure to initialize
1309 *
1310 * We allocate one q_vector per queue interrupt. If allocation fails we
1311 * return -ENOMEM.
1312 **/
1313 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1314 {
1315 int q_vectors = adapter->num_q_vectors;
1316 int rxr_remaining = adapter->num_rx_queues;
1317 int txr_remaining = adapter->num_tx_queues;
1318 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1319 int err;
1320
1321 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1322 for (; rxr_remaining; v_idx++) {
1323 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1324 0, 0, 1, rxr_idx);
1325
1326 if (err)
1327 goto err_out;
1328
1329 /* update counts and index */
1330 rxr_remaining--;
1331 rxr_idx++;
1332 }
1333 }
1334
1335 for (; v_idx < q_vectors; v_idx++) {
1336 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1337 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1338
1339 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1340 tqpv, txr_idx, rqpv, rxr_idx);
1341
1342 if (err)
1343 goto err_out;
1344
1345 /* update counts and index */
1346 rxr_remaining -= rqpv;
1347 txr_remaining -= tqpv;
1348 rxr_idx++;
1349 txr_idx++;
1350 }
1351
1352 return 0;
1353
1354 err_out:
1355 adapter->num_tx_queues = 0;
1356 adapter->num_rx_queues = 0;
1357 adapter->num_q_vectors = 0;
1358
1359 while (v_idx--)
1360 igb_free_q_vector(adapter, v_idx);
1361
1362 return -ENOMEM;
1363 }
1364
1365 /**
1366 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1367 * @adapter: board private structure to initialize
1368 * @msix: boolean value of MSIX capability
1369 *
1370 * This function initializes the interrupts and allocates all of the queues.
1371 **/
1372 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1373 {
1374 struct pci_dev *pdev = adapter->pdev;
1375 int err;
1376
1377 igb_set_interrupt_capability(adapter, msix);
1378
1379 err = igb_alloc_q_vectors(adapter);
1380 if (err) {
1381 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1382 goto err_alloc_q_vectors;
1383 }
1384
1385 igb_cache_ring_register(adapter);
1386
1387 return 0;
1388
1389 err_alloc_q_vectors:
1390 igb_reset_interrupt_capability(adapter);
1391 return err;
1392 }
1393
1394 /**
1395 * igb_request_irq - initialize interrupts
1396 * @adapter: board private structure to initialize
1397 *
1398 * Attempts to configure interrupts using the best available
1399 * capabilities of the hardware and kernel.
1400 **/
1401 static int igb_request_irq(struct igb_adapter *adapter)
1402 {
1403 struct net_device *netdev = adapter->netdev;
1404 struct pci_dev *pdev = adapter->pdev;
1405 int err = 0;
1406
1407 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1408 err = igb_request_msix(adapter);
1409 if (!err)
1410 goto request_done;
1411 /* fall back to MSI */
1412 igb_free_all_tx_resources(adapter);
1413 igb_free_all_rx_resources(adapter);
1414
1415 igb_clear_interrupt_scheme(adapter);
1416 err = igb_init_interrupt_scheme(adapter, false);
1417 if (err)
1418 goto request_done;
1419
1420 igb_setup_all_tx_resources(adapter);
1421 igb_setup_all_rx_resources(adapter);
1422 igb_configure(adapter);
1423 }
1424
1425 igb_assign_vector(adapter->q_vector[0], 0);
1426
1427 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1428 err = request_irq(pdev->irq, igb_intr_msi, 0,
1429 netdev->name, adapter);
1430 if (!err)
1431 goto request_done;
1432
1433 /* fall back to legacy interrupts */
1434 igb_reset_interrupt_capability(adapter);
1435 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1436 }
1437
1438 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1439 netdev->name, adapter);
1440
1441 if (err)
1442 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1443 err);
1444
1445 request_done:
1446 return err;
1447 }
1448
1449 static void igb_free_irq(struct igb_adapter *adapter)
1450 {
1451 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1452 int vector = 0, i;
1453
1454 free_irq(adapter->msix_entries[vector++].vector, adapter);
1455
1456 for (i = 0; i < adapter->num_q_vectors; i++)
1457 free_irq(adapter->msix_entries[vector++].vector,
1458 adapter->q_vector[i]);
1459 } else {
1460 free_irq(adapter->pdev->irq, adapter);
1461 }
1462 }
1463
1464 /**
1465 * igb_irq_disable - Mask off interrupt generation on the NIC
1466 * @adapter: board private structure
1467 **/
1468 static void igb_irq_disable(struct igb_adapter *adapter)
1469 {
1470 struct e1000_hw *hw = &adapter->hw;
1471
1472 /* we need to be careful when disabling interrupts. The VFs are also
1473 * mapped into these registers and so clearing the bits can cause
1474 * issues on the VF drivers so we only need to clear what we set
1475 */
1476 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1477 u32 regval = rd32(E1000_EIAM);
1478
1479 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1480 wr32(E1000_EIMC, adapter->eims_enable_mask);
1481 regval = rd32(E1000_EIAC);
1482 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1483 }
1484
1485 wr32(E1000_IAM, 0);
1486 wr32(E1000_IMC, ~0);
1487 wrfl();
1488 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1489 int i;
1490
1491 for (i = 0; i < adapter->num_q_vectors; i++)
1492 synchronize_irq(adapter->msix_entries[i].vector);
1493 } else {
1494 synchronize_irq(adapter->pdev->irq);
1495 }
1496 }
1497
1498 /**
1499 * igb_irq_enable - Enable default interrupt generation settings
1500 * @adapter: board private structure
1501 **/
1502 static void igb_irq_enable(struct igb_adapter *adapter)
1503 {
1504 struct e1000_hw *hw = &adapter->hw;
1505
1506 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1507 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1508 u32 regval = rd32(E1000_EIAC);
1509
1510 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1511 regval = rd32(E1000_EIAM);
1512 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1513 wr32(E1000_EIMS, adapter->eims_enable_mask);
1514 if (adapter->vfs_allocated_count) {
1515 wr32(E1000_MBVFIMR, 0xFF);
1516 ims |= E1000_IMS_VMMB;
1517 }
1518 wr32(E1000_IMS, ims);
1519 } else {
1520 wr32(E1000_IMS, IMS_ENABLE_MASK |
1521 E1000_IMS_DRSTA);
1522 wr32(E1000_IAM, IMS_ENABLE_MASK |
1523 E1000_IMS_DRSTA);
1524 }
1525 }
1526
1527 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1528 {
1529 struct e1000_hw *hw = &adapter->hw;
1530 u16 vid = adapter->hw.mng_cookie.vlan_id;
1531 u16 old_vid = adapter->mng_vlan_id;
1532
1533 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1534 /* add VID to filter table */
1535 igb_vfta_set(hw, vid, true);
1536 adapter->mng_vlan_id = vid;
1537 } else {
1538 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1539 }
1540
1541 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1542 (vid != old_vid) &&
1543 !test_bit(old_vid, adapter->active_vlans)) {
1544 /* remove VID from filter table */
1545 igb_vfta_set(hw, old_vid, false);
1546 }
1547 }
1548
1549 /**
1550 * igb_release_hw_control - release control of the h/w to f/w
1551 * @adapter: address of board private structure
1552 *
1553 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1554 * For ASF and Pass Through versions of f/w this means that the
1555 * driver is no longer loaded.
1556 **/
1557 static void igb_release_hw_control(struct igb_adapter *adapter)
1558 {
1559 struct e1000_hw *hw = &adapter->hw;
1560 u32 ctrl_ext;
1561
1562 /* Let firmware take over control of h/w */
1563 ctrl_ext = rd32(E1000_CTRL_EXT);
1564 wr32(E1000_CTRL_EXT,
1565 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1566 }
1567
1568 /**
1569 * igb_get_hw_control - get control of the h/w from f/w
1570 * @adapter: address of board private structure
1571 *
1572 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1573 * For ASF and Pass Through versions of f/w this means that
1574 * the driver is loaded.
1575 **/
1576 static void igb_get_hw_control(struct igb_adapter *adapter)
1577 {
1578 struct e1000_hw *hw = &adapter->hw;
1579 u32 ctrl_ext;
1580
1581 /* Let firmware know the driver has taken over */
1582 ctrl_ext = rd32(E1000_CTRL_EXT);
1583 wr32(E1000_CTRL_EXT,
1584 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1585 }
1586
1587 /**
1588 * igb_configure - configure the hardware for RX and TX
1589 * @adapter: private board structure
1590 **/
1591 static void igb_configure(struct igb_adapter *adapter)
1592 {
1593 struct net_device *netdev = adapter->netdev;
1594 int i;
1595
1596 igb_get_hw_control(adapter);
1597 igb_set_rx_mode(netdev);
1598
1599 igb_restore_vlan(adapter);
1600
1601 igb_setup_tctl(adapter);
1602 igb_setup_mrqc(adapter);
1603 igb_setup_rctl(adapter);
1604
1605 igb_configure_tx(adapter);
1606 igb_configure_rx(adapter);
1607
1608 igb_rx_fifo_flush_82575(&adapter->hw);
1609
1610 /* call igb_desc_unused which always leaves
1611 * at least 1 descriptor unused to make sure
1612 * next_to_use != next_to_clean
1613 */
1614 for (i = 0; i < adapter->num_rx_queues; i++) {
1615 struct igb_ring *ring = adapter->rx_ring[i];
1616 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1617 }
1618 }
1619
1620 /**
1621 * igb_power_up_link - Power up the phy/serdes link
1622 * @adapter: address of board private structure
1623 **/
1624 void igb_power_up_link(struct igb_adapter *adapter)
1625 {
1626 igb_reset_phy(&adapter->hw);
1627
1628 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1629 igb_power_up_phy_copper(&adapter->hw);
1630 else
1631 igb_power_up_serdes_link_82575(&adapter->hw);
1632
1633 igb_setup_link(&adapter->hw);
1634 }
1635
1636 /**
1637 * igb_power_down_link - Power down the phy/serdes link
1638 * @adapter: address of board private structure
1639 */
1640 static void igb_power_down_link(struct igb_adapter *adapter)
1641 {
1642 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1643 igb_power_down_phy_copper_82575(&adapter->hw);
1644 else
1645 igb_shutdown_serdes_link_82575(&adapter->hw);
1646 }
1647
1648 /**
1649 * Detect and switch function for Media Auto Sense
1650 * @adapter: address of the board private structure
1651 **/
1652 static void igb_check_swap_media(struct igb_adapter *adapter)
1653 {
1654 struct e1000_hw *hw = &adapter->hw;
1655 u32 ctrl_ext, connsw;
1656 bool swap_now = false;
1657
1658 ctrl_ext = rd32(E1000_CTRL_EXT);
1659 connsw = rd32(E1000_CONNSW);
1660
1661 /* need to live swap if current media is copper and we have fiber/serdes
1662 * to go to.
1663 */
1664
1665 if ((hw->phy.media_type == e1000_media_type_copper) &&
1666 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1667 swap_now = true;
1668 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1669 /* copper signal takes time to appear */
1670 if (adapter->copper_tries < 4) {
1671 adapter->copper_tries++;
1672 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1673 wr32(E1000_CONNSW, connsw);
1674 return;
1675 } else {
1676 adapter->copper_tries = 0;
1677 if ((connsw & E1000_CONNSW_PHYSD) &&
1678 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1679 swap_now = true;
1680 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 }
1683 }
1684 }
1685
1686 if (!swap_now)
1687 return;
1688
1689 switch (hw->phy.media_type) {
1690 case e1000_media_type_copper:
1691 netdev_info(adapter->netdev,
1692 "MAS: changing media to fiber/serdes\n");
1693 ctrl_ext |=
1694 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1695 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1696 adapter->copper_tries = 0;
1697 break;
1698 case e1000_media_type_internal_serdes:
1699 case e1000_media_type_fiber:
1700 netdev_info(adapter->netdev,
1701 "MAS: changing media to copper\n");
1702 ctrl_ext &=
1703 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1704 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1705 break;
1706 default:
1707 /* shouldn't get here during regular operation */
1708 netdev_err(adapter->netdev,
1709 "AMS: Invalid media type found, returning\n");
1710 break;
1711 }
1712 wr32(E1000_CTRL_EXT, ctrl_ext);
1713 }
1714
1715 /**
1716 * igb_up - Open the interface and prepare it to handle traffic
1717 * @adapter: board private structure
1718 **/
1719 int igb_up(struct igb_adapter *adapter)
1720 {
1721 struct e1000_hw *hw = &adapter->hw;
1722 int i;
1723
1724 /* hardware has been reset, we need to reload some things */
1725 igb_configure(adapter);
1726
1727 clear_bit(__IGB_DOWN, &adapter->state);
1728
1729 for (i = 0; i < adapter->num_q_vectors; i++)
1730 napi_enable(&(adapter->q_vector[i]->napi));
1731
1732 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1733 igb_configure_msix(adapter);
1734 else
1735 igb_assign_vector(adapter->q_vector[0], 0);
1736
1737 /* Clear any pending interrupts. */
1738 rd32(E1000_ICR);
1739 igb_irq_enable(adapter);
1740
1741 /* notify VFs that reset has been completed */
1742 if (adapter->vfs_allocated_count) {
1743 u32 reg_data = rd32(E1000_CTRL_EXT);
1744
1745 reg_data |= E1000_CTRL_EXT_PFRSTD;
1746 wr32(E1000_CTRL_EXT, reg_data);
1747 }
1748
1749 netif_tx_start_all_queues(adapter->netdev);
1750
1751 /* start the watchdog. */
1752 hw->mac.get_link_status = 1;
1753 schedule_work(&adapter->watchdog_task);
1754
1755 if ((adapter->flags & IGB_FLAG_EEE) &&
1756 (!hw->dev_spec._82575.eee_disable))
1757 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1758
1759 return 0;
1760 }
1761
1762 void igb_down(struct igb_adapter *adapter)
1763 {
1764 struct net_device *netdev = adapter->netdev;
1765 struct e1000_hw *hw = &adapter->hw;
1766 u32 tctl, rctl;
1767 int i;
1768
1769 /* signal that we're down so the interrupt handler does not
1770 * reschedule our watchdog timer
1771 */
1772 set_bit(__IGB_DOWN, &adapter->state);
1773
1774 /* disable receives in the hardware */
1775 rctl = rd32(E1000_RCTL);
1776 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1777 /* flush and sleep below */
1778
1779 netif_tx_stop_all_queues(netdev);
1780
1781 /* disable transmits in the hardware */
1782 tctl = rd32(E1000_TCTL);
1783 tctl &= ~E1000_TCTL_EN;
1784 wr32(E1000_TCTL, tctl);
1785 /* flush both disables and wait for them to finish */
1786 wrfl();
1787 usleep_range(10000, 11000);
1788
1789 igb_irq_disable(adapter);
1790
1791 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1792
1793 for (i = 0; i < adapter->num_q_vectors; i++) {
1794 if (adapter->q_vector[i]) {
1795 napi_synchronize(&adapter->q_vector[i]->napi);
1796 napi_disable(&adapter->q_vector[i]->napi);
1797 }
1798 }
1799
1800
1801 del_timer_sync(&adapter->watchdog_timer);
1802 del_timer_sync(&adapter->phy_info_timer);
1803
1804 netif_carrier_off(netdev);
1805
1806 /* record the stats before reset*/
1807 spin_lock(&adapter->stats64_lock);
1808 igb_update_stats(adapter, &adapter->stats64);
1809 spin_unlock(&adapter->stats64_lock);
1810
1811 adapter->link_speed = 0;
1812 adapter->link_duplex = 0;
1813
1814 if (!pci_channel_offline(adapter->pdev))
1815 igb_reset(adapter);
1816 igb_clean_all_tx_rings(adapter);
1817 igb_clean_all_rx_rings(adapter);
1818 #ifdef CONFIG_IGB_DCA
1819
1820 /* since we reset the hardware DCA settings were cleared */
1821 igb_setup_dca(adapter);
1822 #endif
1823 }
1824
1825 void igb_reinit_locked(struct igb_adapter *adapter)
1826 {
1827 WARN_ON(in_interrupt());
1828 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1829 usleep_range(1000, 2000);
1830 igb_down(adapter);
1831 igb_up(adapter);
1832 clear_bit(__IGB_RESETTING, &adapter->state);
1833 }
1834
1835 /** igb_enable_mas - Media Autosense re-enable after swap
1836 *
1837 * @adapter: adapter struct
1838 **/
1839 static s32 igb_enable_mas(struct igb_adapter *adapter)
1840 {
1841 struct e1000_hw *hw = &adapter->hw;
1842 u32 connsw;
1843 s32 ret_val = 0;
1844
1845 connsw = rd32(E1000_CONNSW);
1846 if (!(hw->phy.media_type == e1000_media_type_copper))
1847 return ret_val;
1848
1849 /* configure for SerDes media detect */
1850 if (!(connsw & E1000_CONNSW_SERDESD)) {
1851 connsw |= E1000_CONNSW_ENRGSRC;
1852 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1853 wr32(E1000_CONNSW, connsw);
1854 wrfl();
1855 } else if (connsw & E1000_CONNSW_SERDESD) {
1856 /* already SerDes, no need to enable anything */
1857 return ret_val;
1858 } else {
1859 netdev_info(adapter->netdev,
1860 "MAS: Unable to configure feature, disabling..\n");
1861 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1862 }
1863 return ret_val;
1864 }
1865
1866 void igb_reset(struct igb_adapter *adapter)
1867 {
1868 struct pci_dev *pdev = adapter->pdev;
1869 struct e1000_hw *hw = &adapter->hw;
1870 struct e1000_mac_info *mac = &hw->mac;
1871 struct e1000_fc_info *fc = &hw->fc;
1872 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1873
1874 /* Repartition Pba for greater than 9k mtu
1875 * To take effect CTRL.RST is required.
1876 */
1877 switch (mac->type) {
1878 case e1000_i350:
1879 case e1000_i354:
1880 case e1000_82580:
1881 pba = rd32(E1000_RXPBS);
1882 pba = igb_rxpbs_adjust_82580(pba);
1883 break;
1884 case e1000_82576:
1885 pba = rd32(E1000_RXPBS);
1886 pba &= E1000_RXPBS_SIZE_MASK_82576;
1887 break;
1888 case e1000_82575:
1889 case e1000_i210:
1890 case e1000_i211:
1891 default:
1892 pba = E1000_PBA_34K;
1893 break;
1894 }
1895
1896 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1897 (mac->type < e1000_82576)) {
1898 /* adjust PBA for jumbo frames */
1899 wr32(E1000_PBA, pba);
1900
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
1906 * expressed in KB.
1907 */
1908 pba = rd32(E1000_PBA);
1909 /* upper 16 bits has Tx packet buffer allocation size in KB */
1910 tx_space = pba >> 16;
1911 /* lower 16 bits has Rx packet buffer allocation size in KB */
1912 pba &= 0xffff;
1913 /* the Tx fifo also stores 16 bytes of information about the Tx
1914 * but don't include ethernet FCS because hardware appends it
1915 */
1916 min_tx_space = (adapter->max_frame_size +
1917 sizeof(union e1000_adv_tx_desc) -
1918 ETH_FCS_LEN) * 2;
1919 min_tx_space = ALIGN(min_tx_space, 1024);
1920 min_tx_space >>= 10;
1921 /* software strips receive CRC, so leave room for it */
1922 min_rx_space = adapter->max_frame_size;
1923 min_rx_space = ALIGN(min_rx_space, 1024);
1924 min_rx_space >>= 10;
1925
1926 /* If current Tx allocation is less than the min Tx FIFO size,
1927 * and the min Tx FIFO size is less than the current Rx FIFO
1928 * allocation, take space away from current Rx allocation
1929 */
1930 if (tx_space < min_tx_space &&
1931 ((min_tx_space - tx_space) < pba)) {
1932 pba = pba - (min_tx_space - tx_space);
1933
1934 /* if short on Rx space, Rx wins and must trump Tx
1935 * adjustment
1936 */
1937 if (pba < min_rx_space)
1938 pba = min_rx_space;
1939 }
1940 wr32(E1000_PBA, pba);
1941 }
1942
1943 /* flow control settings */
1944 /* The high water mark must be low enough to fit one full frame
1945 * (or the size used for early receive) above it in the Rx FIFO.
1946 * Set it to the lower of:
1947 * - 90% of the Rx FIFO size, or
1948 * - the full Rx FIFO size minus one full frame
1949 */
1950 hwm = min(((pba << 10) * 9 / 10),
1951 ((pba << 10) - 2 * adapter->max_frame_size));
1952
1953 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
1954 fc->low_water = fc->high_water - 16;
1955 fc->pause_time = 0xFFFF;
1956 fc->send_xon = 1;
1957 fc->current_mode = fc->requested_mode;
1958
1959 /* disable receive for all VFs and wait one second */
1960 if (adapter->vfs_allocated_count) {
1961 int i;
1962
1963 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1964 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1965
1966 /* ping all the active vfs to let them know we are going down */
1967 igb_ping_all_vfs(adapter);
1968
1969 /* disable transmits and receives */
1970 wr32(E1000_VFRE, 0);
1971 wr32(E1000_VFTE, 0);
1972 }
1973
1974 /* Allow time for pending master requests to run */
1975 hw->mac.ops.reset_hw(hw);
1976 wr32(E1000_WUC, 0);
1977
1978 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1979 /* need to resetup here after media swap */
1980 adapter->ei.get_invariants(hw);
1981 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1982 }
1983 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1984 if (igb_enable_mas(adapter))
1985 dev_err(&pdev->dev,
1986 "Error enabling Media Auto Sense\n");
1987 }
1988 if (hw->mac.ops.init_hw(hw))
1989 dev_err(&pdev->dev, "Hardware Error\n");
1990
1991 /* Flow control settings reset on hardware reset, so guarantee flow
1992 * control is off when forcing speed.
1993 */
1994 if (!hw->mac.autoneg)
1995 igb_force_mac_fc(hw);
1996
1997 igb_init_dmac(adapter, pba);
1998 #ifdef CONFIG_IGB_HWMON
1999 /* Re-initialize the thermal sensor on i350 devices. */
2000 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2001 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2002 /* If present, re-initialize the external thermal sensor
2003 * interface.
2004 */
2005 if (adapter->ets)
2006 mac->ops.init_thermal_sensor_thresh(hw);
2007 }
2008 }
2009 #endif
2010 /* Re-establish EEE setting */
2011 if (hw->phy.media_type == e1000_media_type_copper) {
2012 switch (mac->type) {
2013 case e1000_i350:
2014 case e1000_i210:
2015 case e1000_i211:
2016 igb_set_eee_i350(hw, true, true);
2017 break;
2018 case e1000_i354:
2019 igb_set_eee_i354(hw, true, true);
2020 break;
2021 default:
2022 break;
2023 }
2024 }
2025 if (!netif_running(adapter->netdev))
2026 igb_power_down_link(adapter);
2027
2028 igb_update_mng_vlan(adapter);
2029
2030 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2031 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2032
2033 /* Re-enable PTP, where applicable. */
2034 igb_ptp_reset(adapter);
2035
2036 igb_get_phy_info(hw);
2037 }
2038
2039 static netdev_features_t igb_fix_features(struct net_device *netdev,
2040 netdev_features_t features)
2041 {
2042 /* Since there is no support for separate Rx/Tx vlan accel
2043 * enable/disable make sure Tx flag is always in same state as Rx.
2044 */
2045 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2046 features |= NETIF_F_HW_VLAN_CTAG_TX;
2047 else
2048 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2049
2050 return features;
2051 }
2052
2053 static int igb_set_features(struct net_device *netdev,
2054 netdev_features_t features)
2055 {
2056 netdev_features_t changed = netdev->features ^ features;
2057 struct igb_adapter *adapter = netdev_priv(netdev);
2058
2059 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2060 igb_vlan_mode(netdev, features);
2061
2062 if (!(changed & NETIF_F_RXALL))
2063 return 0;
2064
2065 netdev->features = features;
2066
2067 if (netif_running(netdev))
2068 igb_reinit_locked(adapter);
2069 else
2070 igb_reset(adapter);
2071
2072 return 0;
2073 }
2074
2075 static const struct net_device_ops igb_netdev_ops = {
2076 .ndo_open = igb_open,
2077 .ndo_stop = igb_close,
2078 .ndo_start_xmit = igb_xmit_frame,
2079 .ndo_get_stats64 = igb_get_stats64,
2080 .ndo_set_rx_mode = igb_set_rx_mode,
2081 .ndo_set_mac_address = igb_set_mac,
2082 .ndo_change_mtu = igb_change_mtu,
2083 .ndo_do_ioctl = igb_ioctl,
2084 .ndo_tx_timeout = igb_tx_timeout,
2085 .ndo_validate_addr = eth_validate_addr,
2086 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2087 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2088 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2089 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2090 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2091 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2092 .ndo_get_vf_config = igb_ndo_get_vf_config,
2093 #ifdef CONFIG_NET_POLL_CONTROLLER
2094 .ndo_poll_controller = igb_netpoll,
2095 #endif
2096 .ndo_fix_features = igb_fix_features,
2097 .ndo_set_features = igb_set_features,
2098 };
2099
2100 /**
2101 * igb_set_fw_version - Configure version string for ethtool
2102 * @adapter: adapter struct
2103 **/
2104 void igb_set_fw_version(struct igb_adapter *adapter)
2105 {
2106 struct e1000_hw *hw = &adapter->hw;
2107 struct e1000_fw_version fw;
2108
2109 igb_get_fw_version(hw, &fw);
2110
2111 switch (hw->mac.type) {
2112 case e1000_i210:
2113 case e1000_i211:
2114 if (!(igb_get_flash_presence_i210(hw))) {
2115 snprintf(adapter->fw_version,
2116 sizeof(adapter->fw_version),
2117 "%2d.%2d-%d",
2118 fw.invm_major, fw.invm_minor,
2119 fw.invm_img_type);
2120 break;
2121 }
2122 /* fall through */
2123 default:
2124 /* if option is rom valid, display its version too */
2125 if (fw.or_valid) {
2126 snprintf(adapter->fw_version,
2127 sizeof(adapter->fw_version),
2128 "%d.%d, 0x%08x, %d.%d.%d",
2129 fw.eep_major, fw.eep_minor, fw.etrack_id,
2130 fw.or_major, fw.or_build, fw.or_patch);
2131 /* no option rom */
2132 } else if (fw.etrack_id != 0X0000) {
2133 snprintf(adapter->fw_version,
2134 sizeof(adapter->fw_version),
2135 "%d.%d, 0x%08x",
2136 fw.eep_major, fw.eep_minor, fw.etrack_id);
2137 } else {
2138 snprintf(adapter->fw_version,
2139 sizeof(adapter->fw_version),
2140 "%d.%d.%d",
2141 fw.eep_major, fw.eep_minor, fw.eep_build);
2142 }
2143 break;
2144 }
2145 }
2146
2147 /**
2148 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2149 *
2150 * @adapter: adapter struct
2151 **/
2152 static void igb_init_mas(struct igb_adapter *adapter)
2153 {
2154 struct e1000_hw *hw = &adapter->hw;
2155 u16 eeprom_data;
2156
2157 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2158 switch (hw->bus.func) {
2159 case E1000_FUNC_0:
2160 if (eeprom_data & IGB_MAS_ENABLE_0) {
2161 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2162 netdev_info(adapter->netdev,
2163 "MAS: Enabling Media Autosense for port %d\n",
2164 hw->bus.func);
2165 }
2166 break;
2167 case E1000_FUNC_1:
2168 if (eeprom_data & IGB_MAS_ENABLE_1) {
2169 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2170 netdev_info(adapter->netdev,
2171 "MAS: Enabling Media Autosense for port %d\n",
2172 hw->bus.func);
2173 }
2174 break;
2175 case E1000_FUNC_2:
2176 if (eeprom_data & IGB_MAS_ENABLE_2) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 case E1000_FUNC_3:
2184 if (eeprom_data & IGB_MAS_ENABLE_3) {
2185 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2186 netdev_info(adapter->netdev,
2187 "MAS: Enabling Media Autosense for port %d\n",
2188 hw->bus.func);
2189 }
2190 break;
2191 default:
2192 /* Shouldn't get here */
2193 netdev_err(adapter->netdev,
2194 "MAS: Invalid port configuration, returning\n");
2195 break;
2196 }
2197 }
2198
2199 /**
2200 * igb_init_i2c - Init I2C interface
2201 * @adapter: pointer to adapter structure
2202 **/
2203 static s32 igb_init_i2c(struct igb_adapter *adapter)
2204 {
2205 s32 status = 0;
2206
2207 /* I2C interface supported on i350 devices */
2208 if (adapter->hw.mac.type != e1000_i350)
2209 return 0;
2210
2211 /* Initialize the i2c bus which is controlled by the registers.
2212 * This bus will use the i2c_algo_bit structue that implements
2213 * the protocol through toggling of the 4 bits in the register.
2214 */
2215 adapter->i2c_adap.owner = THIS_MODULE;
2216 adapter->i2c_algo = igb_i2c_algo;
2217 adapter->i2c_algo.data = adapter;
2218 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2219 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2220 strlcpy(adapter->i2c_adap.name, "igb BB",
2221 sizeof(adapter->i2c_adap.name));
2222 status = i2c_bit_add_bus(&adapter->i2c_adap);
2223 return status;
2224 }
2225
2226 /**
2227 * igb_probe - Device Initialization Routine
2228 * @pdev: PCI device information struct
2229 * @ent: entry in igb_pci_tbl
2230 *
2231 * Returns 0 on success, negative on failure
2232 *
2233 * igb_probe initializes an adapter identified by a pci_dev structure.
2234 * The OS initialization, configuring of the adapter private structure,
2235 * and a hardware reset occur.
2236 **/
2237 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2238 {
2239 struct net_device *netdev;
2240 struct igb_adapter *adapter;
2241 struct e1000_hw *hw;
2242 u16 eeprom_data = 0;
2243 s32 ret_val;
2244 static int global_quad_port_a; /* global quad port a indication */
2245 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2246 int err, pci_using_dac;
2247 u8 part_str[E1000_PBANUM_LENGTH];
2248
2249 /* Catch broken hardware that put the wrong VF device ID in
2250 * the PCIe SR-IOV capability.
2251 */
2252 if (pdev->is_virtfn) {
2253 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2254 pci_name(pdev), pdev->vendor, pdev->device);
2255 return -EINVAL;
2256 }
2257
2258 err = pci_enable_device_mem(pdev);
2259 if (err)
2260 return err;
2261
2262 pci_using_dac = 0;
2263 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2264 if (!err) {
2265 pci_using_dac = 1;
2266 } else {
2267 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2268 if (err) {
2269 dev_err(&pdev->dev,
2270 "No usable DMA configuration, aborting\n");
2271 goto err_dma;
2272 }
2273 }
2274
2275 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2276 IORESOURCE_MEM),
2277 igb_driver_name);
2278 if (err)
2279 goto err_pci_reg;
2280
2281 pci_enable_pcie_error_reporting(pdev);
2282
2283 pci_set_master(pdev);
2284 pci_save_state(pdev);
2285
2286 err = -ENOMEM;
2287 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2288 IGB_MAX_TX_QUEUES);
2289 if (!netdev)
2290 goto err_alloc_etherdev;
2291
2292 SET_NETDEV_DEV(netdev, &pdev->dev);
2293
2294 pci_set_drvdata(pdev, netdev);
2295 adapter = netdev_priv(netdev);
2296 adapter->netdev = netdev;
2297 adapter->pdev = pdev;
2298 hw = &adapter->hw;
2299 hw->back = adapter;
2300 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2301
2302 err = -EIO;
2303 hw->hw_addr = pci_iomap(pdev, 0, 0);
2304 if (!hw->hw_addr)
2305 goto err_ioremap;
2306
2307 netdev->netdev_ops = &igb_netdev_ops;
2308 igb_set_ethtool_ops(netdev);
2309 netdev->watchdog_timeo = 5 * HZ;
2310
2311 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2312
2313 netdev->mem_start = pci_resource_start(pdev, 0);
2314 netdev->mem_end = pci_resource_end(pdev, 0);
2315
2316 /* PCI config space info */
2317 hw->vendor_id = pdev->vendor;
2318 hw->device_id = pdev->device;
2319 hw->revision_id = pdev->revision;
2320 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2321 hw->subsystem_device_id = pdev->subsystem_device;
2322
2323 /* Copy the default MAC, PHY and NVM function pointers */
2324 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2325 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2326 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2327 /* Initialize skew-specific constants */
2328 err = ei->get_invariants(hw);
2329 if (err)
2330 goto err_sw_init;
2331
2332 /* setup the private structure */
2333 err = igb_sw_init(adapter);
2334 if (err)
2335 goto err_sw_init;
2336
2337 igb_get_bus_info_pcie(hw);
2338
2339 hw->phy.autoneg_wait_to_complete = false;
2340
2341 /* Copper options */
2342 if (hw->phy.media_type == e1000_media_type_copper) {
2343 hw->phy.mdix = AUTO_ALL_MODES;
2344 hw->phy.disable_polarity_correction = false;
2345 hw->phy.ms_type = e1000_ms_hw_default;
2346 }
2347
2348 if (igb_check_reset_block(hw))
2349 dev_info(&pdev->dev,
2350 "PHY reset is blocked due to SOL/IDER session.\n");
2351
2352 /* features is initialized to 0 in allocation, it might have bits
2353 * set by igb_sw_init so we should use an or instead of an
2354 * assignment.
2355 */
2356 netdev->features |= NETIF_F_SG |
2357 NETIF_F_IP_CSUM |
2358 NETIF_F_IPV6_CSUM |
2359 NETIF_F_TSO |
2360 NETIF_F_TSO6 |
2361 NETIF_F_RXHASH |
2362 NETIF_F_RXCSUM |
2363 NETIF_F_HW_VLAN_CTAG_RX |
2364 NETIF_F_HW_VLAN_CTAG_TX;
2365
2366 /* copy netdev features into list of user selectable features */
2367 netdev->hw_features |= netdev->features;
2368 netdev->hw_features |= NETIF_F_RXALL;
2369
2370 /* set this bit last since it cannot be part of hw_features */
2371 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2372
2373 netdev->vlan_features |= NETIF_F_TSO |
2374 NETIF_F_TSO6 |
2375 NETIF_F_IP_CSUM |
2376 NETIF_F_IPV6_CSUM |
2377 NETIF_F_SG;
2378
2379 netdev->priv_flags |= IFF_SUPP_NOFCS;
2380
2381 if (pci_using_dac) {
2382 netdev->features |= NETIF_F_HIGHDMA;
2383 netdev->vlan_features |= NETIF_F_HIGHDMA;
2384 }
2385
2386 if (hw->mac.type >= e1000_82576) {
2387 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2388 netdev->features |= NETIF_F_SCTP_CSUM;
2389 }
2390
2391 netdev->priv_flags |= IFF_UNICAST_FLT;
2392
2393 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2394
2395 /* before reading the NVM, reset the controller to put the device in a
2396 * known good starting state
2397 */
2398 hw->mac.ops.reset_hw(hw);
2399
2400 /* make sure the NVM is good , i211/i210 parts can have special NVM
2401 * that doesn't contain a checksum
2402 */
2403 switch (hw->mac.type) {
2404 case e1000_i210:
2405 case e1000_i211:
2406 if (igb_get_flash_presence_i210(hw)) {
2407 if (hw->nvm.ops.validate(hw) < 0) {
2408 dev_err(&pdev->dev,
2409 "The NVM Checksum Is Not Valid\n");
2410 err = -EIO;
2411 goto err_eeprom;
2412 }
2413 }
2414 break;
2415 default:
2416 if (hw->nvm.ops.validate(hw) < 0) {
2417 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2418 err = -EIO;
2419 goto err_eeprom;
2420 }
2421 break;
2422 }
2423
2424 /* copy the MAC address out of the NVM */
2425 if (hw->mac.ops.read_mac_addr(hw))
2426 dev_err(&pdev->dev, "NVM Read Error\n");
2427
2428 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2429
2430 if (!is_valid_ether_addr(netdev->dev_addr)) {
2431 dev_err(&pdev->dev, "Invalid MAC Address\n");
2432 err = -EIO;
2433 goto err_eeprom;
2434 }
2435
2436 /* get firmware version for ethtool -i */
2437 igb_set_fw_version(adapter);
2438
2439 /* configure RXPBSIZE and TXPBSIZE */
2440 if (hw->mac.type == e1000_i210) {
2441 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2442 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2443 }
2444
2445 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2446 (unsigned long) adapter);
2447 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2448 (unsigned long) adapter);
2449
2450 INIT_WORK(&adapter->reset_task, igb_reset_task);
2451 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2452
2453 /* Initialize link properties that are user-changeable */
2454 adapter->fc_autoneg = true;
2455 hw->mac.autoneg = true;
2456 hw->phy.autoneg_advertised = 0x2f;
2457
2458 hw->fc.requested_mode = e1000_fc_default;
2459 hw->fc.current_mode = e1000_fc_default;
2460
2461 igb_validate_mdi_setting(hw);
2462
2463 /* By default, support wake on port A */
2464 if (hw->bus.func == 0)
2465 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2466
2467 /* Check the NVM for wake support on non-port A ports */
2468 if (hw->mac.type >= e1000_82580)
2469 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2470 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2471 &eeprom_data);
2472 else if (hw->bus.func == 1)
2473 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2474
2475 if (eeprom_data & IGB_EEPROM_APME)
2476 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2477
2478 /* now that we have the eeprom settings, apply the special cases where
2479 * the eeprom may be wrong or the board simply won't support wake on
2480 * lan on a particular port
2481 */
2482 switch (pdev->device) {
2483 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2484 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2485 break;
2486 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2487 case E1000_DEV_ID_82576_FIBER:
2488 case E1000_DEV_ID_82576_SERDES:
2489 /* Wake events only supported on port A for dual fiber
2490 * regardless of eeprom setting
2491 */
2492 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2493 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2494 break;
2495 case E1000_DEV_ID_82576_QUAD_COPPER:
2496 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2497 /* if quad port adapter, disable WoL on all but port A */
2498 if (global_quad_port_a != 0)
2499 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2500 else
2501 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2502 /* Reset for multiple quad port adapters */
2503 if (++global_quad_port_a == 4)
2504 global_quad_port_a = 0;
2505 break;
2506 default:
2507 /* If the device can't wake, don't set software support */
2508 if (!device_can_wakeup(&adapter->pdev->dev))
2509 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2510 }
2511
2512 /* initialize the wol settings based on the eeprom settings */
2513 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2514 adapter->wol |= E1000_WUFC_MAG;
2515
2516 /* Some vendors want WoL disabled by default, but still supported */
2517 if ((hw->mac.type == e1000_i350) &&
2518 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2519 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2520 adapter->wol = 0;
2521 }
2522
2523 device_set_wakeup_enable(&adapter->pdev->dev,
2524 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2525
2526 /* reset the hardware with the new settings */
2527 igb_reset(adapter);
2528
2529 /* Init the I2C interface */
2530 err = igb_init_i2c(adapter);
2531 if (err) {
2532 dev_err(&pdev->dev, "failed to init i2c interface\n");
2533 goto err_eeprom;
2534 }
2535
2536 /* let the f/w know that the h/w is now under the control of the
2537 * driver.
2538 */
2539 igb_get_hw_control(adapter);
2540
2541 strcpy(netdev->name, "eth%d");
2542 err = register_netdev(netdev);
2543 if (err)
2544 goto err_register;
2545
2546 /* carrier off reporting is important to ethtool even BEFORE open */
2547 netif_carrier_off(netdev);
2548
2549 #ifdef CONFIG_IGB_DCA
2550 if (dca_add_requester(&pdev->dev) == 0) {
2551 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2552 dev_info(&pdev->dev, "DCA enabled\n");
2553 igb_setup_dca(adapter);
2554 }
2555
2556 #endif
2557 #ifdef CONFIG_IGB_HWMON
2558 /* Initialize the thermal sensor on i350 devices. */
2559 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2560 u16 ets_word;
2561
2562 /* Read the NVM to determine if this i350 device supports an
2563 * external thermal sensor.
2564 */
2565 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2566 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2567 adapter->ets = true;
2568 else
2569 adapter->ets = false;
2570 if (igb_sysfs_init(adapter))
2571 dev_err(&pdev->dev,
2572 "failed to allocate sysfs resources\n");
2573 } else {
2574 adapter->ets = false;
2575 }
2576 #endif
2577 /* Check if Media Autosense is enabled */
2578 adapter->ei = *ei;
2579 if (hw->dev_spec._82575.mas_capable)
2580 igb_init_mas(adapter);
2581
2582 /* do hw tstamp init after resetting */
2583 igb_ptp_init(adapter);
2584
2585 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2586 /* print bus type/speed/width info, not applicable to i354 */
2587 if (hw->mac.type != e1000_i354) {
2588 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2589 netdev->name,
2590 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2591 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2592 "unknown"),
2593 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2594 "Width x4" :
2595 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2596 "Width x2" :
2597 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2598 "Width x1" : "unknown"), netdev->dev_addr);
2599 }
2600
2601 if ((hw->mac.type >= e1000_i210 ||
2602 igb_get_flash_presence_i210(hw))) {
2603 ret_val = igb_read_part_string(hw, part_str,
2604 E1000_PBANUM_LENGTH);
2605 } else {
2606 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2607 }
2608
2609 if (ret_val)
2610 strcpy(part_str, "Unknown");
2611 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2612 dev_info(&pdev->dev,
2613 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2614 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
2615 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2616 adapter->num_rx_queues, adapter->num_tx_queues);
2617 if (hw->phy.media_type == e1000_media_type_copper) {
2618 switch (hw->mac.type) {
2619 case e1000_i350:
2620 case e1000_i210:
2621 case e1000_i211:
2622 /* Enable EEE for internal copper PHY devices */
2623 err = igb_set_eee_i350(hw, true, true);
2624 if ((!err) &&
2625 (!hw->dev_spec._82575.eee_disable)) {
2626 adapter->eee_advert =
2627 MDIO_EEE_100TX | MDIO_EEE_1000T;
2628 adapter->flags |= IGB_FLAG_EEE;
2629 }
2630 break;
2631 case e1000_i354:
2632 if ((rd32(E1000_CTRL_EXT) &
2633 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2634 err = igb_set_eee_i354(hw, true, true);
2635 if ((!err) &&
2636 (!hw->dev_spec._82575.eee_disable)) {
2637 adapter->eee_advert =
2638 MDIO_EEE_100TX | MDIO_EEE_1000T;
2639 adapter->flags |= IGB_FLAG_EEE;
2640 }
2641 }
2642 break;
2643 default:
2644 break;
2645 }
2646 }
2647 pm_runtime_put_noidle(&pdev->dev);
2648 return 0;
2649
2650 err_register:
2651 igb_release_hw_control(adapter);
2652 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2653 err_eeprom:
2654 if (!igb_check_reset_block(hw))
2655 igb_reset_phy(hw);
2656
2657 if (hw->flash_address)
2658 iounmap(hw->flash_address);
2659 err_sw_init:
2660 igb_clear_interrupt_scheme(adapter);
2661 pci_iounmap(pdev, hw->hw_addr);
2662 err_ioremap:
2663 free_netdev(netdev);
2664 err_alloc_etherdev:
2665 pci_release_selected_regions(pdev,
2666 pci_select_bars(pdev, IORESOURCE_MEM));
2667 err_pci_reg:
2668 err_dma:
2669 pci_disable_device(pdev);
2670 return err;
2671 }
2672
2673 #ifdef CONFIG_PCI_IOV
2674 static int igb_disable_sriov(struct pci_dev *pdev)
2675 {
2676 struct net_device *netdev = pci_get_drvdata(pdev);
2677 struct igb_adapter *adapter = netdev_priv(netdev);
2678 struct e1000_hw *hw = &adapter->hw;
2679
2680 /* reclaim resources allocated to VFs */
2681 if (adapter->vf_data) {
2682 /* disable iov and allow time for transactions to clear */
2683 if (pci_vfs_assigned(pdev)) {
2684 dev_warn(&pdev->dev,
2685 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2686 return -EPERM;
2687 } else {
2688 pci_disable_sriov(pdev);
2689 msleep(500);
2690 }
2691
2692 kfree(adapter->vf_data);
2693 adapter->vf_data = NULL;
2694 adapter->vfs_allocated_count = 0;
2695 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2696 wrfl();
2697 msleep(100);
2698 dev_info(&pdev->dev, "IOV Disabled\n");
2699
2700 /* Re-enable DMA Coalescing flag since IOV is turned off */
2701 adapter->flags |= IGB_FLAG_DMAC;
2702 }
2703
2704 return 0;
2705 }
2706
2707 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2708 {
2709 struct net_device *netdev = pci_get_drvdata(pdev);
2710 struct igb_adapter *adapter = netdev_priv(netdev);
2711 int old_vfs = pci_num_vf(pdev);
2712 int err = 0;
2713 int i;
2714
2715 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
2716 err = -EPERM;
2717 goto out;
2718 }
2719 if (!num_vfs)
2720 goto out;
2721
2722 if (old_vfs) {
2723 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2724 old_vfs, max_vfs);
2725 adapter->vfs_allocated_count = old_vfs;
2726 } else
2727 adapter->vfs_allocated_count = num_vfs;
2728
2729 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2730 sizeof(struct vf_data_storage), GFP_KERNEL);
2731
2732 /* if allocation failed then we do not support SR-IOV */
2733 if (!adapter->vf_data) {
2734 adapter->vfs_allocated_count = 0;
2735 dev_err(&pdev->dev,
2736 "Unable to allocate memory for VF Data Storage\n");
2737 err = -ENOMEM;
2738 goto out;
2739 }
2740
2741 /* only call pci_enable_sriov() if no VFs are allocated already */
2742 if (!old_vfs) {
2743 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2744 if (err)
2745 goto err_out;
2746 }
2747 dev_info(&pdev->dev, "%d VFs allocated\n",
2748 adapter->vfs_allocated_count);
2749 for (i = 0; i < adapter->vfs_allocated_count; i++)
2750 igb_vf_configure(adapter, i);
2751
2752 /* DMA Coalescing is not supported in IOV mode. */
2753 adapter->flags &= ~IGB_FLAG_DMAC;
2754 goto out;
2755
2756 err_out:
2757 kfree(adapter->vf_data);
2758 adapter->vf_data = NULL;
2759 adapter->vfs_allocated_count = 0;
2760 out:
2761 return err;
2762 }
2763
2764 #endif
2765 /**
2766 * igb_remove_i2c - Cleanup I2C interface
2767 * @adapter: pointer to adapter structure
2768 **/
2769 static void igb_remove_i2c(struct igb_adapter *adapter)
2770 {
2771 /* free the adapter bus structure */
2772 i2c_del_adapter(&adapter->i2c_adap);
2773 }
2774
2775 /**
2776 * igb_remove - Device Removal Routine
2777 * @pdev: PCI device information struct
2778 *
2779 * igb_remove is called by the PCI subsystem to alert the driver
2780 * that it should release a PCI device. The could be caused by a
2781 * Hot-Plug event, or because the driver is going to be removed from
2782 * memory.
2783 **/
2784 static void igb_remove(struct pci_dev *pdev)
2785 {
2786 struct net_device *netdev = pci_get_drvdata(pdev);
2787 struct igb_adapter *adapter = netdev_priv(netdev);
2788 struct e1000_hw *hw = &adapter->hw;
2789
2790 pm_runtime_get_noresume(&pdev->dev);
2791 #ifdef CONFIG_IGB_HWMON
2792 igb_sysfs_exit(adapter);
2793 #endif
2794 igb_remove_i2c(adapter);
2795 igb_ptp_stop(adapter);
2796 /* The watchdog timer may be rescheduled, so explicitly
2797 * disable watchdog from being rescheduled.
2798 */
2799 set_bit(__IGB_DOWN, &adapter->state);
2800 del_timer_sync(&adapter->watchdog_timer);
2801 del_timer_sync(&adapter->phy_info_timer);
2802
2803 cancel_work_sync(&adapter->reset_task);
2804 cancel_work_sync(&adapter->watchdog_task);
2805
2806 #ifdef CONFIG_IGB_DCA
2807 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2808 dev_info(&pdev->dev, "DCA disabled\n");
2809 dca_remove_requester(&pdev->dev);
2810 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2811 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2812 }
2813 #endif
2814
2815 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2816 * would have already happened in close and is redundant.
2817 */
2818 igb_release_hw_control(adapter);
2819
2820 unregister_netdev(netdev);
2821
2822 igb_clear_interrupt_scheme(adapter);
2823
2824 #ifdef CONFIG_PCI_IOV
2825 igb_disable_sriov(pdev);
2826 #endif
2827
2828 pci_iounmap(pdev, hw->hw_addr);
2829 if (hw->flash_address)
2830 iounmap(hw->flash_address);
2831 pci_release_selected_regions(pdev,
2832 pci_select_bars(pdev, IORESOURCE_MEM));
2833
2834 kfree(adapter->shadow_vfta);
2835 free_netdev(netdev);
2836
2837 pci_disable_pcie_error_reporting(pdev);
2838
2839 pci_disable_device(pdev);
2840 }
2841
2842 /**
2843 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2844 * @adapter: board private structure to initialize
2845 *
2846 * This function initializes the vf specific data storage and then attempts to
2847 * allocate the VFs. The reason for ordering it this way is because it is much
2848 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2849 * the memory for the VFs.
2850 **/
2851 static void igb_probe_vfs(struct igb_adapter *adapter)
2852 {
2853 #ifdef CONFIG_PCI_IOV
2854 struct pci_dev *pdev = adapter->pdev;
2855 struct e1000_hw *hw = &adapter->hw;
2856
2857 /* Virtualization features not supported on i210 family. */
2858 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2859 return;
2860
2861 pci_sriov_set_totalvfs(pdev, 7);
2862 igb_pci_enable_sriov(pdev, max_vfs);
2863
2864 #endif /* CONFIG_PCI_IOV */
2865 }
2866
2867 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2868 {
2869 struct e1000_hw *hw = &adapter->hw;
2870 u32 max_rss_queues;
2871
2872 /* Determine the maximum number of RSS queues supported. */
2873 switch (hw->mac.type) {
2874 case e1000_i211:
2875 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2876 break;
2877 case e1000_82575:
2878 case e1000_i210:
2879 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2880 break;
2881 case e1000_i350:
2882 /* I350 cannot do RSS and SR-IOV at the same time */
2883 if (!!adapter->vfs_allocated_count) {
2884 max_rss_queues = 1;
2885 break;
2886 }
2887 /* fall through */
2888 case e1000_82576:
2889 if (!!adapter->vfs_allocated_count) {
2890 max_rss_queues = 2;
2891 break;
2892 }
2893 /* fall through */
2894 case e1000_82580:
2895 case e1000_i354:
2896 default:
2897 max_rss_queues = IGB_MAX_RX_QUEUES;
2898 break;
2899 }
2900
2901 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2902
2903 /* Determine if we need to pair queues. */
2904 switch (hw->mac.type) {
2905 case e1000_82575:
2906 case e1000_i211:
2907 /* Device supports enough interrupts without queue pairing. */
2908 break;
2909 case e1000_82576:
2910 /* If VFs are going to be allocated with RSS queues then we
2911 * should pair the queues in order to conserve interrupts due
2912 * to limited supply.
2913 */
2914 if ((adapter->rss_queues > 1) &&
2915 (adapter->vfs_allocated_count > 6))
2916 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2917 /* fall through */
2918 case e1000_82580:
2919 case e1000_i350:
2920 case e1000_i354:
2921 case e1000_i210:
2922 default:
2923 /* If rss_queues > half of max_rss_queues, pair the queues in
2924 * order to conserve interrupts due to limited supply.
2925 */
2926 if (adapter->rss_queues > (max_rss_queues / 2))
2927 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2928 break;
2929 }
2930 }
2931
2932 /**
2933 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2934 * @adapter: board private structure to initialize
2935 *
2936 * igb_sw_init initializes the Adapter private data structure.
2937 * Fields are initialized based on PCI device information and
2938 * OS network device settings (MTU size).
2939 **/
2940 static int igb_sw_init(struct igb_adapter *adapter)
2941 {
2942 struct e1000_hw *hw = &adapter->hw;
2943 struct net_device *netdev = adapter->netdev;
2944 struct pci_dev *pdev = adapter->pdev;
2945
2946 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2947
2948 /* set default ring sizes */
2949 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2950 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2951
2952 /* set default ITR values */
2953 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2954 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2955
2956 /* set default work limits */
2957 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2958
2959 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2960 VLAN_HLEN;
2961 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2962
2963 spin_lock_init(&adapter->stats64_lock);
2964 #ifdef CONFIG_PCI_IOV
2965 switch (hw->mac.type) {
2966 case e1000_82576:
2967 case e1000_i350:
2968 if (max_vfs > 7) {
2969 dev_warn(&pdev->dev,
2970 "Maximum of 7 VFs per PF, using max\n");
2971 max_vfs = adapter->vfs_allocated_count = 7;
2972 } else
2973 adapter->vfs_allocated_count = max_vfs;
2974 if (adapter->vfs_allocated_count)
2975 dev_warn(&pdev->dev,
2976 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2977 break;
2978 default:
2979 break;
2980 }
2981 #endif /* CONFIG_PCI_IOV */
2982
2983 igb_init_queue_configuration(adapter);
2984
2985 /* Setup and initialize a copy of the hw vlan table array */
2986 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2987 GFP_ATOMIC);
2988
2989 /* This call may decrease the number of queues */
2990 if (igb_init_interrupt_scheme(adapter, true)) {
2991 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2992 return -ENOMEM;
2993 }
2994
2995 igb_probe_vfs(adapter);
2996
2997 /* Explicitly disable IRQ since the NIC can be in any state. */
2998 igb_irq_disable(adapter);
2999
3000 if (hw->mac.type >= e1000_i350)
3001 adapter->flags &= ~IGB_FLAG_DMAC;
3002
3003 set_bit(__IGB_DOWN, &adapter->state);
3004 return 0;
3005 }
3006
3007 /**
3008 * igb_open - Called when a network interface is made active
3009 * @netdev: network interface device structure
3010 *
3011 * Returns 0 on success, negative value on failure
3012 *
3013 * The open entry point is called when a network interface is made
3014 * active by the system (IFF_UP). At this point all resources needed
3015 * for transmit and receive operations are allocated, the interrupt
3016 * handler is registered with the OS, the watchdog timer is started,
3017 * and the stack is notified that the interface is ready.
3018 **/
3019 static int __igb_open(struct net_device *netdev, bool resuming)
3020 {
3021 struct igb_adapter *adapter = netdev_priv(netdev);
3022 struct e1000_hw *hw = &adapter->hw;
3023 struct pci_dev *pdev = adapter->pdev;
3024 int err;
3025 int i;
3026
3027 /* disallow open during test */
3028 if (test_bit(__IGB_TESTING, &adapter->state)) {
3029 WARN_ON(resuming);
3030 return -EBUSY;
3031 }
3032
3033 if (!resuming)
3034 pm_runtime_get_sync(&pdev->dev);
3035
3036 netif_carrier_off(netdev);
3037
3038 /* allocate transmit descriptors */
3039 err = igb_setup_all_tx_resources(adapter);
3040 if (err)
3041 goto err_setup_tx;
3042
3043 /* allocate receive descriptors */
3044 err = igb_setup_all_rx_resources(adapter);
3045 if (err)
3046 goto err_setup_rx;
3047
3048 igb_power_up_link(adapter);
3049
3050 /* before we allocate an interrupt, we must be ready to handle it.
3051 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3052 * as soon as we call pci_request_irq, so we have to setup our
3053 * clean_rx handler before we do so.
3054 */
3055 igb_configure(adapter);
3056
3057 err = igb_request_irq(adapter);
3058 if (err)
3059 goto err_req_irq;
3060
3061 /* Notify the stack of the actual queue counts. */
3062 err = netif_set_real_num_tx_queues(adapter->netdev,
3063 adapter->num_tx_queues);
3064 if (err)
3065 goto err_set_queues;
3066
3067 err = netif_set_real_num_rx_queues(adapter->netdev,
3068 adapter->num_rx_queues);
3069 if (err)
3070 goto err_set_queues;
3071
3072 /* From here on the code is the same as igb_up() */
3073 clear_bit(__IGB_DOWN, &adapter->state);
3074
3075 for (i = 0; i < adapter->num_q_vectors; i++)
3076 napi_enable(&(adapter->q_vector[i]->napi));
3077
3078 /* Clear any pending interrupts. */
3079 rd32(E1000_ICR);
3080
3081 igb_irq_enable(adapter);
3082
3083 /* notify VFs that reset has been completed */
3084 if (adapter->vfs_allocated_count) {
3085 u32 reg_data = rd32(E1000_CTRL_EXT);
3086
3087 reg_data |= E1000_CTRL_EXT_PFRSTD;
3088 wr32(E1000_CTRL_EXT, reg_data);
3089 }
3090
3091 netif_tx_start_all_queues(netdev);
3092
3093 if (!resuming)
3094 pm_runtime_put(&pdev->dev);
3095
3096 /* start the watchdog. */
3097 hw->mac.get_link_status = 1;
3098 schedule_work(&adapter->watchdog_task);
3099
3100 return 0;
3101
3102 err_set_queues:
3103 igb_free_irq(adapter);
3104 err_req_irq:
3105 igb_release_hw_control(adapter);
3106 igb_power_down_link(adapter);
3107 igb_free_all_rx_resources(adapter);
3108 err_setup_rx:
3109 igb_free_all_tx_resources(adapter);
3110 err_setup_tx:
3111 igb_reset(adapter);
3112 if (!resuming)
3113 pm_runtime_put(&pdev->dev);
3114
3115 return err;
3116 }
3117
3118 static int igb_open(struct net_device *netdev)
3119 {
3120 return __igb_open(netdev, false);
3121 }
3122
3123 /**
3124 * igb_close - Disables a network interface
3125 * @netdev: network interface device structure
3126 *
3127 * Returns 0, this is not allowed to fail
3128 *
3129 * The close entry point is called when an interface is de-activated
3130 * by the OS. The hardware is still under the driver's control, but
3131 * needs to be disabled. A global MAC reset is issued to stop the
3132 * hardware, and all transmit and receive resources are freed.
3133 **/
3134 static int __igb_close(struct net_device *netdev, bool suspending)
3135 {
3136 struct igb_adapter *adapter = netdev_priv(netdev);
3137 struct pci_dev *pdev = adapter->pdev;
3138
3139 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3140
3141 if (!suspending)
3142 pm_runtime_get_sync(&pdev->dev);
3143
3144 igb_down(adapter);
3145 igb_free_irq(adapter);
3146
3147 igb_free_all_tx_resources(adapter);
3148 igb_free_all_rx_resources(adapter);
3149
3150 if (!suspending)
3151 pm_runtime_put_sync(&pdev->dev);
3152 return 0;
3153 }
3154
3155 static int igb_close(struct net_device *netdev)
3156 {
3157 return __igb_close(netdev, false);
3158 }
3159
3160 /**
3161 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3162 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3163 *
3164 * Return 0 on success, negative on failure
3165 **/
3166 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3167 {
3168 struct device *dev = tx_ring->dev;
3169 int size;
3170
3171 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3172
3173 tx_ring->tx_buffer_info = vzalloc(size);
3174 if (!tx_ring->tx_buffer_info)
3175 goto err;
3176
3177 /* round up to nearest 4K */
3178 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3179 tx_ring->size = ALIGN(tx_ring->size, 4096);
3180
3181 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3182 &tx_ring->dma, GFP_KERNEL);
3183 if (!tx_ring->desc)
3184 goto err;
3185
3186 tx_ring->next_to_use = 0;
3187 tx_ring->next_to_clean = 0;
3188
3189 return 0;
3190
3191 err:
3192 vfree(tx_ring->tx_buffer_info);
3193 tx_ring->tx_buffer_info = NULL;
3194 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3195 return -ENOMEM;
3196 }
3197
3198 /**
3199 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3200 * (Descriptors) for all queues
3201 * @adapter: board private structure
3202 *
3203 * Return 0 on success, negative on failure
3204 **/
3205 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3206 {
3207 struct pci_dev *pdev = adapter->pdev;
3208 int i, err = 0;
3209
3210 for (i = 0; i < adapter->num_tx_queues; i++) {
3211 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3212 if (err) {
3213 dev_err(&pdev->dev,
3214 "Allocation for Tx Queue %u failed\n", i);
3215 for (i--; i >= 0; i--)
3216 igb_free_tx_resources(adapter->tx_ring[i]);
3217 break;
3218 }
3219 }
3220
3221 return err;
3222 }
3223
3224 /**
3225 * igb_setup_tctl - configure the transmit control registers
3226 * @adapter: Board private structure
3227 **/
3228 void igb_setup_tctl(struct igb_adapter *adapter)
3229 {
3230 struct e1000_hw *hw = &adapter->hw;
3231 u32 tctl;
3232
3233 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3234 wr32(E1000_TXDCTL(0), 0);
3235
3236 /* Program the Transmit Control Register */
3237 tctl = rd32(E1000_TCTL);
3238 tctl &= ~E1000_TCTL_CT;
3239 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3240 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3241
3242 igb_config_collision_dist(hw);
3243
3244 /* Enable transmits */
3245 tctl |= E1000_TCTL_EN;
3246
3247 wr32(E1000_TCTL, tctl);
3248 }
3249
3250 /**
3251 * igb_configure_tx_ring - Configure transmit ring after Reset
3252 * @adapter: board private structure
3253 * @ring: tx ring to configure
3254 *
3255 * Configure a transmit ring after a reset.
3256 **/
3257 void igb_configure_tx_ring(struct igb_adapter *adapter,
3258 struct igb_ring *ring)
3259 {
3260 struct e1000_hw *hw = &adapter->hw;
3261 u32 txdctl = 0;
3262 u64 tdba = ring->dma;
3263 int reg_idx = ring->reg_idx;
3264
3265 /* disable the queue */
3266 wr32(E1000_TXDCTL(reg_idx), 0);
3267 wrfl();
3268 mdelay(10);
3269
3270 wr32(E1000_TDLEN(reg_idx),
3271 ring->count * sizeof(union e1000_adv_tx_desc));
3272 wr32(E1000_TDBAL(reg_idx),
3273 tdba & 0x00000000ffffffffULL);
3274 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3275
3276 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3277 wr32(E1000_TDH(reg_idx), 0);
3278 writel(0, ring->tail);
3279
3280 txdctl |= IGB_TX_PTHRESH;
3281 txdctl |= IGB_TX_HTHRESH << 8;
3282 txdctl |= IGB_TX_WTHRESH << 16;
3283
3284 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3285 wr32(E1000_TXDCTL(reg_idx), txdctl);
3286 }
3287
3288 /**
3289 * igb_configure_tx - Configure transmit Unit after Reset
3290 * @adapter: board private structure
3291 *
3292 * Configure the Tx unit of the MAC after a reset.
3293 **/
3294 static void igb_configure_tx(struct igb_adapter *adapter)
3295 {
3296 int i;
3297
3298 for (i = 0; i < adapter->num_tx_queues; i++)
3299 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3300 }
3301
3302 /**
3303 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3304 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3305 *
3306 * Returns 0 on success, negative on failure
3307 **/
3308 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3309 {
3310 struct device *dev = rx_ring->dev;
3311 int size;
3312
3313 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3314
3315 rx_ring->rx_buffer_info = vzalloc(size);
3316 if (!rx_ring->rx_buffer_info)
3317 goto err;
3318
3319 /* Round up to nearest 4K */
3320 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3321 rx_ring->size = ALIGN(rx_ring->size, 4096);
3322
3323 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3324 &rx_ring->dma, GFP_KERNEL);
3325 if (!rx_ring->desc)
3326 goto err;
3327
3328 rx_ring->next_to_alloc = 0;
3329 rx_ring->next_to_clean = 0;
3330 rx_ring->next_to_use = 0;
3331
3332 return 0;
3333
3334 err:
3335 vfree(rx_ring->rx_buffer_info);
3336 rx_ring->rx_buffer_info = NULL;
3337 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3338 return -ENOMEM;
3339 }
3340
3341 /**
3342 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3343 * (Descriptors) for all queues
3344 * @adapter: board private structure
3345 *
3346 * Return 0 on success, negative on failure
3347 **/
3348 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3349 {
3350 struct pci_dev *pdev = adapter->pdev;
3351 int i, err = 0;
3352
3353 for (i = 0; i < adapter->num_rx_queues; i++) {
3354 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3355 if (err) {
3356 dev_err(&pdev->dev,
3357 "Allocation for Rx Queue %u failed\n", i);
3358 for (i--; i >= 0; i--)
3359 igb_free_rx_resources(adapter->rx_ring[i]);
3360 break;
3361 }
3362 }
3363
3364 return err;
3365 }
3366
3367 /**
3368 * igb_setup_mrqc - configure the multiple receive queue control registers
3369 * @adapter: Board private structure
3370 **/
3371 static void igb_setup_mrqc(struct igb_adapter *adapter)
3372 {
3373 struct e1000_hw *hw = &adapter->hw;
3374 u32 mrqc, rxcsum;
3375 u32 j, num_rx_queues;
3376 u32 rss_key[10];
3377
3378 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3379 for (j = 0; j < 10; j++)
3380 wr32(E1000_RSSRK(j), rss_key[j]);
3381
3382 num_rx_queues = adapter->rss_queues;
3383
3384 switch (hw->mac.type) {
3385 case e1000_82576:
3386 /* 82576 supports 2 RSS queues for SR-IOV */
3387 if (adapter->vfs_allocated_count)
3388 num_rx_queues = 2;
3389 break;
3390 default:
3391 break;
3392 }
3393
3394 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3395 for (j = 0; j < IGB_RETA_SIZE; j++)
3396 adapter->rss_indir_tbl[j] =
3397 (j * num_rx_queues) / IGB_RETA_SIZE;
3398 adapter->rss_indir_tbl_init = num_rx_queues;
3399 }
3400 igb_write_rss_indir_tbl(adapter);
3401
3402 /* Disable raw packet checksumming so that RSS hash is placed in
3403 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3404 * offloads as they are enabled by default
3405 */
3406 rxcsum = rd32(E1000_RXCSUM);
3407 rxcsum |= E1000_RXCSUM_PCSD;
3408
3409 if (adapter->hw.mac.type >= e1000_82576)
3410 /* Enable Receive Checksum Offload for SCTP */
3411 rxcsum |= E1000_RXCSUM_CRCOFL;
3412
3413 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3414 wr32(E1000_RXCSUM, rxcsum);
3415
3416 /* Generate RSS hash based on packet types, TCP/UDP
3417 * port numbers and/or IPv4/v6 src and dst addresses
3418 */
3419 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3420 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3421 E1000_MRQC_RSS_FIELD_IPV6 |
3422 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3424
3425 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3426 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3427 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3428 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3429
3430 /* If VMDq is enabled then we set the appropriate mode for that, else
3431 * we default to RSS so that an RSS hash is calculated per packet even
3432 * if we are only using one queue
3433 */
3434 if (adapter->vfs_allocated_count) {
3435 if (hw->mac.type > e1000_82575) {
3436 /* Set the default pool for the PF's first queue */
3437 u32 vtctl = rd32(E1000_VT_CTL);
3438
3439 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3440 E1000_VT_CTL_DISABLE_DEF_POOL);
3441 vtctl |= adapter->vfs_allocated_count <<
3442 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3443 wr32(E1000_VT_CTL, vtctl);
3444 }
3445 if (adapter->rss_queues > 1)
3446 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3447 else
3448 mrqc |= E1000_MRQC_ENABLE_VMDQ;
3449 } else {
3450 if (hw->mac.type != e1000_i211)
3451 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3452 }
3453 igb_vmm_control(adapter);
3454
3455 wr32(E1000_MRQC, mrqc);
3456 }
3457
3458 /**
3459 * igb_setup_rctl - configure the receive control registers
3460 * @adapter: Board private structure
3461 **/
3462 void igb_setup_rctl(struct igb_adapter *adapter)
3463 {
3464 struct e1000_hw *hw = &adapter->hw;
3465 u32 rctl;
3466
3467 rctl = rd32(E1000_RCTL);
3468
3469 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3470 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3471
3472 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3473 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3474
3475 /* enable stripping of CRC. It's unlikely this will break BMC
3476 * redirection as it did with e1000. Newer features require
3477 * that the HW strips the CRC.
3478 */
3479 rctl |= E1000_RCTL_SECRC;
3480
3481 /* disable store bad packets and clear size bits. */
3482 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3483
3484 /* enable LPE to prevent packets larger than max_frame_size */
3485 rctl |= E1000_RCTL_LPE;
3486
3487 /* disable queue 0 to prevent tail write w/o re-config */
3488 wr32(E1000_RXDCTL(0), 0);
3489
3490 /* Attention!!! For SR-IOV PF driver operations you must enable
3491 * queue drop for all VF and PF queues to prevent head of line blocking
3492 * if an un-trusted VF does not provide descriptors to hardware.
3493 */
3494 if (adapter->vfs_allocated_count) {
3495 /* set all queue drop enable bits */
3496 wr32(E1000_QDE, ALL_QUEUES);
3497 }
3498
3499 /* This is useful for sniffing bad packets. */
3500 if (adapter->netdev->features & NETIF_F_RXALL) {
3501 /* UPE and MPE will be handled by normal PROMISC logic
3502 * in e1000e_set_rx_mode
3503 */
3504 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3505 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3506 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3507
3508 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3509 E1000_RCTL_DPF | /* Allow filtered pause */
3510 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3511 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3512 * and that breaks VLANs.
3513 */
3514 }
3515
3516 wr32(E1000_RCTL, rctl);
3517 }
3518
3519 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3520 int vfn)
3521 {
3522 struct e1000_hw *hw = &adapter->hw;
3523 u32 vmolr;
3524
3525 /* if it isn't the PF check to see if VFs are enabled and
3526 * increase the size to support vlan tags
3527 */
3528 if (vfn < adapter->vfs_allocated_count &&
3529 adapter->vf_data[vfn].vlans_enabled)
3530 size += VLAN_TAG_SIZE;
3531
3532 vmolr = rd32(E1000_VMOLR(vfn));
3533 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3534 vmolr |= size | E1000_VMOLR_LPE;
3535 wr32(E1000_VMOLR(vfn), vmolr);
3536
3537 return 0;
3538 }
3539
3540 /**
3541 * igb_rlpml_set - set maximum receive packet size
3542 * @adapter: board private structure
3543 *
3544 * Configure maximum receivable packet size.
3545 **/
3546 static void igb_rlpml_set(struct igb_adapter *adapter)
3547 {
3548 u32 max_frame_size = adapter->max_frame_size;
3549 struct e1000_hw *hw = &adapter->hw;
3550 u16 pf_id = adapter->vfs_allocated_count;
3551
3552 if (pf_id) {
3553 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3554 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3555 * to our max jumbo frame size, in case we need to enable
3556 * jumbo frames on one of the rings later.
3557 * This will not pass over-length frames into the default
3558 * queue because it's gated by the VMOLR.RLPML.
3559 */
3560 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3561 }
3562
3563 wr32(E1000_RLPML, max_frame_size);
3564 }
3565
3566 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3567 int vfn, bool aupe)
3568 {
3569 struct e1000_hw *hw = &adapter->hw;
3570 u32 vmolr;
3571
3572 /* This register exists only on 82576 and newer so if we are older then
3573 * we should exit and do nothing
3574 */
3575 if (hw->mac.type < e1000_82576)
3576 return;
3577
3578 vmolr = rd32(E1000_VMOLR(vfn));
3579 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3580 if (hw->mac.type == e1000_i350) {
3581 u32 dvmolr;
3582
3583 dvmolr = rd32(E1000_DVMOLR(vfn));
3584 dvmolr |= E1000_DVMOLR_STRVLAN;
3585 wr32(E1000_DVMOLR(vfn), dvmolr);
3586 }
3587 if (aupe)
3588 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3589 else
3590 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3591
3592 /* clear all bits that might not be set */
3593 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3594
3595 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3596 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3597 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3598 * multicast packets
3599 */
3600 if (vfn <= adapter->vfs_allocated_count)
3601 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3602
3603 wr32(E1000_VMOLR(vfn), vmolr);
3604 }
3605
3606 /**
3607 * igb_configure_rx_ring - Configure a receive ring after Reset
3608 * @adapter: board private structure
3609 * @ring: receive ring to be configured
3610 *
3611 * Configure the Rx unit of the MAC after a reset.
3612 **/
3613 void igb_configure_rx_ring(struct igb_adapter *adapter,
3614 struct igb_ring *ring)
3615 {
3616 struct e1000_hw *hw = &adapter->hw;
3617 u64 rdba = ring->dma;
3618 int reg_idx = ring->reg_idx;
3619 u32 srrctl = 0, rxdctl = 0;
3620
3621 /* disable the queue */
3622 wr32(E1000_RXDCTL(reg_idx), 0);
3623
3624 /* Set DMA base address registers */
3625 wr32(E1000_RDBAL(reg_idx),
3626 rdba & 0x00000000ffffffffULL);
3627 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3628 wr32(E1000_RDLEN(reg_idx),
3629 ring->count * sizeof(union e1000_adv_rx_desc));
3630
3631 /* initialize head and tail */
3632 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3633 wr32(E1000_RDH(reg_idx), 0);
3634 writel(0, ring->tail);
3635
3636 /* set descriptor configuration */
3637 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3638 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3639 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3640 if (hw->mac.type >= e1000_82580)
3641 srrctl |= E1000_SRRCTL_TIMESTAMP;
3642 /* Only set Drop Enable if we are supporting multiple queues */
3643 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3644 srrctl |= E1000_SRRCTL_DROP_EN;
3645
3646 wr32(E1000_SRRCTL(reg_idx), srrctl);
3647
3648 /* set filtering for VMDQ pools */
3649 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3650
3651 rxdctl |= IGB_RX_PTHRESH;
3652 rxdctl |= IGB_RX_HTHRESH << 8;
3653 rxdctl |= IGB_RX_WTHRESH << 16;
3654
3655 /* enable receive descriptor fetching */
3656 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3657 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3658 }
3659
3660 /**
3661 * igb_configure_rx - Configure receive Unit after Reset
3662 * @adapter: board private structure
3663 *
3664 * Configure the Rx unit of the MAC after a reset.
3665 **/
3666 static void igb_configure_rx(struct igb_adapter *adapter)
3667 {
3668 int i;
3669
3670 /* set UTA to appropriate mode */
3671 igb_set_uta(adapter);
3672
3673 /* set the correct pool for the PF default MAC address in entry 0 */
3674 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3675 adapter->vfs_allocated_count);
3676
3677 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3678 * the Base and Length of the Rx Descriptor Ring
3679 */
3680 for (i = 0; i < adapter->num_rx_queues; i++)
3681 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3682 }
3683
3684 /**
3685 * igb_free_tx_resources - Free Tx Resources per Queue
3686 * @tx_ring: Tx descriptor ring for a specific queue
3687 *
3688 * Free all transmit software resources
3689 **/
3690 void igb_free_tx_resources(struct igb_ring *tx_ring)
3691 {
3692 igb_clean_tx_ring(tx_ring);
3693
3694 vfree(tx_ring->tx_buffer_info);
3695 tx_ring->tx_buffer_info = NULL;
3696
3697 /* if not set, then don't free */
3698 if (!tx_ring->desc)
3699 return;
3700
3701 dma_free_coherent(tx_ring->dev, tx_ring->size,
3702 tx_ring->desc, tx_ring->dma);
3703
3704 tx_ring->desc = NULL;
3705 }
3706
3707 /**
3708 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3709 * @adapter: board private structure
3710 *
3711 * Free all transmit software resources
3712 **/
3713 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3714 {
3715 int i;
3716
3717 for (i = 0; i < adapter->num_tx_queues; i++)
3718 if (adapter->tx_ring[i])
3719 igb_free_tx_resources(adapter->tx_ring[i]);
3720 }
3721
3722 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3723 struct igb_tx_buffer *tx_buffer)
3724 {
3725 if (tx_buffer->skb) {
3726 dev_kfree_skb_any(tx_buffer->skb);
3727 if (dma_unmap_len(tx_buffer, len))
3728 dma_unmap_single(ring->dev,
3729 dma_unmap_addr(tx_buffer, dma),
3730 dma_unmap_len(tx_buffer, len),
3731 DMA_TO_DEVICE);
3732 } else if (dma_unmap_len(tx_buffer, len)) {
3733 dma_unmap_page(ring->dev,
3734 dma_unmap_addr(tx_buffer, dma),
3735 dma_unmap_len(tx_buffer, len),
3736 DMA_TO_DEVICE);
3737 }
3738 tx_buffer->next_to_watch = NULL;
3739 tx_buffer->skb = NULL;
3740 dma_unmap_len_set(tx_buffer, len, 0);
3741 /* buffer_info must be completely set up in the transmit path */
3742 }
3743
3744 /**
3745 * igb_clean_tx_ring - Free Tx Buffers
3746 * @tx_ring: ring to be cleaned
3747 **/
3748 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3749 {
3750 struct igb_tx_buffer *buffer_info;
3751 unsigned long size;
3752 u16 i;
3753
3754 if (!tx_ring->tx_buffer_info)
3755 return;
3756 /* Free all the Tx ring sk_buffs */
3757
3758 for (i = 0; i < tx_ring->count; i++) {
3759 buffer_info = &tx_ring->tx_buffer_info[i];
3760 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3761 }
3762
3763 netdev_tx_reset_queue(txring_txq(tx_ring));
3764
3765 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3766 memset(tx_ring->tx_buffer_info, 0, size);
3767
3768 /* Zero out the descriptor ring */
3769 memset(tx_ring->desc, 0, tx_ring->size);
3770
3771 tx_ring->next_to_use = 0;
3772 tx_ring->next_to_clean = 0;
3773 }
3774
3775 /**
3776 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3777 * @adapter: board private structure
3778 **/
3779 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3780 {
3781 int i;
3782
3783 for (i = 0; i < adapter->num_tx_queues; i++)
3784 if (adapter->tx_ring[i])
3785 igb_clean_tx_ring(adapter->tx_ring[i]);
3786 }
3787
3788 /**
3789 * igb_free_rx_resources - Free Rx Resources
3790 * @rx_ring: ring to clean the resources from
3791 *
3792 * Free all receive software resources
3793 **/
3794 void igb_free_rx_resources(struct igb_ring *rx_ring)
3795 {
3796 igb_clean_rx_ring(rx_ring);
3797
3798 vfree(rx_ring->rx_buffer_info);
3799 rx_ring->rx_buffer_info = NULL;
3800
3801 /* if not set, then don't free */
3802 if (!rx_ring->desc)
3803 return;
3804
3805 dma_free_coherent(rx_ring->dev, rx_ring->size,
3806 rx_ring->desc, rx_ring->dma);
3807
3808 rx_ring->desc = NULL;
3809 }
3810
3811 /**
3812 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3813 * @adapter: board private structure
3814 *
3815 * Free all receive software resources
3816 **/
3817 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3818 {
3819 int i;
3820
3821 for (i = 0; i < adapter->num_rx_queues; i++)
3822 if (adapter->rx_ring[i])
3823 igb_free_rx_resources(adapter->rx_ring[i]);
3824 }
3825
3826 /**
3827 * igb_clean_rx_ring - Free Rx Buffers per Queue
3828 * @rx_ring: ring to free buffers from
3829 **/
3830 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3831 {
3832 unsigned long size;
3833 u16 i;
3834
3835 if (rx_ring->skb)
3836 dev_kfree_skb(rx_ring->skb);
3837 rx_ring->skb = NULL;
3838
3839 if (!rx_ring->rx_buffer_info)
3840 return;
3841
3842 /* Free all the Rx ring sk_buffs */
3843 for (i = 0; i < rx_ring->count; i++) {
3844 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3845
3846 if (!buffer_info->page)
3847 continue;
3848
3849 dma_unmap_page(rx_ring->dev,
3850 buffer_info->dma,
3851 PAGE_SIZE,
3852 DMA_FROM_DEVICE);
3853 __free_page(buffer_info->page);
3854
3855 buffer_info->page = NULL;
3856 }
3857
3858 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3859 memset(rx_ring->rx_buffer_info, 0, size);
3860
3861 /* Zero out the descriptor ring */
3862 memset(rx_ring->desc, 0, rx_ring->size);
3863
3864 rx_ring->next_to_alloc = 0;
3865 rx_ring->next_to_clean = 0;
3866 rx_ring->next_to_use = 0;
3867 }
3868
3869 /**
3870 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3871 * @adapter: board private structure
3872 **/
3873 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3874 {
3875 int i;
3876
3877 for (i = 0; i < adapter->num_rx_queues; i++)
3878 if (adapter->rx_ring[i])
3879 igb_clean_rx_ring(adapter->rx_ring[i]);
3880 }
3881
3882 /**
3883 * igb_set_mac - Change the Ethernet Address of the NIC
3884 * @netdev: network interface device structure
3885 * @p: pointer to an address structure
3886 *
3887 * Returns 0 on success, negative on failure
3888 **/
3889 static int igb_set_mac(struct net_device *netdev, void *p)
3890 {
3891 struct igb_adapter *adapter = netdev_priv(netdev);
3892 struct e1000_hw *hw = &adapter->hw;
3893 struct sockaddr *addr = p;
3894
3895 if (!is_valid_ether_addr(addr->sa_data))
3896 return -EADDRNOTAVAIL;
3897
3898 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3899 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3900
3901 /* set the correct pool for the new PF MAC address in entry 0 */
3902 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3903 adapter->vfs_allocated_count);
3904
3905 return 0;
3906 }
3907
3908 /**
3909 * igb_write_mc_addr_list - write multicast addresses to MTA
3910 * @netdev: network interface device structure
3911 *
3912 * Writes multicast address list to the MTA hash table.
3913 * Returns: -ENOMEM on failure
3914 * 0 on no addresses written
3915 * X on writing X addresses to MTA
3916 **/
3917 static int igb_write_mc_addr_list(struct net_device *netdev)
3918 {
3919 struct igb_adapter *adapter = netdev_priv(netdev);
3920 struct e1000_hw *hw = &adapter->hw;
3921 struct netdev_hw_addr *ha;
3922 u8 *mta_list;
3923 int i;
3924
3925 if (netdev_mc_empty(netdev)) {
3926 /* nothing to program, so clear mc list */
3927 igb_update_mc_addr_list(hw, NULL, 0);
3928 igb_restore_vf_multicasts(adapter);
3929 return 0;
3930 }
3931
3932 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3933 if (!mta_list)
3934 return -ENOMEM;
3935
3936 /* The shared function expects a packed array of only addresses. */
3937 i = 0;
3938 netdev_for_each_mc_addr(ha, netdev)
3939 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3940
3941 igb_update_mc_addr_list(hw, mta_list, i);
3942 kfree(mta_list);
3943
3944 return netdev_mc_count(netdev);
3945 }
3946
3947 /**
3948 * igb_write_uc_addr_list - write unicast addresses to RAR table
3949 * @netdev: network interface device structure
3950 *
3951 * Writes unicast address list to the RAR table.
3952 * Returns: -ENOMEM on failure/insufficient address space
3953 * 0 on no addresses written
3954 * X on writing X addresses to the RAR table
3955 **/
3956 static int igb_write_uc_addr_list(struct net_device *netdev)
3957 {
3958 struct igb_adapter *adapter = netdev_priv(netdev);
3959 struct e1000_hw *hw = &adapter->hw;
3960 unsigned int vfn = adapter->vfs_allocated_count;
3961 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3962 int count = 0;
3963
3964 /* return ENOMEM indicating insufficient memory for addresses */
3965 if (netdev_uc_count(netdev) > rar_entries)
3966 return -ENOMEM;
3967
3968 if (!netdev_uc_empty(netdev) && rar_entries) {
3969 struct netdev_hw_addr *ha;
3970
3971 netdev_for_each_uc_addr(ha, netdev) {
3972 if (!rar_entries)
3973 break;
3974 igb_rar_set_qsel(adapter, ha->addr,
3975 rar_entries--,
3976 vfn);
3977 count++;
3978 }
3979 }
3980 /* write the addresses in reverse order to avoid write combining */
3981 for (; rar_entries > 0 ; rar_entries--) {
3982 wr32(E1000_RAH(rar_entries), 0);
3983 wr32(E1000_RAL(rar_entries), 0);
3984 }
3985 wrfl();
3986
3987 return count;
3988 }
3989
3990 /**
3991 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3992 * @netdev: network interface device structure
3993 *
3994 * The set_rx_mode entry point is called whenever the unicast or multicast
3995 * address lists or the network interface flags are updated. This routine is
3996 * responsible for configuring the hardware for proper unicast, multicast,
3997 * promiscuous mode, and all-multi behavior.
3998 **/
3999 static void igb_set_rx_mode(struct net_device *netdev)
4000 {
4001 struct igb_adapter *adapter = netdev_priv(netdev);
4002 struct e1000_hw *hw = &adapter->hw;
4003 unsigned int vfn = adapter->vfs_allocated_count;
4004 u32 rctl, vmolr = 0;
4005 int count;
4006
4007 /* Check for Promiscuous and All Multicast modes */
4008 rctl = rd32(E1000_RCTL);
4009
4010 /* clear the effected bits */
4011 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4012
4013 if (netdev->flags & IFF_PROMISC) {
4014 /* retain VLAN HW filtering if in VT mode */
4015 if (adapter->vfs_allocated_count)
4016 rctl |= E1000_RCTL_VFE;
4017 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4018 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4019 } else {
4020 if (netdev->flags & IFF_ALLMULTI) {
4021 rctl |= E1000_RCTL_MPE;
4022 vmolr |= E1000_VMOLR_MPME;
4023 } else {
4024 /* Write addresses to the MTA, if the attempt fails
4025 * then we should just turn on promiscuous mode so
4026 * that we can at least receive multicast traffic
4027 */
4028 count = igb_write_mc_addr_list(netdev);
4029 if (count < 0) {
4030 rctl |= E1000_RCTL_MPE;
4031 vmolr |= E1000_VMOLR_MPME;
4032 } else if (count) {
4033 vmolr |= E1000_VMOLR_ROMPE;
4034 }
4035 }
4036 /* Write addresses to available RAR registers, if there is not
4037 * sufficient space to store all the addresses then enable
4038 * unicast promiscuous mode
4039 */
4040 count = igb_write_uc_addr_list(netdev);
4041 if (count < 0) {
4042 rctl |= E1000_RCTL_UPE;
4043 vmolr |= E1000_VMOLR_ROPE;
4044 }
4045 rctl |= E1000_RCTL_VFE;
4046 }
4047 wr32(E1000_RCTL, rctl);
4048
4049 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4050 * the VMOLR to enable the appropriate modes. Without this workaround
4051 * we will have issues with VLAN tag stripping not being done for frames
4052 * that are only arriving because we are the default pool
4053 */
4054 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4055 return;
4056
4057 vmolr |= rd32(E1000_VMOLR(vfn)) &
4058 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4059 wr32(E1000_VMOLR(vfn), vmolr);
4060 igb_restore_vf_multicasts(adapter);
4061 }
4062
4063 static void igb_check_wvbr(struct igb_adapter *adapter)
4064 {
4065 struct e1000_hw *hw = &adapter->hw;
4066 u32 wvbr = 0;
4067
4068 switch (hw->mac.type) {
4069 case e1000_82576:
4070 case e1000_i350:
4071 wvbr = rd32(E1000_WVBR);
4072 if (!wvbr)
4073 return;
4074 break;
4075 default:
4076 break;
4077 }
4078
4079 adapter->wvbr |= wvbr;
4080 }
4081
4082 #define IGB_STAGGERED_QUEUE_OFFSET 8
4083
4084 static void igb_spoof_check(struct igb_adapter *adapter)
4085 {
4086 int j;
4087
4088 if (!adapter->wvbr)
4089 return;
4090
4091 for (j = 0; j < adapter->vfs_allocated_count; j++) {
4092 if (adapter->wvbr & (1 << j) ||
4093 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4094 dev_warn(&adapter->pdev->dev,
4095 "Spoof event(s) detected on VF %d\n", j);
4096 adapter->wvbr &=
4097 ~((1 << j) |
4098 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4099 }
4100 }
4101 }
4102
4103 /* Need to wait a few seconds after link up to get diagnostic information from
4104 * the phy
4105 */
4106 static void igb_update_phy_info(unsigned long data)
4107 {
4108 struct igb_adapter *adapter = (struct igb_adapter *) data;
4109 igb_get_phy_info(&adapter->hw);
4110 }
4111
4112 /**
4113 * igb_has_link - check shared code for link and determine up/down
4114 * @adapter: pointer to driver private info
4115 **/
4116 bool igb_has_link(struct igb_adapter *adapter)
4117 {
4118 struct e1000_hw *hw = &adapter->hw;
4119 bool link_active = false;
4120
4121 /* get_link_status is set on LSC (link status) interrupt or
4122 * rx sequence error interrupt. get_link_status will stay
4123 * false until the e1000_check_for_link establishes link
4124 * for copper adapters ONLY
4125 */
4126 switch (hw->phy.media_type) {
4127 case e1000_media_type_copper:
4128 if (!hw->mac.get_link_status)
4129 return true;
4130 case e1000_media_type_internal_serdes:
4131 hw->mac.ops.check_for_link(hw);
4132 link_active = !hw->mac.get_link_status;
4133 break;
4134 default:
4135 case e1000_media_type_unknown:
4136 break;
4137 }
4138
4139 if (((hw->mac.type == e1000_i210) ||
4140 (hw->mac.type == e1000_i211)) &&
4141 (hw->phy.id == I210_I_PHY_ID)) {
4142 if (!netif_carrier_ok(adapter->netdev)) {
4143 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4144 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4145 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4146 adapter->link_check_timeout = jiffies;
4147 }
4148 }
4149
4150 return link_active;
4151 }
4152
4153 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4154 {
4155 bool ret = false;
4156 u32 ctrl_ext, thstat;
4157
4158 /* check for thermal sensor event on i350 copper only */
4159 if (hw->mac.type == e1000_i350) {
4160 thstat = rd32(E1000_THSTAT);
4161 ctrl_ext = rd32(E1000_CTRL_EXT);
4162
4163 if ((hw->phy.media_type == e1000_media_type_copper) &&
4164 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4165 ret = !!(thstat & event);
4166 }
4167
4168 return ret;
4169 }
4170
4171 /**
4172 * igb_check_lvmmc - check for malformed packets received
4173 * and indicated in LVMMC register
4174 * @adapter: pointer to adapter
4175 **/
4176 static void igb_check_lvmmc(struct igb_adapter *adapter)
4177 {
4178 struct e1000_hw *hw = &adapter->hw;
4179 u32 lvmmc;
4180
4181 lvmmc = rd32(E1000_LVMMC);
4182 if (lvmmc) {
4183 if (unlikely(net_ratelimit())) {
4184 netdev_warn(adapter->netdev,
4185 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4186 lvmmc);
4187 }
4188 }
4189 }
4190
4191 /**
4192 * igb_watchdog - Timer Call-back
4193 * @data: pointer to adapter cast into an unsigned long
4194 **/
4195 static void igb_watchdog(unsigned long data)
4196 {
4197 struct igb_adapter *adapter = (struct igb_adapter *)data;
4198 /* Do the rest outside of interrupt context */
4199 schedule_work(&adapter->watchdog_task);
4200 }
4201
4202 static void igb_watchdog_task(struct work_struct *work)
4203 {
4204 struct igb_adapter *adapter = container_of(work,
4205 struct igb_adapter,
4206 watchdog_task);
4207 struct e1000_hw *hw = &adapter->hw;
4208 struct e1000_phy_info *phy = &hw->phy;
4209 struct net_device *netdev = adapter->netdev;
4210 u32 link;
4211 int i;
4212 u32 connsw;
4213
4214 link = igb_has_link(adapter);
4215
4216 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4217 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4218 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4219 else
4220 link = false;
4221 }
4222
4223 /* Force link down if we have fiber to swap to */
4224 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4225 if (hw->phy.media_type == e1000_media_type_copper) {
4226 connsw = rd32(E1000_CONNSW);
4227 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4228 link = 0;
4229 }
4230 }
4231 if (link) {
4232 /* Perform a reset if the media type changed. */
4233 if (hw->dev_spec._82575.media_changed) {
4234 hw->dev_spec._82575.media_changed = false;
4235 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4236 igb_reset(adapter);
4237 }
4238 /* Cancel scheduled suspend requests. */
4239 pm_runtime_resume(netdev->dev.parent);
4240
4241 if (!netif_carrier_ok(netdev)) {
4242 u32 ctrl;
4243
4244 hw->mac.ops.get_speed_and_duplex(hw,
4245 &adapter->link_speed,
4246 &adapter->link_duplex);
4247
4248 ctrl = rd32(E1000_CTRL);
4249 /* Links status message must follow this format */
4250 netdev_info(netdev,
4251 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4252 netdev->name,
4253 adapter->link_speed,
4254 adapter->link_duplex == FULL_DUPLEX ?
4255 "Full" : "Half",
4256 (ctrl & E1000_CTRL_TFCE) &&
4257 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4258 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4259 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
4260
4261 /* disable EEE if enabled */
4262 if ((adapter->flags & IGB_FLAG_EEE) &&
4263 (adapter->link_duplex == HALF_DUPLEX)) {
4264 dev_info(&adapter->pdev->dev,
4265 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4266 adapter->hw.dev_spec._82575.eee_disable = true;
4267 adapter->flags &= ~IGB_FLAG_EEE;
4268 }
4269
4270 /* check if SmartSpeed worked */
4271 igb_check_downshift(hw);
4272 if (phy->speed_downgraded)
4273 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4274
4275 /* check for thermal sensor event */
4276 if (igb_thermal_sensor_event(hw,
4277 E1000_THSTAT_LINK_THROTTLE))
4278 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4279
4280 /* adjust timeout factor according to speed/duplex */
4281 adapter->tx_timeout_factor = 1;
4282 switch (adapter->link_speed) {
4283 case SPEED_10:
4284 adapter->tx_timeout_factor = 14;
4285 break;
4286 case SPEED_100:
4287 /* maybe add some timeout factor ? */
4288 break;
4289 }
4290
4291 netif_carrier_on(netdev);
4292
4293 igb_ping_all_vfs(adapter);
4294 igb_check_vf_rate_limit(adapter);
4295
4296 /* link state has changed, schedule phy info update */
4297 if (!test_bit(__IGB_DOWN, &adapter->state))
4298 mod_timer(&adapter->phy_info_timer,
4299 round_jiffies(jiffies + 2 * HZ));
4300 }
4301 } else {
4302 if (netif_carrier_ok(netdev)) {
4303 adapter->link_speed = 0;
4304 adapter->link_duplex = 0;
4305
4306 /* check for thermal sensor event */
4307 if (igb_thermal_sensor_event(hw,
4308 E1000_THSTAT_PWR_DOWN)) {
4309 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
4310 }
4311
4312 /* Links status message must follow this format */
4313 netdev_info(netdev, "igb: %s NIC Link is Down\n",
4314 netdev->name);
4315 netif_carrier_off(netdev);
4316
4317 igb_ping_all_vfs(adapter);
4318
4319 /* link state has changed, schedule phy info update */
4320 if (!test_bit(__IGB_DOWN, &adapter->state))
4321 mod_timer(&adapter->phy_info_timer,
4322 round_jiffies(jiffies + 2 * HZ));
4323
4324 /* link is down, time to check for alternate media */
4325 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4326 igb_check_swap_media(adapter);
4327 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4328 schedule_work(&adapter->reset_task);
4329 /* return immediately */
4330 return;
4331 }
4332 }
4333 pm_schedule_suspend(netdev->dev.parent,
4334 MSEC_PER_SEC * 5);
4335
4336 /* also check for alternate media here */
4337 } else if (!netif_carrier_ok(netdev) &&
4338 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4339 igb_check_swap_media(adapter);
4340 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4341 schedule_work(&adapter->reset_task);
4342 /* return immediately */
4343 return;
4344 }
4345 }
4346 }
4347
4348 spin_lock(&adapter->stats64_lock);
4349 igb_update_stats(adapter, &adapter->stats64);
4350 spin_unlock(&adapter->stats64_lock);
4351
4352 for (i = 0; i < adapter->num_tx_queues; i++) {
4353 struct igb_ring *tx_ring = adapter->tx_ring[i];
4354 if (!netif_carrier_ok(netdev)) {
4355 /* We've lost link, so the controller stops DMA,
4356 * but we've got queued Tx work that's never going
4357 * to get done, so reset controller to flush Tx.
4358 * (Do the reset outside of interrupt context).
4359 */
4360 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4361 adapter->tx_timeout_count++;
4362 schedule_work(&adapter->reset_task);
4363 /* return immediately since reset is imminent */
4364 return;
4365 }
4366 }
4367
4368 /* Force detection of hung controller every watchdog period */
4369 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4370 }
4371
4372 /* Cause software interrupt to ensure Rx ring is cleaned */
4373 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4374 u32 eics = 0;
4375
4376 for (i = 0; i < adapter->num_q_vectors; i++)
4377 eics |= adapter->q_vector[i]->eims_value;
4378 wr32(E1000_EICS, eics);
4379 } else {
4380 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4381 }
4382
4383 igb_spoof_check(adapter);
4384 igb_ptp_rx_hang(adapter);
4385
4386 /* Check LVMMC register on i350/i354 only */
4387 if ((adapter->hw.mac.type == e1000_i350) ||
4388 (adapter->hw.mac.type == e1000_i354))
4389 igb_check_lvmmc(adapter);
4390
4391 /* Reset the timer */
4392 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4393 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4394 mod_timer(&adapter->watchdog_timer,
4395 round_jiffies(jiffies + HZ));
4396 else
4397 mod_timer(&adapter->watchdog_timer,
4398 round_jiffies(jiffies + 2 * HZ));
4399 }
4400 }
4401
4402 enum latency_range {
4403 lowest_latency = 0,
4404 low_latency = 1,
4405 bulk_latency = 2,
4406 latency_invalid = 255
4407 };
4408
4409 /**
4410 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4411 * @q_vector: pointer to q_vector
4412 *
4413 * Stores a new ITR value based on strictly on packet size. This
4414 * algorithm is less sophisticated than that used in igb_update_itr,
4415 * due to the difficulty of synchronizing statistics across multiple
4416 * receive rings. The divisors and thresholds used by this function
4417 * were determined based on theoretical maximum wire speed and testing
4418 * data, in order to minimize response time while increasing bulk
4419 * throughput.
4420 * This functionality is controlled by ethtool's coalescing settings.
4421 * NOTE: This function is called only when operating in a multiqueue
4422 * receive environment.
4423 **/
4424 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4425 {
4426 int new_val = q_vector->itr_val;
4427 int avg_wire_size = 0;
4428 struct igb_adapter *adapter = q_vector->adapter;
4429 unsigned int packets;
4430
4431 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4432 * ints/sec - ITR timer value of 120 ticks.
4433 */
4434 if (adapter->link_speed != SPEED_1000) {
4435 new_val = IGB_4K_ITR;
4436 goto set_itr_val;
4437 }
4438
4439 packets = q_vector->rx.total_packets;
4440 if (packets)
4441 avg_wire_size = q_vector->rx.total_bytes / packets;
4442
4443 packets = q_vector->tx.total_packets;
4444 if (packets)
4445 avg_wire_size = max_t(u32, avg_wire_size,
4446 q_vector->tx.total_bytes / packets);
4447
4448 /* if avg_wire_size isn't set no work was done */
4449 if (!avg_wire_size)
4450 goto clear_counts;
4451
4452 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4453 avg_wire_size += 24;
4454
4455 /* Don't starve jumbo frames */
4456 avg_wire_size = min(avg_wire_size, 3000);
4457
4458 /* Give a little boost to mid-size frames */
4459 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4460 new_val = avg_wire_size / 3;
4461 else
4462 new_val = avg_wire_size / 2;
4463
4464 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4465 if (new_val < IGB_20K_ITR &&
4466 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4467 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4468 new_val = IGB_20K_ITR;
4469
4470 set_itr_val:
4471 if (new_val != q_vector->itr_val) {
4472 q_vector->itr_val = new_val;
4473 q_vector->set_itr = 1;
4474 }
4475 clear_counts:
4476 q_vector->rx.total_bytes = 0;
4477 q_vector->rx.total_packets = 0;
4478 q_vector->tx.total_bytes = 0;
4479 q_vector->tx.total_packets = 0;
4480 }
4481
4482 /**
4483 * igb_update_itr - update the dynamic ITR value based on statistics
4484 * @q_vector: pointer to q_vector
4485 * @ring_container: ring info to update the itr for
4486 *
4487 * Stores a new ITR value based on packets and byte
4488 * counts during the last interrupt. The advantage of per interrupt
4489 * computation is faster updates and more accurate ITR for the current
4490 * traffic pattern. Constants in this function were computed
4491 * based on theoretical maximum wire speed and thresholds were set based
4492 * on testing data as well as attempting to minimize response time
4493 * while increasing bulk throughput.
4494 * This functionality is controlled by ethtool's coalescing settings.
4495 * NOTE: These calculations are only valid when operating in a single-
4496 * queue environment.
4497 **/
4498 static void igb_update_itr(struct igb_q_vector *q_vector,
4499 struct igb_ring_container *ring_container)
4500 {
4501 unsigned int packets = ring_container->total_packets;
4502 unsigned int bytes = ring_container->total_bytes;
4503 u8 itrval = ring_container->itr;
4504
4505 /* no packets, exit with status unchanged */
4506 if (packets == 0)
4507 return;
4508
4509 switch (itrval) {
4510 case lowest_latency:
4511 /* handle TSO and jumbo frames */
4512 if (bytes/packets > 8000)
4513 itrval = bulk_latency;
4514 else if ((packets < 5) && (bytes > 512))
4515 itrval = low_latency;
4516 break;
4517 case low_latency: /* 50 usec aka 20000 ints/s */
4518 if (bytes > 10000) {
4519 /* this if handles the TSO accounting */
4520 if (bytes/packets > 8000)
4521 itrval = bulk_latency;
4522 else if ((packets < 10) || ((bytes/packets) > 1200))
4523 itrval = bulk_latency;
4524 else if ((packets > 35))
4525 itrval = lowest_latency;
4526 } else if (bytes/packets > 2000) {
4527 itrval = bulk_latency;
4528 } else if (packets <= 2 && bytes < 512) {
4529 itrval = lowest_latency;
4530 }
4531 break;
4532 case bulk_latency: /* 250 usec aka 4000 ints/s */
4533 if (bytes > 25000) {
4534 if (packets > 35)
4535 itrval = low_latency;
4536 } else if (bytes < 1500) {
4537 itrval = low_latency;
4538 }
4539 break;
4540 }
4541
4542 /* clear work counters since we have the values we need */
4543 ring_container->total_bytes = 0;
4544 ring_container->total_packets = 0;
4545
4546 /* write updated itr to ring container */
4547 ring_container->itr = itrval;
4548 }
4549
4550 static void igb_set_itr(struct igb_q_vector *q_vector)
4551 {
4552 struct igb_adapter *adapter = q_vector->adapter;
4553 u32 new_itr = q_vector->itr_val;
4554 u8 current_itr = 0;
4555
4556 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4557 if (adapter->link_speed != SPEED_1000) {
4558 current_itr = 0;
4559 new_itr = IGB_4K_ITR;
4560 goto set_itr_now;
4561 }
4562
4563 igb_update_itr(q_vector, &q_vector->tx);
4564 igb_update_itr(q_vector, &q_vector->rx);
4565
4566 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4567
4568 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4569 if (current_itr == lowest_latency &&
4570 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4571 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4572 current_itr = low_latency;
4573
4574 switch (current_itr) {
4575 /* counts and packets in update_itr are dependent on these numbers */
4576 case lowest_latency:
4577 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4578 break;
4579 case low_latency:
4580 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4581 break;
4582 case bulk_latency:
4583 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
4584 break;
4585 default:
4586 break;
4587 }
4588
4589 set_itr_now:
4590 if (new_itr != q_vector->itr_val) {
4591 /* this attempts to bias the interrupt rate towards Bulk
4592 * by adding intermediate steps when interrupt rate is
4593 * increasing
4594 */
4595 new_itr = new_itr > q_vector->itr_val ?
4596 max((new_itr * q_vector->itr_val) /
4597 (new_itr + (q_vector->itr_val >> 2)),
4598 new_itr) : new_itr;
4599 /* Don't write the value here; it resets the adapter's
4600 * internal timer, and causes us to delay far longer than
4601 * we should between interrupts. Instead, we write the ITR
4602 * value at the beginning of the next interrupt so the timing
4603 * ends up being correct.
4604 */
4605 q_vector->itr_val = new_itr;
4606 q_vector->set_itr = 1;
4607 }
4608 }
4609
4610 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4611 u32 type_tucmd, u32 mss_l4len_idx)
4612 {
4613 struct e1000_adv_tx_context_desc *context_desc;
4614 u16 i = tx_ring->next_to_use;
4615
4616 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4617
4618 i++;
4619 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4620
4621 /* set bits to identify this as an advanced context descriptor */
4622 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4623
4624 /* For 82575, context index must be unique per ring. */
4625 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4626 mss_l4len_idx |= tx_ring->reg_idx << 4;
4627
4628 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4629 context_desc->seqnum_seed = 0;
4630 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4631 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4632 }
4633
4634 static int igb_tso(struct igb_ring *tx_ring,
4635 struct igb_tx_buffer *first,
4636 u8 *hdr_len)
4637 {
4638 struct sk_buff *skb = first->skb;
4639 u32 vlan_macip_lens, type_tucmd;
4640 u32 mss_l4len_idx, l4len;
4641 int err;
4642
4643 if (skb->ip_summed != CHECKSUM_PARTIAL)
4644 return 0;
4645
4646 if (!skb_is_gso(skb))
4647 return 0;
4648
4649 err = skb_cow_head(skb, 0);
4650 if (err < 0)
4651 return err;
4652
4653 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4654 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4655
4656 if (first->protocol == htons(ETH_P_IP)) {
4657 struct iphdr *iph = ip_hdr(skb);
4658 iph->tot_len = 0;
4659 iph->check = 0;
4660 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4661 iph->daddr, 0,
4662 IPPROTO_TCP,
4663 0);
4664 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4665 first->tx_flags |= IGB_TX_FLAGS_TSO |
4666 IGB_TX_FLAGS_CSUM |
4667 IGB_TX_FLAGS_IPV4;
4668 } else if (skb_is_gso_v6(skb)) {
4669 ipv6_hdr(skb)->payload_len = 0;
4670 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4671 &ipv6_hdr(skb)->daddr,
4672 0, IPPROTO_TCP, 0);
4673 first->tx_flags |= IGB_TX_FLAGS_TSO |
4674 IGB_TX_FLAGS_CSUM;
4675 }
4676
4677 /* compute header lengths */
4678 l4len = tcp_hdrlen(skb);
4679 *hdr_len = skb_transport_offset(skb) + l4len;
4680
4681 /* update gso size and bytecount with header size */
4682 first->gso_segs = skb_shinfo(skb)->gso_segs;
4683 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4684
4685 /* MSS L4LEN IDX */
4686 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4687 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4688
4689 /* VLAN MACLEN IPLEN */
4690 vlan_macip_lens = skb_network_header_len(skb);
4691 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4692 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4693
4694 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4695
4696 return 1;
4697 }
4698
4699 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4700 {
4701 struct sk_buff *skb = first->skb;
4702 u32 vlan_macip_lens = 0;
4703 u32 mss_l4len_idx = 0;
4704 u32 type_tucmd = 0;
4705
4706 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4707 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4708 return;
4709 } else {
4710 u8 l4_hdr = 0;
4711
4712 switch (first->protocol) {
4713 case htons(ETH_P_IP):
4714 vlan_macip_lens |= skb_network_header_len(skb);
4715 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4716 l4_hdr = ip_hdr(skb)->protocol;
4717 break;
4718 case htons(ETH_P_IPV6):
4719 vlan_macip_lens |= skb_network_header_len(skb);
4720 l4_hdr = ipv6_hdr(skb)->nexthdr;
4721 break;
4722 default:
4723 if (unlikely(net_ratelimit())) {
4724 dev_warn(tx_ring->dev,
4725 "partial checksum but proto=%x!\n",
4726 first->protocol);
4727 }
4728 break;
4729 }
4730
4731 switch (l4_hdr) {
4732 case IPPROTO_TCP:
4733 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4734 mss_l4len_idx = tcp_hdrlen(skb) <<
4735 E1000_ADVTXD_L4LEN_SHIFT;
4736 break;
4737 case IPPROTO_SCTP:
4738 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4739 mss_l4len_idx = sizeof(struct sctphdr) <<
4740 E1000_ADVTXD_L4LEN_SHIFT;
4741 break;
4742 case IPPROTO_UDP:
4743 mss_l4len_idx = sizeof(struct udphdr) <<
4744 E1000_ADVTXD_L4LEN_SHIFT;
4745 break;
4746 default:
4747 if (unlikely(net_ratelimit())) {
4748 dev_warn(tx_ring->dev,
4749 "partial checksum but l4 proto=%x!\n",
4750 l4_hdr);
4751 }
4752 break;
4753 }
4754
4755 /* update TX checksum flag */
4756 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4757 }
4758
4759 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4760 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4761
4762 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4763 }
4764
4765 #define IGB_SET_FLAG(_input, _flag, _result) \
4766 ((_flag <= _result) ? \
4767 ((u32)(_input & _flag) * (_result / _flag)) : \
4768 ((u32)(_input & _flag) / (_flag / _result)))
4769
4770 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4771 {
4772 /* set type for advanced descriptor with frame checksum insertion */
4773 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4774 E1000_ADVTXD_DCMD_DEXT |
4775 E1000_ADVTXD_DCMD_IFCS;
4776
4777 /* set HW vlan bit if vlan is present */
4778 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4779 (E1000_ADVTXD_DCMD_VLE));
4780
4781 /* set segmentation bits for TSO */
4782 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4783 (E1000_ADVTXD_DCMD_TSE));
4784
4785 /* set timestamp bit if present */
4786 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4787 (E1000_ADVTXD_MAC_TSTAMP));
4788
4789 /* insert frame checksum */
4790 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4791
4792 return cmd_type;
4793 }
4794
4795 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4796 union e1000_adv_tx_desc *tx_desc,
4797 u32 tx_flags, unsigned int paylen)
4798 {
4799 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4800
4801 /* 82575 requires a unique index per ring */
4802 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4803 olinfo_status |= tx_ring->reg_idx << 4;
4804
4805 /* insert L4 checksum */
4806 olinfo_status |= IGB_SET_FLAG(tx_flags,
4807 IGB_TX_FLAGS_CSUM,
4808 (E1000_TXD_POPTS_TXSM << 8));
4809
4810 /* insert IPv4 checksum */
4811 olinfo_status |= IGB_SET_FLAG(tx_flags,
4812 IGB_TX_FLAGS_IPV4,
4813 (E1000_TXD_POPTS_IXSM << 8));
4814
4815 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4816 }
4817
4818 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4819 {
4820 struct net_device *netdev = tx_ring->netdev;
4821
4822 netif_stop_subqueue(netdev, tx_ring->queue_index);
4823
4824 /* Herbert's original patch had:
4825 * smp_mb__after_netif_stop_queue();
4826 * but since that doesn't exist yet, just open code it.
4827 */
4828 smp_mb();
4829
4830 /* We need to check again in a case another CPU has just
4831 * made room available.
4832 */
4833 if (igb_desc_unused(tx_ring) < size)
4834 return -EBUSY;
4835
4836 /* A reprieve! */
4837 netif_wake_subqueue(netdev, tx_ring->queue_index);
4838
4839 u64_stats_update_begin(&tx_ring->tx_syncp2);
4840 tx_ring->tx_stats.restart_queue2++;
4841 u64_stats_update_end(&tx_ring->tx_syncp2);
4842
4843 return 0;
4844 }
4845
4846 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4847 {
4848 if (igb_desc_unused(tx_ring) >= size)
4849 return 0;
4850 return __igb_maybe_stop_tx(tx_ring, size);
4851 }
4852
4853 static void igb_tx_map(struct igb_ring *tx_ring,
4854 struct igb_tx_buffer *first,
4855 const u8 hdr_len)
4856 {
4857 struct sk_buff *skb = first->skb;
4858 struct igb_tx_buffer *tx_buffer;
4859 union e1000_adv_tx_desc *tx_desc;
4860 struct skb_frag_struct *frag;
4861 dma_addr_t dma;
4862 unsigned int data_len, size;
4863 u32 tx_flags = first->tx_flags;
4864 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4865 u16 i = tx_ring->next_to_use;
4866
4867 tx_desc = IGB_TX_DESC(tx_ring, i);
4868
4869 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4870
4871 size = skb_headlen(skb);
4872 data_len = skb->data_len;
4873
4874 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4875
4876 tx_buffer = first;
4877
4878 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4879 if (dma_mapping_error(tx_ring->dev, dma))
4880 goto dma_error;
4881
4882 /* record length, and DMA address */
4883 dma_unmap_len_set(tx_buffer, len, size);
4884 dma_unmap_addr_set(tx_buffer, dma, dma);
4885
4886 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4887
4888 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4889 tx_desc->read.cmd_type_len =
4890 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4891
4892 i++;
4893 tx_desc++;
4894 if (i == tx_ring->count) {
4895 tx_desc = IGB_TX_DESC(tx_ring, 0);
4896 i = 0;
4897 }
4898 tx_desc->read.olinfo_status = 0;
4899
4900 dma += IGB_MAX_DATA_PER_TXD;
4901 size -= IGB_MAX_DATA_PER_TXD;
4902
4903 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4904 }
4905
4906 if (likely(!data_len))
4907 break;
4908
4909 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4910
4911 i++;
4912 tx_desc++;
4913 if (i == tx_ring->count) {
4914 tx_desc = IGB_TX_DESC(tx_ring, 0);
4915 i = 0;
4916 }
4917 tx_desc->read.olinfo_status = 0;
4918
4919 size = skb_frag_size(frag);
4920 data_len -= size;
4921
4922 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4923 size, DMA_TO_DEVICE);
4924
4925 tx_buffer = &tx_ring->tx_buffer_info[i];
4926 }
4927
4928 /* write last descriptor with RS and EOP bits */
4929 cmd_type |= size | IGB_TXD_DCMD;
4930 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4931
4932 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4933
4934 /* set the timestamp */
4935 first->time_stamp = jiffies;
4936
4937 /* Force memory writes to complete before letting h/w know there
4938 * are new descriptors to fetch. (Only applicable for weak-ordered
4939 * memory model archs, such as IA-64).
4940 *
4941 * We also need this memory barrier to make certain all of the
4942 * status bits have been updated before next_to_watch is written.
4943 */
4944 wmb();
4945
4946 /* set next_to_watch value indicating a packet is present */
4947 first->next_to_watch = tx_desc;
4948
4949 i++;
4950 if (i == tx_ring->count)
4951 i = 0;
4952
4953 tx_ring->next_to_use = i;
4954
4955 /* Make sure there is space in the ring for the next send. */
4956 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4957
4958 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
4959 writel(i, tx_ring->tail);
4960
4961 /* we need this if more than one processor can write to our tail
4962 * at a time, it synchronizes IO on IA64/Altix systems
4963 */
4964 mmiowb();
4965 }
4966 return;
4967
4968 dma_error:
4969 dev_err(tx_ring->dev, "TX DMA map failed\n");
4970
4971 /* clear dma mappings for failed tx_buffer_info map */
4972 for (;;) {
4973 tx_buffer = &tx_ring->tx_buffer_info[i];
4974 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4975 if (tx_buffer == first)
4976 break;
4977 if (i == 0)
4978 i = tx_ring->count;
4979 i--;
4980 }
4981
4982 tx_ring->next_to_use = i;
4983 }
4984
4985 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4986 struct igb_ring *tx_ring)
4987 {
4988 struct igb_tx_buffer *first;
4989 int tso;
4990 u32 tx_flags = 0;
4991 u16 count = TXD_USE_COUNT(skb_headlen(skb));
4992 __be16 protocol = vlan_get_protocol(skb);
4993 u8 hdr_len = 0;
4994
4995 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4996 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4997 * + 2 desc gap to keep tail from touching head,
4998 * + 1 desc for context descriptor,
4999 * otherwise try next time
5000 */
5001 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
5002 unsigned short f;
5003
5004 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5005 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5006 } else {
5007 count += skb_shinfo(skb)->nr_frags;
5008 }
5009
5010 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5011 /* this is a hard error */
5012 return NETDEV_TX_BUSY;
5013 }
5014
5015 /* record the location of the first descriptor for this packet */
5016 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5017 first->skb = skb;
5018 first->bytecount = skb->len;
5019 first->gso_segs = 1;
5020
5021 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5022 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5023
5024 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5025 &adapter->state)) {
5026 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5027 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5028
5029 adapter->ptp_tx_skb = skb_get(skb);
5030 adapter->ptp_tx_start = jiffies;
5031 if (adapter->hw.mac.type == e1000_82576)
5032 schedule_work(&adapter->ptp_tx_work);
5033 }
5034 }
5035
5036 skb_tx_timestamp(skb);
5037
5038 if (vlan_tx_tag_present(skb)) {
5039 tx_flags |= IGB_TX_FLAGS_VLAN;
5040 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5041 }
5042
5043 /* record initial flags and protocol */
5044 first->tx_flags = tx_flags;
5045 first->protocol = protocol;
5046
5047 tso = igb_tso(tx_ring, first, &hdr_len);
5048 if (tso < 0)
5049 goto out_drop;
5050 else if (!tso)
5051 igb_tx_csum(tx_ring, first);
5052
5053 igb_tx_map(tx_ring, first, hdr_len);
5054
5055 return NETDEV_TX_OK;
5056
5057 out_drop:
5058 igb_unmap_and_free_tx_resource(tx_ring, first);
5059
5060 return NETDEV_TX_OK;
5061 }
5062
5063 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5064 struct sk_buff *skb)
5065 {
5066 unsigned int r_idx = skb->queue_mapping;
5067
5068 if (r_idx >= adapter->num_tx_queues)
5069 r_idx = r_idx % adapter->num_tx_queues;
5070
5071 return adapter->tx_ring[r_idx];
5072 }
5073
5074 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5075 struct net_device *netdev)
5076 {
5077 struct igb_adapter *adapter = netdev_priv(netdev);
5078
5079 if (test_bit(__IGB_DOWN, &adapter->state)) {
5080 dev_kfree_skb_any(skb);
5081 return NETDEV_TX_OK;
5082 }
5083
5084 if (skb->len <= 0) {
5085 dev_kfree_skb_any(skb);
5086 return NETDEV_TX_OK;
5087 }
5088
5089 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5090 * in order to meet this minimum size requirement.
5091 */
5092 if (skb_put_padto(skb, 17))
5093 return NETDEV_TX_OK;
5094
5095 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5096 }
5097
5098 /**
5099 * igb_tx_timeout - Respond to a Tx Hang
5100 * @netdev: network interface device structure
5101 **/
5102 static void igb_tx_timeout(struct net_device *netdev)
5103 {
5104 struct igb_adapter *adapter = netdev_priv(netdev);
5105 struct e1000_hw *hw = &adapter->hw;
5106
5107 /* Do the reset outside of interrupt context */
5108 adapter->tx_timeout_count++;
5109
5110 if (hw->mac.type >= e1000_82580)
5111 hw->dev_spec._82575.global_device_reset = true;
5112
5113 schedule_work(&adapter->reset_task);
5114 wr32(E1000_EICS,
5115 (adapter->eims_enable_mask & ~adapter->eims_other));
5116 }
5117
5118 static void igb_reset_task(struct work_struct *work)
5119 {
5120 struct igb_adapter *adapter;
5121 adapter = container_of(work, struct igb_adapter, reset_task);
5122
5123 igb_dump(adapter);
5124 netdev_err(adapter->netdev, "Reset adapter\n");
5125 igb_reinit_locked(adapter);
5126 }
5127
5128 /**
5129 * igb_get_stats64 - Get System Network Statistics
5130 * @netdev: network interface device structure
5131 * @stats: rtnl_link_stats64 pointer
5132 **/
5133 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
5134 struct rtnl_link_stats64 *stats)
5135 {
5136 struct igb_adapter *adapter = netdev_priv(netdev);
5137
5138 spin_lock(&adapter->stats64_lock);
5139 igb_update_stats(adapter, &adapter->stats64);
5140 memcpy(stats, &adapter->stats64, sizeof(*stats));
5141 spin_unlock(&adapter->stats64_lock);
5142
5143 return stats;
5144 }
5145
5146 /**
5147 * igb_change_mtu - Change the Maximum Transfer Unit
5148 * @netdev: network interface device structure
5149 * @new_mtu: new value for maximum frame size
5150 *
5151 * Returns 0 on success, negative on failure
5152 **/
5153 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5154 {
5155 struct igb_adapter *adapter = netdev_priv(netdev);
5156 struct pci_dev *pdev = adapter->pdev;
5157 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5158
5159 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
5160 dev_err(&pdev->dev, "Invalid MTU setting\n");
5161 return -EINVAL;
5162 }
5163
5164 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5165 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
5166 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
5167 return -EINVAL;
5168 }
5169
5170 /* adjust max frame to be at least the size of a standard frame */
5171 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5172 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5173
5174 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5175 usleep_range(1000, 2000);
5176
5177 /* igb_down has a dependency on max_frame_size */
5178 adapter->max_frame_size = max_frame;
5179
5180 if (netif_running(netdev))
5181 igb_down(adapter);
5182
5183 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5184 netdev->mtu, new_mtu);
5185 netdev->mtu = new_mtu;
5186
5187 if (netif_running(netdev))
5188 igb_up(adapter);
5189 else
5190 igb_reset(adapter);
5191
5192 clear_bit(__IGB_RESETTING, &adapter->state);
5193
5194 return 0;
5195 }
5196
5197 /**
5198 * igb_update_stats - Update the board statistics counters
5199 * @adapter: board private structure
5200 **/
5201 void igb_update_stats(struct igb_adapter *adapter,
5202 struct rtnl_link_stats64 *net_stats)
5203 {
5204 struct e1000_hw *hw = &adapter->hw;
5205 struct pci_dev *pdev = adapter->pdev;
5206 u32 reg, mpc;
5207 int i;
5208 u64 bytes, packets;
5209 unsigned int start;
5210 u64 _bytes, _packets;
5211
5212 /* Prevent stats update while adapter is being reset, or if the pci
5213 * connection is down.
5214 */
5215 if (adapter->link_speed == 0)
5216 return;
5217 if (pci_channel_offline(pdev))
5218 return;
5219
5220 bytes = 0;
5221 packets = 0;
5222
5223 rcu_read_lock();
5224 for (i = 0; i < adapter->num_rx_queues; i++) {
5225 struct igb_ring *ring = adapter->rx_ring[i];
5226 u32 rqdpc = rd32(E1000_RQDPC(i));
5227 if (hw->mac.type >= e1000_i210)
5228 wr32(E1000_RQDPC(i), 0);
5229
5230 if (rqdpc) {
5231 ring->rx_stats.drops += rqdpc;
5232 net_stats->rx_fifo_errors += rqdpc;
5233 }
5234
5235 do {
5236 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5237 _bytes = ring->rx_stats.bytes;
5238 _packets = ring->rx_stats.packets;
5239 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5240 bytes += _bytes;
5241 packets += _packets;
5242 }
5243
5244 net_stats->rx_bytes = bytes;
5245 net_stats->rx_packets = packets;
5246
5247 bytes = 0;
5248 packets = 0;
5249 for (i = 0; i < adapter->num_tx_queues; i++) {
5250 struct igb_ring *ring = adapter->tx_ring[i];
5251 do {
5252 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5253 _bytes = ring->tx_stats.bytes;
5254 _packets = ring->tx_stats.packets;
5255 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5256 bytes += _bytes;
5257 packets += _packets;
5258 }
5259 net_stats->tx_bytes = bytes;
5260 net_stats->tx_packets = packets;
5261 rcu_read_unlock();
5262
5263 /* read stats registers */
5264 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5265 adapter->stats.gprc += rd32(E1000_GPRC);
5266 adapter->stats.gorc += rd32(E1000_GORCL);
5267 rd32(E1000_GORCH); /* clear GORCL */
5268 adapter->stats.bprc += rd32(E1000_BPRC);
5269 adapter->stats.mprc += rd32(E1000_MPRC);
5270 adapter->stats.roc += rd32(E1000_ROC);
5271
5272 adapter->stats.prc64 += rd32(E1000_PRC64);
5273 adapter->stats.prc127 += rd32(E1000_PRC127);
5274 adapter->stats.prc255 += rd32(E1000_PRC255);
5275 adapter->stats.prc511 += rd32(E1000_PRC511);
5276 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5277 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5278 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5279 adapter->stats.sec += rd32(E1000_SEC);
5280
5281 mpc = rd32(E1000_MPC);
5282 adapter->stats.mpc += mpc;
5283 net_stats->rx_fifo_errors += mpc;
5284 adapter->stats.scc += rd32(E1000_SCC);
5285 adapter->stats.ecol += rd32(E1000_ECOL);
5286 adapter->stats.mcc += rd32(E1000_MCC);
5287 adapter->stats.latecol += rd32(E1000_LATECOL);
5288 adapter->stats.dc += rd32(E1000_DC);
5289 adapter->stats.rlec += rd32(E1000_RLEC);
5290 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5291 adapter->stats.xontxc += rd32(E1000_XONTXC);
5292 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5293 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5294 adapter->stats.fcruc += rd32(E1000_FCRUC);
5295 adapter->stats.gptc += rd32(E1000_GPTC);
5296 adapter->stats.gotc += rd32(E1000_GOTCL);
5297 rd32(E1000_GOTCH); /* clear GOTCL */
5298 adapter->stats.rnbc += rd32(E1000_RNBC);
5299 adapter->stats.ruc += rd32(E1000_RUC);
5300 adapter->stats.rfc += rd32(E1000_RFC);
5301 adapter->stats.rjc += rd32(E1000_RJC);
5302 adapter->stats.tor += rd32(E1000_TORH);
5303 adapter->stats.tot += rd32(E1000_TOTH);
5304 adapter->stats.tpr += rd32(E1000_TPR);
5305
5306 adapter->stats.ptc64 += rd32(E1000_PTC64);
5307 adapter->stats.ptc127 += rd32(E1000_PTC127);
5308 adapter->stats.ptc255 += rd32(E1000_PTC255);
5309 adapter->stats.ptc511 += rd32(E1000_PTC511);
5310 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5311 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5312
5313 adapter->stats.mptc += rd32(E1000_MPTC);
5314 adapter->stats.bptc += rd32(E1000_BPTC);
5315
5316 adapter->stats.tpt += rd32(E1000_TPT);
5317 adapter->stats.colc += rd32(E1000_COLC);
5318
5319 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5320 /* read internal phy specific stats */
5321 reg = rd32(E1000_CTRL_EXT);
5322 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5323 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5324
5325 /* this stat has invalid values on i210/i211 */
5326 if ((hw->mac.type != e1000_i210) &&
5327 (hw->mac.type != e1000_i211))
5328 adapter->stats.tncrs += rd32(E1000_TNCRS);
5329 }
5330
5331 adapter->stats.tsctc += rd32(E1000_TSCTC);
5332 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5333
5334 adapter->stats.iac += rd32(E1000_IAC);
5335 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5336 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5337 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5338 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5339 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5340 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5341 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5342 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5343
5344 /* Fill out the OS statistics structure */
5345 net_stats->multicast = adapter->stats.mprc;
5346 net_stats->collisions = adapter->stats.colc;
5347
5348 /* Rx Errors */
5349
5350 /* RLEC on some newer hardware can be incorrect so build
5351 * our own version based on RUC and ROC
5352 */
5353 net_stats->rx_errors = adapter->stats.rxerrc +
5354 adapter->stats.crcerrs + adapter->stats.algnerrc +
5355 adapter->stats.ruc + adapter->stats.roc +
5356 adapter->stats.cexterr;
5357 net_stats->rx_length_errors = adapter->stats.ruc +
5358 adapter->stats.roc;
5359 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5360 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5361 net_stats->rx_missed_errors = adapter->stats.mpc;
5362
5363 /* Tx Errors */
5364 net_stats->tx_errors = adapter->stats.ecol +
5365 adapter->stats.latecol;
5366 net_stats->tx_aborted_errors = adapter->stats.ecol;
5367 net_stats->tx_window_errors = adapter->stats.latecol;
5368 net_stats->tx_carrier_errors = adapter->stats.tncrs;
5369
5370 /* Tx Dropped needs to be maintained elsewhere */
5371
5372 /* Management Stats */
5373 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5374 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5375 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5376
5377 /* OS2BMC Stats */
5378 reg = rd32(E1000_MANC);
5379 if (reg & E1000_MANC_EN_BMC2OS) {
5380 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5381 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5382 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5383 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5384 }
5385 }
5386
5387 static irqreturn_t igb_msix_other(int irq, void *data)
5388 {
5389 struct igb_adapter *adapter = data;
5390 struct e1000_hw *hw = &adapter->hw;
5391 u32 icr = rd32(E1000_ICR);
5392 /* reading ICR causes bit 31 of EICR to be cleared */
5393
5394 if (icr & E1000_ICR_DRSTA)
5395 schedule_work(&adapter->reset_task);
5396
5397 if (icr & E1000_ICR_DOUTSYNC) {
5398 /* HW is reporting DMA is out of sync */
5399 adapter->stats.doosync++;
5400 /* The DMA Out of Sync is also indication of a spoof event
5401 * in IOV mode. Check the Wrong VM Behavior register to
5402 * see if it is really a spoof event.
5403 */
5404 igb_check_wvbr(adapter);
5405 }
5406
5407 /* Check for a mailbox event */
5408 if (icr & E1000_ICR_VMMB)
5409 igb_msg_task(adapter);
5410
5411 if (icr & E1000_ICR_LSC) {
5412 hw->mac.get_link_status = 1;
5413 /* guard against interrupt when we're going down */
5414 if (!test_bit(__IGB_DOWN, &adapter->state))
5415 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5416 }
5417
5418 if (icr & E1000_ICR_TS) {
5419 u32 tsicr = rd32(E1000_TSICR);
5420
5421 if (tsicr & E1000_TSICR_TXTS) {
5422 /* acknowledge the interrupt */
5423 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5424 /* retrieve hardware timestamp */
5425 schedule_work(&adapter->ptp_tx_work);
5426 }
5427 }
5428
5429 wr32(E1000_EIMS, adapter->eims_other);
5430
5431 return IRQ_HANDLED;
5432 }
5433
5434 static void igb_write_itr(struct igb_q_vector *q_vector)
5435 {
5436 struct igb_adapter *adapter = q_vector->adapter;
5437 u32 itr_val = q_vector->itr_val & 0x7FFC;
5438
5439 if (!q_vector->set_itr)
5440 return;
5441
5442 if (!itr_val)
5443 itr_val = 0x4;
5444
5445 if (adapter->hw.mac.type == e1000_82575)
5446 itr_val |= itr_val << 16;
5447 else
5448 itr_val |= E1000_EITR_CNT_IGNR;
5449
5450 writel(itr_val, q_vector->itr_register);
5451 q_vector->set_itr = 0;
5452 }
5453
5454 static irqreturn_t igb_msix_ring(int irq, void *data)
5455 {
5456 struct igb_q_vector *q_vector = data;
5457
5458 /* Write the ITR value calculated from the previous interrupt. */
5459 igb_write_itr(q_vector);
5460
5461 napi_schedule(&q_vector->napi);
5462
5463 return IRQ_HANDLED;
5464 }
5465
5466 #ifdef CONFIG_IGB_DCA
5467 static void igb_update_tx_dca(struct igb_adapter *adapter,
5468 struct igb_ring *tx_ring,
5469 int cpu)
5470 {
5471 struct e1000_hw *hw = &adapter->hw;
5472 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5473
5474 if (hw->mac.type != e1000_82575)
5475 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5476
5477 /* We can enable relaxed ordering for reads, but not writes when
5478 * DCA is enabled. This is due to a known issue in some chipsets
5479 * which will cause the DCA tag to be cleared.
5480 */
5481 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5482 E1000_DCA_TXCTRL_DATA_RRO_EN |
5483 E1000_DCA_TXCTRL_DESC_DCA_EN;
5484
5485 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5486 }
5487
5488 static void igb_update_rx_dca(struct igb_adapter *adapter,
5489 struct igb_ring *rx_ring,
5490 int cpu)
5491 {
5492 struct e1000_hw *hw = &adapter->hw;
5493 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5494
5495 if (hw->mac.type != e1000_82575)
5496 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5497
5498 /* We can enable relaxed ordering for reads, but not writes when
5499 * DCA is enabled. This is due to a known issue in some chipsets
5500 * which will cause the DCA tag to be cleared.
5501 */
5502 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5503 E1000_DCA_RXCTRL_DESC_DCA_EN;
5504
5505 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5506 }
5507
5508 static void igb_update_dca(struct igb_q_vector *q_vector)
5509 {
5510 struct igb_adapter *adapter = q_vector->adapter;
5511 int cpu = get_cpu();
5512
5513 if (q_vector->cpu == cpu)
5514 goto out_no_update;
5515
5516 if (q_vector->tx.ring)
5517 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5518
5519 if (q_vector->rx.ring)
5520 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5521
5522 q_vector->cpu = cpu;
5523 out_no_update:
5524 put_cpu();
5525 }
5526
5527 static void igb_setup_dca(struct igb_adapter *adapter)
5528 {
5529 struct e1000_hw *hw = &adapter->hw;
5530 int i;
5531
5532 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5533 return;
5534
5535 /* Always use CB2 mode, difference is masked in the CB driver. */
5536 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5537
5538 for (i = 0; i < adapter->num_q_vectors; i++) {
5539 adapter->q_vector[i]->cpu = -1;
5540 igb_update_dca(adapter->q_vector[i]);
5541 }
5542 }
5543
5544 static int __igb_notify_dca(struct device *dev, void *data)
5545 {
5546 struct net_device *netdev = dev_get_drvdata(dev);
5547 struct igb_adapter *adapter = netdev_priv(netdev);
5548 struct pci_dev *pdev = adapter->pdev;
5549 struct e1000_hw *hw = &adapter->hw;
5550 unsigned long event = *(unsigned long *)data;
5551
5552 switch (event) {
5553 case DCA_PROVIDER_ADD:
5554 /* if already enabled, don't do it again */
5555 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5556 break;
5557 if (dca_add_requester(dev) == 0) {
5558 adapter->flags |= IGB_FLAG_DCA_ENABLED;
5559 dev_info(&pdev->dev, "DCA enabled\n");
5560 igb_setup_dca(adapter);
5561 break;
5562 }
5563 /* Fall Through since DCA is disabled. */
5564 case DCA_PROVIDER_REMOVE:
5565 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5566 /* without this a class_device is left
5567 * hanging around in the sysfs model
5568 */
5569 dca_remove_requester(dev);
5570 dev_info(&pdev->dev, "DCA disabled\n");
5571 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5572 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5573 }
5574 break;
5575 }
5576
5577 return 0;
5578 }
5579
5580 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5581 void *p)
5582 {
5583 int ret_val;
5584
5585 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5586 __igb_notify_dca);
5587
5588 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5589 }
5590 #endif /* CONFIG_IGB_DCA */
5591
5592 #ifdef CONFIG_PCI_IOV
5593 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5594 {
5595 unsigned char mac_addr[ETH_ALEN];
5596
5597 eth_zero_addr(mac_addr);
5598 igb_set_vf_mac(adapter, vf, mac_addr);
5599
5600 /* By default spoof check is enabled for all VFs */
5601 adapter->vf_data[vf].spoofchk_enabled = true;
5602
5603 return 0;
5604 }
5605
5606 #endif
5607 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5608 {
5609 struct e1000_hw *hw = &adapter->hw;
5610 u32 ping;
5611 int i;
5612
5613 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5614 ping = E1000_PF_CONTROL_MSG;
5615 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5616 ping |= E1000_VT_MSGTYPE_CTS;
5617 igb_write_mbx(hw, &ping, 1, i);
5618 }
5619 }
5620
5621 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5622 {
5623 struct e1000_hw *hw = &adapter->hw;
5624 u32 vmolr = rd32(E1000_VMOLR(vf));
5625 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5626
5627 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5628 IGB_VF_FLAG_MULTI_PROMISC);
5629 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5630
5631 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5632 vmolr |= E1000_VMOLR_MPME;
5633 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5634 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5635 } else {
5636 /* if we have hashes and we are clearing a multicast promisc
5637 * flag we need to write the hashes to the MTA as this step
5638 * was previously skipped
5639 */
5640 if (vf_data->num_vf_mc_hashes > 30) {
5641 vmolr |= E1000_VMOLR_MPME;
5642 } else if (vf_data->num_vf_mc_hashes) {
5643 int j;
5644
5645 vmolr |= E1000_VMOLR_ROMPE;
5646 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5647 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5648 }
5649 }
5650
5651 wr32(E1000_VMOLR(vf), vmolr);
5652
5653 /* there are flags left unprocessed, likely not supported */
5654 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5655 return -EINVAL;
5656
5657 return 0;
5658 }
5659
5660 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5661 u32 *msgbuf, u32 vf)
5662 {
5663 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5664 u16 *hash_list = (u16 *)&msgbuf[1];
5665 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5666 int i;
5667
5668 /* salt away the number of multicast addresses assigned
5669 * to this VF for later use to restore when the PF multi cast
5670 * list changes
5671 */
5672 vf_data->num_vf_mc_hashes = n;
5673
5674 /* only up to 30 hash values supported */
5675 if (n > 30)
5676 n = 30;
5677
5678 /* store the hashes for later use */
5679 for (i = 0; i < n; i++)
5680 vf_data->vf_mc_hashes[i] = hash_list[i];
5681
5682 /* Flush and reset the mta with the new values */
5683 igb_set_rx_mode(adapter->netdev);
5684
5685 return 0;
5686 }
5687
5688 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5689 {
5690 struct e1000_hw *hw = &adapter->hw;
5691 struct vf_data_storage *vf_data;
5692 int i, j;
5693
5694 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5695 u32 vmolr = rd32(E1000_VMOLR(i));
5696
5697 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5698
5699 vf_data = &adapter->vf_data[i];
5700
5701 if ((vf_data->num_vf_mc_hashes > 30) ||
5702 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5703 vmolr |= E1000_VMOLR_MPME;
5704 } else if (vf_data->num_vf_mc_hashes) {
5705 vmolr |= E1000_VMOLR_ROMPE;
5706 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5707 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5708 }
5709 wr32(E1000_VMOLR(i), vmolr);
5710 }
5711 }
5712
5713 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5714 {
5715 struct e1000_hw *hw = &adapter->hw;
5716 u32 pool_mask, reg, vid;
5717 int i;
5718
5719 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5720
5721 /* Find the vlan filter for this id */
5722 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5723 reg = rd32(E1000_VLVF(i));
5724
5725 /* remove the vf from the pool */
5726 reg &= ~pool_mask;
5727
5728 /* if pool is empty then remove entry from vfta */
5729 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5730 (reg & E1000_VLVF_VLANID_ENABLE)) {
5731 reg = 0;
5732 vid = reg & E1000_VLVF_VLANID_MASK;
5733 igb_vfta_set(hw, vid, false);
5734 }
5735
5736 wr32(E1000_VLVF(i), reg);
5737 }
5738
5739 adapter->vf_data[vf].vlans_enabled = 0;
5740 }
5741
5742 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5743 {
5744 struct e1000_hw *hw = &adapter->hw;
5745 u32 reg, i;
5746
5747 /* The vlvf table only exists on 82576 hardware and newer */
5748 if (hw->mac.type < e1000_82576)
5749 return -1;
5750
5751 /* we only need to do this if VMDq is enabled */
5752 if (!adapter->vfs_allocated_count)
5753 return -1;
5754
5755 /* Find the vlan filter for this id */
5756 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5757 reg = rd32(E1000_VLVF(i));
5758 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5759 vid == (reg & E1000_VLVF_VLANID_MASK))
5760 break;
5761 }
5762
5763 if (add) {
5764 if (i == E1000_VLVF_ARRAY_SIZE) {
5765 /* Did not find a matching VLAN ID entry that was
5766 * enabled. Search for a free filter entry, i.e.
5767 * one without the enable bit set
5768 */
5769 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5770 reg = rd32(E1000_VLVF(i));
5771 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5772 break;
5773 }
5774 }
5775 if (i < E1000_VLVF_ARRAY_SIZE) {
5776 /* Found an enabled/available entry */
5777 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5778
5779 /* if !enabled we need to set this up in vfta */
5780 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5781 /* add VID to filter table */
5782 igb_vfta_set(hw, vid, true);
5783 reg |= E1000_VLVF_VLANID_ENABLE;
5784 }
5785 reg &= ~E1000_VLVF_VLANID_MASK;
5786 reg |= vid;
5787 wr32(E1000_VLVF(i), reg);
5788
5789 /* do not modify RLPML for PF devices */
5790 if (vf >= adapter->vfs_allocated_count)
5791 return 0;
5792
5793 if (!adapter->vf_data[vf].vlans_enabled) {
5794 u32 size;
5795
5796 reg = rd32(E1000_VMOLR(vf));
5797 size = reg & E1000_VMOLR_RLPML_MASK;
5798 size += 4;
5799 reg &= ~E1000_VMOLR_RLPML_MASK;
5800 reg |= size;
5801 wr32(E1000_VMOLR(vf), reg);
5802 }
5803
5804 adapter->vf_data[vf].vlans_enabled++;
5805 }
5806 } else {
5807 if (i < E1000_VLVF_ARRAY_SIZE) {
5808 /* remove vf from the pool */
5809 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5810 /* if pool is empty then remove entry from vfta */
5811 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5812 reg = 0;
5813 igb_vfta_set(hw, vid, false);
5814 }
5815 wr32(E1000_VLVF(i), reg);
5816
5817 /* do not modify RLPML for PF devices */
5818 if (vf >= adapter->vfs_allocated_count)
5819 return 0;
5820
5821 adapter->vf_data[vf].vlans_enabled--;
5822 if (!adapter->vf_data[vf].vlans_enabled) {
5823 u32 size;
5824
5825 reg = rd32(E1000_VMOLR(vf));
5826 size = reg & E1000_VMOLR_RLPML_MASK;
5827 size -= 4;
5828 reg &= ~E1000_VMOLR_RLPML_MASK;
5829 reg |= size;
5830 wr32(E1000_VMOLR(vf), reg);
5831 }
5832 }
5833 }
5834 return 0;
5835 }
5836
5837 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5838 {
5839 struct e1000_hw *hw = &adapter->hw;
5840
5841 if (vid)
5842 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5843 else
5844 wr32(E1000_VMVIR(vf), 0);
5845 }
5846
5847 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5848 int vf, u16 vlan, u8 qos)
5849 {
5850 int err = 0;
5851 struct igb_adapter *adapter = netdev_priv(netdev);
5852
5853 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5854 return -EINVAL;
5855 if (vlan || qos) {
5856 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5857 if (err)
5858 goto out;
5859 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5860 igb_set_vmolr(adapter, vf, !vlan);
5861 adapter->vf_data[vf].pf_vlan = vlan;
5862 adapter->vf_data[vf].pf_qos = qos;
5863 dev_info(&adapter->pdev->dev,
5864 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5865 if (test_bit(__IGB_DOWN, &adapter->state)) {
5866 dev_warn(&adapter->pdev->dev,
5867 "The VF VLAN has been set, but the PF device is not up.\n");
5868 dev_warn(&adapter->pdev->dev,
5869 "Bring the PF device up before attempting to use the VF device.\n");
5870 }
5871 } else {
5872 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5873 false, vf);
5874 igb_set_vmvir(adapter, vlan, vf);
5875 igb_set_vmolr(adapter, vf, true);
5876 adapter->vf_data[vf].pf_vlan = 0;
5877 adapter->vf_data[vf].pf_qos = 0;
5878 }
5879 out:
5880 return err;
5881 }
5882
5883 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5884 {
5885 struct e1000_hw *hw = &adapter->hw;
5886 int i;
5887 u32 reg;
5888
5889 /* Find the vlan filter for this id */
5890 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5891 reg = rd32(E1000_VLVF(i));
5892 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5893 vid == (reg & E1000_VLVF_VLANID_MASK))
5894 break;
5895 }
5896
5897 if (i >= E1000_VLVF_ARRAY_SIZE)
5898 i = -1;
5899
5900 return i;
5901 }
5902
5903 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5904 {
5905 struct e1000_hw *hw = &adapter->hw;
5906 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5907 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5908 int err = 0;
5909
5910 /* If in promiscuous mode we need to make sure the PF also has
5911 * the VLAN filter set.
5912 */
5913 if (add && (adapter->netdev->flags & IFF_PROMISC))
5914 err = igb_vlvf_set(adapter, vid, add,
5915 adapter->vfs_allocated_count);
5916 if (err)
5917 goto out;
5918
5919 err = igb_vlvf_set(adapter, vid, add, vf);
5920
5921 if (err)
5922 goto out;
5923
5924 /* Go through all the checks to see if the VLAN filter should
5925 * be wiped completely.
5926 */
5927 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5928 u32 vlvf, bits;
5929 int regndx = igb_find_vlvf_entry(adapter, vid);
5930
5931 if (regndx < 0)
5932 goto out;
5933 /* See if any other pools are set for this VLAN filter
5934 * entry other than the PF.
5935 */
5936 vlvf = bits = rd32(E1000_VLVF(regndx));
5937 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5938 adapter->vfs_allocated_count);
5939 /* If the filter was removed then ensure PF pool bit
5940 * is cleared if the PF only added itself to the pool
5941 * because the PF is in promiscuous mode.
5942 */
5943 if ((vlvf & VLAN_VID_MASK) == vid &&
5944 !test_bit(vid, adapter->active_vlans) &&
5945 !bits)
5946 igb_vlvf_set(adapter, vid, add,
5947 adapter->vfs_allocated_count);
5948 }
5949
5950 out:
5951 return err;
5952 }
5953
5954 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5955 {
5956 /* clear flags - except flag that indicates PF has set the MAC */
5957 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5958 adapter->vf_data[vf].last_nack = jiffies;
5959
5960 /* reset offloads to defaults */
5961 igb_set_vmolr(adapter, vf, true);
5962
5963 /* reset vlans for device */
5964 igb_clear_vf_vfta(adapter, vf);
5965 if (adapter->vf_data[vf].pf_vlan)
5966 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5967 adapter->vf_data[vf].pf_vlan,
5968 adapter->vf_data[vf].pf_qos);
5969 else
5970 igb_clear_vf_vfta(adapter, vf);
5971
5972 /* reset multicast table array for vf */
5973 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5974
5975 /* Flush and reset the mta with the new values */
5976 igb_set_rx_mode(adapter->netdev);
5977 }
5978
5979 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5980 {
5981 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5982
5983 /* clear mac address as we were hotplug removed/added */
5984 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5985 eth_zero_addr(vf_mac);
5986
5987 /* process remaining reset events */
5988 igb_vf_reset(adapter, vf);
5989 }
5990
5991 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5992 {
5993 struct e1000_hw *hw = &adapter->hw;
5994 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5995 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5996 u32 reg, msgbuf[3];
5997 u8 *addr = (u8 *)(&msgbuf[1]);
5998
5999 /* process all the same items cleared in a function level reset */
6000 igb_vf_reset(adapter, vf);
6001
6002 /* set vf mac address */
6003 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
6004
6005 /* enable transmit and receive for vf */
6006 reg = rd32(E1000_VFTE);
6007 wr32(E1000_VFTE, reg | (1 << vf));
6008 reg = rd32(E1000_VFRE);
6009 wr32(E1000_VFRE, reg | (1 << vf));
6010
6011 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6012
6013 /* reply to reset with ack and vf mac address */
6014 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6015 memcpy(addr, vf_mac, ETH_ALEN);
6016 igb_write_mbx(hw, msgbuf, 3, vf);
6017 }
6018
6019 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6020 {
6021 /* The VF MAC Address is stored in a packed array of bytes
6022 * starting at the second 32 bit word of the msg array
6023 */
6024 unsigned char *addr = (char *)&msg[1];
6025 int err = -1;
6026
6027 if (is_valid_ether_addr(addr))
6028 err = igb_set_vf_mac(adapter, vf, addr);
6029
6030 return err;
6031 }
6032
6033 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6034 {
6035 struct e1000_hw *hw = &adapter->hw;
6036 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6037 u32 msg = E1000_VT_MSGTYPE_NACK;
6038
6039 /* if device isn't clear to send it shouldn't be reading either */
6040 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6041 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
6042 igb_write_mbx(hw, &msg, 1, vf);
6043 vf_data->last_nack = jiffies;
6044 }
6045 }
6046
6047 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
6048 {
6049 struct pci_dev *pdev = adapter->pdev;
6050 u32 msgbuf[E1000_VFMAILBOX_SIZE];
6051 struct e1000_hw *hw = &adapter->hw;
6052 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6053 s32 retval;
6054
6055 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
6056
6057 if (retval) {
6058 /* if receive failed revoke VF CTS stats and restart init */
6059 dev_err(&pdev->dev, "Error receiving message from VF\n");
6060 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6061 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6062 return;
6063 goto out;
6064 }
6065
6066 /* this is a message we already processed, do nothing */
6067 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
6068 return;
6069
6070 /* until the vf completes a reset it should not be
6071 * allowed to start any configuration.
6072 */
6073 if (msgbuf[0] == E1000_VF_RESET) {
6074 igb_vf_reset_msg(adapter, vf);
6075 return;
6076 }
6077
6078 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
6079 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6080 return;
6081 retval = -1;
6082 goto out;
6083 }
6084
6085 switch ((msgbuf[0] & 0xFFFF)) {
6086 case E1000_VF_SET_MAC_ADDR:
6087 retval = -EINVAL;
6088 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6089 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6090 else
6091 dev_warn(&pdev->dev,
6092 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6093 vf);
6094 break;
6095 case E1000_VF_SET_PROMISC:
6096 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6097 break;
6098 case E1000_VF_SET_MULTICAST:
6099 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6100 break;
6101 case E1000_VF_SET_LPE:
6102 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6103 break;
6104 case E1000_VF_SET_VLAN:
6105 retval = -1;
6106 if (vf_data->pf_vlan)
6107 dev_warn(&pdev->dev,
6108 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6109 vf);
6110 else
6111 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
6112 break;
6113 default:
6114 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
6115 retval = -1;
6116 break;
6117 }
6118
6119 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6120 out:
6121 /* notify the VF of the results of what it sent us */
6122 if (retval)
6123 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6124 else
6125 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6126
6127 igb_write_mbx(hw, msgbuf, 1, vf);
6128 }
6129
6130 static void igb_msg_task(struct igb_adapter *adapter)
6131 {
6132 struct e1000_hw *hw = &adapter->hw;
6133 u32 vf;
6134
6135 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6136 /* process any reset requests */
6137 if (!igb_check_for_rst(hw, vf))
6138 igb_vf_reset_event(adapter, vf);
6139
6140 /* process any messages pending */
6141 if (!igb_check_for_msg(hw, vf))
6142 igb_rcv_msg_from_vf(adapter, vf);
6143
6144 /* process any acks */
6145 if (!igb_check_for_ack(hw, vf))
6146 igb_rcv_ack_from_vf(adapter, vf);
6147 }
6148 }
6149
6150 /**
6151 * igb_set_uta - Set unicast filter table address
6152 * @adapter: board private structure
6153 *
6154 * The unicast table address is a register array of 32-bit registers.
6155 * The table is meant to be used in a way similar to how the MTA is used
6156 * however due to certain limitations in the hardware it is necessary to
6157 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6158 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6159 **/
6160 static void igb_set_uta(struct igb_adapter *adapter)
6161 {
6162 struct e1000_hw *hw = &adapter->hw;
6163 int i;
6164
6165 /* The UTA table only exists on 82576 hardware and newer */
6166 if (hw->mac.type < e1000_82576)
6167 return;
6168
6169 /* we only need to do this if VMDq is enabled */
6170 if (!adapter->vfs_allocated_count)
6171 return;
6172
6173 for (i = 0; i < hw->mac.uta_reg_count; i++)
6174 array_wr32(E1000_UTA, i, ~0);
6175 }
6176
6177 /**
6178 * igb_intr_msi - Interrupt Handler
6179 * @irq: interrupt number
6180 * @data: pointer to a network interface device structure
6181 **/
6182 static irqreturn_t igb_intr_msi(int irq, void *data)
6183 {
6184 struct igb_adapter *adapter = data;
6185 struct igb_q_vector *q_vector = adapter->q_vector[0];
6186 struct e1000_hw *hw = &adapter->hw;
6187 /* read ICR disables interrupts using IAM */
6188 u32 icr = rd32(E1000_ICR);
6189
6190 igb_write_itr(q_vector);
6191
6192 if (icr & E1000_ICR_DRSTA)
6193 schedule_work(&adapter->reset_task);
6194
6195 if (icr & E1000_ICR_DOUTSYNC) {
6196 /* HW is reporting DMA is out of sync */
6197 adapter->stats.doosync++;
6198 }
6199
6200 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6201 hw->mac.get_link_status = 1;
6202 if (!test_bit(__IGB_DOWN, &adapter->state))
6203 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6204 }
6205
6206 if (icr & E1000_ICR_TS) {
6207 u32 tsicr = rd32(E1000_TSICR);
6208
6209 if (tsicr & E1000_TSICR_TXTS) {
6210 /* acknowledge the interrupt */
6211 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6212 /* retrieve hardware timestamp */
6213 schedule_work(&adapter->ptp_tx_work);
6214 }
6215 }
6216
6217 napi_schedule(&q_vector->napi);
6218
6219 return IRQ_HANDLED;
6220 }
6221
6222 /**
6223 * igb_intr - Legacy Interrupt Handler
6224 * @irq: interrupt number
6225 * @data: pointer to a network interface device structure
6226 **/
6227 static irqreturn_t igb_intr(int irq, void *data)
6228 {
6229 struct igb_adapter *adapter = data;
6230 struct igb_q_vector *q_vector = adapter->q_vector[0];
6231 struct e1000_hw *hw = &adapter->hw;
6232 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6233 * need for the IMC write
6234 */
6235 u32 icr = rd32(E1000_ICR);
6236
6237 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6238 * not set, then the adapter didn't send an interrupt
6239 */
6240 if (!(icr & E1000_ICR_INT_ASSERTED))
6241 return IRQ_NONE;
6242
6243 igb_write_itr(q_vector);
6244
6245 if (icr & E1000_ICR_DRSTA)
6246 schedule_work(&adapter->reset_task);
6247
6248 if (icr & E1000_ICR_DOUTSYNC) {
6249 /* HW is reporting DMA is out of sync */
6250 adapter->stats.doosync++;
6251 }
6252
6253 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6254 hw->mac.get_link_status = 1;
6255 /* guard against interrupt when we're going down */
6256 if (!test_bit(__IGB_DOWN, &adapter->state))
6257 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6258 }
6259
6260 if (icr & E1000_ICR_TS) {
6261 u32 tsicr = rd32(E1000_TSICR);
6262
6263 if (tsicr & E1000_TSICR_TXTS) {
6264 /* acknowledge the interrupt */
6265 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6266 /* retrieve hardware timestamp */
6267 schedule_work(&adapter->ptp_tx_work);
6268 }
6269 }
6270
6271 napi_schedule(&q_vector->napi);
6272
6273 return IRQ_HANDLED;
6274 }
6275
6276 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
6277 {
6278 struct igb_adapter *adapter = q_vector->adapter;
6279 struct e1000_hw *hw = &adapter->hw;
6280
6281 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6282 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6283 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6284 igb_set_itr(q_vector);
6285 else
6286 igb_update_ring_itr(q_vector);
6287 }
6288
6289 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6290 if (adapter->flags & IGB_FLAG_HAS_MSIX)
6291 wr32(E1000_EIMS, q_vector->eims_value);
6292 else
6293 igb_irq_enable(adapter);
6294 }
6295 }
6296
6297 /**
6298 * igb_poll - NAPI Rx polling callback
6299 * @napi: napi polling structure
6300 * @budget: count of how many packets we should handle
6301 **/
6302 static int igb_poll(struct napi_struct *napi, int budget)
6303 {
6304 struct igb_q_vector *q_vector = container_of(napi,
6305 struct igb_q_vector,
6306 napi);
6307 bool clean_complete = true;
6308
6309 #ifdef CONFIG_IGB_DCA
6310 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6311 igb_update_dca(q_vector);
6312 #endif
6313 if (q_vector->tx.ring)
6314 clean_complete = igb_clean_tx_irq(q_vector);
6315
6316 if (q_vector->rx.ring)
6317 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6318
6319 /* If all work not completed, return budget and keep polling */
6320 if (!clean_complete)
6321 return budget;
6322
6323 /* If not enough Rx work done, exit the polling mode */
6324 napi_complete(napi);
6325 igb_ring_irq_enable(q_vector);
6326
6327 return 0;
6328 }
6329
6330 /**
6331 * igb_clean_tx_irq - Reclaim resources after transmit completes
6332 * @q_vector: pointer to q_vector containing needed info
6333 *
6334 * returns true if ring is completely cleaned
6335 **/
6336 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6337 {
6338 struct igb_adapter *adapter = q_vector->adapter;
6339 struct igb_ring *tx_ring = q_vector->tx.ring;
6340 struct igb_tx_buffer *tx_buffer;
6341 union e1000_adv_tx_desc *tx_desc;
6342 unsigned int total_bytes = 0, total_packets = 0;
6343 unsigned int budget = q_vector->tx.work_limit;
6344 unsigned int i = tx_ring->next_to_clean;
6345
6346 if (test_bit(__IGB_DOWN, &adapter->state))
6347 return true;
6348
6349 tx_buffer = &tx_ring->tx_buffer_info[i];
6350 tx_desc = IGB_TX_DESC(tx_ring, i);
6351 i -= tx_ring->count;
6352
6353 do {
6354 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6355
6356 /* if next_to_watch is not set then there is no work pending */
6357 if (!eop_desc)
6358 break;
6359
6360 /* prevent any other reads prior to eop_desc */
6361 read_barrier_depends();
6362
6363 /* if DD is not set pending work has not been completed */
6364 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6365 break;
6366
6367 /* clear next_to_watch to prevent false hangs */
6368 tx_buffer->next_to_watch = NULL;
6369
6370 /* update the statistics for this packet */
6371 total_bytes += tx_buffer->bytecount;
6372 total_packets += tx_buffer->gso_segs;
6373
6374 /* free the skb */
6375 dev_consume_skb_any(tx_buffer->skb);
6376
6377 /* unmap skb header data */
6378 dma_unmap_single(tx_ring->dev,
6379 dma_unmap_addr(tx_buffer, dma),
6380 dma_unmap_len(tx_buffer, len),
6381 DMA_TO_DEVICE);
6382
6383 /* clear tx_buffer data */
6384 tx_buffer->skb = NULL;
6385 dma_unmap_len_set(tx_buffer, len, 0);
6386
6387 /* clear last DMA location and unmap remaining buffers */
6388 while (tx_desc != eop_desc) {
6389 tx_buffer++;
6390 tx_desc++;
6391 i++;
6392 if (unlikely(!i)) {
6393 i -= tx_ring->count;
6394 tx_buffer = tx_ring->tx_buffer_info;
6395 tx_desc = IGB_TX_DESC(tx_ring, 0);
6396 }
6397
6398 /* unmap any remaining paged data */
6399 if (dma_unmap_len(tx_buffer, len)) {
6400 dma_unmap_page(tx_ring->dev,
6401 dma_unmap_addr(tx_buffer, dma),
6402 dma_unmap_len(tx_buffer, len),
6403 DMA_TO_DEVICE);
6404 dma_unmap_len_set(tx_buffer, len, 0);
6405 }
6406 }
6407
6408 /* move us one more past the eop_desc for start of next pkt */
6409 tx_buffer++;
6410 tx_desc++;
6411 i++;
6412 if (unlikely(!i)) {
6413 i -= tx_ring->count;
6414 tx_buffer = tx_ring->tx_buffer_info;
6415 tx_desc = IGB_TX_DESC(tx_ring, 0);
6416 }
6417
6418 /* issue prefetch for next Tx descriptor */
6419 prefetch(tx_desc);
6420
6421 /* update budget accounting */
6422 budget--;
6423 } while (likely(budget));
6424
6425 netdev_tx_completed_queue(txring_txq(tx_ring),
6426 total_packets, total_bytes);
6427 i += tx_ring->count;
6428 tx_ring->next_to_clean = i;
6429 u64_stats_update_begin(&tx_ring->tx_syncp);
6430 tx_ring->tx_stats.bytes += total_bytes;
6431 tx_ring->tx_stats.packets += total_packets;
6432 u64_stats_update_end(&tx_ring->tx_syncp);
6433 q_vector->tx.total_bytes += total_bytes;
6434 q_vector->tx.total_packets += total_packets;
6435
6436 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6437 struct e1000_hw *hw = &adapter->hw;
6438
6439 /* Detect a transmit hang in hardware, this serializes the
6440 * check with the clearing of time_stamp and movement of i
6441 */
6442 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6443 if (tx_buffer->next_to_watch &&
6444 time_after(jiffies, tx_buffer->time_stamp +
6445 (adapter->tx_timeout_factor * HZ)) &&
6446 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6447
6448 /* detected Tx unit hang */
6449 dev_err(tx_ring->dev,
6450 "Detected Tx Unit Hang\n"
6451 " Tx Queue <%d>\n"
6452 " TDH <%x>\n"
6453 " TDT <%x>\n"
6454 " next_to_use <%x>\n"
6455 " next_to_clean <%x>\n"
6456 "buffer_info[next_to_clean]\n"
6457 " time_stamp <%lx>\n"
6458 " next_to_watch <%p>\n"
6459 " jiffies <%lx>\n"
6460 " desc.status <%x>\n",
6461 tx_ring->queue_index,
6462 rd32(E1000_TDH(tx_ring->reg_idx)),
6463 readl(tx_ring->tail),
6464 tx_ring->next_to_use,
6465 tx_ring->next_to_clean,
6466 tx_buffer->time_stamp,
6467 tx_buffer->next_to_watch,
6468 jiffies,
6469 tx_buffer->next_to_watch->wb.status);
6470 netif_stop_subqueue(tx_ring->netdev,
6471 tx_ring->queue_index);
6472
6473 /* we are about to reset, no point in enabling stuff */
6474 return true;
6475 }
6476 }
6477
6478 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6479 if (unlikely(total_packets &&
6480 netif_carrier_ok(tx_ring->netdev) &&
6481 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6482 /* Make sure that anybody stopping the queue after this
6483 * sees the new next_to_clean.
6484 */
6485 smp_mb();
6486 if (__netif_subqueue_stopped(tx_ring->netdev,
6487 tx_ring->queue_index) &&
6488 !(test_bit(__IGB_DOWN, &adapter->state))) {
6489 netif_wake_subqueue(tx_ring->netdev,
6490 tx_ring->queue_index);
6491
6492 u64_stats_update_begin(&tx_ring->tx_syncp);
6493 tx_ring->tx_stats.restart_queue++;
6494 u64_stats_update_end(&tx_ring->tx_syncp);
6495 }
6496 }
6497
6498 return !!budget;
6499 }
6500
6501 /**
6502 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6503 * @rx_ring: rx descriptor ring to store buffers on
6504 * @old_buff: donor buffer to have page reused
6505 *
6506 * Synchronizes page for reuse by the adapter
6507 **/
6508 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6509 struct igb_rx_buffer *old_buff)
6510 {
6511 struct igb_rx_buffer *new_buff;
6512 u16 nta = rx_ring->next_to_alloc;
6513
6514 new_buff = &rx_ring->rx_buffer_info[nta];
6515
6516 /* update, and store next to alloc */
6517 nta++;
6518 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6519
6520 /* transfer page from old buffer to new buffer */
6521 *new_buff = *old_buff;
6522
6523 /* sync the buffer for use by the device */
6524 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6525 old_buff->page_offset,
6526 IGB_RX_BUFSZ,
6527 DMA_FROM_DEVICE);
6528 }
6529
6530 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6531 struct page *page,
6532 unsigned int truesize)
6533 {
6534 /* avoid re-using remote pages */
6535 if (unlikely(page_to_nid(page) != numa_node_id()))
6536 return false;
6537
6538 if (unlikely(page->pfmemalloc))
6539 return false;
6540
6541 #if (PAGE_SIZE < 8192)
6542 /* if we are only owner of page we can reuse it */
6543 if (unlikely(page_count(page) != 1))
6544 return false;
6545
6546 /* flip page offset to other buffer */
6547 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6548
6549 /* Even if we own the page, we are not allowed to use atomic_set()
6550 * This would break get_page_unless_zero() users.
6551 */
6552 atomic_inc(&page->_count);
6553 #else
6554 /* move offset up to the next cache line */
6555 rx_buffer->page_offset += truesize;
6556
6557 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6558 return false;
6559
6560 /* bump ref count on page before it is given to the stack */
6561 get_page(page);
6562 #endif
6563
6564 return true;
6565 }
6566
6567 /**
6568 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6569 * @rx_ring: rx descriptor ring to transact packets on
6570 * @rx_buffer: buffer containing page to add
6571 * @rx_desc: descriptor containing length of buffer written by hardware
6572 * @skb: sk_buff to place the data into
6573 *
6574 * This function will add the data contained in rx_buffer->page to the skb.
6575 * This is done either through a direct copy if the data in the buffer is
6576 * less than the skb header size, otherwise it will just attach the page as
6577 * a frag to the skb.
6578 *
6579 * The function will then update the page offset if necessary and return
6580 * true if the buffer can be reused by the adapter.
6581 **/
6582 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6583 struct igb_rx_buffer *rx_buffer,
6584 union e1000_adv_rx_desc *rx_desc,
6585 struct sk_buff *skb)
6586 {
6587 struct page *page = rx_buffer->page;
6588 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6589 #if (PAGE_SIZE < 8192)
6590 unsigned int truesize = IGB_RX_BUFSZ;
6591 #else
6592 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6593 #endif
6594
6595 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6596 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6597
6598 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6599 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6600 va += IGB_TS_HDR_LEN;
6601 size -= IGB_TS_HDR_LEN;
6602 }
6603
6604 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6605
6606 /* we can reuse buffer as-is, just make sure it is local */
6607 if (likely((page_to_nid(page) == numa_node_id()) &&
6608 !page->pfmemalloc))
6609 return true;
6610
6611 /* this page cannot be reused so discard it */
6612 put_page(page);
6613 return false;
6614 }
6615
6616 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6617 rx_buffer->page_offset, size, truesize);
6618
6619 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6620 }
6621
6622 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6623 union e1000_adv_rx_desc *rx_desc,
6624 struct sk_buff *skb)
6625 {
6626 struct igb_rx_buffer *rx_buffer;
6627 struct page *page;
6628
6629 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6630
6631 page = rx_buffer->page;
6632 prefetchw(page);
6633
6634 if (likely(!skb)) {
6635 void *page_addr = page_address(page) +
6636 rx_buffer->page_offset;
6637
6638 /* prefetch first cache line of first page */
6639 prefetch(page_addr);
6640 #if L1_CACHE_BYTES < 128
6641 prefetch(page_addr + L1_CACHE_BYTES);
6642 #endif
6643
6644 /* allocate a skb to store the frags */
6645 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
6646 if (unlikely(!skb)) {
6647 rx_ring->rx_stats.alloc_failed++;
6648 return NULL;
6649 }
6650
6651 /* we will be copying header into skb->data in
6652 * pskb_may_pull so it is in our interest to prefetch
6653 * it now to avoid a possible cache miss
6654 */
6655 prefetchw(skb->data);
6656 }
6657
6658 /* we are reusing so sync this buffer for CPU use */
6659 dma_sync_single_range_for_cpu(rx_ring->dev,
6660 rx_buffer->dma,
6661 rx_buffer->page_offset,
6662 IGB_RX_BUFSZ,
6663 DMA_FROM_DEVICE);
6664
6665 /* pull page into skb */
6666 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6667 /* hand second half of page back to the ring */
6668 igb_reuse_rx_page(rx_ring, rx_buffer);
6669 } else {
6670 /* we are not reusing the buffer so unmap it */
6671 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6672 PAGE_SIZE, DMA_FROM_DEVICE);
6673 }
6674
6675 /* clear contents of rx_buffer */
6676 rx_buffer->page = NULL;
6677
6678 return skb;
6679 }
6680
6681 static inline void igb_rx_checksum(struct igb_ring *ring,
6682 union e1000_adv_rx_desc *rx_desc,
6683 struct sk_buff *skb)
6684 {
6685 skb_checksum_none_assert(skb);
6686
6687 /* Ignore Checksum bit is set */
6688 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6689 return;
6690
6691 /* Rx checksum disabled via ethtool */
6692 if (!(ring->netdev->features & NETIF_F_RXCSUM))
6693 return;
6694
6695 /* TCP/UDP checksum error bit is set */
6696 if (igb_test_staterr(rx_desc,
6697 E1000_RXDEXT_STATERR_TCPE |
6698 E1000_RXDEXT_STATERR_IPE)) {
6699 /* work around errata with sctp packets where the TCPE aka
6700 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6701 * packets, (aka let the stack check the crc32c)
6702 */
6703 if (!((skb->len == 60) &&
6704 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6705 u64_stats_update_begin(&ring->rx_syncp);
6706 ring->rx_stats.csum_err++;
6707 u64_stats_update_end(&ring->rx_syncp);
6708 }
6709 /* let the stack verify checksum errors */
6710 return;
6711 }
6712 /* It must be a TCP or UDP packet with a valid checksum */
6713 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6714 E1000_RXD_STAT_UDPCS))
6715 skb->ip_summed = CHECKSUM_UNNECESSARY;
6716
6717 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6718 le32_to_cpu(rx_desc->wb.upper.status_error));
6719 }
6720
6721 static inline void igb_rx_hash(struct igb_ring *ring,
6722 union e1000_adv_rx_desc *rx_desc,
6723 struct sk_buff *skb)
6724 {
6725 if (ring->netdev->features & NETIF_F_RXHASH)
6726 skb_set_hash(skb,
6727 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6728 PKT_HASH_TYPE_L3);
6729 }
6730
6731 /**
6732 * igb_is_non_eop - process handling of non-EOP buffers
6733 * @rx_ring: Rx ring being processed
6734 * @rx_desc: Rx descriptor for current buffer
6735 * @skb: current socket buffer containing buffer in progress
6736 *
6737 * This function updates next to clean. If the buffer is an EOP buffer
6738 * this function exits returning false, otherwise it will place the
6739 * sk_buff in the next buffer to be chained and return true indicating
6740 * that this is in fact a non-EOP buffer.
6741 **/
6742 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6743 union e1000_adv_rx_desc *rx_desc)
6744 {
6745 u32 ntc = rx_ring->next_to_clean + 1;
6746
6747 /* fetch, update, and store next to clean */
6748 ntc = (ntc < rx_ring->count) ? ntc : 0;
6749 rx_ring->next_to_clean = ntc;
6750
6751 prefetch(IGB_RX_DESC(rx_ring, ntc));
6752
6753 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6754 return false;
6755
6756 return true;
6757 }
6758
6759 /**
6760 * igb_pull_tail - igb specific version of skb_pull_tail
6761 * @rx_ring: rx descriptor ring packet is being transacted on
6762 * @rx_desc: pointer to the EOP Rx descriptor
6763 * @skb: pointer to current skb being adjusted
6764 *
6765 * This function is an igb specific version of __pskb_pull_tail. The
6766 * main difference between this version and the original function is that
6767 * this function can make several assumptions about the state of things
6768 * that allow for significant optimizations versus the standard function.
6769 * As a result we can do things like drop a frag and maintain an accurate
6770 * truesize for the skb.
6771 */
6772 static void igb_pull_tail(struct igb_ring *rx_ring,
6773 union e1000_adv_rx_desc *rx_desc,
6774 struct sk_buff *skb)
6775 {
6776 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6777 unsigned char *va;
6778 unsigned int pull_len;
6779
6780 /* it is valid to use page_address instead of kmap since we are
6781 * working with pages allocated out of the lomem pool per
6782 * alloc_page(GFP_ATOMIC)
6783 */
6784 va = skb_frag_address(frag);
6785
6786 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6787 /* retrieve timestamp from buffer */
6788 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6789
6790 /* update pointers to remove timestamp header */
6791 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6792 frag->page_offset += IGB_TS_HDR_LEN;
6793 skb->data_len -= IGB_TS_HDR_LEN;
6794 skb->len -= IGB_TS_HDR_LEN;
6795
6796 /* move va to start of packet data */
6797 va += IGB_TS_HDR_LEN;
6798 }
6799
6800 /* we need the header to contain the greater of either ETH_HLEN or
6801 * 60 bytes if the skb->len is less than 60 for skb_pad.
6802 */
6803 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6804
6805 /* align pull length to size of long to optimize memcpy performance */
6806 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6807
6808 /* update all of the pointers */
6809 skb_frag_size_sub(frag, pull_len);
6810 frag->page_offset += pull_len;
6811 skb->data_len -= pull_len;
6812 skb->tail += pull_len;
6813 }
6814
6815 /**
6816 * igb_cleanup_headers - Correct corrupted or empty headers
6817 * @rx_ring: rx descriptor ring packet is being transacted on
6818 * @rx_desc: pointer to the EOP Rx descriptor
6819 * @skb: pointer to current skb being fixed
6820 *
6821 * Address the case where we are pulling data in on pages only
6822 * and as such no data is present in the skb header.
6823 *
6824 * In addition if skb is not at least 60 bytes we need to pad it so that
6825 * it is large enough to qualify as a valid Ethernet frame.
6826 *
6827 * Returns true if an error was encountered and skb was freed.
6828 **/
6829 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6830 union e1000_adv_rx_desc *rx_desc,
6831 struct sk_buff *skb)
6832 {
6833 if (unlikely((igb_test_staterr(rx_desc,
6834 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6835 struct net_device *netdev = rx_ring->netdev;
6836 if (!(netdev->features & NETIF_F_RXALL)) {
6837 dev_kfree_skb_any(skb);
6838 return true;
6839 }
6840 }
6841
6842 /* place header in linear portion of buffer */
6843 if (skb_is_nonlinear(skb))
6844 igb_pull_tail(rx_ring, rx_desc, skb);
6845
6846 /* if eth_skb_pad returns an error the skb was freed */
6847 if (eth_skb_pad(skb))
6848 return true;
6849
6850 return false;
6851 }
6852
6853 /**
6854 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6855 * @rx_ring: rx descriptor ring packet is being transacted on
6856 * @rx_desc: pointer to the EOP Rx descriptor
6857 * @skb: pointer to current skb being populated
6858 *
6859 * This function checks the ring, descriptor, and packet information in
6860 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6861 * other fields within the skb.
6862 **/
6863 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6864 union e1000_adv_rx_desc *rx_desc,
6865 struct sk_buff *skb)
6866 {
6867 struct net_device *dev = rx_ring->netdev;
6868
6869 igb_rx_hash(rx_ring, rx_desc, skb);
6870
6871 igb_rx_checksum(rx_ring, rx_desc, skb);
6872
6873 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6874 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6875 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
6876
6877 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6878 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6879 u16 vid;
6880
6881 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6882 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6883 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6884 else
6885 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6886
6887 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6888 }
6889
6890 skb_record_rx_queue(skb, rx_ring->queue_index);
6891
6892 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6893 }
6894
6895 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6896 {
6897 struct igb_ring *rx_ring = q_vector->rx.ring;
6898 struct sk_buff *skb = rx_ring->skb;
6899 unsigned int total_bytes = 0, total_packets = 0;
6900 u16 cleaned_count = igb_desc_unused(rx_ring);
6901
6902 while (likely(total_packets < budget)) {
6903 union e1000_adv_rx_desc *rx_desc;
6904
6905 /* return some buffers to hardware, one at a time is too slow */
6906 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6907 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6908 cleaned_count = 0;
6909 }
6910
6911 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6912
6913 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6914 break;
6915
6916 /* This memory barrier is needed to keep us from reading
6917 * any other fields out of the rx_desc until we know the
6918 * RXD_STAT_DD bit is set
6919 */
6920 rmb();
6921
6922 /* retrieve a buffer from the ring */
6923 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6924
6925 /* exit if we failed to retrieve a buffer */
6926 if (!skb)
6927 break;
6928
6929 cleaned_count++;
6930
6931 /* fetch next buffer in frame if non-eop */
6932 if (igb_is_non_eop(rx_ring, rx_desc))
6933 continue;
6934
6935 /* verify the packet layout is correct */
6936 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6937 skb = NULL;
6938 continue;
6939 }
6940
6941 /* probably a little skewed due to removing CRC */
6942 total_bytes += skb->len;
6943
6944 /* populate checksum, timestamp, VLAN, and protocol */
6945 igb_process_skb_fields(rx_ring, rx_desc, skb);
6946
6947 napi_gro_receive(&q_vector->napi, skb);
6948
6949 /* reset skb pointer */
6950 skb = NULL;
6951
6952 /* update budget accounting */
6953 total_packets++;
6954 }
6955
6956 /* place incomplete frames back on ring for completion */
6957 rx_ring->skb = skb;
6958
6959 u64_stats_update_begin(&rx_ring->rx_syncp);
6960 rx_ring->rx_stats.packets += total_packets;
6961 rx_ring->rx_stats.bytes += total_bytes;
6962 u64_stats_update_end(&rx_ring->rx_syncp);
6963 q_vector->rx.total_packets += total_packets;
6964 q_vector->rx.total_bytes += total_bytes;
6965
6966 if (cleaned_count)
6967 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6968
6969 return total_packets < budget;
6970 }
6971
6972 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6973 struct igb_rx_buffer *bi)
6974 {
6975 struct page *page = bi->page;
6976 dma_addr_t dma;
6977
6978 /* since we are recycling buffers we should seldom need to alloc */
6979 if (likely(page))
6980 return true;
6981
6982 /* alloc new page for storage */
6983 page = dev_alloc_page();
6984 if (unlikely(!page)) {
6985 rx_ring->rx_stats.alloc_failed++;
6986 return false;
6987 }
6988
6989 /* map page for use */
6990 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6991
6992 /* if mapping failed free memory back to system since
6993 * there isn't much point in holding memory we can't use
6994 */
6995 if (dma_mapping_error(rx_ring->dev, dma)) {
6996 __free_page(page);
6997
6998 rx_ring->rx_stats.alloc_failed++;
6999 return false;
7000 }
7001
7002 bi->dma = dma;
7003 bi->page = page;
7004 bi->page_offset = 0;
7005
7006 return true;
7007 }
7008
7009 /**
7010 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7011 * @adapter: address of board private structure
7012 **/
7013 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
7014 {
7015 union e1000_adv_rx_desc *rx_desc;
7016 struct igb_rx_buffer *bi;
7017 u16 i = rx_ring->next_to_use;
7018
7019 /* nothing to do */
7020 if (!cleaned_count)
7021 return;
7022
7023 rx_desc = IGB_RX_DESC(rx_ring, i);
7024 bi = &rx_ring->rx_buffer_info[i];
7025 i -= rx_ring->count;
7026
7027 do {
7028 if (!igb_alloc_mapped_page(rx_ring, bi))
7029 break;
7030
7031 /* Refresh the desc even if buffer_addrs didn't change
7032 * because each write-back erases this info.
7033 */
7034 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
7035
7036 rx_desc++;
7037 bi++;
7038 i++;
7039 if (unlikely(!i)) {
7040 rx_desc = IGB_RX_DESC(rx_ring, 0);
7041 bi = rx_ring->rx_buffer_info;
7042 i -= rx_ring->count;
7043 }
7044
7045 /* clear the hdr_addr for the next_to_use descriptor */
7046 rx_desc->read.hdr_addr = 0;
7047
7048 cleaned_count--;
7049 } while (cleaned_count);
7050
7051 i += rx_ring->count;
7052
7053 if (rx_ring->next_to_use != i) {
7054 /* record the next descriptor to use */
7055 rx_ring->next_to_use = i;
7056
7057 /* update next to alloc since we have filled the ring */
7058 rx_ring->next_to_alloc = i;
7059
7060 /* Force memory writes to complete before letting h/w
7061 * know there are new descriptors to fetch. (Only
7062 * applicable for weak-ordered memory model archs,
7063 * such as IA-64).
7064 */
7065 wmb();
7066 writel(i, rx_ring->tail);
7067 }
7068 }
7069
7070 /**
7071 * igb_mii_ioctl -
7072 * @netdev:
7073 * @ifreq:
7074 * @cmd:
7075 **/
7076 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7077 {
7078 struct igb_adapter *adapter = netdev_priv(netdev);
7079 struct mii_ioctl_data *data = if_mii(ifr);
7080
7081 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7082 return -EOPNOTSUPP;
7083
7084 switch (cmd) {
7085 case SIOCGMIIPHY:
7086 data->phy_id = adapter->hw.phy.addr;
7087 break;
7088 case SIOCGMIIREG:
7089 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7090 &data->val_out))
7091 return -EIO;
7092 break;
7093 case SIOCSMIIREG:
7094 default:
7095 return -EOPNOTSUPP;
7096 }
7097 return 0;
7098 }
7099
7100 /**
7101 * igb_ioctl -
7102 * @netdev:
7103 * @ifreq:
7104 * @cmd:
7105 **/
7106 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7107 {
7108 switch (cmd) {
7109 case SIOCGMIIPHY:
7110 case SIOCGMIIREG:
7111 case SIOCSMIIREG:
7112 return igb_mii_ioctl(netdev, ifr, cmd);
7113 case SIOCGHWTSTAMP:
7114 return igb_ptp_get_ts_config(netdev, ifr);
7115 case SIOCSHWTSTAMP:
7116 return igb_ptp_set_ts_config(netdev, ifr);
7117 default:
7118 return -EOPNOTSUPP;
7119 }
7120 }
7121
7122 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7123 {
7124 struct igb_adapter *adapter = hw->back;
7125
7126 pci_read_config_word(adapter->pdev, reg, value);
7127 }
7128
7129 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7130 {
7131 struct igb_adapter *adapter = hw->back;
7132
7133 pci_write_config_word(adapter->pdev, reg, *value);
7134 }
7135
7136 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7137 {
7138 struct igb_adapter *adapter = hw->back;
7139
7140 if (pcie_capability_read_word(adapter->pdev, reg, value))
7141 return -E1000_ERR_CONFIG;
7142
7143 return 0;
7144 }
7145
7146 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7147 {
7148 struct igb_adapter *adapter = hw->back;
7149
7150 if (pcie_capability_write_word(adapter->pdev, reg, *value))
7151 return -E1000_ERR_CONFIG;
7152
7153 return 0;
7154 }
7155
7156 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
7157 {
7158 struct igb_adapter *adapter = netdev_priv(netdev);
7159 struct e1000_hw *hw = &adapter->hw;
7160 u32 ctrl, rctl;
7161 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
7162
7163 if (enable) {
7164 /* enable VLAN tag insert/strip */
7165 ctrl = rd32(E1000_CTRL);
7166 ctrl |= E1000_CTRL_VME;
7167 wr32(E1000_CTRL, ctrl);
7168
7169 /* Disable CFI check */
7170 rctl = rd32(E1000_RCTL);
7171 rctl &= ~E1000_RCTL_CFIEN;
7172 wr32(E1000_RCTL, rctl);
7173 } else {
7174 /* disable VLAN tag insert/strip */
7175 ctrl = rd32(E1000_CTRL);
7176 ctrl &= ~E1000_CTRL_VME;
7177 wr32(E1000_CTRL, ctrl);
7178 }
7179
7180 igb_rlpml_set(adapter);
7181 }
7182
7183 static int igb_vlan_rx_add_vid(struct net_device *netdev,
7184 __be16 proto, u16 vid)
7185 {
7186 struct igb_adapter *adapter = netdev_priv(netdev);
7187 struct e1000_hw *hw = &adapter->hw;
7188 int pf_id = adapter->vfs_allocated_count;
7189
7190 /* attempt to add filter to vlvf array */
7191 igb_vlvf_set(adapter, vid, true, pf_id);
7192
7193 /* add the filter since PF can receive vlans w/o entry in vlvf */
7194 igb_vfta_set(hw, vid, true);
7195
7196 set_bit(vid, adapter->active_vlans);
7197
7198 return 0;
7199 }
7200
7201 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7202 __be16 proto, u16 vid)
7203 {
7204 struct igb_adapter *adapter = netdev_priv(netdev);
7205 struct e1000_hw *hw = &adapter->hw;
7206 int pf_id = adapter->vfs_allocated_count;
7207 s32 err;
7208
7209 /* remove vlan from VLVF table array */
7210 err = igb_vlvf_set(adapter, vid, false, pf_id);
7211
7212 /* if vid was not present in VLVF just remove it from table */
7213 if (err)
7214 igb_vfta_set(hw, vid, false);
7215
7216 clear_bit(vid, adapter->active_vlans);
7217
7218 return 0;
7219 }
7220
7221 static void igb_restore_vlan(struct igb_adapter *adapter)
7222 {
7223 u16 vid;
7224
7225 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7226
7227 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7228 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7229 }
7230
7231 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7232 {
7233 struct pci_dev *pdev = adapter->pdev;
7234 struct e1000_mac_info *mac = &adapter->hw.mac;
7235
7236 mac->autoneg = 0;
7237
7238 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7239 * for the switch() below to work
7240 */
7241 if ((spd & 1) || (dplx & ~1))
7242 goto err_inval;
7243
7244 /* Fiber NIC's only allow 1000 gbps Full duplex
7245 * and 100Mbps Full duplex for 100baseFx sfp
7246 */
7247 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7248 switch (spd + dplx) {
7249 case SPEED_10 + DUPLEX_HALF:
7250 case SPEED_10 + DUPLEX_FULL:
7251 case SPEED_100 + DUPLEX_HALF:
7252 goto err_inval;
7253 default:
7254 break;
7255 }
7256 }
7257
7258 switch (spd + dplx) {
7259 case SPEED_10 + DUPLEX_HALF:
7260 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7261 break;
7262 case SPEED_10 + DUPLEX_FULL:
7263 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7264 break;
7265 case SPEED_100 + DUPLEX_HALF:
7266 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7267 break;
7268 case SPEED_100 + DUPLEX_FULL:
7269 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7270 break;
7271 case SPEED_1000 + DUPLEX_FULL:
7272 mac->autoneg = 1;
7273 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7274 break;
7275 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7276 default:
7277 goto err_inval;
7278 }
7279
7280 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7281 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7282
7283 return 0;
7284
7285 err_inval:
7286 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7287 return -EINVAL;
7288 }
7289
7290 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7291 bool runtime)
7292 {
7293 struct net_device *netdev = pci_get_drvdata(pdev);
7294 struct igb_adapter *adapter = netdev_priv(netdev);
7295 struct e1000_hw *hw = &adapter->hw;
7296 u32 ctrl, rctl, status;
7297 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7298 #ifdef CONFIG_PM
7299 int retval = 0;
7300 #endif
7301
7302 netif_device_detach(netdev);
7303
7304 if (netif_running(netdev))
7305 __igb_close(netdev, true);
7306
7307 igb_clear_interrupt_scheme(adapter);
7308
7309 #ifdef CONFIG_PM
7310 retval = pci_save_state(pdev);
7311 if (retval)
7312 return retval;
7313 #endif
7314
7315 status = rd32(E1000_STATUS);
7316 if (status & E1000_STATUS_LU)
7317 wufc &= ~E1000_WUFC_LNKC;
7318
7319 if (wufc) {
7320 igb_setup_rctl(adapter);
7321 igb_set_rx_mode(netdev);
7322
7323 /* turn on all-multi mode if wake on multicast is enabled */
7324 if (wufc & E1000_WUFC_MC) {
7325 rctl = rd32(E1000_RCTL);
7326 rctl |= E1000_RCTL_MPE;
7327 wr32(E1000_RCTL, rctl);
7328 }
7329
7330 ctrl = rd32(E1000_CTRL);
7331 /* advertise wake from D3Cold */
7332 #define E1000_CTRL_ADVD3WUC 0x00100000
7333 /* phy power management enable */
7334 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7335 ctrl |= E1000_CTRL_ADVD3WUC;
7336 wr32(E1000_CTRL, ctrl);
7337
7338 /* Allow time for pending master requests to run */
7339 igb_disable_pcie_master(hw);
7340
7341 wr32(E1000_WUC, E1000_WUC_PME_EN);
7342 wr32(E1000_WUFC, wufc);
7343 } else {
7344 wr32(E1000_WUC, 0);
7345 wr32(E1000_WUFC, 0);
7346 }
7347
7348 *enable_wake = wufc || adapter->en_mng_pt;
7349 if (!*enable_wake)
7350 igb_power_down_link(adapter);
7351 else
7352 igb_power_up_link(adapter);
7353
7354 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7355 * would have already happened in close and is redundant.
7356 */
7357 igb_release_hw_control(adapter);
7358
7359 pci_disable_device(pdev);
7360
7361 return 0;
7362 }
7363
7364 #ifdef CONFIG_PM
7365 #ifdef CONFIG_PM_SLEEP
7366 static int igb_suspend(struct device *dev)
7367 {
7368 int retval;
7369 bool wake;
7370 struct pci_dev *pdev = to_pci_dev(dev);
7371
7372 retval = __igb_shutdown(pdev, &wake, 0);
7373 if (retval)
7374 return retval;
7375
7376 if (wake) {
7377 pci_prepare_to_sleep(pdev);
7378 } else {
7379 pci_wake_from_d3(pdev, false);
7380 pci_set_power_state(pdev, PCI_D3hot);
7381 }
7382
7383 return 0;
7384 }
7385 #endif /* CONFIG_PM_SLEEP */
7386
7387 static int igb_resume(struct device *dev)
7388 {
7389 struct pci_dev *pdev = to_pci_dev(dev);
7390 struct net_device *netdev = pci_get_drvdata(pdev);
7391 struct igb_adapter *adapter = netdev_priv(netdev);
7392 struct e1000_hw *hw = &adapter->hw;
7393 u32 err;
7394
7395 pci_set_power_state(pdev, PCI_D0);
7396 pci_restore_state(pdev);
7397 pci_save_state(pdev);
7398
7399 if (!pci_device_is_present(pdev))
7400 return -ENODEV;
7401 err = pci_enable_device_mem(pdev);
7402 if (err) {
7403 dev_err(&pdev->dev,
7404 "igb: Cannot enable PCI device from suspend\n");
7405 return err;
7406 }
7407 pci_set_master(pdev);
7408
7409 pci_enable_wake(pdev, PCI_D3hot, 0);
7410 pci_enable_wake(pdev, PCI_D3cold, 0);
7411
7412 if (igb_init_interrupt_scheme(adapter, true)) {
7413 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7414 return -ENOMEM;
7415 }
7416
7417 igb_reset(adapter);
7418
7419 /* let the f/w know that the h/w is now under the control of the
7420 * driver.
7421 */
7422 igb_get_hw_control(adapter);
7423
7424 wr32(E1000_WUS, ~0);
7425
7426 if (netdev->flags & IFF_UP) {
7427 rtnl_lock();
7428 err = __igb_open(netdev, true);
7429 rtnl_unlock();
7430 if (err)
7431 return err;
7432 }
7433
7434 netif_device_attach(netdev);
7435 return 0;
7436 }
7437
7438 static int igb_runtime_idle(struct device *dev)
7439 {
7440 struct pci_dev *pdev = to_pci_dev(dev);
7441 struct net_device *netdev = pci_get_drvdata(pdev);
7442 struct igb_adapter *adapter = netdev_priv(netdev);
7443
7444 if (!igb_has_link(adapter))
7445 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7446
7447 return -EBUSY;
7448 }
7449
7450 static int igb_runtime_suspend(struct device *dev)
7451 {
7452 struct pci_dev *pdev = to_pci_dev(dev);
7453 int retval;
7454 bool wake;
7455
7456 retval = __igb_shutdown(pdev, &wake, 1);
7457 if (retval)
7458 return retval;
7459
7460 if (wake) {
7461 pci_prepare_to_sleep(pdev);
7462 } else {
7463 pci_wake_from_d3(pdev, false);
7464 pci_set_power_state(pdev, PCI_D3hot);
7465 }
7466
7467 return 0;
7468 }
7469
7470 static int igb_runtime_resume(struct device *dev)
7471 {
7472 return igb_resume(dev);
7473 }
7474 #endif /* CONFIG_PM */
7475
7476 static void igb_shutdown(struct pci_dev *pdev)
7477 {
7478 bool wake;
7479
7480 __igb_shutdown(pdev, &wake, 0);
7481
7482 if (system_state == SYSTEM_POWER_OFF) {
7483 pci_wake_from_d3(pdev, wake);
7484 pci_set_power_state(pdev, PCI_D3hot);
7485 }
7486 }
7487
7488 #ifdef CONFIG_PCI_IOV
7489 static int igb_sriov_reinit(struct pci_dev *dev)
7490 {
7491 struct net_device *netdev = pci_get_drvdata(dev);
7492 struct igb_adapter *adapter = netdev_priv(netdev);
7493 struct pci_dev *pdev = adapter->pdev;
7494
7495 rtnl_lock();
7496
7497 if (netif_running(netdev))
7498 igb_close(netdev);
7499 else
7500 igb_reset(adapter);
7501
7502 igb_clear_interrupt_scheme(adapter);
7503
7504 igb_init_queue_configuration(adapter);
7505
7506 if (igb_init_interrupt_scheme(adapter, true)) {
7507 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7508 return -ENOMEM;
7509 }
7510
7511 if (netif_running(netdev))
7512 igb_open(netdev);
7513
7514 rtnl_unlock();
7515
7516 return 0;
7517 }
7518
7519 static int igb_pci_disable_sriov(struct pci_dev *dev)
7520 {
7521 int err = igb_disable_sriov(dev);
7522
7523 if (!err)
7524 err = igb_sriov_reinit(dev);
7525
7526 return err;
7527 }
7528
7529 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7530 {
7531 int err = igb_enable_sriov(dev, num_vfs);
7532
7533 if (err)
7534 goto out;
7535
7536 err = igb_sriov_reinit(dev);
7537 if (!err)
7538 return num_vfs;
7539
7540 out:
7541 return err;
7542 }
7543
7544 #endif
7545 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7546 {
7547 #ifdef CONFIG_PCI_IOV
7548 if (num_vfs == 0)
7549 return igb_pci_disable_sriov(dev);
7550 else
7551 return igb_pci_enable_sriov(dev, num_vfs);
7552 #endif
7553 return 0;
7554 }
7555
7556 #ifdef CONFIG_NET_POLL_CONTROLLER
7557 /* Polling 'interrupt' - used by things like netconsole to send skbs
7558 * without having to re-enable interrupts. It's not called while
7559 * the interrupt routine is executing.
7560 */
7561 static void igb_netpoll(struct net_device *netdev)
7562 {
7563 struct igb_adapter *adapter = netdev_priv(netdev);
7564 struct e1000_hw *hw = &adapter->hw;
7565 struct igb_q_vector *q_vector;
7566 int i;
7567
7568 for (i = 0; i < adapter->num_q_vectors; i++) {
7569 q_vector = adapter->q_vector[i];
7570 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7571 wr32(E1000_EIMC, q_vector->eims_value);
7572 else
7573 igb_irq_disable(adapter);
7574 napi_schedule(&q_vector->napi);
7575 }
7576 }
7577 #endif /* CONFIG_NET_POLL_CONTROLLER */
7578
7579 /**
7580 * igb_io_error_detected - called when PCI error is detected
7581 * @pdev: Pointer to PCI device
7582 * @state: The current pci connection state
7583 *
7584 * This function is called after a PCI bus error affecting
7585 * this device has been detected.
7586 **/
7587 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7588 pci_channel_state_t state)
7589 {
7590 struct net_device *netdev = pci_get_drvdata(pdev);
7591 struct igb_adapter *adapter = netdev_priv(netdev);
7592
7593 netif_device_detach(netdev);
7594
7595 if (state == pci_channel_io_perm_failure)
7596 return PCI_ERS_RESULT_DISCONNECT;
7597
7598 if (netif_running(netdev))
7599 igb_down(adapter);
7600 pci_disable_device(pdev);
7601
7602 /* Request a slot slot reset. */
7603 return PCI_ERS_RESULT_NEED_RESET;
7604 }
7605
7606 /**
7607 * igb_io_slot_reset - called after the pci bus has been reset.
7608 * @pdev: Pointer to PCI device
7609 *
7610 * Restart the card from scratch, as if from a cold-boot. Implementation
7611 * resembles the first-half of the igb_resume routine.
7612 **/
7613 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7614 {
7615 struct net_device *netdev = pci_get_drvdata(pdev);
7616 struct igb_adapter *adapter = netdev_priv(netdev);
7617 struct e1000_hw *hw = &adapter->hw;
7618 pci_ers_result_t result;
7619 int err;
7620
7621 if (pci_enable_device_mem(pdev)) {
7622 dev_err(&pdev->dev,
7623 "Cannot re-enable PCI device after reset.\n");
7624 result = PCI_ERS_RESULT_DISCONNECT;
7625 } else {
7626 pci_set_master(pdev);
7627 pci_restore_state(pdev);
7628 pci_save_state(pdev);
7629
7630 pci_enable_wake(pdev, PCI_D3hot, 0);
7631 pci_enable_wake(pdev, PCI_D3cold, 0);
7632
7633 igb_reset(adapter);
7634 wr32(E1000_WUS, ~0);
7635 result = PCI_ERS_RESULT_RECOVERED;
7636 }
7637
7638 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7639 if (err) {
7640 dev_err(&pdev->dev,
7641 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7642 err);
7643 /* non-fatal, continue */
7644 }
7645
7646 return result;
7647 }
7648
7649 /**
7650 * igb_io_resume - called when traffic can start flowing again.
7651 * @pdev: Pointer to PCI device
7652 *
7653 * This callback is called when the error recovery driver tells us that
7654 * its OK to resume normal operation. Implementation resembles the
7655 * second-half of the igb_resume routine.
7656 */
7657 static void igb_io_resume(struct pci_dev *pdev)
7658 {
7659 struct net_device *netdev = pci_get_drvdata(pdev);
7660 struct igb_adapter *adapter = netdev_priv(netdev);
7661
7662 if (netif_running(netdev)) {
7663 if (igb_up(adapter)) {
7664 dev_err(&pdev->dev, "igb_up failed after reset\n");
7665 return;
7666 }
7667 }
7668
7669 netif_device_attach(netdev);
7670
7671 /* let the f/w know that the h/w is now under the control of the
7672 * driver.
7673 */
7674 igb_get_hw_control(adapter);
7675 }
7676
7677 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7678 u8 qsel)
7679 {
7680 u32 rar_low, rar_high;
7681 struct e1000_hw *hw = &adapter->hw;
7682
7683 /* HW expects these in little endian so we reverse the byte order
7684 * from network order (big endian) to little endian
7685 */
7686 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7687 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7688 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7689
7690 /* Indicate to hardware the Address is Valid. */
7691 rar_high |= E1000_RAH_AV;
7692
7693 if (hw->mac.type == e1000_82575)
7694 rar_high |= E1000_RAH_POOL_1 * qsel;
7695 else
7696 rar_high |= E1000_RAH_POOL_1 << qsel;
7697
7698 wr32(E1000_RAL(index), rar_low);
7699 wrfl();
7700 wr32(E1000_RAH(index), rar_high);
7701 wrfl();
7702 }
7703
7704 static int igb_set_vf_mac(struct igb_adapter *adapter,
7705 int vf, unsigned char *mac_addr)
7706 {
7707 struct e1000_hw *hw = &adapter->hw;
7708 /* VF MAC addresses start at end of receive addresses and moves
7709 * towards the first, as a result a collision should not be possible
7710 */
7711 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7712
7713 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7714
7715 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7716
7717 return 0;
7718 }
7719
7720 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7721 {
7722 struct igb_adapter *adapter = netdev_priv(netdev);
7723 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7724 return -EINVAL;
7725 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7726 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7727 dev_info(&adapter->pdev->dev,
7728 "Reload the VF driver to make this change effective.");
7729 if (test_bit(__IGB_DOWN, &adapter->state)) {
7730 dev_warn(&adapter->pdev->dev,
7731 "The VF MAC address has been set, but the PF device is not up.\n");
7732 dev_warn(&adapter->pdev->dev,
7733 "Bring the PF device up before attempting to use the VF device.\n");
7734 }
7735 return igb_set_vf_mac(adapter, vf, mac);
7736 }
7737
7738 static int igb_link_mbps(int internal_link_speed)
7739 {
7740 switch (internal_link_speed) {
7741 case SPEED_100:
7742 return 100;
7743 case SPEED_1000:
7744 return 1000;
7745 default:
7746 return 0;
7747 }
7748 }
7749
7750 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7751 int link_speed)
7752 {
7753 int rf_dec, rf_int;
7754 u32 bcnrc_val;
7755
7756 if (tx_rate != 0) {
7757 /* Calculate the rate factor values to set */
7758 rf_int = link_speed / tx_rate;
7759 rf_dec = (link_speed - (rf_int * tx_rate));
7760 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7761 tx_rate;
7762
7763 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7764 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7765 E1000_RTTBCNRC_RF_INT_MASK);
7766 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7767 } else {
7768 bcnrc_val = 0;
7769 }
7770
7771 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7772 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7773 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7774 */
7775 wr32(E1000_RTTBCNRM, 0x14);
7776 wr32(E1000_RTTBCNRC, bcnrc_val);
7777 }
7778
7779 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7780 {
7781 int actual_link_speed, i;
7782 bool reset_rate = false;
7783
7784 /* VF TX rate limit was not set or not supported */
7785 if ((adapter->vf_rate_link_speed == 0) ||
7786 (adapter->hw.mac.type != e1000_82576))
7787 return;
7788
7789 actual_link_speed = igb_link_mbps(adapter->link_speed);
7790 if (actual_link_speed != adapter->vf_rate_link_speed) {
7791 reset_rate = true;
7792 adapter->vf_rate_link_speed = 0;
7793 dev_info(&adapter->pdev->dev,
7794 "Link speed has been changed. VF Transmit rate is disabled\n");
7795 }
7796
7797 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7798 if (reset_rate)
7799 adapter->vf_data[i].tx_rate = 0;
7800
7801 igb_set_vf_rate_limit(&adapter->hw, i,
7802 adapter->vf_data[i].tx_rate,
7803 actual_link_speed);
7804 }
7805 }
7806
7807 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7808 int min_tx_rate, int max_tx_rate)
7809 {
7810 struct igb_adapter *adapter = netdev_priv(netdev);
7811 struct e1000_hw *hw = &adapter->hw;
7812 int actual_link_speed;
7813
7814 if (hw->mac.type != e1000_82576)
7815 return -EOPNOTSUPP;
7816
7817 if (min_tx_rate)
7818 return -EINVAL;
7819
7820 actual_link_speed = igb_link_mbps(adapter->link_speed);
7821 if ((vf >= adapter->vfs_allocated_count) ||
7822 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7823 (max_tx_rate < 0) ||
7824 (max_tx_rate > actual_link_speed))
7825 return -EINVAL;
7826
7827 adapter->vf_rate_link_speed = actual_link_speed;
7828 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7829 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
7830
7831 return 0;
7832 }
7833
7834 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7835 bool setting)
7836 {
7837 struct igb_adapter *adapter = netdev_priv(netdev);
7838 struct e1000_hw *hw = &adapter->hw;
7839 u32 reg_val, reg_offset;
7840
7841 if (!adapter->vfs_allocated_count)
7842 return -EOPNOTSUPP;
7843
7844 if (vf >= adapter->vfs_allocated_count)
7845 return -EINVAL;
7846
7847 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7848 reg_val = rd32(reg_offset);
7849 if (setting)
7850 reg_val |= ((1 << vf) |
7851 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7852 else
7853 reg_val &= ~((1 << vf) |
7854 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7855 wr32(reg_offset, reg_val);
7856
7857 adapter->vf_data[vf].spoofchk_enabled = setting;
7858 return 0;
7859 }
7860
7861 static int igb_ndo_get_vf_config(struct net_device *netdev,
7862 int vf, struct ifla_vf_info *ivi)
7863 {
7864 struct igb_adapter *adapter = netdev_priv(netdev);
7865 if (vf >= adapter->vfs_allocated_count)
7866 return -EINVAL;
7867 ivi->vf = vf;
7868 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7869 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7870 ivi->min_tx_rate = 0;
7871 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7872 ivi->qos = adapter->vf_data[vf].pf_qos;
7873 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7874 return 0;
7875 }
7876
7877 static void igb_vmm_control(struct igb_adapter *adapter)
7878 {
7879 struct e1000_hw *hw = &adapter->hw;
7880 u32 reg;
7881
7882 switch (hw->mac.type) {
7883 case e1000_82575:
7884 case e1000_i210:
7885 case e1000_i211:
7886 case e1000_i354:
7887 default:
7888 /* replication is not supported for 82575 */
7889 return;
7890 case e1000_82576:
7891 /* notify HW that the MAC is adding vlan tags */
7892 reg = rd32(E1000_DTXCTL);
7893 reg |= E1000_DTXCTL_VLAN_ADDED;
7894 wr32(E1000_DTXCTL, reg);
7895 /* Fall through */
7896 case e1000_82580:
7897 /* enable replication vlan tag stripping */
7898 reg = rd32(E1000_RPLOLR);
7899 reg |= E1000_RPLOLR_STRVLAN;
7900 wr32(E1000_RPLOLR, reg);
7901 /* Fall through */
7902 case e1000_i350:
7903 /* none of the above registers are supported by i350 */
7904 break;
7905 }
7906
7907 if (adapter->vfs_allocated_count) {
7908 igb_vmdq_set_loopback_pf(hw, true);
7909 igb_vmdq_set_replication_pf(hw, true);
7910 igb_vmdq_set_anti_spoofing_pf(hw, true,
7911 adapter->vfs_allocated_count);
7912 } else {
7913 igb_vmdq_set_loopback_pf(hw, false);
7914 igb_vmdq_set_replication_pf(hw, false);
7915 }
7916 }
7917
7918 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7919 {
7920 struct e1000_hw *hw = &adapter->hw;
7921 u32 dmac_thr;
7922 u16 hwm;
7923
7924 if (hw->mac.type > e1000_82580) {
7925 if (adapter->flags & IGB_FLAG_DMAC) {
7926 u32 reg;
7927
7928 /* force threshold to 0. */
7929 wr32(E1000_DMCTXTH, 0);
7930
7931 /* DMA Coalescing high water mark needs to be greater
7932 * than the Rx threshold. Set hwm to PBA - max frame
7933 * size in 16B units, capping it at PBA - 6KB.
7934 */
7935 hwm = 64 * pba - adapter->max_frame_size / 16;
7936 if (hwm < 64 * (pba - 6))
7937 hwm = 64 * (pba - 6);
7938 reg = rd32(E1000_FCRTC);
7939 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7940 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7941 & E1000_FCRTC_RTH_COAL_MASK);
7942 wr32(E1000_FCRTC, reg);
7943
7944 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7945 * frame size, capping it at PBA - 10KB.
7946 */
7947 dmac_thr = pba - adapter->max_frame_size / 512;
7948 if (dmac_thr < pba - 10)
7949 dmac_thr = pba - 10;
7950 reg = rd32(E1000_DMACR);
7951 reg &= ~E1000_DMACR_DMACTHR_MASK;
7952 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7953 & E1000_DMACR_DMACTHR_MASK);
7954
7955 /* transition to L0x or L1 if available..*/
7956 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7957
7958 /* watchdog timer= +-1000 usec in 32usec intervals */
7959 reg |= (1000 >> 5);
7960
7961 /* Disable BMC-to-OS Watchdog Enable */
7962 if (hw->mac.type != e1000_i354)
7963 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7964
7965 wr32(E1000_DMACR, reg);
7966
7967 /* no lower threshold to disable
7968 * coalescing(smart fifb)-UTRESH=0
7969 */
7970 wr32(E1000_DMCRTRH, 0);
7971
7972 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7973
7974 wr32(E1000_DMCTLX, reg);
7975
7976 /* free space in tx packet buffer to wake from
7977 * DMA coal
7978 */
7979 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7980 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7981
7982 /* make low power state decision controlled
7983 * by DMA coal
7984 */
7985 reg = rd32(E1000_PCIEMISC);
7986 reg &= ~E1000_PCIEMISC_LX_DECISION;
7987 wr32(E1000_PCIEMISC, reg);
7988 } /* endif adapter->dmac is not disabled */
7989 } else if (hw->mac.type == e1000_82580) {
7990 u32 reg = rd32(E1000_PCIEMISC);
7991
7992 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7993 wr32(E1000_DMACR, 0);
7994 }
7995 }
7996
7997 /**
7998 * igb_read_i2c_byte - Reads 8 bit word over I2C
7999 * @hw: pointer to hardware structure
8000 * @byte_offset: byte offset to read
8001 * @dev_addr: device address
8002 * @data: value read
8003 *
8004 * Performs byte read operation over I2C interface at
8005 * a specified device address.
8006 **/
8007 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8008 u8 dev_addr, u8 *data)
8009 {
8010 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8011 struct i2c_client *this_client = adapter->i2c_client;
8012 s32 status;
8013 u16 swfw_mask = 0;
8014
8015 if (!this_client)
8016 return E1000_ERR_I2C;
8017
8018 swfw_mask = E1000_SWFW_PHY0_SM;
8019
8020 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8021 return E1000_ERR_SWFW_SYNC;
8022
8023 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8024 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8025
8026 if (status < 0)
8027 return E1000_ERR_I2C;
8028 else {
8029 *data = status;
8030 return 0;
8031 }
8032 }
8033
8034 /**
8035 * igb_write_i2c_byte - Writes 8 bit word over I2C
8036 * @hw: pointer to hardware structure
8037 * @byte_offset: byte offset to write
8038 * @dev_addr: device address
8039 * @data: value to write
8040 *
8041 * Performs byte write operation over I2C interface at
8042 * a specified device address.
8043 **/
8044 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
8045 u8 dev_addr, u8 data)
8046 {
8047 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
8048 struct i2c_client *this_client = adapter->i2c_client;
8049 s32 status;
8050 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8051
8052 if (!this_client)
8053 return E1000_ERR_I2C;
8054
8055 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
8056 return E1000_ERR_SWFW_SYNC;
8057 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8058 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8059
8060 if (status)
8061 return E1000_ERR_I2C;
8062 else
8063 return 0;
8064
8065 }
8066
8067 int igb_reinit_queues(struct igb_adapter *adapter)
8068 {
8069 struct net_device *netdev = adapter->netdev;
8070 struct pci_dev *pdev = adapter->pdev;
8071 int err = 0;
8072
8073 if (netif_running(netdev))
8074 igb_close(netdev);
8075
8076 igb_reset_interrupt_capability(adapter);
8077
8078 if (igb_init_interrupt_scheme(adapter, true)) {
8079 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8080 return -ENOMEM;
8081 }
8082
8083 if (netif_running(netdev))
8084 err = igb_open(netdev);
8085
8086 return err;
8087 }
8088 /* igb_main.c */
Linux kernel - Deliverables
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