2 * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
4 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/pci.h>
23 #include <linux/ptp_classify.h>
27 #define INCVALUE_MASK 0x7fffffff
28 #define ISGN 0x80000000
31 * The 82580 timesync updates the system timer every 8ns by 8ns,
32 * and this update value cannot be reprogrammed.
34 * Neither the 82576 nor the 82580 offer registers wide enough to hold
35 * nanoseconds time values for very long. For the 82580, SYSTIM always
36 * counts nanoseconds, but the upper 24 bits are not availible. The
37 * frequency is adjusted by changing the 32 bit fractional nanoseconds
40 * For the 82576, the SYSTIM register time unit is affect by the
41 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
42 * field are needed to provide the nominal 16 nanosecond period,
43 * leaving 19 bits for fractional nanoseconds.
45 * We scale the NIC clock cycle by a large factor so that relatively
46 * small clock corrections can be added or subtracted at each clock
47 * tick. The drawbacks of a large factor are a) that the clock
48 * register overflows more quickly (not such a big deal) and b) that
49 * the increment per tick has to fit into 24 bits. As a result we
50 * need to use a shift of 19 so we can fit a value of 16 into the
55 * +--------------+ +---+---+------+
56 * 82576 | 32 | | 8 | 5 | 19 |
57 * +--------------+ +---+---+------+
58 * \________ 45 bits _______/ fract
60 * +----------+---+ +--------------+
61 * 82580 | 24 | 8 | | 32 |
62 * +----------+---+ +--------------+
63 * reserved \______ 40 bits _____/
66 * The 45 bit 82576 SYSTIM overflows every
67 * 2^45 * 10^-9 / 3600 = 9.77 hours.
69 * The 40 bit 82580 SYSTIM overflows every
70 * 2^40 * 10^-9 / 60 = 18.3 minutes.
73 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
74 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
75 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
76 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
77 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
78 #define IGB_NBITS_82580 40
81 * SYSTIM read access for the 82576
84 static cycle_t
igb_ptp_read_82576(const struct cyclecounter
*cc
)
86 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
87 struct e1000_hw
*hw
= &igb
->hw
;
91 lo
= rd32(E1000_SYSTIML
);
92 hi
= rd32(E1000_SYSTIMH
);
94 val
= ((u64
) hi
) << 32;
101 * SYSTIM read access for the 82580
104 static cycle_t
igb_ptp_read_82580(const struct cyclecounter
*cc
)
106 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
107 struct e1000_hw
*hw
= &igb
->hw
;
112 * The timestamp latches on lowest register read. For the 82580
113 * the lowest register is SYSTIMR instead of SYSTIML. However we only
114 * need to provide nanosecond resolution, so we just ignore it.
116 jk
= rd32(E1000_SYSTIMR
);
117 lo
= rd32(E1000_SYSTIML
);
118 hi
= rd32(E1000_SYSTIMH
);
120 val
= ((u64
) hi
) << 32;
127 * SYSTIM read access for I210/I211
130 static void igb_ptp_read_i210(struct igb_adapter
*adapter
, struct timespec
*ts
)
132 struct e1000_hw
*hw
= &adapter
->hw
;
136 * The timestamp latches on lowest register read. For I210/I211, the
137 * lowest register is SYSTIMR. Since we only need to provide nanosecond
138 * resolution, we can ignore it.
140 jk
= rd32(E1000_SYSTIMR
);
141 nsec
= rd32(E1000_SYSTIML
);
142 sec
= rd32(E1000_SYSTIMH
);
148 static void igb_ptp_write_i210(struct igb_adapter
*adapter
,
149 const struct timespec
*ts
)
151 struct e1000_hw
*hw
= &adapter
->hw
;
154 * Writing the SYSTIMR register is not necessary as it only provides
155 * sub-nanosecond resolution.
157 wr32(E1000_SYSTIML
, ts
->tv_nsec
);
158 wr32(E1000_SYSTIMH
, ts
->tv_sec
);
162 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
163 * @adapter: board private structure
164 * @hwtstamps: timestamp structure to update
165 * @systim: unsigned 64bit system time value.
167 * We need to convert the system time value stored in the RX/TXSTMP registers
168 * into a hwtstamp which can be used by the upper level timestamping functions.
170 * The 'tmreg_lock' spinlock is used to protect the consistency of the
171 * system time value. This is needed because reading the 64 bit time
172 * value involves reading two (or three) 32 bit registers. The first
173 * read latches the value. Ditto for writing.
175 * In addition, here have extended the system time with an overflow
176 * counter in software.
178 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter
*adapter
,
179 struct skb_shared_hwtstamps
*hwtstamps
,
185 switch (adapter
->hw
.mac
.type
) {
189 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
191 ns
= timecounter_cyc2time(&adapter
->tc
, systim
);
193 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
195 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
196 hwtstamps
->hwtstamp
= ns_to_ktime(ns
);
200 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
201 /* Upper 32 bits contain s, lower 32 bits contain ns. */
202 hwtstamps
->hwtstamp
= ktime_set(systim
>> 32,
203 systim
& 0xFFFFFFFF);
211 * PTP clock operations
214 static int igb_ptp_adjfreq_82576(struct ptp_clock_info
*ptp
, s32 ppb
)
216 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
218 struct e1000_hw
*hw
= &igb
->hw
;
229 rate
= div_u64(rate
, 1953125);
231 incvalue
= 16 << IGB_82576_TSYNC_SHIFT
;
238 wr32(E1000_TIMINCA
, INCPERIOD_82576
| (incvalue
& INCVALUE_82576_MASK
));
243 static int igb_ptp_adjfreq_82580(struct ptp_clock_info
*ptp
, s32 ppb
)
245 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
247 struct e1000_hw
*hw
= &igb
->hw
;
258 rate
= div_u64(rate
, 1953125);
260 inca
= rate
& INCVALUE_MASK
;
264 wr32(E1000_TIMINCA
, inca
);
269 static int igb_ptp_adjtime_82576(struct ptp_clock_info
*ptp
, s64 delta
)
271 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
276 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
278 now
= timecounter_read(&igb
->tc
);
280 timecounter_init(&igb
->tc
, &igb
->cc
, now
);
282 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
287 static int igb_ptp_adjtime_i210(struct ptp_clock_info
*ptp
, s64 delta
)
289 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
292 struct timespec now
, then
= ns_to_timespec(delta
);
294 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
296 igb_ptp_read_i210(igb
, &now
);
297 now
= timespec_add(now
, then
);
298 igb_ptp_write_i210(igb
, (const struct timespec
*)&now
);
300 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
305 static int igb_ptp_gettime_82576(struct ptp_clock_info
*ptp
,
308 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
314 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
316 ns
= timecounter_read(&igb
->tc
);
318 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
320 ts
->tv_sec
= div_u64_rem(ns
, 1000000000, &remainder
);
321 ts
->tv_nsec
= remainder
;
326 static int igb_ptp_gettime_i210(struct ptp_clock_info
*ptp
,
329 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
333 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
335 igb_ptp_read_i210(igb
, ts
);
337 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
342 static int igb_ptp_settime_82576(struct ptp_clock_info
*ptp
,
343 const struct timespec
*ts
)
345 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
350 ns
= ts
->tv_sec
* 1000000000ULL;
353 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
355 timecounter_init(&igb
->tc
, &igb
->cc
, ns
);
357 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
362 static int igb_ptp_settime_i210(struct ptp_clock_info
*ptp
,
363 const struct timespec
*ts
)
365 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
369 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
371 igb_ptp_write_i210(igb
, ts
);
373 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
378 static int igb_ptp_enable(struct ptp_clock_info
*ptp
,
379 struct ptp_clock_request
*rq
, int on
)
386 * @work: pointer to work struct
388 * This work function polls the TSYNCTXCTL valid bit to determine when a
389 * timestamp has been taken for the current stored skb.
391 void igb_ptp_tx_work(struct work_struct
*work
)
393 struct igb_adapter
*adapter
= container_of(work
, struct igb_adapter
,
395 struct e1000_hw
*hw
= &adapter
->hw
;
398 if (!adapter
->ptp_tx_skb
)
401 if (time_is_before_jiffies(adapter
->ptp_tx_start
+
402 IGB_PTP_TX_TIMEOUT
)) {
403 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
404 adapter
->ptp_tx_skb
= NULL
;
405 adapter
->tx_hwtstamp_timeouts
++;
406 dev_warn(&adapter
->pdev
->dev
, "clearing Tx timestamp hang");
410 tsynctxctl
= rd32(E1000_TSYNCTXCTL
);
411 if (tsynctxctl
& E1000_TSYNCTXCTL_VALID
)
412 igb_ptp_tx_hwtstamp(adapter
);
414 /* reschedule to check later */
415 schedule_work(&adapter
->ptp_tx_work
);
418 static void igb_ptp_overflow_check(struct work_struct
*work
)
420 struct igb_adapter
*igb
=
421 container_of(work
, struct igb_adapter
, ptp_overflow_work
.work
);
424 igb
->ptp_caps
.gettime(&igb
->ptp_caps
, &ts
);
426 pr_debug("igb overflow check at %ld.%09lu\n", ts
.tv_sec
, ts
.tv_nsec
);
428 schedule_delayed_work(&igb
->ptp_overflow_work
,
429 IGB_SYSTIM_OVERFLOW_PERIOD
);
433 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
434 * @adapter: private network adapter structure
436 * This watchdog task is scheduled to detect error case where hardware has
437 * dropped an Rx packet that was timestamped when the ring is full. The
438 * particular error is rare but leaves the device in a state unable to timestamp
439 * any future packets.
441 void igb_ptp_rx_hang(struct igb_adapter
*adapter
)
443 struct e1000_hw
*hw
= &adapter
->hw
;
444 struct igb_ring
*rx_ring
;
445 u32 tsyncrxctl
= rd32(E1000_TSYNCRXCTL
);
446 unsigned long rx_event
;
449 if (hw
->mac
.type
!= e1000_82576
)
452 /* If we don't have a valid timestamp in the registers, just update the
453 * timeout counter and exit
455 if (!(tsyncrxctl
& E1000_TSYNCRXCTL_VALID
)) {
456 adapter
->last_rx_ptp_check
= jiffies
;
460 /* Determine the most recent watchdog or rx_timestamp event */
461 rx_event
= adapter
->last_rx_ptp_check
;
462 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
463 rx_ring
= adapter
->rx_ring
[n
];
464 if (time_after(rx_ring
->last_rx_timestamp
, rx_event
))
465 rx_event
= rx_ring
->last_rx_timestamp
;
468 /* Only need to read the high RXSTMP register to clear the lock */
469 if (time_is_before_jiffies(rx_event
+ 5 * HZ
)) {
471 adapter
->last_rx_ptp_check
= jiffies
;
472 adapter
->rx_hwtstamp_cleared
++;
473 dev_warn(&adapter
->pdev
->dev
, "clearing Rx timestamp hang");
478 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
479 * @adapter: Board private structure.
481 * If we were asked to do hardware stamping and such a time stamp is
482 * available, then it must have been for this skb here because we only
483 * allow only one such packet into the queue.
485 void igb_ptp_tx_hwtstamp(struct igb_adapter
*adapter
)
487 struct e1000_hw
*hw
= &adapter
->hw
;
488 struct skb_shared_hwtstamps shhwtstamps
;
491 regval
= rd32(E1000_TXSTMPL
);
492 regval
|= (u64
)rd32(E1000_TXSTMPH
) << 32;
494 igb_ptp_systim_to_hwtstamp(adapter
, &shhwtstamps
, regval
);
495 skb_tstamp_tx(adapter
->ptp_tx_skb
, &shhwtstamps
);
496 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
497 adapter
->ptp_tx_skb
= NULL
;
501 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
502 * @q_vector: Pointer to interrupt specific structure
503 * @va: Pointer to address containing Rx buffer
504 * @skb: Buffer containing timestamp and packet
506 * This function is meant to retrieve a timestamp from the first buffer of an
507 * incoming frame. The value is stored in little endian format starting on
510 void igb_ptp_rx_pktstamp(struct igb_q_vector
*q_vector
,
514 __le64
*regval
= (__le64
*)va
;
517 * The timestamp is recorded in little endian format.
519 * Field: Reserved Reserved SYSTIML SYSTIMH
521 igb_ptp_systim_to_hwtstamp(q_vector
->adapter
, skb_hwtstamps(skb
),
522 le64_to_cpu(regval
[1]));
526 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
527 * @q_vector: Pointer to interrupt specific structure
528 * @skb: Buffer containing timestamp and packet
530 * This function is meant to retrieve a timestamp from the internal registers
531 * of the adapter and store it in the skb.
533 void igb_ptp_rx_rgtstamp(struct igb_q_vector
*q_vector
,
536 struct igb_adapter
*adapter
= q_vector
->adapter
;
537 struct e1000_hw
*hw
= &adapter
->hw
;
541 * If this bit is set, then the RX registers contain the time stamp. No
542 * other packet will be time stamped until we read these registers, so
543 * read the registers to make them available again. Because only one
544 * packet can be time stamped at a time, we know that the register
545 * values must belong to this one here and therefore we don't need to
546 * compare any of the additional attributes stored for it.
548 * If nothing went wrong, then it should have a shared tx_flags that we
549 * can turn into a skb_shared_hwtstamps.
551 if (!(rd32(E1000_TSYNCRXCTL
) & E1000_TSYNCRXCTL_VALID
))
554 regval
= rd32(E1000_RXSTMPL
);
555 regval
|= (u64
)rd32(E1000_RXSTMPH
) << 32;
557 igb_ptp_systim_to_hwtstamp(adapter
, skb_hwtstamps(skb
), regval
);
561 * igb_ptp_hwtstamp_ioctl - control hardware time stamping
566 * Outgoing time stamping can be enabled and disabled. Play nice and
567 * disable it when requested, although it shouldn't case any overhead
568 * when no packet needs it. At most one packet in the queue may be
569 * marked for time stamping, otherwise it would be impossible to tell
570 * for sure to which packet the hardware time stamp belongs.
572 * Incoming time stamping has to be configured via the hardware
573 * filters. Not all combinations are supported, in particular event
574 * type has to be specified. Matching the kind of event packet is
575 * not supported, with the exception of "all V2 events regardless of
579 int igb_ptp_hwtstamp_ioctl(struct net_device
*netdev
,
580 struct ifreq
*ifr
, int cmd
)
582 struct igb_adapter
*adapter
= netdev_priv(netdev
);
583 struct e1000_hw
*hw
= &adapter
->hw
;
584 struct hwtstamp_config config
;
585 u32 tsync_tx_ctl
= E1000_TSYNCTXCTL_ENABLED
;
586 u32 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
587 u32 tsync_rx_cfg
= 0;
592 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
595 /* reserved for future extensions */
599 switch (config
.tx_type
) {
600 case HWTSTAMP_TX_OFF
:
608 switch (config
.rx_filter
) {
609 case HWTSTAMP_FILTER_NONE
:
612 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
613 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
614 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE
;
617 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
618 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
619 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE
;
622 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
623 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
624 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
625 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
626 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
627 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
628 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
629 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
630 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
631 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_EVENT_V2
;
632 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
636 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
637 case HWTSTAMP_FILTER_ALL
:
638 /* 82576 cannot timestamp all packets, which it needs to do to
639 * support both V1 Sync and Delay_Req messages
641 if (hw
->mac
.type
!= e1000_82576
) {
642 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
643 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
648 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
652 if (hw
->mac
.type
== e1000_82575
) {
653 if (tsync_rx_ctl
| tsync_tx_ctl
)
659 * Per-packet timestamping only works if all packets are
660 * timestamped, so enable timestamping in all packets as
661 * long as one rx filter was configured.
663 if ((hw
->mac
.type
>= e1000_82580
) && tsync_rx_ctl
) {
664 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
665 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
666 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
670 if ((hw
->mac
.type
== e1000_i210
) ||
671 (hw
->mac
.type
== e1000_i211
)) {
672 regval
= rd32(E1000_RXPBS
);
673 regval
|= E1000_RXPBS_CFG_TS_EN
;
674 wr32(E1000_RXPBS
, regval
);
678 /* enable/disable TX */
679 regval
= rd32(E1000_TSYNCTXCTL
);
680 regval
&= ~E1000_TSYNCTXCTL_ENABLED
;
681 regval
|= tsync_tx_ctl
;
682 wr32(E1000_TSYNCTXCTL
, regval
);
684 /* enable/disable RX */
685 regval
= rd32(E1000_TSYNCRXCTL
);
686 regval
&= ~(E1000_TSYNCRXCTL_ENABLED
| E1000_TSYNCRXCTL_TYPE_MASK
);
687 regval
|= tsync_rx_ctl
;
688 wr32(E1000_TSYNCRXCTL
, regval
);
690 /* define which PTP packets are time stamped */
691 wr32(E1000_TSYNCRXCFG
, tsync_rx_cfg
);
693 /* define ethertype filter for timestamped packets */
696 (E1000_ETQF_FILTER_ENABLE
| /* enable filter */
697 E1000_ETQF_1588
| /* enable timestamping */
698 ETH_P_1588
)); /* 1588 eth protocol type */
700 wr32(E1000_ETQF(3), 0);
702 /* L4 Queue Filter[3]: filter by destination port and protocol */
704 u32 ftqf
= (IPPROTO_UDP
/* UDP */
705 | E1000_FTQF_VF_BP
/* VF not compared */
706 | E1000_FTQF_1588_TIME_STAMP
/* Enable Timestamping */
707 | E1000_FTQF_MASK
); /* mask all inputs */
708 ftqf
&= ~E1000_FTQF_MASK_PROTO_BP
; /* enable protocol check */
710 wr32(E1000_IMIR(3), htons(PTP_EV_PORT
));
711 wr32(E1000_IMIREXT(3),
712 (E1000_IMIREXT_SIZE_BP
| E1000_IMIREXT_CTRL_BP
));
713 if (hw
->mac
.type
== e1000_82576
) {
714 /* enable source port check */
715 wr32(E1000_SPQF(3), htons(PTP_EV_PORT
));
716 ftqf
&= ~E1000_FTQF_MASK_SOURCE_PORT_BP
;
718 wr32(E1000_FTQF(3), ftqf
);
720 wr32(E1000_FTQF(3), E1000_FTQF_MASK
);
724 /* clear TX/RX time stamp registers, just to be sure */
725 regval
= rd32(E1000_TXSTMPL
);
726 regval
= rd32(E1000_TXSTMPH
);
727 regval
= rd32(E1000_RXSTMPL
);
728 regval
= rd32(E1000_RXSTMPH
);
730 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
734 void igb_ptp_init(struct igb_adapter
*adapter
)
736 struct e1000_hw
*hw
= &adapter
->hw
;
737 struct net_device
*netdev
= adapter
->netdev
;
739 switch (hw
->mac
.type
) {
741 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
742 adapter
->ptp_caps
.owner
= THIS_MODULE
;
743 adapter
->ptp_caps
.max_adj
= 1000000000;
744 adapter
->ptp_caps
.n_ext_ts
= 0;
745 adapter
->ptp_caps
.pps
= 0;
746 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82576
;
747 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_82576
;
748 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_82576
;
749 adapter
->ptp_caps
.settime
= igb_ptp_settime_82576
;
750 adapter
->ptp_caps
.enable
= igb_ptp_enable
;
751 adapter
->cc
.read
= igb_ptp_read_82576
;
752 adapter
->cc
.mask
= CLOCKSOURCE_MASK(64);
753 adapter
->cc
.mult
= 1;
754 adapter
->cc
.shift
= IGB_82576_TSYNC_SHIFT
;
755 /* Dial the nominal frequency. */
756 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
760 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
761 adapter
->ptp_caps
.owner
= THIS_MODULE
;
762 adapter
->ptp_caps
.max_adj
= 62499999;
763 adapter
->ptp_caps
.n_ext_ts
= 0;
764 adapter
->ptp_caps
.pps
= 0;
765 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
766 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_82576
;
767 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_82576
;
768 adapter
->ptp_caps
.settime
= igb_ptp_settime_82576
;
769 adapter
->ptp_caps
.enable
= igb_ptp_enable
;
770 adapter
->cc
.read
= igb_ptp_read_82580
;
771 adapter
->cc
.mask
= CLOCKSOURCE_MASK(IGB_NBITS_82580
);
772 adapter
->cc
.mult
= 1;
773 adapter
->cc
.shift
= 0;
774 /* Enable the timer functions by clearing bit 31. */
775 wr32(E1000_TSAUXC
, 0x0);
779 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
780 adapter
->ptp_caps
.owner
= THIS_MODULE
;
781 adapter
->ptp_caps
.max_adj
= 62499999;
782 adapter
->ptp_caps
.n_ext_ts
= 0;
783 adapter
->ptp_caps
.pps
= 0;
784 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
785 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_i210
;
786 adapter
->ptp_caps
.gettime
= igb_ptp_gettime_i210
;
787 adapter
->ptp_caps
.settime
= igb_ptp_settime_i210
;
788 adapter
->ptp_caps
.enable
= igb_ptp_enable
;
789 /* Enable the timer functions by clearing bit 31. */
790 wr32(E1000_TSAUXC
, 0x0);
793 adapter
->ptp_clock
= NULL
;
799 spin_lock_init(&adapter
->tmreg_lock
);
800 INIT_WORK(&adapter
->ptp_tx_work
, igb_ptp_tx_work
);
802 /* Initialize the clock and overflow work for devices that need it. */
803 if ((hw
->mac
.type
== e1000_i210
) || (hw
->mac
.type
== e1000_i211
)) {
804 struct timespec ts
= ktime_to_timespec(ktime_get_real());
806 igb_ptp_settime_i210(&adapter
->ptp_caps
, &ts
);
808 timecounter_init(&adapter
->tc
, &adapter
->cc
,
809 ktime_to_ns(ktime_get_real()));
811 INIT_DELAYED_WORK(&adapter
->ptp_overflow_work
,
812 igb_ptp_overflow_check
);
814 schedule_delayed_work(&adapter
->ptp_overflow_work
,
815 IGB_SYSTIM_OVERFLOW_PERIOD
);
818 /* Initialize the time sync interrupts for devices that support it. */
819 if (hw
->mac
.type
>= e1000_82580
) {
820 wr32(E1000_TSIM
, E1000_TSIM_TXTS
);
821 wr32(E1000_IMS
, E1000_IMS_TS
);
824 adapter
->ptp_clock
= ptp_clock_register(&adapter
->ptp_caps
,
825 &adapter
->pdev
->dev
);
826 if (IS_ERR(adapter
->ptp_clock
)) {
827 adapter
->ptp_clock
= NULL
;
828 dev_err(&adapter
->pdev
->dev
, "ptp_clock_register failed\n");
830 dev_info(&adapter
->pdev
->dev
, "added PHC on %s\n",
831 adapter
->netdev
->name
);
832 adapter
->flags
|= IGB_FLAG_PTP
;
837 * igb_ptp_stop - Disable PTP device and stop the overflow check.
838 * @adapter: Board private structure.
840 * This function stops the PTP support and cancels the delayed work.
842 void igb_ptp_stop(struct igb_adapter
*adapter
)
844 switch (adapter
->hw
.mac
.type
) {
848 cancel_delayed_work_sync(&adapter
->ptp_overflow_work
);
852 /* No delayed work to cancel. */
858 cancel_work_sync(&adapter
->ptp_tx_work
);
859 if (adapter
->ptp_tx_skb
) {
860 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
861 adapter
->ptp_tx_skb
= NULL
;
864 if (adapter
->ptp_clock
) {
865 ptp_clock_unregister(adapter
->ptp_clock
);
866 dev_info(&adapter
->pdev
->dev
, "removed PHC on %s\n",
867 adapter
->netdev
->name
);
868 adapter
->flags
&= ~IGB_FLAG_PTP
;
873 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
874 * @adapter: Board private structure.
876 * This function handles the reset work required to re-enable the PTP device.
878 void igb_ptp_reset(struct igb_adapter
*adapter
)
880 struct e1000_hw
*hw
= &adapter
->hw
;
882 if (!(adapter
->flags
& IGB_FLAG_PTP
))
885 switch (adapter
->hw
.mac
.type
) {
887 /* Dial the nominal frequency. */
888 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
894 /* Enable the timer functions and interrupts. */
895 wr32(E1000_TSAUXC
, 0x0);
896 wr32(E1000_TSIM
, E1000_TSIM_TXTS
);
897 wr32(E1000_IMS
, E1000_IMS_TS
);
904 /* Re-initialize the timer. */
905 if ((hw
->mac
.type
== e1000_i210
) || (hw
->mac
.type
== e1000_i211
)) {
906 struct timespec ts
= ktime_to_timespec(ktime_get_real());
908 igb_ptp_settime_i210(&adapter
->ptp_caps
, &ts
);
910 timecounter_init(&adapter
->tc
, &adapter
->cc
,
911 ktime_to_ns(ktime_get_real()));