2 * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
4 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/pci.h>
26 #define INCVALUE_MASK 0x7fffffff
27 #define ISGN 0x80000000
30 * The 82580 timesync updates the system timer every 8ns by 8ns,
31 * and this update value cannot be reprogrammed.
33 * Neither the 82576 nor the 82580 offer registers wide enough to hold
34 * nanoseconds time values for very long. For the 82580, SYSTIM always
35 * counts nanoseconds, but the upper 24 bits are not availible. The
36 * frequency is adjusted by changing the 32 bit fractional nanoseconds
39 * For the 82576, the SYSTIM register time unit is affect by the
40 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
41 * field are needed to provide the nominal 16 nanosecond period,
42 * leaving 19 bits for fractional nanoseconds.
44 * We scale the NIC clock cycle by a large factor so that relatively
45 * small clock corrections can be added or subtracted at each clock
46 * tick. The drawbacks of a large factor are a) that the clock
47 * register overflows more quickly (not such a big deal) and b) that
48 * the increment per tick has to fit into 24 bits. As a result we
49 * need to use a shift of 19 so we can fit a value of 16 into the
54 * +--------------+ +---+---+------+
55 * 82576 | 32 | | 8 | 5 | 19 |
56 * +--------------+ +---+---+------+
57 * \________ 45 bits _______/ fract
59 * +----------+---+ +--------------+
60 * 82580 | 24 | 8 | | 32 |
61 * +----------+---+ +--------------+
62 * reserved \______ 40 bits _____/
65 * The 45 bit 82576 SYSTIM overflows every
66 * 2^45 * 10^-9 / 3600 = 9.77 hours.
68 * The 40 bit 82580 SYSTIM overflows every
69 * 2^40 * 10^-9 / 60 = 18.3 minutes.
72 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
73 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
74 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
75 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
76 #define IGB_NBITS_82580 40
79 * SYSTIM read access for the 82576
82 static cycle_t
igb_ptp_read_82576(const struct cyclecounter
*cc
)
84 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
85 struct e1000_hw
*hw
= &igb
->hw
;
89 lo
= rd32(E1000_SYSTIML
);
90 hi
= rd32(E1000_SYSTIMH
);
92 val
= ((u64
) hi
) << 32;
99 * SYSTIM read access for the 82580
102 static cycle_t
igb_ptp_read_82580(const struct cyclecounter
*cc
)
104 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
105 struct e1000_hw
*hw
= &igb
->hw
;
110 * The timestamp latches on lowest register read. For the 82580
111 * the lowest register is SYSTIMR instead of SYSTIML. However we only
112 * need to provide nanosecond resolution, so we just ignore it.
114 jk
= rd32(E1000_SYSTIMR
);
115 lo
= rd32(E1000_SYSTIML
);
116 hi
= rd32(E1000_SYSTIMH
);
118 val
= ((u64
) hi
) << 32;
125 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
126 * @adapter: board private structure
127 * @hwtstamps: timestamp structure to update
128 * @systim: unsigned 64bit system time value.
130 * We need to convert the system time value stored in the RX/TXSTMP registers
131 * into a hwtstamp which can be used by the upper level timestamping functions.
133 * The 'tmreg_lock' spinlock is used to protect the consistency of the
134 * system time value. This is needed because reading the 64 bit time
135 * value involves reading two (or three) 32 bit registers. The first
136 * read latches the value. Ditto for writing.
138 * In addition, here have extended the system time with an overflow
139 * counter in software.
141 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter
*adapter
,
142 struct skb_shared_hwtstamps
*hwtstamps
,
148 switch (adapter
->hw
.mac
.type
) {
159 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
161 ns
= timecounter_cyc2time(&adapter
->tc
, systim
);
163 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
165 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
166 hwtstamps
->hwtstamp
= ns_to_ktime(ns
);
170 * PTP clock operations
173 static int igb_ptp_adjfreq_82576(struct ptp_clock_info
*ptp
, s32 ppb
)
175 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
177 struct e1000_hw
*hw
= &igb
->hw
;
188 rate
= div_u64(rate
, 1953125);
190 incvalue
= 16 << IGB_82576_TSYNC_SHIFT
;
197 wr32(E1000_TIMINCA
, INCPERIOD_82576
| (incvalue
& INCVALUE_82576_MASK
));
202 static int igb_ptp_adjfreq_82580(struct ptp_clock_info
*ptp
, s32 ppb
)
204 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
206 struct e1000_hw
*hw
= &igb
->hw
;
217 rate
= div_u64(rate
, 1953125);
219 inca
= rate
& INCVALUE_MASK
;
223 wr32(E1000_TIMINCA
, inca
);
228 static int igb_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
230 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
235 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
237 now
= timecounter_read(&igb
->tc
);
239 timecounter_init(&igb
->tc
, &igb
->cc
, now
);
241 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
246 static int igb_ptp_gettime(struct ptp_clock_info
*ptp
, struct timespec
*ts
)
248 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
254 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
256 ns
= timecounter_read(&igb
->tc
);
258 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
260 ts
->tv_sec
= div_u64_rem(ns
, 1000000000, &remainder
);
261 ts
->tv_nsec
= remainder
;
266 static int igb_ptp_settime(struct ptp_clock_info
*ptp
,
267 const struct timespec
*ts
)
269 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
274 ns
= ts
->tv_sec
* 1000000000ULL;
277 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
279 timecounter_init(&igb
->tc
, &igb
->cc
, ns
);
281 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
286 static int igb_ptp_enable(struct ptp_clock_info
*ptp
,
287 struct ptp_clock_request
*rq
, int on
)
294 * @work: pointer to work struct
296 * This work function polls the TSYNCTXCTL valid bit to determine when a
297 * timestamp has been taken for the current stored skb.
299 void igb_ptp_tx_work(struct work_struct
*work
)
301 struct igb_adapter
*adapter
= container_of(work
, struct igb_adapter
,
303 struct e1000_hw
*hw
= &adapter
->hw
;
306 if (!adapter
->ptp_tx_skb
)
309 tsynctxctl
= rd32(E1000_TSYNCTXCTL
);
310 if (tsynctxctl
& E1000_TSYNCTXCTL_VALID
)
311 igb_ptp_tx_hwtstamp(adapter
);
313 /* reschedule to check later */
314 schedule_work(&adapter
->ptp_tx_work
);
317 static void igb_ptp_overflow_check(struct work_struct
*work
)
319 struct igb_adapter
*igb
=
320 container_of(work
, struct igb_adapter
, ptp_overflow_work
.work
);
323 igb_ptp_gettime(&igb
->ptp_caps
, &ts
);
325 pr_debug("igb overflow check at %ld.%09lu\n", ts
.tv_sec
, ts
.tv_nsec
);
327 schedule_delayed_work(&igb
->ptp_overflow_work
,
328 IGB_SYSTIM_OVERFLOW_PERIOD
);
332 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
333 * @adapter: Board private structure.
335 * If we were asked to do hardware stamping and such a time stamp is
336 * available, then it must have been for this skb here because we only
337 * allow only one such packet into the queue.
339 void igb_ptp_tx_hwtstamp(struct igb_adapter
*adapter
)
341 struct e1000_hw
*hw
= &adapter
->hw
;
342 struct skb_shared_hwtstamps shhwtstamps
;
345 regval
= rd32(E1000_TXSTMPL
);
346 regval
|= (u64
)rd32(E1000_TXSTMPH
) << 32;
348 igb_ptp_systim_to_hwtstamp(adapter
, &shhwtstamps
, regval
);
349 skb_tstamp_tx(adapter
->ptp_tx_skb
, &shhwtstamps
);
350 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
351 adapter
->ptp_tx_skb
= NULL
;
354 void igb_ptp_rx_hwtstamp(struct igb_q_vector
*q_vector
,
355 union e1000_adv_rx_desc
*rx_desc
,
358 struct igb_adapter
*adapter
= q_vector
->adapter
;
359 struct e1000_hw
*hw
= &adapter
->hw
;
362 if (!igb_test_staterr(rx_desc
, E1000_RXDADV_STAT_TSIP
|
363 E1000_RXDADV_STAT_TS
))
367 * If this bit is set, then the RX registers contain the time stamp. No
368 * other packet will be time stamped until we read these registers, so
369 * read the registers to make them available again. Because only one
370 * packet can be time stamped at a time, we know that the register
371 * values must belong to this one here and therefore we don't need to
372 * compare any of the additional attributes stored for it.
374 * If nothing went wrong, then it should have a shared tx_flags that we
375 * can turn into a skb_shared_hwtstamps.
377 if (igb_test_staterr(rx_desc
, E1000_RXDADV_STAT_TSIP
)) {
378 u32
*stamp
= (u32
*)skb
->data
;
379 regval
= le32_to_cpu(*(stamp
+ 2));
380 regval
|= (u64
)le32_to_cpu(*(stamp
+ 3)) << 32;
381 skb_pull(skb
, IGB_TS_HDR_LEN
);
383 if (!(rd32(E1000_TSYNCRXCTL
) & E1000_TSYNCRXCTL_VALID
))
386 regval
= rd32(E1000_RXSTMPL
);
387 regval
|= (u64
)rd32(E1000_RXSTMPH
) << 32;
390 igb_ptp_systim_to_hwtstamp(adapter
, skb_hwtstamps(skb
), regval
);
394 * igb_ptp_hwtstamp_ioctl - control hardware time stamping
399 * Outgoing time stamping can be enabled and disabled. Play nice and
400 * disable it when requested, although it shouldn't case any overhead
401 * when no packet needs it. At most one packet in the queue may be
402 * marked for time stamping, otherwise it would be impossible to tell
403 * for sure to which packet the hardware time stamp belongs.
405 * Incoming time stamping has to be configured via the hardware
406 * filters. Not all combinations are supported, in particular event
407 * type has to be specified. Matching the kind of event packet is
408 * not supported, with the exception of "all V2 events regardless of
412 int igb_ptp_hwtstamp_ioctl(struct net_device
*netdev
,
413 struct ifreq
*ifr
, int cmd
)
415 struct igb_adapter
*adapter
= netdev_priv(netdev
);
416 struct e1000_hw
*hw
= &adapter
->hw
;
417 struct hwtstamp_config config
;
418 u32 tsync_tx_ctl
= E1000_TSYNCTXCTL_ENABLED
;
419 u32 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
420 u32 tsync_rx_cfg
= 0;
425 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
428 /* reserved for future extensions */
432 switch (config
.tx_type
) {
433 case HWTSTAMP_TX_OFF
:
441 switch (config
.rx_filter
) {
442 case HWTSTAMP_FILTER_NONE
:
445 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
446 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
447 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
448 case HWTSTAMP_FILTER_ALL
:
450 * register TSYNCRXCFG must be set, therefore it is not
451 * possible to time stamp both Sync and Delay_Req messages
452 * => fall back to time stamping all packets
454 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
455 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
457 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
458 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
459 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE
;
462 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
463 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
464 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE
;
467 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
468 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
469 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L2_L4_V2
;
470 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE
;
473 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
475 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
476 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
477 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L2_L4_V2
;
478 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE
;
481 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
483 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
484 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
485 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
486 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_EVENT_V2
;
487 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
495 if (hw
->mac
.type
== e1000_82575
) {
496 if (tsync_rx_ctl
| tsync_tx_ctl
)
502 * Per-packet timestamping only works if all packets are
503 * timestamped, so enable timestamping in all packets as
504 * long as one rx filter was configured.
506 if ((hw
->mac
.type
>= e1000_82580
) && tsync_rx_ctl
) {
507 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
508 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
511 /* enable/disable TX */
512 regval
= rd32(E1000_TSYNCTXCTL
);
513 regval
&= ~E1000_TSYNCTXCTL_ENABLED
;
514 regval
|= tsync_tx_ctl
;
515 wr32(E1000_TSYNCTXCTL
, regval
);
517 /* enable/disable RX */
518 regval
= rd32(E1000_TSYNCRXCTL
);
519 regval
&= ~(E1000_TSYNCRXCTL_ENABLED
| E1000_TSYNCRXCTL_TYPE_MASK
);
520 regval
|= tsync_rx_ctl
;
521 wr32(E1000_TSYNCRXCTL
, regval
);
523 /* define which PTP packets are time stamped */
524 wr32(E1000_TSYNCRXCFG
, tsync_rx_cfg
);
526 /* define ethertype filter for timestamped packets */
529 (E1000_ETQF_FILTER_ENABLE
| /* enable filter */
530 E1000_ETQF_1588
| /* enable timestamping */
531 ETH_P_1588
)); /* 1588 eth protocol type */
533 wr32(E1000_ETQF(3), 0);
536 /* L4 Queue Filter[3]: filter by destination port and protocol */
538 u32 ftqf
= (IPPROTO_UDP
/* UDP */
539 | E1000_FTQF_VF_BP
/* VF not compared */
540 | E1000_FTQF_1588_TIME_STAMP
/* Enable Timestamping */
541 | E1000_FTQF_MASK
); /* mask all inputs */
542 ftqf
&= ~E1000_FTQF_MASK_PROTO_BP
; /* enable protocol check */
544 wr32(E1000_IMIR(3), htons(PTP_PORT
));
545 wr32(E1000_IMIREXT(3),
546 (E1000_IMIREXT_SIZE_BP
| E1000_IMIREXT_CTRL_BP
));
547 if (hw
->mac
.type
== e1000_82576
) {
548 /* enable source port check */
549 wr32(E1000_SPQF(3), htons(PTP_PORT
));
550 ftqf
&= ~E1000_FTQF_MASK_SOURCE_PORT_BP
;
552 wr32(E1000_FTQF(3), ftqf
);
554 wr32(E1000_FTQF(3), E1000_FTQF_MASK
);
558 /* clear TX/RX time stamp registers, just to be sure */
559 regval
= rd32(E1000_TXSTMPH
);
560 regval
= rd32(E1000_RXSTMPH
);
562 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
566 void igb_ptp_init(struct igb_adapter
*adapter
)
568 struct e1000_hw
*hw
= &adapter
->hw
;
569 struct net_device
*netdev
= adapter
->netdev
;
571 switch (hw
->mac
.type
) {
576 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
577 adapter
->ptp_caps
.owner
= THIS_MODULE
;
578 adapter
->ptp_caps
.max_adj
= 62499999;
579 adapter
->ptp_caps
.n_ext_ts
= 0;
580 adapter
->ptp_caps
.pps
= 0;
581 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
582 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime
;
583 adapter
->ptp_caps
.gettime
= igb_ptp_gettime
;
584 adapter
->ptp_caps
.settime
= igb_ptp_settime
;
585 adapter
->ptp_caps
.enable
= igb_ptp_enable
;
586 adapter
->cc
.read
= igb_ptp_read_82580
;
587 adapter
->cc
.mask
= CLOCKSOURCE_MASK(IGB_NBITS_82580
);
588 adapter
->cc
.mult
= 1;
589 adapter
->cc
.shift
= 0;
590 /* Enable the timer functions by clearing bit 31. */
591 wr32(E1000_TSAUXC
, 0x0);
594 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
595 adapter
->ptp_caps
.owner
= THIS_MODULE
;
596 adapter
->ptp_caps
.max_adj
= 1000000000;
597 adapter
->ptp_caps
.n_ext_ts
= 0;
598 adapter
->ptp_caps
.pps
= 0;
599 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82576
;
600 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime
;
601 adapter
->ptp_caps
.gettime
= igb_ptp_gettime
;
602 adapter
->ptp_caps
.settime
= igb_ptp_settime
;
603 adapter
->ptp_caps
.enable
= igb_ptp_enable
;
604 adapter
->cc
.read
= igb_ptp_read_82576
;
605 adapter
->cc
.mask
= CLOCKSOURCE_MASK(64);
606 adapter
->cc
.mult
= 1;
607 adapter
->cc
.shift
= IGB_82576_TSYNC_SHIFT
;
608 /* Dial the nominal frequency. */
609 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
612 adapter
->ptp_clock
= NULL
;
618 timecounter_init(&adapter
->tc
, &adapter
->cc
,
619 ktime_to_ns(ktime_get_real()));
621 INIT_DELAYED_WORK(&adapter
->ptp_overflow_work
, igb_ptp_overflow_check
);
623 spin_lock_init(&adapter
->tmreg_lock
);
625 INIT_WORK(&adapter
->ptp_tx_work
, igb_ptp_tx_work
);
627 schedule_delayed_work(&adapter
->ptp_overflow_work
,
628 IGB_SYSTIM_OVERFLOW_PERIOD
);
630 /* Initialize the time sync interrupts for devices that support it. */
631 if (hw
->mac
.type
>= e1000_82580
) {
632 wr32(E1000_TSIM
, E1000_TSIM_TXTS
);
633 wr32(E1000_IMS
, E1000_IMS_TS
);
636 adapter
->ptp_clock
= ptp_clock_register(&adapter
->ptp_caps
);
637 if (IS_ERR(adapter
->ptp_clock
)) {
638 adapter
->ptp_clock
= NULL
;
639 dev_err(&adapter
->pdev
->dev
, "ptp_clock_register failed\n");
641 dev_info(&adapter
->pdev
->dev
, "added PHC on %s\n",
642 adapter
->netdev
->name
);
643 adapter
->flags
|= IGB_FLAG_PTP
;
648 * igb_ptp_stop - Disable PTP device and stop the overflow check.
649 * @adapter: Board private structure.
651 * This function stops the PTP support and cancels the delayed work.
653 void igb_ptp_stop(struct igb_adapter
*adapter
)
655 switch (adapter
->hw
.mac
.type
) {
659 cancel_delayed_work_sync(&adapter
->ptp_overflow_work
);
663 /* No delayed work to cancel. */
669 cancel_work_sync(&adapter
->ptp_tx_work
);
671 if (adapter
->ptp_clock
) {
672 ptp_clock_unregister(adapter
->ptp_clock
);
673 dev_info(&adapter
->pdev
->dev
, "removed PHC on %s\n",
674 adapter
->netdev
->name
);
675 adapter
->flags
&= ~IGB_FLAG_PTP
;
680 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
681 * @adapter: Board private structure.
683 * This function handles the reset work required to re-enable the PTP device.
685 void igb_ptp_reset(struct igb_adapter
*adapter
)
687 struct e1000_hw
*hw
= &adapter
->hw
;
689 if (!(adapter
->flags
& IGB_FLAG_PTP
))
692 switch (adapter
->hw
.mac
.type
) {
694 /* Dial the nominal frequency. */
695 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
701 /* Enable the timer functions and interrupts. */
702 wr32(E1000_TSAUXC
, 0x0);
703 wr32(E1000_TSIM
, E1000_TSIM_TXTS
);
704 wr32(E1000_IMS
, E1000_IMS_TS
);
711 timecounter_init(&adapter
->tc
, &adapter
->cc
,
712 ktime_to_ns(ktime_get_real()));