drivers/net/ethernet/intel/igb/igb_ptp.c

   1 /*
   2  * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
   3  *
   4  * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20 #include <linux/module.h>
  21 #include <linux/device.h>
  22 #include <linux/pci.h>
  23
  24 #include "igb.h"
  25
  26 #define INCVALUE_MASK           0x7fffffff
  27 #define ISGN                    0x80000000
  28
  29 /*
  30  * The 82580 timesync updates the system timer every 8ns by 8ns,
  31  * and this update value cannot be reprogrammed.
  32  *
  33  * Neither the 82576 nor the 82580 offer registers wide enough to hold
  34  * nanoseconds time values for very long. For the 82580, SYSTIM always
  35  * counts nanoseconds, but the upper 24 bits are not availible. The
  36  * frequency is adjusted by changing the 32 bit fractional nanoseconds
  37  * register, TIMINCA.
  38  *
  39  * For the 82576, the SYSTIM register time unit is affect by the
  40  * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
  41  * field are needed to provide the nominal 16 nanosecond period,
  42  * leaving 19 bits for fractional nanoseconds.
  43  *
  44  * We scale the NIC clock cycle by a large factor so that relatively
  45  * small clock corrections can be added or subtracted at each clock
  46  * tick. The drawbacks of a large factor are a) that the clock
  47  * register overflows more quickly (not such a big deal) and b) that
  48  * the increment per tick has to fit into 24 bits.  As a result we
  49  * need to use a shift of 19 so we can fit a value of 16 into the
  50  * TIMINCA register.
  51  *
  52  *
  53  *             SYSTIMH            SYSTIML
  54  *        +--------------+   +---+---+------+
  55  *  82576 |      32      |   | 8 | 5 |  19  |
  56  *        +--------------+   +---+---+------+
  57  *         \________ 45 bits _______/  fract
  58  *
  59  *        +----------+---+   +--------------+
  60  *  82580 |    24    | 8 |   |      32      |
  61  *        +----------+---+   +--------------+
  62  *          reserved  \______ 40 bits _____/
  63  *
  64  *
  65  * The 45 bit 82576 SYSTIM overflows every
  66  *   2^45 * 10^-9 / 3600 = 9.77 hours.
  67  *
  68  * The 40 bit 82580 SYSTIM overflows every
  69  *   2^40 * 10^-9 /  60  = 18.3 minutes.
  70  */
  71
  72 #define IGB_SYSTIM_OVERFLOW_PERIOD      (HZ * 60 * 9)
  73 #define INCPERIOD_82576                 (1 << E1000_TIMINCA_16NS_SHIFT)
  74 #define INCVALUE_82576_MASK             ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
  75 #define INCVALUE_82576                  (16 << IGB_82576_TSYNC_SHIFT)
  76 #define IGB_NBITS_82580                 40
  77
  78 /*
  79  * SYSTIM read access for the 82576
  80  */
  81
  82 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
  83 {
  84         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
  85         struct e1000_hw *hw = &igb->hw;
  86         u64 val;
  87         u32 lo, hi;
  88
  89         lo = rd32(E1000_SYSTIML);
  90         hi = rd32(E1000_SYSTIMH);
  91
  92         val = ((u64) hi) << 32;
  93         val |= lo;
  94
  95         return val;
  96 }
  97
  98 /*
  99  * SYSTIM read access for the 82580
 100  */
 101
 102 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
 103 {
 104         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
 105         struct e1000_hw *hw = &igb->hw;
 106         u64 val;
 107         u32 lo, hi, jk;
 108
 109         /*
 110          * The timestamp latches on lowest register read. For the 82580
 111          * the lowest register is SYSTIMR instead of SYSTIML.  However we only
 112          * need to provide nanosecond resolution, so we just ignore it.
 113          */
 114         jk = rd32(E1000_SYSTIMR);
 115         lo = rd32(E1000_SYSTIML);
 116         hi = rd32(E1000_SYSTIMH);
 117
 118         val = ((u64) hi) << 32;
 119         val |= lo;
 120
 121         return val;
 122 }
 123
 124 /**
 125  * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
 126  * @adapter: board private structure
 127  * @hwtstamps: timestamp structure to update
 128  * @systim: unsigned 64bit system time value.
 129  *
 130  * We need to convert the system time value stored in the RX/TXSTMP registers
 131  * into a hwtstamp which can be used by the upper level timestamping functions.
 132  *
 133  * The 'tmreg_lock' spinlock is used to protect the consistency of the
 134  * system time value. This is needed because reading the 64 bit time
 135  * value involves reading two (or three) 32 bit registers. The first
 136  * read latches the value. Ditto for writing.
 137  *
 138  * In addition, here have extended the system time with an overflow
 139  * counter in software.
 140  **/
 141 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
 142                                        struct skb_shared_hwtstamps *hwtstamps,
 143                                        u64 systim)
 144 {
 145         unsigned long flags;
 146         u64 ns;
 147
 148         switch (adapter->hw.mac.type) {
 149         case e1000_i210:
 150         case e1000_i211:
 151         case e1000_i350:
 152         case e1000_82580:
 153         case e1000_82576:
 154                 break;
 155         default:
 156                 return;
 157         }
 158
 159         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 160
 161         ns = timecounter_cyc2time(&adapter->tc, systim);
 162
 163         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 164
 165         memset(hwtstamps, 0, sizeof(*hwtstamps));
 166         hwtstamps->hwtstamp = ns_to_ktime(ns);
 167 }
 168
 169 /*
 170  * PTP clock operations
 171  */
 172
 173 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
 174 {
 175         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 176                                                ptp_caps);
 177         struct e1000_hw *hw = &igb->hw;
 178         int neg_adj = 0;
 179         u64 rate;
 180         u32 incvalue;
 181
 182         if (ppb < 0) {
 183                 neg_adj = 1;
 184                 ppb = -ppb;
 185         }
 186         rate = ppb;
 187         rate <<= 14;
 188         rate = div_u64(rate, 1953125);
 189
 190         incvalue = 16 << IGB_82576_TSYNC_SHIFT;
 191
 192         if (neg_adj)
 193                 incvalue -= rate;
 194         else
 195                 incvalue += rate;
 196
 197         wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
 198
 199         return 0;
 200 }
 201
 202 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
 203 {
 204         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 205                                                ptp_caps);
 206         struct e1000_hw *hw = &igb->hw;
 207         int neg_adj = 0;
 208         u64 rate;
 209         u32 inca;
 210
 211         if (ppb < 0) {
 212                 neg_adj = 1;
 213                 ppb = -ppb;
 214         }
 215         rate = ppb;
 216         rate <<= 26;
 217         rate = div_u64(rate, 1953125);
 218
 219         inca = rate & INCVALUE_MASK;
 220         if (neg_adj)
 221                 inca |= ISGN;
 222
 223         wr32(E1000_TIMINCA, inca);
 224
 225         return 0;
 226 }
 227
 228 static int igb_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 229 {
 230         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 231                                                ptp_caps);
 232         unsigned long flags;
 233         s64 now;
 234
 235         spin_lock_irqsave(&igb->tmreg_lock, flags);
 236
 237         now = timecounter_read(&igb->tc);
 238         now += delta;
 239         timecounter_init(&igb->tc, &igb->cc, now);
 240
 241         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 242
 243         return 0;
 244 }
 245
 246 static int igb_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 247 {
 248         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 249                                                ptp_caps);
 250         unsigned long flags;
 251         u64 ns;
 252         u32 remainder;
 253
 254         spin_lock_irqsave(&igb->tmreg_lock, flags);
 255
 256         ns = timecounter_read(&igb->tc);
 257
 258         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 259
 260         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
 261         ts->tv_nsec = remainder;
 262
 263         return 0;
 264 }
 265
 266 static int igb_ptp_settime(struct ptp_clock_info *ptp,
 267                            const struct timespec *ts)
 268 {
 269         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 270                                                ptp_caps);
 271         unsigned long flags;
 272         u64 ns;
 273
 274         ns = ts->tv_sec * 1000000000ULL;
 275         ns += ts->tv_nsec;
 276
 277         spin_lock_irqsave(&igb->tmreg_lock, flags);
 278
 279         timecounter_init(&igb->tc, &igb->cc, ns);
 280
 281         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 282
 283         return 0;
 284 }
 285
 286 static int igb_ptp_enable(struct ptp_clock_info *ptp,
 287                           struct ptp_clock_request *rq, int on)
 288 {
 289         return -EOPNOTSUPP;
 290 }
 291
 292 static void igb_ptp_overflow_check(struct work_struct *work)
 293 {
 294         struct igb_adapter *igb =
 295                 container_of(work, struct igb_adapter, ptp_overflow_work.work);
 296         struct timespec ts;
 297
 298         igb_ptp_gettime(&igb->ptp_caps, &ts);
 299
 300         pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
 301
 302         schedule_delayed_work(&igb->ptp_overflow_work,
 303                               IGB_SYSTIM_OVERFLOW_PERIOD);
 304 }
 305
 306 /**
 307  * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 308  * @q_vector: pointer to q_vector containing needed info
 309  * @buffer: pointer to igb_tx_buffer structure
 310  *
 311  * If we were asked to do hardware stamping and such a time stamp is
 312  * available, then it must have been for this skb here because we only
 313  * allow only one such packet into the queue.
 314  */
 315 void igb_ptp_tx_hwtstamp(struct igb_q_vector *q_vector,
 316                          struct igb_tx_buffer *buffer_info)
 317 {
 318         struct igb_adapter *adapter = q_vector->adapter;
 319         struct e1000_hw *hw = &adapter->hw;
 320         struct skb_shared_hwtstamps shhwtstamps;
 321         u64 regval;
 322
 323         /* if skb does not support hw timestamp or TX stamp not valid exit */
 324         if (likely(!(buffer_info->tx_flags & IGB_TX_FLAGS_TSTAMP)) ||
 325             !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
 326                 return;
 327
 328         regval = rd32(E1000_TXSTMPL);
 329         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
 330
 331         igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
 332         skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
 333 }
 334
 335 void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector,
 336                          union e1000_adv_rx_desc *rx_desc,
 337                          struct sk_buff *skb)
 338 {
 339         struct igb_adapter *adapter = q_vector->adapter;
 340         struct e1000_hw *hw = &adapter->hw;
 341         u64 regval;
 342
 343         if (!igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP |
 344                                        E1000_RXDADV_STAT_TS))
 345                 return;
 346
 347         /*
 348          * If this bit is set, then the RX registers contain the time stamp. No
 349          * other packet will be time stamped until we read these registers, so
 350          * read the registers to make them available again. Because only one
 351          * packet can be time stamped at a time, we know that the register
 352          * values must belong to this one here and therefore we don't need to
 353          * compare any of the additional attributes stored for it.
 354          *
 355          * If nothing went wrong, then it should have a shared tx_flags that we
 356          * can turn into a skb_shared_hwtstamps.
 357          */
 358         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
 359                 u32 *stamp = (u32 *)skb->data;
 360                 regval = le32_to_cpu(*(stamp + 2));
 361                 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
 362                 skb_pull(skb, IGB_TS_HDR_LEN);
 363         } else {
 364                 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
 365                         return;
 366
 367                 regval = rd32(E1000_RXSTMPL);
 368                 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
 369         }
 370
 371         igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
 372 }
 373
 374 /**
 375  * igb_ptp_hwtstamp_ioctl - control hardware time stamping
 376  * @netdev:
 377  * @ifreq:
 378  * @cmd:
 379  *
 380  * Outgoing time stamping can be enabled and disabled. Play nice and
 381  * disable it when requested, although it shouldn't case any overhead
 382  * when no packet needs it. At most one packet in the queue may be
 383  * marked for time stamping, otherwise it would be impossible to tell
 384  * for sure to which packet the hardware time stamp belongs.
 385  *
 386  * Incoming time stamping has to be configured via the hardware
 387  * filters. Not all combinations are supported, in particular event
 388  * type has to be specified. Matching the kind of event packet is
 389  * not supported, with the exception of "all V2 events regardless of
 390  * level 2 or 4".
 391  *
 392  **/
 393 int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
 394                            struct ifreq *ifr, int cmd)
 395 {
 396         struct igb_adapter *adapter = netdev_priv(netdev);
 397         struct e1000_hw *hw = &adapter->hw;
 398         struct hwtstamp_config config;
 399         u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
 400         u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 401         u32 tsync_rx_cfg = 0;
 402         bool is_l4 = false;
 403         bool is_l2 = false;
 404         u32 regval;
 405
 406         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 407                 return -EFAULT;
 408
 409         /* reserved for future extensions */
 410         if (config.flags)
 411                 return -EINVAL;
 412
 413         switch (config.tx_type) {
 414         case HWTSTAMP_TX_OFF:
 415                 tsync_tx_ctl = 0;
 416         case HWTSTAMP_TX_ON:
 417                 break;
 418         default:
 419                 return -ERANGE;
 420         }
 421
 422         switch (config.rx_filter) {
 423         case HWTSTAMP_FILTER_NONE:
 424                 tsync_rx_ctl = 0;
 425                 break;
 426         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 427         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 428         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 429         case HWTSTAMP_FILTER_ALL:
 430                 /*
 431                  * register TSYNCRXCFG must be set, therefore it is not
 432                  * possible to time stamp both Sync and Delay_Req messages
 433                  * => fall back to time stamping all packets
 434                  */
 435                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 436                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 437                 break;
 438         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 439                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 440                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
 441                 is_l4 = true;
 442                 break;
 443         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 444                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 445                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
 446                 is_l4 = true;
 447                 break;
 448         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 449         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 450                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
 451                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
 452                 is_l2 = true;
 453                 is_l4 = true;
 454                 config.rx_filter = HWTSTAMP_FILTER_SOME;
 455                 break;
 456         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 457         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 458                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
 459                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
 460                 is_l2 = true;
 461                 is_l4 = true;
 462                 config.rx_filter = HWTSTAMP_FILTER_SOME;
 463                 break;
 464         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 465         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 466         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 467                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
 468                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 469                 is_l2 = true;
 470                 is_l4 = true;
 471                 break;
 472         default:
 473                 return -ERANGE;
 474         }
 475
 476         if (hw->mac.type == e1000_82575) {
 477                 if (tsync_rx_ctl | tsync_tx_ctl)
 478                         return -EINVAL;
 479                 return 0;
 480         }
 481
 482         /*
 483          * Per-packet timestamping only works if all packets are
 484          * timestamped, so enable timestamping in all packets as
 485          * long as one rx filter was configured.
 486          */
 487         if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
 488                 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 489                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 490         }
 491
 492         /* enable/disable TX */
 493         regval = rd32(E1000_TSYNCTXCTL);
 494         regval &= ~E1000_TSYNCTXCTL_ENABLED;
 495         regval |= tsync_tx_ctl;
 496         wr32(E1000_TSYNCTXCTL, regval);
 497
 498         /* enable/disable RX */
 499         regval = rd32(E1000_TSYNCRXCTL);
 500         regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
 501         regval |= tsync_rx_ctl;
 502         wr32(E1000_TSYNCRXCTL, regval);
 503
 504         /* define which PTP packets are time stamped */
 505         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
 506
 507         /* define ethertype filter for timestamped packets */
 508         if (is_l2)
 509                 wr32(E1000_ETQF(3),
 510                      (E1000_ETQF_FILTER_ENABLE | /* enable filter */
 511                       E1000_ETQF_1588 | /* enable timestamping */
 512                       ETH_P_1588));     /* 1588 eth protocol type */
 513         else
 514                 wr32(E1000_ETQF(3), 0);
 515
 516 #define PTP_PORT 319
 517         /* L4 Queue Filter[3]: filter by destination port and protocol */
 518         if (is_l4) {
 519                 u32 ftqf = (IPPROTO_UDP /* UDP */
 520                         | E1000_FTQF_VF_BP /* VF not compared */
 521                         | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
 522                         | E1000_FTQF_MASK); /* mask all inputs */
 523                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
 524
 525                 wr32(E1000_IMIR(3), htons(PTP_PORT));
 526                 wr32(E1000_IMIREXT(3),
 527                      (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
 528                 if (hw->mac.type == e1000_82576) {
 529                         /* enable source port check */
 530                         wr32(E1000_SPQF(3), htons(PTP_PORT));
 531                         ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
 532                 }
 533                 wr32(E1000_FTQF(3), ftqf);
 534         } else {
 535                 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
 536         }
 537         wrfl();
 538
 539         /* clear TX/RX time stamp registers, just to be sure */
 540         regval = rd32(E1000_TXSTMPH);
 541         regval = rd32(E1000_RXSTMPH);
 542
 543         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 544                 -EFAULT : 0;
 545 }
 546
 547 void igb_ptp_init(struct igb_adapter *adapter)
 548 {
 549         struct e1000_hw *hw = &adapter->hw;
 550         struct net_device *netdev = adapter->netdev;
 551
 552         switch (hw->mac.type) {
 553         case e1000_i210:
 554         case e1000_i211:
 555         case e1000_i350:
 556         case e1000_82580:
 557                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 558                 adapter->ptp_caps.owner = THIS_MODULE;
 559                 adapter->ptp_caps.max_adj = 62499999;
 560                 adapter->ptp_caps.n_ext_ts = 0;
 561                 adapter->ptp_caps.pps = 0;
 562                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
 563                 adapter->ptp_caps.adjtime = igb_ptp_adjtime;
 564                 adapter->ptp_caps.gettime = igb_ptp_gettime;
 565                 adapter->ptp_caps.settime = igb_ptp_settime;
 566                 adapter->ptp_caps.enable = igb_ptp_enable;
 567                 adapter->cc.read = igb_ptp_read_82580;
 568                 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);
 569                 adapter->cc.mult = 1;
 570                 adapter->cc.shift = 0;
 571                 /* Enable the timer functions by clearing bit 31. */
 572                 wr32(E1000_TSAUXC, 0x0);
 573                 break;
 574         case e1000_82576:
 575                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 576                 adapter->ptp_caps.owner = THIS_MODULE;
 577                 adapter->ptp_caps.max_adj = 1000000000;
 578                 adapter->ptp_caps.n_ext_ts = 0;
 579                 adapter->ptp_caps.pps = 0;
 580                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
 581                 adapter->ptp_caps.adjtime = igb_ptp_adjtime;
 582                 adapter->ptp_caps.gettime = igb_ptp_gettime;
 583                 adapter->ptp_caps.settime = igb_ptp_settime;
 584                 adapter->ptp_caps.enable = igb_ptp_enable;
 585                 adapter->cc.read = igb_ptp_read_82576;
 586                 adapter->cc.mask = CLOCKSOURCE_MASK(64);
 587                 adapter->cc.mult = 1;
 588                 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
 589                 /* Dial the nominal frequency. */
 590                 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
 591                 break;
 592         default:
 593                 adapter->ptp_clock = NULL;
 594                 return;
 595         }
 596
 597         wrfl();
 598
 599         timecounter_init(&adapter->tc, &adapter->cc,
 600                          ktime_to_ns(ktime_get_real()));
 601
 602         INIT_DELAYED_WORK(&adapter->ptp_overflow_work, igb_ptp_overflow_check);
 603
 604         spin_lock_init(&adapter->tmreg_lock);
 605
 606         schedule_delayed_work(&adapter->ptp_overflow_work,
 607                               IGB_SYSTIM_OVERFLOW_PERIOD);
 608
 609         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps);
 610         if (IS_ERR(adapter->ptp_clock)) {
 611                 adapter->ptp_clock = NULL;
 612                 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
 613         } else
 614                 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
 615                          adapter->netdev->name);
 616 }
 617
 618 /**
 619  * igb_ptp_stop - Disable PTP device and stop the overflow check.
 620  * @adapter: Board private structure.
 621  *
 622  * This function stops the PTP support and cancels the delayed work.
 623  **/
 624 void igb_ptp_stop(struct igb_adapter *adapter)
 625 {
 626         switch (adapter->hw.mac.type) {
 627         case e1000_i211:
 628         case e1000_i210:
 629         case e1000_i350:
 630         case e1000_82580:
 631         case e1000_82576:
 632                 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
 633                 break;
 634         default:
 635                 return;
 636         }
 637
 638         if (adapter->ptp_clock) {
 639                 ptp_clock_unregister(adapter->ptp_clock);
 640                 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
 641                          adapter->netdev->name);
 642         }
 643 }