2 * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
4 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/pci.h>
26 #define INCVALUE_MASK 0x7fffffff
27 #define ISGN 0x80000000
30 * The 82580 timesync updates the system timer every 8ns by 8ns,
31 * and this update value cannot be reprogrammed.
33 * Neither the 82576 nor the 82580 offer registers wide enough to hold
34 * nanoseconds time values for very long. For the 82580, SYSTIM always
35 * counts nanoseconds, but the upper 24 bits are not availible. The
36 * frequency is adjusted by changing the 32 bit fractional nanoseconds
39 * For the 82576, the SYSTIM register time unit is affect by the
40 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
41 * field are needed to provide the nominal 16 nanosecond period,
42 * leaving 19 bits for fractional nanoseconds.
44 * We scale the NIC clock cycle by a large factor so that relatively
45 * small clock corrections can be added or subtracted at each clock
46 * tick. The drawbacks of a large factor are a) that the clock
47 * register overflows more quickly (not such a big deal) and b) that
48 * the increment per tick has to fit into 24 bits. As a result we
49 * need to use a shift of 19 so we can fit a value of 16 into the
54 * +--------------+ +---+---+------+
55 * 82576 | 32 | | 8 | 5 | 19 |
56 * +--------------+ +---+---+------+
57 * \________ 45 bits _______/ fract
59 * +----------+---+ +--------------+
60 * 82580 | 24 | 8 | | 32 |
61 * +----------+---+ +--------------+
62 * reserved \______ 40 bits _____/
65 * The 45 bit 82576 SYSTIM overflows every
66 * 2^45 * 10^-9 / 3600 = 9.77 hours.
68 * The 40 bit 82580 SYSTIM overflows every
69 * 2^40 * 10^-9 / 60 = 18.3 minutes.
72 #define IGB_OVERFLOW_PERIOD (HZ * 60 * 9)
73 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
74 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
75 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
76 #define IGB_NBITS_82580 40
79 * SYSTIM read access for the 82576
82 static cycle_t
igb_82576_systim_read(const struct cyclecounter
*cc
)
86 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
87 struct e1000_hw
*hw
= &igb
->hw
;
89 lo
= rd32(E1000_SYSTIML
);
90 hi
= rd32(E1000_SYSTIMH
);
92 val
= ((u64
) hi
) << 32;
99 * SYSTIM read access for the 82580
102 static cycle_t
igb_82580_systim_read(const struct cyclecounter
*cc
)
106 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
107 struct e1000_hw
*hw
= &igb
->hw
;
110 * The timestamp latches on lowest register read. For the 82580
111 * the lowest register is SYSTIMR instead of SYSTIML. However we only
112 * need to provide nanosecond resolution, so we just ignore it.
114 jk
= rd32(E1000_SYSTIMR
);
115 lo
= rd32(E1000_SYSTIML
);
116 hi
= rd32(E1000_SYSTIMH
);
118 val
= ((u64
) hi
) << 32;
125 * PTP clock operations
128 static int ptp_82576_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
133 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
, caps
);
134 struct e1000_hw
*hw
= &igb
->hw
;
142 rate
= div_u64(rate
, 1953125);
144 incvalue
= 16 << IGB_82576_TSYNC_SHIFT
;
151 wr32(E1000_TIMINCA
, INCPERIOD_82576
| (incvalue
& INCVALUE_82576_MASK
));
156 static int ptp_82580_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
161 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
, caps
);
162 struct e1000_hw
*hw
= &igb
->hw
;
170 rate
= div_u64(rate
, 1953125);
172 inca
= rate
& INCVALUE_MASK
;
176 wr32(E1000_TIMINCA
, inca
);
181 static int igb_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
185 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
, caps
);
187 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
189 now
= timecounter_read(&igb
->tc
);
191 timecounter_init(&igb
->tc
, &igb
->cc
, now
);
193 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
198 static int igb_gettime(struct ptp_clock_info
*ptp
, struct timespec
*ts
)
203 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
, caps
);
205 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
207 ns
= timecounter_read(&igb
->tc
);
209 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
211 ts
->tv_sec
= div_u64_rem(ns
, 1000000000, &remainder
);
212 ts
->tv_nsec
= remainder
;
217 static int igb_settime(struct ptp_clock_info
*ptp
, const struct timespec
*ts
)
221 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
, caps
);
223 ns
= ts
->tv_sec
* 1000000000ULL;
226 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
228 timecounter_init(&igb
->tc
, &igb
->cc
, ns
);
230 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
235 static int ptp_82576_enable(struct ptp_clock_info
*ptp
,
236 struct ptp_clock_request
*rq
, int on
)
241 static int ptp_82580_enable(struct ptp_clock_info
*ptp
,
242 struct ptp_clock_request
*rq
, int on
)
247 static void igb_overflow_check(struct work_struct
*work
)
250 struct igb_adapter
*igb
=
251 container_of(work
, struct igb_adapter
, overflow_work
.work
);
253 igb_gettime(&igb
->caps
, &ts
);
255 pr_debug("igb overflow check at %ld.%09lu\n", ts
.tv_sec
, ts
.tv_nsec
);
257 schedule_delayed_work(&igb
->overflow_work
, IGB_OVERFLOW_PERIOD
);
260 void igb_ptp_init(struct igb_adapter
*adapter
)
262 struct e1000_hw
*hw
= &adapter
->hw
;
264 switch (hw
->mac
.type
) {
269 adapter
->caps
.owner
= THIS_MODULE
;
270 strcpy(adapter
->caps
.name
, "igb-82580");
271 adapter
->caps
.max_adj
= 62499999;
272 adapter
->caps
.n_ext_ts
= 0;
273 adapter
->caps
.pps
= 0;
274 adapter
->caps
.adjfreq
= ptp_82580_adjfreq
;
275 adapter
->caps
.adjtime
= igb_adjtime
;
276 adapter
->caps
.gettime
= igb_gettime
;
277 adapter
->caps
.settime
= igb_settime
;
278 adapter
->caps
.enable
= ptp_82580_enable
;
279 adapter
->cc
.read
= igb_82580_systim_read
;
280 adapter
->cc
.mask
= CLOCKSOURCE_MASK(IGB_NBITS_82580
);
281 adapter
->cc
.mult
= 1;
282 adapter
->cc
.shift
= 0;
283 /* Enable the timer functions by clearing bit 31. */
284 wr32(E1000_TSAUXC
, 0x0);
288 adapter
->caps
.owner
= THIS_MODULE
;
289 strcpy(adapter
->caps
.name
, "igb-82576");
290 adapter
->caps
.max_adj
= 1000000000;
291 adapter
->caps
.n_ext_ts
= 0;
292 adapter
->caps
.pps
= 0;
293 adapter
->caps
.adjfreq
= ptp_82576_adjfreq
;
294 adapter
->caps
.adjtime
= igb_adjtime
;
295 adapter
->caps
.gettime
= igb_gettime
;
296 adapter
->caps
.settime
= igb_settime
;
297 adapter
->caps
.enable
= ptp_82576_enable
;
298 adapter
->cc
.read
= igb_82576_systim_read
;
299 adapter
->cc
.mask
= CLOCKSOURCE_MASK(64);
300 adapter
->cc
.mult
= 1;
301 adapter
->cc
.shift
= IGB_82576_TSYNC_SHIFT
;
302 /* Dial the nominal frequency. */
303 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
307 adapter
->ptp_clock
= NULL
;
313 timecounter_init(&adapter
->tc
, &adapter
->cc
,
314 ktime_to_ns(ktime_get_real()));
316 INIT_DELAYED_WORK(&adapter
->overflow_work
, igb_overflow_check
);
318 spin_lock_init(&adapter
->tmreg_lock
);
320 schedule_delayed_work(&adapter
->overflow_work
, IGB_OVERFLOW_PERIOD
);
322 adapter
->ptp_clock
= ptp_clock_register(&adapter
->caps
);
323 if (IS_ERR(adapter
->ptp_clock
)) {
324 adapter
->ptp_clock
= NULL
;
325 dev_err(&adapter
->pdev
->dev
, "ptp_clock_register failed\n");
327 dev_info(&adapter
->pdev
->dev
, "added PHC on %s\n",
328 adapter
->netdev
->name
);
331 void igb_ptp_remove(struct igb_adapter
*adapter
)
333 switch (adapter
->hw
.mac
.type
) {
339 cancel_delayed_work_sync(&adapter
->overflow_work
);
345 if (adapter
->ptp_clock
) {
346 ptp_clock_unregister(adapter
->ptp_clock
);
347 dev_info(&adapter
->pdev
->dev
, "removed PHC on %s\n",
348 adapter
->netdev
->name
);
353 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
354 * @adapter: board private structure
355 * @hwtstamps: timestamp structure to update
356 * @systim: unsigned 64bit system time value.
358 * We need to convert the system time value stored in the RX/TXSTMP registers
359 * into a hwtstamp which can be used by the upper level timestamping functions.
361 * The 'tmreg_lock' spinlock is used to protect the consistency of the
362 * system time value. This is needed because reading the 64 bit time
363 * value involves reading two (or three) 32 bit registers. The first
364 * read latches the value. Ditto for writing.
366 * In addition, here have extended the system time with an overflow
367 * counter in software.
369 void igb_systim_to_hwtstamp(struct igb_adapter
*adapter
,
370 struct skb_shared_hwtstamps
*hwtstamps
,
376 switch (adapter
->hw
.mac
.type
) {
387 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
389 ns
= timecounter_cyc2time(&adapter
->tc
, systim
);
391 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
393 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
394 hwtstamps
->hwtstamp
= ns_to_ktime(ns
);
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