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ixgbe, ixgbevf: Add new mbox API xcast mode
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe.h
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #ifndef _IXGBE_H_
30 #define _IXGBE_H_
31
32 #include <linux/bitops.h>
33 #include <linux/types.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/cpumask.h>
37 #include <linux/aer.h>
38 #include <linux/if_vlan.h>
39 #include <linux/jiffies.h>
40
41 #include <linux/timecounter.h>
42 #include <linux/net_tstamp.h>
43 #include <linux/ptp_clock_kernel.h>
44
45 #include "ixgbe_type.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb.h"
48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
49 #define IXGBE_FCOE
50 #include "ixgbe_fcoe.h"
51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
52 #ifdef CONFIG_IXGBE_DCA
53 #include <linux/dca.h>
54 #endif
55
56 #include <net/busy_poll.h>
57
58 #ifdef CONFIG_NET_RX_BUSY_POLL
59 #define BP_EXTENDED_STATS
60 #endif
61 /* common prefix used by pr_<> macros */
62 #undef pr_fmt
63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
64
65 /* TX/RX descriptor defines */
66 #define IXGBE_DEFAULT_TXD 512
67 #define IXGBE_DEFAULT_TX_WORK 256
68 #define IXGBE_MAX_TXD 4096
69 #define IXGBE_MIN_TXD 64
70
71 #if (PAGE_SIZE < 8192)
72 #define IXGBE_DEFAULT_RXD 512
73 #else
74 #define IXGBE_DEFAULT_RXD 128
75 #endif
76 #define IXGBE_MAX_RXD 4096
77 #define IXGBE_MIN_RXD 64
78
79 #define IXGBE_ETH_P_LLDP 0x88CC
80
81 /* flow control */
82 #define IXGBE_MIN_FCRTL 0x40
83 #define IXGBE_MAX_FCRTL 0x7FF80
84 #define IXGBE_MIN_FCRTH 0x600
85 #define IXGBE_MAX_FCRTH 0x7FFF0
86 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
87 #define IXGBE_MIN_FCPAUSE 0
88 #define IXGBE_MAX_FCPAUSE 0xFFFF
89
90 /* Supported Rx Buffer Sizes */
91 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
92 #define IXGBE_RXBUFFER_2K 2048
93 #define IXGBE_RXBUFFER_3K 3072
94 #define IXGBE_RXBUFFER_4K 4096
95 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
96
97 /*
98 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
99 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
100 * this adds up to 448 bytes of extra data.
101 *
102 * Since netdev_alloc_skb now allocates a page fragment we can use a value
103 * of 256 and the resultant skb will have a truesize of 960 or less.
104 */
105 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
106
107 /* How many Rx Buffers do we bundle into one write to the hardware ? */
108 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
109
110 enum ixgbe_tx_flags {
111 /* cmd_type flags */
112 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
113 IXGBE_TX_FLAGS_TSO = 0x02,
114 IXGBE_TX_FLAGS_TSTAMP = 0x04,
115
116 /* olinfo flags */
117 IXGBE_TX_FLAGS_CC = 0x08,
118 IXGBE_TX_FLAGS_IPV4 = 0x10,
119 IXGBE_TX_FLAGS_CSUM = 0x20,
120
121 /* software defined flags */
122 IXGBE_TX_FLAGS_SW_VLAN = 0x40,
123 IXGBE_TX_FLAGS_FCOE = 0x80,
124 };
125
126 /* VLAN info */
127 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
128 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
129 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
130 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
131
132 #define IXGBE_MAX_VF_MC_ENTRIES 30
133 #define IXGBE_MAX_VF_FUNCTIONS 64
134 #define IXGBE_MAX_VFTA_ENTRIES 128
135 #define MAX_EMULATION_MAC_ADDRS 16
136 #define IXGBE_MAX_PF_MACVLANS 15
137 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
138 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
139 #define IXGBE_X540_VF_DEVICE_ID 0x1515
140
141 struct vf_data_storage {
142 unsigned char vf_mac_addresses[ETH_ALEN];
143 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
144 u16 num_vf_mc_hashes;
145 u16 default_vf_vlan_id;
146 u16 vlans_enabled;
147 bool clear_to_send;
148 bool pf_set_mac;
149 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
150 u16 pf_qos;
151 u16 tx_rate;
152 u16 vlan_count;
153 u8 spoofchk_enabled;
154 bool rss_query_enabled;
155 u8 trusted;
156 int xcast_mode;
157 unsigned int vf_api;
158 };
159
160 enum ixgbevf_xcast_modes {
161 IXGBEVF_XCAST_MODE_NONE = 0,
162 IXGBEVF_XCAST_MODE_MULTI,
163 IXGBEVF_XCAST_MODE_ALLMULTI,
164 };
165
166 struct vf_macvlans {
167 struct list_head l;
168 int vf;
169 bool free;
170 bool is_macvlan;
171 u8 vf_macvlan[ETH_ALEN];
172 };
173
174 #define IXGBE_MAX_TXD_PWR 14
175 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
176
177 /* Tx Descriptors needed, worst case */
178 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
179 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
180
181 /* wrapper around a pointer to a socket buffer,
182 * so a DMA handle can be stored along with the buffer */
183 struct ixgbe_tx_buffer {
184 union ixgbe_adv_tx_desc *next_to_watch;
185 unsigned long time_stamp;
186 struct sk_buff *skb;
187 unsigned int bytecount;
188 unsigned short gso_segs;
189 __be16 protocol;
190 DEFINE_DMA_UNMAP_ADDR(dma);
191 DEFINE_DMA_UNMAP_LEN(len);
192 u32 tx_flags;
193 };
194
195 struct ixgbe_rx_buffer {
196 struct sk_buff *skb;
197 dma_addr_t dma;
198 struct page *page;
199 unsigned int page_offset;
200 };
201
202 struct ixgbe_queue_stats {
203 u64 packets;
204 u64 bytes;
205 #ifdef BP_EXTENDED_STATS
206 u64 yields;
207 u64 misses;
208 u64 cleaned;
209 #endif /* BP_EXTENDED_STATS */
210 };
211
212 struct ixgbe_tx_queue_stats {
213 u64 restart_queue;
214 u64 tx_busy;
215 u64 tx_done_old;
216 };
217
218 struct ixgbe_rx_queue_stats {
219 u64 rsc_count;
220 u64 rsc_flush;
221 u64 non_eop_descs;
222 u64 alloc_rx_page_failed;
223 u64 alloc_rx_buff_failed;
224 u64 csum_err;
225 };
226
227 enum ixgbe_ring_state_t {
228 __IXGBE_TX_FDIR_INIT_DONE,
229 __IXGBE_TX_XPS_INIT_DONE,
230 __IXGBE_TX_DETECT_HANG,
231 __IXGBE_HANG_CHECK_ARMED,
232 __IXGBE_RX_RSC_ENABLED,
233 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
234 __IXGBE_RX_FCOE,
235 };
236
237 struct ixgbe_fwd_adapter {
238 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
239 struct net_device *netdev;
240 struct ixgbe_adapter *real_adapter;
241 unsigned int tx_base_queue;
242 unsigned int rx_base_queue;
243 int pool;
244 };
245
246 #define check_for_tx_hang(ring) \
247 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
248 #define set_check_for_tx_hang(ring) \
249 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
250 #define clear_check_for_tx_hang(ring) \
251 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
252 #define ring_is_rsc_enabled(ring) \
253 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
254 #define set_ring_rsc_enabled(ring) \
255 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
256 #define clear_ring_rsc_enabled(ring) \
257 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
258 struct ixgbe_ring {
259 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
260 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
261 struct net_device *netdev; /* netdev ring belongs to */
262 struct device *dev; /* device for DMA mapping */
263 struct ixgbe_fwd_adapter *l2_accel_priv;
264 void *desc; /* descriptor ring memory */
265 union {
266 struct ixgbe_tx_buffer *tx_buffer_info;
267 struct ixgbe_rx_buffer *rx_buffer_info;
268 };
269 unsigned long state;
270 u8 __iomem *tail;
271 dma_addr_t dma; /* phys. address of descriptor ring */
272 unsigned int size; /* length in bytes */
273
274 u16 count; /* amount of descriptors */
275
276 u8 queue_index; /* needed for multiqueue queue management */
277 u8 reg_idx; /* holds the special value that gets
278 * the hardware register offset
279 * associated with this ring, which is
280 * different for DCB and RSS modes
281 */
282 u16 next_to_use;
283 u16 next_to_clean;
284
285 union {
286 u16 next_to_alloc;
287 struct {
288 u8 atr_sample_rate;
289 u8 atr_count;
290 };
291 };
292
293 u8 dcb_tc;
294 struct ixgbe_queue_stats stats;
295 struct u64_stats_sync syncp;
296 union {
297 struct ixgbe_tx_queue_stats tx_stats;
298 struct ixgbe_rx_queue_stats rx_stats;
299 };
300 } ____cacheline_internodealigned_in_smp;
301
302 enum ixgbe_ring_f_enum {
303 RING_F_NONE = 0,
304 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
305 RING_F_RSS,
306 RING_F_FDIR,
307 #ifdef IXGBE_FCOE
308 RING_F_FCOE,
309 #endif /* IXGBE_FCOE */
310
311 RING_F_ARRAY_SIZE /* must be last in enum set */
312 };
313
314 #define IXGBE_MAX_RSS_INDICES 16
315 #define IXGBE_MAX_RSS_INDICES_X550 64
316 #define IXGBE_MAX_VMDQ_INDICES 64
317 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
318 #define IXGBE_MAX_FCOE_INDICES 8
319 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
320 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
321 #define IXGBE_MAX_L2A_QUEUES 4
322 #define IXGBE_BAD_L2A_QUEUE 3
323 #define IXGBE_MAX_MACVLANS 31
324 #define IXGBE_MAX_DCBMACVLANS 8
325
326 struct ixgbe_ring_feature {
327 u16 limit; /* upper limit on feature indices */
328 u16 indices; /* current value of indices */
329 u16 mask; /* Mask used for feature to ring mapping */
330 u16 offset; /* offset to start of feature */
331 } ____cacheline_internodealigned_in_smp;
332
333 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
334 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
335 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
336
337 /*
338 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
339 * this is twice the size of a half page we need to double the page order
340 * for FCoE enabled Rx queues.
341 */
342 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
343 {
344 #ifdef IXGBE_FCOE
345 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
346 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
347 IXGBE_RXBUFFER_3K;
348 #endif
349 return IXGBE_RXBUFFER_2K;
350 }
351
352 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
353 {
354 #ifdef IXGBE_FCOE
355 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
356 return (PAGE_SIZE < 8192) ? 1 : 0;
357 #endif
358 return 0;
359 }
360 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
361
362 struct ixgbe_ring_container {
363 struct ixgbe_ring *ring; /* pointer to linked list of rings */
364 unsigned int total_bytes; /* total bytes processed this int */
365 unsigned int total_packets; /* total packets processed this int */
366 u16 work_limit; /* total work allowed per interrupt */
367 u8 count; /* total number of rings in vector */
368 u8 itr; /* current ITR setting for ring */
369 };
370
371 /* iterator for handling rings in ring container */
372 #define ixgbe_for_each_ring(pos, head) \
373 for (pos = (head).ring; pos != NULL; pos = pos->next)
374
375 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
376 ? 8 : 1)
377 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
378
379 /* MAX_Q_VECTORS of these are allocated,
380 * but we only use one per queue-specific vector.
381 */
382 struct ixgbe_q_vector {
383 struct ixgbe_adapter *adapter;
384 #ifdef CONFIG_IXGBE_DCA
385 int cpu; /* CPU for DCA */
386 #endif
387 u16 v_idx; /* index of q_vector within array, also used for
388 * finding the bit in EICR and friends that
389 * represents the vector for this ring */
390 u16 itr; /* Interrupt throttle rate written to EITR */
391 struct ixgbe_ring_container rx, tx;
392
393 struct napi_struct napi;
394 cpumask_t affinity_mask;
395 int numa_node;
396 struct rcu_head rcu; /* to avoid race with update stats on free */
397 char name[IFNAMSIZ + 9];
398
399 #ifdef CONFIG_NET_RX_BUSY_POLL
400 atomic_t state;
401 #endif /* CONFIG_NET_RX_BUSY_POLL */
402
403 /* for dynamic allocation of rings associated with this q_vector */
404 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
405 };
406
407 #ifdef CONFIG_NET_RX_BUSY_POLL
408 enum ixgbe_qv_state_t {
409 IXGBE_QV_STATE_IDLE = 0,
410 IXGBE_QV_STATE_NAPI,
411 IXGBE_QV_STATE_POLL,
412 IXGBE_QV_STATE_DISABLE
413 };
414
415 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
416 {
417 /* reset state to idle */
418 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
419 }
420
421 /* called from the device poll routine to get ownership of a q_vector */
422 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
423 {
424 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
425 IXGBE_QV_STATE_NAPI);
426 #ifdef BP_EXTENDED_STATS
427 if (rc != IXGBE_QV_STATE_IDLE)
428 q_vector->tx.ring->stats.yields++;
429 #endif
430
431 return rc == IXGBE_QV_STATE_IDLE;
432 }
433
434 /* returns true is someone tried to get the qv while napi had it */
435 static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
436 {
437 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI);
438
439 /* flush any outstanding Rx frames */
440 if (q_vector->napi.gro_list)
441 napi_gro_flush(&q_vector->napi, false);
442
443 /* reset state to idle */
444 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
445 }
446
447 /* called from ixgbe_low_latency_poll() */
448 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
449 {
450 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
451 IXGBE_QV_STATE_POLL);
452 #ifdef BP_EXTENDED_STATS
453 if (rc != IXGBE_QV_STATE_IDLE)
454 q_vector->tx.ring->stats.yields++;
455 #endif
456 return rc == IXGBE_QV_STATE_IDLE;
457 }
458
459 /* returns true if someone tried to get the qv while it was locked */
460 static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
461 {
462 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL);
463
464 /* reset state to idle */
465 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
466 }
467
468 /* true if a socket is polling, even if it did not get the lock */
469 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
470 {
471 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL;
472 }
473
474 /* false if QV is currently owned */
475 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
476 {
477 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
478 IXGBE_QV_STATE_DISABLE);
479
480 return rc == IXGBE_QV_STATE_IDLE;
481 }
482
483 #else /* CONFIG_NET_RX_BUSY_POLL */
484 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
485 {
486 }
487
488 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
489 {
490 return true;
491 }
492
493 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
494 {
495 return false;
496 }
497
498 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
499 {
500 return false;
501 }
502
503 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
504 {
505 return false;
506 }
507
508 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
509 {
510 return false;
511 }
512
513 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
514 {
515 return true;
516 }
517
518 #endif /* CONFIG_NET_RX_BUSY_POLL */
519
520 #ifdef CONFIG_IXGBE_HWMON
521
522 #define IXGBE_HWMON_TYPE_LOC 0
523 #define IXGBE_HWMON_TYPE_TEMP 1
524 #define IXGBE_HWMON_TYPE_CAUTION 2
525 #define IXGBE_HWMON_TYPE_MAX 3
526
527 struct hwmon_attr {
528 struct device_attribute dev_attr;
529 struct ixgbe_hw *hw;
530 struct ixgbe_thermal_diode_data *sensor;
531 char name[12];
532 };
533
534 struct hwmon_buff {
535 struct attribute_group group;
536 const struct attribute_group *groups[2];
537 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
538 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
539 unsigned int n_hwmon;
540 };
541 #endif /* CONFIG_IXGBE_HWMON */
542
543 /*
544 * microsecond values for various ITR rates shifted by 2 to fit itr register
545 * with the first 3 bits reserved 0
546 */
547 #define IXGBE_MIN_RSC_ITR 24
548 #define IXGBE_100K_ITR 40
549 #define IXGBE_20K_ITR 200
550 #define IXGBE_12K_ITR 336
551
552 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
553 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
554 const u32 stat_err_bits)
555 {
556 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
557 }
558
559 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
560 {
561 u16 ntc = ring->next_to_clean;
562 u16 ntu = ring->next_to_use;
563
564 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
565 }
566
567 #define IXGBE_RX_DESC(R, i) \
568 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
569 #define IXGBE_TX_DESC(R, i) \
570 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
571 #define IXGBE_TX_CTXTDESC(R, i) \
572 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
573
574 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
575 #ifdef IXGBE_FCOE
576 /* Use 3K as the baby jumbo frame size for FCoE */
577 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
578 #endif /* IXGBE_FCOE */
579
580 #define OTHER_VECTOR 1
581 #define NON_Q_VECTORS (OTHER_VECTOR)
582
583 #define MAX_MSIX_VECTORS_82599 64
584 #define MAX_Q_VECTORS_82599 64
585 #define MAX_MSIX_VECTORS_82598 18
586 #define MAX_Q_VECTORS_82598 16
587
588 struct ixgbe_mac_addr {
589 u8 addr[ETH_ALEN];
590 u16 queue;
591 u16 state; /* bitmask */
592 };
593 #define IXGBE_MAC_STATE_DEFAULT 0x1
594 #define IXGBE_MAC_STATE_MODIFIED 0x2
595 #define IXGBE_MAC_STATE_IN_USE 0x4
596
597 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
598 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
599
600 #define MIN_MSIX_Q_VECTORS 1
601 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
602
603 /* default to trying for four seconds */
604 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
605 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
606
607 /* board specific private data structure */
608 struct ixgbe_adapter {
609 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
610 /* OS defined structs */
611 struct net_device *netdev;
612 struct pci_dev *pdev;
613
614 unsigned long state;
615
616 /* Some features need tri-state capability,
617 * thus the additional *_CAPABLE flags.
618 */
619 u32 flags;
620 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
621 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
622 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
623 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
624 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
625 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
626 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
627 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
628 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
629 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
630 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
631 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
632 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
633 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
634 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
635 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
636 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
637 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
638 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
639 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
640 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
641 #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24)
642
643 u32 flags2;
644 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
645 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
646 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
647 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
648 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
649 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
650 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
651 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
652 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
653 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
654 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
655 #define IXGBE_FLAG2_PHY_INTERRUPT (u32)(1 << 11)
656 #ifdef CONFIG_IXGBE_VXLAN
657 #define IXGBE_FLAG2_VXLAN_REREG_NEEDED BIT(12)
658 #endif
659
660 /* Tx fast path data */
661 int num_tx_queues;
662 u16 tx_itr_setting;
663 u16 tx_work_limit;
664
665 /* Rx fast path data */
666 int num_rx_queues;
667 u16 rx_itr_setting;
668
669 /* TX */
670 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
671
672 u64 restart_queue;
673 u64 lsc_int;
674 u32 tx_timeout_count;
675
676 /* RX */
677 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
678 int num_rx_pools; /* == num_rx_queues in 82598 */
679 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
680 u64 hw_csum_rx_error;
681 u64 hw_rx_no_dma_resources;
682 u64 rsc_total_count;
683 u64 rsc_total_flush;
684 u64 non_eop_descs;
685 u32 alloc_rx_page_failed;
686 u32 alloc_rx_buff_failed;
687
688 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
689
690 /* DCB parameters */
691 struct ieee_pfc *ixgbe_ieee_pfc;
692 struct ieee_ets *ixgbe_ieee_ets;
693 struct ixgbe_dcb_config dcb_cfg;
694 struct ixgbe_dcb_config temp_dcb_cfg;
695 u8 dcb_set_bitmap;
696 u8 dcbx_cap;
697 enum ixgbe_fc_mode last_lfc_mode;
698
699 int num_q_vectors; /* current number of q_vectors for device */
700 int max_q_vectors; /* true count of q_vectors for device */
701 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
702 struct msix_entry *msix_entries;
703
704 u32 test_icr;
705 struct ixgbe_ring test_tx_ring;
706 struct ixgbe_ring test_rx_ring;
707
708 /* structs defined in ixgbe_hw.h */
709 struct ixgbe_hw hw;
710 u16 msg_enable;
711 struct ixgbe_hw_stats stats;
712
713 u64 tx_busy;
714 unsigned int tx_ring_count;
715 unsigned int rx_ring_count;
716
717 u32 link_speed;
718 bool link_up;
719 unsigned long sfp_poll_time;
720 unsigned long link_check_timeout;
721
722 struct timer_list service_timer;
723 struct work_struct service_task;
724
725 struct hlist_head fdir_filter_list;
726 unsigned long fdir_overflow; /* number of times ATR was backed off */
727 union ixgbe_atr_input fdir_mask;
728 int fdir_filter_count;
729 u32 fdir_pballoc;
730 u32 atr_sample_rate;
731 spinlock_t fdir_perfect_lock;
732
733 #ifdef IXGBE_FCOE
734 struct ixgbe_fcoe fcoe;
735 #endif /* IXGBE_FCOE */
736 u8 __iomem *io_addr; /* Mainly for iounmap use */
737 u32 wol;
738
739 u16 bridge_mode;
740
741 u16 eeprom_verh;
742 u16 eeprom_verl;
743 u16 eeprom_cap;
744
745 u32 interrupt_event;
746 u32 led_reg;
747
748 struct ptp_clock *ptp_clock;
749 struct ptp_clock_info ptp_caps;
750 struct work_struct ptp_tx_work;
751 struct sk_buff *ptp_tx_skb;
752 struct hwtstamp_config tstamp_config;
753 unsigned long ptp_tx_start;
754 unsigned long last_overflow_check;
755 unsigned long last_rx_ptp_check;
756 unsigned long last_rx_timestamp;
757 spinlock_t tmreg_lock;
758 struct cyclecounter cc;
759 struct timecounter tc;
760 u32 base_incval;
761
762 /* SR-IOV */
763 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
764 unsigned int num_vfs;
765 struct vf_data_storage *vfinfo;
766 int vf_rate_link_speed;
767 struct vf_macvlans vf_mvs;
768 struct vf_macvlans *mv_list;
769
770 u32 timer_event_accumulator;
771 u32 vferr_refcount;
772 struct ixgbe_mac_addr *mac_table;
773 #ifdef CONFIG_IXGBE_VXLAN
774 u16 vxlan_port;
775 #endif
776 struct kobject *info_kobj;
777 #ifdef CONFIG_IXGBE_HWMON
778 struct hwmon_buff *ixgbe_hwmon_buff;
779 #endif /* CONFIG_IXGBE_HWMON */
780 #ifdef CONFIG_DEBUG_FS
781 struct dentry *ixgbe_dbg_adapter;
782 #endif /*CONFIG_DEBUG_FS*/
783
784 u8 default_up;
785 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */
786
787 /* maximum number of RETA entries among all devices supported by ixgbe
788 * driver: currently it's x550 device in non-SRIOV mode
789 */
790 #define IXGBE_MAX_RETA_ENTRIES 512
791 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
792
793 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
794 u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)];
795 };
796
797 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
798 {
799 switch (adapter->hw.mac.type) {
800 case ixgbe_mac_82598EB:
801 case ixgbe_mac_82599EB:
802 case ixgbe_mac_X540:
803 return IXGBE_MAX_RSS_INDICES;
804 case ixgbe_mac_X550:
805 case ixgbe_mac_X550EM_x:
806 return IXGBE_MAX_RSS_INDICES_X550;
807 default:
808 return 0;
809 }
810 }
811
812 struct ixgbe_fdir_filter {
813 struct hlist_node fdir_node;
814 union ixgbe_atr_input filter;
815 u16 sw_idx;
816 u16 action;
817 };
818
819 enum ixgbe_state_t {
820 __IXGBE_TESTING,
821 __IXGBE_RESETTING,
822 __IXGBE_DOWN,
823 __IXGBE_DISABLED,
824 __IXGBE_REMOVING,
825 __IXGBE_SERVICE_SCHED,
826 __IXGBE_SERVICE_INITED,
827 __IXGBE_IN_SFP_INIT,
828 __IXGBE_PTP_RUNNING,
829 __IXGBE_PTP_TX_IN_PROGRESS,
830 };
831
832 struct ixgbe_cb {
833 union { /* Union defining head/tail partner */
834 struct sk_buff *head;
835 struct sk_buff *tail;
836 };
837 dma_addr_t dma;
838 u16 append_cnt;
839 bool page_released;
840 };
841 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
842
843 enum ixgbe_boards {
844 board_82598,
845 board_82599,
846 board_X540,
847 board_X550,
848 board_X550EM_x,
849 };
850
851 extern struct ixgbe_info ixgbe_82598_info;
852 extern struct ixgbe_info ixgbe_82599_info;
853 extern struct ixgbe_info ixgbe_X540_info;
854 extern struct ixgbe_info ixgbe_X550_info;
855 extern struct ixgbe_info ixgbe_X550EM_x_info;
856 #ifdef CONFIG_IXGBE_DCB
857 extern const struct dcbnl_rtnl_ops dcbnl_ops;
858 #endif
859
860 extern char ixgbe_driver_name[];
861 extern const char ixgbe_driver_version[];
862 #ifdef IXGBE_FCOE
863 extern char ixgbe_default_device_descr[];
864 #endif /* IXGBE_FCOE */
865
866 void ixgbe_up(struct ixgbe_adapter *adapter);
867 void ixgbe_down(struct ixgbe_adapter *adapter);
868 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
869 void ixgbe_reset(struct ixgbe_adapter *adapter);
870 void ixgbe_set_ethtool_ops(struct net_device *netdev);
871 int ixgbe_setup_rx_resources(struct ixgbe_ring *);
872 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
873 void ixgbe_free_rx_resources(struct ixgbe_ring *);
874 void ixgbe_free_tx_resources(struct ixgbe_ring *);
875 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
876 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
877 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
878 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
879 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
880 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
881 u16 subdevice_id);
882 #ifdef CONFIG_PCI_IOV
883 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
884 #endif
885 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
886 u8 *addr, u16 queue);
887 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
888 u8 *addr, u16 queue);
889 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
890 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
891 struct ixgbe_ring *);
892 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
893 struct ixgbe_tx_buffer *);
894 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
895 void ixgbe_write_eitr(struct ixgbe_q_vector *);
896 int ixgbe_poll(struct napi_struct *napi, int budget);
897 int ethtool_ioctl(struct ifreq *ifr);
898 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
899 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
900 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
901 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
902 union ixgbe_atr_hash_dword input,
903 union ixgbe_atr_hash_dword common,
904 u8 queue);
905 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
906 union ixgbe_atr_input *input_mask);
907 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
908 union ixgbe_atr_input *input,
909 u16 soft_id, u8 queue);
910 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
911 union ixgbe_atr_input *input,
912 u16 soft_id);
913 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
914 union ixgbe_atr_input *mask);
915 void ixgbe_set_rx_mode(struct net_device *netdev);
916 #ifdef CONFIG_IXGBE_DCB
917 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
918 #endif
919 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
920 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
921 void ixgbe_do_reset(struct net_device *netdev);
922 #ifdef CONFIG_IXGBE_HWMON
923 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
924 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
925 #endif /* CONFIG_IXGBE_HWMON */
926 #ifdef IXGBE_FCOE
927 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
928 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
929 u8 *hdr_len);
930 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
931 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
932 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
933 struct scatterlist *sgl, unsigned int sgc);
934 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
935 struct scatterlist *sgl, unsigned int sgc);
936 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
937 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
938 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
939 int ixgbe_fcoe_enable(struct net_device *netdev);
940 int ixgbe_fcoe_disable(struct net_device *netdev);
941 #ifdef CONFIG_IXGBE_DCB
942 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
943 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
944 #endif /* CONFIG_IXGBE_DCB */
945 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
946 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
947 struct netdev_fcoe_hbainfo *info);
948 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
949 #endif /* IXGBE_FCOE */
950 #ifdef CONFIG_DEBUG_FS
951 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
952 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
953 void ixgbe_dbg_init(void);
954 void ixgbe_dbg_exit(void);
955 #else
956 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
957 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
958 static inline void ixgbe_dbg_init(void) {}
959 static inline void ixgbe_dbg_exit(void) {}
960 #endif /* CONFIG_DEBUG_FS */
961 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
962 {
963 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
964 }
965
966 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
967 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
968 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
969 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
970 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
971 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb);
972 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
973 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
974 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
975 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
976 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
977 #ifdef CONFIG_PCI_IOV
978 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
979 #endif
980
981 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
982 struct ixgbe_adapter *adapter,
983 struct ixgbe_ring *tx_ring);
984 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
985 void ixgbe_store_reta(struct ixgbe_adapter *adapter);
986 #endif /* _IXGBE_H_ */
Linux kernel - Deliverables
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