drivers/net/ethernet/intel/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/jiffies.h>
  39
  40 #include <linux/clocksource.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/ptp_clock_kernel.h>
  43
  44 #include "ixgbe_type.h"
  45 #include "ixgbe_common.h"
  46 #include "ixgbe_dcb.h"
  47 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  48 #define IXGBE_FCOE
  49 #include "ixgbe_fcoe.h"
  50 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  51 #ifdef CONFIG_IXGBE_DCA
  52 #include <linux/dca.h>
  53 #endif
  54
  55 /* common prefix used by pr_<> macros */
  56 #undef pr_fmt
  57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  58
  59 /* TX/RX descriptor defines */
  60 #define IXGBE_DEFAULT_TXD                   512
  61 #define IXGBE_DEFAULT_TX_WORK               256
  62 #define IXGBE_MAX_TXD                      4096
  63 #define IXGBE_MIN_TXD                        64
  64
  65 #define IXGBE_DEFAULT_RXD                   512
  66 #define IXGBE_MAX_RXD                      4096
  67 #define IXGBE_MIN_RXD                        64
  68
  69 /* flow control */
  70 #define IXGBE_MIN_FCRTL                    0x40
  71 #define IXGBE_MAX_FCRTL                 0x7FF80
  72 #define IXGBE_MIN_FCRTH                   0x600
  73 #define IXGBE_MAX_FCRTH                 0x7FFF0
  74 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  75 #define IXGBE_MIN_FCPAUSE                     0
  76 #define IXGBE_MAX_FCPAUSE                0xFFFF
  77
  78 /* Supported Rx Buffer Sizes */
  79 #define IXGBE_RXBUFFER_256    256  /* Used for skb receive header */
  80 #define IXGBE_RXBUFFER_2K    2048
  81 #define IXGBE_RXBUFFER_3K    3072
  82 #define IXGBE_RXBUFFER_4K    4096
  83 #define IXGBE_MAX_RXBUFFER  16384  /* largest size for a single descriptor */
  84
  85 /*
  86  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
  87  * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
  88  * this adds up to 448 bytes of extra data.
  89  *
  90  * Since netdev_alloc_skb now allocates a page fragment we can use a value
  91  * of 256 and the resultant skb will have a truesize of 960 or less.
  92  */
  93 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
  94
  95 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  96
  97 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  98 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  99
 100 enum ixgbe_tx_flags {
 101         /* cmd_type flags */
 102         IXGBE_TX_FLAGS_HW_VLAN  = 0x01,
 103         IXGBE_TX_FLAGS_TSO      = 0x02,
 104         IXGBE_TX_FLAGS_TSTAMP   = 0x04,
 105
 106         /* olinfo flags */
 107         IXGBE_TX_FLAGS_CC       = 0x08,
 108         IXGBE_TX_FLAGS_IPV4     = 0x10,
 109         IXGBE_TX_FLAGS_CSUM     = 0x20,
 110
 111         /* software defined flags */
 112         IXGBE_TX_FLAGS_SW_VLAN  = 0x40,
 113         IXGBE_TX_FLAGS_FCOE     = 0x80,
 114 };
 115
 116 /* VLAN info */
 117 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 118 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0xe0000000
 119 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT  29
 120 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 121
 122 #define IXGBE_MAX_VF_MC_ENTRIES         30
 123 #define IXGBE_MAX_VF_FUNCTIONS          64
 124 #define IXGBE_MAX_VFTA_ENTRIES          128
 125 #define MAX_EMULATION_MAC_ADDRS         16
 126 #define IXGBE_MAX_PF_MACVLANS           15
 127 #define VMDQ_P(p)   ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
 128 #define IXGBE_82599_VF_DEVICE_ID        0x10ED
 129 #define IXGBE_X540_VF_DEVICE_ID         0x1515
 130
 131 struct vf_data_storage {
 132         unsigned char vf_mac_addresses[ETH_ALEN];
 133         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 134         u16 num_vf_mc_hashes;
 135         u16 default_vf_vlan_id;
 136         u16 vlans_enabled;
 137         bool clear_to_send;
 138         bool pf_set_mac;
 139         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 140         u16 pf_qos;
 141         u16 tx_rate;
 142         u16 vlan_count;
 143         u8 spoofchk_enabled;
 144         unsigned int vf_api;
 145 };
 146
 147 struct vf_macvlans {
 148         struct list_head l;
 149         int vf;
 150         int rar_entry;
 151         bool free;
 152         bool is_macvlan;
 153         u8 vf_macvlan[ETH_ALEN];
 154 };
 155
 156 #define IXGBE_MAX_TXD_PWR       14
 157 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 158
 159 /* Tx Descriptors needed, worst case */
 160 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
 161 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
 162
 163 /* wrapper around a pointer to a socket buffer,
 164  * so a DMA handle can be stored along with the buffer */
 165 struct ixgbe_tx_buffer {
 166         union ixgbe_adv_tx_desc *next_to_watch;
 167         unsigned long time_stamp;
 168         struct sk_buff *skb;
 169         unsigned int bytecount;
 170         unsigned short gso_segs;
 171         __be16 protocol;
 172         DEFINE_DMA_UNMAP_ADDR(dma);
 173         DEFINE_DMA_UNMAP_LEN(len);
 174         u32 tx_flags;
 175 };
 176
 177 struct ixgbe_rx_buffer {
 178         struct sk_buff *skb;
 179         dma_addr_t dma;
 180         struct page *page;
 181         unsigned int page_offset;
 182 };
 183
 184 struct ixgbe_queue_stats {
 185         u64 packets;
 186         u64 bytes;
 187 };
 188
 189 struct ixgbe_tx_queue_stats {
 190         u64 restart_queue;
 191         u64 tx_busy;
 192         u64 tx_done_old;
 193 };
 194
 195 struct ixgbe_rx_queue_stats {
 196         u64 rsc_count;
 197         u64 rsc_flush;
 198         u64 non_eop_descs;
 199         u64 alloc_rx_page_failed;
 200         u64 alloc_rx_buff_failed;
 201         u64 csum_err;
 202 };
 203
 204 enum ixgbe_ring_state_t {
 205         __IXGBE_TX_FDIR_INIT_DONE,
 206         __IXGBE_TX_DETECT_HANG,
 207         __IXGBE_HANG_CHECK_ARMED,
 208         __IXGBE_RX_RSC_ENABLED,
 209         __IXGBE_RX_CSUM_UDP_ZERO_ERR,
 210         __IXGBE_RX_FCOE,
 211 };
 212
 213 #define check_for_tx_hang(ring) \
 214         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 215 #define set_check_for_tx_hang(ring) \
 216         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 217 #define clear_check_for_tx_hang(ring) \
 218         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 219 #define ring_is_rsc_enabled(ring) \
 220         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 221 #define set_ring_rsc_enabled(ring) \
 222         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 223 #define clear_ring_rsc_enabled(ring) \
 224         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 225 struct ixgbe_ring {
 226         struct ixgbe_ring *next;        /* pointer to next ring in q_vector */
 227         struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
 228         struct net_device *netdev;      /* netdev ring belongs to */
 229         struct device *dev;             /* device for DMA mapping */
 230         void *desc;                     /* descriptor ring memory */
 231         union {
 232                 struct ixgbe_tx_buffer *tx_buffer_info;
 233                 struct ixgbe_rx_buffer *rx_buffer_info;
 234         };
 235         unsigned long last_rx_timestamp;
 236         unsigned long state;
 237         u8 __iomem *tail;
 238         dma_addr_t dma;                 /* phys. address of descriptor ring */
 239         unsigned int size;              /* length in bytes */
 240
 241         u16 count;                      /* amount of descriptors */
 242
 243         u8 queue_index; /* needed for multiqueue queue management */
 244         u8 reg_idx;                     /* holds the special value that gets
 245                                          * the hardware register offset
 246                                          * associated with this ring, which is
 247                                          * different for DCB and RSS modes
 248                                          */
 249         u16 next_to_use;
 250         u16 next_to_clean;
 251
 252         union {
 253                 u16 next_to_alloc;
 254                 struct {
 255                         u8 atr_sample_rate;
 256                         u8 atr_count;
 257                 };
 258         };
 259
 260         u8 dcb_tc;
 261         struct ixgbe_queue_stats stats;
 262         struct u64_stats_sync syncp;
 263         union {
 264                 struct ixgbe_tx_queue_stats tx_stats;
 265                 struct ixgbe_rx_queue_stats rx_stats;
 266         };
 267 } ____cacheline_internodealigned_in_smp;
 268
 269 enum ixgbe_ring_f_enum {
 270         RING_F_NONE = 0,
 271         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 272         RING_F_RSS,
 273         RING_F_FDIR,
 274 #ifdef IXGBE_FCOE
 275         RING_F_FCOE,
 276 #endif /* IXGBE_FCOE */
 277
 278         RING_F_ARRAY_SIZE      /* must be last in enum set */
 279 };
 280
 281 #define IXGBE_MAX_RSS_INDICES  16
 282 #define IXGBE_MAX_VMDQ_INDICES 64
 283 #define IXGBE_MAX_FDIR_INDICES 64
 284 #ifdef IXGBE_FCOE
 285 #define IXGBE_MAX_FCOE_INDICES  8
 286 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 287 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 288 #else
 289 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 290 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 291 #endif /* IXGBE_FCOE */
 292 struct ixgbe_ring_feature {
 293         u16 limit;      /* upper limit on feature indices */
 294         u16 indices;    /* current value of indices */
 295         u16 mask;       /* Mask used for feature to ring mapping */
 296         u16 offset;     /* offset to start of feature */
 297 } ____cacheline_internodealigned_in_smp;
 298
 299 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
 300 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
 301 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
 302
 303 /*
 304  * FCoE requires that all Rx buffers be over 2200 bytes in length.  Since
 305  * this is twice the size of a half page we need to double the page order
 306  * for FCoE enabled Rx queues.
 307  */
 308 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
 309 {
 310 #ifdef IXGBE_FCOE
 311         if (test_bit(__IXGBE_RX_FCOE, &ring->state))
 312                 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
 313                                             IXGBE_RXBUFFER_3K;
 314 #endif
 315         return IXGBE_RXBUFFER_2K;
 316 }
 317
 318 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
 319 {
 320 #ifdef IXGBE_FCOE
 321         if (test_bit(__IXGBE_RX_FCOE, &ring->state))
 322                 return (PAGE_SIZE < 8192) ? 1 : 0;
 323 #endif
 324         return 0;
 325 }
 326 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
 327
 328 struct ixgbe_ring_container {
 329         struct ixgbe_ring *ring;        /* pointer to linked list of rings */
 330         unsigned int total_bytes;       /* total bytes processed this int */
 331         unsigned int total_packets;     /* total packets processed this int */
 332         u16 work_limit;                 /* total work allowed per interrupt */
 333         u8 count;                       /* total number of rings in vector */
 334         u8 itr;                         /* current ITR setting for ring */
 335 };
 336
 337 /* iterator for handling rings in ring container */
 338 #define ixgbe_for_each_ring(pos, head) \
 339         for (pos = (head).ring; pos != NULL; pos = pos->next)
 340
 341 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 342                               ? 8 : 1)
 343 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 344
 345 /* MAX_Q_VECTORS of these are allocated,
 346  * but we only use one per queue-specific vector.
 347  */
 348 struct ixgbe_q_vector {
 349         struct ixgbe_adapter *adapter;
 350 #ifdef CONFIG_IXGBE_DCA
 351         int cpu;            /* CPU for DCA */
 352 #endif
 353         u16 v_idx;              /* index of q_vector within array, also used for
 354                                  * finding the bit in EICR and friends that
 355                                  * represents the vector for this ring */
 356         u16 itr;                /* Interrupt throttle rate written to EITR */
 357         struct ixgbe_ring_container rx, tx;
 358
 359         struct napi_struct napi;
 360         cpumask_t affinity_mask;
 361         int numa_node;
 362         struct rcu_head rcu;    /* to avoid race with update stats on free */
 363         char name[IFNAMSIZ + 9];
 364
 365         /* for dynamic allocation of rings associated with this q_vector */
 366         struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
 367 };
 368 #ifdef CONFIG_IXGBE_HWMON
 369
 370 #define IXGBE_HWMON_TYPE_LOC            0
 371 #define IXGBE_HWMON_TYPE_TEMP           1
 372 #define IXGBE_HWMON_TYPE_CAUTION        2
 373 #define IXGBE_HWMON_TYPE_MAX            3
 374
 375 struct hwmon_attr {
 376         struct device_attribute dev_attr;
 377         struct ixgbe_hw *hw;
 378         struct ixgbe_thermal_diode_data *sensor;
 379         char name[12];
 380 };
 381
 382 struct hwmon_buff {
 383         struct device *device;
 384         struct hwmon_attr *hwmon_list;
 385         unsigned int n_hwmon;
 386 };
 387 #endif /* CONFIG_IXGBE_HWMON */
 388
 389 /*
 390  * microsecond values for various ITR rates shifted by 2 to fit itr register
 391  * with the first 3 bits reserved 0
 392  */
 393 #define IXGBE_MIN_RSC_ITR       24
 394 #define IXGBE_100K_ITR          40
 395 #define IXGBE_20K_ITR           200
 396 #define IXGBE_10K_ITR           400
 397 #define IXGBE_8K_ITR            500
 398
 399 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
 400 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
 401                                         const u32 stat_err_bits)
 402 {
 403         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 404 }
 405
 406 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
 407 {
 408         u16 ntc = ring->next_to_clean;
 409         u16 ntu = ring->next_to_use;
 410
 411         return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
 412 }
 413
 414 #define IXGBE_RX_DESC(R, i)         \
 415         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 416 #define IXGBE_TX_DESC(R, i)         \
 417         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 418 #define IXGBE_TX_CTXTDESC(R, i)     \
 419         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 420
 421 #define IXGBE_MAX_JUMBO_FRAME_SIZE      9728 /* Maximum Supported Size 9.5KB */
 422 #ifdef IXGBE_FCOE
 423 /* Use 3K as the baby jumbo frame size for FCoE */
 424 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 425 #endif /* IXGBE_FCOE */
 426
 427 #define OTHER_VECTOR 1
 428 #define NON_Q_VECTORS (OTHER_VECTOR)
 429
 430 #define MAX_MSIX_VECTORS_82599 64
 431 #define MAX_Q_VECTORS_82599 64
 432 #define MAX_MSIX_VECTORS_82598 18
 433 #define MAX_Q_VECTORS_82598 16
 434
 435 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
 436 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 437
 438 #define MIN_MSIX_Q_VECTORS 1
 439 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 440
 441 /* default to trying for four seconds */
 442 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 443
 444 /* board specific private data structure */
 445 struct ixgbe_adapter {
 446         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 447         /* OS defined structs */
 448         struct net_device *netdev;
 449         struct pci_dev *pdev;
 450
 451         unsigned long state;
 452
 453         /* Some features need tri-state capability,
 454          * thus the additional *_CAPABLE flags.
 455          */
 456         u32 flags;
 457 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 0)
 458 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 1)
 459 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 2)
 460 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 3)
 461 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 4)
 462 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 5)
 463 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 6)
 464 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 7)
 465 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 8)
 466 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 9)
 467 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 10)
 468 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 11)
 469 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 12)
 470 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 13)
 471 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 14)
 472 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 15)
 473 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 16)
 474 #define IXGBE_FLAG_NEED_LINK_CONFIG             (u32)(1 << 17)
 475 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 18)
 476 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 19)
 477 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 20)
 478 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 21)
 479 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 22)
 480 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 23)
 481
 482         u32 flags2;
 483 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1 << 0)
 484 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 485 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 486 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT           (u32)(1 << 3)
 487 #define IXGBE_FLAG2_SEARCH_FOR_SFP              (u32)(1 << 4)
 488 #define IXGBE_FLAG2_SFP_NEEDS_RESET             (u32)(1 << 5)
 489 #define IXGBE_FLAG2_RESET_REQUESTED             (u32)(1 << 6)
 490 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        (u32)(1 << 7)
 491 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP          (u32)(1 << 8)
 492 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP          (u32)(1 << 9)
 493 #define IXGBE_FLAG2_PTP_ENABLED                 (u32)(1 << 10)
 494 #define IXGBE_FLAG2_PTP_PPS_ENABLED             (u32)(1 << 11)
 495 #define IXGBE_FLAG2_BRIDGE_MODE_VEB             (u32)(1 << 12)
 496
 497         /* Tx fast path data */
 498         int num_tx_queues;
 499         u16 tx_itr_setting;
 500         u16 tx_work_limit;
 501
 502         /* Rx fast path data */
 503         int num_rx_queues;
 504         u16 rx_itr_setting;
 505
 506         /* TX */
 507         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 508
 509         u64 restart_queue;
 510         u64 lsc_int;
 511         u32 tx_timeout_count;
 512
 513         /* RX */
 514         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
 515         int num_rx_pools;               /* == num_rx_queues in 82598 */
 516         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 517         u64 hw_csum_rx_error;
 518         u64 hw_rx_no_dma_resources;
 519         u64 rsc_total_count;
 520         u64 rsc_total_flush;
 521         u64 non_eop_descs;
 522         u32 alloc_rx_page_failed;
 523         u32 alloc_rx_buff_failed;
 524
 525         struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
 526
 527         /* DCB parameters */
 528         struct ieee_pfc *ixgbe_ieee_pfc;
 529         struct ieee_ets *ixgbe_ieee_ets;
 530         struct ixgbe_dcb_config dcb_cfg;
 531         struct ixgbe_dcb_config temp_dcb_cfg;
 532         u8 dcb_set_bitmap;
 533         u8 dcbx_cap;
 534         enum ixgbe_fc_mode last_lfc_mode;
 535
 536         int num_q_vectors;      /* current number of q_vectors for device */
 537         int max_q_vectors;      /* true count of q_vectors for device */
 538         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 539         struct msix_entry *msix_entries;
 540
 541         u32 test_icr;
 542         struct ixgbe_ring test_tx_ring;
 543         struct ixgbe_ring test_rx_ring;
 544
 545         /* structs defined in ixgbe_hw.h */
 546         struct ixgbe_hw hw;
 547         u16 msg_enable;
 548         struct ixgbe_hw_stats stats;
 549
 550         u64 tx_busy;
 551         unsigned int tx_ring_count;
 552         unsigned int rx_ring_count;
 553
 554         u32 link_speed;
 555         bool link_up;
 556         unsigned long link_check_timeout;
 557
 558         struct timer_list service_timer;
 559         struct work_struct service_task;
 560
 561         struct hlist_head fdir_filter_list;
 562         unsigned long fdir_overflow; /* number of times ATR was backed off */
 563         union ixgbe_atr_input fdir_mask;
 564         int fdir_filter_count;
 565         u32 fdir_pballoc;
 566         u32 atr_sample_rate;
 567         spinlock_t fdir_perfect_lock;
 568
 569 #ifdef IXGBE_FCOE
 570         struct ixgbe_fcoe fcoe;
 571 #endif /* IXGBE_FCOE */
 572         u32 wol;
 573
 574         u16 bd_number;
 575
 576         u16 eeprom_verh;
 577         u16 eeprom_verl;
 578         u16 eeprom_cap;
 579
 580         u32 interrupt_event;
 581         u32 led_reg;
 582
 583         struct ptp_clock *ptp_clock;
 584         struct ptp_clock_info ptp_caps;
 585         unsigned long last_overflow_check;
 586         unsigned long last_rx_ptp_check;
 587         spinlock_t tmreg_lock;
 588         struct cyclecounter cc;
 589         struct timecounter tc;
 590         u32 base_incval;
 591
 592         /* SR-IOV */
 593         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 594         unsigned int num_vfs;
 595         struct vf_data_storage *vfinfo;
 596         int vf_rate_link_speed;
 597         struct vf_macvlans vf_mvs;
 598         struct vf_macvlans *mv_list;
 599
 600         u32 timer_event_accumulator;
 601         u32 vferr_refcount;
 602         struct kobject *info_kobj;
 603 #ifdef CONFIG_IXGBE_HWMON
 604         struct hwmon_buff ixgbe_hwmon_buff;
 605 #endif /* CONFIG_IXGBE_HWMON */
 606 #ifdef CONFIG_DEBUG_FS
 607         struct dentry *ixgbe_dbg_adapter;
 608 #endif /*CONFIG_DEBUG_FS*/
 609
 610         u8 default_up;
 611 };
 612
 613 struct ixgbe_fdir_filter {
 614         struct hlist_node fdir_node;
 615         union ixgbe_atr_input filter;
 616         u16 sw_idx;
 617         u16 action;
 618 };
 619
 620 enum ixgbe_state_t {
 621         __IXGBE_TESTING,
 622         __IXGBE_RESETTING,
 623         __IXGBE_DOWN,
 624         __IXGBE_SERVICE_SCHED,
 625         __IXGBE_IN_SFP_INIT,
 626 };
 627
 628 struct ixgbe_cb {
 629         union {                         /* Union defining head/tail partner */
 630                 struct sk_buff *head;
 631                 struct sk_buff *tail;
 632         };
 633         dma_addr_t dma;
 634         u16 append_cnt;
 635         bool page_released;
 636 };
 637 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
 638
 639 enum ixgbe_boards {
 640         board_82598,
 641         board_82599,
 642         board_X540,
 643 };
 644
 645 extern struct ixgbe_info ixgbe_82598_info;
 646 extern struct ixgbe_info ixgbe_82599_info;
 647 extern struct ixgbe_info ixgbe_X540_info;
 648 #ifdef CONFIG_IXGBE_DCB
 649 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 650 #endif
 651
 652 extern char ixgbe_driver_name[];
 653 extern const char ixgbe_driver_version[];
 654 #ifdef IXGBE_FCOE
 655 extern char ixgbe_default_device_descr[];
 656 #endif /* IXGBE_FCOE */
 657
 658 extern void ixgbe_up(struct ixgbe_adapter *adapter);
 659 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 660 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 661 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 662 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 663 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 664 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 665 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 666 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 667 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 668 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 669 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
 670                                    struct ixgbe_ring *);
 671 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 672 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 673 extern int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
 674                                u16 subdevice_id);
 675 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 676 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 677                                          struct ixgbe_adapter *,
 678                                          struct ixgbe_ring *);
 679 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 680                                              struct ixgbe_tx_buffer *);
 681 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 682 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 683 extern int ixgbe_poll(struct napi_struct *napi, int budget);
 684 extern int ethtool_ioctl(struct ifreq *ifr);
 685 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 686 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 687 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 688 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 689                                                  union ixgbe_atr_hash_dword input,
 690                                                  union ixgbe_atr_hash_dword common,
 691                                                  u8 queue);
 692 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 693                                            union ixgbe_atr_input *input_mask);
 694 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 695                                                  union ixgbe_atr_input *input,
 696                                                  u16 soft_id, u8 queue);
 697 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 698                                                  union ixgbe_atr_input *input,
 699                                                  u16 soft_id);
 700 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 701                                                  union ixgbe_atr_input *mask);
 702 extern bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
 703 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 704 #ifdef CONFIG_IXGBE_DCB
 705 extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
 706 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
 707 #endif
 708 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
 709 extern void ixgbe_do_reset(struct net_device *netdev);
 710 #ifdef CONFIG_IXGBE_HWMON
 711 extern void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
 712 extern int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
 713 #endif /* CONFIG_IXGBE_HWMON */
 714 #ifdef IXGBE_FCOE
 715 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 716 extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
 717                      struct ixgbe_tx_buffer *first,
 718                      u8 *hdr_len);
 719 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 720                           union ixgbe_adv_rx_desc *rx_desc,
 721                           struct sk_buff *skb);
 722 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 723                               struct scatterlist *sgl, unsigned int sgc);
 724 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
 725                                  struct scatterlist *sgl, unsigned int sgc);
 726 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 727 extern int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
 728 extern void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
 729 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 730 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 731 #ifdef CONFIG_IXGBE_DCB
 732 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 733 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 734 #endif /* CONFIG_IXGBE_DCB */
 735 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 736 extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
 737                                   struct netdev_fcoe_hbainfo *info);
 738 extern u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
 739 #endif /* IXGBE_FCOE */
 740 #ifdef CONFIG_DEBUG_FS
 741 extern void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
 742 extern void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
 743 extern void ixgbe_dbg_init(void);
 744 extern void ixgbe_dbg_exit(void);
 745 #endif /* CONFIG_DEBUG_FS */
 746 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
 747 {
 748         return netdev_get_tx_queue(ring->netdev, ring->queue_index);
 749 }
 750
 751 extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
 752 extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
 753 extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
 754 extern void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
 755 extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
 756                                   struct sk_buff *skb);
 757 extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
 758                                   union ixgbe_adv_rx_desc *rx_desc,
 759                                   struct sk_buff *skb);
 760 extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
 761                                     struct ifreq *ifr, int cmd);
 762 extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
 763 extern void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
 764 extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
 765
 766 #endif /* _IXGBE_H_ */